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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
7f84eef0 SS |
69 | #include "xhci.h" |
70 | ||
71 | /* | |
72 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
73 | * address of the TRB. | |
74 | */ | |
23e3be11 | 75 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
76 | union xhci_trb *trb) |
77 | { | |
6071d836 | 78 | unsigned long segment_offset; |
7f84eef0 | 79 | |
6071d836 | 80 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 81 | return 0; |
6071d836 SS |
82 | /* offset in TRBs */ |
83 | segment_offset = trb - seg->trbs; | |
84 | if (segment_offset > TRBS_PER_SEGMENT) | |
7f84eef0 | 85 | return 0; |
6071d836 | 86 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
87 | } |
88 | ||
89 | /* Does this link TRB point to the first segment in a ring, | |
90 | * or was the previous TRB the last TRB on the last segment in the ERST? | |
91 | */ | |
92 | static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
93 | struct xhci_segment *seg, union xhci_trb *trb) | |
94 | { | |
95 | if (ring == xhci->event_ring) | |
96 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && | |
97 | (seg->next == xhci->event_ring->first_seg); | |
98 | else | |
99 | return trb->link.control & LINK_TOGGLE; | |
100 | } | |
101 | ||
102 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring | |
103 | * segment? I.e. would the updated event TRB pointer step off the end of the | |
104 | * event seg? | |
105 | */ | |
106 | static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
107 | struct xhci_segment *seg, union xhci_trb *trb) | |
108 | { | |
109 | if (ring == xhci->event_ring) | |
110 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; | |
111 | else | |
112 | return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK); | |
113 | } | |
114 | ||
6c12db90 JY |
115 | static inline int enqueue_is_link_trb(struct xhci_ring *ring) |
116 | { | |
117 | struct xhci_link_trb *link = &ring->enqueue->link; | |
118 | return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)); | |
119 | } | |
120 | ||
ae636747 SS |
121 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
122 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
123 | * effect the ring dequeue or enqueue pointers. | |
124 | */ | |
125 | static void next_trb(struct xhci_hcd *xhci, | |
126 | struct xhci_ring *ring, | |
127 | struct xhci_segment **seg, | |
128 | union xhci_trb **trb) | |
129 | { | |
130 | if (last_trb(xhci, ring, *seg, *trb)) { | |
131 | *seg = (*seg)->next; | |
132 | *trb = ((*seg)->trbs); | |
133 | } else { | |
134 | *trb = (*trb)++; | |
135 | } | |
136 | } | |
137 | ||
7f84eef0 SS |
138 | /* |
139 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
140 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
141 | */ | |
142 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer) | |
143 | { | |
144 | union xhci_trb *next = ++(ring->dequeue); | |
66e49d87 | 145 | unsigned long long addr; |
7f84eef0 SS |
146 | |
147 | ring->deq_updates++; | |
148 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
149 | * the end of an event ring segment (which doesn't have link TRBS) | |
150 | */ | |
151 | while (last_trb(xhci, ring, ring->deq_seg, next)) { | |
152 | if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) { | |
153 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
154 | if (!in_interrupt()) | |
700e2052 GKH |
155 | xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", |
156 | ring, | |
7f84eef0 SS |
157 | (unsigned int) ring->cycle_state); |
158 | } | |
159 | ring->deq_seg = ring->deq_seg->next; | |
160 | ring->dequeue = ring->deq_seg->trbs; | |
161 | next = ring->dequeue; | |
162 | } | |
66e49d87 SS |
163 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); |
164 | if (ring == xhci->event_ring) | |
165 | xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr); | |
166 | else if (ring == xhci->cmd_ring) | |
167 | xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr); | |
168 | else | |
169 | xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr); | |
7f84eef0 SS |
170 | } |
171 | ||
172 | /* | |
173 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
174 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
175 | * | |
176 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
177 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
178 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
179 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
180 | * | |
181 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
182 | * set, but other sections talk about dealing with the chain bit set. This was |
183 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
184 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
185 | * |
186 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
187 | * prepare_transfer()? | |
7f84eef0 | 188 | */ |
6cc30d85 SS |
189 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
190 | bool consumer, bool more_trbs_coming) | |
7f84eef0 SS |
191 | { |
192 | u32 chain; | |
193 | union xhci_trb *next; | |
66e49d87 | 194 | unsigned long long addr; |
7f84eef0 SS |
195 | |
196 | chain = ring->enqueue->generic.field[3] & TRB_CHAIN; | |
197 | next = ++(ring->enqueue); | |
198 | ||
199 | ring->enq_updates++; | |
200 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
201 | * the end of an event ring segment (which doesn't have link TRBS) | |
202 | */ | |
203 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
204 | if (!consumer) { | |
205 | if (ring != xhci->event_ring) { | |
6cc30d85 SS |
206 | /* |
207 | * If the caller doesn't plan on enqueueing more | |
208 | * TDs before ringing the doorbell, then we | |
209 | * don't want to give the link TRB to the | |
210 | * hardware just yet. We'll give the link TRB | |
211 | * back in prepare_ring() just before we enqueue | |
212 | * the TD at the top of the ring. | |
213 | */ | |
214 | if (!chain && !more_trbs_coming) | |
6c12db90 | 215 | break; |
6cc30d85 SS |
216 | |
217 | /* If we're not dealing with 0.95 hardware, | |
218 | * carry over the chain bit of the previous TRB | |
219 | * (which may mean the chain bit is cleared). | |
220 | */ | |
221 | if (!xhci_link_trb_quirk(xhci)) { | |
222 | next->link.control &= ~TRB_CHAIN; | |
223 | next->link.control |= chain; | |
b0567b3f | 224 | } |
6cc30d85 SS |
225 | /* Give this link TRB to the hardware */ |
226 | wmb(); | |
227 | next->link.control ^= TRB_CYCLE; | |
7f84eef0 SS |
228 | } |
229 | /* Toggle the cycle bit after the last ring segment. */ | |
230 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
231 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
232 | if (!in_interrupt()) | |
700e2052 GKH |
233 | xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n", |
234 | ring, | |
7f84eef0 SS |
235 | (unsigned int) ring->cycle_state); |
236 | } | |
237 | } | |
238 | ring->enq_seg = ring->enq_seg->next; | |
239 | ring->enqueue = ring->enq_seg->trbs; | |
240 | next = ring->enqueue; | |
241 | } | |
66e49d87 SS |
242 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); |
243 | if (ring == xhci->event_ring) | |
244 | xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr); | |
245 | else if (ring == xhci->cmd_ring) | |
246 | xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr); | |
247 | else | |
248 | xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr); | |
7f84eef0 SS |
249 | } |
250 | ||
251 | /* | |
252 | * Check to see if there's room to enqueue num_trbs on the ring. See rules | |
253 | * above. | |
254 | * FIXME: this would be simpler and faster if we just kept track of the number | |
255 | * of free TRBs in a ring. | |
256 | */ | |
257 | static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
258 | unsigned int num_trbs) | |
259 | { | |
260 | int i; | |
261 | union xhci_trb *enq = ring->enqueue; | |
262 | struct xhci_segment *enq_seg = ring->enq_seg; | |
44ebd037 SS |
263 | struct xhci_segment *cur_seg; |
264 | unsigned int left_on_ring; | |
7f84eef0 | 265 | |
6c12db90 JY |
266 | /* If we are currently pointing to a link TRB, advance the |
267 | * enqueue pointer before checking for space */ | |
268 | while (last_trb(xhci, ring, enq_seg, enq)) { | |
269 | enq_seg = enq_seg->next; | |
270 | enq = enq_seg->trbs; | |
271 | } | |
272 | ||
7f84eef0 | 273 | /* Check if ring is empty */ |
44ebd037 SS |
274 | if (enq == ring->dequeue) { |
275 | /* Can't use link trbs */ | |
276 | left_on_ring = TRBS_PER_SEGMENT - 1; | |
277 | for (cur_seg = enq_seg->next; cur_seg != enq_seg; | |
278 | cur_seg = cur_seg->next) | |
279 | left_on_ring += TRBS_PER_SEGMENT - 1; | |
280 | ||
281 | /* Always need one TRB free in the ring. */ | |
282 | left_on_ring -= 1; | |
283 | if (num_trbs > left_on_ring) { | |
284 | xhci_warn(xhci, "Not enough room on ring; " | |
285 | "need %u TRBs, %u TRBs left\n", | |
286 | num_trbs, left_on_ring); | |
287 | return 0; | |
288 | } | |
7f84eef0 | 289 | return 1; |
44ebd037 | 290 | } |
7f84eef0 SS |
291 | /* Make sure there's an extra empty TRB available */ |
292 | for (i = 0; i <= num_trbs; ++i) { | |
293 | if (enq == ring->dequeue) | |
294 | return 0; | |
295 | enq++; | |
296 | while (last_trb(xhci, ring, enq_seg, enq)) { | |
297 | enq_seg = enq_seg->next; | |
298 | enq = enq_seg->trbs; | |
299 | } | |
300 | } | |
301 | return 1; | |
302 | } | |
303 | ||
23e3be11 | 304 | void xhci_set_hc_event_deq(struct xhci_hcd *xhci) |
7f84eef0 | 305 | { |
8e595a5d | 306 | u64 temp; |
7f84eef0 SS |
307 | dma_addr_t deq; |
308 | ||
23e3be11 | 309 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, |
7f84eef0 SS |
310 | xhci->event_ring->dequeue); |
311 | if (deq == 0 && !in_interrupt()) | |
312 | xhci_warn(xhci, "WARN something wrong with SW event ring " | |
313 | "dequeue ptr.\n"); | |
314 | /* Update HC event ring dequeue pointer */ | |
8e595a5d | 315 | temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
7f84eef0 | 316 | temp &= ERST_PTR_MASK; |
2d83109b SS |
317 | /* Don't clear the EHB bit (which is RW1C) because |
318 | * there might be more events to service. | |
319 | */ | |
320 | temp &= ~ERST_EHB; | |
66e49d87 | 321 | xhci_dbg(xhci, "// Write event ring dequeue pointer, preserving EHB bit\n"); |
8e595a5d SS |
322 | xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp, |
323 | &xhci->ir_set->erst_dequeue); | |
7f84eef0 SS |
324 | } |
325 | ||
326 | /* Ring the host controller doorbell after placing a command on the ring */ | |
23e3be11 | 327 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 SS |
328 | { |
329 | u32 temp; | |
330 | ||
331 | xhci_dbg(xhci, "// Ding dong!\n"); | |
332 | temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK; | |
333 | xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]); | |
334 | /* Flush PCI posted writes */ | |
335 | xhci_readl(xhci, &xhci->dba->doorbell[0]); | |
336 | } | |
337 | ||
ae636747 SS |
338 | static void ring_ep_doorbell(struct xhci_hcd *xhci, |
339 | unsigned int slot_id, | |
e9df17eb SS |
340 | unsigned int ep_index, |
341 | unsigned int stream_id) | |
ae636747 | 342 | { |
63a0d9ab SS |
343 | struct xhci_virt_ep *ep; |
344 | unsigned int ep_state; | |
ae636747 SS |
345 | u32 field; |
346 | __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; | |
347 | ||
63a0d9ab SS |
348 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
349 | ep_state = ep->ep_state; | |
ae636747 SS |
350 | /* Don't ring the doorbell for this endpoint if there are pending |
351 | * cancellations because the we don't want to interrupt processing. | |
8df75f42 SS |
352 | * We don't want to restart any stream rings if there's a set dequeue |
353 | * pointer command pending because the device can choose to start any | |
354 | * stream once the endpoint is on the HW schedule. | |
355 | * FIXME - check all the stream rings for pending cancellations. | |
ae636747 | 356 | */ |
678539cf | 357 | if (!(ep_state & EP_HALT_PENDING) && !(ep_state & SET_DEQ_PENDING) |
63a0d9ab | 358 | && !(ep_state & EP_HALTED)) { |
ae636747 | 359 | field = xhci_readl(xhci, db_addr) & DB_MASK; |
e9df17eb SS |
360 | field |= EPI_TO_DB(ep_index) | STREAM_ID_TO_DB(stream_id); |
361 | xhci_writel(xhci, field, db_addr); | |
ae636747 SS |
362 | /* Flush PCI posted writes - FIXME Matthew Wilcox says this |
363 | * isn't time-critical and we shouldn't make the CPU wait for | |
364 | * the flush. | |
365 | */ | |
366 | xhci_readl(xhci, db_addr); | |
367 | } | |
368 | } | |
369 | ||
e9df17eb SS |
370 | /* Ring the doorbell for any rings with pending URBs */ |
371 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
372 | unsigned int slot_id, | |
373 | unsigned int ep_index) | |
374 | { | |
375 | unsigned int stream_id; | |
376 | struct xhci_virt_ep *ep; | |
377 | ||
378 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
379 | ||
380 | /* A ring has pending URBs if its TD list is not empty */ | |
381 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
382 | if (!(list_empty(&ep->ring->td_list))) | |
383 | ring_ep_doorbell(xhci, slot_id, ep_index, 0); | |
384 | return; | |
385 | } | |
386 | ||
387 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
388 | stream_id++) { | |
389 | struct xhci_stream_info *stream_info = ep->stream_info; | |
390 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
391 | ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); | |
392 | } | |
393 | } | |
394 | ||
ae636747 SS |
395 | /* |
396 | * Find the segment that trb is in. Start searching in start_seg. | |
397 | * If we must move past a segment that has a link TRB with a toggle cycle state | |
398 | * bit set, then we will toggle the value pointed at by cycle_state. | |
399 | */ | |
400 | static struct xhci_segment *find_trb_seg( | |
401 | struct xhci_segment *start_seg, | |
402 | union xhci_trb *trb, int *cycle_state) | |
403 | { | |
404 | struct xhci_segment *cur_seg = start_seg; | |
405 | struct xhci_generic_trb *generic_trb; | |
406 | ||
407 | while (cur_seg->trbs > trb || | |
408 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { | |
409 | generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; | |
54b5acf3 AX |
410 | if ((generic_trb->field[3] & TRB_TYPE_BITMASK) == |
411 | TRB_TYPE(TRB_LINK) && | |
ae636747 SS |
412 | (generic_trb->field[3] & LINK_TOGGLE)) |
413 | *cycle_state = ~(*cycle_state) & 0x1; | |
414 | cur_seg = cur_seg->next; | |
415 | if (cur_seg == start_seg) | |
416 | /* Looped over the entire list. Oops! */ | |
326b4810 | 417 | return NULL; |
ae636747 SS |
418 | } |
419 | return cur_seg; | |
420 | } | |
421 | ||
ae636747 SS |
422 | /* |
423 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
424 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
425 | * dequeue pointer, and new consumer cycle state in state. | |
426 | * Update our internal representation of the ring's dequeue pointer. | |
427 | * | |
428 | * We do this in three jumps: | |
429 | * - First we update our new ring state to be the same as when the xHC stopped. | |
430 | * - Then we traverse the ring to find the segment that contains | |
431 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
432 | * any link TRBs with the toggle cycle bit set. | |
433 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
434 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
435 | */ | |
c92bcfa7 | 436 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 437 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
438 | unsigned int stream_id, struct xhci_td *cur_td, |
439 | struct xhci_dequeue_state *state) | |
ae636747 SS |
440 | { |
441 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
e9df17eb | 442 | struct xhci_ring *ep_ring; |
ae636747 | 443 | struct xhci_generic_trb *trb; |
d115b048 | 444 | struct xhci_ep_ctx *ep_ctx; |
c92bcfa7 | 445 | dma_addr_t addr; |
ae636747 | 446 | |
e9df17eb SS |
447 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
448 | ep_index, stream_id); | |
449 | if (!ep_ring) { | |
450 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
451 | "for invalid stream ID %u.\n", | |
452 | stream_id); | |
453 | return; | |
454 | } | |
ae636747 | 455 | state->new_cycle_state = 0; |
c92bcfa7 | 456 | xhci_dbg(xhci, "Finding segment containing stopped TRB.\n"); |
ae636747 | 457 | state->new_deq_seg = find_trb_seg(cur_td->start_seg, |
63a0d9ab | 458 | dev->eps[ep_index].stopped_trb, |
ae636747 SS |
459 | &state->new_cycle_state); |
460 | if (!state->new_deq_seg) | |
461 | BUG(); | |
462 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ | |
c92bcfa7 | 463 | xhci_dbg(xhci, "Finding endpoint context\n"); |
d115b048 JY |
464 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
465 | state->new_cycle_state = 0x1 & ep_ctx->deq; | |
ae636747 SS |
466 | |
467 | state->new_deq_ptr = cur_td->last_trb; | |
c92bcfa7 | 468 | xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n"); |
ae636747 SS |
469 | state->new_deq_seg = find_trb_seg(state->new_deq_seg, |
470 | state->new_deq_ptr, | |
471 | &state->new_cycle_state); | |
472 | if (!state->new_deq_seg) | |
473 | BUG(); | |
474 | ||
475 | trb = &state->new_deq_ptr->generic; | |
54b5acf3 | 476 | if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) && |
ae636747 SS |
477 | (trb->field[3] & LINK_TOGGLE)) |
478 | state->new_cycle_state = ~(state->new_cycle_state) & 0x1; | |
479 | next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); | |
480 | ||
481 | /* Don't update the ring cycle state for the producer (us). */ | |
c92bcfa7 SS |
482 | xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", |
483 | state->new_deq_seg); | |
484 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
485 | xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", | |
486 | (unsigned long long) addr); | |
487 | xhci_dbg(xhci, "Setting dequeue pointer in internal ring state.\n"); | |
ae636747 SS |
488 | ep_ring->dequeue = state->new_deq_ptr; |
489 | ep_ring->deq_seg = state->new_deq_seg; | |
490 | } | |
491 | ||
23e3be11 | 492 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
ae636747 SS |
493 | struct xhci_td *cur_td) |
494 | { | |
495 | struct xhci_segment *cur_seg; | |
496 | union xhci_trb *cur_trb; | |
497 | ||
498 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; | |
499 | true; | |
500 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
501 | if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) == | |
502 | TRB_TYPE(TRB_LINK)) { | |
503 | /* Unchain any chained Link TRBs, but | |
504 | * leave the pointers intact. | |
505 | */ | |
506 | cur_trb->generic.field[3] &= ~TRB_CHAIN; | |
507 | xhci_dbg(xhci, "Cancel (unchain) link TRB\n"); | |
700e2052 GKH |
508 | xhci_dbg(xhci, "Address = %p (0x%llx dma); " |
509 | "in seg %p (0x%llx dma)\n", | |
510 | cur_trb, | |
23e3be11 | 511 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
512 | cur_seg, |
513 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
514 | } else { |
515 | cur_trb->generic.field[0] = 0; | |
516 | cur_trb->generic.field[1] = 0; | |
517 | cur_trb->generic.field[2] = 0; | |
518 | /* Preserve only the cycle bit of this TRB */ | |
519 | cur_trb->generic.field[3] &= TRB_CYCLE; | |
520 | cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP); | |
700e2052 GKH |
521 | xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) " |
522 | "in seg %p (0x%llx dma)\n", | |
523 | cur_trb, | |
23e3be11 | 524 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
525 | cur_seg, |
526 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
527 | } |
528 | if (cur_trb == cur_td->last_trb) | |
529 | break; | |
530 | } | |
531 | } | |
532 | ||
533 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
e9df17eb SS |
534 | unsigned int ep_index, unsigned int stream_id, |
535 | struct xhci_segment *deq_seg, | |
ae636747 SS |
536 | union xhci_trb *deq_ptr, u32 cycle_state); |
537 | ||
c92bcfa7 | 538 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
63a0d9ab | 539 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb | 540 | unsigned int stream_id, |
63a0d9ab | 541 | struct xhci_dequeue_state *deq_state) |
c92bcfa7 | 542 | { |
63a0d9ab SS |
543 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
544 | ||
c92bcfa7 SS |
545 | xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), " |
546 | "new deq ptr = %p (0x%llx dma), new cycle = %u\n", | |
547 | deq_state->new_deq_seg, | |
548 | (unsigned long long)deq_state->new_deq_seg->dma, | |
549 | deq_state->new_deq_ptr, | |
550 | (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
551 | deq_state->new_cycle_state); | |
e9df17eb | 552 | queue_set_tr_deq(xhci, slot_id, ep_index, stream_id, |
c92bcfa7 SS |
553 | deq_state->new_deq_seg, |
554 | deq_state->new_deq_ptr, | |
555 | (u32) deq_state->new_cycle_state); | |
556 | /* Stop the TD queueing code from ringing the doorbell until | |
557 | * this command completes. The HC won't set the dequeue pointer | |
558 | * if the ring is running, and ringing the doorbell starts the | |
559 | * ring running. | |
560 | */ | |
63a0d9ab | 561 | ep->ep_state |= SET_DEQ_PENDING; |
c92bcfa7 SS |
562 | } |
563 | ||
6f5165cf SS |
564 | static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
565 | struct xhci_virt_ep *ep) | |
566 | { | |
567 | ep->ep_state &= ~EP_HALT_PENDING; | |
568 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the | |
569 | * timer is running on another CPU, we don't decrement stop_cmds_pending | |
570 | * (since we didn't successfully stop the watchdog timer). | |
571 | */ | |
572 | if (del_timer(&ep->stop_cmd_timer)) | |
573 | ep->stop_cmds_pending--; | |
574 | } | |
575 | ||
576 | /* Must be called with xhci->lock held in interrupt context */ | |
577 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | |
578 | struct xhci_td *cur_td, int status, char *adjective) | |
579 | { | |
580 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | |
581 | ||
582 | cur_td->urb->hcpriv = NULL; | |
583 | usb_hcd_unlink_urb_from_ep(hcd, cur_td->urb); | |
584 | xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, cur_td->urb); | |
585 | ||
586 | spin_unlock(&xhci->lock); | |
587 | usb_hcd_giveback_urb(hcd, cur_td->urb, status); | |
588 | kfree(cur_td); | |
589 | spin_lock(&xhci->lock); | |
590 | xhci_dbg(xhci, "%s URB given back\n", adjective); | |
591 | } | |
592 | ||
ae636747 SS |
593 | /* |
594 | * When we get a command completion for a Stop Endpoint Command, we need to | |
595 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
596 | * | |
597 | * 1. If the HW was in the middle of processing the TD that needs to be | |
598 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
599 | * in the TD with a Set Dequeue Pointer Command. | |
600 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
601 | * bit cleared) so that the HW will skip over them. | |
602 | */ | |
603 | static void handle_stopped_endpoint(struct xhci_hcd *xhci, | |
604 | union xhci_trb *trb) | |
605 | { | |
606 | unsigned int slot_id; | |
607 | unsigned int ep_index; | |
608 | struct xhci_ring *ep_ring; | |
63a0d9ab | 609 | struct xhci_virt_ep *ep; |
ae636747 | 610 | struct list_head *entry; |
326b4810 | 611 | struct xhci_td *cur_td = NULL; |
ae636747 SS |
612 | struct xhci_td *last_unlinked_td; |
613 | ||
c92bcfa7 | 614 | struct xhci_dequeue_state deq_state; |
ae636747 SS |
615 | |
616 | memset(&deq_state, 0, sizeof(deq_state)); | |
617 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | |
618 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | |
63a0d9ab | 619 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
ae636747 | 620 | |
678539cf | 621 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 622 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
e9df17eb | 623 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 624 | return; |
678539cf | 625 | } |
ae636747 SS |
626 | |
627 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
628 | * We have the xHCI lock, so nothing can modify this list until we drop | |
629 | * it. We're also in the event handler, so we can't get re-interrupted | |
630 | * if another Stop Endpoint command completes | |
631 | */ | |
63a0d9ab | 632 | list_for_each(entry, &ep->cancelled_td_list) { |
ae636747 | 633 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
700e2052 GKH |
634 | xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n", |
635 | cur_td->first_trb, | |
23e3be11 | 636 | (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb)); |
e9df17eb SS |
637 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
638 | if (!ep_ring) { | |
639 | /* This shouldn't happen unless a driver is mucking | |
640 | * with the stream ID after submission. This will | |
641 | * leave the TD on the hardware ring, and the hardware | |
642 | * will try to execute it, and may access a buffer | |
643 | * that has already been freed. In the best case, the | |
644 | * hardware will execute it, and the event handler will | |
645 | * ignore the completion event for that TD, since it was | |
646 | * removed from the td_list for that endpoint. In | |
647 | * short, don't muck with the stream ID after | |
648 | * submission. | |
649 | */ | |
650 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
651 | "has invalid stream ID %u.\n", | |
652 | cur_td->urb, | |
653 | cur_td->urb->stream_id); | |
654 | goto remove_finished_td; | |
655 | } | |
ae636747 SS |
656 | /* |
657 | * If we stopped on the TD we need to cancel, then we have to | |
658 | * move the xHC endpoint ring dequeue pointer past this TD. | |
659 | */ | |
63a0d9ab | 660 | if (cur_td == ep->stopped_td) |
e9df17eb SS |
661 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
662 | cur_td->urb->stream_id, | |
663 | cur_td, &deq_state); | |
ae636747 SS |
664 | else |
665 | td_to_noop(xhci, ep_ring, cur_td); | |
e9df17eb | 666 | remove_finished_td: |
ae636747 SS |
667 | /* |
668 | * The event handler won't see a completion for this TD anymore, | |
669 | * so remove it from the endpoint ring's TD list. Keep it in | |
670 | * the cancelled TD list for URB completion later. | |
671 | */ | |
672 | list_del(&cur_td->td_list); | |
ae636747 SS |
673 | } |
674 | last_unlinked_td = cur_td; | |
6f5165cf | 675 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
676 | |
677 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
678 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
63a0d9ab | 679 | xhci_queue_new_dequeue_state(xhci, |
e9df17eb SS |
680 | slot_id, ep_index, |
681 | ep->stopped_td->urb->stream_id, | |
682 | &deq_state); | |
ac9d8fe7 | 683 | xhci_ring_cmd_db(xhci); |
ae636747 | 684 | } else { |
e9df17eb SS |
685 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
686 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 687 | } |
1624ae1c SS |
688 | ep->stopped_td = NULL; |
689 | ep->stopped_trb = NULL; | |
ae636747 SS |
690 | |
691 | /* | |
692 | * Drop the lock and complete the URBs in the cancelled TD list. | |
693 | * New TDs to be cancelled might be added to the end of the list before | |
694 | * we can complete all the URBs for the TDs we already unlinked. | |
695 | * So stop when we've completed the URB for the last TD we unlinked. | |
696 | */ | |
697 | do { | |
63a0d9ab | 698 | cur_td = list_entry(ep->cancelled_td_list.next, |
ae636747 SS |
699 | struct xhci_td, cancelled_td_list); |
700 | list_del(&cur_td->cancelled_td_list); | |
701 | ||
702 | /* Clean up the cancelled URB */ | |
ae636747 SS |
703 | /* Doesn't matter what we pass for status, since the core will |
704 | * just overwrite it (because the URB has been unlinked). | |
705 | */ | |
6f5165cf | 706 | xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled"); |
ae636747 | 707 | |
6f5165cf SS |
708 | /* Stop processing the cancelled list if the watchdog timer is |
709 | * running. | |
710 | */ | |
711 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
712 | return; | |
ae636747 SS |
713 | } while (cur_td != last_unlinked_td); |
714 | ||
715 | /* Return to the event handler with xhci->lock re-acquired */ | |
716 | } | |
717 | ||
6f5165cf SS |
718 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
719 | * In this case, we assume the host controller is broken or dying or dead. The | |
720 | * host may still be completing some other events, so we have to be careful to | |
721 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
722 | * through xhci->state. | |
723 | * | |
724 | * The timer may also fire if the host takes a very long time to respond to the | |
725 | * command, and the stop endpoint command completion handler cannot delete the | |
726 | * timer before the timer function is called. Another endpoint cancellation may | |
727 | * sneak in before the timer function can grab the lock, and that may queue | |
728 | * another stop endpoint command and add the timer back. So we cannot use a | |
729 | * simple flag to say whether there is a pending stop endpoint command for a | |
730 | * particular endpoint. | |
731 | * | |
732 | * Instead we use a combination of that flag and a counter for the number of | |
733 | * pending stop endpoint commands. If the timer is the tail end of the last | |
734 | * stop endpoint command, and the endpoint's command is still pending, we assume | |
735 | * the host is dying. | |
736 | */ | |
737 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
738 | { | |
739 | struct xhci_hcd *xhci; | |
740 | struct xhci_virt_ep *ep; | |
741 | struct xhci_virt_ep *temp_ep; | |
742 | struct xhci_ring *ring; | |
743 | struct xhci_td *cur_td; | |
744 | int ret, i, j; | |
745 | ||
746 | ep = (struct xhci_virt_ep *) arg; | |
747 | xhci = ep->xhci; | |
748 | ||
749 | spin_lock(&xhci->lock); | |
750 | ||
751 | ep->stop_cmds_pending--; | |
752 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
753 | xhci_dbg(xhci, "Stop EP timer ran, but another timer marked " | |
754 | "xHCI as DYING, exiting.\n"); | |
755 | spin_unlock(&xhci->lock); | |
756 | return; | |
757 | } | |
758 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { | |
759 | xhci_dbg(xhci, "Stop EP timer ran, but no command pending, " | |
760 | "exiting.\n"); | |
761 | spin_unlock(&xhci->lock); | |
762 | return; | |
763 | } | |
764 | ||
765 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
766 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
767 | /* Oops, HC is dead or dying or at least not responding to the stop | |
768 | * endpoint command. | |
769 | */ | |
770 | xhci->xhc_state |= XHCI_STATE_DYING; | |
771 | /* Disable interrupts from the host controller and start halting it */ | |
772 | xhci_quiesce(xhci); | |
773 | spin_unlock(&xhci->lock); | |
774 | ||
775 | ret = xhci_halt(xhci); | |
776 | ||
777 | spin_lock(&xhci->lock); | |
778 | if (ret < 0) { | |
779 | /* This is bad; the host is not responding to commands and it's | |
780 | * not allowing itself to be halted. At least interrupts are | |
781 | * disabled, so we can set HC_STATE_HALT and notify the | |
782 | * USB core. But if we call usb_hc_died(), it will attempt to | |
783 | * disconnect all device drivers under this host. Those | |
784 | * disconnect() methods will wait for all URBs to be unlinked, | |
785 | * so we must complete them. | |
786 | */ | |
787 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
788 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
789 | /* We could turn all TDs on the rings to no-ops. This won't | |
790 | * help if the host has cached part of the ring, and is slow if | |
791 | * we want to preserve the cycle bit. Skip it and hope the host | |
792 | * doesn't touch the memory. | |
793 | */ | |
794 | } | |
795 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
796 | if (!xhci->devs[i]) | |
797 | continue; | |
798 | for (j = 0; j < 31; j++) { | |
799 | temp_ep = &xhci->devs[i]->eps[j]; | |
800 | ring = temp_ep->ring; | |
801 | if (!ring) | |
802 | continue; | |
803 | xhci_dbg(xhci, "Killing URBs for slot ID %u, " | |
804 | "ep index %u\n", i, j); | |
805 | while (!list_empty(&ring->td_list)) { | |
806 | cur_td = list_first_entry(&ring->td_list, | |
807 | struct xhci_td, | |
808 | td_list); | |
809 | list_del(&cur_td->td_list); | |
810 | if (!list_empty(&cur_td->cancelled_td_list)) | |
811 | list_del(&cur_td->cancelled_td_list); | |
812 | xhci_giveback_urb_in_irq(xhci, cur_td, | |
813 | -ESHUTDOWN, "killed"); | |
814 | } | |
815 | while (!list_empty(&temp_ep->cancelled_td_list)) { | |
816 | cur_td = list_first_entry( | |
817 | &temp_ep->cancelled_td_list, | |
818 | struct xhci_td, | |
819 | cancelled_td_list); | |
820 | list_del(&cur_td->cancelled_td_list); | |
821 | xhci_giveback_urb_in_irq(xhci, cur_td, | |
822 | -ESHUTDOWN, "killed"); | |
823 | } | |
824 | } | |
825 | } | |
826 | spin_unlock(&xhci->lock); | |
827 | xhci_to_hcd(xhci)->state = HC_STATE_HALT; | |
828 | xhci_dbg(xhci, "Calling usb_hc_died()\n"); | |
829 | usb_hc_died(xhci_to_hcd(xhci)); | |
830 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); | |
831 | } | |
832 | ||
ae636747 SS |
833 | /* |
834 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
835 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
836 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
837 | * endpoint doorbell to restart the ring, but only if there aren't more | |
838 | * cancellations pending. | |
839 | */ | |
840 | static void handle_set_deq_completion(struct xhci_hcd *xhci, | |
841 | struct xhci_event_cmd *event, | |
842 | union xhci_trb *trb) | |
843 | { | |
844 | unsigned int slot_id; | |
845 | unsigned int ep_index; | |
e9df17eb | 846 | unsigned int stream_id; |
ae636747 SS |
847 | struct xhci_ring *ep_ring; |
848 | struct xhci_virt_device *dev; | |
d115b048 JY |
849 | struct xhci_ep_ctx *ep_ctx; |
850 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 SS |
851 | |
852 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | |
853 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | |
e9df17eb | 854 | stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]); |
ae636747 | 855 | dev = xhci->devs[slot_id]; |
e9df17eb SS |
856 | |
857 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
858 | if (!ep_ring) { | |
859 | xhci_warn(xhci, "WARN Set TR deq ptr command for " | |
860 | "freed stream ID %u\n", | |
861 | stream_id); | |
862 | /* XXX: Harmless??? */ | |
863 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; | |
864 | return; | |
865 | } | |
866 | ||
d115b048 JY |
867 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
868 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
ae636747 SS |
869 | |
870 | if (GET_COMP_CODE(event->status) != COMP_SUCCESS) { | |
871 | unsigned int ep_state; | |
872 | unsigned int slot_state; | |
873 | ||
874 | switch (GET_COMP_CODE(event->status)) { | |
875 | case COMP_TRB_ERR: | |
876 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because " | |
877 | "of stream ID configuration\n"); | |
878 | break; | |
879 | case COMP_CTX_STATE: | |
880 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due " | |
881 | "to incorrect slot or ep state.\n"); | |
d115b048 | 882 | ep_state = ep_ctx->ep_info; |
ae636747 | 883 | ep_state &= EP_STATE_MASK; |
d115b048 | 884 | slot_state = slot_ctx->dev_state; |
ae636747 SS |
885 | slot_state = GET_SLOT_STATE(slot_state); |
886 | xhci_dbg(xhci, "Slot state = %u, EP state = %u\n", | |
887 | slot_state, ep_state); | |
888 | break; | |
889 | case COMP_EBADSLT: | |
890 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because " | |
891 | "slot %u was not enabled.\n", slot_id); | |
892 | break; | |
893 | default: | |
894 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown " | |
895 | "completion code of %u.\n", | |
896 | GET_COMP_CODE(event->status)); | |
897 | break; | |
898 | } | |
899 | /* OK what do we do now? The endpoint state is hosed, and we | |
900 | * should never get to this point if the synchronization between | |
901 | * queueing, and endpoint state are correct. This might happen | |
902 | * if the device gets disconnected after we've finished | |
903 | * cancelling URBs, which might not be an error... | |
904 | */ | |
905 | } else { | |
8e595a5d | 906 | xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", |
d115b048 | 907 | ep_ctx->deq); |
ae636747 SS |
908 | } |
909 | ||
63a0d9ab | 910 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
e9df17eb SS |
911 | /* Restart any rings with pending URBs */ |
912 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
913 | } |
914 | ||
a1587d97 SS |
915 | static void handle_reset_ep_completion(struct xhci_hcd *xhci, |
916 | struct xhci_event_cmd *event, | |
917 | union xhci_trb *trb) | |
918 | { | |
919 | int slot_id; | |
920 | unsigned int ep_index; | |
921 | ||
922 | slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]); | |
923 | ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]); | |
924 | /* This command will only fail if the endpoint wasn't halted, | |
925 | * but we don't care. | |
926 | */ | |
927 | xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n", | |
928 | (unsigned int) GET_COMP_CODE(event->status)); | |
929 | ||
ac9d8fe7 SS |
930 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
931 | * command complete before the endpoint can be used. Queue that here | |
932 | * because the HW can't handle two commands being queued in a row. | |
933 | */ | |
934 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
935 | xhci_dbg(xhci, "Queueing configure endpoint command\n"); | |
936 | xhci_queue_configure_endpoint(xhci, | |
913a8a34 SS |
937 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
938 | false); | |
ac9d8fe7 SS |
939 | xhci_ring_cmd_db(xhci); |
940 | } else { | |
e9df17eb | 941 | /* Clear our internal halted state and restart the ring(s) */ |
63a0d9ab | 942 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
e9df17eb | 943 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ac9d8fe7 | 944 | } |
a1587d97 | 945 | } |
ae636747 | 946 | |
a50c8aa9 SS |
947 | /* Check to see if a command in the device's command queue matches this one. |
948 | * Signal the completion or free the command, and return 1. Return 0 if the | |
949 | * completed command isn't at the head of the command list. | |
950 | */ | |
951 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | |
952 | struct xhci_virt_device *virt_dev, | |
953 | struct xhci_event_cmd *event) | |
954 | { | |
955 | struct xhci_command *command; | |
956 | ||
957 | if (list_empty(&virt_dev->cmd_list)) | |
958 | return 0; | |
959 | ||
960 | command = list_entry(virt_dev->cmd_list.next, | |
961 | struct xhci_command, cmd_list); | |
962 | if (xhci->cmd_ring->dequeue != command->command_trb) | |
963 | return 0; | |
964 | ||
965 | command->status = | |
966 | GET_COMP_CODE(event->status); | |
967 | list_del(&command->cmd_list); | |
968 | if (command->completion) | |
969 | complete(command->completion); | |
970 | else | |
971 | xhci_free_command(xhci, command); | |
972 | return 1; | |
973 | } | |
974 | ||
7f84eef0 SS |
975 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
976 | struct xhci_event_cmd *event) | |
977 | { | |
3ffbba95 | 978 | int slot_id = TRB_TO_SLOT_ID(event->flags); |
7f84eef0 SS |
979 | u64 cmd_dma; |
980 | dma_addr_t cmd_dequeue_dma; | |
ac9d8fe7 | 981 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 982 | struct xhci_virt_device *virt_dev; |
ac9d8fe7 SS |
983 | unsigned int ep_index; |
984 | struct xhci_ring *ep_ring; | |
985 | unsigned int ep_state; | |
7f84eef0 | 986 | |
8e595a5d | 987 | cmd_dma = event->cmd_trb; |
23e3be11 | 988 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
7f84eef0 SS |
989 | xhci->cmd_ring->dequeue); |
990 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ | |
991 | if (cmd_dequeue_dma == 0) { | |
992 | xhci->error_bitmask |= 1 << 4; | |
993 | return; | |
994 | } | |
995 | /* Does the DMA address match our internal dequeue pointer address? */ | |
996 | if (cmd_dma != (u64) cmd_dequeue_dma) { | |
997 | xhci->error_bitmask |= 1 << 5; | |
998 | return; | |
999 | } | |
1000 | switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) { | |
3ffbba95 SS |
1001 | case TRB_TYPE(TRB_ENABLE_SLOT): |
1002 | if (GET_COMP_CODE(event->status) == COMP_SUCCESS) | |
1003 | xhci->slot_id = slot_id; | |
1004 | else | |
1005 | xhci->slot_id = 0; | |
1006 | complete(&xhci->addr_dev); | |
1007 | break; | |
1008 | case TRB_TYPE(TRB_DISABLE_SLOT): | |
1009 | if (xhci->devs[slot_id]) | |
1010 | xhci_free_virt_device(xhci, slot_id); | |
1011 | break; | |
f94e0186 | 1012 | case TRB_TYPE(TRB_CONFIG_EP): |
913a8a34 | 1013 | virt_dev = xhci->devs[slot_id]; |
a50c8aa9 | 1014 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) |
913a8a34 | 1015 | break; |
ac9d8fe7 SS |
1016 | /* |
1017 | * Configure endpoint commands can come from the USB core | |
1018 | * configuration or alt setting changes, or because the HW | |
1019 | * needed an extra configure endpoint command after a reset | |
8df75f42 SS |
1020 | * endpoint command or streams were being configured. |
1021 | * If the command was for a halted endpoint, the xHCI driver | |
1022 | * is not waiting on the configure endpoint command. | |
ac9d8fe7 SS |
1023 | */ |
1024 | ctrl_ctx = xhci_get_input_control_ctx(xhci, | |
913a8a34 | 1025 | virt_dev->in_ctx); |
ac9d8fe7 SS |
1026 | /* Input ctx add_flags are the endpoint index plus one */ |
1027 | ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1; | |
06df5729 | 1028 | /* A usb_set_interface() call directly after clearing a halted |
e9df17eb SS |
1029 | * condition may race on this quirky hardware. Not worth |
1030 | * worrying about, since this is prototype hardware. Not sure | |
1031 | * if this will work for streams, but streams support was | |
1032 | * untested on this prototype. | |
06df5729 | 1033 | */ |
ac9d8fe7 | 1034 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && |
06df5729 SS |
1035 | ep_index != (unsigned int) -1 && |
1036 | ctrl_ctx->add_flags - SLOT_FLAG == | |
1037 | ctrl_ctx->drop_flags) { | |
1038 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; | |
1039 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
1040 | if (!(ep_state & EP_HALTED)) | |
1041 | goto bandwidth_change; | |
1042 | xhci_dbg(xhci, "Completed config ep cmd - " | |
1043 | "last ep index = %d, state = %d\n", | |
1044 | ep_index, ep_state); | |
e9df17eb | 1045 | /* Clear internal halted state and restart ring(s) */ |
63a0d9ab | 1046 | xhci->devs[slot_id]->eps[ep_index].ep_state &= |
ac9d8fe7 | 1047 | ~EP_HALTED; |
e9df17eb | 1048 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
06df5729 | 1049 | break; |
ac9d8fe7 | 1050 | } |
06df5729 SS |
1051 | bandwidth_change: |
1052 | xhci_dbg(xhci, "Completed config ep cmd\n"); | |
1053 | xhci->devs[slot_id]->cmd_status = | |
1054 | GET_COMP_CODE(event->status); | |
1055 | complete(&xhci->devs[slot_id]->cmd_completion); | |
f94e0186 | 1056 | break; |
2d3f1fac | 1057 | case TRB_TYPE(TRB_EVAL_CONTEXT): |
ac1c1b7f SS |
1058 | virt_dev = xhci->devs[slot_id]; |
1059 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) | |
1060 | break; | |
2d3f1fac SS |
1061 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); |
1062 | complete(&xhci->devs[slot_id]->cmd_completion); | |
1063 | break; | |
3ffbba95 SS |
1064 | case TRB_TYPE(TRB_ADDR_DEV): |
1065 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status); | |
1066 | complete(&xhci->addr_dev); | |
1067 | break; | |
ae636747 SS |
1068 | case TRB_TYPE(TRB_STOP_RING): |
1069 | handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue); | |
1070 | break; | |
1071 | case TRB_TYPE(TRB_SET_DEQ): | |
1072 | handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); | |
1073 | break; | |
7f84eef0 SS |
1074 | case TRB_TYPE(TRB_CMD_NOOP): |
1075 | ++xhci->noops_handled; | |
1076 | break; | |
a1587d97 SS |
1077 | case TRB_TYPE(TRB_RESET_EP): |
1078 | handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); | |
1079 | break; | |
2a8f82c4 SS |
1080 | case TRB_TYPE(TRB_RESET_DEV): |
1081 | xhci_dbg(xhci, "Completed reset device command.\n"); | |
1082 | slot_id = TRB_TO_SLOT_ID( | |
1083 | xhci->cmd_ring->dequeue->generic.field[3]); | |
1084 | virt_dev = xhci->devs[slot_id]; | |
1085 | if (virt_dev) | |
1086 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); | |
1087 | else | |
1088 | xhci_warn(xhci, "Reset device command completion " | |
1089 | "for disabled slot %u\n", slot_id); | |
1090 | break; | |
0238634d SS |
1091 | case TRB_TYPE(TRB_NEC_GET_FW): |
1092 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
1093 | xhci->error_bitmask |= 1 << 6; | |
1094 | break; | |
1095 | } | |
1096 | xhci_dbg(xhci, "NEC firmware version %2x.%02x\n", | |
1097 | NEC_FW_MAJOR(event->status), | |
1098 | NEC_FW_MINOR(event->status)); | |
1099 | break; | |
7f84eef0 SS |
1100 | default: |
1101 | /* Skip over unknown commands on the event ring */ | |
1102 | xhci->error_bitmask |= 1 << 6; | |
1103 | break; | |
1104 | } | |
1105 | inc_deq(xhci, xhci->cmd_ring, false); | |
1106 | } | |
1107 | ||
0238634d SS |
1108 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1109 | union xhci_trb *event) | |
1110 | { | |
1111 | u32 trb_type; | |
1112 | ||
1113 | trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]); | |
1114 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); | |
1115 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1116 | handle_cmd_completion(xhci, &event->event_cmd); | |
1117 | } | |
1118 | ||
0f2a7930 SS |
1119 | static void handle_port_status(struct xhci_hcd *xhci, |
1120 | union xhci_trb *event) | |
1121 | { | |
1122 | u32 port_id; | |
1123 | ||
1124 | /* Port status change events always have a successful completion code */ | |
1125 | if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) { | |
1126 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); | |
1127 | xhci->error_bitmask |= 1 << 8; | |
1128 | } | |
1129 | /* FIXME: core doesn't care about all port link state changes yet */ | |
1130 | port_id = GET_PORT_ID(event->generic.field[0]); | |
1131 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); | |
1132 | ||
1133 | /* Update event ring dequeue pointer before dropping the lock */ | |
1134 | inc_deq(xhci, xhci->event_ring, true); | |
23e3be11 | 1135 | xhci_set_hc_event_deq(xhci); |
0f2a7930 SS |
1136 | |
1137 | spin_unlock(&xhci->lock); | |
1138 | /* Pass this up to the core */ | |
1139 | usb_hcd_poll_rh_status(xhci_to_hcd(xhci)); | |
1140 | spin_lock(&xhci->lock); | |
1141 | } | |
1142 | ||
d0e96f5a SS |
1143 | /* |
1144 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1145 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1146 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1147 | * returns 0. | |
1148 | */ | |
6648f29d | 1149 | struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, |
d0e96f5a SS |
1150 | union xhci_trb *start_trb, |
1151 | union xhci_trb *end_trb, | |
1152 | dma_addr_t suspect_dma) | |
1153 | { | |
1154 | dma_addr_t start_dma; | |
1155 | dma_addr_t end_seg_dma; | |
1156 | dma_addr_t end_trb_dma; | |
1157 | struct xhci_segment *cur_seg; | |
1158 | ||
23e3be11 | 1159 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1160 | cur_seg = start_seg; |
1161 | ||
1162 | do { | |
2fa88daa | 1163 | if (start_dma == 0) |
326b4810 | 1164 | return NULL; |
ae636747 | 1165 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1166 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1167 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1168 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1169 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a SS |
1170 | |
1171 | if (end_trb_dma > 0) { | |
1172 | /* The end TRB is in this segment, so suspect should be here */ | |
1173 | if (start_dma <= end_trb_dma) { | |
1174 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1175 | return cur_seg; | |
1176 | } else { | |
1177 | /* Case for one segment with | |
1178 | * a TD wrapped around to the top | |
1179 | */ | |
1180 | if ((suspect_dma >= start_dma && | |
1181 | suspect_dma <= end_seg_dma) || | |
1182 | (suspect_dma >= cur_seg->dma && | |
1183 | suspect_dma <= end_trb_dma)) | |
1184 | return cur_seg; | |
1185 | } | |
326b4810 | 1186 | return NULL; |
d0e96f5a SS |
1187 | } else { |
1188 | /* Might still be somewhere in this segment */ | |
1189 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1190 | return cur_seg; | |
1191 | } | |
1192 | cur_seg = cur_seg->next; | |
23e3be11 | 1193 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1194 | } while (cur_seg != start_seg); |
d0e96f5a | 1195 | |
326b4810 | 1196 | return NULL; |
d0e96f5a SS |
1197 | } |
1198 | ||
bcef3fd5 SS |
1199 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1200 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1201 | unsigned int stream_id, |
bcef3fd5 SS |
1202 | struct xhci_td *td, union xhci_trb *event_trb) |
1203 | { | |
1204 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
1205 | ep->ep_state |= EP_HALTED; | |
1206 | ep->stopped_td = td; | |
1207 | ep->stopped_trb = event_trb; | |
e9df17eb | 1208 | ep->stopped_stream = stream_id; |
1624ae1c | 1209 | |
bcef3fd5 SS |
1210 | xhci_queue_reset_ep(xhci, slot_id, ep_index); |
1211 | xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); | |
1624ae1c SS |
1212 | |
1213 | ep->stopped_td = NULL; | |
1214 | ep->stopped_trb = NULL; | |
5e5cf6fc | 1215 | ep->stopped_stream = 0; |
1624ae1c | 1216 | |
bcef3fd5 SS |
1217 | xhci_ring_cmd_db(xhci); |
1218 | } | |
1219 | ||
1220 | /* Check if an error has halted the endpoint ring. The class driver will | |
1221 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1222 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1223 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1224 | * Ring Dequeue Pointer command manually. | |
1225 | */ | |
1226 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1227 | struct xhci_ep_ctx *ep_ctx, | |
1228 | unsigned int trb_comp_code) | |
1229 | { | |
1230 | /* TRB completion codes that may require a manual halt cleanup */ | |
1231 | if (trb_comp_code == COMP_TX_ERR || | |
1232 | trb_comp_code == COMP_BABBLE || | |
1233 | trb_comp_code == COMP_SPLIT_ERR) | |
1234 | /* The 0.96 spec says a babbling control endpoint | |
1235 | * is not halted. The 0.96 spec says it is. Some HW | |
1236 | * claims to be 0.95 compliant, but it halts the control | |
1237 | * endpoint anyway. Check if a babble halted the | |
1238 | * endpoint. | |
1239 | */ | |
1240 | if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED) | |
1241 | return 1; | |
1242 | ||
1243 | return 0; | |
1244 | } | |
1245 | ||
b45b5069 SS |
1246 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1247 | { | |
1248 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1249 | /* Vendor defined "informational" completion code, | |
1250 | * treat as not-an-error. | |
1251 | */ | |
1252 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1253 | trb_comp_code); | |
1254 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1255 | return 1; | |
1256 | } | |
1257 | return 0; | |
1258 | } | |
1259 | ||
d0e96f5a SS |
1260 | /* |
1261 | * If this function returns an error condition, it means it got a Transfer | |
1262 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
1263 | * At this point, the host controller is probably hosed and should be reset. | |
1264 | */ | |
1265 | static int handle_tx_event(struct xhci_hcd *xhci, | |
1266 | struct xhci_transfer_event *event) | |
1267 | { | |
1268 | struct xhci_virt_device *xdev; | |
63a0d9ab | 1269 | struct xhci_virt_ep *ep; |
d0e96f5a | 1270 | struct xhci_ring *ep_ring; |
82d1009f | 1271 | unsigned int slot_id; |
d0e96f5a | 1272 | int ep_index; |
326b4810 | 1273 | struct xhci_td *td = NULL; |
d0e96f5a SS |
1274 | dma_addr_t event_dma; |
1275 | struct xhci_segment *event_seg; | |
1276 | union xhci_trb *event_trb; | |
326b4810 | 1277 | struct urb *urb = NULL; |
d0e96f5a | 1278 | int status = -EINPROGRESS; |
d115b048 | 1279 | struct xhci_ep_ctx *ep_ctx; |
66d1eebc | 1280 | u32 trb_comp_code; |
d0e96f5a | 1281 | |
66e49d87 | 1282 | xhci_dbg(xhci, "In %s\n", __func__); |
82d1009f SS |
1283 | slot_id = TRB_TO_SLOT_ID(event->flags); |
1284 | xdev = xhci->devs[slot_id]; | |
d0e96f5a SS |
1285 | if (!xdev) { |
1286 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | |
1287 | return -ENODEV; | |
1288 | } | |
1289 | ||
1290 | /* Endpoint ID is 1 based, our index is zero based */ | |
1291 | ep_index = TRB_TO_EP_ID(event->flags) - 1; | |
66e49d87 | 1292 | xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index); |
63a0d9ab | 1293 | ep = &xdev->eps[ep_index]; |
e9df17eb | 1294 | ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer); |
d115b048 JY |
1295 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
1296 | if (!ep_ring || (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) { | |
e9df17eb SS |
1297 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
1298 | "or incorrect stream ring\n"); | |
d0e96f5a SS |
1299 | return -ENODEV; |
1300 | } | |
1301 | ||
8e595a5d | 1302 | event_dma = event->buffer; |
d0e96f5a | 1303 | /* This TRB should be in the TD at the head of this ring's TD list */ |
66e49d87 | 1304 | xhci_dbg(xhci, "%s - checking for list empty\n", __func__); |
d0e96f5a SS |
1305 | if (list_empty(&ep_ring->td_list)) { |
1306 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", | |
1307 | TRB_TO_SLOT_ID(event->flags), ep_index); | |
1308 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", | |
1309 | (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10); | |
1310 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); | |
1311 | urb = NULL; | |
1312 | goto cleanup; | |
1313 | } | |
66e49d87 | 1314 | xhci_dbg(xhci, "%s - getting list entry\n", __func__); |
d0e96f5a SS |
1315 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
1316 | ||
1317 | /* Is this a TRB in the currently executing TD? */ | |
66e49d87 | 1318 | xhci_dbg(xhci, "%s - looking for TD\n", __func__); |
d0e96f5a SS |
1319 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, |
1320 | td->last_trb, event_dma); | |
66e49d87 | 1321 | xhci_dbg(xhci, "%s - found event_seg = %p\n", __func__, event_seg); |
d0e96f5a SS |
1322 | if (!event_seg) { |
1323 | /* HC is busted, give up! */ | |
1324 | xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n"); | |
1325 | return -ESHUTDOWN; | |
1326 | } | |
1327 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)]; | |
b10de142 SS |
1328 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", |
1329 | (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10); | |
8e595a5d SS |
1330 | xhci_dbg(xhci, "Offset 0x00 (buffer lo) = 0x%x\n", |
1331 | lower_32_bits(event->buffer)); | |
1332 | xhci_dbg(xhci, "Offset 0x04 (buffer hi) = 0x%x\n", | |
1333 | upper_32_bits(event->buffer)); | |
b10de142 SS |
1334 | xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n", |
1335 | (unsigned int) event->transfer_len); | |
1336 | xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n", | |
1337 | (unsigned int) event->flags); | |
1338 | ||
1339 | /* Look for common error cases */ | |
66d1eebc SS |
1340 | trb_comp_code = GET_COMP_CODE(event->transfer_len); |
1341 | switch (trb_comp_code) { | |
b10de142 SS |
1342 | /* Skip codes that require special handling depending on |
1343 | * transfer type | |
1344 | */ | |
1345 | case COMP_SUCCESS: | |
1346 | case COMP_SHORT_TX: | |
1347 | break; | |
ae636747 SS |
1348 | case COMP_STOP: |
1349 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); | |
1350 | break; | |
1351 | case COMP_STOP_INVAL: | |
1352 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); | |
1353 | break; | |
b10de142 SS |
1354 | case COMP_STALL: |
1355 | xhci_warn(xhci, "WARN: Stalled endpoint\n"); | |
63a0d9ab | 1356 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
1357 | status = -EPIPE; |
1358 | break; | |
1359 | case COMP_TRB_ERR: | |
1360 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); | |
1361 | status = -EILSEQ; | |
1362 | break; | |
ec74e403 | 1363 | case COMP_SPLIT_ERR: |
b10de142 SS |
1364 | case COMP_TX_ERR: |
1365 | xhci_warn(xhci, "WARN: transfer error on endpoint\n"); | |
1366 | status = -EPROTO; | |
1367 | break; | |
4a73143c SS |
1368 | case COMP_BABBLE: |
1369 | xhci_warn(xhci, "WARN: babble error on endpoint\n"); | |
1370 | status = -EOVERFLOW; | |
1371 | break; | |
b10de142 SS |
1372 | case COMP_DB_ERR: |
1373 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); | |
1374 | status = -ENOSR; | |
1375 | break; | |
1376 | default: | |
b45b5069 | 1377 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
1378 | status = 0; |
1379 | break; | |
1380 | } | |
b10de142 SS |
1381 | xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n"); |
1382 | urb = NULL; | |
1383 | goto cleanup; | |
1384 | } | |
d0e96f5a SS |
1385 | /* Now update the urb's actual_length and give back to the core */ |
1386 | /* Was this a control transfer? */ | |
1387 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) { | |
1388 | xhci_debug_trb(xhci, xhci->event_ring->dequeue); | |
66d1eebc | 1389 | switch (trb_comp_code) { |
d0e96f5a SS |
1390 | case COMP_SUCCESS: |
1391 | if (event_trb == ep_ring->dequeue) { | |
1392 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n"); | |
1393 | status = -ESHUTDOWN; | |
1394 | } else if (event_trb != td->last_trb) { | |
1395 | xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n"); | |
1396 | status = -ESHUTDOWN; | |
1397 | } else { | |
1398 | xhci_dbg(xhci, "Successful control transfer!\n"); | |
1399 | status = 0; | |
1400 | } | |
1401 | break; | |
1402 | case COMP_SHORT_TX: | |
1403 | xhci_warn(xhci, "WARN: short transfer on control ep\n"); | |
204970a4 SS |
1404 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
1405 | status = -EREMOTEIO; | |
1406 | else | |
1407 | status = 0; | |
d0e96f5a | 1408 | break; |
bcef3fd5 SS |
1409 | |
1410 | default: | |
1411 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
1412 | ep_ctx, trb_comp_code)) | |
83fbcdcc | 1413 | break; |
bcef3fd5 SS |
1414 | xhci_dbg(xhci, "TRB error code %u, " |
1415 | "halted endpoint index = %u\n", | |
1416 | trb_comp_code, ep_index); | |
83fbcdcc | 1417 | /* else fall through */ |
82d1009f SS |
1418 | case COMP_STALL: |
1419 | /* Did we transfer part of the data (middle) phase? */ | |
1420 | if (event_trb != ep_ring->dequeue && | |
1421 | event_trb != td->last_trb) | |
1422 | td->urb->actual_length = | |
1423 | td->urb->transfer_buffer_length | |
1424 | - TRB_LEN(event->transfer_len); | |
1425 | else | |
1426 | td->urb->actual_length = 0; | |
1427 | ||
bcef3fd5 | 1428 | xhci_cleanup_halted_endpoint(xhci, |
e9df17eb | 1429 | slot_id, ep_index, 0, td, event_trb); |
82d1009f | 1430 | goto td_cleanup; |
d0e96f5a SS |
1431 | } |
1432 | /* | |
1433 | * Did we transfer any data, despite the errors that might have | |
1434 | * happened? I.e. did we get past the setup stage? | |
1435 | */ | |
1436 | if (event_trb != ep_ring->dequeue) { | |
1437 | /* The event was for the status stage */ | |
1438 | if (event_trb == td->last_trb) { | |
c92bcfa7 SS |
1439 | if (td->urb->actual_length != 0) { |
1440 | /* Don't overwrite a previously set error code */ | |
204970a4 SS |
1441 | if ((status == -EINPROGRESS || |
1442 | status == 0) && | |
1443 | (td->urb->transfer_flags | |
1444 | & URB_SHORT_NOT_OK)) | |
c92bcfa7 SS |
1445 | /* Did we already see a short data stage? */ |
1446 | status = -EREMOTEIO; | |
1447 | } else { | |
62889610 SS |
1448 | td->urb->actual_length = |
1449 | td->urb->transfer_buffer_length; | |
c92bcfa7 | 1450 | } |
d0e96f5a | 1451 | } else { |
ae636747 | 1452 | /* Maybe the event was for the data stage? */ |
66d1eebc | 1453 | if (trb_comp_code != COMP_STOP_INVAL) { |
ae636747 SS |
1454 | /* We didn't stop on a link TRB in the middle */ |
1455 | td->urb->actual_length = | |
1456 | td->urb->transfer_buffer_length - | |
1457 | TRB_LEN(event->transfer_len); | |
62889610 SS |
1458 | xhci_dbg(xhci, "Waiting for status stage event\n"); |
1459 | urb = NULL; | |
1460 | goto cleanup; | |
1461 | } | |
d0e96f5a SS |
1462 | } |
1463 | } | |
d0e96f5a | 1464 | } else { |
66d1eebc | 1465 | switch (trb_comp_code) { |
b10de142 SS |
1466 | case COMP_SUCCESS: |
1467 | /* Double check that the HW transferred everything. */ | |
1468 | if (event_trb != td->last_trb) { | |
1469 | xhci_warn(xhci, "WARN Successful completion " | |
1470 | "on short TX\n"); | |
1471 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1472 | status = -EREMOTEIO; | |
1473 | else | |
1474 | status = 0; | |
1475 | } else { | |
624defa1 SS |
1476 | if (usb_endpoint_xfer_bulk(&td->urb->ep->desc)) |
1477 | xhci_dbg(xhci, "Successful bulk " | |
1478 | "transfer!\n"); | |
1479 | else | |
1480 | xhci_dbg(xhci, "Successful interrupt " | |
1481 | "transfer!\n"); | |
b10de142 SS |
1482 | status = 0; |
1483 | } | |
1484 | break; | |
1485 | case COMP_SHORT_TX: | |
1486 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1487 | status = -EREMOTEIO; | |
1488 | else | |
1489 | status = 0; | |
1490 | break; | |
1491 | default: | |
1492 | /* Others already handled above */ | |
1493 | break; | |
1494 | } | |
1495 | dev_dbg(&td->urb->dev->dev, | |
1496 | "ep %#x - asked for %d bytes, " | |
1497 | "%d bytes untransferred\n", | |
1498 | td->urb->ep->desc.bEndpointAddress, | |
1499 | td->urb->transfer_buffer_length, | |
1500 | TRB_LEN(event->transfer_len)); | |
1501 | /* Fast path - was this the last TRB in the TD for this URB? */ | |
1502 | if (event_trb == td->last_trb) { | |
1503 | if (TRB_LEN(event->transfer_len) != 0) { | |
1504 | td->urb->actual_length = | |
1505 | td->urb->transfer_buffer_length - | |
1506 | TRB_LEN(event->transfer_len); | |
99eb32db SS |
1507 | if (td->urb->transfer_buffer_length < |
1508 | td->urb->actual_length) { | |
b10de142 SS |
1509 | xhci_warn(xhci, "HC gave bad length " |
1510 | "of %d bytes left\n", | |
1511 | TRB_LEN(event->transfer_len)); | |
1512 | td->urb->actual_length = 0; | |
2f697f6c SS |
1513 | if (td->urb->transfer_flags & |
1514 | URB_SHORT_NOT_OK) | |
1515 | status = -EREMOTEIO; | |
1516 | else | |
1517 | status = 0; | |
b10de142 | 1518 | } |
c92bcfa7 SS |
1519 | /* Don't overwrite a previously set error code */ |
1520 | if (status == -EINPROGRESS) { | |
1521 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1522 | status = -EREMOTEIO; | |
1523 | else | |
1524 | status = 0; | |
1525 | } | |
b10de142 SS |
1526 | } else { |
1527 | td->urb->actual_length = td->urb->transfer_buffer_length; | |
1528 | /* Ignore a short packet completion if the | |
1529 | * untransferred length was zero. | |
1530 | */ | |
c92bcfa7 SS |
1531 | if (status == -EREMOTEIO) |
1532 | status = 0; | |
b10de142 SS |
1533 | } |
1534 | } else { | |
ae636747 SS |
1535 | /* Slow path - walk the list, starting from the dequeue |
1536 | * pointer, to get the actual length transferred. | |
b10de142 | 1537 | */ |
ae636747 SS |
1538 | union xhci_trb *cur_trb; |
1539 | struct xhci_segment *cur_seg; | |
1540 | ||
b10de142 | 1541 | td->urb->actual_length = 0; |
ae636747 SS |
1542 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; |
1543 | cur_trb != event_trb; | |
1544 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
54b5acf3 AX |
1545 | if ((cur_trb->generic.field[3] & |
1546 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) && | |
1547 | (cur_trb->generic.field[3] & | |
1548 | TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK)) | |
ae636747 SS |
1549 | td->urb->actual_length += |
1550 | TRB_LEN(cur_trb->generic.field[2]); | |
b10de142 | 1551 | } |
ae636747 SS |
1552 | /* If the ring didn't stop on a Link or No-op TRB, add |
1553 | * in the actual bytes transferred from the Normal TRB | |
1554 | */ | |
66d1eebc | 1555 | if (trb_comp_code != COMP_STOP_INVAL) |
ae636747 SS |
1556 | td->urb->actual_length += |
1557 | TRB_LEN(cur_trb->generic.field[2]) - | |
1558 | TRB_LEN(event->transfer_len); | |
b10de142 | 1559 | } |
d0e96f5a | 1560 | } |
66d1eebc SS |
1561 | if (trb_comp_code == COMP_STOP_INVAL || |
1562 | trb_comp_code == COMP_STOP) { | |
c92bcfa7 SS |
1563 | /* The Endpoint Stop Command completion will take care of any |
1564 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1565 | * the ring dequeue pointer or take this TD off any lists yet. | |
1566 | */ | |
63a0d9ab SS |
1567 | ep->stopped_td = td; |
1568 | ep->stopped_trb = event_trb; | |
ae636747 | 1569 | } else { |
bcef3fd5 | 1570 | if (trb_comp_code == COMP_STALL) { |
c92bcfa7 SS |
1571 | /* The transfer is completed from the driver's |
1572 | * perspective, but we need to issue a set dequeue | |
1573 | * command for this stalled endpoint to move the dequeue | |
1574 | * pointer past the TD. We can't do that here because | |
bcef3fd5 SS |
1575 | * the halt condition must be cleared first. Let the |
1576 | * USB class driver clear the stall later. | |
c92bcfa7 | 1577 | */ |
63a0d9ab SS |
1578 | ep->stopped_td = td; |
1579 | ep->stopped_trb = event_trb; | |
e9df17eb | 1580 | ep->stopped_stream = ep_ring->stream_id; |
bcef3fd5 SS |
1581 | } else if (xhci_requires_manual_halt_cleanup(xhci, |
1582 | ep_ctx, trb_comp_code)) { | |
1583 | /* Other types of errors halt the endpoint, but the | |
1584 | * class driver doesn't call usb_reset_endpoint() unless | |
1585 | * the error is -EPIPE. Clear the halted status in the | |
1586 | * xHCI hardware manually. | |
1587 | */ | |
1588 | xhci_cleanup_halted_endpoint(xhci, | |
e9df17eb | 1589 | slot_id, ep_index, ep_ring->stream_id, td, event_trb); |
c92bcfa7 SS |
1590 | } else { |
1591 | /* Update ring dequeue pointer */ | |
1592 | while (ep_ring->dequeue != td->last_trb) | |
1593 | inc_deq(xhci, ep_ring, false); | |
ae636747 | 1594 | inc_deq(xhci, ep_ring, false); |
c92bcfa7 | 1595 | } |
b10de142 | 1596 | |
82d1009f | 1597 | td_cleanup: |
ae636747 SS |
1598 | /* Clean up the endpoint's TD list */ |
1599 | urb = td->urb; | |
99eb32db SS |
1600 | /* Do one last check of the actual transfer length. |
1601 | * If the host controller said we transferred more data than | |
1602 | * the buffer length, urb->actual_length will be a very big | |
1603 | * number (since it's unsigned). Play it safe and say we didn't | |
1604 | * transfer anything. | |
1605 | */ | |
1606 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1607 | xhci_warn(xhci, "URB transfer length is wrong, " | |
1608 | "xHC issue? req. len = %u, " | |
1609 | "act. len = %u\n", | |
1610 | urb->transfer_buffer_length, | |
1611 | urb->actual_length); | |
1612 | urb->actual_length = 0; | |
2f697f6c SS |
1613 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
1614 | status = -EREMOTEIO; | |
1615 | else | |
1616 | status = 0; | |
99eb32db | 1617 | } |
ae636747 SS |
1618 | list_del(&td->td_list); |
1619 | /* Was this TD slated to be cancelled but completed anyway? */ | |
678539cf | 1620 | if (!list_empty(&td->cancelled_td_list)) |
ae636747 | 1621 | list_del(&td->cancelled_td_list); |
678539cf | 1622 | |
82d1009f SS |
1623 | /* Leave the TD around for the reset endpoint function to use |
1624 | * (but only if it's not a control endpoint, since we already | |
1625 | * queued the Set TR dequeue pointer command for stalled | |
1626 | * control endpoints). | |
1627 | */ | |
1628 | if (usb_endpoint_xfer_control(&urb->ep->desc) || | |
83fbcdcc SS |
1629 | (trb_comp_code != COMP_STALL && |
1630 | trb_comp_code != COMP_BABBLE)) { | |
c92bcfa7 SS |
1631 | kfree(td); |
1632 | } | |
ae636747 SS |
1633 | urb->hcpriv = NULL; |
1634 | } | |
d0e96f5a SS |
1635 | cleanup: |
1636 | inc_deq(xhci, xhci->event_ring, true); | |
23e3be11 | 1637 | xhci_set_hc_event_deq(xhci); |
d0e96f5a | 1638 | |
b10de142 | 1639 | /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */ |
d0e96f5a SS |
1640 | if (urb) { |
1641 | usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb); | |
66e49d87 | 1642 | xhci_dbg(xhci, "Giveback URB %p, len = %d, status = %d\n", |
9191eee7 | 1643 | urb, urb->actual_length, status); |
d0e96f5a SS |
1644 | spin_unlock(&xhci->lock); |
1645 | usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status); | |
1646 | spin_lock(&xhci->lock); | |
1647 | } | |
1648 | return 0; | |
1649 | } | |
1650 | ||
0f2a7930 SS |
1651 | /* |
1652 | * This function handles all OS-owned events on the event ring. It may drop | |
1653 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
1654 | */ | |
b7258a4a | 1655 | void xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
1656 | { |
1657 | union xhci_trb *event; | |
0f2a7930 | 1658 | int update_ptrs = 1; |
d0e96f5a | 1659 | int ret; |
7f84eef0 | 1660 | |
66e49d87 | 1661 | xhci_dbg(xhci, "In %s\n", __func__); |
7f84eef0 SS |
1662 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
1663 | xhci->error_bitmask |= 1 << 1; | |
1664 | return; | |
1665 | } | |
1666 | ||
1667 | event = xhci->event_ring->dequeue; | |
1668 | /* Does the HC or OS own the TRB? */ | |
1669 | if ((event->event_cmd.flags & TRB_CYCLE) != | |
1670 | xhci->event_ring->cycle_state) { | |
1671 | xhci->error_bitmask |= 1 << 2; | |
1672 | return; | |
1673 | } | |
66e49d87 | 1674 | xhci_dbg(xhci, "%s - OS owns TRB\n", __func__); |
7f84eef0 | 1675 | |
0f2a7930 | 1676 | /* FIXME: Handle more event types. */ |
7f84eef0 SS |
1677 | switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) { |
1678 | case TRB_TYPE(TRB_COMPLETION): | |
66e49d87 | 1679 | xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__); |
7f84eef0 | 1680 | handle_cmd_completion(xhci, &event->event_cmd); |
66e49d87 | 1681 | xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__); |
7f84eef0 | 1682 | break; |
0f2a7930 | 1683 | case TRB_TYPE(TRB_PORT_STATUS): |
66e49d87 | 1684 | xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__); |
0f2a7930 | 1685 | handle_port_status(xhci, event); |
66e49d87 | 1686 | xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__); |
0f2a7930 SS |
1687 | update_ptrs = 0; |
1688 | break; | |
d0e96f5a | 1689 | case TRB_TYPE(TRB_TRANSFER): |
66e49d87 | 1690 | xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__); |
d0e96f5a | 1691 | ret = handle_tx_event(xhci, &event->trans_event); |
66e49d87 | 1692 | xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__); |
d0e96f5a SS |
1693 | if (ret < 0) |
1694 | xhci->error_bitmask |= 1 << 9; | |
1695 | else | |
1696 | update_ptrs = 0; | |
1697 | break; | |
7f84eef0 | 1698 | default: |
0238634d SS |
1699 | if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48)) |
1700 | handle_vendor_event(xhci, event); | |
1701 | else | |
1702 | xhci->error_bitmask |= 1 << 3; | |
7f84eef0 | 1703 | } |
6f5165cf SS |
1704 | /* Any of the above functions may drop and re-acquire the lock, so check |
1705 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
1706 | */ | |
1707 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
1708 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
1709 | "event handler.\n"); | |
1710 | return; | |
1711 | } | |
7f84eef0 | 1712 | |
0f2a7930 SS |
1713 | if (update_ptrs) { |
1714 | /* Update SW and HC event ring dequeue pointer */ | |
1715 | inc_deq(xhci, xhci->event_ring, true); | |
23e3be11 | 1716 | xhci_set_hc_event_deq(xhci); |
0f2a7930 | 1717 | } |
7f84eef0 | 1718 | /* Are there more items on the event ring? */ |
b7258a4a | 1719 | xhci_handle_event(xhci); |
7f84eef0 SS |
1720 | } |
1721 | ||
d0e96f5a SS |
1722 | /**** Endpoint Ring Operations ****/ |
1723 | ||
7f84eef0 SS |
1724 | /* |
1725 | * Generic function for queueing a TRB on a ring. | |
1726 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
1727 | * |
1728 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
1729 | * prepare_transfer()? | |
7f84eef0 SS |
1730 | */ |
1731 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
6cc30d85 | 1732 | bool consumer, bool more_trbs_coming, |
7f84eef0 SS |
1733 | u32 field1, u32 field2, u32 field3, u32 field4) |
1734 | { | |
1735 | struct xhci_generic_trb *trb; | |
1736 | ||
1737 | trb = &ring->enqueue->generic; | |
1738 | trb->field[0] = field1; | |
1739 | trb->field[1] = field2; | |
1740 | trb->field[2] = field3; | |
1741 | trb->field[3] = field4; | |
6cc30d85 | 1742 | inc_enq(xhci, ring, consumer, more_trbs_coming); |
7f84eef0 SS |
1743 | } |
1744 | ||
d0e96f5a SS |
1745 | /* |
1746 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
1747 | * FIXME allocate segments if the ring is full. | |
1748 | */ | |
1749 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
1750 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) | |
1751 | { | |
1752 | /* Make sure the endpoint has been added to xHC schedule */ | |
1753 | xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state); | |
1754 | switch (ep_state) { | |
1755 | case EP_STATE_DISABLED: | |
1756 | /* | |
1757 | * USB core changed config/interfaces without notifying us, | |
1758 | * or hardware is reporting the wrong state. | |
1759 | */ | |
1760 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
1761 | return -ENOENT; | |
d0e96f5a | 1762 | case EP_STATE_ERROR: |
c92bcfa7 | 1763 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
1764 | /* FIXME event handling code for error needs to clear it */ |
1765 | /* XXX not sure if this should be -ENOENT or not */ | |
1766 | return -EINVAL; | |
c92bcfa7 SS |
1767 | case EP_STATE_HALTED: |
1768 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
1769 | case EP_STATE_STOPPED: |
1770 | case EP_STATE_RUNNING: | |
1771 | break; | |
1772 | default: | |
1773 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
1774 | /* | |
1775 | * FIXME issue Configure Endpoint command to try to get the HC | |
1776 | * back into a known state. | |
1777 | */ | |
1778 | return -EINVAL; | |
1779 | } | |
1780 | if (!room_on_ring(xhci, ep_ring, num_trbs)) { | |
1781 | /* FIXME allocate more room */ | |
1782 | xhci_err(xhci, "ERROR no room on ep ring\n"); | |
1783 | return -ENOMEM; | |
1784 | } | |
6c12db90 JY |
1785 | |
1786 | if (enqueue_is_link_trb(ep_ring)) { | |
1787 | struct xhci_ring *ring = ep_ring; | |
1788 | union xhci_trb *next; | |
6c12db90 JY |
1789 | |
1790 | xhci_dbg(xhci, "prepare_ring: pointing to link trb\n"); | |
1791 | next = ring->enqueue; | |
1792 | ||
1793 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
1794 | ||
1795 | /* If we're not dealing with 0.95 hardware, | |
1796 | * clear the chain bit. | |
1797 | */ | |
1798 | if (!xhci_link_trb_quirk(xhci)) | |
1799 | next->link.control &= ~TRB_CHAIN; | |
1800 | else | |
1801 | next->link.control |= TRB_CHAIN; | |
1802 | ||
1803 | wmb(); | |
1804 | next->link.control ^= (u32) TRB_CYCLE; | |
1805 | ||
1806 | /* Toggle the cycle bit after the last ring segment. */ | |
1807 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
1808 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
1809 | if (!in_interrupt()) { | |
1810 | xhci_dbg(xhci, "queue_trb: Toggle cycle " | |
1811 | "state for ring %p = %i\n", | |
1812 | ring, (unsigned int)ring->cycle_state); | |
1813 | } | |
1814 | } | |
1815 | ring->enq_seg = ring->enq_seg->next; | |
1816 | ring->enqueue = ring->enq_seg->trbs; | |
1817 | next = ring->enqueue; | |
1818 | } | |
1819 | } | |
1820 | ||
d0e96f5a SS |
1821 | return 0; |
1822 | } | |
1823 | ||
23e3be11 | 1824 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
1825 | struct xhci_virt_device *xdev, |
1826 | unsigned int ep_index, | |
e9df17eb | 1827 | unsigned int stream_id, |
d0e96f5a SS |
1828 | unsigned int num_trbs, |
1829 | struct urb *urb, | |
1830 | struct xhci_td **td, | |
1831 | gfp_t mem_flags) | |
1832 | { | |
1833 | int ret; | |
e9df17eb | 1834 | struct xhci_ring *ep_ring; |
d115b048 | 1835 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
1836 | |
1837 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
1838 | if (!ep_ring) { | |
1839 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
1840 | stream_id); | |
1841 | return -EINVAL; | |
1842 | } | |
1843 | ||
1844 | ret = prepare_ring(xhci, ep_ring, | |
d115b048 | 1845 | ep_ctx->ep_info & EP_STATE_MASK, |
d0e96f5a SS |
1846 | num_trbs, mem_flags); |
1847 | if (ret) | |
1848 | return ret; | |
1849 | *td = kzalloc(sizeof(struct xhci_td), mem_flags); | |
1850 | if (!*td) | |
1851 | return -ENOMEM; | |
1852 | INIT_LIST_HEAD(&(*td)->td_list); | |
ae636747 | 1853 | INIT_LIST_HEAD(&(*td)->cancelled_td_list); |
d0e96f5a SS |
1854 | |
1855 | ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb); | |
1856 | if (unlikely(ret)) { | |
1857 | kfree(*td); | |
1858 | return ret; | |
1859 | } | |
1860 | ||
1861 | (*td)->urb = urb; | |
1862 | urb->hcpriv = (void *) (*td); | |
1863 | /* Add this TD to the tail of the endpoint ring's TD list */ | |
e9df17eb SS |
1864 | list_add_tail(&(*td)->td_list, &ep_ring->td_list); |
1865 | (*td)->start_seg = ep_ring->enq_seg; | |
1866 | (*td)->first_trb = ep_ring->enqueue; | |
d0e96f5a SS |
1867 | |
1868 | return 0; | |
1869 | } | |
1870 | ||
23e3be11 | 1871 | static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) |
8a96c052 SS |
1872 | { |
1873 | int num_sgs, num_trbs, running_total, temp, i; | |
1874 | struct scatterlist *sg; | |
1875 | ||
1876 | sg = NULL; | |
1877 | num_sgs = urb->num_sgs; | |
1878 | temp = urb->transfer_buffer_length; | |
1879 | ||
1880 | xhci_dbg(xhci, "count sg list trbs: \n"); | |
1881 | num_trbs = 0; | |
910f8d0c | 1882 | for_each_sg(urb->sg, sg, num_sgs, i) { |
8a96c052 SS |
1883 | unsigned int previous_total_trbs = num_trbs; |
1884 | unsigned int len = sg_dma_len(sg); | |
1885 | ||
1886 | /* Scatter gather list entries may cross 64KB boundaries */ | |
1887 | running_total = TRB_MAX_BUFF_SIZE - | |
1888 | (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
1889 | if (running_total != 0) | |
1890 | num_trbs++; | |
1891 | ||
1892 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
1893 | while (running_total < sg_dma_len(sg)) { | |
1894 | num_trbs++; | |
1895 | running_total += TRB_MAX_BUFF_SIZE; | |
1896 | } | |
700e2052 GKH |
1897 | xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n", |
1898 | i, (unsigned long long)sg_dma_address(sg), | |
1899 | len, len, num_trbs - previous_total_trbs); | |
8a96c052 SS |
1900 | |
1901 | len = min_t(int, len, temp); | |
1902 | temp -= len; | |
1903 | if (temp == 0) | |
1904 | break; | |
1905 | } | |
1906 | xhci_dbg(xhci, "\n"); | |
1907 | if (!in_interrupt()) | |
1908 | dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n", | |
1909 | urb->ep->desc.bEndpointAddress, | |
1910 | urb->transfer_buffer_length, | |
1911 | num_trbs); | |
1912 | return num_trbs; | |
1913 | } | |
1914 | ||
23e3be11 | 1915 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
8a96c052 SS |
1916 | { |
1917 | if (num_trbs != 0) | |
1918 | dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " | |
1919 | "TRBs, %d left\n", __func__, | |
1920 | urb->ep->desc.bEndpointAddress, num_trbs); | |
1921 | if (running_total != urb->transfer_buffer_length) | |
1922 | dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " | |
1923 | "queued %#x (%d), asked for %#x (%d)\n", | |
1924 | __func__, | |
1925 | urb->ep->desc.bEndpointAddress, | |
1926 | running_total, running_total, | |
1927 | urb->transfer_buffer_length, | |
1928 | urb->transfer_buffer_length); | |
1929 | } | |
1930 | ||
23e3be11 | 1931 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 1932 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
8a96c052 SS |
1933 | struct xhci_generic_trb *start_trb, struct xhci_td *td) |
1934 | { | |
8a96c052 SS |
1935 | /* |
1936 | * Pass all the TRBs to the hardware at once and make sure this write | |
1937 | * isn't reordered. | |
1938 | */ | |
1939 | wmb(); | |
1940 | start_trb->field[3] |= start_cycle; | |
e9df17eb | 1941 | ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
1942 | } |
1943 | ||
624defa1 SS |
1944 | /* |
1945 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
1946 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
1947 | * (comprised of sg list entries) can take several service intervals to | |
1948 | * transmit. | |
1949 | */ | |
1950 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
1951 | struct urb *urb, int slot_id, unsigned int ep_index) | |
1952 | { | |
1953 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, | |
1954 | xhci->devs[slot_id]->out_ctx, ep_index); | |
1955 | int xhci_interval; | |
1956 | int ep_interval; | |
1957 | ||
1958 | xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info); | |
1959 | ep_interval = urb->interval; | |
1960 | /* Convert to microframes */ | |
1961 | if (urb->dev->speed == USB_SPEED_LOW || | |
1962 | urb->dev->speed == USB_SPEED_FULL) | |
1963 | ep_interval *= 8; | |
1964 | /* FIXME change this to a warning and a suggestion to use the new API | |
1965 | * to set the polling interval (once the API is added). | |
1966 | */ | |
1967 | if (xhci_interval != ep_interval) { | |
1968 | if (!printk_ratelimit()) | |
1969 | dev_dbg(&urb->dev->dev, "Driver uses different interval" | |
1970 | " (%d microframe%s) than xHCI " | |
1971 | "(%d microframe%s)\n", | |
1972 | ep_interval, | |
1973 | ep_interval == 1 ? "" : "s", | |
1974 | xhci_interval, | |
1975 | xhci_interval == 1 ? "" : "s"); | |
1976 | urb->interval = xhci_interval; | |
1977 | /* Convert back to frames for LS/FS devices */ | |
1978 | if (urb->dev->speed == USB_SPEED_LOW || | |
1979 | urb->dev->speed == USB_SPEED_FULL) | |
1980 | urb->interval /= 8; | |
1981 | } | |
1982 | return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index); | |
1983 | } | |
1984 | ||
04dd950d SS |
1985 | /* |
1986 | * The TD size is the number of bytes remaining in the TD (including this TRB), | |
1987 | * right shifted by 10. | |
1988 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
1989 | */ | |
1990 | static u32 xhci_td_remainder(unsigned int remainder) | |
1991 | { | |
1992 | u32 max = (1 << (21 - 17 + 1)) - 1; | |
1993 | ||
1994 | if ((remainder >> 10) >= max) | |
1995 | return max << 17; | |
1996 | else | |
1997 | return (remainder >> 10) << 17; | |
1998 | } | |
1999 | ||
23e3be11 | 2000 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
8a96c052 SS |
2001 | struct urb *urb, int slot_id, unsigned int ep_index) |
2002 | { | |
2003 | struct xhci_ring *ep_ring; | |
2004 | unsigned int num_trbs; | |
2005 | struct xhci_td *td; | |
2006 | struct scatterlist *sg; | |
2007 | int num_sgs; | |
2008 | int trb_buff_len, this_sg_len, running_total; | |
2009 | bool first_trb; | |
2010 | u64 addr; | |
6cc30d85 | 2011 | bool more_trbs_coming; |
8a96c052 SS |
2012 | |
2013 | struct xhci_generic_trb *start_trb; | |
2014 | int start_cycle; | |
2015 | ||
e9df17eb SS |
2016 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
2017 | if (!ep_ring) | |
2018 | return -EINVAL; | |
2019 | ||
8a96c052 SS |
2020 | num_trbs = count_sg_trbs_needed(xhci, urb); |
2021 | num_sgs = urb->num_sgs; | |
2022 | ||
23e3be11 | 2023 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb SS |
2024 | ep_index, urb->stream_id, |
2025 | num_trbs, urb, &td, mem_flags); | |
8a96c052 SS |
2026 | if (trb_buff_len < 0) |
2027 | return trb_buff_len; | |
2028 | /* | |
2029 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
2030 | * until we've finished creating all the other TRBs. The ring's cycle | |
2031 | * state may change as we enqueue the other TRBs, so save it too. | |
2032 | */ | |
2033 | start_trb = &ep_ring->enqueue->generic; | |
2034 | start_cycle = ep_ring->cycle_state; | |
2035 | ||
2036 | running_total = 0; | |
2037 | /* | |
2038 | * How much data is in the first TRB? | |
2039 | * | |
2040 | * There are three forces at work for TRB buffer pointers and lengths: | |
2041 | * 1. We don't want to walk off the end of this sg-list entry buffer. | |
2042 | * 2. The transfer length that the driver requested may be smaller than | |
2043 | * the amount of memory allocated for this scatter-gather list. | |
2044 | * 3. TRBs buffers can't cross 64KB boundaries. | |
2045 | */ | |
910f8d0c | 2046 | sg = urb->sg; |
8a96c052 SS |
2047 | addr = (u64) sg_dma_address(sg); |
2048 | this_sg_len = sg_dma_len(sg); | |
2049 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
2050 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
2051 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); | |
2052 | if (trb_buff_len > urb->transfer_buffer_length) | |
2053 | trb_buff_len = urb->transfer_buffer_length; | |
2054 | xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n", | |
2055 | trb_buff_len); | |
2056 | ||
2057 | first_trb = true; | |
2058 | /* Queue the first TRB, even if it's zero-length */ | |
2059 | do { | |
2060 | u32 field = 0; | |
f9dc68fe | 2061 | u32 length_field = 0; |
04dd950d | 2062 | u32 remainder = 0; |
8a96c052 SS |
2063 | |
2064 | /* Don't change the cycle bit of the first TRB until later */ | |
2065 | if (first_trb) | |
2066 | first_trb = false; | |
2067 | else | |
2068 | field |= ep_ring->cycle_state; | |
2069 | ||
2070 | /* Chain all the TRBs together; clear the chain bit in the last | |
2071 | * TRB to indicate it's the last TRB in the chain. | |
2072 | */ | |
2073 | if (num_trbs > 1) { | |
2074 | field |= TRB_CHAIN; | |
2075 | } else { | |
2076 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
2077 | td->last_trb = ep_ring->enqueue; | |
2078 | field |= TRB_IOC; | |
2079 | } | |
2080 | xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), " | |
2081 | "64KB boundary at %#x, end dma = %#x\n", | |
2082 | (unsigned int) addr, trb_buff_len, trb_buff_len, | |
2083 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
2084 | (unsigned int) addr + trb_buff_len); | |
2085 | if (TRB_MAX_BUFF_SIZE - | |
2086 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) { | |
2087 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); | |
2088 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", | |
2089 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
2090 | (unsigned int) addr + trb_buff_len); | |
2091 | } | |
04dd950d SS |
2092 | remainder = xhci_td_remainder(urb->transfer_buffer_length - |
2093 | running_total) ; | |
f9dc68fe | 2094 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 2095 | remainder | |
f9dc68fe | 2096 | TRB_INTR_TARGET(0); |
6cc30d85 SS |
2097 | if (num_trbs > 1) |
2098 | more_trbs_coming = true; | |
2099 | else | |
2100 | more_trbs_coming = false; | |
2101 | queue_trb(xhci, ep_ring, false, more_trbs_coming, | |
8e595a5d SS |
2102 | lower_32_bits(addr), |
2103 | upper_32_bits(addr), | |
f9dc68fe | 2104 | length_field, |
8a96c052 SS |
2105 | /* We always want to know if the TRB was short, |
2106 | * or we won't get an event when it completes. | |
2107 | * (Unless we use event data TRBs, which are a | |
2108 | * waste of space and HC resources.) | |
2109 | */ | |
2110 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); | |
2111 | --num_trbs; | |
2112 | running_total += trb_buff_len; | |
2113 | ||
2114 | /* Calculate length for next transfer -- | |
2115 | * Are we done queueing all the TRBs for this sg entry? | |
2116 | */ | |
2117 | this_sg_len -= trb_buff_len; | |
2118 | if (this_sg_len == 0) { | |
2119 | --num_sgs; | |
2120 | if (num_sgs == 0) | |
2121 | break; | |
2122 | sg = sg_next(sg); | |
2123 | addr = (u64) sg_dma_address(sg); | |
2124 | this_sg_len = sg_dma_len(sg); | |
2125 | } else { | |
2126 | addr += trb_buff_len; | |
2127 | } | |
2128 | ||
2129 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
2130 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
2131 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); | |
2132 | if (running_total + trb_buff_len > urb->transfer_buffer_length) | |
2133 | trb_buff_len = | |
2134 | urb->transfer_buffer_length - running_total; | |
2135 | } while (running_total < urb->transfer_buffer_length); | |
2136 | ||
2137 | check_trb_math(urb, num_trbs, running_total); | |
e9df17eb SS |
2138 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
2139 | start_cycle, start_trb, td); | |
8a96c052 SS |
2140 | return 0; |
2141 | } | |
2142 | ||
b10de142 | 2143 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
23e3be11 | 2144 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
b10de142 SS |
2145 | struct urb *urb, int slot_id, unsigned int ep_index) |
2146 | { | |
2147 | struct xhci_ring *ep_ring; | |
2148 | struct xhci_td *td; | |
2149 | int num_trbs; | |
2150 | struct xhci_generic_trb *start_trb; | |
2151 | bool first_trb; | |
6cc30d85 | 2152 | bool more_trbs_coming; |
b10de142 | 2153 | int start_cycle; |
f9dc68fe | 2154 | u32 field, length_field; |
b10de142 SS |
2155 | |
2156 | int running_total, trb_buff_len, ret; | |
2157 | u64 addr; | |
2158 | ||
ff9c895f | 2159 | if (urb->num_sgs) |
8a96c052 SS |
2160 | return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); |
2161 | ||
e9df17eb SS |
2162 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
2163 | if (!ep_ring) | |
2164 | return -EINVAL; | |
b10de142 SS |
2165 | |
2166 | num_trbs = 0; | |
2167 | /* How much data is (potentially) left before the 64KB boundary? */ | |
2168 | running_total = TRB_MAX_BUFF_SIZE - | |
2169 | (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
2170 | ||
2171 | /* If there's some data on this 64KB chunk, or we have to send a | |
2172 | * zero-length transfer, we need at least one TRB | |
2173 | */ | |
2174 | if (running_total != 0 || urb->transfer_buffer_length == 0) | |
2175 | num_trbs++; | |
2176 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
2177 | while (running_total < urb->transfer_buffer_length) { | |
2178 | num_trbs++; | |
2179 | running_total += TRB_MAX_BUFF_SIZE; | |
2180 | } | |
2181 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ | |
2182 | ||
2183 | if (!in_interrupt()) | |
700e2052 | 2184 | dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n", |
b10de142 | 2185 | urb->ep->desc.bEndpointAddress, |
8a96c052 SS |
2186 | urb->transfer_buffer_length, |
2187 | urb->transfer_buffer_length, | |
700e2052 | 2188 | (unsigned long long)urb->transfer_dma, |
b10de142 | 2189 | num_trbs); |
8a96c052 | 2190 | |
e9df17eb SS |
2191 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
2192 | ep_index, urb->stream_id, | |
b10de142 SS |
2193 | num_trbs, urb, &td, mem_flags); |
2194 | if (ret < 0) | |
2195 | return ret; | |
2196 | ||
2197 | /* | |
2198 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
2199 | * until we've finished creating all the other TRBs. The ring's cycle | |
2200 | * state may change as we enqueue the other TRBs, so save it too. | |
2201 | */ | |
2202 | start_trb = &ep_ring->enqueue->generic; | |
2203 | start_cycle = ep_ring->cycle_state; | |
2204 | ||
2205 | running_total = 0; | |
2206 | /* How much data is in the first TRB? */ | |
2207 | addr = (u64) urb->transfer_dma; | |
2208 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
2209 | (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
2210 | if (urb->transfer_buffer_length < trb_buff_len) | |
2211 | trb_buff_len = urb->transfer_buffer_length; | |
2212 | ||
2213 | first_trb = true; | |
2214 | ||
2215 | /* Queue the first TRB, even if it's zero-length */ | |
2216 | do { | |
04dd950d | 2217 | u32 remainder = 0; |
b10de142 SS |
2218 | field = 0; |
2219 | ||
2220 | /* Don't change the cycle bit of the first TRB until later */ | |
2221 | if (first_trb) | |
2222 | first_trb = false; | |
2223 | else | |
2224 | field |= ep_ring->cycle_state; | |
2225 | ||
2226 | /* Chain all the TRBs together; clear the chain bit in the last | |
2227 | * TRB to indicate it's the last TRB in the chain. | |
2228 | */ | |
2229 | if (num_trbs > 1) { | |
2230 | field |= TRB_CHAIN; | |
2231 | } else { | |
2232 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
2233 | td->last_trb = ep_ring->enqueue; | |
2234 | field |= TRB_IOC; | |
2235 | } | |
04dd950d SS |
2236 | remainder = xhci_td_remainder(urb->transfer_buffer_length - |
2237 | running_total); | |
f9dc68fe | 2238 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 2239 | remainder | |
f9dc68fe | 2240 | TRB_INTR_TARGET(0); |
6cc30d85 SS |
2241 | if (num_trbs > 1) |
2242 | more_trbs_coming = true; | |
2243 | else | |
2244 | more_trbs_coming = false; | |
2245 | queue_trb(xhci, ep_ring, false, more_trbs_coming, | |
8e595a5d SS |
2246 | lower_32_bits(addr), |
2247 | upper_32_bits(addr), | |
f9dc68fe | 2248 | length_field, |
b10de142 SS |
2249 | /* We always want to know if the TRB was short, |
2250 | * or we won't get an event when it completes. | |
2251 | * (Unless we use event data TRBs, which are a | |
2252 | * waste of space and HC resources.) | |
2253 | */ | |
2254 | field | TRB_ISP | TRB_TYPE(TRB_NORMAL)); | |
2255 | --num_trbs; | |
2256 | running_total += trb_buff_len; | |
2257 | ||
2258 | /* Calculate length for next transfer */ | |
2259 | addr += trb_buff_len; | |
2260 | trb_buff_len = urb->transfer_buffer_length - running_total; | |
2261 | if (trb_buff_len > TRB_MAX_BUFF_SIZE) | |
2262 | trb_buff_len = TRB_MAX_BUFF_SIZE; | |
2263 | } while (running_total < urb->transfer_buffer_length); | |
2264 | ||
8a96c052 | 2265 | check_trb_math(urb, num_trbs, running_total); |
e9df17eb SS |
2266 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
2267 | start_cycle, start_trb, td); | |
b10de142 SS |
2268 | return 0; |
2269 | } | |
2270 | ||
d0e96f5a | 2271 | /* Caller must have locked xhci->lock */ |
23e3be11 | 2272 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
2273 | struct urb *urb, int slot_id, unsigned int ep_index) |
2274 | { | |
2275 | struct xhci_ring *ep_ring; | |
2276 | int num_trbs; | |
2277 | int ret; | |
2278 | struct usb_ctrlrequest *setup; | |
2279 | struct xhci_generic_trb *start_trb; | |
2280 | int start_cycle; | |
f9dc68fe | 2281 | u32 field, length_field; |
d0e96f5a SS |
2282 | struct xhci_td *td; |
2283 | ||
e9df17eb SS |
2284 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
2285 | if (!ep_ring) | |
2286 | return -EINVAL; | |
d0e96f5a SS |
2287 | |
2288 | /* | |
2289 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
2290 | * DMA address. | |
2291 | */ | |
2292 | if (!urb->setup_packet) | |
2293 | return -EINVAL; | |
2294 | ||
2295 | if (!in_interrupt()) | |
2296 | xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n", | |
2297 | slot_id, ep_index); | |
2298 | /* 1 TRB for setup, 1 for status */ | |
2299 | num_trbs = 2; | |
2300 | /* | |
2301 | * Don't need to check if we need additional event data and normal TRBs, | |
2302 | * since data in control transfers will never get bigger than 16MB | |
2303 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
2304 | */ | |
2305 | if (urb->transfer_buffer_length > 0) | |
2306 | num_trbs++; | |
e9df17eb SS |
2307 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
2308 | ep_index, urb->stream_id, | |
2309 | num_trbs, urb, &td, mem_flags); | |
d0e96f5a SS |
2310 | if (ret < 0) |
2311 | return ret; | |
2312 | ||
2313 | /* | |
2314 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
2315 | * until we've finished creating all the other TRBs. The ring's cycle | |
2316 | * state may change as we enqueue the other TRBs, so save it too. | |
2317 | */ | |
2318 | start_trb = &ep_ring->enqueue->generic; | |
2319 | start_cycle = ep_ring->cycle_state; | |
2320 | ||
2321 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
2322 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
2323 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
6cc30d85 | 2324 | queue_trb(xhci, ep_ring, false, true, |
d0e96f5a SS |
2325 | /* FIXME endianness is probably going to bite my ass here. */ |
2326 | setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16, | |
2327 | setup->wIndex | setup->wLength << 16, | |
2328 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
2329 | /* Immediate data in pointer */ | |
2330 | TRB_IDT | TRB_TYPE(TRB_SETUP)); | |
2331 | ||
2332 | /* If there's data, queue data TRBs */ | |
2333 | field = 0; | |
f9dc68fe | 2334 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
04dd950d | 2335 | xhci_td_remainder(urb->transfer_buffer_length) | |
f9dc68fe | 2336 | TRB_INTR_TARGET(0); |
d0e96f5a SS |
2337 | if (urb->transfer_buffer_length > 0) { |
2338 | if (setup->bRequestType & USB_DIR_IN) | |
2339 | field |= TRB_DIR_IN; | |
6cc30d85 | 2340 | queue_trb(xhci, ep_ring, false, true, |
d0e96f5a SS |
2341 | lower_32_bits(urb->transfer_dma), |
2342 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 2343 | length_field, |
d0e96f5a SS |
2344 | /* Event on short tx */ |
2345 | field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state); | |
2346 | } | |
2347 | ||
2348 | /* Save the DMA address of the last TRB in the TD */ | |
2349 | td->last_trb = ep_ring->enqueue; | |
2350 | ||
2351 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
2352 | /* If the device sent data, the status stage is an OUT transfer */ | |
2353 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
2354 | field = 0; | |
2355 | else | |
2356 | field = TRB_DIR_IN; | |
6cc30d85 | 2357 | queue_trb(xhci, ep_ring, false, false, |
d0e96f5a SS |
2358 | 0, |
2359 | 0, | |
2360 | TRB_INTR_TARGET(0), | |
2361 | /* Event on completion */ | |
2362 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
2363 | ||
e9df17eb SS |
2364 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
2365 | start_cycle, start_trb, td); | |
d0e96f5a SS |
2366 | return 0; |
2367 | } | |
2368 | ||
2369 | /**** Command Ring Operations ****/ | |
2370 | ||
913a8a34 SS |
2371 | /* Generic function for queueing a command TRB on the command ring. |
2372 | * Check to make sure there's room on the command ring for one command TRB. | |
2373 | * Also check that there's room reserved for commands that must not fail. | |
2374 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
2375 | * then only check for the number of reserved spots. | |
2376 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
2377 | * because the command event handler may want to resubmit a failed command. | |
2378 | */ | |
2379 | static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, | |
2380 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 2381 | { |
913a8a34 | 2382 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a SS |
2383 | int ret; |
2384 | ||
913a8a34 SS |
2385 | if (!command_must_succeed) |
2386 | reserved_trbs++; | |
2387 | ||
d1dc908a SS |
2388 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
2389 | reserved_trbs, GFP_ATOMIC); | |
2390 | if (ret < 0) { | |
2391 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
2392 | if (command_must_succeed) |
2393 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
2394 | "unfailable commands failed.\n"); | |
d1dc908a | 2395 | return ret; |
7f84eef0 | 2396 | } |
6cc30d85 | 2397 | queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3, |
7f84eef0 SS |
2398 | field4 | xhci->cmd_ring->cycle_state); |
2399 | return 0; | |
2400 | } | |
2401 | ||
2402 | /* Queue a no-op command on the command ring */ | |
2403 | static int queue_cmd_noop(struct xhci_hcd *xhci) | |
2404 | { | |
913a8a34 | 2405 | return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP), false); |
7f84eef0 SS |
2406 | } |
2407 | ||
2408 | /* | |
2409 | * Place a no-op command on the command ring to test the command and | |
2410 | * event ring. | |
2411 | */ | |
23e3be11 | 2412 | void *xhci_setup_one_noop(struct xhci_hcd *xhci) |
7f84eef0 SS |
2413 | { |
2414 | if (queue_cmd_noop(xhci) < 0) | |
2415 | return NULL; | |
2416 | xhci->noops_submitted++; | |
23e3be11 | 2417 | return xhci_ring_cmd_db; |
7f84eef0 | 2418 | } |
3ffbba95 SS |
2419 | |
2420 | /* Queue a slot enable or disable request on the command ring */ | |
23e3be11 | 2421 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) |
3ffbba95 SS |
2422 | { |
2423 | return queue_command(xhci, 0, 0, 0, | |
913a8a34 | 2424 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
2425 | } |
2426 | ||
2427 | /* Queue an address device command TRB */ | |
23e3be11 SS |
2428 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
2429 | u32 slot_id) | |
3ffbba95 | 2430 | { |
8e595a5d SS |
2431 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
2432 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 | 2433 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id), |
2a8f82c4 SS |
2434 | false); |
2435 | } | |
2436 | ||
0238634d SS |
2437 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, |
2438 | u32 field1, u32 field2, u32 field3, u32 field4) | |
2439 | { | |
2440 | return queue_command(xhci, field1, field2, field3, field4, false); | |
2441 | } | |
2442 | ||
2a8f82c4 SS |
2443 | /* Queue a reset device command TRB */ |
2444 | int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id) | |
2445 | { | |
2446 | return queue_command(xhci, 0, 0, 0, | |
2447 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), | |
913a8a34 | 2448 | false); |
3ffbba95 | 2449 | } |
f94e0186 SS |
2450 | |
2451 | /* Queue a configure endpoint command TRB */ | |
23e3be11 | 2452 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
913a8a34 | 2453 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 2454 | { |
8e595a5d SS |
2455 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
2456 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
2457 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
2458 | command_must_succeed); | |
f94e0186 | 2459 | } |
ae636747 | 2460 | |
f2217e8e SS |
2461 | /* Queue an evaluate context command TRB */ |
2462 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, | |
2463 | u32 slot_id) | |
2464 | { | |
2465 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), | |
2466 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
2467 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
2468 | false); | |
f2217e8e SS |
2469 | } |
2470 | ||
23e3be11 | 2471 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
ae636747 SS |
2472 | unsigned int ep_index) |
2473 | { | |
2474 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
2475 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
2476 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
2477 | ||
2478 | return queue_command(xhci, 0, 0, 0, | |
913a8a34 | 2479 | trb_slot_id | trb_ep_index | type, false); |
ae636747 SS |
2480 | } |
2481 | ||
2482 | /* Set Transfer Ring Dequeue Pointer command. | |
2483 | * This should not be used for endpoints that have streams enabled. | |
2484 | */ | |
2485 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
e9df17eb SS |
2486 | unsigned int ep_index, unsigned int stream_id, |
2487 | struct xhci_segment *deq_seg, | |
ae636747 SS |
2488 | union xhci_trb *deq_ptr, u32 cycle_state) |
2489 | { | |
2490 | dma_addr_t addr; | |
2491 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
2492 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
e9df17eb | 2493 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
ae636747 SS |
2494 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
2495 | ||
23e3be11 | 2496 | addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); |
c92bcfa7 | 2497 | if (addr == 0) { |
ae636747 | 2498 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 GKH |
2499 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
2500 | deq_seg, deq_ptr); | |
c92bcfa7 SS |
2501 | return 0; |
2502 | } | |
8e595a5d | 2503 | return queue_command(xhci, lower_32_bits(addr) | cycle_state, |
e9df17eb | 2504 | upper_32_bits(addr), trb_stream_id, |
913a8a34 | 2505 | trb_slot_id | trb_ep_index | type, false); |
ae636747 | 2506 | } |
a1587d97 SS |
2507 | |
2508 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, | |
2509 | unsigned int ep_index) | |
2510 | { | |
2511 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
2512 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
2513 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
2514 | ||
913a8a34 SS |
2515 | return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type, |
2516 | false); | |
a1587d97 | 2517 | } |