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Commit | Line | Data |
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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
f9c589e1 | 69 | #include <linux/dma-mapping.h> |
7f84eef0 | 70 | #include "xhci.h" |
3a7fa5be | 71 | #include "xhci-trace.h" |
0cbd4b34 | 72 | #include "xhci-mtk.h" |
7f84eef0 SS |
73 | |
74 | /* | |
75 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
76 | * address of the TRB. | |
77 | */ | |
23e3be11 | 78 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
79 | union xhci_trb *trb) |
80 | { | |
6071d836 | 81 | unsigned long segment_offset; |
7f84eef0 | 82 | |
6071d836 | 83 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 84 | return 0; |
6071d836 SS |
85 | /* offset in TRBs */ |
86 | segment_offset = trb - seg->trbs; | |
7895086a | 87 | if (segment_offset >= TRBS_PER_SEGMENT) |
7f84eef0 | 88 | return 0; |
6071d836 | 89 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
90 | } |
91 | ||
2d98ef40 MN |
92 | static bool trb_is_link(union xhci_trb *trb) |
93 | { | |
94 | return TRB_TYPE_LINK_LE32(trb->link.control); | |
95 | } | |
96 | ||
bd5e67f5 MN |
97 | static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) |
98 | { | |
99 | return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; | |
100 | } | |
101 | ||
102 | static bool last_trb_on_ring(struct xhci_ring *ring, | |
103 | struct xhci_segment *seg, union xhci_trb *trb) | |
104 | { | |
105 | return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); | |
106 | } | |
107 | ||
d0c77d84 MN |
108 | static bool link_trb_toggles_cycle(union xhci_trb *trb) |
109 | { | |
110 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; | |
111 | } | |
112 | ||
ae636747 SS |
113 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
114 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
115 | * effect the ring dequeue or enqueue pointers. | |
116 | */ | |
117 | static void next_trb(struct xhci_hcd *xhci, | |
118 | struct xhci_ring *ring, | |
119 | struct xhci_segment **seg, | |
120 | union xhci_trb **trb) | |
121 | { | |
2d98ef40 | 122 | if (trb_is_link(*trb)) { |
ae636747 SS |
123 | *seg = (*seg)->next; |
124 | *trb = ((*seg)->trbs); | |
125 | } else { | |
a1669b2c | 126 | (*trb)++; |
ae636747 SS |
127 | } |
128 | } | |
129 | ||
7f84eef0 SS |
130 | /* |
131 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
132 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
133 | */ | |
3b72fca0 | 134 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 135 | { |
7f84eef0 | 136 | ring->deq_updates++; |
b008df60 | 137 | |
bd5e67f5 MN |
138 | /* event ring doesn't have link trbs, check for last trb */ |
139 | if (ring->type == TYPE_EVENT) { | |
140 | if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { | |
50d0206f | 141 | ring->dequeue++; |
bd5e67f5 | 142 | return; |
7f84eef0 | 143 | } |
bd5e67f5 MN |
144 | if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) |
145 | ring->cycle_state ^= 1; | |
146 | ring->deq_seg = ring->deq_seg->next; | |
147 | ring->dequeue = ring->deq_seg->trbs; | |
148 | return; | |
149 | } | |
150 | ||
151 | /* All other rings have link trbs */ | |
152 | if (!trb_is_link(ring->dequeue)) { | |
153 | ring->dequeue++; | |
154 | ring->num_trbs_free++; | |
155 | } | |
156 | while (trb_is_link(ring->dequeue)) { | |
157 | ring->deq_seg = ring->deq_seg->next; | |
158 | ring->dequeue = ring->deq_seg->trbs; | |
159 | } | |
160 | return; | |
7f84eef0 SS |
161 | } |
162 | ||
163 | /* | |
164 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
165 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
166 | * | |
167 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
168 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
169 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
170 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
171 | * | |
172 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
173 | * set, but other sections talk about dealing with the chain bit set. This was |
174 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
175 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
176 | * |
177 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
178 | * prepare_transfer()? | |
7f84eef0 | 179 | */ |
6cc30d85 | 180 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 181 | bool more_trbs_coming) |
7f84eef0 SS |
182 | { |
183 | u32 chain; | |
184 | union xhci_trb *next; | |
185 | ||
28ccd296 | 186 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 | 187 | /* If this is not event ring, there is one less usable TRB */ |
2d98ef40 | 188 | if (!trb_is_link(ring->enqueue)) |
b008df60 | 189 | ring->num_trbs_free--; |
7f84eef0 SS |
190 | next = ++(ring->enqueue); |
191 | ||
192 | ring->enq_updates++; | |
2251198b | 193 | /* Update the dequeue pointer further if that was a link TRB */ |
2d98ef40 | 194 | while (trb_is_link(next)) { |
6cc30d85 | 195 | |
2251198b MN |
196 | /* |
197 | * If the caller doesn't plan on enqueueing more TDs before | |
198 | * ringing the doorbell, then we don't want to give the link TRB | |
199 | * to the hardware just yet. We'll give the link TRB back in | |
200 | * prepare_ring() just before we enqueue the TD at the top of | |
201 | * the ring. | |
202 | */ | |
203 | if (!chain && !more_trbs_coming) | |
204 | break; | |
3b72fca0 | 205 | |
2251198b MN |
206 | /* If we're not dealing with 0.95 hardware or isoc rings on |
207 | * AMD 0.96 host, carry over the chain bit of the previous TRB | |
208 | * (which may mean the chain bit is cleared). | |
209 | */ | |
210 | if (!(ring->type == TYPE_ISOC && | |
211 | (xhci->quirks & XHCI_AMD_0x96_HOST)) && | |
212 | !xhci_link_trb_quirk(xhci)) { | |
213 | next->link.control &= cpu_to_le32(~TRB_CHAIN); | |
214 | next->link.control |= cpu_to_le32(chain); | |
7f84eef0 | 215 | } |
2251198b MN |
216 | /* Give this link TRB to the hardware */ |
217 | wmb(); | |
218 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
219 | ||
220 | /* Toggle the cycle bit after the last ring segment. */ | |
d0c77d84 | 221 | if (link_trb_toggles_cycle(next)) |
2251198b MN |
222 | ring->cycle_state ^= 1; |
223 | ||
7f84eef0 SS |
224 | ring->enq_seg = ring->enq_seg->next; |
225 | ring->enqueue = ring->enq_seg->trbs; | |
226 | next = ring->enqueue; | |
227 | } | |
228 | } | |
229 | ||
230 | /* | |
085deb16 AX |
231 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
232 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 233 | */ |
b008df60 | 234 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
235 | unsigned int num_trbs) |
236 | { | |
085deb16 | 237 | int num_trbs_in_deq_seg; |
b008df60 | 238 | |
085deb16 AX |
239 | if (ring->num_trbs_free < num_trbs) |
240 | return 0; | |
241 | ||
242 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
243 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
244 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
245 | return 0; | |
246 | } | |
247 | ||
248 | return 1; | |
7f84eef0 SS |
249 | } |
250 | ||
7f84eef0 | 251 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 252 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 253 | { |
c181bc5b EF |
254 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
255 | return; | |
256 | ||
7f84eef0 | 257 | xhci_dbg(xhci, "// Ding dong!\n"); |
204b7793 | 258 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 | 259 | /* Flush PCI posted writes */ |
b0ba9720 | 260 | readl(&xhci->dba->doorbell[0]); |
7f84eef0 SS |
261 | } |
262 | ||
b92cc66c EF |
263 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci) |
264 | { | |
265 | u64 temp_64; | |
266 | int ret; | |
267 | ||
268 | xhci_dbg(xhci, "Abort command ring\n"); | |
269 | ||
f7b2e403 | 270 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
b92cc66c | 271 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; |
3425aa03 MN |
272 | |
273 | /* | |
274 | * Writing the CMD_RING_ABORT bit should cause a cmd completion event, | |
275 | * however on some host hw the CMD_RING_RUNNING bit is correctly cleared | |
276 | * but the completion event in never sent. Use the cmd timeout timer to | |
277 | * handle those cases. Use twice the time to cover the bit polling retry | |
278 | */ | |
279 | mod_timer(&xhci->cmd_timer, jiffies + (2 * XHCI_CMD_DEFAULT_TIMEOUT)); | |
477632df SS |
280 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, |
281 | &xhci->op_regs->cmd_ring); | |
b92cc66c EF |
282 | |
283 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should | |
284 | * time the completion od all xHCI commands, including | |
285 | * the Command Abort operation. If software doesn't see | |
286 | * CRR negated in a timely manner (e.g. longer than 5 | |
287 | * seconds), then it should assume that the there are | |
288 | * larger problems with the xHC and assert HCRST. | |
289 | */ | |
dc0b177c | 290 | ret = xhci_handshake(&xhci->op_regs->cmd_ring, |
b92cc66c EF |
291 | CMD_RING_RUNNING, 0, 5 * 1000 * 1000); |
292 | if (ret < 0) { | |
a6809ffd MN |
293 | /* we are about to kill xhci, give it one more chance */ |
294 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, | |
295 | &xhci->op_regs->cmd_ring); | |
296 | udelay(1000); | |
297 | ret = xhci_handshake(&xhci->op_regs->cmd_ring, | |
298 | CMD_RING_RUNNING, 0, 3 * 1000 * 1000); | |
299 | if (ret == 0) | |
300 | return 0; | |
301 | ||
b92cc66c EF |
302 | xhci_err(xhci, "Stopped the command ring failed, " |
303 | "maybe the host is dead\n"); | |
3425aa03 | 304 | del_timer(&xhci->cmd_timer); |
b92cc66c | 305 | xhci->xhc_state |= XHCI_STATE_DYING; |
b92cc66c EF |
306 | xhci_halt(xhci); |
307 | return -ESHUTDOWN; | |
308 | } | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
be88fe4f | 313 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 314 | unsigned int slot_id, |
e9df17eb SS |
315 | unsigned int ep_index, |
316 | unsigned int stream_id) | |
ae636747 | 317 | { |
28ccd296 | 318 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
319 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
320 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 321 | |
ae636747 | 322 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 323 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
324 | * We don't want to restart any stream rings if there's a set dequeue |
325 | * pointer command pending because the device can choose to start any | |
326 | * stream once the endpoint is on the HW schedule. | |
ae636747 | 327 | */ |
50d64676 MW |
328 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
329 | (ep_state & EP_HALTED)) | |
330 | return; | |
204b7793 | 331 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
50d64676 MW |
332 | /* The CPU has better things to do at this point than wait for a |
333 | * write-posting flush. It'll get there soon enough. | |
334 | */ | |
ae636747 SS |
335 | } |
336 | ||
e9df17eb SS |
337 | /* Ring the doorbell for any rings with pending URBs */ |
338 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
339 | unsigned int slot_id, | |
340 | unsigned int ep_index) | |
341 | { | |
342 | unsigned int stream_id; | |
343 | struct xhci_virt_ep *ep; | |
344 | ||
345 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
346 | ||
347 | /* A ring has pending URBs if its TD list is not empty */ | |
348 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
d66eaf9f | 349 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
be88fe4f | 350 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
351 | return; |
352 | } | |
353 | ||
354 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
355 | stream_id++) { | |
356 | struct xhci_stream_info *stream_info = ep->stream_info; | |
357 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
358 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
359 | stream_id); | |
e9df17eb SS |
360 | } |
361 | } | |
362 | ||
75b040ec AI |
363 | /* Get the right ring for the given slot_id, ep_index and stream_id. |
364 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
365 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
366 | */ | |
367 | struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
021bff91 SS |
368 | unsigned int slot_id, unsigned int ep_index, |
369 | unsigned int stream_id) | |
370 | { | |
371 | struct xhci_virt_ep *ep; | |
372 | ||
373 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
374 | /* Common case: no streams */ | |
375 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
376 | return ep->ring; | |
377 | ||
378 | if (stream_id == 0) { | |
379 | xhci_warn(xhci, | |
380 | "WARN: Slot ID %u, ep index %u has streams, " | |
381 | "but URB has no stream ID.\n", | |
382 | slot_id, ep_index); | |
383 | return NULL; | |
384 | } | |
385 | ||
386 | if (stream_id < ep->stream_info->num_streams) | |
387 | return ep->stream_info->stream_rings[stream_id]; | |
388 | ||
389 | xhci_warn(xhci, | |
390 | "WARN: Slot ID %u, ep index %u has " | |
391 | "stream IDs 1 to %u allocated, " | |
392 | "but stream ID %u is requested.\n", | |
393 | slot_id, ep_index, | |
394 | ep->stream_info->num_streams - 1, | |
395 | stream_id); | |
396 | return NULL; | |
397 | } | |
398 | ||
ae636747 SS |
399 | /* |
400 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
401 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
402 | * dequeue pointer, and new consumer cycle state in state. | |
403 | * Update our internal representation of the ring's dequeue pointer. | |
404 | * | |
405 | * We do this in three jumps: | |
406 | * - First we update our new ring state to be the same as when the xHC stopped. | |
407 | * - Then we traverse the ring to find the segment that contains | |
408 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
409 | * any link TRBs with the toggle cycle bit set. | |
410 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
411 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
28ccd296 ME |
412 | * |
413 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | |
414 | * with correct __le32 accesses they should work fine. Only users of this are | |
415 | * in here. | |
ae636747 | 416 | */ |
c92bcfa7 | 417 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 418 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
419 | unsigned int stream_id, struct xhci_td *cur_td, |
420 | struct xhci_dequeue_state *state) | |
ae636747 SS |
421 | { |
422 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
c4bedb77 | 423 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; |
e9df17eb | 424 | struct xhci_ring *ep_ring; |
365038d8 MN |
425 | struct xhci_segment *new_seg; |
426 | union xhci_trb *new_deq; | |
c92bcfa7 | 427 | dma_addr_t addr; |
1f81b6d2 | 428 | u64 hw_dequeue; |
365038d8 MN |
429 | bool cycle_found = false; |
430 | bool td_last_trb_found = false; | |
ae636747 | 431 | |
e9df17eb SS |
432 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
433 | ep_index, stream_id); | |
434 | if (!ep_ring) { | |
435 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
436 | "for invalid stream ID %u.\n", | |
437 | stream_id); | |
438 | return; | |
439 | } | |
68e41c5d | 440 | |
ae636747 | 441 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
aa50b290 XR |
442 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
443 | "Finding endpoint context"); | |
c4bedb77 HG |
444 | /* 4.6.9 the css flag is written to the stream context for streams */ |
445 | if (ep->ep_state & EP_HAS_STREAMS) { | |
446 | struct xhci_stream_ctx *ctx = | |
447 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1f81b6d2 | 448 | hw_dequeue = le64_to_cpu(ctx->stream_ring); |
c4bedb77 HG |
449 | } else { |
450 | struct xhci_ep_ctx *ep_ctx | |
451 | = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); | |
1f81b6d2 | 452 | hw_dequeue = le64_to_cpu(ep_ctx->deq); |
c4bedb77 | 453 | } |
ae636747 | 454 | |
365038d8 MN |
455 | new_seg = ep_ring->deq_seg; |
456 | new_deq = ep_ring->dequeue; | |
457 | state->new_cycle_state = hw_dequeue & 0x1; | |
458 | ||
1f81b6d2 | 459 | /* |
365038d8 MN |
460 | * We want to find the pointer, segment and cycle state of the new trb |
461 | * (the one after current TD's last_trb). We know the cycle state at | |
462 | * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are | |
463 | * found. | |
1f81b6d2 | 464 | */ |
365038d8 MN |
465 | do { |
466 | if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) | |
467 | == (dma_addr_t)(hw_dequeue & ~0xf)) { | |
468 | cycle_found = true; | |
469 | if (td_last_trb_found) | |
470 | break; | |
471 | } | |
472 | if (new_deq == cur_td->last_trb) | |
473 | td_last_trb_found = true; | |
1f81b6d2 | 474 | |
365038d8 MN |
475 | if (cycle_found && |
476 | TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) && | |
477 | new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE)) | |
478 | state->new_cycle_state ^= 0x1; | |
479 | ||
480 | next_trb(xhci, ep_ring, &new_seg, &new_deq); | |
481 | ||
482 | /* Search wrapped around, bail out */ | |
483 | if (new_deq == ep->ring->dequeue) { | |
484 | xhci_err(xhci, "Error: Failed finding new dequeue state\n"); | |
485 | state->new_deq_seg = NULL; | |
486 | state->new_deq_ptr = NULL; | |
487 | return; | |
488 | } | |
489 | ||
490 | } while (!cycle_found || !td_last_trb_found); | |
ae636747 | 491 | |
365038d8 MN |
492 | state->new_deq_seg = new_seg; |
493 | state->new_deq_ptr = new_deq; | |
ae636747 | 494 | |
1f81b6d2 | 495 | /* Don't update the ring cycle state for the producer (us). */ |
aa50b290 XR |
496 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
497 | "Cycle state = 0x%x", state->new_cycle_state); | |
01a1fdb9 | 498 | |
aa50b290 XR |
499 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
500 | "New dequeue segment = %p (virtual)", | |
c92bcfa7 SS |
501 | state->new_deq_seg); |
502 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
aa50b290 XR |
503 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
504 | "New dequeue pointer = 0x%llx (DMA)", | |
c92bcfa7 | 505 | (unsigned long long) addr); |
ae636747 SS |
506 | } |
507 | ||
522989a2 SS |
508 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
509 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
510 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
511 | */ | |
23e3be11 | 512 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
522989a2 | 513 | struct xhci_td *cur_td, bool flip_cycle) |
ae636747 SS |
514 | { |
515 | struct xhci_segment *cur_seg; | |
516 | union xhci_trb *cur_trb; | |
517 | ||
518 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; | |
519 | true; | |
520 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 | 521 | if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) { |
ae636747 SS |
522 | /* Unchain any chained Link TRBs, but |
523 | * leave the pointers intact. | |
524 | */ | |
28ccd296 | 525 | cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN); |
522989a2 SS |
526 | /* Flip the cycle bit (link TRBs can't be the first |
527 | * or last TRB). | |
528 | */ | |
529 | if (flip_cycle) | |
530 | cur_trb->generic.field[3] ^= | |
531 | cpu_to_le32(TRB_CYCLE); | |
aa50b290 XR |
532 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
533 | "Cancel (unchain) link TRB"); | |
534 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
535 | "Address = %p (0x%llx dma); " | |
536 | "in seg %p (0x%llx dma)", | |
700e2052 | 537 | cur_trb, |
23e3be11 | 538 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
539 | cur_seg, |
540 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
541 | } else { |
542 | cur_trb->generic.field[0] = 0; | |
543 | cur_trb->generic.field[1] = 0; | |
544 | cur_trb->generic.field[2] = 0; | |
545 | /* Preserve only the cycle bit of this TRB */ | |
28ccd296 | 546 | cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); |
522989a2 SS |
547 | /* Flip the cycle bit except on the first or last TRB */ |
548 | if (flip_cycle && cur_trb != cur_td->first_trb && | |
549 | cur_trb != cur_td->last_trb) | |
550 | cur_trb->generic.field[3] ^= | |
551 | cpu_to_le32(TRB_CYCLE); | |
28ccd296 ME |
552 | cur_trb->generic.field[3] |= cpu_to_le32( |
553 | TRB_TYPE(TRB_TR_NOOP)); | |
aa50b290 XR |
554 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
555 | "TRB to noop at offset 0x%llx", | |
79688acf SS |
556 | (unsigned long long) |
557 | xhci_trb_virt_to_dma(cur_seg, cur_trb)); | |
ae636747 SS |
558 | } |
559 | if (cur_trb == cur_td->last_trb) | |
560 | break; | |
561 | } | |
562 | } | |
563 | ||
575688e1 | 564 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
565 | struct xhci_virt_ep *ep) |
566 | { | |
567 | ep->ep_state &= ~EP_HALT_PENDING; | |
568 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the | |
569 | * timer is running on another CPU, we don't decrement stop_cmds_pending | |
570 | * (since we didn't successfully stop the watchdog timer). | |
571 | */ | |
572 | if (del_timer(&ep->stop_cmd_timer)) | |
573 | ep->stop_cmds_pending--; | |
574 | } | |
575 | ||
576 | /* Must be called with xhci->lock held in interrupt context */ | |
577 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | |
07a37e9e | 578 | struct xhci_td *cur_td, int status) |
6f5165cf | 579 | { |
214f76f7 | 580 | struct usb_hcd *hcd; |
8e51adcc AX |
581 | struct urb *urb; |
582 | struct urb_priv *urb_priv; | |
6f5165cf | 583 | |
8e51adcc AX |
584 | urb = cur_td->urb; |
585 | urb_priv = urb->hcpriv; | |
586 | urb_priv->td_cnt++; | |
214f76f7 | 587 | hcd = bus_to_hcd(urb->dev->bus); |
6f5165cf | 588 | |
8e51adcc AX |
589 | /* Only giveback urb when this is the last td in urb */ |
590 | if (urb_priv->td_cnt == urb_priv->length) { | |
c41136b0 AX |
591 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
592 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
593 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
594 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
595 | usb_amd_quirk_pll_enable(); | |
596 | } | |
597 | } | |
8e51adcc | 598 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
8e51adcc AX |
599 | |
600 | spin_unlock(&xhci->lock); | |
601 | usb_hcd_giveback_urb(hcd, urb, status); | |
4daf9df5 | 602 | xhci_urb_free_priv(urb_priv); |
8e51adcc | 603 | spin_lock(&xhci->lock); |
8e51adcc | 604 | } |
6f5165cf SS |
605 | } |
606 | ||
f9c589e1 MN |
607 | void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, struct xhci_ring *ring, |
608 | struct xhci_td *td) | |
609 | { | |
610 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
611 | struct xhci_segment *seg = td->bounce_seg; | |
612 | struct urb *urb = td->urb; | |
613 | ||
614 | if (!seg || !urb) | |
615 | return; | |
616 | ||
617 | if (usb_urb_dir_out(urb)) { | |
618 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
619 | DMA_TO_DEVICE); | |
620 | return; | |
621 | } | |
622 | ||
623 | /* for in tranfers we need to copy the data from bounce to sg */ | |
624 | sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf, | |
625 | seg->bounce_len, seg->bounce_offs); | |
626 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
627 | DMA_FROM_DEVICE); | |
628 | seg->bounce_len = 0; | |
629 | seg->bounce_offs = 0; | |
630 | } | |
631 | ||
ae636747 SS |
632 | /* |
633 | * When we get a command completion for a Stop Endpoint Command, we need to | |
634 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
635 | * | |
636 | * 1. If the HW was in the middle of processing the TD that needs to be | |
637 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
638 | * in the TD with a Set Dequeue Pointer Command. | |
639 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
640 | * bit cleared) so that the HW will skip over them. | |
641 | */ | |
b8200c94 | 642 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 643 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 | 644 | { |
ae636747 SS |
645 | unsigned int ep_index; |
646 | struct xhci_ring *ep_ring; | |
63a0d9ab | 647 | struct xhci_virt_ep *ep; |
ae636747 | 648 | struct list_head *entry; |
326b4810 | 649 | struct xhci_td *cur_td = NULL; |
ae636747 SS |
650 | struct xhci_td *last_unlinked_td; |
651 | ||
c92bcfa7 | 652 | struct xhci_dequeue_state deq_state; |
ae636747 | 653 | |
bc752bde | 654 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
9ea1833e | 655 | if (!xhci->devs[slot_id]) |
be88fe4f AX |
656 | xhci_warn(xhci, "Stop endpoint command " |
657 | "completion for disabled slot %u\n", | |
658 | slot_id); | |
659 | return; | |
660 | } | |
661 | ||
ae636747 | 662 | memset(&deq_state, 0, sizeof(deq_state)); |
28ccd296 | 663 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
63a0d9ab | 664 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
ae636747 | 665 | |
678539cf | 666 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 667 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
0714a57c | 668 | ep->stopped_td = NULL; |
e9df17eb | 669 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 670 | return; |
678539cf | 671 | } |
ae636747 SS |
672 | |
673 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
674 | * We have the xHCI lock, so nothing can modify this list until we drop | |
675 | * it. We're also in the event handler, so we can't get re-interrupted | |
676 | * if another Stop Endpoint command completes | |
677 | */ | |
63a0d9ab | 678 | list_for_each(entry, &ep->cancelled_td_list) { |
ae636747 | 679 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
aa50b290 XR |
680 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
681 | "Removing canceled TD starting at 0x%llx (dma).", | |
79688acf SS |
682 | (unsigned long long)xhci_trb_virt_to_dma( |
683 | cur_td->start_seg, cur_td->first_trb)); | |
e9df17eb SS |
684 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
685 | if (!ep_ring) { | |
686 | /* This shouldn't happen unless a driver is mucking | |
687 | * with the stream ID after submission. This will | |
688 | * leave the TD on the hardware ring, and the hardware | |
689 | * will try to execute it, and may access a buffer | |
690 | * that has already been freed. In the best case, the | |
691 | * hardware will execute it, and the event handler will | |
692 | * ignore the completion event for that TD, since it was | |
693 | * removed from the td_list for that endpoint. In | |
694 | * short, don't muck with the stream ID after | |
695 | * submission. | |
696 | */ | |
697 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
698 | "has invalid stream ID %u.\n", | |
699 | cur_td->urb, | |
700 | cur_td->urb->stream_id); | |
701 | goto remove_finished_td; | |
702 | } | |
ae636747 SS |
703 | /* |
704 | * If we stopped on the TD we need to cancel, then we have to | |
705 | * move the xHC endpoint ring dequeue pointer past this TD. | |
706 | */ | |
63a0d9ab | 707 | if (cur_td == ep->stopped_td) |
e9df17eb SS |
708 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
709 | cur_td->urb->stream_id, | |
710 | cur_td, &deq_state); | |
ae636747 | 711 | else |
522989a2 | 712 | td_to_noop(xhci, ep_ring, cur_td, false); |
e9df17eb | 713 | remove_finished_td: |
ae636747 SS |
714 | /* |
715 | * The event handler won't see a completion for this TD anymore, | |
716 | * so remove it from the endpoint ring's TD list. Keep it in | |
717 | * the cancelled TD list for URB completion later. | |
718 | */ | |
585df1d9 | 719 | list_del_init(&cur_td->td_list); |
ae636747 SS |
720 | } |
721 | last_unlinked_td = cur_td; | |
6f5165cf | 722 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
723 | |
724 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
725 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
1e3452e3 HG |
726 | xhci_queue_new_dequeue_state(xhci, slot_id, ep_index, |
727 | ep->stopped_td->urb->stream_id, &deq_state); | |
ac9d8fe7 | 728 | xhci_ring_cmd_db(xhci); |
ae636747 | 729 | } else { |
e9df17eb SS |
730 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
731 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 732 | } |
526867c3 | 733 | |
d97b4f8d | 734 | ep->stopped_td = NULL; |
ae636747 SS |
735 | |
736 | /* | |
737 | * Drop the lock and complete the URBs in the cancelled TD list. | |
738 | * New TDs to be cancelled might be added to the end of the list before | |
739 | * we can complete all the URBs for the TDs we already unlinked. | |
740 | * So stop when we've completed the URB for the last TD we unlinked. | |
741 | */ | |
742 | do { | |
63a0d9ab | 743 | cur_td = list_entry(ep->cancelled_td_list.next, |
ae636747 | 744 | struct xhci_td, cancelled_td_list); |
585df1d9 | 745 | list_del_init(&cur_td->cancelled_td_list); |
ae636747 SS |
746 | |
747 | /* Clean up the cancelled URB */ | |
ae636747 SS |
748 | /* Doesn't matter what we pass for status, since the core will |
749 | * just overwrite it (because the URB has been unlinked). | |
750 | */ | |
f76a28a6 | 751 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
f9c589e1 MN |
752 | if (ep_ring && cur_td->bounce_seg) |
753 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td); | |
07a37e9e | 754 | xhci_giveback_urb_in_irq(xhci, cur_td, 0); |
ae636747 | 755 | |
6f5165cf SS |
756 | /* Stop processing the cancelled list if the watchdog timer is |
757 | * running. | |
758 | */ | |
759 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
760 | return; | |
ae636747 SS |
761 | } while (cur_td != last_unlinked_td); |
762 | ||
763 | /* Return to the event handler with xhci->lock re-acquired */ | |
764 | } | |
765 | ||
50e8725e SS |
766 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
767 | { | |
768 | struct xhci_td *cur_td; | |
769 | ||
770 | while (!list_empty(&ring->td_list)) { | |
771 | cur_td = list_first_entry(&ring->td_list, | |
772 | struct xhci_td, td_list); | |
773 | list_del_init(&cur_td->td_list); | |
774 | if (!list_empty(&cur_td->cancelled_td_list)) | |
775 | list_del_init(&cur_td->cancelled_td_list); | |
f9c589e1 MN |
776 | |
777 | if (cur_td->bounce_seg) | |
778 | xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); | |
50e8725e SS |
779 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); |
780 | } | |
781 | } | |
782 | ||
783 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, | |
784 | int slot_id, int ep_index) | |
785 | { | |
786 | struct xhci_td *cur_td; | |
787 | struct xhci_virt_ep *ep; | |
788 | struct xhci_ring *ring; | |
789 | ||
790 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
21d0e51b SS |
791 | if ((ep->ep_state & EP_HAS_STREAMS) || |
792 | (ep->ep_state & EP_GETTING_NO_STREAMS)) { | |
793 | int stream_id; | |
794 | ||
795 | for (stream_id = 0; stream_id < ep->stream_info->num_streams; | |
796 | stream_id++) { | |
797 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
798 | "Killing URBs for slot ID %u, ep index %u, stream %u", | |
799 | slot_id, ep_index, stream_id + 1); | |
800 | xhci_kill_ring_urbs(xhci, | |
801 | ep->stream_info->stream_rings[stream_id]); | |
802 | } | |
803 | } else { | |
804 | ring = ep->ring; | |
805 | if (!ring) | |
806 | return; | |
807 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
808 | "Killing URBs for slot ID %u, ep index %u", | |
809 | slot_id, ep_index); | |
810 | xhci_kill_ring_urbs(xhci, ring); | |
811 | } | |
50e8725e SS |
812 | while (!list_empty(&ep->cancelled_td_list)) { |
813 | cur_td = list_first_entry(&ep->cancelled_td_list, | |
814 | struct xhci_td, cancelled_td_list); | |
815 | list_del_init(&cur_td->cancelled_td_list); | |
816 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
817 | } | |
818 | } | |
819 | ||
6f5165cf SS |
820 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
821 | * In this case, we assume the host controller is broken or dying or dead. The | |
822 | * host may still be completing some other events, so we have to be careful to | |
823 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
824 | * through xhci->state. | |
825 | * | |
826 | * The timer may also fire if the host takes a very long time to respond to the | |
827 | * command, and the stop endpoint command completion handler cannot delete the | |
828 | * timer before the timer function is called. Another endpoint cancellation may | |
829 | * sneak in before the timer function can grab the lock, and that may queue | |
830 | * another stop endpoint command and add the timer back. So we cannot use a | |
831 | * simple flag to say whether there is a pending stop endpoint command for a | |
832 | * particular endpoint. | |
833 | * | |
834 | * Instead we use a combination of that flag and a counter for the number of | |
835 | * pending stop endpoint commands. If the timer is the tail end of the last | |
836 | * stop endpoint command, and the endpoint's command is still pending, we assume | |
837 | * the host is dying. | |
838 | */ | |
839 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
840 | { | |
841 | struct xhci_hcd *xhci; | |
842 | struct xhci_virt_ep *ep; | |
6f5165cf | 843 | int ret, i, j; |
f43d6231 | 844 | unsigned long flags; |
6f5165cf SS |
845 | |
846 | ep = (struct xhci_virt_ep *) arg; | |
847 | xhci = ep->xhci; | |
848 | ||
f43d6231 | 849 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
850 | |
851 | ep->stop_cmds_pending--; | |
bcf42aa6 MN |
852 | if (xhci->xhc_state & XHCI_STATE_REMOVING) { |
853 | spin_unlock_irqrestore(&xhci->lock, flags); | |
854 | return; | |
855 | } | |
6f5165cf | 856 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
aa50b290 XR |
857 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
858 | "Stop EP timer ran, but another timer marked " | |
859 | "xHCI as DYING, exiting."); | |
f43d6231 | 860 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
861 | return; |
862 | } | |
863 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { | |
aa50b290 XR |
864 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
865 | "Stop EP timer ran, but no command pending, " | |
866 | "exiting."); | |
f43d6231 | 867 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
868 | return; |
869 | } | |
870 | ||
871 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
872 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
873 | /* Oops, HC is dead or dying or at least not responding to the stop | |
874 | * endpoint command. | |
875 | */ | |
876 | xhci->xhc_state |= XHCI_STATE_DYING; | |
877 | /* Disable interrupts from the host controller and start halting it */ | |
878 | xhci_quiesce(xhci); | |
f43d6231 | 879 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
880 | |
881 | ret = xhci_halt(xhci); | |
882 | ||
f43d6231 | 883 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
884 | if (ret < 0) { |
885 | /* This is bad; the host is not responding to commands and it's | |
886 | * not allowing itself to be halted. At least interrupts are | |
ac04e6ff | 887 | * disabled. If we call usb_hc_died(), it will attempt to |
6f5165cf SS |
888 | * disconnect all device drivers under this host. Those |
889 | * disconnect() methods will wait for all URBs to be unlinked, | |
890 | * so we must complete them. | |
891 | */ | |
892 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
893 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
894 | /* We could turn all TDs on the rings to no-ops. This won't | |
895 | * help if the host has cached part of the ring, and is slow if | |
896 | * we want to preserve the cycle bit. Skip it and hope the host | |
897 | * doesn't touch the memory. | |
898 | */ | |
899 | } | |
900 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
901 | if (!xhci->devs[i]) | |
902 | continue; | |
50e8725e SS |
903 | for (j = 0; j < 31; j++) |
904 | xhci_kill_endpoint_urbs(xhci, i, j); | |
6f5165cf | 905 | } |
f43d6231 | 906 | spin_unlock_irqrestore(&xhci->lock, flags); |
aa50b290 XR |
907 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
908 | "Calling usb_hc_died()"); | |
bcf42aa6 | 909 | usb_hc_died(xhci_to_hcd(xhci)); |
aa50b290 XR |
910 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
911 | "xHCI host controller is dead."); | |
6f5165cf SS |
912 | } |
913 | ||
b008df60 AX |
914 | |
915 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, | |
916 | struct xhci_virt_device *dev, | |
917 | struct xhci_ring *ep_ring, | |
918 | unsigned int ep_index) | |
919 | { | |
920 | union xhci_trb *dequeue_temp; | |
921 | int num_trbs_free_temp; | |
922 | bool revert = false; | |
923 | ||
924 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
925 | dequeue_temp = ep_ring->dequeue; | |
926 | ||
0d9f78a9 SS |
927 | /* If we get two back-to-back stalls, and the first stalled transfer |
928 | * ends just before a link TRB, the dequeue pointer will be left on | |
929 | * the link TRB by the code in the while loop. So we have to update | |
930 | * the dequeue pointer one segment further, or we'll jump off | |
931 | * the segment into la-la-land. | |
932 | */ | |
2d98ef40 | 933 | if (trb_is_link(ep_ring->dequeue)) { |
0d9f78a9 SS |
934 | ep_ring->deq_seg = ep_ring->deq_seg->next; |
935 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
936 | } | |
937 | ||
b008df60 AX |
938 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
939 | /* We have more usable TRBs */ | |
940 | ep_ring->num_trbs_free++; | |
941 | ep_ring->dequeue++; | |
2d98ef40 | 942 | if (trb_is_link(ep_ring->dequeue)) { |
b008df60 AX |
943 | if (ep_ring->dequeue == |
944 | dev->eps[ep_index].queued_deq_ptr) | |
945 | break; | |
946 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
947 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
948 | } | |
949 | if (ep_ring->dequeue == dequeue_temp) { | |
950 | revert = true; | |
951 | break; | |
952 | } | |
953 | } | |
954 | ||
955 | if (revert) { | |
956 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
957 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
958 | } | |
959 | } | |
960 | ||
ae636747 SS |
961 | /* |
962 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
963 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
964 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
965 | * endpoint doorbell to restart the ring, but only if there aren't more | |
966 | * cancellations pending. | |
967 | */ | |
b8200c94 | 968 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 969 | union xhci_trb *trb, u32 cmd_comp_code) |
ae636747 | 970 | { |
ae636747 | 971 | unsigned int ep_index; |
e9df17eb | 972 | unsigned int stream_id; |
ae636747 SS |
973 | struct xhci_ring *ep_ring; |
974 | struct xhci_virt_device *dev; | |
9aad95e2 | 975 | struct xhci_virt_ep *ep; |
d115b048 JY |
976 | struct xhci_ep_ctx *ep_ctx; |
977 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 | 978 | |
28ccd296 ME |
979 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
980 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
ae636747 | 981 | dev = xhci->devs[slot_id]; |
9aad95e2 | 982 | ep = &dev->eps[ep_index]; |
e9df17eb SS |
983 | |
984 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
985 | if (!ep_ring) { | |
e587b8b2 | 986 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
e9df17eb SS |
987 | stream_id); |
988 | /* XXX: Harmless??? */ | |
0d4976ec | 989 | goto cleanup; |
e9df17eb SS |
990 | } |
991 | ||
d115b048 JY |
992 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
993 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
ae636747 | 994 | |
c69a0597 | 995 | if (cmd_comp_code != COMP_SUCCESS) { |
ae636747 SS |
996 | unsigned int ep_state; |
997 | unsigned int slot_state; | |
998 | ||
c69a0597 | 999 | switch (cmd_comp_code) { |
ae636747 | 1000 | case COMP_TRB_ERR: |
e587b8b2 | 1001 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
ae636747 SS |
1002 | break; |
1003 | case COMP_CTX_STATE: | |
e587b8b2 | 1004 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
28ccd296 | 1005 | ep_state = le32_to_cpu(ep_ctx->ep_info); |
ae636747 | 1006 | ep_state &= EP_STATE_MASK; |
28ccd296 | 1007 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 | 1008 | slot_state = GET_SLOT_STATE(slot_state); |
aa50b290 XR |
1009 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1010 | "Slot state = %u, EP state = %u", | |
ae636747 SS |
1011 | slot_state, ep_state); |
1012 | break; | |
1013 | case COMP_EBADSLT: | |
e587b8b2 ON |
1014 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
1015 | slot_id); | |
ae636747 SS |
1016 | break; |
1017 | default: | |
e587b8b2 ON |
1018 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
1019 | cmd_comp_code); | |
ae636747 SS |
1020 | break; |
1021 | } | |
1022 | /* OK what do we do now? The endpoint state is hosed, and we | |
1023 | * should never get to this point if the synchronization between | |
1024 | * queueing, and endpoint state are correct. This might happen | |
1025 | * if the device gets disconnected after we've finished | |
1026 | * cancelling URBs, which might not be an error... | |
1027 | */ | |
1028 | } else { | |
9aad95e2 HG |
1029 | u64 deq; |
1030 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ | |
1031 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1032 | struct xhci_stream_ctx *ctx = | |
1033 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1034 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; | |
1035 | } else { | |
1036 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; | |
1037 | } | |
aa50b290 | 1038 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
9aad95e2 HG |
1039 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
1040 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, | |
1041 | ep->queued_deq_ptr) == deq) { | |
bf161e85 SS |
1042 | /* Update the ring's dequeue segment and dequeue pointer |
1043 | * to reflect the new position. | |
1044 | */ | |
b008df60 AX |
1045 | update_ring_for_set_deq_completion(xhci, dev, |
1046 | ep_ring, ep_index); | |
bf161e85 | 1047 | } else { |
e587b8b2 | 1048 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
bf161e85 | 1049 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
9aad95e2 | 1050 | ep->queued_deq_seg, ep->queued_deq_ptr); |
bf161e85 | 1051 | } |
ae636747 SS |
1052 | } |
1053 | ||
0d4976ec | 1054 | cleanup: |
63a0d9ab | 1055 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
bf161e85 SS |
1056 | dev->eps[ep_index].queued_deq_seg = NULL; |
1057 | dev->eps[ep_index].queued_deq_ptr = NULL; | |
e9df17eb SS |
1058 | /* Restart any rings with pending URBs */ |
1059 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1060 | } |
1061 | ||
b8200c94 | 1062 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1063 | union xhci_trb *trb, u32 cmd_comp_code) |
a1587d97 | 1064 | { |
a1587d97 SS |
1065 | unsigned int ep_index; |
1066 | ||
28ccd296 | 1067 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
a1587d97 SS |
1068 | /* This command will only fail if the endpoint wasn't halted, |
1069 | * but we don't care. | |
1070 | */ | |
a0254324 | 1071 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
c69a0597 | 1072 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
a1587d97 | 1073 | |
ac9d8fe7 SS |
1074 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
1075 | * command complete before the endpoint can be used. Queue that here | |
1076 | * because the HW can't handle two commands being queued in a row. | |
1077 | */ | |
1078 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
ddba5cd0 MN |
1079 | struct xhci_command *command; |
1080 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
a0ee619f HG |
1081 | if (!command) { |
1082 | xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n"); | |
1083 | return; | |
1084 | } | |
4bdfe4c3 XR |
1085 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1086 | "Queueing configure endpoint command"); | |
ddba5cd0 | 1087 | xhci_queue_configure_endpoint(xhci, command, |
913a8a34 SS |
1088 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
1089 | false); | |
ac9d8fe7 SS |
1090 | xhci_ring_cmd_db(xhci); |
1091 | } else { | |
c3492dbf | 1092 | /* Clear our internal halted state */ |
63a0d9ab | 1093 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
ac9d8fe7 | 1094 | } |
a1587d97 | 1095 | } |
ae636747 | 1096 | |
b244b431 XR |
1097 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
1098 | u32 cmd_comp_code) | |
1099 | { | |
1100 | if (cmd_comp_code == COMP_SUCCESS) | |
1101 | xhci->slot_id = slot_id; | |
1102 | else | |
1103 | xhci->slot_id = 0; | |
b244b431 XR |
1104 | } |
1105 | ||
6c02dd14 XR |
1106 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
1107 | { | |
1108 | struct xhci_virt_device *virt_dev; | |
1109 | ||
1110 | virt_dev = xhci->devs[slot_id]; | |
1111 | if (!virt_dev) | |
1112 | return; | |
1113 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) | |
1114 | /* Delete default control endpoint resources */ | |
1115 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); | |
1116 | xhci_free_virt_device(xhci, slot_id); | |
1117 | } | |
1118 | ||
6ed46d33 XR |
1119 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
1120 | struct xhci_event_cmd *event, u32 cmd_comp_code) | |
1121 | { | |
1122 | struct xhci_virt_device *virt_dev; | |
1123 | struct xhci_input_control_ctx *ctrl_ctx; | |
1124 | unsigned int ep_index; | |
1125 | unsigned int ep_state; | |
1126 | u32 add_flags, drop_flags; | |
1127 | ||
6ed46d33 XR |
1128 | /* |
1129 | * Configure endpoint commands can come from the USB core | |
1130 | * configuration or alt setting changes, or because the HW | |
1131 | * needed an extra configure endpoint command after a reset | |
1132 | * endpoint command or streams were being configured. | |
1133 | * If the command was for a halted endpoint, the xHCI driver | |
1134 | * is not waiting on the configure endpoint command. | |
1135 | */ | |
9ea1833e | 1136 | virt_dev = xhci->devs[slot_id]; |
4daf9df5 | 1137 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
6ed46d33 XR |
1138 | if (!ctrl_ctx) { |
1139 | xhci_warn(xhci, "Could not get input context, bad type.\n"); | |
1140 | return; | |
1141 | } | |
1142 | ||
1143 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
1144 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
1145 | /* Input ctx add_flags are the endpoint index plus one */ | |
1146 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; | |
1147 | ||
1148 | /* A usb_set_interface() call directly after clearing a halted | |
1149 | * condition may race on this quirky hardware. Not worth | |
1150 | * worrying about, since this is prototype hardware. Not sure | |
1151 | * if this will work for streams, but streams support was | |
1152 | * untested on this prototype. | |
1153 | */ | |
1154 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
1155 | ep_index != (unsigned int) -1 && | |
1156 | add_flags - SLOT_FLAG == drop_flags) { | |
1157 | ep_state = virt_dev->eps[ep_index].ep_state; | |
1158 | if (!(ep_state & EP_HALTED)) | |
ddba5cd0 | 1159 | return; |
6ed46d33 XR |
1160 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1161 | "Completed config ep cmd - " | |
1162 | "last ep index = %d, state = %d", | |
1163 | ep_index, ep_state); | |
1164 | /* Clear internal halted state and restart ring(s) */ | |
1165 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; | |
1166 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
1167 | return; | |
1168 | } | |
6ed46d33 XR |
1169 | return; |
1170 | } | |
1171 | ||
f681321b XR |
1172 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, |
1173 | struct xhci_event_cmd *event) | |
1174 | { | |
f681321b | 1175 | xhci_dbg(xhci, "Completed reset device command.\n"); |
9ea1833e | 1176 | if (!xhci->devs[slot_id]) |
f681321b XR |
1177 | xhci_warn(xhci, "Reset device command completion " |
1178 | "for disabled slot %u\n", slot_id); | |
1179 | } | |
1180 | ||
2c070821 XR |
1181 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
1182 | struct xhci_event_cmd *event) | |
1183 | { | |
1184 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
1185 | xhci->error_bitmask |= 1 << 6; | |
1186 | return; | |
1187 | } | |
1188 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1189 | "NEC firmware version %2x.%02x", | |
1190 | NEC_FW_MAJOR(le32_to_cpu(event->status)), | |
1191 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
1192 | } | |
1193 | ||
9ea1833e | 1194 | static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) |
c9aa1a2d MN |
1195 | { |
1196 | list_del(&cmd->cmd_list); | |
9ea1833e MN |
1197 | |
1198 | if (cmd->completion) { | |
1199 | cmd->status = status; | |
1200 | complete(cmd->completion); | |
1201 | } else { | |
c9aa1a2d | 1202 | kfree(cmd); |
9ea1833e | 1203 | } |
c9aa1a2d MN |
1204 | } |
1205 | ||
1206 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci) | |
1207 | { | |
1208 | struct xhci_command *cur_cmd, *tmp_cmd; | |
1209 | list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) | |
9ea1833e | 1210 | xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT); |
c9aa1a2d MN |
1211 | } |
1212 | ||
c311e391 MN |
1213 | /* |
1214 | * Turn all commands on command ring with status set to "aborted" to no-op trbs. | |
1215 | * If there are other commands waiting then restart the ring and kick the timer. | |
1216 | * This must be called with command ring stopped and xhci->lock held. | |
1217 | */ | |
1218 | static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, | |
1219 | struct xhci_command *cur_cmd) | |
1220 | { | |
1221 | struct xhci_command *i_cmd, *tmp_cmd; | |
1222 | u32 cycle_state; | |
1223 | ||
1224 | /* Turn all aborted commands in list to no-ops, then restart */ | |
1225 | list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list, | |
1226 | cmd_list) { | |
1227 | ||
1228 | if (i_cmd->status != COMP_CMD_ABORT) | |
1229 | continue; | |
1230 | ||
1231 | i_cmd->status = COMP_CMD_STOP; | |
1232 | ||
1233 | xhci_dbg(xhci, "Turn aborted command %p to no-op\n", | |
1234 | i_cmd->command_trb); | |
1235 | /* get cycle state from the original cmd trb */ | |
1236 | cycle_state = le32_to_cpu( | |
1237 | i_cmd->command_trb->generic.field[3]) & TRB_CYCLE; | |
1238 | /* modify the command trb to no-op command */ | |
1239 | i_cmd->command_trb->generic.field[0] = 0; | |
1240 | i_cmd->command_trb->generic.field[1] = 0; | |
1241 | i_cmd->command_trb->generic.field[2] = 0; | |
1242 | i_cmd->command_trb->generic.field[3] = cpu_to_le32( | |
1243 | TRB_TYPE(TRB_CMD_NOOP) | cycle_state); | |
1244 | ||
1245 | /* | |
1246 | * caller waiting for completion is called when command | |
1247 | * completion event is received for these no-op commands | |
1248 | */ | |
1249 | } | |
1250 | ||
1251 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; | |
1252 | ||
1253 | /* ring command ring doorbell to restart the command ring */ | |
1254 | if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && | |
1255 | !(xhci->xhc_state & XHCI_STATE_DYING)) { | |
1256 | xhci->current_cmd = cur_cmd; | |
1257 | mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT); | |
1258 | xhci_ring_cmd_db(xhci); | |
1259 | } | |
1260 | return; | |
1261 | } | |
1262 | ||
1263 | ||
1264 | void xhci_handle_command_timeout(unsigned long data) | |
1265 | { | |
1266 | struct xhci_hcd *xhci; | |
1267 | int ret; | |
1268 | unsigned long flags; | |
1269 | u64 hw_ring_state; | |
3425aa03 | 1270 | bool second_timeout = false; |
c311e391 MN |
1271 | xhci = (struct xhci_hcd *) data; |
1272 | ||
1273 | /* mark this command to be cancelled */ | |
1274 | spin_lock_irqsave(&xhci->lock, flags); | |
1275 | if (xhci->current_cmd) { | |
3425aa03 MN |
1276 | if (xhci->current_cmd->status == COMP_CMD_ABORT) |
1277 | second_timeout = true; | |
1278 | xhci->current_cmd->status = COMP_CMD_ABORT; | |
c311e391 MN |
1279 | } |
1280 | ||
c311e391 MN |
1281 | /* Make sure command ring is running before aborting it */ |
1282 | hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | |
1283 | if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && | |
1284 | (hw_ring_state & CMD_RING_RUNNING)) { | |
c311e391 MN |
1285 | spin_unlock_irqrestore(&xhci->lock, flags); |
1286 | xhci_dbg(xhci, "Command timeout\n"); | |
1287 | ret = xhci_abort_cmd_ring(xhci); | |
1288 | if (unlikely(ret == -ESHUTDOWN)) { | |
1289 | xhci_err(xhci, "Abort command ring failed\n"); | |
1290 | xhci_cleanup_command_queue(xhci); | |
1291 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); | |
1292 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); | |
1293 | } | |
1294 | return; | |
1295 | } | |
3425aa03 MN |
1296 | |
1297 | /* command ring failed to restart, or host removed. Bail out */ | |
1298 | if (second_timeout || xhci->xhc_state & XHCI_STATE_REMOVING) { | |
1299 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1300 | xhci_dbg(xhci, "command timed out twice, ring start fail?\n"); | |
1301 | xhci_cleanup_command_queue(xhci); | |
1302 | return; | |
1303 | } | |
1304 | ||
c311e391 MN |
1305 | /* command timeout on stopped ring, ring can't be aborted */ |
1306 | xhci_dbg(xhci, "Command timeout on stopped ring\n"); | |
1307 | xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); | |
1308 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1309 | return; | |
1310 | } | |
1311 | ||
7f84eef0 SS |
1312 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1313 | struct xhci_event_cmd *event) | |
1314 | { | |
28ccd296 | 1315 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1316 | u64 cmd_dma; |
1317 | dma_addr_t cmd_dequeue_dma; | |
e7a79a1d | 1318 | u32 cmd_comp_code; |
9124b121 | 1319 | union xhci_trb *cmd_trb; |
c9aa1a2d | 1320 | struct xhci_command *cmd; |
b54fc46d | 1321 | u32 cmd_type; |
7f84eef0 | 1322 | |
28ccd296 | 1323 | cmd_dma = le64_to_cpu(event->cmd_trb); |
9124b121 | 1324 | cmd_trb = xhci->cmd_ring->dequeue; |
23e3be11 | 1325 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
9124b121 | 1326 | cmd_trb); |
7f84eef0 SS |
1327 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ |
1328 | if (cmd_dequeue_dma == 0) { | |
1329 | xhci->error_bitmask |= 1 << 4; | |
1330 | return; | |
1331 | } | |
1332 | /* Does the DMA address match our internal dequeue pointer address? */ | |
1333 | if (cmd_dma != (u64) cmd_dequeue_dma) { | |
1334 | xhci->error_bitmask |= 1 << 5; | |
1335 | return; | |
1336 | } | |
b63f4053 | 1337 | |
c9aa1a2d MN |
1338 | cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list); |
1339 | ||
c311e391 MN |
1340 | del_timer(&xhci->cmd_timer); |
1341 | ||
9124b121 | 1342 | trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event); |
63a23b9a | 1343 | |
e7a79a1d | 1344 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
c311e391 MN |
1345 | |
1346 | /* If CMD ring stopped we own the trbs between enqueue and dequeue */ | |
1347 | if (cmd_comp_code == COMP_CMD_STOP) { | |
1348 | xhci_handle_stopped_cmd_ring(xhci, cmd); | |
1349 | return; | |
1350 | } | |
33be1265 MN |
1351 | |
1352 | if (cmd->command_trb != xhci->cmd_ring->dequeue) { | |
1353 | xhci_err(xhci, | |
1354 | "Command completion event does not match command\n"); | |
1355 | return; | |
1356 | } | |
1357 | ||
c311e391 MN |
1358 | /* |
1359 | * Host aborted the command ring, check if the current command was | |
1360 | * supposed to be aborted, otherwise continue normally. | |
1361 | * The command ring is stopped now, but the xHC will issue a Command | |
1362 | * Ring Stopped event which will cause us to restart it. | |
1363 | */ | |
1364 | if (cmd_comp_code == COMP_CMD_ABORT) { | |
1365 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
1366 | if (cmd->status == COMP_CMD_ABORT) | |
1367 | goto event_handled; | |
b63f4053 EF |
1368 | } |
1369 | ||
b54fc46d XR |
1370 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
1371 | switch (cmd_type) { | |
1372 | case TRB_ENABLE_SLOT: | |
e7a79a1d | 1373 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code); |
3ffbba95 | 1374 | break; |
b54fc46d | 1375 | case TRB_DISABLE_SLOT: |
6c02dd14 | 1376 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
3ffbba95 | 1377 | break; |
b54fc46d | 1378 | case TRB_CONFIG_EP: |
9ea1833e MN |
1379 | if (!cmd->completion) |
1380 | xhci_handle_cmd_config_ep(xhci, slot_id, event, | |
1381 | cmd_comp_code); | |
f94e0186 | 1382 | break; |
b54fc46d | 1383 | case TRB_EVAL_CONTEXT: |
2d3f1fac | 1384 | break; |
b54fc46d | 1385 | case TRB_ADDR_DEV: |
3ffbba95 | 1386 | break; |
b54fc46d | 1387 | case TRB_STOP_RING: |
b8200c94 XR |
1388 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1389 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
1390 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); | |
ae636747 | 1391 | break; |
b54fc46d | 1392 | case TRB_SET_DEQ: |
b8200c94 XR |
1393 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1394 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1395 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
ae636747 | 1396 | break; |
b54fc46d | 1397 | case TRB_CMD_NOOP: |
c311e391 MN |
1398 | /* Is this an aborted command turned to NO-OP? */ |
1399 | if (cmd->status == COMP_CMD_STOP) | |
1400 | cmd_comp_code = COMP_CMD_STOP; | |
7f84eef0 | 1401 | break; |
b54fc46d | 1402 | case TRB_RESET_EP: |
b8200c94 XR |
1403 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1404 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1405 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
a1587d97 | 1406 | break; |
b54fc46d | 1407 | case TRB_RESET_DEV: |
6fcfb0d6 MN |
1408 | /* SLOT_ID field in reset device cmd completion event TRB is 0. |
1409 | * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) | |
1410 | */ | |
1411 | slot_id = TRB_TO_SLOT_ID( | |
1412 | le32_to_cpu(cmd_trb->generic.field[3])); | |
f681321b | 1413 | xhci_handle_cmd_reset_dev(xhci, slot_id, event); |
2a8f82c4 | 1414 | break; |
b54fc46d | 1415 | case TRB_NEC_GET_FW: |
2c070821 | 1416 | xhci_handle_cmd_nec_get_fw(xhci, event); |
0238634d | 1417 | break; |
7f84eef0 SS |
1418 | default: |
1419 | /* Skip over unknown commands on the event ring */ | |
1420 | xhci->error_bitmask |= 1 << 6; | |
1421 | break; | |
1422 | } | |
c9aa1a2d | 1423 | |
c311e391 MN |
1424 | /* restart timer if this wasn't the last command */ |
1425 | if (cmd->cmd_list.next != &xhci->cmd_list) { | |
1426 | xhci->current_cmd = list_entry(cmd->cmd_list.next, | |
1427 | struct xhci_command, cmd_list); | |
1428 | mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT); | |
1429 | } | |
1430 | ||
1431 | event_handled: | |
9ea1833e | 1432 | xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); |
c9aa1a2d | 1433 | |
3b72fca0 | 1434 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1435 | } |
1436 | ||
0238634d SS |
1437 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1438 | union xhci_trb *event) | |
1439 | { | |
1440 | u32 trb_type; | |
1441 | ||
28ccd296 | 1442 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
0238634d SS |
1443 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1444 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1445 | handle_cmd_completion(xhci, &event->event_cmd); | |
1446 | } | |
1447 | ||
f6ff0ac8 SS |
1448 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
1449 | * port registers -- USB 3.0 and USB 2.0). | |
1450 | * | |
1451 | * Returns a zero-based port number, which is suitable for indexing into each of | |
1452 | * the split roothubs' port arrays and bus state arrays. | |
d0cd5d48 | 1453 | * Add one to it in order to call xhci_find_slot_id_by_port. |
f6ff0ac8 SS |
1454 | */ |
1455 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, | |
1456 | struct xhci_hcd *xhci, u32 port_id) | |
1457 | { | |
1458 | unsigned int i; | |
1459 | unsigned int num_similar_speed_ports = 0; | |
1460 | ||
1461 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], | |
1462 | * and usb2_ports are 0-based indexes. Count the number of similar | |
1463 | * speed ports, up to 1 port before this port. | |
1464 | */ | |
1465 | for (i = 0; i < (port_id - 1); i++) { | |
1466 | u8 port_speed = xhci->port_array[i]; | |
1467 | ||
1468 | /* | |
1469 | * Skip ports that don't have known speeds, or have duplicate | |
1470 | * Extended Capabilities port speed entries. | |
1471 | */ | |
22e04870 | 1472 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
1473 | continue; |
1474 | ||
1475 | /* | |
1476 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
1477 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
1478 | * matches the device speed, it's a similar speed port. | |
1479 | */ | |
b50107bb | 1480 | if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3)) |
f6ff0ac8 SS |
1481 | num_similar_speed_ports++; |
1482 | } | |
1483 | return num_similar_speed_ports; | |
1484 | } | |
1485 | ||
623bef9e SS |
1486 | static void handle_device_notification(struct xhci_hcd *xhci, |
1487 | union xhci_trb *event) | |
1488 | { | |
1489 | u32 slot_id; | |
4ee823b8 | 1490 | struct usb_device *udev; |
623bef9e | 1491 | |
7e76ad43 | 1492 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
4ee823b8 | 1493 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1494 | xhci_warn(xhci, "Device Notification event for " |
1495 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1496 | return; |
1497 | } | |
1498 | ||
1499 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1500 | slot_id); | |
1501 | udev = xhci->devs[slot_id]->udev; | |
1502 | if (udev && udev->parent) | |
1503 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1504 | } |
1505 | ||
0f2a7930 SS |
1506 | static void handle_port_status(struct xhci_hcd *xhci, |
1507 | union xhci_trb *event) | |
1508 | { | |
f6ff0ac8 | 1509 | struct usb_hcd *hcd; |
0f2a7930 | 1510 | u32 port_id; |
56192531 | 1511 | u32 temp, temp1; |
518e848e | 1512 | int max_ports; |
56192531 | 1513 | int slot_id; |
5308a91b | 1514 | unsigned int faked_port_index; |
f6ff0ac8 | 1515 | u8 major_revision; |
20b67cf5 | 1516 | struct xhci_bus_state *bus_state; |
28ccd296 | 1517 | __le32 __iomem **port_array; |
386139d7 | 1518 | bool bogus_port_status = false; |
0f2a7930 SS |
1519 | |
1520 | /* Port status change events always have a successful completion code */ | |
28ccd296 | 1521 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) { |
0f2a7930 SS |
1522 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); |
1523 | xhci->error_bitmask |= 1 << 8; | |
1524 | } | |
28ccd296 | 1525 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
0f2a7930 SS |
1526 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
1527 | ||
518e848e SS |
1528 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1529 | if ((port_id <= 0) || (port_id > max_ports)) { | |
56192531 | 1530 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
09ce0c0c PC |
1531 | inc_deq(xhci, xhci->event_ring); |
1532 | return; | |
56192531 AX |
1533 | } |
1534 | ||
f6ff0ac8 SS |
1535 | /* Figure out which usb_hcd this port is attached to: |
1536 | * is it a USB 3.0 port or a USB 2.0/1.1 port? | |
1537 | */ | |
1538 | major_revision = xhci->port_array[port_id - 1]; | |
09ce0c0c PC |
1539 | |
1540 | /* Find the right roothub. */ | |
1541 | hcd = xhci_to_hcd(xhci); | |
b50107bb | 1542 | if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3)) |
09ce0c0c PC |
1543 | hcd = xhci->shared_hcd; |
1544 | ||
f6ff0ac8 SS |
1545 | if (major_revision == 0) { |
1546 | xhci_warn(xhci, "Event for port %u not in " | |
1547 | "Extended Capabilities, ignoring.\n", | |
1548 | port_id); | |
386139d7 | 1549 | bogus_port_status = true; |
f6ff0ac8 | 1550 | goto cleanup; |
5308a91b | 1551 | } |
22e04870 | 1552 | if (major_revision == DUPLICATE_ENTRY) { |
f6ff0ac8 SS |
1553 | xhci_warn(xhci, "Event for port %u duplicated in" |
1554 | "Extended Capabilities, ignoring.\n", | |
1555 | port_id); | |
386139d7 | 1556 | bogus_port_status = true; |
f6ff0ac8 SS |
1557 | goto cleanup; |
1558 | } | |
1559 | ||
1560 | /* | |
1561 | * Hardware port IDs reported by a Port Status Change Event include USB | |
1562 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a | |
1563 | * resume event, but we first need to translate the hardware port ID | |
1564 | * into the index into the ports on the correct split roothub, and the | |
1565 | * correct bus_state structure. | |
1566 | */ | |
f6ff0ac8 | 1567 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
b50107bb | 1568 | if (hcd->speed >= HCD_USB3) |
f6ff0ac8 SS |
1569 | port_array = xhci->usb3_ports; |
1570 | else | |
1571 | port_array = xhci->usb2_ports; | |
1572 | /* Find the faked port hub number */ | |
1573 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, | |
1574 | port_id); | |
5308a91b | 1575 | |
b0ba9720 | 1576 | temp = readl(port_array[faked_port_index]); |
7111ebc9 | 1577 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1578 | xhci_dbg(xhci, "resume root hub\n"); |
1579 | usb_hcd_resume_root_hub(hcd); | |
1580 | } | |
1581 | ||
b50107bb | 1582 | if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE) |
fac4271d ZJC |
1583 | bus_state->port_remote_wakeup &= ~(1 << faked_port_index); |
1584 | ||
56192531 AX |
1585 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { |
1586 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | |
1587 | ||
b0ba9720 | 1588 | temp1 = readl(&xhci->op_regs->command); |
56192531 AX |
1589 | if (!(temp1 & CMD_RUN)) { |
1590 | xhci_warn(xhci, "xHC is not running.\n"); | |
1591 | goto cleanup; | |
1592 | } | |
1593 | ||
2338b9e4 | 1594 | if (DEV_SUPERSPEED_ANY(temp)) { |
d93814cf | 1595 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1596 | /* Set a flag to say the port signaled remote wakeup, |
1597 | * so we can tell the difference between the end of | |
1598 | * device and host initiated resume. | |
1599 | */ | |
1600 | bus_state->port_remote_wakeup |= 1 << faked_port_index; | |
d93814cf SS |
1601 | xhci_test_and_clear_bit(xhci, port_array, |
1602 | faked_port_index, PORT_PLC); | |
c9682dff AX |
1603 | xhci_set_link_state(xhci, port_array, faked_port_index, |
1604 | XDEV_U0); | |
d93814cf SS |
1605 | /* Need to wait until the next link state change |
1606 | * indicates the device is actually in U0. | |
1607 | */ | |
1608 | bogus_port_status = true; | |
1609 | goto cleanup; | |
f69115fd MN |
1610 | } else if (!test_bit(faked_port_index, |
1611 | &bus_state->resuming_ports)) { | |
56192531 | 1612 | xhci_dbg(xhci, "resume HS port %d\n", port_id); |
f6ff0ac8 | 1613 | bus_state->resume_done[faked_port_index] = jiffies + |
b9e45188 | 1614 | msecs_to_jiffies(USB_RESUME_TIMEOUT); |
f370b996 | 1615 | set_bit(faked_port_index, &bus_state->resuming_ports); |
56192531 | 1616 | mod_timer(&hcd->rh_timer, |
f6ff0ac8 | 1617 | bus_state->resume_done[faked_port_index]); |
56192531 AX |
1618 | /* Do the rest in GetPortStatus */ |
1619 | } | |
1620 | } | |
d93814cf SS |
1621 | |
1622 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && | |
2338b9e4 | 1623 | DEV_SUPERSPEED_ANY(temp)) { |
d93814cf | 1624 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); |
4ee823b8 SS |
1625 | /* We've just brought the device into U0 through either the |
1626 | * Resume state after a device remote wakeup, or through the | |
1627 | * U3Exit state after a host-initiated resume. If it's a device | |
1628 | * initiated remote wake, don't pass up the link state change, | |
1629 | * so the roothub behavior is consistent with external | |
1630 | * USB 3.0 hub behavior. | |
1631 | */ | |
d93814cf SS |
1632 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1633 | faked_port_index + 1); | |
1634 | if (slot_id && xhci->devs[slot_id]) | |
1635 | xhci_ring_device(xhci, slot_id); | |
ba7b5c22 | 1636 | if (bus_state->port_remote_wakeup & (1 << faked_port_index)) { |
4ee823b8 SS |
1637 | bus_state->port_remote_wakeup &= |
1638 | ~(1 << faked_port_index); | |
1639 | xhci_test_and_clear_bit(xhci, port_array, | |
1640 | faked_port_index, PORT_PLC); | |
1641 | usb_wakeup_notification(hcd->self.root_hub, | |
1642 | faked_port_index + 1); | |
1643 | bogus_port_status = true; | |
1644 | goto cleanup; | |
1645 | } | |
d93814cf | 1646 | } |
56192531 | 1647 | |
8b3d4570 SS |
1648 | /* |
1649 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or | |
1650 | * RExit to a disconnect state). If so, let the the driver know it's | |
1651 | * out of the RExit state. | |
1652 | */ | |
2338b9e4 | 1653 | if (!DEV_SUPERSPEED_ANY(temp) && |
8b3d4570 SS |
1654 | test_and_clear_bit(faked_port_index, |
1655 | &bus_state->rexit_ports)) { | |
1656 | complete(&bus_state->rexit_done[faked_port_index]); | |
1657 | bogus_port_status = true; | |
1658 | goto cleanup; | |
1659 | } | |
1660 | ||
b50107bb | 1661 | if (hcd->speed < HCD_USB3) |
6fd45621 AX |
1662 | xhci_test_and_clear_bit(xhci, port_array, faked_port_index, |
1663 | PORT_PLC); | |
1664 | ||
56192531 | 1665 | cleanup: |
0f2a7930 | 1666 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 1667 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 1668 | |
386139d7 SS |
1669 | /* Don't make the USB core poll the roothub if we got a bad port status |
1670 | * change event. Besides, at that point we can't tell which roothub | |
1671 | * (USB 2.0 or USB 3.0) to kick. | |
1672 | */ | |
1673 | if (bogus_port_status) | |
1674 | return; | |
1675 | ||
c52804a4 SS |
1676 | /* |
1677 | * xHCI port-status-change events occur when the "or" of all the | |
1678 | * status-change bits in the portsc register changes from 0 to 1. | |
1679 | * New status changes won't cause an event if any other change | |
1680 | * bits are still set. When an event occurs, switch over to | |
1681 | * polling to avoid losing status changes. | |
1682 | */ | |
1683 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1684 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1685 | spin_unlock(&xhci->lock); |
1686 | /* Pass this up to the core */ | |
f6ff0ac8 | 1687 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
1688 | spin_lock(&xhci->lock); |
1689 | } | |
1690 | ||
d0e96f5a SS |
1691 | /* |
1692 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1693 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1694 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1695 | * returns 0. | |
1696 | */ | |
cffb9be8 HG |
1697 | struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, |
1698 | struct xhci_segment *start_seg, | |
d0e96f5a SS |
1699 | union xhci_trb *start_trb, |
1700 | union xhci_trb *end_trb, | |
cffb9be8 HG |
1701 | dma_addr_t suspect_dma, |
1702 | bool debug) | |
d0e96f5a SS |
1703 | { |
1704 | dma_addr_t start_dma; | |
1705 | dma_addr_t end_seg_dma; | |
1706 | dma_addr_t end_trb_dma; | |
1707 | struct xhci_segment *cur_seg; | |
1708 | ||
23e3be11 | 1709 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1710 | cur_seg = start_seg; |
1711 | ||
1712 | do { | |
2fa88daa | 1713 | if (start_dma == 0) |
326b4810 | 1714 | return NULL; |
ae636747 | 1715 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1716 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1717 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1718 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1719 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a | 1720 | |
cffb9be8 HG |
1721 | if (debug) |
1722 | xhci_warn(xhci, | |
1723 | "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", | |
1724 | (unsigned long long)suspect_dma, | |
1725 | (unsigned long long)start_dma, | |
1726 | (unsigned long long)end_trb_dma, | |
1727 | (unsigned long long)cur_seg->dma, | |
1728 | (unsigned long long)end_seg_dma); | |
1729 | ||
d0e96f5a SS |
1730 | if (end_trb_dma > 0) { |
1731 | /* The end TRB is in this segment, so suspect should be here */ | |
1732 | if (start_dma <= end_trb_dma) { | |
1733 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1734 | return cur_seg; | |
1735 | } else { | |
1736 | /* Case for one segment with | |
1737 | * a TD wrapped around to the top | |
1738 | */ | |
1739 | if ((suspect_dma >= start_dma && | |
1740 | suspect_dma <= end_seg_dma) || | |
1741 | (suspect_dma >= cur_seg->dma && | |
1742 | suspect_dma <= end_trb_dma)) | |
1743 | return cur_seg; | |
1744 | } | |
326b4810 | 1745 | return NULL; |
d0e96f5a SS |
1746 | } else { |
1747 | /* Might still be somewhere in this segment */ | |
1748 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1749 | return cur_seg; | |
1750 | } | |
1751 | cur_seg = cur_seg->next; | |
23e3be11 | 1752 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1753 | } while (cur_seg != start_seg); |
d0e96f5a | 1754 | |
326b4810 | 1755 | return NULL; |
d0e96f5a SS |
1756 | } |
1757 | ||
bcef3fd5 SS |
1758 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1759 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1760 | unsigned int stream_id, |
bcef3fd5 SS |
1761 | struct xhci_td *td, union xhci_trb *event_trb) |
1762 | { | |
1763 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
ddba5cd0 MN |
1764 | struct xhci_command *command; |
1765 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
1766 | if (!command) | |
1767 | return; | |
1768 | ||
d0167ad2 | 1769 | ep->ep_state |= EP_HALTED; |
e9df17eb | 1770 | ep->stopped_stream = stream_id; |
1624ae1c | 1771 | |
ddba5cd0 | 1772 | xhci_queue_reset_ep(xhci, command, slot_id, ep_index); |
d97b4f8d | 1773 | xhci_cleanup_stalled_ring(xhci, ep_index, td); |
1624ae1c | 1774 | |
5e5cf6fc | 1775 | ep->stopped_stream = 0; |
1624ae1c | 1776 | |
bcef3fd5 SS |
1777 | xhci_ring_cmd_db(xhci); |
1778 | } | |
1779 | ||
1780 | /* Check if an error has halted the endpoint ring. The class driver will | |
1781 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1782 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1783 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1784 | * Ring Dequeue Pointer command manually. | |
1785 | */ | |
1786 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1787 | struct xhci_ep_ctx *ep_ctx, | |
1788 | unsigned int trb_comp_code) | |
1789 | { | |
1790 | /* TRB completion codes that may require a manual halt cleanup */ | |
1791 | if (trb_comp_code == COMP_TX_ERR || | |
1792 | trb_comp_code == COMP_BABBLE || | |
1793 | trb_comp_code == COMP_SPLIT_ERR) | |
d4fc8bf5 | 1794 | /* The 0.95 spec says a babbling control endpoint |
bcef3fd5 SS |
1795 | * is not halted. The 0.96 spec says it is. Some HW |
1796 | * claims to be 0.95 compliant, but it halts the control | |
1797 | * endpoint anyway. Check if a babble halted the | |
1798 | * endpoint. | |
1799 | */ | |
f5960b69 ME |
1800 | if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == |
1801 | cpu_to_le32(EP_STATE_HALTED)) | |
bcef3fd5 SS |
1802 | return 1; |
1803 | ||
1804 | return 0; | |
1805 | } | |
1806 | ||
b45b5069 SS |
1807 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1808 | { | |
1809 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1810 | /* Vendor defined "informational" completion code, | |
1811 | * treat as not-an-error. | |
1812 | */ | |
1813 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1814 | trb_comp_code); | |
1815 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1816 | return 1; | |
1817 | } | |
1818 | return 0; | |
1819 | } | |
1820 | ||
4422da61 AX |
1821 | /* |
1822 | * Finish the td processing, remove the td from td list; | |
1823 | * Return 1 if the urb can be given back. | |
1824 | */ | |
1825 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1826 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1827 | struct xhci_virt_ep *ep, int *status, bool skip) | |
1828 | { | |
1829 | struct xhci_virt_device *xdev; | |
1830 | struct xhci_ring *ep_ring; | |
1831 | unsigned int slot_id; | |
1832 | int ep_index; | |
1833 | struct urb *urb = NULL; | |
1834 | struct xhci_ep_ctx *ep_ctx; | |
1835 | int ret = 0; | |
8e51adcc | 1836 | struct urb_priv *urb_priv; |
4422da61 AX |
1837 | u32 trb_comp_code; |
1838 | ||
28ccd296 | 1839 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
4422da61 | 1840 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1841 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1842 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
4422da61 | 1843 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1844 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
4422da61 AX |
1845 | |
1846 | if (skip) | |
1847 | goto td_cleanup; | |
1848 | ||
40a3b775 LB |
1849 | if (trb_comp_code == COMP_STOP_INVAL || |
1850 | trb_comp_code == COMP_STOP || | |
1851 | trb_comp_code == COMP_STOP_SHORT) { | |
4422da61 AX |
1852 | /* The Endpoint Stop Command completion will take care of any |
1853 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1854 | * the ring dequeue pointer or take this TD off any lists yet. | |
1855 | */ | |
1856 | ep->stopped_td = td; | |
4422da61 | 1857 | return 0; |
69defe04 MN |
1858 | } |
1859 | if (trb_comp_code == COMP_STALL || | |
1860 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, | |
1861 | trb_comp_code)) { | |
1862 | /* Issue a reset endpoint command to clear the host side | |
1863 | * halt, followed by a set dequeue command to move the | |
1864 | * dequeue pointer past the TD. | |
1865 | * The class driver clears the device side halt later. | |
1866 | */ | |
1867 | xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, | |
1868 | ep_ring->stream_id, td, event_trb); | |
4422da61 | 1869 | } else { |
69defe04 MN |
1870 | /* Update ring dequeue pointer */ |
1871 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 | 1872 | inc_deq(xhci, ep_ring); |
69defe04 MN |
1873 | inc_deq(xhci, ep_ring); |
1874 | } | |
4422da61 AX |
1875 | |
1876 | td_cleanup: | |
69defe04 MN |
1877 | /* Clean up the endpoint's TD list */ |
1878 | urb = td->urb; | |
1879 | urb_priv = urb->hcpriv; | |
1880 | ||
f9c589e1 MN |
1881 | /* if a bounce buffer was used to align this td then unmap it */ |
1882 | if (td->bounce_seg) | |
1883 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); | |
1884 | ||
69defe04 MN |
1885 | /* Do one last check of the actual transfer length. |
1886 | * If the host controller said we transferred more data than the buffer | |
1887 | * length, urb->actual_length will be a very big number (since it's | |
1888 | * unsigned). Play it safe and say we didn't transfer anything. | |
1889 | */ | |
1890 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1891 | xhci_warn(xhci, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n", | |
1892 | urb->transfer_buffer_length, | |
1893 | urb->actual_length); | |
1894 | urb->actual_length = 0; | |
1895 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1896 | *status = -EREMOTEIO; | |
1897 | else | |
1898 | *status = 0; | |
1899 | } | |
1900 | list_del_init(&td->td_list); | |
1901 | /* Was this TD slated to be cancelled but completed anyway? */ | |
1902 | if (!list_empty(&td->cancelled_td_list)) | |
1903 | list_del_init(&td->cancelled_td_list); | |
1904 | ||
1905 | urb_priv->td_cnt++; | |
1906 | /* Giveback the urb when all the tds are completed */ | |
1907 | if (urb_priv->td_cnt == urb_priv->length) { | |
1908 | ret = 1; | |
1909 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | |
1910 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
1911 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
1912 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
1913 | usb_amd_quirk_pll_enable(); | |
c41136b0 AX |
1914 | } |
1915 | } | |
4422da61 AX |
1916 | } |
1917 | ||
1918 | return ret; | |
1919 | } | |
1920 | ||
8af56be1 AX |
1921 | /* |
1922 | * Process control tds, update urb status and actual_length. | |
1923 | */ | |
1924 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1925 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1926 | struct xhci_virt_ep *ep, int *status) | |
1927 | { | |
1928 | struct xhci_virt_device *xdev; | |
1929 | struct xhci_ring *ep_ring; | |
1930 | unsigned int slot_id; | |
1931 | int ep_index; | |
1932 | struct xhci_ep_ctx *ep_ctx; | |
1933 | u32 trb_comp_code; | |
1934 | ||
28ccd296 | 1935 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
8af56be1 | 1936 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1937 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1938 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
8af56be1 | 1939 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1940 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
8af56be1 | 1941 | |
8af56be1 AX |
1942 | switch (trb_comp_code) { |
1943 | case COMP_SUCCESS: | |
1944 | if (event_trb == ep_ring->dequeue) { | |
1945 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB " | |
1946 | "without IOC set??\n"); | |
1947 | *status = -ESHUTDOWN; | |
1948 | } else if (event_trb != td->last_trb) { | |
1949 | xhci_warn(xhci, "WARN: Success on ctrl data TRB " | |
1950 | "without IOC set??\n"); | |
1951 | *status = -ESHUTDOWN; | |
1952 | } else { | |
8af56be1 AX |
1953 | *status = 0; |
1954 | } | |
1955 | break; | |
1956 | case COMP_SHORT_TX: | |
8af56be1 AX |
1957 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
1958 | *status = -EREMOTEIO; | |
1959 | else | |
1960 | *status = 0; | |
1961 | break; | |
40a3b775 LB |
1962 | case COMP_STOP_SHORT: |
1963 | if (event_trb == ep_ring->dequeue || event_trb == td->last_trb) | |
1964 | xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); | |
1965 | else | |
1966 | td->urb->actual_length = | |
1967 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
1968 | ||
1969 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
3abeca99 | 1970 | case COMP_STOP: |
40a3b775 LB |
1971 | /* Did we stop at data stage? */ |
1972 | if (event_trb != ep_ring->dequeue && event_trb != td->last_trb) | |
1973 | td->urb->actual_length = | |
1974 | td->urb->transfer_buffer_length - | |
1975 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
1976 | /* fall through */ | |
1977 | case COMP_STOP_INVAL: | |
3abeca99 | 1978 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
8af56be1 AX |
1979 | default: |
1980 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
1981 | ep_ctx, trb_comp_code)) | |
1982 | break; | |
1983 | xhci_dbg(xhci, "TRB error code %u, " | |
1984 | "halted endpoint index = %u\n", | |
1985 | trb_comp_code, ep_index); | |
1986 | /* else fall through */ | |
1987 | case COMP_STALL: | |
1988 | /* Did we transfer part of the data (middle) phase? */ | |
1989 | if (event_trb != ep_ring->dequeue && | |
1990 | event_trb != td->last_trb) | |
1991 | td->urb->actual_length = | |
1c11a172 VG |
1992 | td->urb->transfer_buffer_length - |
1993 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
22ae47e6 | 1994 | else if (!td->urb_length_set) |
8af56be1 AX |
1995 | td->urb->actual_length = 0; |
1996 | ||
8e71a322 | 1997 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
8af56be1 AX |
1998 | } |
1999 | /* | |
2000 | * Did we transfer any data, despite the errors that might have | |
2001 | * happened? I.e. did we get past the setup stage? | |
2002 | */ | |
2003 | if (event_trb != ep_ring->dequeue) { | |
2004 | /* The event was for the status stage */ | |
2005 | if (event_trb == td->last_trb) { | |
45ba2154 | 2006 | if (td->urb_length_set) { |
8af56be1 AX |
2007 | /* Don't overwrite a previously set error code |
2008 | */ | |
2009 | if ((*status == -EINPROGRESS || *status == 0) && | |
2010 | (td->urb->transfer_flags | |
2011 | & URB_SHORT_NOT_OK)) | |
2012 | /* Did we already see a short data | |
2013 | * stage? */ | |
2014 | *status = -EREMOTEIO; | |
2015 | } else { | |
2016 | td->urb->actual_length = | |
2017 | td->urb->transfer_buffer_length; | |
2018 | } | |
2019 | } else { | |
45ba2154 AM |
2020 | /* |
2021 | * Maybe the event was for the data stage? If so, update | |
2022 | * already the actual_length of the URB and flag it as | |
2023 | * set, so that it is not overwritten in the event for | |
2024 | * the last TRB. | |
2025 | */ | |
2026 | td->urb_length_set = true; | |
3abeca99 SS |
2027 | td->urb->actual_length = |
2028 | td->urb->transfer_buffer_length - | |
1c11a172 | 2029 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
3abeca99 SS |
2030 | xhci_dbg(xhci, "Waiting for status " |
2031 | "stage event\n"); | |
2032 | return 0; | |
8af56be1 AX |
2033 | } |
2034 | } | |
2035 | ||
2036 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
2037 | } | |
2038 | ||
04e51901 AX |
2039 | /* |
2040 | * Process isochronous tds, update urb packet status and actual_length. | |
2041 | */ | |
2042 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
2043 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
2044 | struct xhci_virt_ep *ep, int *status) | |
2045 | { | |
2046 | struct xhci_ring *ep_ring; | |
2047 | struct urb_priv *urb_priv; | |
2048 | int idx; | |
2049 | int len = 0; | |
04e51901 AX |
2050 | union xhci_trb *cur_trb; |
2051 | struct xhci_segment *cur_seg; | |
926008c9 | 2052 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 2053 | u32 trb_comp_code; |
926008c9 | 2054 | bool skip_td = false; |
04e51901 | 2055 | |
28ccd296 ME |
2056 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2057 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
04e51901 AX |
2058 | urb_priv = td->urb->hcpriv; |
2059 | idx = urb_priv->td_cnt; | |
926008c9 | 2060 | frame = &td->urb->iso_frame_desc[idx]; |
04e51901 | 2061 | |
926008c9 DT |
2062 | /* handle completion code */ |
2063 | switch (trb_comp_code) { | |
2064 | case COMP_SUCCESS: | |
1c11a172 | 2065 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) { |
1530bbc6 SS |
2066 | frame->status = 0; |
2067 | break; | |
2068 | } | |
2069 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) | |
2070 | trb_comp_code = COMP_SHORT_TX; | |
40a3b775 LB |
2071 | /* fallthrough */ |
2072 | case COMP_STOP_SHORT: | |
926008c9 DT |
2073 | case COMP_SHORT_TX: |
2074 | frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
2075 | -EREMOTEIO : 0; | |
2076 | break; | |
2077 | case COMP_BW_OVER: | |
2078 | frame->status = -ECOMM; | |
2079 | skip_td = true; | |
2080 | break; | |
2081 | case COMP_BUFF_OVER: | |
2082 | case COMP_BABBLE: | |
2083 | frame->status = -EOVERFLOW; | |
2084 | skip_td = true; | |
2085 | break; | |
f6ba6fe2 | 2086 | case COMP_DEV_ERR: |
926008c9 | 2087 | case COMP_STALL: |
d104d015 MN |
2088 | frame->status = -EPROTO; |
2089 | skip_td = true; | |
2090 | break; | |
9c745995 | 2091 | case COMP_TX_ERR: |
926008c9 | 2092 | frame->status = -EPROTO; |
d104d015 MN |
2093 | if (event_trb != td->last_trb) |
2094 | return 0; | |
926008c9 DT |
2095 | skip_td = true; |
2096 | break; | |
2097 | case COMP_STOP: | |
2098 | case COMP_STOP_INVAL: | |
2099 | break; | |
2100 | default: | |
2101 | frame->status = -1; | |
2102 | break; | |
04e51901 AX |
2103 | } |
2104 | ||
926008c9 DT |
2105 | if (trb_comp_code == COMP_SUCCESS || skip_td) { |
2106 | frame->actual_length = frame->length; | |
2107 | td->urb->actual_length += frame->length; | |
40a3b775 LB |
2108 | } else if (trb_comp_code == COMP_STOP_SHORT) { |
2109 | frame->actual_length = | |
2110 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2111 | td->urb->actual_length += frame->actual_length; | |
04e51901 AX |
2112 | } else { |
2113 | for (cur_trb = ep_ring->dequeue, | |
2114 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; | |
2115 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 ME |
2116 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
2117 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) | |
28ccd296 | 2118 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
04e51901 | 2119 | } |
28ccd296 | 2120 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1c11a172 | 2121 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
04e51901 AX |
2122 | |
2123 | if (trb_comp_code != COMP_STOP_INVAL) { | |
926008c9 | 2124 | frame->actual_length = len; |
04e51901 AX |
2125 | td->urb->actual_length += len; |
2126 | } | |
2127 | } | |
2128 | ||
04e51901 AX |
2129 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
2130 | } | |
2131 | ||
926008c9 DT |
2132 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
2133 | struct xhci_transfer_event *event, | |
2134 | struct xhci_virt_ep *ep, int *status) | |
2135 | { | |
2136 | struct xhci_ring *ep_ring; | |
2137 | struct urb_priv *urb_priv; | |
2138 | struct usb_iso_packet_descriptor *frame; | |
2139 | int idx; | |
2140 | ||
f6975314 | 2141 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
926008c9 DT |
2142 | urb_priv = td->urb->hcpriv; |
2143 | idx = urb_priv->td_cnt; | |
2144 | frame = &td->urb->iso_frame_desc[idx]; | |
2145 | ||
b3df3f9c | 2146 | /* The transfer is partly done. */ |
926008c9 DT |
2147 | frame->status = -EXDEV; |
2148 | ||
2149 | /* calc actual length */ | |
2150 | frame->actual_length = 0; | |
2151 | ||
2152 | /* Update ring dequeue pointer */ | |
2153 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
2154 | inc_deq(xhci, ep_ring); |
2155 | inc_deq(xhci, ep_ring); | |
926008c9 DT |
2156 | |
2157 | return finish_td(xhci, td, NULL, event, ep, status, true); | |
2158 | } | |
2159 | ||
22405ed2 AX |
2160 | /* |
2161 | * Process bulk and interrupt tds, update urb status and actual_length. | |
2162 | */ | |
2163 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
2164 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
2165 | struct xhci_virt_ep *ep, int *status) | |
2166 | { | |
2167 | struct xhci_ring *ep_ring; | |
2168 | union xhci_trb *cur_trb; | |
2169 | struct xhci_segment *cur_seg; | |
2170 | u32 trb_comp_code; | |
2171 | ||
28ccd296 ME |
2172 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2173 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
22405ed2 AX |
2174 | |
2175 | switch (trb_comp_code) { | |
2176 | case COMP_SUCCESS: | |
2177 | /* Double check that the HW transferred everything. */ | |
1530bbc6 | 2178 | if (event_trb != td->last_trb || |
1c11a172 | 2179 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
22405ed2 AX |
2180 | xhci_warn(xhci, "WARN Successful completion " |
2181 | "on short TX\n"); | |
2182 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2183 | *status = -EREMOTEIO; | |
2184 | else | |
2185 | *status = 0; | |
1530bbc6 SS |
2186 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) |
2187 | trb_comp_code = COMP_SHORT_TX; | |
22405ed2 | 2188 | } else { |
22405ed2 AX |
2189 | *status = 0; |
2190 | } | |
2191 | break; | |
40a3b775 | 2192 | case COMP_STOP_SHORT: |
22405ed2 AX |
2193 | case COMP_SHORT_TX: |
2194 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2195 | *status = -EREMOTEIO; | |
2196 | else | |
2197 | *status = 0; | |
2198 | break; | |
2199 | default: | |
2200 | /* Others already handled above */ | |
2201 | break; | |
2202 | } | |
f444ff27 SS |
2203 | if (trb_comp_code == COMP_SHORT_TX) |
2204 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, " | |
2205 | "%d bytes untransferred\n", | |
2206 | td->urb->ep->desc.bEndpointAddress, | |
2207 | td->urb->transfer_buffer_length, | |
1c11a172 | 2208 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
40a3b775 LB |
2209 | /* Stopped - short packet completion */ |
2210 | if (trb_comp_code == COMP_STOP_SHORT) { | |
2211 | td->urb->actual_length = | |
2212 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2213 | ||
2214 | if (td->urb->transfer_buffer_length < | |
2215 | td->urb->actual_length) { | |
2216 | xhci_warn(xhci, "HC gave bad length of %d bytes txed\n", | |
2217 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); | |
2218 | td->urb->actual_length = 0; | |
2219 | /* status will be set by usb core for canceled urbs */ | |
2220 | } | |
22405ed2 | 2221 | /* Fast path - was this the last TRB in the TD for this URB? */ |
40a3b775 | 2222 | } else if (event_trb == td->last_trb) { |
1c11a172 | 2223 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
22405ed2 AX |
2224 | td->urb->actual_length = |
2225 | td->urb->transfer_buffer_length - | |
1c11a172 | 2226 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
22405ed2 AX |
2227 | if (td->urb->transfer_buffer_length < |
2228 | td->urb->actual_length) { | |
2229 | xhci_warn(xhci, "HC gave bad length " | |
2230 | "of %d bytes left\n", | |
1c11a172 | 2231 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
22405ed2 AX |
2232 | td->urb->actual_length = 0; |
2233 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2234 | *status = -EREMOTEIO; | |
2235 | else | |
2236 | *status = 0; | |
2237 | } | |
2238 | /* Don't overwrite a previously set error code */ | |
2239 | if (*status == -EINPROGRESS) { | |
2240 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2241 | *status = -EREMOTEIO; | |
2242 | else | |
2243 | *status = 0; | |
2244 | } | |
2245 | } else { | |
2246 | td->urb->actual_length = | |
2247 | td->urb->transfer_buffer_length; | |
2248 | /* Ignore a short packet completion if the | |
2249 | * untransferred length was zero. | |
2250 | */ | |
2251 | if (*status == -EREMOTEIO) | |
2252 | *status = 0; | |
2253 | } | |
2254 | } else { | |
2255 | /* Slow path - walk the list, starting from the dequeue | |
2256 | * pointer, to get the actual length transferred. | |
2257 | */ | |
2258 | td->urb->actual_length = 0; | |
2259 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; | |
2260 | cur_trb != event_trb; | |
2261 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 ME |
2262 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
2263 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) | |
22405ed2 | 2264 | td->urb->actual_length += |
28ccd296 | 2265 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
22405ed2 AX |
2266 | } |
2267 | /* If the ring didn't stop on a Link or No-op TRB, add | |
2268 | * in the actual bytes transferred from the Normal TRB | |
2269 | */ | |
2270 | if (trb_comp_code != COMP_STOP_INVAL) | |
2271 | td->urb->actual_length += | |
28ccd296 | 2272 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1c11a172 | 2273 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
22405ed2 AX |
2274 | } |
2275 | ||
2276 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
2277 | } | |
2278 | ||
d0e96f5a SS |
2279 | /* |
2280 | * If this function returns an error condition, it means it got a Transfer | |
2281 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2282 | * At this point, the host controller is probably hosed and should be reset. | |
2283 | */ | |
2284 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2285 | struct xhci_transfer_event *event) | |
ed384bd3 FB |
2286 | __releases(&xhci->lock) |
2287 | __acquires(&xhci->lock) | |
d0e96f5a SS |
2288 | { |
2289 | struct xhci_virt_device *xdev; | |
63a0d9ab | 2290 | struct xhci_virt_ep *ep; |
d0e96f5a | 2291 | struct xhci_ring *ep_ring; |
82d1009f | 2292 | unsigned int slot_id; |
d0e96f5a | 2293 | int ep_index; |
326b4810 | 2294 | struct xhci_td *td = NULL; |
d0e96f5a SS |
2295 | dma_addr_t event_dma; |
2296 | struct xhci_segment *event_seg; | |
2297 | union xhci_trb *event_trb; | |
326b4810 | 2298 | struct urb *urb = NULL; |
d0e96f5a | 2299 | int status = -EINPROGRESS; |
8e51adcc | 2300 | struct urb_priv *urb_priv; |
d115b048 | 2301 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2302 | struct list_head *tmp; |
66d1eebc | 2303 | u32 trb_comp_code; |
4422da61 | 2304 | int ret = 0; |
c2d7b49f | 2305 | int td_num = 0; |
3b4739b8 | 2306 | bool handling_skipped_tds = false; |
d0e96f5a | 2307 | |
28ccd296 | 2308 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
82d1009f | 2309 | xdev = xhci->devs[slot_id]; |
d0e96f5a SS |
2310 | if (!xdev) { |
2311 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | |
9258c0b2 | 2312 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2313 | (unsigned long long) xhci_trb_virt_to_dma( |
2314 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2315 | xhci->event_ring->dequeue), |
2316 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2317 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2318 | le32_to_cpu(event->transfer_len), | |
2319 | le32_to_cpu(event->flags)); | |
2320 | xhci_dbg(xhci, "Event ring:\n"); | |
2321 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2322 | return -ENODEV; |
2323 | } | |
2324 | ||
2325 | /* Endpoint ID is 1 based, our index is zero based */ | |
28ccd296 | 2326 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
63a0d9ab | 2327 | ep = &xdev->eps[ep_index]; |
28ccd296 | 2328 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
d115b048 | 2329 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
986a92d4 | 2330 | if (!ep_ring || |
28ccd296 ME |
2331 | (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == |
2332 | EP_STATE_DISABLED) { | |
e9df17eb SS |
2333 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
2334 | "or incorrect stream ring\n"); | |
9258c0b2 | 2335 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2336 | (unsigned long long) xhci_trb_virt_to_dma( |
2337 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2338 | xhci->event_ring->dequeue), |
2339 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2340 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2341 | le32_to_cpu(event->transfer_len), | |
2342 | le32_to_cpu(event->flags)); | |
2343 | xhci_dbg(xhci, "Event ring:\n"); | |
2344 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2345 | return -ENODEV; |
2346 | } | |
2347 | ||
c2d7b49f AX |
2348 | /* Count current td numbers if ep->skip is set */ |
2349 | if (ep->skip) { | |
2350 | list_for_each(tmp, &ep_ring->td_list) | |
2351 | td_num++; | |
2352 | } | |
2353 | ||
28ccd296 ME |
2354 | event_dma = le64_to_cpu(event->buffer); |
2355 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
986a92d4 | 2356 | /* Look for common error cases */ |
66d1eebc | 2357 | switch (trb_comp_code) { |
b10de142 SS |
2358 | /* Skip codes that require special handling depending on |
2359 | * transfer type | |
2360 | */ | |
2361 | case COMP_SUCCESS: | |
1c11a172 | 2362 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
1530bbc6 SS |
2363 | break; |
2364 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2365 | trb_comp_code = COMP_SHORT_TX; | |
2366 | else | |
8202ce2e SS |
2367 | xhci_warn_ratelimited(xhci, |
2368 | "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n"); | |
b10de142 SS |
2369 | case COMP_SHORT_TX: |
2370 | break; | |
ae636747 SS |
2371 | case COMP_STOP: |
2372 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); | |
2373 | break; | |
2374 | case COMP_STOP_INVAL: | |
2375 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); | |
2376 | break; | |
40a3b775 LB |
2377 | case COMP_STOP_SHORT: |
2378 | xhci_dbg(xhci, "Stopped with short packet transfer detected\n"); | |
2379 | break; | |
b10de142 | 2380 | case COMP_STALL: |
2a9227a5 | 2381 | xhci_dbg(xhci, "Stalled endpoint\n"); |
63a0d9ab | 2382 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
2383 | status = -EPIPE; |
2384 | break; | |
2385 | case COMP_TRB_ERR: | |
2386 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); | |
2387 | status = -EILSEQ; | |
2388 | break; | |
ec74e403 | 2389 | case COMP_SPLIT_ERR: |
b10de142 | 2390 | case COMP_TX_ERR: |
2a9227a5 | 2391 | xhci_dbg(xhci, "Transfer error on endpoint\n"); |
b10de142 SS |
2392 | status = -EPROTO; |
2393 | break; | |
4a73143c | 2394 | case COMP_BABBLE: |
2a9227a5 | 2395 | xhci_dbg(xhci, "Babble error on endpoint\n"); |
4a73143c SS |
2396 | status = -EOVERFLOW; |
2397 | break; | |
b10de142 SS |
2398 | case COMP_DB_ERR: |
2399 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); | |
2400 | status = -ENOSR; | |
2401 | break; | |
986a92d4 AX |
2402 | case COMP_BW_OVER: |
2403 | xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); | |
2404 | break; | |
2405 | case COMP_BUFF_OVER: | |
2406 | xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); | |
2407 | break; | |
2408 | case COMP_UNDERRUN: | |
2409 | /* | |
2410 | * When the Isoch ring is empty, the xHC will generate | |
2411 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2412 | * Underrun Event for OUT Isoch endpoint. | |
2413 | */ | |
2414 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2415 | if (!list_empty(&ep_ring->td_list)) | |
2416 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2417 | "still with TDs queued?\n", | |
28ccd296 ME |
2418 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2419 | ep_index); | |
986a92d4 AX |
2420 | goto cleanup; |
2421 | case COMP_OVERRUN: | |
2422 | xhci_dbg(xhci, "overrun event on endpoint\n"); | |
2423 | if (!list_empty(&ep_ring->td_list)) | |
2424 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2425 | "still with TDs queued?\n", | |
28ccd296 ME |
2426 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2427 | ep_index); | |
986a92d4 | 2428 | goto cleanup; |
f6ba6fe2 AH |
2429 | case COMP_DEV_ERR: |
2430 | xhci_warn(xhci, "WARN: detect an incompatible device"); | |
2431 | status = -EPROTO; | |
2432 | break; | |
d18240db AX |
2433 | case COMP_MISSED_INT: |
2434 | /* | |
2435 | * When encounter missed service error, one or more isoc tds | |
2436 | * may be missed by xHC. | |
2437 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2438 | * short transfer when process the ep_ring next time. | |
2439 | */ | |
2440 | ep->skip = true; | |
2441 | xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); | |
2442 | goto cleanup; | |
3b4739b8 MN |
2443 | case COMP_PING_ERR: |
2444 | ep->skip = true; | |
2445 | xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n"); | |
2446 | goto cleanup; | |
b10de142 | 2447 | default: |
b45b5069 | 2448 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2449 | status = 0; |
2450 | break; | |
2451 | } | |
86cd740a MN |
2452 | xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n", |
2453 | trb_comp_code); | |
986a92d4 AX |
2454 | goto cleanup; |
2455 | } | |
2456 | ||
d18240db AX |
2457 | do { |
2458 | /* This TRB should be in the TD at the head of this ring's | |
2459 | * TD list. | |
2460 | */ | |
2461 | if (list_empty(&ep_ring->td_list)) { | |
a83d6755 SS |
2462 | /* |
2463 | * A stopped endpoint may generate an extra completion | |
2464 | * event if the device was suspended. Don't print | |
2465 | * warnings. | |
2466 | */ | |
2467 | if (!(trb_comp_code == COMP_STOP || | |
2468 | trb_comp_code == COMP_STOP_INVAL)) { | |
2469 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", | |
2470 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), | |
2471 | ep_index); | |
2472 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", | |
2473 | (le32_to_cpu(event->flags) & | |
2474 | TRB_TYPE_BITMASK)>>10); | |
2475 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); | |
2476 | } | |
d18240db AX |
2477 | if (ep->skip) { |
2478 | ep->skip = false; | |
2479 | xhci_dbg(xhci, "td_list is empty while skip " | |
2480 | "flag set. Clear skip flag.\n"); | |
2481 | } | |
2482 | ret = 0; | |
2483 | goto cleanup; | |
2484 | } | |
986a92d4 | 2485 | |
c2d7b49f AX |
2486 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2487 | if (ep->skip && td_num == 0) { | |
2488 | ep->skip = false; | |
2489 | xhci_dbg(xhci, "All tds on the ep_ring skipped. " | |
2490 | "Clear skip flag.\n"); | |
2491 | ret = 0; | |
2492 | goto cleanup; | |
2493 | } | |
2494 | ||
d18240db | 2495 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
c2d7b49f AX |
2496 | if (ep->skip) |
2497 | td_num--; | |
926008c9 | 2498 | |
d18240db | 2499 | /* Is this a TRB in the currently executing TD? */ |
cffb9be8 HG |
2500 | event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, |
2501 | td->last_trb, event_dma, false); | |
e1cf486d AH |
2502 | |
2503 | /* | |
2504 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2505 | * is not in the current TD pointed by ep_ring->dequeue because | |
2506 | * that the hardware dequeue pointer still at the previous TRB | |
2507 | * of the current TD. The previous TRB maybe a Link TD or the | |
2508 | * last TRB of the previous TD. The command completion handle | |
2509 | * will take care the rest. | |
2510 | */ | |
9a548863 HG |
2511 | if (!event_seg && (trb_comp_code == COMP_STOP || |
2512 | trb_comp_code == COMP_STOP_INVAL)) { | |
e1cf486d AH |
2513 | ret = 0; |
2514 | goto cleanup; | |
2515 | } | |
2516 | ||
926008c9 DT |
2517 | if (!event_seg) { |
2518 | if (!ep->skip || | |
2519 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2520 | /* Some host controllers give a spurious |
2521 | * successful event after a short transfer. | |
2522 | * Ignore it. | |
2523 | */ | |
ddba5cd0 | 2524 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
ad808333 SS |
2525 | ep_ring->last_td_was_short) { |
2526 | ep_ring->last_td_was_short = false; | |
2527 | ret = 0; | |
2528 | goto cleanup; | |
2529 | } | |
926008c9 DT |
2530 | /* HC is busted, give up! */ |
2531 | xhci_err(xhci, | |
2532 | "ERROR Transfer event TRB DMA ptr not " | |
cffb9be8 HG |
2533 | "part of current TD ep_index %d " |
2534 | "comp_code %u\n", ep_index, | |
2535 | trb_comp_code); | |
2536 | trb_in_td(xhci, ep_ring->deq_seg, | |
2537 | ep_ring->dequeue, td->last_trb, | |
2538 | event_dma, true); | |
926008c9 DT |
2539 | return -ESHUTDOWN; |
2540 | } | |
2541 | ||
2542 | ret = skip_isoc_td(xhci, td, event, ep, &status); | |
2543 | goto cleanup; | |
2544 | } | |
ad808333 SS |
2545 | if (trb_comp_code == COMP_SHORT_TX) |
2546 | ep_ring->last_td_was_short = true; | |
2547 | else | |
2548 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2549 | |
2550 | if (ep->skip) { | |
d18240db AX |
2551 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); |
2552 | ep->skip = false; | |
2553 | } | |
678539cf | 2554 | |
926008c9 DT |
2555 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / |
2556 | sizeof(*event_trb)]; | |
2557 | /* | |
2558 | * No-op TRB should not trigger interrupts. | |
2559 | * If event_trb is a no-op TRB, it means the | |
2560 | * corresponding TD has been cancelled. Just ignore | |
2561 | * the TD. | |
2562 | */ | |
f5960b69 | 2563 | if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) { |
926008c9 DT |
2564 | xhci_dbg(xhci, |
2565 | "event_trb is a no-op TRB. Skip it\n"); | |
2566 | goto cleanup; | |
d18240db | 2567 | } |
4422da61 | 2568 | |
d18240db AX |
2569 | /* Now update the urb's actual_length and give back to |
2570 | * the core | |
82d1009f | 2571 | */ |
d18240db AX |
2572 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
2573 | ret = process_ctrl_td(xhci, td, event_trb, event, ep, | |
2574 | &status); | |
04e51901 AX |
2575 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
2576 | ret = process_isoc_td(xhci, td, event_trb, event, ep, | |
2577 | &status); | |
d18240db AX |
2578 | else |
2579 | ret = process_bulk_intr_td(xhci, td, event_trb, event, | |
2580 | ep, &status); | |
2581 | ||
2582 | cleanup: | |
3b4739b8 MN |
2583 | |
2584 | ||
2585 | handling_skipped_tds = ep->skip && | |
2586 | trb_comp_code != COMP_MISSED_INT && | |
2587 | trb_comp_code != COMP_PING_ERR; | |
2588 | ||
d18240db | 2589 | /* |
3b4739b8 MN |
2590 | * Do not update event ring dequeue pointer if we're in a loop |
2591 | * processing missed tds. | |
d18240db | 2592 | */ |
3b4739b8 | 2593 | if (!handling_skipped_tds) |
3b72fca0 | 2594 | inc_deq(xhci, xhci->event_ring); |
d18240db AX |
2595 | |
2596 | if (ret) { | |
2597 | urb = td->urb; | |
8e51adcc | 2598 | urb_priv = urb->hcpriv; |
8e71a322 | 2599 | |
4daf9df5 | 2600 | xhci_urb_free_priv(urb_priv); |
d18240db | 2601 | |
214f76f7 | 2602 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
f444ff27 SS |
2603 | if ((urb->actual_length != urb->transfer_buffer_length && |
2604 | (urb->transfer_flags & | |
2605 | URB_SHORT_NOT_OK)) || | |
fd984d24 SS |
2606 | (status != 0 && |
2607 | !usb_endpoint_xfer_isoc(&urb->ep->desc))) | |
f444ff27 | 2608 | xhci_dbg(xhci, "Giveback URB %p, len = %d, " |
1949f9e2 | 2609 | "expected = %d, status = %d\n", |
f444ff27 SS |
2610 | urb, urb->actual_length, |
2611 | urb->transfer_buffer_length, | |
2612 | status); | |
d18240db | 2613 | spin_unlock(&xhci->lock); |
b3df3f9c SS |
2614 | /* EHCI, UHCI, and OHCI always unconditionally set the |
2615 | * urb->status of an isochronous endpoint to 0. | |
2616 | */ | |
2617 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
2618 | status = 0; | |
214f76f7 | 2619 | usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); |
d18240db AX |
2620 | spin_lock(&xhci->lock); |
2621 | } | |
2622 | ||
2623 | /* | |
2624 | * If ep->skip is set, it means there are missed tds on the | |
2625 | * endpoint ring need to take care of. | |
2626 | * Process them as short transfer until reach the td pointed by | |
2627 | * the event. | |
2628 | */ | |
3b4739b8 | 2629 | } while (handling_skipped_tds); |
d18240db | 2630 | |
d0e96f5a SS |
2631 | return 0; |
2632 | } | |
2633 | ||
0f2a7930 SS |
2634 | /* |
2635 | * This function handles all OS-owned events on the event ring. It may drop | |
2636 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2637 | * Returns >0 for "possibly more events to process" (caller should call again), |
2638 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2639 | */ |
9dee9a21 | 2640 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2641 | { |
2642 | union xhci_trb *event; | |
0f2a7930 | 2643 | int update_ptrs = 1; |
d0e96f5a | 2644 | int ret; |
7f84eef0 SS |
2645 | |
2646 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { | |
2647 | xhci->error_bitmask |= 1 << 1; | |
9dee9a21 | 2648 | return 0; |
7f84eef0 SS |
2649 | } |
2650 | ||
2651 | event = xhci->event_ring->dequeue; | |
2652 | /* Does the HC or OS own the TRB? */ | |
28ccd296 ME |
2653 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
2654 | xhci->event_ring->cycle_state) { | |
7f84eef0 | 2655 | xhci->error_bitmask |= 1 << 2; |
9dee9a21 | 2656 | return 0; |
7f84eef0 SS |
2657 | } |
2658 | ||
92a3da41 ME |
2659 | /* |
2660 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2661 | * speculative reads of the event's flags/data below. | |
2662 | */ | |
2663 | rmb(); | |
0f2a7930 | 2664 | /* FIXME: Handle more event types. */ |
28ccd296 | 2665 | switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { |
7f84eef0 SS |
2666 | case TRB_TYPE(TRB_COMPLETION): |
2667 | handle_cmd_completion(xhci, &event->event_cmd); | |
2668 | break; | |
0f2a7930 SS |
2669 | case TRB_TYPE(TRB_PORT_STATUS): |
2670 | handle_port_status(xhci, event); | |
2671 | update_ptrs = 0; | |
2672 | break; | |
d0e96f5a SS |
2673 | case TRB_TYPE(TRB_TRANSFER): |
2674 | ret = handle_tx_event(xhci, &event->trans_event); | |
2675 | if (ret < 0) | |
2676 | xhci->error_bitmask |= 1 << 9; | |
2677 | else | |
2678 | update_ptrs = 0; | |
2679 | break; | |
623bef9e SS |
2680 | case TRB_TYPE(TRB_DEV_NOTE): |
2681 | handle_device_notification(xhci, event); | |
2682 | break; | |
7f84eef0 | 2683 | default: |
28ccd296 ME |
2684 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2685 | TRB_TYPE(48)) | |
0238634d SS |
2686 | handle_vendor_event(xhci, event); |
2687 | else | |
2688 | xhci->error_bitmask |= 1 << 3; | |
7f84eef0 | 2689 | } |
6f5165cf SS |
2690 | /* Any of the above functions may drop and re-acquire the lock, so check |
2691 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2692 | */ | |
2693 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2694 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2695 | "event handler.\n"); | |
9dee9a21 | 2696 | return 0; |
6f5165cf | 2697 | } |
7f84eef0 | 2698 | |
c06d68b8 SS |
2699 | if (update_ptrs) |
2700 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 2701 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 2702 | |
9dee9a21 ME |
2703 | /* Are there more items on the event ring? Caller will call us again to |
2704 | * check. | |
2705 | */ | |
2706 | return 1; | |
7f84eef0 | 2707 | } |
9032cd52 SS |
2708 | |
2709 | /* | |
2710 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2711 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2712 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2713 | */ | |
2714 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2715 | { | |
2716 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c21599a3 | 2717 | u32 status; |
bda53145 | 2718 | u64 temp_64; |
c06d68b8 SS |
2719 | union xhci_trb *event_ring_deq; |
2720 | dma_addr_t deq; | |
9032cd52 SS |
2721 | |
2722 | spin_lock(&xhci->lock); | |
9032cd52 | 2723 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
b0ba9720 | 2724 | status = readl(&xhci->op_regs->status); |
c21599a3 | 2725 | if (status == 0xffffffff) |
9032cd52 SS |
2726 | goto hw_died; |
2727 | ||
c21599a3 | 2728 | if (!(status & STS_EINT)) { |
9032cd52 | 2729 | spin_unlock(&xhci->lock); |
9032cd52 SS |
2730 | return IRQ_NONE; |
2731 | } | |
27e0dd4d | 2732 | if (status & STS_FATAL) { |
9032cd52 SS |
2733 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2734 | xhci_halt(xhci); | |
2735 | hw_died: | |
9032cd52 | 2736 | spin_unlock(&xhci->lock); |
948fa135 | 2737 | return IRQ_HANDLED; |
9032cd52 SS |
2738 | } |
2739 | ||
bda53145 SS |
2740 | /* |
2741 | * Clear the op reg interrupt status first, | |
2742 | * so we can receive interrupts from other MSI-X interrupters. | |
2743 | * Write 1 to clear the interrupt status. | |
2744 | */ | |
27e0dd4d | 2745 | status |= STS_EINT; |
204b7793 | 2746 | writel(status, &xhci->op_regs->status); |
bda53145 SS |
2747 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
2748 | /* Clear the MSI-X event interrupt status */ | |
2749 | ||
cd70469d | 2750 | if (hcd->irq) { |
c21599a3 SS |
2751 | u32 irq_pending; |
2752 | /* Acknowledge the PCI interrupt */ | |
b0ba9720 | 2753 | irq_pending = readl(&xhci->ir_set->irq_pending); |
4e833c0b | 2754 | irq_pending |= IMAN_IP; |
204b7793 | 2755 | writel(irq_pending, &xhci->ir_set->irq_pending); |
c21599a3 | 2756 | } |
bda53145 | 2757 | |
27a41a83 GKB |
2758 | if (xhci->xhc_state & XHCI_STATE_DYING || |
2759 | xhci->xhc_state & XHCI_STATE_HALTED) { | |
bda53145 SS |
2760 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2761 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2762 | /* Clear the event handler busy flag (RW1C); |
2763 | * the event ring should be empty. | |
bda53145 | 2764 | */ |
f7b2e403 | 2765 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
477632df SS |
2766 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
2767 | &xhci->ir_set->erst_dequeue); | |
c06d68b8 SS |
2768 | spin_unlock(&xhci->lock); |
2769 | ||
2770 | return IRQ_HANDLED; | |
2771 | } | |
2772 | ||
2773 | event_ring_deq = xhci->event_ring->dequeue; | |
2774 | /* FIXME this should be a delayed service routine | |
2775 | * that clears the EHB. | |
2776 | */ | |
9dee9a21 | 2777 | while (xhci_handle_event(xhci) > 0) {} |
bda53145 | 2778 | |
f7b2e403 | 2779 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2780 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2781 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2782 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2783 | xhci->event_ring->dequeue); | |
2784 | if (deq == 0) | |
2785 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2786 | "ring dequeue ptr.\n"); | |
2787 | /* Update HC event ring dequeue pointer */ | |
2788 | temp_64 &= ERST_PTR_MASK; | |
2789 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2790 | } | |
2791 | ||
2792 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2793 | temp_64 |= ERST_EHB; | |
477632df | 2794 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
c06d68b8 | 2795 | |
9032cd52 SS |
2796 | spin_unlock(&xhci->lock); |
2797 | ||
2798 | return IRQ_HANDLED; | |
2799 | } | |
2800 | ||
851ec164 | 2801 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
9032cd52 | 2802 | { |
968b822c | 2803 | return xhci_irq(hcd); |
9032cd52 | 2804 | } |
7f84eef0 | 2805 | |
d0e96f5a SS |
2806 | /**** Endpoint Ring Operations ****/ |
2807 | ||
7f84eef0 SS |
2808 | /* |
2809 | * Generic function for queueing a TRB on a ring. | |
2810 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2811 | * |
2812 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2813 | * prepare_transfer()? | |
7f84eef0 SS |
2814 | */ |
2815 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 2816 | bool more_trbs_coming, |
7f84eef0 SS |
2817 | u32 field1, u32 field2, u32 field3, u32 field4) |
2818 | { | |
2819 | struct xhci_generic_trb *trb; | |
2820 | ||
2821 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
2822 | trb->field[0] = cpu_to_le32(field1); |
2823 | trb->field[1] = cpu_to_le32(field2); | |
2824 | trb->field[2] = cpu_to_le32(field3); | |
2825 | trb->field[3] = cpu_to_le32(field4); | |
3b72fca0 | 2826 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
2827 | } |
2828 | ||
d0e96f5a SS |
2829 | /* |
2830 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2831 | * FIXME allocate segments if the ring is full. | |
2832 | */ | |
2833 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 2834 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 2835 | { |
8dfec614 AX |
2836 | unsigned int num_trbs_needed; |
2837 | ||
d0e96f5a | 2838 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
2839 | switch (ep_state) { |
2840 | case EP_STATE_DISABLED: | |
2841 | /* | |
2842 | * USB core changed config/interfaces without notifying us, | |
2843 | * or hardware is reporting the wrong state. | |
2844 | */ | |
2845 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2846 | return -ENOENT; | |
d0e96f5a | 2847 | case EP_STATE_ERROR: |
c92bcfa7 | 2848 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
2849 | /* FIXME event handling code for error needs to clear it */ |
2850 | /* XXX not sure if this should be -ENOENT or not */ | |
2851 | return -EINVAL; | |
c92bcfa7 SS |
2852 | case EP_STATE_HALTED: |
2853 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
2854 | case EP_STATE_STOPPED: |
2855 | case EP_STATE_RUNNING: | |
2856 | break; | |
2857 | default: | |
2858 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
2859 | /* | |
2860 | * FIXME issue Configure Endpoint command to try to get the HC | |
2861 | * back into a known state. | |
2862 | */ | |
2863 | return -EINVAL; | |
2864 | } | |
8dfec614 AX |
2865 | |
2866 | while (1) { | |
3d4b81ed SS |
2867 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
2868 | break; | |
8dfec614 AX |
2869 | |
2870 | if (ep_ring == xhci->cmd_ring) { | |
2871 | xhci_err(xhci, "Do not support expand command ring\n"); | |
2872 | return -ENOMEM; | |
2873 | } | |
2874 | ||
68ffb011 XR |
2875 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
2876 | "ERROR no room on ep ring, try ring expansion"); | |
8dfec614 AX |
2877 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
2878 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
2879 | mem_flags)) { | |
2880 | xhci_err(xhci, "Ring expansion failed\n"); | |
2881 | return -ENOMEM; | |
2882 | } | |
261fa12b | 2883 | } |
6c12db90 | 2884 | |
d0c77d84 MN |
2885 | while (trb_is_link(ep_ring->enqueue)) { |
2886 | /* If we're not dealing with 0.95 hardware or isoc rings | |
2887 | * on AMD 0.96 host, clear the chain bit. | |
2888 | */ | |
2889 | if (!xhci_link_trb_quirk(xhci) && | |
2890 | !(ep_ring->type == TYPE_ISOC && | |
2891 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
2892 | ep_ring->enqueue->link.control &= | |
2893 | cpu_to_le32(~TRB_CHAIN); | |
2894 | else | |
2895 | ep_ring->enqueue->link.control |= | |
2896 | cpu_to_le32(TRB_CHAIN); | |
6c12db90 | 2897 | |
d0c77d84 MN |
2898 | wmb(); |
2899 | ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); | |
6c12db90 | 2900 | |
d0c77d84 MN |
2901 | /* Toggle the cycle bit after the last ring segment. */ |
2902 | if (link_trb_toggles_cycle(ep_ring->enqueue)) | |
2903 | ep_ring->cycle_state ^= 1; | |
6c12db90 | 2904 | |
d0c77d84 MN |
2905 | ep_ring->enq_seg = ep_ring->enq_seg->next; |
2906 | ep_ring->enqueue = ep_ring->enq_seg->trbs; | |
6c12db90 | 2907 | } |
d0e96f5a SS |
2908 | return 0; |
2909 | } | |
2910 | ||
23e3be11 | 2911 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
2912 | struct xhci_virt_device *xdev, |
2913 | unsigned int ep_index, | |
e9df17eb | 2914 | unsigned int stream_id, |
d0e96f5a SS |
2915 | unsigned int num_trbs, |
2916 | struct urb *urb, | |
8e51adcc | 2917 | unsigned int td_index, |
d0e96f5a SS |
2918 | gfp_t mem_flags) |
2919 | { | |
2920 | int ret; | |
8e51adcc AX |
2921 | struct urb_priv *urb_priv; |
2922 | struct xhci_td *td; | |
e9df17eb | 2923 | struct xhci_ring *ep_ring; |
d115b048 | 2924 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
2925 | |
2926 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
2927 | if (!ep_ring) { | |
2928 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
2929 | stream_id); | |
2930 | return -EINVAL; | |
2931 | } | |
2932 | ||
2933 | ret = prepare_ring(xhci, ep_ring, | |
28ccd296 | 2934 | le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3b72fca0 | 2935 | num_trbs, mem_flags); |
d0e96f5a SS |
2936 | if (ret) |
2937 | return ret; | |
d0e96f5a | 2938 | |
8e51adcc AX |
2939 | urb_priv = urb->hcpriv; |
2940 | td = urb_priv->td[td_index]; | |
2941 | ||
2942 | INIT_LIST_HEAD(&td->td_list); | |
2943 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
2944 | ||
2945 | if (td_index == 0) { | |
214f76f7 | 2946 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 2947 | if (unlikely(ret)) |
8e51adcc | 2948 | return ret; |
d0e96f5a SS |
2949 | } |
2950 | ||
8e51adcc | 2951 | td->urb = urb; |
d0e96f5a | 2952 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
2953 | list_add_tail(&td->td_list, &ep_ring->td_list); |
2954 | td->start_seg = ep_ring->enq_seg; | |
2955 | td->first_trb = ep_ring->enqueue; | |
2956 | ||
2957 | urb_priv->td[td_index] = td; | |
d0e96f5a SS |
2958 | |
2959 | return 0; | |
2960 | } | |
2961 | ||
d2510342 AI |
2962 | static unsigned int count_trbs(u64 addr, u64 len) |
2963 | { | |
2964 | unsigned int num_trbs; | |
2965 | ||
2966 | num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), | |
2967 | TRB_MAX_BUFF_SIZE); | |
2968 | if (num_trbs == 0) | |
2969 | num_trbs++; | |
2970 | ||
2971 | return num_trbs; | |
2972 | } | |
2973 | ||
2974 | static inline unsigned int count_trbs_needed(struct urb *urb) | |
2975 | { | |
2976 | return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); | |
2977 | } | |
2978 | ||
2979 | static unsigned int count_sg_trbs_needed(struct urb *urb) | |
8a96c052 | 2980 | { |
8a96c052 | 2981 | struct scatterlist *sg; |
d2510342 | 2982 | unsigned int i, len, full_len, num_trbs = 0; |
8a96c052 | 2983 | |
d2510342 | 2984 | full_len = urb->transfer_buffer_length; |
8a96c052 | 2985 | |
d2510342 AI |
2986 | for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { |
2987 | len = sg_dma_len(sg); | |
2988 | num_trbs += count_trbs(sg_dma_address(sg), len); | |
2989 | len = min_t(unsigned int, len, full_len); | |
2990 | full_len -= len; | |
2991 | if (full_len == 0) | |
8a96c052 SS |
2992 | break; |
2993 | } | |
d2510342 | 2994 | |
8a96c052 SS |
2995 | return num_trbs; |
2996 | } | |
2997 | ||
d2510342 AI |
2998 | static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) |
2999 | { | |
3000 | u64 addr, len; | |
3001 | ||
3002 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
3003 | len = urb->iso_frame_desc[i].length; | |
3004 | ||
3005 | return count_trbs(addr, len); | |
3006 | } | |
3007 | ||
3008 | static void check_trb_math(struct urb *urb, int running_total) | |
8a96c052 | 3009 | { |
d2510342 | 3010 | if (unlikely(running_total != urb->transfer_buffer_length)) |
a2490187 | 3011 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
3012 | "queued %#x (%d), asked for %#x (%d)\n", |
3013 | __func__, | |
3014 | urb->ep->desc.bEndpointAddress, | |
3015 | running_total, running_total, | |
3016 | urb->transfer_buffer_length, | |
3017 | urb->transfer_buffer_length); | |
3018 | } | |
3019 | ||
23e3be11 | 3020 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 3021 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 3022 | struct xhci_generic_trb *start_trb) |
8a96c052 | 3023 | { |
8a96c052 SS |
3024 | /* |
3025 | * Pass all the TRBs to the hardware at once and make sure this write | |
3026 | * isn't reordered. | |
3027 | */ | |
3028 | wmb(); | |
50f7b52a | 3029 | if (start_cycle) |
28ccd296 | 3030 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 3031 | else |
28ccd296 | 3032 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 3033 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
3034 | } |
3035 | ||
78140156 AI |
3036 | static void check_interval(struct xhci_hcd *xhci, struct urb *urb, |
3037 | struct xhci_ep_ctx *ep_ctx) | |
624defa1 | 3038 | { |
624defa1 SS |
3039 | int xhci_interval; |
3040 | int ep_interval; | |
3041 | ||
28ccd296 | 3042 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 | 3043 | ep_interval = urb->interval; |
78140156 | 3044 | |
624defa1 SS |
3045 | /* Convert to microframes */ |
3046 | if (urb->dev->speed == USB_SPEED_LOW || | |
3047 | urb->dev->speed == USB_SPEED_FULL) | |
3048 | ep_interval *= 8; | |
78140156 | 3049 | |
624defa1 SS |
3050 | /* FIXME change this to a warning and a suggestion to use the new API |
3051 | * to set the polling interval (once the API is added). | |
3052 | */ | |
3053 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3054 | dev_dbg_ratelimited(&urb->dev->dev, |
3055 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3056 | ep_interval, ep_interval == 1 ? "" : "s", | |
3057 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
624defa1 SS |
3058 | urb->interval = xhci_interval; |
3059 | /* Convert back to frames for LS/FS devices */ | |
3060 | if (urb->dev->speed == USB_SPEED_LOW || | |
3061 | urb->dev->speed == USB_SPEED_FULL) | |
3062 | urb->interval /= 8; | |
3063 | } | |
78140156 AI |
3064 | } |
3065 | ||
3066 | /* | |
3067 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
3068 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
3069 | * (comprised of sg list entries) can take several service intervals to | |
3070 | * transmit. | |
3071 | */ | |
3072 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3073 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3074 | { | |
3075 | struct xhci_ep_ctx *ep_ctx; | |
3076 | ||
3077 | ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); | |
3078 | check_interval(xhci, urb, ep_ctx); | |
3079 | ||
3fc8206d | 3080 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
3081 | } |
3082 | ||
4da6e6f2 | 3083 | /* |
4525c0a1 SS |
3084 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
3085 | * packets remaining in the TD (*not* including this TRB). | |
4da6e6f2 SS |
3086 | * |
3087 | * Total TD packet count = total_packet_count = | |
4525c0a1 | 3088 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
4da6e6f2 SS |
3089 | * |
3090 | * Packets transferred up to and including this TRB = packets_transferred = | |
3091 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
3092 | * | |
3093 | * TD size = total_packet_count - packets_transferred | |
3094 | * | |
c840d6ce MN |
3095 | * For xHCI 0.96 and older, TD size field should be the remaining bytes |
3096 | * including this TRB, right shifted by 10 | |
3097 | * | |
3098 | * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. | |
3099 | * This is taken care of in the TRB_TD_SIZE() macro | |
3100 | * | |
4525c0a1 | 3101 | * The last TRB in a TD must have the TD size set to zero. |
4da6e6f2 | 3102 | */ |
c840d6ce MN |
3103 | static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, |
3104 | int trb_buff_len, unsigned int td_total_len, | |
124c3937 | 3105 | struct urb *urb, bool more_trbs_coming) |
4da6e6f2 | 3106 | { |
c840d6ce MN |
3107 | u32 maxp, total_packet_count; |
3108 | ||
0cbd4b34 CY |
3109 | /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */ |
3110 | if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) | |
c840d6ce MN |
3111 | return ((td_total_len - transferred) >> 10); |
3112 | ||
48df4a6f | 3113 | /* One TRB with a zero-length data packet. */ |
124c3937 | 3114 | if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || |
c840d6ce | 3115 | trb_buff_len == td_total_len) |
48df4a6f SS |
3116 | return 0; |
3117 | ||
0cbd4b34 CY |
3118 | /* for MTK xHCI, TD size doesn't include this TRB */ |
3119 | if (xhci->quirks & XHCI_MTK_HOST) | |
3120 | trb_buff_len = 0; | |
3121 | ||
3122 | maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); | |
3123 | total_packet_count = DIV_ROUND_UP(td_total_len, maxp); | |
3124 | ||
c840d6ce MN |
3125 | /* Queueing functions don't count the current TRB into transferred */ |
3126 | return (total_packet_count - ((transferred + trb_buff_len) / maxp)); | |
4da6e6f2 SS |
3127 | } |
3128 | ||
f9c589e1 | 3129 | |
474ed23a | 3130 | static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, |
f9c589e1 | 3131 | u32 *trb_buff_len, struct xhci_segment *seg) |
474ed23a | 3132 | { |
f9c589e1 | 3133 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
474ed23a MN |
3134 | unsigned int unalign; |
3135 | unsigned int max_pkt; | |
f9c589e1 | 3136 | u32 new_buff_len; |
474ed23a MN |
3137 | |
3138 | max_pkt = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); | |
3139 | unalign = (enqd_len + *trb_buff_len) % max_pkt; | |
3140 | ||
3141 | /* we got lucky, last normal TRB data on segment is packet aligned */ | |
3142 | if (unalign == 0) | |
3143 | return 0; | |
3144 | ||
f9c589e1 MN |
3145 | xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", |
3146 | unalign, *trb_buff_len); | |
3147 | ||
474ed23a MN |
3148 | /* is the last nornal TRB alignable by splitting it */ |
3149 | if (*trb_buff_len > unalign) { | |
3150 | *trb_buff_len -= unalign; | |
f9c589e1 | 3151 | xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); |
474ed23a MN |
3152 | return 0; |
3153 | } | |
f9c589e1 MN |
3154 | |
3155 | /* | |
3156 | * We want enqd_len + trb_buff_len to sum up to a number aligned to | |
3157 | * number which is divisible by the endpoint's wMaxPacketSize. IOW: | |
3158 | * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. | |
3159 | */ | |
3160 | new_buff_len = max_pkt - (enqd_len % max_pkt); | |
3161 | ||
3162 | if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) | |
3163 | new_buff_len = (urb->transfer_buffer_length - enqd_len); | |
3164 | ||
3165 | /* create a max max_pkt sized bounce buffer pointed to by last trb */ | |
3166 | if (usb_urb_dir_out(urb)) { | |
3167 | sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs, | |
3168 | seg->bounce_buf, new_buff_len, enqd_len); | |
3169 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3170 | max_pkt, DMA_TO_DEVICE); | |
3171 | } else { | |
3172 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3173 | max_pkt, DMA_FROM_DEVICE); | |
3174 | } | |
3175 | ||
3176 | if (dma_mapping_error(dev, seg->bounce_dma)) { | |
3177 | /* try without aligning. Some host controllers survive */ | |
3178 | xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); | |
3179 | return 0; | |
3180 | } | |
3181 | *trb_buff_len = new_buff_len; | |
3182 | seg->bounce_len = new_buff_len; | |
3183 | seg->bounce_offs = enqd_len; | |
3184 | ||
3185 | xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); | |
3186 | ||
474ed23a MN |
3187 | return 1; |
3188 | } | |
3189 | ||
d2510342 AI |
3190 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
3191 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
8a96c052 SS |
3192 | struct urb *urb, int slot_id, unsigned int ep_index) |
3193 | { | |
5a5a0b1a | 3194 | struct xhci_ring *ring; |
8e51adcc | 3195 | struct urb_priv *urb_priv; |
8a96c052 | 3196 | struct xhci_td *td; |
d2510342 AI |
3197 | struct xhci_generic_trb *start_trb; |
3198 | struct scatterlist *sg = NULL; | |
5a83f04a MN |
3199 | bool more_trbs_coming = true; |
3200 | bool need_zero_pkt = false; | |
86065c27 MN |
3201 | bool first_trb = true; |
3202 | unsigned int num_trbs; | |
d2510342 | 3203 | unsigned int start_cycle, num_sgs = 0; |
86065c27 | 3204 | unsigned int enqd_len, block_len, trb_buff_len, full_len; |
f9c589e1 | 3205 | int sent_len, ret; |
d2510342 | 3206 | u32 field, length_field, remainder; |
f9c589e1 | 3207 | u64 addr, send_addr; |
8a96c052 | 3208 | |
5a5a0b1a MN |
3209 | ring = xhci_urb_to_transfer_ring(xhci, urb); |
3210 | if (!ring) | |
e9df17eb SS |
3211 | return -EINVAL; |
3212 | ||
86065c27 | 3213 | full_len = urb->transfer_buffer_length; |
d2510342 AI |
3214 | /* If we have scatter/gather list, we use it. */ |
3215 | if (urb->num_sgs) { | |
3216 | num_sgs = urb->num_mapped_sgs; | |
3217 | sg = urb->sg; | |
86065c27 MN |
3218 | addr = (u64) sg_dma_address(sg); |
3219 | block_len = sg_dma_len(sg); | |
d2510342 | 3220 | num_trbs = count_sg_trbs_needed(urb); |
86065c27 | 3221 | } else { |
d2510342 | 3222 | num_trbs = count_trbs_needed(urb); |
86065c27 MN |
3223 | addr = (u64) urb->transfer_dma; |
3224 | block_len = full_len; | |
3225 | } | |
4758dcd1 | 3226 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 3227 | ep_index, urb->stream_id, |
3b72fca0 | 3228 | num_trbs, urb, 0, mem_flags); |
d2510342 | 3229 | if (unlikely(ret < 0)) |
4758dcd1 | 3230 | return ret; |
8e51adcc AX |
3231 | |
3232 | urb_priv = urb->hcpriv; | |
4758dcd1 RA |
3233 | |
3234 | /* Deal with URB_ZERO_PACKET - need one more td/trb */ | |
5a83f04a MN |
3235 | if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->length > 1) |
3236 | need_zero_pkt = true; | |
4758dcd1 | 3237 | |
8e51adcc AX |
3238 | td = urb_priv->td[0]; |
3239 | ||
8a96c052 SS |
3240 | /* |
3241 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3242 | * until we've finished creating all the other TRBs. The ring's cycle | |
3243 | * state may change as we enqueue the other TRBs, so save it too. | |
3244 | */ | |
5a5a0b1a MN |
3245 | start_trb = &ring->enqueue->generic; |
3246 | start_cycle = ring->cycle_state; | |
f9c589e1 | 3247 | send_addr = addr; |
8a96c052 | 3248 | |
d2510342 | 3249 | /* Queue the TRBs, even if they are zero-length */ |
0d2daade AB |
3250 | for (enqd_len = 0; first_trb || enqd_len < full_len; |
3251 | enqd_len += trb_buff_len) { | |
d2510342 | 3252 | field = TRB_TYPE(TRB_NORMAL); |
af8b9e63 | 3253 | |
86065c27 MN |
3254 | /* TRB buffer should not cross 64KB boundaries */ |
3255 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); | |
3256 | trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); | |
8a96c052 | 3257 | |
86065c27 MN |
3258 | if (enqd_len + trb_buff_len > full_len) |
3259 | trb_buff_len = full_len - enqd_len; | |
b10de142 SS |
3260 | |
3261 | /* Don't change the cycle bit of the first TRB until later */ | |
86065c27 MN |
3262 | if (first_trb) { |
3263 | first_trb = false; | |
50f7b52a | 3264 | if (start_cycle == 0) |
d2510342 | 3265 | field |= TRB_CYCLE; |
50f7b52a | 3266 | } else |
5a5a0b1a | 3267 | field |= ring->cycle_state; |
b10de142 SS |
3268 | |
3269 | /* Chain all the TRBs together; clear the chain bit in the last | |
3270 | * TRB to indicate it's the last TRB in the chain. | |
3271 | */ | |
86065c27 | 3272 | if (enqd_len + trb_buff_len < full_len) { |
b10de142 | 3273 | field |= TRB_CHAIN; |
2d98ef40 | 3274 | if (trb_is_link(ring->enqueue + 1)) { |
474ed23a | 3275 | if (xhci_align_td(xhci, urb, enqd_len, |
f9c589e1 MN |
3276 | &trb_buff_len, |
3277 | ring->enq_seg)) { | |
3278 | send_addr = ring->enq_seg->bounce_dma; | |
3279 | /* assuming TD won't span 2 segs */ | |
3280 | td->bounce_seg = ring->enq_seg; | |
3281 | } | |
474ed23a | 3282 | } |
f9c589e1 MN |
3283 | } |
3284 | if (enqd_len + trb_buff_len >= full_len) { | |
3285 | field &= ~TRB_CHAIN; | |
4758dcd1 | 3286 | field |= TRB_IOC; |
124c3937 | 3287 | more_trbs_coming = false; |
5a83f04a | 3288 | td->last_trb = ring->enqueue; |
b10de142 | 3289 | } |
af8b9e63 SS |
3290 | |
3291 | /* Only set interrupt on short packet for IN endpoints */ | |
3292 | if (usb_urb_dir_in(urb)) | |
3293 | field |= TRB_ISP; | |
3294 | ||
4da6e6f2 | 3295 | /* Set the TRB length, TD size, and interrupter fields. */ |
86065c27 MN |
3296 | remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, |
3297 | full_len, urb, more_trbs_coming); | |
3298 | ||
f9dc68fe | 3299 | length_field = TRB_LEN(trb_buff_len) | |
c840d6ce | 3300 | TRB_TD_SIZE(remainder) | |
f9dc68fe | 3301 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3302 | |
124c3937 | 3303 | queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, |
f9c589e1 MN |
3304 | lower_32_bits(send_addr), |
3305 | upper_32_bits(send_addr), | |
f9dc68fe | 3306 | length_field, |
d2510342 | 3307 | field); |
b10de142 | 3308 | |
b10de142 | 3309 | addr += trb_buff_len; |
f9c589e1 | 3310 | sent_len = trb_buff_len; |
d2510342 | 3311 | |
f9c589e1 | 3312 | while (sg && sent_len >= block_len) { |
86065c27 MN |
3313 | /* New sg entry */ |
3314 | --num_sgs; | |
f9c589e1 | 3315 | sent_len -= block_len; |
86065c27 | 3316 | if (num_sgs != 0) { |
d2510342 | 3317 | sg = sg_next(sg); |
86065c27 MN |
3318 | block_len = sg_dma_len(sg); |
3319 | addr = (u64) sg_dma_address(sg); | |
f9c589e1 | 3320 | addr += sent_len; |
d2510342 AI |
3321 | } |
3322 | } | |
f9c589e1 MN |
3323 | block_len -= sent_len; |
3324 | send_addr = addr; | |
d2510342 | 3325 | } |
b10de142 | 3326 | |
5a83f04a MN |
3327 | if (need_zero_pkt) { |
3328 | ret = prepare_transfer(xhci, xhci->devs[slot_id], | |
3329 | ep_index, urb->stream_id, | |
3330 | 1, urb, 1, mem_flags); | |
3331 | urb_priv->td[1]->last_trb = ring->enqueue; | |
3332 | field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; | |
3333 | queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); | |
3334 | } | |
3335 | ||
86065c27 | 3336 | check_trb_math(urb, enqd_len); |
e9df17eb | 3337 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3338 | start_cycle, start_trb); |
b10de142 SS |
3339 | return 0; |
3340 | } | |
3341 | ||
d0e96f5a | 3342 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3343 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3344 | struct urb *urb, int slot_id, unsigned int ep_index) |
3345 | { | |
3346 | struct xhci_ring *ep_ring; | |
3347 | int num_trbs; | |
3348 | int ret; | |
3349 | struct usb_ctrlrequest *setup; | |
3350 | struct xhci_generic_trb *start_trb; | |
3351 | int start_cycle; | |
c840d6ce | 3352 | u32 field, length_field, remainder; |
8e51adcc | 3353 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3354 | struct xhci_td *td; |
3355 | ||
e9df17eb SS |
3356 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3357 | if (!ep_ring) | |
3358 | return -EINVAL; | |
d0e96f5a SS |
3359 | |
3360 | /* | |
3361 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3362 | * DMA address. | |
3363 | */ | |
3364 | if (!urb->setup_packet) | |
3365 | return -EINVAL; | |
3366 | ||
d0e96f5a SS |
3367 | /* 1 TRB for setup, 1 for status */ |
3368 | num_trbs = 2; | |
3369 | /* | |
3370 | * Don't need to check if we need additional event data and normal TRBs, | |
3371 | * since data in control transfers will never get bigger than 16MB | |
3372 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3373 | */ | |
3374 | if (urb->transfer_buffer_length > 0) | |
3375 | num_trbs++; | |
e9df17eb SS |
3376 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3377 | ep_index, urb->stream_id, | |
3b72fca0 | 3378 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3379 | if (ret < 0) |
3380 | return ret; | |
3381 | ||
8e51adcc AX |
3382 | urb_priv = urb->hcpriv; |
3383 | td = urb_priv->td[0]; | |
3384 | ||
d0e96f5a SS |
3385 | /* |
3386 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3387 | * until we've finished creating all the other TRBs. The ring's cycle | |
3388 | * state may change as we enqueue the other TRBs, so save it too. | |
3389 | */ | |
3390 | start_trb = &ep_ring->enqueue->generic; | |
3391 | start_cycle = ep_ring->cycle_state; | |
3392 | ||
3393 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3394 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3395 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3396 | field = 0; |
3397 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3398 | if (start_cycle == 0) | |
3399 | field |= 0x1; | |
b83cdc8f | 3400 | |
dca77945 | 3401 | /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ |
0cbd4b34 | 3402 | if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { |
b83cdc8f AX |
3403 | if (urb->transfer_buffer_length > 0) { |
3404 | if (setup->bRequestType & USB_DIR_IN) | |
3405 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3406 | else | |
3407 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3408 | } | |
3409 | } | |
3410 | ||
3b72fca0 | 3411 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3412 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3413 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3414 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3415 | /* Immediate data in pointer */ | |
3416 | field); | |
d0e96f5a SS |
3417 | |
3418 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3419 | /* Only set interrupt on short packet for IN endpoints */ |
3420 | if (usb_urb_dir_in(urb)) | |
3421 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3422 | else | |
3423 | field = TRB_TYPE(TRB_DATA); | |
3424 | ||
c840d6ce MN |
3425 | remainder = xhci_td_remainder(xhci, 0, |
3426 | urb->transfer_buffer_length, | |
3427 | urb->transfer_buffer_length, | |
3428 | urb, 1); | |
3429 | ||
f9dc68fe | 3430 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
c840d6ce | 3431 | TRB_TD_SIZE(remainder) | |
f9dc68fe | 3432 | TRB_INTR_TARGET(0); |
c840d6ce | 3433 | |
d0e96f5a SS |
3434 | if (urb->transfer_buffer_length > 0) { |
3435 | if (setup->bRequestType & USB_DIR_IN) | |
3436 | field |= TRB_DIR_IN; | |
3b72fca0 | 3437 | queue_trb(xhci, ep_ring, true, |
d0e96f5a SS |
3438 | lower_32_bits(urb->transfer_dma), |
3439 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 3440 | length_field, |
af8b9e63 | 3441 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3442 | } |
3443 | ||
3444 | /* Save the DMA address of the last TRB in the TD */ | |
3445 | td->last_trb = ep_ring->enqueue; | |
3446 | ||
3447 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3448 | /* If the device sent data, the status stage is an OUT transfer */ | |
3449 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3450 | field = 0; | |
3451 | else | |
3452 | field = TRB_DIR_IN; | |
3b72fca0 | 3453 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3454 | 0, |
3455 | 0, | |
3456 | TRB_INTR_TARGET(0), | |
3457 | /* Event on completion */ | |
3458 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3459 | ||
e9df17eb | 3460 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3461 | start_cycle, start_trb); |
d0e96f5a SS |
3462 | return 0; |
3463 | } | |
3464 | ||
5cd43e33 SS |
3465 | /* |
3466 | * The transfer burst count field of the isochronous TRB defines the number of | |
3467 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3468 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3469 | * This field is zero based, meaning a value of zero in the field means one | |
3470 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3471 | * zero. Only xHCI 1.0 host controllers support this field. | |
3472 | */ | |
3473 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
5cd43e33 SS |
3474 | struct urb *urb, unsigned int total_packet_count) |
3475 | { | |
3476 | unsigned int max_burst; | |
3477 | ||
09c352ed | 3478 | if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) |
5cd43e33 SS |
3479 | return 0; |
3480 | ||
3481 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3213b151 | 3482 | return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; |
5cd43e33 SS |
3483 | } |
3484 | ||
b61d378f SS |
3485 | /* |
3486 | * Returns the number of packets in the last "burst" of packets. This field is | |
3487 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3488 | * the last burst packet count is equal to the total number of packets in the | |
3489 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3490 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3491 | * contain 1 to (bMaxBurst + 1) packets. | |
3492 | */ | |
3493 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
b61d378f SS |
3494 | struct urb *urb, unsigned int total_packet_count) |
3495 | { | |
3496 | unsigned int max_burst; | |
3497 | unsigned int residue; | |
3498 | ||
3499 | if (xhci->hci_version < 0x100) | |
3500 | return 0; | |
3501 | ||
09c352ed | 3502 | if (urb->dev->speed >= USB_SPEED_SUPER) { |
b61d378f SS |
3503 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ |
3504 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3505 | residue = total_packet_count % (max_burst + 1); | |
3506 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3507 | * number of packets, but the TLBPC field is zero-based. | |
3508 | */ | |
3509 | if (residue == 0) | |
3510 | return max_burst; | |
3511 | return residue - 1; | |
b61d378f | 3512 | } |
09c352ed MN |
3513 | if (total_packet_count == 0) |
3514 | return 0; | |
3515 | return total_packet_count - 1; | |
b61d378f SS |
3516 | } |
3517 | ||
79b8094f LB |
3518 | /* |
3519 | * Calculates Frame ID field of the isochronous TRB identifies the | |
3520 | * target frame that the Interval associated with this Isochronous | |
3521 | * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. | |
3522 | * | |
3523 | * Returns actual frame id on success, negative value on error. | |
3524 | */ | |
3525 | static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, | |
3526 | struct urb *urb, int index) | |
3527 | { | |
3528 | int start_frame, ist, ret = 0; | |
3529 | int start_frame_id, end_frame_id, current_frame_id; | |
3530 | ||
3531 | if (urb->dev->speed == USB_SPEED_LOW || | |
3532 | urb->dev->speed == USB_SPEED_FULL) | |
3533 | start_frame = urb->start_frame + index * urb->interval; | |
3534 | else | |
3535 | start_frame = (urb->start_frame + index * urb->interval) >> 3; | |
3536 | ||
3537 | /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): | |
3538 | * | |
3539 | * If bit [3] of IST is cleared to '0', software can add a TRB no | |
3540 | * later than IST[2:0] Microframes before that TRB is scheduled to | |
3541 | * be executed. | |
3542 | * If bit [3] of IST is set to '1', software can add a TRB no later | |
3543 | * than IST[2:0] Frames before that TRB is scheduled to be executed. | |
3544 | */ | |
3545 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3546 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3547 | ist <<= 3; | |
3548 | ||
3549 | /* Software shall not schedule an Isoch TD with a Frame ID value that | |
3550 | * is less than the Start Frame ID or greater than the End Frame ID, | |
3551 | * where: | |
3552 | * | |
3553 | * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 | |
3554 | * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 | |
3555 | * | |
3556 | * Both the End Frame ID and Start Frame ID values are calculated | |
3557 | * in microframes. When software determines the valid Frame ID value; | |
3558 | * The End Frame ID value should be rounded down to the nearest Frame | |
3559 | * boundary, and the Start Frame ID value should be rounded up to the | |
3560 | * nearest Frame boundary. | |
3561 | */ | |
3562 | current_frame_id = readl(&xhci->run_regs->microframe_index); | |
3563 | start_frame_id = roundup(current_frame_id + ist + 1, 8); | |
3564 | end_frame_id = rounddown(current_frame_id + 895 * 8, 8); | |
3565 | ||
3566 | start_frame &= 0x7ff; | |
3567 | start_frame_id = (start_frame_id >> 3) & 0x7ff; | |
3568 | end_frame_id = (end_frame_id >> 3) & 0x7ff; | |
3569 | ||
3570 | xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", | |
3571 | __func__, index, readl(&xhci->run_regs->microframe_index), | |
3572 | start_frame_id, end_frame_id, start_frame); | |
3573 | ||
3574 | if (start_frame_id < end_frame_id) { | |
3575 | if (start_frame > end_frame_id || | |
3576 | start_frame < start_frame_id) | |
3577 | ret = -EINVAL; | |
3578 | } else if (start_frame_id > end_frame_id) { | |
3579 | if ((start_frame > end_frame_id && | |
3580 | start_frame < start_frame_id)) | |
3581 | ret = -EINVAL; | |
3582 | } else { | |
3583 | ret = -EINVAL; | |
3584 | } | |
3585 | ||
3586 | if (index == 0) { | |
3587 | if (ret == -EINVAL || start_frame == start_frame_id) { | |
3588 | start_frame = start_frame_id + 1; | |
3589 | if (urb->dev->speed == USB_SPEED_LOW || | |
3590 | urb->dev->speed == USB_SPEED_FULL) | |
3591 | urb->start_frame = start_frame; | |
3592 | else | |
3593 | urb->start_frame = start_frame << 3; | |
3594 | ret = 0; | |
3595 | } | |
3596 | } | |
3597 | ||
3598 | if (ret) { | |
3599 | xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", | |
3600 | start_frame, current_frame_id, index, | |
3601 | start_frame_id, end_frame_id); | |
3602 | xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); | |
3603 | return ret; | |
3604 | } | |
3605 | ||
3606 | return start_frame; | |
3607 | } | |
3608 | ||
04e51901 AX |
3609 | /* This is for isoc transfer */ |
3610 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3611 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3612 | { | |
3613 | struct xhci_ring *ep_ring; | |
3614 | struct urb_priv *urb_priv; | |
3615 | struct xhci_td *td; | |
3616 | int num_tds, trbs_per_td; | |
3617 | struct xhci_generic_trb *start_trb; | |
3618 | bool first_trb; | |
3619 | int start_cycle; | |
3620 | u32 field, length_field; | |
3621 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
3622 | u64 start_addr, addr; | |
3623 | int i, j; | |
47cbf692 | 3624 | bool more_trbs_coming; |
79b8094f | 3625 | struct xhci_virt_ep *xep; |
09c352ed | 3626 | int frame_id; |
04e51901 | 3627 | |
79b8094f | 3628 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
3629 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
3630 | ||
3631 | num_tds = urb->number_of_packets; | |
3632 | if (num_tds < 1) { | |
3633 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
3634 | return -EINVAL; | |
3635 | } | |
04e51901 AX |
3636 | start_addr = (u64) urb->transfer_dma; |
3637 | start_trb = &ep_ring->enqueue->generic; | |
3638 | start_cycle = ep_ring->cycle_state; | |
3639 | ||
522989a2 | 3640 | urb_priv = urb->hcpriv; |
09c352ed | 3641 | /* Queue the TRBs for each TD, even if they are zero-length */ |
04e51901 | 3642 | for (i = 0; i < num_tds; i++) { |
09c352ed MN |
3643 | unsigned int total_pkt_count, max_pkt; |
3644 | unsigned int burst_count, last_burst_pkt_count; | |
3645 | u32 sia_frame_id; | |
04e51901 | 3646 | |
4da6e6f2 | 3647 | first_trb = true; |
04e51901 AX |
3648 | running_total = 0; |
3649 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
3650 | td_len = urb->iso_frame_desc[i].length; | |
3651 | td_remain_len = td_len; | |
09c352ed MN |
3652 | max_pkt = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); |
3653 | total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); | |
3654 | ||
48df4a6f | 3655 | /* A zero-length transfer still involves at least one packet. */ |
09c352ed MN |
3656 | if (total_pkt_count == 0) |
3657 | total_pkt_count++; | |
3658 | burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); | |
3659 | last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, | |
3660 | urb, total_pkt_count); | |
04e51901 | 3661 | |
d2510342 | 3662 | trbs_per_td = count_isoc_trbs_needed(urb, i); |
04e51901 AX |
3663 | |
3664 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 3665 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
3666 | if (ret < 0) { |
3667 | if (i == 0) | |
3668 | return ret; | |
3669 | goto cleanup; | |
3670 | } | |
04e51901 | 3671 | td = urb_priv->td[i]; |
09c352ed MN |
3672 | |
3673 | /* use SIA as default, if frame id is used overwrite it */ | |
3674 | sia_frame_id = TRB_SIA; | |
3675 | if (!(urb->transfer_flags & URB_ISO_ASAP) && | |
3676 | HCC_CFC(xhci->hcc_params)) { | |
3677 | frame_id = xhci_get_isoc_frame_id(xhci, urb, i); | |
3678 | if (frame_id >= 0) | |
3679 | sia_frame_id = TRB_FRAME_ID(frame_id); | |
3680 | } | |
3681 | /* | |
3682 | * Set isoc specific data for the first TRB in a TD. | |
3683 | * Prevent HW from getting the TRBs by keeping the cycle state | |
3684 | * inverted in the first TDs isoc TRB. | |
3685 | */ | |
2f6d3b65 | 3686 | field = TRB_TYPE(TRB_ISOC) | |
09c352ed MN |
3687 | TRB_TLBPC(last_burst_pkt_count) | |
3688 | sia_frame_id | | |
3689 | (i ? ep_ring->cycle_state : !start_cycle); | |
3690 | ||
2f6d3b65 MN |
3691 | /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ |
3692 | if (!xep->use_extended_tbc) | |
3693 | field |= TRB_TBC(burst_count); | |
3694 | ||
09c352ed | 3695 | /* fill the rest of the TRB fields, and remaining normal TRBs */ |
04e51901 AX |
3696 | for (j = 0; j < trbs_per_td; j++) { |
3697 | u32 remainder = 0; | |
09c352ed MN |
3698 | |
3699 | /* only first TRB is isoc, overwrite otherwise */ | |
3700 | if (!first_trb) | |
3701 | field = TRB_TYPE(TRB_NORMAL) | | |
3702 | ep_ring->cycle_state; | |
04e51901 | 3703 | |
af8b9e63 SS |
3704 | /* Only set interrupt on short packet for IN EPs */ |
3705 | if (usb_urb_dir_in(urb)) | |
3706 | field |= TRB_ISP; | |
3707 | ||
09c352ed | 3708 | /* Set the chain bit for all except the last TRB */ |
04e51901 | 3709 | if (j < trbs_per_td - 1) { |
47cbf692 | 3710 | more_trbs_coming = true; |
09c352ed | 3711 | field |= TRB_CHAIN; |
04e51901 | 3712 | } else { |
09c352ed | 3713 | more_trbs_coming = false; |
04e51901 AX |
3714 | td->last_trb = ep_ring->enqueue; |
3715 | field |= TRB_IOC; | |
09c352ed MN |
3716 | /* set BEI, except for the last TD */ |
3717 | if (xhci->hci_version >= 0x100 && | |
3718 | !(xhci->quirks & XHCI_AVOID_BEI) && | |
3719 | i < num_tds - 1) | |
3720 | field |= TRB_BEI; | |
04e51901 | 3721 | } |
04e51901 | 3722 | /* Calculate TRB length */ |
d2510342 | 3723 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); |
04e51901 AX |
3724 | if (trb_buff_len > td_remain_len) |
3725 | trb_buff_len = td_remain_len; | |
3726 | ||
4da6e6f2 | 3727 | /* Set the TRB length, TD size, & interrupter fields. */ |
c840d6ce MN |
3728 | remainder = xhci_td_remainder(xhci, running_total, |
3729 | trb_buff_len, td_len, | |
124c3937 | 3730 | urb, more_trbs_coming); |
c840d6ce | 3731 | |
04e51901 | 3732 | length_field = TRB_LEN(trb_buff_len) | |
04e51901 | 3733 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3734 | |
2f6d3b65 MN |
3735 | /* xhci 1.1 with ETE uses TD Size field for TBC */ |
3736 | if (first_trb && xep->use_extended_tbc) | |
3737 | length_field |= TRB_TD_SIZE_TBC(burst_count); | |
3738 | else | |
3739 | length_field |= TRB_TD_SIZE(remainder); | |
3740 | first_trb = false; | |
3741 | ||
3b72fca0 | 3742 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
3743 | lower_32_bits(addr), |
3744 | upper_32_bits(addr), | |
3745 | length_field, | |
af8b9e63 | 3746 | field); |
04e51901 AX |
3747 | running_total += trb_buff_len; |
3748 | ||
3749 | addr += trb_buff_len; | |
3750 | td_remain_len -= trb_buff_len; | |
3751 | } | |
3752 | ||
3753 | /* Check TD length */ | |
3754 | if (running_total != td_len) { | |
3755 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
3756 | ret = -EINVAL; |
3757 | goto cleanup; | |
04e51901 AX |
3758 | } |
3759 | } | |
3760 | ||
79b8094f LB |
3761 | /* store the next frame id */ |
3762 | if (HCC_CFC(xhci->hcc_params)) | |
3763 | xep->next_frame_id = urb->start_frame + num_tds * urb->interval; | |
3764 | ||
c41136b0 AX |
3765 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
3766 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
3767 | usb_amd_quirk_pll_disable(); | |
3768 | } | |
3769 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
3770 | ||
e1eab2e0 AX |
3771 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3772 | start_cycle, start_trb); | |
04e51901 | 3773 | return 0; |
522989a2 SS |
3774 | cleanup: |
3775 | /* Clean up a partially enqueued isoc transfer. */ | |
3776 | ||
3777 | for (i--; i >= 0; i--) | |
585df1d9 | 3778 | list_del_init(&urb_priv->td[i]->td_list); |
522989a2 SS |
3779 | |
3780 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
3781 | * into No-ops with a software-owned cycle bit. That way the hardware | |
3782 | * won't accidentally start executing bogus TDs when we partially | |
3783 | * overwrite them. td->first_trb and td->start_seg are already set. | |
3784 | */ | |
3785 | urb_priv->td[0]->last_trb = ep_ring->enqueue; | |
3786 | /* Every TRB except the first & last will have its cycle bit flipped. */ | |
3787 | td_to_noop(xhci, ep_ring, urb_priv->td[0], true); | |
3788 | ||
3789 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
3790 | ep_ring->enqueue = urb_priv->td[0]->first_trb; | |
3791 | ep_ring->enq_seg = urb_priv->td[0]->start_seg; | |
3792 | ep_ring->cycle_state = start_cycle; | |
b008df60 | 3793 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
3794 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
3795 | return ret; | |
04e51901 AX |
3796 | } |
3797 | ||
3798 | /* | |
3799 | * Check transfer ring to guarantee there is enough room for the urb. | |
3800 | * Update ISO URB start_frame and interval. | |
79b8094f LB |
3801 | * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to |
3802 | * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or | |
3803 | * Contiguous Frame ID is not supported by HC. | |
04e51901 AX |
3804 | */ |
3805 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3806 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3807 | { | |
3808 | struct xhci_virt_device *xdev; | |
3809 | struct xhci_ring *ep_ring; | |
3810 | struct xhci_ep_ctx *ep_ctx; | |
3811 | int start_frame; | |
04e51901 AX |
3812 | int num_tds, num_trbs, i; |
3813 | int ret; | |
79b8094f LB |
3814 | struct xhci_virt_ep *xep; |
3815 | int ist; | |
04e51901 AX |
3816 | |
3817 | xdev = xhci->devs[slot_id]; | |
79b8094f | 3818 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
3819 | ep_ring = xdev->eps[ep_index].ring; |
3820 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3821 | ||
3822 | num_trbs = 0; | |
3823 | num_tds = urb->number_of_packets; | |
3824 | for (i = 0; i < num_tds; i++) | |
d2510342 | 3825 | num_trbs += count_isoc_trbs_needed(urb, i); |
04e51901 AX |
3826 | |
3827 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3828 | * Do not insert any td of the urb to the ring if the check failed. | |
3829 | */ | |
28ccd296 | 3830 | ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3b72fca0 | 3831 | num_trbs, mem_flags); |
04e51901 AX |
3832 | if (ret) |
3833 | return ret; | |
3834 | ||
79b8094f LB |
3835 | /* |
3836 | * Check interval value. This should be done before we start to | |
3837 | * calculate the start frame value. | |
3838 | */ | |
78140156 | 3839 | check_interval(xhci, urb, ep_ctx); |
79b8094f LB |
3840 | |
3841 | /* Calculate the start frame and put it in urb->start_frame. */ | |
42df7215 LB |
3842 | if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { |
3843 | if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == | |
3844 | EP_STATE_RUNNING) { | |
3845 | urb->start_frame = xep->next_frame_id; | |
3846 | goto skip_start_over; | |
3847 | } | |
79b8094f LB |
3848 | } |
3849 | ||
3850 | start_frame = readl(&xhci->run_regs->microframe_index); | |
3851 | start_frame &= 0x3fff; | |
3852 | /* | |
3853 | * Round up to the next frame and consider the time before trb really | |
3854 | * gets scheduled by hardare. | |
3855 | */ | |
3856 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3857 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3858 | ist <<= 3; | |
3859 | start_frame += ist + XHCI_CFC_DELAY; | |
3860 | start_frame = roundup(start_frame, 8); | |
3861 | ||
3862 | /* | |
3863 | * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT | |
3864 | * is greate than 8 microframes. | |
3865 | */ | |
3866 | if (urb->dev->speed == USB_SPEED_LOW || | |
3867 | urb->dev->speed == USB_SPEED_FULL) { | |
3868 | start_frame = roundup(start_frame, urb->interval << 3); | |
3869 | urb->start_frame = start_frame >> 3; | |
3870 | } else { | |
3871 | start_frame = roundup(start_frame, urb->interval); | |
3872 | urb->start_frame = start_frame; | |
3873 | } | |
3874 | ||
3875 | skip_start_over: | |
b008df60 AX |
3876 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
3877 | ||
3fc8206d | 3878 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
3879 | } |
3880 | ||
d0e96f5a SS |
3881 | /**** Command Ring Operations ****/ |
3882 | ||
913a8a34 SS |
3883 | /* Generic function for queueing a command TRB on the command ring. |
3884 | * Check to make sure there's room on the command ring for one command TRB. | |
3885 | * Also check that there's room reserved for commands that must not fail. | |
3886 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
3887 | * then only check for the number of reserved spots. | |
3888 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
3889 | * because the command event handler may want to resubmit a failed command. | |
3890 | */ | |
ddba5cd0 MN |
3891 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3892 | u32 field1, u32 field2, | |
3893 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 3894 | { |
913a8a34 | 3895 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a | 3896 | int ret; |
ad6b1d91 | 3897 | |
98d74f9c MN |
3898 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
3899 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
ad6b1d91 | 3900 | xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); |
c9aa1a2d | 3901 | return -ESHUTDOWN; |
ad6b1d91 | 3902 | } |
d1dc908a | 3903 | |
913a8a34 SS |
3904 | if (!command_must_succeed) |
3905 | reserved_trbs++; | |
3906 | ||
d1dc908a | 3907 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 3908 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
3909 | if (ret < 0) { |
3910 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
3911 | if (command_must_succeed) |
3912 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
3913 | "unfailable commands failed.\n"); | |
d1dc908a | 3914 | return ret; |
7f84eef0 | 3915 | } |
c9aa1a2d MN |
3916 | |
3917 | cmd->command_trb = xhci->cmd_ring->enqueue; | |
3918 | list_add_tail(&cmd->cmd_list, &xhci->cmd_list); | |
ddba5cd0 | 3919 | |
c311e391 MN |
3920 | /* if there are no other commands queued we start the timeout timer */ |
3921 | if (xhci->cmd_list.next == &cmd->cmd_list && | |
3922 | !timer_pending(&xhci->cmd_timer)) { | |
3923 | xhci->current_cmd = cmd; | |
3924 | mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT); | |
3925 | } | |
3926 | ||
3b72fca0 AX |
3927 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
3928 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
3929 | return 0; |
3930 | } | |
3931 | ||
3ffbba95 | 3932 | /* Queue a slot enable or disable request on the command ring */ |
ddba5cd0 MN |
3933 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3934 | u32 trb_type, u32 slot_id) | |
3ffbba95 | 3935 | { |
ddba5cd0 | 3936 | return queue_command(xhci, cmd, 0, 0, 0, |
913a8a34 | 3937 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
3938 | } |
3939 | ||
3940 | /* Queue an address device command TRB */ | |
ddba5cd0 MN |
3941 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3942 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) | |
3ffbba95 | 3943 | { |
ddba5cd0 | 3944 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3945 | upper_32_bits(in_ctx_ptr), 0, |
48fc7dbd DW |
3946 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
3947 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); | |
2a8f82c4 SS |
3948 | } |
3949 | ||
ddba5cd0 | 3950 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
0238634d SS |
3951 | u32 field1, u32 field2, u32 field3, u32 field4) |
3952 | { | |
ddba5cd0 | 3953 | return queue_command(xhci, cmd, field1, field2, field3, field4, false); |
0238634d SS |
3954 | } |
3955 | ||
2a8f82c4 | 3956 | /* Queue a reset device command TRB */ |
ddba5cd0 MN |
3957 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3958 | u32 slot_id) | |
2a8f82c4 | 3959 | { |
ddba5cd0 | 3960 | return queue_command(xhci, cmd, 0, 0, 0, |
2a8f82c4 | 3961 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
913a8a34 | 3962 | false); |
3ffbba95 | 3963 | } |
f94e0186 SS |
3964 | |
3965 | /* Queue a configure endpoint command TRB */ | |
ddba5cd0 MN |
3966 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
3967 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, | |
913a8a34 | 3968 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 3969 | { |
ddba5cd0 | 3970 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3971 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 SS |
3972 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
3973 | command_must_succeed); | |
f94e0186 | 3974 | } |
ae636747 | 3975 | |
f2217e8e | 3976 | /* Queue an evaluate context command TRB */ |
ddba5cd0 MN |
3977 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3978 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) | |
f2217e8e | 3979 | { |
ddba5cd0 | 3980 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
f2217e8e | 3981 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 | 3982 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 3983 | command_must_succeed); |
f2217e8e SS |
3984 | } |
3985 | ||
be88fe4f AX |
3986 | /* |
3987 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
3988 | * activity on an endpoint that is about to be suspended. | |
3989 | */ | |
ddba5cd0 MN |
3990 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3991 | int slot_id, unsigned int ep_index, int suspend) | |
ae636747 SS |
3992 | { |
3993 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3994 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3995 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 3996 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 | 3997 | |
ddba5cd0 | 3998 | return queue_command(xhci, cmd, 0, 0, 0, |
be88fe4f | 3999 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
4000 | } |
4001 | ||
d3a43e66 HG |
4002 | /* Set Transfer Ring Dequeue Pointer command */ |
4003 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, | |
4004 | unsigned int slot_id, unsigned int ep_index, | |
4005 | unsigned int stream_id, | |
4006 | struct xhci_dequeue_state *deq_state) | |
ae636747 SS |
4007 | { |
4008 | dma_addr_t addr; | |
4009 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4010 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
e9df17eb | 4011 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
95241dbd | 4012 | u32 trb_sct = 0; |
ae636747 | 4013 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
bf161e85 | 4014 | struct xhci_virt_ep *ep; |
1e3452e3 HG |
4015 | struct xhci_command *cmd; |
4016 | int ret; | |
ae636747 | 4017 | |
d3a43e66 HG |
4018 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
4019 | "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u", | |
4020 | deq_state->new_deq_seg, | |
4021 | (unsigned long long)deq_state->new_deq_seg->dma, | |
4022 | deq_state->new_deq_ptr, | |
4023 | (unsigned long long)xhci_trb_virt_to_dma( | |
4024 | deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
4025 | deq_state->new_cycle_state); | |
4026 | ||
4027 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
4028 | deq_state->new_deq_ptr); | |
c92bcfa7 | 4029 | if (addr == 0) { |
ae636747 | 4030 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 | 4031 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
d3a43e66 HG |
4032 | deq_state->new_deq_seg, deq_state->new_deq_ptr); |
4033 | return; | |
c92bcfa7 | 4034 | } |
bf161e85 SS |
4035 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
4036 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
4037 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | |
4038 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | |
d3a43e66 | 4039 | return; |
bf161e85 | 4040 | } |
1e3452e3 HG |
4041 | |
4042 | /* This function gets called from contexts where it cannot sleep */ | |
4043 | cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
4044 | if (!cmd) { | |
4045 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n"); | |
d3a43e66 | 4046 | return; |
1e3452e3 HG |
4047 | } |
4048 | ||
d3a43e66 HG |
4049 | ep->queued_deq_seg = deq_state->new_deq_seg; |
4050 | ep->queued_deq_ptr = deq_state->new_deq_ptr; | |
95241dbd HG |
4051 | if (stream_id) |
4052 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); | |
1e3452e3 | 4053 | ret = queue_command(xhci, cmd, |
d3a43e66 HG |
4054 | lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state, |
4055 | upper_32_bits(addr), trb_stream_id, | |
4056 | trb_slot_id | trb_ep_index | type, false); | |
1e3452e3 HG |
4057 | if (ret < 0) { |
4058 | xhci_free_command(xhci, cmd); | |
d3a43e66 | 4059 | return; |
1e3452e3 HG |
4060 | } |
4061 | ||
d3a43e66 HG |
4062 | /* Stop the TD queueing code from ringing the doorbell until |
4063 | * this command completes. The HC won't set the dequeue pointer | |
4064 | * if the ring is running, and ringing the doorbell starts the | |
4065 | * ring running. | |
4066 | */ | |
4067 | ep->ep_state |= SET_DEQ_PENDING; | |
ae636747 | 4068 | } |
a1587d97 | 4069 | |
ddba5cd0 MN |
4070 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4071 | int slot_id, unsigned int ep_index) | |
a1587d97 SS |
4072 | { |
4073 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4074 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4075 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
4076 | ||
ddba5cd0 MN |
4077 | return queue_command(xhci, cmd, 0, 0, 0, |
4078 | trb_slot_id | trb_ep_index | type, false); | |
a1587d97 | 4079 | } |