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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
7f84eef0 SS |
69 | #include "xhci.h" |
70 | ||
be88fe4f AX |
71 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, |
72 | struct xhci_virt_device *virt_dev, | |
73 | struct xhci_event_cmd *event); | |
74 | ||
7f84eef0 SS |
75 | /* |
76 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
77 | * address of the TRB. | |
78 | */ | |
23e3be11 | 79 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
80 | union xhci_trb *trb) |
81 | { | |
6071d836 | 82 | unsigned long segment_offset; |
7f84eef0 | 83 | |
6071d836 | 84 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 85 | return 0; |
6071d836 SS |
86 | /* offset in TRBs */ |
87 | segment_offset = trb - seg->trbs; | |
88 | if (segment_offset > TRBS_PER_SEGMENT) | |
7f84eef0 | 89 | return 0; |
6071d836 | 90 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
91 | } |
92 | ||
93 | /* Does this link TRB point to the first segment in a ring, | |
94 | * or was the previous TRB the last TRB on the last segment in the ERST? | |
95 | */ | |
575688e1 | 96 | static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
97 | struct xhci_segment *seg, union xhci_trb *trb) |
98 | { | |
99 | if (ring == xhci->event_ring) | |
100 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && | |
101 | (seg->next == xhci->event_ring->first_seg); | |
102 | else | |
28ccd296 | 103 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; |
7f84eef0 SS |
104 | } |
105 | ||
106 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring | |
107 | * segment? I.e. would the updated event TRB pointer step off the end of the | |
108 | * event seg? | |
109 | */ | |
575688e1 | 110 | static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
111 | struct xhci_segment *seg, union xhci_trb *trb) |
112 | { | |
113 | if (ring == xhci->event_ring) | |
114 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; | |
115 | else | |
f5960b69 | 116 | return TRB_TYPE_LINK_LE32(trb->link.control); |
7f84eef0 SS |
117 | } |
118 | ||
575688e1 | 119 | static int enqueue_is_link_trb(struct xhci_ring *ring) |
6c12db90 JY |
120 | { |
121 | struct xhci_link_trb *link = &ring->enqueue->link; | |
f5960b69 | 122 | return TRB_TYPE_LINK_LE32(link->control); |
6c12db90 JY |
123 | } |
124 | ||
ae636747 SS |
125 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
126 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
127 | * effect the ring dequeue or enqueue pointers. | |
128 | */ | |
129 | static void next_trb(struct xhci_hcd *xhci, | |
130 | struct xhci_ring *ring, | |
131 | struct xhci_segment **seg, | |
132 | union xhci_trb **trb) | |
133 | { | |
134 | if (last_trb(xhci, ring, *seg, *trb)) { | |
135 | *seg = (*seg)->next; | |
136 | *trb = ((*seg)->trbs); | |
137 | } else { | |
a1669b2c | 138 | (*trb)++; |
ae636747 SS |
139 | } |
140 | } | |
141 | ||
7f84eef0 SS |
142 | /* |
143 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
144 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
145 | */ | |
3b72fca0 | 146 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 147 | { |
66e49d87 | 148 | unsigned long long addr; |
7f84eef0 SS |
149 | |
150 | ring->deq_updates++; | |
b008df60 | 151 | |
50d0206f SS |
152 | /* |
153 | * If this is not event ring, and the dequeue pointer | |
154 | * is not on a link TRB, there is one more usable TRB | |
155 | */ | |
b008df60 AX |
156 | if (ring->type != TYPE_EVENT && |
157 | !last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) | |
158 | ring->num_trbs_free++; | |
b008df60 | 159 | |
50d0206f SS |
160 | do { |
161 | /* | |
162 | * Update the dequeue pointer further if that was a link TRB or | |
163 | * we're at the end of an event ring segment (which doesn't have | |
164 | * link TRBS) | |
165 | */ | |
166 | if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) { | |
167 | if (ring->type == TYPE_EVENT && | |
168 | last_trb_on_last_seg(xhci, ring, | |
169 | ring->deq_seg, ring->dequeue)) { | |
170 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
171 | } | |
172 | ring->deq_seg = ring->deq_seg->next; | |
173 | ring->dequeue = ring->deq_seg->trbs; | |
174 | } else { | |
175 | ring->dequeue++; | |
7f84eef0 | 176 | } |
50d0206f SS |
177 | } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)); |
178 | ||
66e49d87 | 179 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue); |
7f84eef0 SS |
180 | } |
181 | ||
182 | /* | |
183 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
184 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
185 | * | |
186 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
187 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
188 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
189 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
190 | * | |
191 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
192 | * set, but other sections talk about dealing with the chain bit set. This was |
193 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
194 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
195 | * |
196 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
197 | * prepare_transfer()? | |
7f84eef0 | 198 | */ |
6cc30d85 | 199 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 200 | bool more_trbs_coming) |
7f84eef0 SS |
201 | { |
202 | u32 chain; | |
203 | union xhci_trb *next; | |
66e49d87 | 204 | unsigned long long addr; |
7f84eef0 | 205 | |
28ccd296 | 206 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 AX |
207 | /* If this is not event ring, there is one less usable TRB */ |
208 | if (ring->type != TYPE_EVENT && | |
209 | !last_trb(xhci, ring, ring->enq_seg, ring->enqueue)) | |
210 | ring->num_trbs_free--; | |
7f84eef0 SS |
211 | next = ++(ring->enqueue); |
212 | ||
213 | ring->enq_updates++; | |
214 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
215 | * the end of an event ring segment (which doesn't have link TRBS) | |
216 | */ | |
217 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
3b72fca0 AX |
218 | if (ring->type != TYPE_EVENT) { |
219 | /* | |
220 | * If the caller doesn't plan on enqueueing more | |
221 | * TDs before ringing the doorbell, then we | |
222 | * don't want to give the link TRB to the | |
223 | * hardware just yet. We'll give the link TRB | |
224 | * back in prepare_ring() just before we enqueue | |
225 | * the TD at the top of the ring. | |
226 | */ | |
227 | if (!chain && !more_trbs_coming) | |
228 | break; | |
6cc30d85 | 229 | |
3b72fca0 AX |
230 | /* If we're not dealing with 0.95 hardware or |
231 | * isoc rings on AMD 0.96 host, | |
232 | * carry over the chain bit of the previous TRB | |
233 | * (which may mean the chain bit is cleared). | |
234 | */ | |
235 | if (!(ring->type == TYPE_ISOC && | |
236 | (xhci->quirks & XHCI_AMD_0x96_HOST)) | |
7e393a83 | 237 | && !xhci_link_trb_quirk(xhci)) { |
3b72fca0 AX |
238 | next->link.control &= |
239 | cpu_to_le32(~TRB_CHAIN); | |
240 | next->link.control |= | |
241 | cpu_to_le32(chain); | |
7f84eef0 | 242 | } |
3b72fca0 AX |
243 | /* Give this link TRB to the hardware */ |
244 | wmb(); | |
245 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
246 | ||
7f84eef0 SS |
247 | /* Toggle the cycle bit after the last ring segment. */ |
248 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
249 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
7f84eef0 SS |
250 | } |
251 | } | |
252 | ring->enq_seg = ring->enq_seg->next; | |
253 | ring->enqueue = ring->enq_seg->trbs; | |
254 | next = ring->enqueue; | |
255 | } | |
66e49d87 | 256 | addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue); |
7f84eef0 SS |
257 | } |
258 | ||
259 | /* | |
085deb16 AX |
260 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
261 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 262 | */ |
b008df60 | 263 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
264 | unsigned int num_trbs) |
265 | { | |
085deb16 | 266 | int num_trbs_in_deq_seg; |
b008df60 | 267 | |
085deb16 AX |
268 | if (ring->num_trbs_free < num_trbs) |
269 | return 0; | |
270 | ||
271 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
272 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
273 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
274 | return 0; | |
275 | } | |
276 | ||
277 | return 1; | |
7f84eef0 SS |
278 | } |
279 | ||
7f84eef0 | 280 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 281 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 282 | { |
c181bc5b EF |
283 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
284 | return; | |
285 | ||
7f84eef0 | 286 | xhci_dbg(xhci, "// Ding dong!\n"); |
50d64676 | 287 | xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 SS |
288 | /* Flush PCI posted writes */ |
289 | xhci_readl(xhci, &xhci->dba->doorbell[0]); | |
290 | } | |
291 | ||
be88fe4f | 292 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 293 | unsigned int slot_id, |
e9df17eb SS |
294 | unsigned int ep_index, |
295 | unsigned int stream_id) | |
ae636747 | 296 | { |
28ccd296 | 297 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
298 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
299 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 300 | |
ae636747 | 301 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 302 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
303 | * We don't want to restart any stream rings if there's a set dequeue |
304 | * pointer command pending because the device can choose to start any | |
305 | * stream once the endpoint is on the HW schedule. | |
306 | * FIXME - check all the stream rings for pending cancellations. | |
ae636747 | 307 | */ |
50d64676 MW |
308 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
309 | (ep_state & EP_HALTED)) | |
310 | return; | |
311 | xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr); | |
312 | /* The CPU has better things to do at this point than wait for a | |
313 | * write-posting flush. It'll get there soon enough. | |
314 | */ | |
ae636747 SS |
315 | } |
316 | ||
e9df17eb SS |
317 | /* Ring the doorbell for any rings with pending URBs */ |
318 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
319 | unsigned int slot_id, | |
320 | unsigned int ep_index) | |
321 | { | |
322 | unsigned int stream_id; | |
323 | struct xhci_virt_ep *ep; | |
324 | ||
325 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
326 | ||
327 | /* A ring has pending URBs if its TD list is not empty */ | |
328 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
329 | if (!(list_empty(&ep->ring->td_list))) | |
be88fe4f | 330 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
331 | return; |
332 | } | |
333 | ||
334 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
335 | stream_id++) { | |
336 | struct xhci_stream_info *stream_info = ep->stream_info; | |
337 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
338 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
339 | stream_id); | |
e9df17eb SS |
340 | } |
341 | } | |
342 | ||
ae636747 SS |
343 | /* |
344 | * Find the segment that trb is in. Start searching in start_seg. | |
345 | * If we must move past a segment that has a link TRB with a toggle cycle state | |
346 | * bit set, then we will toggle the value pointed at by cycle_state. | |
347 | */ | |
348 | static struct xhci_segment *find_trb_seg( | |
349 | struct xhci_segment *start_seg, | |
350 | union xhci_trb *trb, int *cycle_state) | |
351 | { | |
352 | struct xhci_segment *cur_seg = start_seg; | |
353 | struct xhci_generic_trb *generic_trb; | |
354 | ||
355 | while (cur_seg->trbs > trb || | |
356 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { | |
357 | generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; | |
f5960b69 | 358 | if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE)) |
ba0a4d9a | 359 | *cycle_state ^= 0x1; |
ae636747 SS |
360 | cur_seg = cur_seg->next; |
361 | if (cur_seg == start_seg) | |
362 | /* Looped over the entire list. Oops! */ | |
326b4810 | 363 | return NULL; |
ae636747 SS |
364 | } |
365 | return cur_seg; | |
366 | } | |
367 | ||
021bff91 SS |
368 | |
369 | static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
370 | unsigned int slot_id, unsigned int ep_index, | |
371 | unsigned int stream_id) | |
372 | { | |
373 | struct xhci_virt_ep *ep; | |
374 | ||
375 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
376 | /* Common case: no streams */ | |
377 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
378 | return ep->ring; | |
379 | ||
380 | if (stream_id == 0) { | |
381 | xhci_warn(xhci, | |
382 | "WARN: Slot ID %u, ep index %u has streams, " | |
383 | "but URB has no stream ID.\n", | |
384 | slot_id, ep_index); | |
385 | return NULL; | |
386 | } | |
387 | ||
388 | if (stream_id < ep->stream_info->num_streams) | |
389 | return ep->stream_info->stream_rings[stream_id]; | |
390 | ||
391 | xhci_warn(xhci, | |
392 | "WARN: Slot ID %u, ep index %u has " | |
393 | "stream IDs 1 to %u allocated, " | |
394 | "but stream ID %u is requested.\n", | |
395 | slot_id, ep_index, | |
396 | ep->stream_info->num_streams - 1, | |
397 | stream_id); | |
398 | return NULL; | |
399 | } | |
400 | ||
401 | /* Get the right ring for the given URB. | |
402 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
403 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
404 | */ | |
405 | static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, | |
406 | struct urb *urb) | |
407 | { | |
408 | return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, | |
409 | xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id); | |
410 | } | |
411 | ||
ae636747 SS |
412 | /* |
413 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
414 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
415 | * dequeue pointer, and new consumer cycle state in state. | |
416 | * Update our internal representation of the ring's dequeue pointer. | |
417 | * | |
418 | * We do this in three jumps: | |
419 | * - First we update our new ring state to be the same as when the xHC stopped. | |
420 | * - Then we traverse the ring to find the segment that contains | |
421 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
422 | * any link TRBs with the toggle cycle bit set. | |
423 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
424 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
28ccd296 ME |
425 | * |
426 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | |
427 | * with correct __le32 accesses they should work fine. Only users of this are | |
428 | * in here. | |
ae636747 | 429 | */ |
c92bcfa7 | 430 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 431 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
432 | unsigned int stream_id, struct xhci_td *cur_td, |
433 | struct xhci_dequeue_state *state) | |
ae636747 SS |
434 | { |
435 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
e9df17eb | 436 | struct xhci_ring *ep_ring; |
ae636747 | 437 | struct xhci_generic_trb *trb; |
d115b048 | 438 | struct xhci_ep_ctx *ep_ctx; |
c92bcfa7 | 439 | dma_addr_t addr; |
ae636747 | 440 | |
e9df17eb SS |
441 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
442 | ep_index, stream_id); | |
443 | if (!ep_ring) { | |
444 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
445 | "for invalid stream ID %u.\n", | |
446 | stream_id); | |
447 | return; | |
448 | } | |
ae636747 | 449 | state->new_cycle_state = 0; |
c92bcfa7 | 450 | xhci_dbg(xhci, "Finding segment containing stopped TRB.\n"); |
ae636747 | 451 | state->new_deq_seg = find_trb_seg(cur_td->start_seg, |
63a0d9ab | 452 | dev->eps[ep_index].stopped_trb, |
ae636747 | 453 | &state->new_cycle_state); |
68e41c5d PZ |
454 | if (!state->new_deq_seg) { |
455 | WARN_ON(1); | |
456 | return; | |
457 | } | |
458 | ||
ae636747 | 459 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
c92bcfa7 | 460 | xhci_dbg(xhci, "Finding endpoint context\n"); |
d115b048 | 461 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
28ccd296 | 462 | state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq); |
ae636747 SS |
463 | |
464 | state->new_deq_ptr = cur_td->last_trb; | |
c92bcfa7 | 465 | xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n"); |
ae636747 SS |
466 | state->new_deq_seg = find_trb_seg(state->new_deq_seg, |
467 | state->new_deq_ptr, | |
468 | &state->new_cycle_state); | |
68e41c5d PZ |
469 | if (!state->new_deq_seg) { |
470 | WARN_ON(1); | |
471 | return; | |
472 | } | |
ae636747 SS |
473 | |
474 | trb = &state->new_deq_ptr->generic; | |
f5960b69 ME |
475 | if (TRB_TYPE_LINK_LE32(trb->field[3]) && |
476 | (trb->field[3] & cpu_to_le32(LINK_TOGGLE))) | |
ba0a4d9a | 477 | state->new_cycle_state ^= 0x1; |
ae636747 SS |
478 | next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); |
479 | ||
01a1fdb9 SS |
480 | /* |
481 | * If there is only one segment in a ring, find_trb_seg()'s while loop | |
482 | * will not run, and it will return before it has a chance to see if it | |
483 | * needs to toggle the cycle bit. It can't tell if the stalled transfer | |
484 | * ended just before the link TRB on a one-segment ring, or if the TD | |
485 | * wrapped around the top of the ring, because it doesn't have the TD in | |
486 | * question. Look for the one-segment case where stalled TRB's address | |
487 | * is greater than the new dequeue pointer address. | |
488 | */ | |
489 | if (ep_ring->first_seg == ep_ring->first_seg->next && | |
490 | state->new_deq_ptr < dev->eps[ep_index].stopped_trb) | |
491 | state->new_cycle_state ^= 0x1; | |
492 | xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state); | |
493 | ||
ae636747 | 494 | /* Don't update the ring cycle state for the producer (us). */ |
c92bcfa7 SS |
495 | xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n", |
496 | state->new_deq_seg); | |
497 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
498 | xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n", | |
499 | (unsigned long long) addr); | |
ae636747 SS |
500 | } |
501 | ||
522989a2 SS |
502 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
503 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
504 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
505 | */ | |
23e3be11 | 506 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
522989a2 | 507 | struct xhci_td *cur_td, bool flip_cycle) |
ae636747 SS |
508 | { |
509 | struct xhci_segment *cur_seg; | |
510 | union xhci_trb *cur_trb; | |
511 | ||
512 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; | |
513 | true; | |
514 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 | 515 | if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) { |
ae636747 SS |
516 | /* Unchain any chained Link TRBs, but |
517 | * leave the pointers intact. | |
518 | */ | |
28ccd296 | 519 | cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN); |
522989a2 SS |
520 | /* Flip the cycle bit (link TRBs can't be the first |
521 | * or last TRB). | |
522 | */ | |
523 | if (flip_cycle) | |
524 | cur_trb->generic.field[3] ^= | |
525 | cpu_to_le32(TRB_CYCLE); | |
ae636747 | 526 | xhci_dbg(xhci, "Cancel (unchain) link TRB\n"); |
700e2052 GKH |
527 | xhci_dbg(xhci, "Address = %p (0x%llx dma); " |
528 | "in seg %p (0x%llx dma)\n", | |
529 | cur_trb, | |
23e3be11 | 530 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
531 | cur_seg, |
532 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
533 | } else { |
534 | cur_trb->generic.field[0] = 0; | |
535 | cur_trb->generic.field[1] = 0; | |
536 | cur_trb->generic.field[2] = 0; | |
537 | /* Preserve only the cycle bit of this TRB */ | |
28ccd296 | 538 | cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); |
522989a2 SS |
539 | /* Flip the cycle bit except on the first or last TRB */ |
540 | if (flip_cycle && cur_trb != cur_td->first_trb && | |
541 | cur_trb != cur_td->last_trb) | |
542 | cur_trb->generic.field[3] ^= | |
543 | cpu_to_le32(TRB_CYCLE); | |
28ccd296 ME |
544 | cur_trb->generic.field[3] |= cpu_to_le32( |
545 | TRB_TYPE(TRB_TR_NOOP)); | |
79688acf SS |
546 | xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n", |
547 | (unsigned long long) | |
548 | xhci_trb_virt_to_dma(cur_seg, cur_trb)); | |
ae636747 SS |
549 | } |
550 | if (cur_trb == cur_td->last_trb) | |
551 | break; | |
552 | } | |
553 | } | |
554 | ||
555 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
e9df17eb SS |
556 | unsigned int ep_index, unsigned int stream_id, |
557 | struct xhci_segment *deq_seg, | |
ae636747 SS |
558 | union xhci_trb *deq_ptr, u32 cycle_state); |
559 | ||
c92bcfa7 | 560 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
63a0d9ab | 561 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb | 562 | unsigned int stream_id, |
63a0d9ab | 563 | struct xhci_dequeue_state *deq_state) |
c92bcfa7 | 564 | { |
63a0d9ab SS |
565 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
566 | ||
c92bcfa7 SS |
567 | xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), " |
568 | "new deq ptr = %p (0x%llx dma), new cycle = %u\n", | |
569 | deq_state->new_deq_seg, | |
570 | (unsigned long long)deq_state->new_deq_seg->dma, | |
571 | deq_state->new_deq_ptr, | |
572 | (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
573 | deq_state->new_cycle_state); | |
e9df17eb | 574 | queue_set_tr_deq(xhci, slot_id, ep_index, stream_id, |
c92bcfa7 SS |
575 | deq_state->new_deq_seg, |
576 | deq_state->new_deq_ptr, | |
577 | (u32) deq_state->new_cycle_state); | |
578 | /* Stop the TD queueing code from ringing the doorbell until | |
579 | * this command completes. The HC won't set the dequeue pointer | |
580 | * if the ring is running, and ringing the doorbell starts the | |
581 | * ring running. | |
582 | */ | |
63a0d9ab | 583 | ep->ep_state |= SET_DEQ_PENDING; |
c92bcfa7 SS |
584 | } |
585 | ||
575688e1 | 586 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
587 | struct xhci_virt_ep *ep) |
588 | { | |
589 | ep->ep_state &= ~EP_HALT_PENDING; | |
590 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the | |
591 | * timer is running on another CPU, we don't decrement stop_cmds_pending | |
592 | * (since we didn't successfully stop the watchdog timer). | |
593 | */ | |
594 | if (del_timer(&ep->stop_cmd_timer)) | |
595 | ep->stop_cmds_pending--; | |
596 | } | |
597 | ||
598 | /* Must be called with xhci->lock held in interrupt context */ | |
599 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | |
600 | struct xhci_td *cur_td, int status, char *adjective) | |
601 | { | |
214f76f7 | 602 | struct usb_hcd *hcd; |
8e51adcc AX |
603 | struct urb *urb; |
604 | struct urb_priv *urb_priv; | |
6f5165cf | 605 | |
8e51adcc AX |
606 | urb = cur_td->urb; |
607 | urb_priv = urb->hcpriv; | |
608 | urb_priv->td_cnt++; | |
214f76f7 | 609 | hcd = bus_to_hcd(urb->dev->bus); |
6f5165cf | 610 | |
8e51adcc AX |
611 | /* Only giveback urb when this is the last td in urb */ |
612 | if (urb_priv->td_cnt == urb_priv->length) { | |
c41136b0 AX |
613 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
614 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
615 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
616 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
617 | usb_amd_quirk_pll_enable(); | |
618 | } | |
619 | } | |
8e51adcc | 620 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
8e51adcc AX |
621 | |
622 | spin_unlock(&xhci->lock); | |
623 | usb_hcd_giveback_urb(hcd, urb, status); | |
624 | xhci_urb_free_priv(xhci, urb_priv); | |
625 | spin_lock(&xhci->lock); | |
8e51adcc | 626 | } |
6f5165cf SS |
627 | } |
628 | ||
ae636747 SS |
629 | /* |
630 | * When we get a command completion for a Stop Endpoint Command, we need to | |
631 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
632 | * | |
633 | * 1. If the HW was in the middle of processing the TD that needs to be | |
634 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
635 | * in the TD with a Set Dequeue Pointer Command. | |
636 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
637 | * bit cleared) so that the HW will skip over them. | |
638 | */ | |
639 | static void handle_stopped_endpoint(struct xhci_hcd *xhci, | |
be88fe4f | 640 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 SS |
641 | { |
642 | unsigned int slot_id; | |
643 | unsigned int ep_index; | |
be88fe4f | 644 | struct xhci_virt_device *virt_dev; |
ae636747 | 645 | struct xhci_ring *ep_ring; |
63a0d9ab | 646 | struct xhci_virt_ep *ep; |
ae636747 | 647 | struct list_head *entry; |
326b4810 | 648 | struct xhci_td *cur_td = NULL; |
ae636747 SS |
649 | struct xhci_td *last_unlinked_td; |
650 | ||
c92bcfa7 | 651 | struct xhci_dequeue_state deq_state; |
ae636747 | 652 | |
be88fe4f | 653 | if (unlikely(TRB_TO_SUSPEND_PORT( |
28ccd296 | 654 | le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) { |
be88fe4f | 655 | slot_id = TRB_TO_SLOT_ID( |
28ccd296 | 656 | le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])); |
be88fe4f AX |
657 | virt_dev = xhci->devs[slot_id]; |
658 | if (virt_dev) | |
659 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, | |
660 | event); | |
661 | else | |
662 | xhci_warn(xhci, "Stop endpoint command " | |
663 | "completion for disabled slot %u\n", | |
664 | slot_id); | |
665 | return; | |
666 | } | |
667 | ||
ae636747 | 668 | memset(&deq_state, 0, sizeof(deq_state)); |
28ccd296 ME |
669 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); |
670 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); | |
63a0d9ab | 671 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
ae636747 | 672 | |
678539cf | 673 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 674 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
0714a57c SS |
675 | ep->stopped_td = NULL; |
676 | ep->stopped_trb = NULL; | |
e9df17eb | 677 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 678 | return; |
678539cf | 679 | } |
ae636747 SS |
680 | |
681 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
682 | * We have the xHCI lock, so nothing can modify this list until we drop | |
683 | * it. We're also in the event handler, so we can't get re-interrupted | |
684 | * if another Stop Endpoint command completes | |
685 | */ | |
63a0d9ab | 686 | list_for_each(entry, &ep->cancelled_td_list) { |
ae636747 | 687 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
79688acf SS |
688 | xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n", |
689 | (unsigned long long)xhci_trb_virt_to_dma( | |
690 | cur_td->start_seg, cur_td->first_trb)); | |
e9df17eb SS |
691 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
692 | if (!ep_ring) { | |
693 | /* This shouldn't happen unless a driver is mucking | |
694 | * with the stream ID after submission. This will | |
695 | * leave the TD on the hardware ring, and the hardware | |
696 | * will try to execute it, and may access a buffer | |
697 | * that has already been freed. In the best case, the | |
698 | * hardware will execute it, and the event handler will | |
699 | * ignore the completion event for that TD, since it was | |
700 | * removed from the td_list for that endpoint. In | |
701 | * short, don't muck with the stream ID after | |
702 | * submission. | |
703 | */ | |
704 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
705 | "has invalid stream ID %u.\n", | |
706 | cur_td->urb, | |
707 | cur_td->urb->stream_id); | |
708 | goto remove_finished_td; | |
709 | } | |
ae636747 SS |
710 | /* |
711 | * If we stopped on the TD we need to cancel, then we have to | |
712 | * move the xHC endpoint ring dequeue pointer past this TD. | |
713 | */ | |
63a0d9ab | 714 | if (cur_td == ep->stopped_td) |
e9df17eb SS |
715 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
716 | cur_td->urb->stream_id, | |
717 | cur_td, &deq_state); | |
ae636747 | 718 | else |
522989a2 | 719 | td_to_noop(xhci, ep_ring, cur_td, false); |
e9df17eb | 720 | remove_finished_td: |
ae636747 SS |
721 | /* |
722 | * The event handler won't see a completion for this TD anymore, | |
723 | * so remove it from the endpoint ring's TD list. Keep it in | |
724 | * the cancelled TD list for URB completion later. | |
725 | */ | |
585df1d9 | 726 | list_del_init(&cur_td->td_list); |
ae636747 SS |
727 | } |
728 | last_unlinked_td = cur_td; | |
6f5165cf | 729 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
730 | |
731 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
732 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
63a0d9ab | 733 | xhci_queue_new_dequeue_state(xhci, |
e9df17eb SS |
734 | slot_id, ep_index, |
735 | ep->stopped_td->urb->stream_id, | |
736 | &deq_state); | |
ac9d8fe7 | 737 | xhci_ring_cmd_db(xhci); |
ae636747 | 738 | } else { |
e9df17eb SS |
739 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
740 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 741 | } |
1624ae1c SS |
742 | ep->stopped_td = NULL; |
743 | ep->stopped_trb = NULL; | |
ae636747 SS |
744 | |
745 | /* | |
746 | * Drop the lock and complete the URBs in the cancelled TD list. | |
747 | * New TDs to be cancelled might be added to the end of the list before | |
748 | * we can complete all the URBs for the TDs we already unlinked. | |
749 | * So stop when we've completed the URB for the last TD we unlinked. | |
750 | */ | |
751 | do { | |
63a0d9ab | 752 | cur_td = list_entry(ep->cancelled_td_list.next, |
ae636747 | 753 | struct xhci_td, cancelled_td_list); |
585df1d9 | 754 | list_del_init(&cur_td->cancelled_td_list); |
ae636747 SS |
755 | |
756 | /* Clean up the cancelled URB */ | |
ae636747 SS |
757 | /* Doesn't matter what we pass for status, since the core will |
758 | * just overwrite it (because the URB has been unlinked). | |
759 | */ | |
6f5165cf | 760 | xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled"); |
ae636747 | 761 | |
6f5165cf SS |
762 | /* Stop processing the cancelled list if the watchdog timer is |
763 | * running. | |
764 | */ | |
765 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
766 | return; | |
ae636747 SS |
767 | } while (cur_td != last_unlinked_td); |
768 | ||
769 | /* Return to the event handler with xhci->lock re-acquired */ | |
770 | } | |
771 | ||
6f5165cf SS |
772 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
773 | * In this case, we assume the host controller is broken or dying or dead. The | |
774 | * host may still be completing some other events, so we have to be careful to | |
775 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
776 | * through xhci->state. | |
777 | * | |
778 | * The timer may also fire if the host takes a very long time to respond to the | |
779 | * command, and the stop endpoint command completion handler cannot delete the | |
780 | * timer before the timer function is called. Another endpoint cancellation may | |
781 | * sneak in before the timer function can grab the lock, and that may queue | |
782 | * another stop endpoint command and add the timer back. So we cannot use a | |
783 | * simple flag to say whether there is a pending stop endpoint command for a | |
784 | * particular endpoint. | |
785 | * | |
786 | * Instead we use a combination of that flag and a counter for the number of | |
787 | * pending stop endpoint commands. If the timer is the tail end of the last | |
788 | * stop endpoint command, and the endpoint's command is still pending, we assume | |
789 | * the host is dying. | |
790 | */ | |
791 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
792 | { | |
793 | struct xhci_hcd *xhci; | |
794 | struct xhci_virt_ep *ep; | |
795 | struct xhci_virt_ep *temp_ep; | |
796 | struct xhci_ring *ring; | |
797 | struct xhci_td *cur_td; | |
798 | int ret, i, j; | |
f43d6231 | 799 | unsigned long flags; |
6f5165cf SS |
800 | |
801 | ep = (struct xhci_virt_ep *) arg; | |
802 | xhci = ep->xhci; | |
803 | ||
f43d6231 | 804 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
805 | |
806 | ep->stop_cmds_pending--; | |
807 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
808 | xhci_dbg(xhci, "Stop EP timer ran, but another timer marked " | |
809 | "xHCI as DYING, exiting.\n"); | |
f43d6231 | 810 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
811 | return; |
812 | } | |
813 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { | |
814 | xhci_dbg(xhci, "Stop EP timer ran, but no command pending, " | |
815 | "exiting.\n"); | |
f43d6231 | 816 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
817 | return; |
818 | } | |
819 | ||
820 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
821 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
822 | /* Oops, HC is dead or dying or at least not responding to the stop | |
823 | * endpoint command. | |
824 | */ | |
825 | xhci->xhc_state |= XHCI_STATE_DYING; | |
826 | /* Disable interrupts from the host controller and start halting it */ | |
827 | xhci_quiesce(xhci); | |
f43d6231 | 828 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
829 | |
830 | ret = xhci_halt(xhci); | |
831 | ||
f43d6231 | 832 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
833 | if (ret < 0) { |
834 | /* This is bad; the host is not responding to commands and it's | |
835 | * not allowing itself to be halted. At least interrupts are | |
ac04e6ff | 836 | * disabled. If we call usb_hc_died(), it will attempt to |
6f5165cf SS |
837 | * disconnect all device drivers under this host. Those |
838 | * disconnect() methods will wait for all URBs to be unlinked, | |
839 | * so we must complete them. | |
840 | */ | |
841 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
842 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
843 | /* We could turn all TDs on the rings to no-ops. This won't | |
844 | * help if the host has cached part of the ring, and is slow if | |
845 | * we want to preserve the cycle bit. Skip it and hope the host | |
846 | * doesn't touch the memory. | |
847 | */ | |
848 | } | |
849 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
850 | if (!xhci->devs[i]) | |
851 | continue; | |
852 | for (j = 0; j < 31; j++) { | |
853 | temp_ep = &xhci->devs[i]->eps[j]; | |
854 | ring = temp_ep->ring; | |
855 | if (!ring) | |
856 | continue; | |
857 | xhci_dbg(xhci, "Killing URBs for slot ID %u, " | |
858 | "ep index %u\n", i, j); | |
859 | while (!list_empty(&ring->td_list)) { | |
860 | cur_td = list_first_entry(&ring->td_list, | |
861 | struct xhci_td, | |
862 | td_list); | |
585df1d9 | 863 | list_del_init(&cur_td->td_list); |
6f5165cf | 864 | if (!list_empty(&cur_td->cancelled_td_list)) |
585df1d9 | 865 | list_del_init(&cur_td->cancelled_td_list); |
6f5165cf SS |
866 | xhci_giveback_urb_in_irq(xhci, cur_td, |
867 | -ESHUTDOWN, "killed"); | |
868 | } | |
869 | while (!list_empty(&temp_ep->cancelled_td_list)) { | |
870 | cur_td = list_first_entry( | |
871 | &temp_ep->cancelled_td_list, | |
872 | struct xhci_td, | |
873 | cancelled_td_list); | |
585df1d9 | 874 | list_del_init(&cur_td->cancelled_td_list); |
6f5165cf SS |
875 | xhci_giveback_urb_in_irq(xhci, cur_td, |
876 | -ESHUTDOWN, "killed"); | |
877 | } | |
878 | } | |
879 | } | |
f43d6231 | 880 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf | 881 | xhci_dbg(xhci, "Calling usb_hc_died()\n"); |
f6ff0ac8 | 882 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); |
6f5165cf SS |
883 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); |
884 | } | |
885 | ||
b008df60 AX |
886 | |
887 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, | |
888 | struct xhci_virt_device *dev, | |
889 | struct xhci_ring *ep_ring, | |
890 | unsigned int ep_index) | |
891 | { | |
892 | union xhci_trb *dequeue_temp; | |
893 | int num_trbs_free_temp; | |
894 | bool revert = false; | |
895 | ||
896 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
897 | dequeue_temp = ep_ring->dequeue; | |
898 | ||
0d9f78a9 SS |
899 | /* If we get two back-to-back stalls, and the first stalled transfer |
900 | * ends just before a link TRB, the dequeue pointer will be left on | |
901 | * the link TRB by the code in the while loop. So we have to update | |
902 | * the dequeue pointer one segment further, or we'll jump off | |
903 | * the segment into la-la-land. | |
904 | */ | |
905 | if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) { | |
906 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
907 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
908 | } | |
909 | ||
b008df60 AX |
910 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
911 | /* We have more usable TRBs */ | |
912 | ep_ring->num_trbs_free++; | |
913 | ep_ring->dequeue++; | |
914 | if (last_trb(xhci, ep_ring, ep_ring->deq_seg, | |
915 | ep_ring->dequeue)) { | |
916 | if (ep_ring->dequeue == | |
917 | dev->eps[ep_index].queued_deq_ptr) | |
918 | break; | |
919 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
920 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
921 | } | |
922 | if (ep_ring->dequeue == dequeue_temp) { | |
923 | revert = true; | |
924 | break; | |
925 | } | |
926 | } | |
927 | ||
928 | if (revert) { | |
929 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
930 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
931 | } | |
932 | } | |
933 | ||
ae636747 SS |
934 | /* |
935 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
936 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
937 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
938 | * endpoint doorbell to restart the ring, but only if there aren't more | |
939 | * cancellations pending. | |
940 | */ | |
941 | static void handle_set_deq_completion(struct xhci_hcd *xhci, | |
942 | struct xhci_event_cmd *event, | |
943 | union xhci_trb *trb) | |
944 | { | |
945 | unsigned int slot_id; | |
946 | unsigned int ep_index; | |
e9df17eb | 947 | unsigned int stream_id; |
ae636747 SS |
948 | struct xhci_ring *ep_ring; |
949 | struct xhci_virt_device *dev; | |
d115b048 JY |
950 | struct xhci_ep_ctx *ep_ctx; |
951 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 | 952 | |
28ccd296 ME |
953 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); |
954 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); | |
955 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
ae636747 | 956 | dev = xhci->devs[slot_id]; |
e9df17eb SS |
957 | |
958 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
959 | if (!ep_ring) { | |
960 | xhci_warn(xhci, "WARN Set TR deq ptr command for " | |
961 | "freed stream ID %u\n", | |
962 | stream_id); | |
963 | /* XXX: Harmless??? */ | |
964 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; | |
965 | return; | |
966 | } | |
967 | ||
d115b048 JY |
968 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
969 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
ae636747 | 970 | |
28ccd296 | 971 | if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) { |
ae636747 SS |
972 | unsigned int ep_state; |
973 | unsigned int slot_state; | |
974 | ||
28ccd296 | 975 | switch (GET_COMP_CODE(le32_to_cpu(event->status))) { |
ae636747 SS |
976 | case COMP_TRB_ERR: |
977 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because " | |
978 | "of stream ID configuration\n"); | |
979 | break; | |
980 | case COMP_CTX_STATE: | |
981 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due " | |
982 | "to incorrect slot or ep state.\n"); | |
28ccd296 | 983 | ep_state = le32_to_cpu(ep_ctx->ep_info); |
ae636747 | 984 | ep_state &= EP_STATE_MASK; |
28ccd296 | 985 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 SS |
986 | slot_state = GET_SLOT_STATE(slot_state); |
987 | xhci_dbg(xhci, "Slot state = %u, EP state = %u\n", | |
988 | slot_state, ep_state); | |
989 | break; | |
990 | case COMP_EBADSLT: | |
991 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because " | |
992 | "slot %u was not enabled.\n", slot_id); | |
993 | break; | |
994 | default: | |
995 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown " | |
996 | "completion code of %u.\n", | |
28ccd296 | 997 | GET_COMP_CODE(le32_to_cpu(event->status))); |
ae636747 SS |
998 | break; |
999 | } | |
1000 | /* OK what do we do now? The endpoint state is hosed, and we | |
1001 | * should never get to this point if the synchronization between | |
1002 | * queueing, and endpoint state are correct. This might happen | |
1003 | * if the device gets disconnected after we've finished | |
1004 | * cancelling URBs, which might not be an error... | |
1005 | */ | |
1006 | } else { | |
8e595a5d | 1007 | xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n", |
28ccd296 | 1008 | le64_to_cpu(ep_ctx->deq)); |
bf161e85 | 1009 | if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg, |
28ccd296 ME |
1010 | dev->eps[ep_index].queued_deq_ptr) == |
1011 | (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) { | |
bf161e85 SS |
1012 | /* Update the ring's dequeue segment and dequeue pointer |
1013 | * to reflect the new position. | |
1014 | */ | |
b008df60 AX |
1015 | update_ring_for_set_deq_completion(xhci, dev, |
1016 | ep_ring, ep_index); | |
bf161e85 SS |
1017 | } else { |
1018 | xhci_warn(xhci, "Mismatch between completed Set TR Deq " | |
1019 | "Ptr command & xHCI internal state.\n"); | |
1020 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", | |
1021 | dev->eps[ep_index].queued_deq_seg, | |
1022 | dev->eps[ep_index].queued_deq_ptr); | |
1023 | } | |
ae636747 SS |
1024 | } |
1025 | ||
63a0d9ab | 1026 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
bf161e85 SS |
1027 | dev->eps[ep_index].queued_deq_seg = NULL; |
1028 | dev->eps[ep_index].queued_deq_ptr = NULL; | |
e9df17eb SS |
1029 | /* Restart any rings with pending URBs */ |
1030 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1031 | } |
1032 | ||
a1587d97 SS |
1033 | static void handle_reset_ep_completion(struct xhci_hcd *xhci, |
1034 | struct xhci_event_cmd *event, | |
1035 | union xhci_trb *trb) | |
1036 | { | |
1037 | int slot_id; | |
1038 | unsigned int ep_index; | |
1039 | ||
28ccd296 ME |
1040 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3])); |
1041 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); | |
a1587d97 SS |
1042 | /* This command will only fail if the endpoint wasn't halted, |
1043 | * but we don't care. | |
1044 | */ | |
1045 | xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n", | |
f5960b69 | 1046 | GET_COMP_CODE(le32_to_cpu(event->status))); |
a1587d97 | 1047 | |
ac9d8fe7 SS |
1048 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
1049 | * command complete before the endpoint can be used. Queue that here | |
1050 | * because the HW can't handle two commands being queued in a row. | |
1051 | */ | |
1052 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
1053 | xhci_dbg(xhci, "Queueing configure endpoint command\n"); | |
1054 | xhci_queue_configure_endpoint(xhci, | |
913a8a34 SS |
1055 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
1056 | false); | |
ac9d8fe7 SS |
1057 | xhci_ring_cmd_db(xhci); |
1058 | } else { | |
e9df17eb | 1059 | /* Clear our internal halted state and restart the ring(s) */ |
63a0d9ab | 1060 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
e9df17eb | 1061 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ac9d8fe7 | 1062 | } |
a1587d97 | 1063 | } |
ae636747 | 1064 | |
a50c8aa9 SS |
1065 | /* Check to see if a command in the device's command queue matches this one. |
1066 | * Signal the completion or free the command, and return 1. Return 0 if the | |
1067 | * completed command isn't at the head of the command list. | |
1068 | */ | |
1069 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | |
1070 | struct xhci_virt_device *virt_dev, | |
1071 | struct xhci_event_cmd *event) | |
1072 | { | |
1073 | struct xhci_command *command; | |
1074 | ||
1075 | if (list_empty(&virt_dev->cmd_list)) | |
1076 | return 0; | |
1077 | ||
1078 | command = list_entry(virt_dev->cmd_list.next, | |
1079 | struct xhci_command, cmd_list); | |
1080 | if (xhci->cmd_ring->dequeue != command->command_trb) | |
1081 | return 0; | |
1082 | ||
28ccd296 | 1083 | command->status = GET_COMP_CODE(le32_to_cpu(event->status)); |
a50c8aa9 SS |
1084 | list_del(&command->cmd_list); |
1085 | if (command->completion) | |
1086 | complete(command->completion); | |
1087 | else | |
1088 | xhci_free_command(xhci, command); | |
1089 | return 1; | |
1090 | } | |
1091 | ||
7f84eef0 SS |
1092 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1093 | struct xhci_event_cmd *event) | |
1094 | { | |
28ccd296 | 1095 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1096 | u64 cmd_dma; |
1097 | dma_addr_t cmd_dequeue_dma; | |
ac9d8fe7 | 1098 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 1099 | struct xhci_virt_device *virt_dev; |
ac9d8fe7 SS |
1100 | unsigned int ep_index; |
1101 | struct xhci_ring *ep_ring; | |
1102 | unsigned int ep_state; | |
7f84eef0 | 1103 | |
28ccd296 | 1104 | cmd_dma = le64_to_cpu(event->cmd_trb); |
23e3be11 | 1105 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
7f84eef0 SS |
1106 | xhci->cmd_ring->dequeue); |
1107 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ | |
1108 | if (cmd_dequeue_dma == 0) { | |
1109 | xhci->error_bitmask |= 1 << 4; | |
1110 | return; | |
1111 | } | |
1112 | /* Does the DMA address match our internal dequeue pointer address? */ | |
1113 | if (cmd_dma != (u64) cmd_dequeue_dma) { | |
1114 | xhci->error_bitmask |= 1 << 5; | |
1115 | return; | |
1116 | } | |
28ccd296 ME |
1117 | switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]) |
1118 | & TRB_TYPE_BITMASK) { | |
3ffbba95 | 1119 | case TRB_TYPE(TRB_ENABLE_SLOT): |
28ccd296 | 1120 | if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS) |
3ffbba95 SS |
1121 | xhci->slot_id = slot_id; |
1122 | else | |
1123 | xhci->slot_id = 0; | |
1124 | complete(&xhci->addr_dev); | |
1125 | break; | |
1126 | case TRB_TYPE(TRB_DISABLE_SLOT): | |
2cf95c18 SS |
1127 | if (xhci->devs[slot_id]) { |
1128 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) | |
1129 | /* Delete default control endpoint resources */ | |
1130 | xhci_free_device_endpoint_resources(xhci, | |
1131 | xhci->devs[slot_id], true); | |
3ffbba95 | 1132 | xhci_free_virt_device(xhci, slot_id); |
2cf95c18 | 1133 | } |
3ffbba95 | 1134 | break; |
f94e0186 | 1135 | case TRB_TYPE(TRB_CONFIG_EP): |
913a8a34 | 1136 | virt_dev = xhci->devs[slot_id]; |
a50c8aa9 | 1137 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) |
913a8a34 | 1138 | break; |
ac9d8fe7 SS |
1139 | /* |
1140 | * Configure endpoint commands can come from the USB core | |
1141 | * configuration or alt setting changes, or because the HW | |
1142 | * needed an extra configure endpoint command after a reset | |
8df75f42 SS |
1143 | * endpoint command or streams were being configured. |
1144 | * If the command was for a halted endpoint, the xHCI driver | |
1145 | * is not waiting on the configure endpoint command. | |
ac9d8fe7 SS |
1146 | */ |
1147 | ctrl_ctx = xhci_get_input_control_ctx(xhci, | |
913a8a34 | 1148 | virt_dev->in_ctx); |
ac9d8fe7 | 1149 | /* Input ctx add_flags are the endpoint index plus one */ |
28ccd296 | 1150 | ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1; |
06df5729 | 1151 | /* A usb_set_interface() call directly after clearing a halted |
e9df17eb SS |
1152 | * condition may race on this quirky hardware. Not worth |
1153 | * worrying about, since this is prototype hardware. Not sure | |
1154 | * if this will work for streams, but streams support was | |
1155 | * untested on this prototype. | |
06df5729 | 1156 | */ |
ac9d8fe7 | 1157 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && |
06df5729 | 1158 | ep_index != (unsigned int) -1 && |
28ccd296 ME |
1159 | le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG == |
1160 | le32_to_cpu(ctrl_ctx->drop_flags)) { | |
06df5729 SS |
1161 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
1162 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
1163 | if (!(ep_state & EP_HALTED)) | |
1164 | goto bandwidth_change; | |
1165 | xhci_dbg(xhci, "Completed config ep cmd - " | |
1166 | "last ep index = %d, state = %d\n", | |
1167 | ep_index, ep_state); | |
e9df17eb | 1168 | /* Clear internal halted state and restart ring(s) */ |
63a0d9ab | 1169 | xhci->devs[slot_id]->eps[ep_index].ep_state &= |
ac9d8fe7 | 1170 | ~EP_HALTED; |
e9df17eb | 1171 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
06df5729 | 1172 | break; |
ac9d8fe7 | 1173 | } |
06df5729 SS |
1174 | bandwidth_change: |
1175 | xhci_dbg(xhci, "Completed config ep cmd\n"); | |
1176 | xhci->devs[slot_id]->cmd_status = | |
28ccd296 | 1177 | GET_COMP_CODE(le32_to_cpu(event->status)); |
06df5729 | 1178 | complete(&xhci->devs[slot_id]->cmd_completion); |
f94e0186 | 1179 | break; |
2d3f1fac | 1180 | case TRB_TYPE(TRB_EVAL_CONTEXT): |
ac1c1b7f SS |
1181 | virt_dev = xhci->devs[slot_id]; |
1182 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) | |
1183 | break; | |
28ccd296 | 1184 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status)); |
2d3f1fac SS |
1185 | complete(&xhci->devs[slot_id]->cmd_completion); |
1186 | break; | |
3ffbba95 | 1187 | case TRB_TYPE(TRB_ADDR_DEV): |
28ccd296 | 1188 | xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status)); |
3ffbba95 SS |
1189 | complete(&xhci->addr_dev); |
1190 | break; | |
ae636747 | 1191 | case TRB_TYPE(TRB_STOP_RING): |
be88fe4f | 1192 | handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event); |
ae636747 SS |
1193 | break; |
1194 | case TRB_TYPE(TRB_SET_DEQ): | |
1195 | handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue); | |
1196 | break; | |
7f84eef0 | 1197 | case TRB_TYPE(TRB_CMD_NOOP): |
7f84eef0 | 1198 | break; |
a1587d97 SS |
1199 | case TRB_TYPE(TRB_RESET_EP): |
1200 | handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue); | |
1201 | break; | |
2a8f82c4 SS |
1202 | case TRB_TYPE(TRB_RESET_DEV): |
1203 | xhci_dbg(xhci, "Completed reset device command.\n"); | |
1204 | slot_id = TRB_TO_SLOT_ID( | |
28ccd296 | 1205 | le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])); |
2a8f82c4 SS |
1206 | virt_dev = xhci->devs[slot_id]; |
1207 | if (virt_dev) | |
1208 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); | |
1209 | else | |
1210 | xhci_warn(xhci, "Reset device command completion " | |
1211 | "for disabled slot %u\n", slot_id); | |
1212 | break; | |
0238634d SS |
1213 | case TRB_TYPE(TRB_NEC_GET_FW): |
1214 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
1215 | xhci->error_bitmask |= 1 << 6; | |
1216 | break; | |
1217 | } | |
1218 | xhci_dbg(xhci, "NEC firmware version %2x.%02x\n", | |
28ccd296 ME |
1219 | NEC_FW_MAJOR(le32_to_cpu(event->status)), |
1220 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
0238634d | 1221 | break; |
7f84eef0 SS |
1222 | default: |
1223 | /* Skip over unknown commands on the event ring */ | |
1224 | xhci->error_bitmask |= 1 << 6; | |
1225 | break; | |
1226 | } | |
3b72fca0 | 1227 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1228 | } |
1229 | ||
0238634d SS |
1230 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1231 | union xhci_trb *event) | |
1232 | { | |
1233 | u32 trb_type; | |
1234 | ||
28ccd296 | 1235 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
0238634d SS |
1236 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1237 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1238 | handle_cmd_completion(xhci, &event->event_cmd); | |
1239 | } | |
1240 | ||
f6ff0ac8 SS |
1241 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
1242 | * port registers -- USB 3.0 and USB 2.0). | |
1243 | * | |
1244 | * Returns a zero-based port number, which is suitable for indexing into each of | |
1245 | * the split roothubs' port arrays and bus state arrays. | |
d0cd5d48 | 1246 | * Add one to it in order to call xhci_find_slot_id_by_port. |
f6ff0ac8 SS |
1247 | */ |
1248 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, | |
1249 | struct xhci_hcd *xhci, u32 port_id) | |
1250 | { | |
1251 | unsigned int i; | |
1252 | unsigned int num_similar_speed_ports = 0; | |
1253 | ||
1254 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], | |
1255 | * and usb2_ports are 0-based indexes. Count the number of similar | |
1256 | * speed ports, up to 1 port before this port. | |
1257 | */ | |
1258 | for (i = 0; i < (port_id - 1); i++) { | |
1259 | u8 port_speed = xhci->port_array[i]; | |
1260 | ||
1261 | /* | |
1262 | * Skip ports that don't have known speeds, or have duplicate | |
1263 | * Extended Capabilities port speed entries. | |
1264 | */ | |
22e04870 | 1265 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
1266 | continue; |
1267 | ||
1268 | /* | |
1269 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
1270 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
1271 | * matches the device speed, it's a similar speed port. | |
1272 | */ | |
1273 | if ((port_speed == 0x03) == (hcd->speed == HCD_USB3)) | |
1274 | num_similar_speed_ports++; | |
1275 | } | |
1276 | return num_similar_speed_ports; | |
1277 | } | |
1278 | ||
623bef9e SS |
1279 | static void handle_device_notification(struct xhci_hcd *xhci, |
1280 | union xhci_trb *event) | |
1281 | { | |
1282 | u32 slot_id; | |
4ee823b8 | 1283 | struct usb_device *udev; |
623bef9e SS |
1284 | |
1285 | slot_id = TRB_TO_SLOT_ID(event->generic.field[3]); | |
4ee823b8 | 1286 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1287 | xhci_warn(xhci, "Device Notification event for " |
1288 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1289 | return; |
1290 | } | |
1291 | ||
1292 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1293 | slot_id); | |
1294 | udev = xhci->devs[slot_id]->udev; | |
1295 | if (udev && udev->parent) | |
1296 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1297 | } |
1298 | ||
0f2a7930 SS |
1299 | static void handle_port_status(struct xhci_hcd *xhci, |
1300 | union xhci_trb *event) | |
1301 | { | |
f6ff0ac8 | 1302 | struct usb_hcd *hcd; |
0f2a7930 | 1303 | u32 port_id; |
56192531 | 1304 | u32 temp, temp1; |
518e848e | 1305 | int max_ports; |
56192531 | 1306 | int slot_id; |
5308a91b | 1307 | unsigned int faked_port_index; |
f6ff0ac8 | 1308 | u8 major_revision; |
20b67cf5 | 1309 | struct xhci_bus_state *bus_state; |
28ccd296 | 1310 | __le32 __iomem **port_array; |
386139d7 | 1311 | bool bogus_port_status = false; |
0f2a7930 SS |
1312 | |
1313 | /* Port status change events always have a successful completion code */ | |
28ccd296 | 1314 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) { |
0f2a7930 SS |
1315 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); |
1316 | xhci->error_bitmask |= 1 << 8; | |
1317 | } | |
28ccd296 | 1318 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
0f2a7930 SS |
1319 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
1320 | ||
518e848e SS |
1321 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1322 | if ((port_id <= 0) || (port_id > max_ports)) { | |
56192531 | 1323 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
386139d7 | 1324 | bogus_port_status = true; |
56192531 AX |
1325 | goto cleanup; |
1326 | } | |
1327 | ||
f6ff0ac8 SS |
1328 | /* Figure out which usb_hcd this port is attached to: |
1329 | * is it a USB 3.0 port or a USB 2.0/1.1 port? | |
1330 | */ | |
1331 | major_revision = xhci->port_array[port_id - 1]; | |
1332 | if (major_revision == 0) { | |
1333 | xhci_warn(xhci, "Event for port %u not in " | |
1334 | "Extended Capabilities, ignoring.\n", | |
1335 | port_id); | |
386139d7 | 1336 | bogus_port_status = true; |
f6ff0ac8 | 1337 | goto cleanup; |
5308a91b | 1338 | } |
22e04870 | 1339 | if (major_revision == DUPLICATE_ENTRY) { |
f6ff0ac8 SS |
1340 | xhci_warn(xhci, "Event for port %u duplicated in" |
1341 | "Extended Capabilities, ignoring.\n", | |
1342 | port_id); | |
386139d7 | 1343 | bogus_port_status = true; |
f6ff0ac8 SS |
1344 | goto cleanup; |
1345 | } | |
1346 | ||
1347 | /* | |
1348 | * Hardware port IDs reported by a Port Status Change Event include USB | |
1349 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a | |
1350 | * resume event, but we first need to translate the hardware port ID | |
1351 | * into the index into the ports on the correct split roothub, and the | |
1352 | * correct bus_state structure. | |
1353 | */ | |
1354 | /* Find the right roothub. */ | |
1355 | hcd = xhci_to_hcd(xhci); | |
1356 | if ((major_revision == 0x03) != (hcd->speed == HCD_USB3)) | |
1357 | hcd = xhci->shared_hcd; | |
1358 | bus_state = &xhci->bus_state[hcd_index(hcd)]; | |
1359 | if (hcd->speed == HCD_USB3) | |
1360 | port_array = xhci->usb3_ports; | |
1361 | else | |
1362 | port_array = xhci->usb2_ports; | |
1363 | /* Find the faked port hub number */ | |
1364 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, | |
1365 | port_id); | |
5308a91b | 1366 | |
5308a91b | 1367 | temp = xhci_readl(xhci, port_array[faked_port_index]); |
7111ebc9 | 1368 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1369 | xhci_dbg(xhci, "resume root hub\n"); |
1370 | usb_hcd_resume_root_hub(hcd); | |
1371 | } | |
1372 | ||
1373 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { | |
1374 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | |
1375 | ||
1376 | temp1 = xhci_readl(xhci, &xhci->op_regs->command); | |
1377 | if (!(temp1 & CMD_RUN)) { | |
1378 | xhci_warn(xhci, "xHC is not running.\n"); | |
1379 | goto cleanup; | |
1380 | } | |
1381 | ||
1382 | if (DEV_SUPERSPEED(temp)) { | |
d93814cf | 1383 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1384 | /* Set a flag to say the port signaled remote wakeup, |
1385 | * so we can tell the difference between the end of | |
1386 | * device and host initiated resume. | |
1387 | */ | |
1388 | bus_state->port_remote_wakeup |= 1 << faked_port_index; | |
d93814cf SS |
1389 | xhci_test_and_clear_bit(xhci, port_array, |
1390 | faked_port_index, PORT_PLC); | |
c9682dff AX |
1391 | xhci_set_link_state(xhci, port_array, faked_port_index, |
1392 | XDEV_U0); | |
d93814cf SS |
1393 | /* Need to wait until the next link state change |
1394 | * indicates the device is actually in U0. | |
1395 | */ | |
1396 | bogus_port_status = true; | |
1397 | goto cleanup; | |
56192531 AX |
1398 | } else { |
1399 | xhci_dbg(xhci, "resume HS port %d\n", port_id); | |
f6ff0ac8 | 1400 | bus_state->resume_done[faked_port_index] = jiffies + |
56192531 | 1401 | msecs_to_jiffies(20); |
f370b996 | 1402 | set_bit(faked_port_index, &bus_state->resuming_ports); |
56192531 | 1403 | mod_timer(&hcd->rh_timer, |
f6ff0ac8 | 1404 | bus_state->resume_done[faked_port_index]); |
56192531 AX |
1405 | /* Do the rest in GetPortStatus */ |
1406 | } | |
1407 | } | |
d93814cf SS |
1408 | |
1409 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && | |
1410 | DEV_SUPERSPEED(temp)) { | |
1411 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); | |
4ee823b8 SS |
1412 | /* We've just brought the device into U0 through either the |
1413 | * Resume state after a device remote wakeup, or through the | |
1414 | * U3Exit state after a host-initiated resume. If it's a device | |
1415 | * initiated remote wake, don't pass up the link state change, | |
1416 | * so the roothub behavior is consistent with external | |
1417 | * USB 3.0 hub behavior. | |
1418 | */ | |
d93814cf SS |
1419 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1420 | faked_port_index + 1); | |
1421 | if (slot_id && xhci->devs[slot_id]) | |
1422 | xhci_ring_device(xhci, slot_id); | |
4ee823b8 SS |
1423 | if (bus_state->port_remote_wakeup && (1 << faked_port_index)) { |
1424 | bus_state->port_remote_wakeup &= | |
1425 | ~(1 << faked_port_index); | |
1426 | xhci_test_and_clear_bit(xhci, port_array, | |
1427 | faked_port_index, PORT_PLC); | |
1428 | usb_wakeup_notification(hcd->self.root_hub, | |
1429 | faked_port_index + 1); | |
1430 | bogus_port_status = true; | |
1431 | goto cleanup; | |
1432 | } | |
d93814cf | 1433 | } |
56192531 | 1434 | |
6fd45621 AX |
1435 | if (hcd->speed != HCD_USB3) |
1436 | xhci_test_and_clear_bit(xhci, port_array, faked_port_index, | |
1437 | PORT_PLC); | |
1438 | ||
56192531 | 1439 | cleanup: |
0f2a7930 | 1440 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 1441 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 1442 | |
386139d7 SS |
1443 | /* Don't make the USB core poll the roothub if we got a bad port status |
1444 | * change event. Besides, at that point we can't tell which roothub | |
1445 | * (USB 2.0 or USB 3.0) to kick. | |
1446 | */ | |
1447 | if (bogus_port_status) | |
1448 | return; | |
1449 | ||
0f2a7930 SS |
1450 | spin_unlock(&xhci->lock); |
1451 | /* Pass this up to the core */ | |
f6ff0ac8 | 1452 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
1453 | spin_lock(&xhci->lock); |
1454 | } | |
1455 | ||
d0e96f5a SS |
1456 | /* |
1457 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1458 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1459 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1460 | * returns 0. | |
1461 | */ | |
6648f29d | 1462 | struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, |
d0e96f5a SS |
1463 | union xhci_trb *start_trb, |
1464 | union xhci_trb *end_trb, | |
1465 | dma_addr_t suspect_dma) | |
1466 | { | |
1467 | dma_addr_t start_dma; | |
1468 | dma_addr_t end_seg_dma; | |
1469 | dma_addr_t end_trb_dma; | |
1470 | struct xhci_segment *cur_seg; | |
1471 | ||
23e3be11 | 1472 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1473 | cur_seg = start_seg; |
1474 | ||
1475 | do { | |
2fa88daa | 1476 | if (start_dma == 0) |
326b4810 | 1477 | return NULL; |
ae636747 | 1478 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1479 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1480 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1481 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1482 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a SS |
1483 | |
1484 | if (end_trb_dma > 0) { | |
1485 | /* The end TRB is in this segment, so suspect should be here */ | |
1486 | if (start_dma <= end_trb_dma) { | |
1487 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1488 | return cur_seg; | |
1489 | } else { | |
1490 | /* Case for one segment with | |
1491 | * a TD wrapped around to the top | |
1492 | */ | |
1493 | if ((suspect_dma >= start_dma && | |
1494 | suspect_dma <= end_seg_dma) || | |
1495 | (suspect_dma >= cur_seg->dma && | |
1496 | suspect_dma <= end_trb_dma)) | |
1497 | return cur_seg; | |
1498 | } | |
326b4810 | 1499 | return NULL; |
d0e96f5a SS |
1500 | } else { |
1501 | /* Might still be somewhere in this segment */ | |
1502 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1503 | return cur_seg; | |
1504 | } | |
1505 | cur_seg = cur_seg->next; | |
23e3be11 | 1506 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1507 | } while (cur_seg != start_seg); |
d0e96f5a | 1508 | |
326b4810 | 1509 | return NULL; |
d0e96f5a SS |
1510 | } |
1511 | ||
bcef3fd5 SS |
1512 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1513 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1514 | unsigned int stream_id, |
bcef3fd5 SS |
1515 | struct xhci_td *td, union xhci_trb *event_trb) |
1516 | { | |
1517 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
1518 | ep->ep_state |= EP_HALTED; | |
1519 | ep->stopped_td = td; | |
1520 | ep->stopped_trb = event_trb; | |
e9df17eb | 1521 | ep->stopped_stream = stream_id; |
1624ae1c | 1522 | |
bcef3fd5 SS |
1523 | xhci_queue_reset_ep(xhci, slot_id, ep_index); |
1524 | xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); | |
1624ae1c SS |
1525 | |
1526 | ep->stopped_td = NULL; | |
1527 | ep->stopped_trb = NULL; | |
5e5cf6fc | 1528 | ep->stopped_stream = 0; |
1624ae1c | 1529 | |
bcef3fd5 SS |
1530 | xhci_ring_cmd_db(xhci); |
1531 | } | |
1532 | ||
1533 | /* Check if an error has halted the endpoint ring. The class driver will | |
1534 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1535 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1536 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1537 | * Ring Dequeue Pointer command manually. | |
1538 | */ | |
1539 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1540 | struct xhci_ep_ctx *ep_ctx, | |
1541 | unsigned int trb_comp_code) | |
1542 | { | |
1543 | /* TRB completion codes that may require a manual halt cleanup */ | |
1544 | if (trb_comp_code == COMP_TX_ERR || | |
1545 | trb_comp_code == COMP_BABBLE || | |
1546 | trb_comp_code == COMP_SPLIT_ERR) | |
1547 | /* The 0.96 spec says a babbling control endpoint | |
1548 | * is not halted. The 0.96 spec says it is. Some HW | |
1549 | * claims to be 0.95 compliant, but it halts the control | |
1550 | * endpoint anyway. Check if a babble halted the | |
1551 | * endpoint. | |
1552 | */ | |
f5960b69 ME |
1553 | if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == |
1554 | cpu_to_le32(EP_STATE_HALTED)) | |
bcef3fd5 SS |
1555 | return 1; |
1556 | ||
1557 | return 0; | |
1558 | } | |
1559 | ||
b45b5069 SS |
1560 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1561 | { | |
1562 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1563 | /* Vendor defined "informational" completion code, | |
1564 | * treat as not-an-error. | |
1565 | */ | |
1566 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1567 | trb_comp_code); | |
1568 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1569 | return 1; | |
1570 | } | |
1571 | return 0; | |
1572 | } | |
1573 | ||
4422da61 AX |
1574 | /* |
1575 | * Finish the td processing, remove the td from td list; | |
1576 | * Return 1 if the urb can be given back. | |
1577 | */ | |
1578 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1579 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1580 | struct xhci_virt_ep *ep, int *status, bool skip) | |
1581 | { | |
1582 | struct xhci_virt_device *xdev; | |
1583 | struct xhci_ring *ep_ring; | |
1584 | unsigned int slot_id; | |
1585 | int ep_index; | |
1586 | struct urb *urb = NULL; | |
1587 | struct xhci_ep_ctx *ep_ctx; | |
1588 | int ret = 0; | |
8e51adcc | 1589 | struct urb_priv *urb_priv; |
4422da61 AX |
1590 | u32 trb_comp_code; |
1591 | ||
28ccd296 | 1592 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
4422da61 | 1593 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1594 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1595 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
4422da61 | 1596 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1597 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
4422da61 AX |
1598 | |
1599 | if (skip) | |
1600 | goto td_cleanup; | |
1601 | ||
1602 | if (trb_comp_code == COMP_STOP_INVAL || | |
1603 | trb_comp_code == COMP_STOP) { | |
1604 | /* The Endpoint Stop Command completion will take care of any | |
1605 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1606 | * the ring dequeue pointer or take this TD off any lists yet. | |
1607 | */ | |
1608 | ep->stopped_td = td; | |
1609 | ep->stopped_trb = event_trb; | |
1610 | return 0; | |
1611 | } else { | |
1612 | if (trb_comp_code == COMP_STALL) { | |
1613 | /* The transfer is completed from the driver's | |
1614 | * perspective, but we need to issue a set dequeue | |
1615 | * command for this stalled endpoint to move the dequeue | |
1616 | * pointer past the TD. We can't do that here because | |
1617 | * the halt condition must be cleared first. Let the | |
1618 | * USB class driver clear the stall later. | |
1619 | */ | |
1620 | ep->stopped_td = td; | |
1621 | ep->stopped_trb = event_trb; | |
1622 | ep->stopped_stream = ep_ring->stream_id; | |
1623 | } else if (xhci_requires_manual_halt_cleanup(xhci, | |
1624 | ep_ctx, trb_comp_code)) { | |
1625 | /* Other types of errors halt the endpoint, but the | |
1626 | * class driver doesn't call usb_reset_endpoint() unless | |
1627 | * the error is -EPIPE. Clear the halted status in the | |
1628 | * xHCI hardware manually. | |
1629 | */ | |
1630 | xhci_cleanup_halted_endpoint(xhci, | |
1631 | slot_id, ep_index, ep_ring->stream_id, | |
1632 | td, event_trb); | |
1633 | } else { | |
1634 | /* Update ring dequeue pointer */ | |
1635 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
1636 | inc_deq(xhci, ep_ring); |
1637 | inc_deq(xhci, ep_ring); | |
4422da61 AX |
1638 | } |
1639 | ||
1640 | td_cleanup: | |
1641 | /* Clean up the endpoint's TD list */ | |
1642 | urb = td->urb; | |
8e51adcc | 1643 | urb_priv = urb->hcpriv; |
4422da61 AX |
1644 | |
1645 | /* Do one last check of the actual transfer length. | |
1646 | * If the host controller said we transferred more data than | |
1647 | * the buffer length, urb->actual_length will be a very big | |
1648 | * number (since it's unsigned). Play it safe and say we didn't | |
1649 | * transfer anything. | |
1650 | */ | |
1651 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1652 | xhci_warn(xhci, "URB transfer length is wrong, " | |
1653 | "xHC issue? req. len = %u, " | |
1654 | "act. len = %u\n", | |
1655 | urb->transfer_buffer_length, | |
1656 | urb->actual_length); | |
1657 | urb->actual_length = 0; | |
1658 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1659 | *status = -EREMOTEIO; | |
1660 | else | |
1661 | *status = 0; | |
1662 | } | |
585df1d9 | 1663 | list_del_init(&td->td_list); |
4422da61 AX |
1664 | /* Was this TD slated to be cancelled but completed anyway? */ |
1665 | if (!list_empty(&td->cancelled_td_list)) | |
585df1d9 | 1666 | list_del_init(&td->cancelled_td_list); |
4422da61 | 1667 | |
8e51adcc AX |
1668 | urb_priv->td_cnt++; |
1669 | /* Giveback the urb when all the tds are completed */ | |
c41136b0 | 1670 | if (urb_priv->td_cnt == urb_priv->length) { |
8e51adcc | 1671 | ret = 1; |
c41136b0 AX |
1672 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
1673 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
1674 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs | |
1675 | == 0) { | |
1676 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
1677 | usb_amd_quirk_pll_enable(); | |
1678 | } | |
1679 | } | |
1680 | } | |
4422da61 AX |
1681 | } |
1682 | ||
1683 | return ret; | |
1684 | } | |
1685 | ||
8af56be1 AX |
1686 | /* |
1687 | * Process control tds, update urb status and actual_length. | |
1688 | */ | |
1689 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1690 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1691 | struct xhci_virt_ep *ep, int *status) | |
1692 | { | |
1693 | struct xhci_virt_device *xdev; | |
1694 | struct xhci_ring *ep_ring; | |
1695 | unsigned int slot_id; | |
1696 | int ep_index; | |
1697 | struct xhci_ep_ctx *ep_ctx; | |
1698 | u32 trb_comp_code; | |
1699 | ||
28ccd296 | 1700 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
8af56be1 | 1701 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1702 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1703 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
8af56be1 | 1704 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1705 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
8af56be1 | 1706 | |
8af56be1 AX |
1707 | switch (trb_comp_code) { |
1708 | case COMP_SUCCESS: | |
1709 | if (event_trb == ep_ring->dequeue) { | |
1710 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB " | |
1711 | "without IOC set??\n"); | |
1712 | *status = -ESHUTDOWN; | |
1713 | } else if (event_trb != td->last_trb) { | |
1714 | xhci_warn(xhci, "WARN: Success on ctrl data TRB " | |
1715 | "without IOC set??\n"); | |
1716 | *status = -ESHUTDOWN; | |
1717 | } else { | |
8af56be1 AX |
1718 | *status = 0; |
1719 | } | |
1720 | break; | |
1721 | case COMP_SHORT_TX: | |
8af56be1 AX |
1722 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
1723 | *status = -EREMOTEIO; | |
1724 | else | |
1725 | *status = 0; | |
1726 | break; | |
3abeca99 SS |
1727 | case COMP_STOP_INVAL: |
1728 | case COMP_STOP: | |
1729 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
8af56be1 AX |
1730 | default: |
1731 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
1732 | ep_ctx, trb_comp_code)) | |
1733 | break; | |
1734 | xhci_dbg(xhci, "TRB error code %u, " | |
1735 | "halted endpoint index = %u\n", | |
1736 | trb_comp_code, ep_index); | |
1737 | /* else fall through */ | |
1738 | case COMP_STALL: | |
1739 | /* Did we transfer part of the data (middle) phase? */ | |
1740 | if (event_trb != ep_ring->dequeue && | |
1741 | event_trb != td->last_trb) | |
1742 | td->urb->actual_length = | |
1743 | td->urb->transfer_buffer_length | |
28ccd296 | 1744 | - TRB_LEN(le32_to_cpu(event->transfer_len)); |
8af56be1 AX |
1745 | else |
1746 | td->urb->actual_length = 0; | |
1747 | ||
1748 | xhci_cleanup_halted_endpoint(xhci, | |
1749 | slot_id, ep_index, 0, td, event_trb); | |
1750 | return finish_td(xhci, td, event_trb, event, ep, status, true); | |
1751 | } | |
1752 | /* | |
1753 | * Did we transfer any data, despite the errors that might have | |
1754 | * happened? I.e. did we get past the setup stage? | |
1755 | */ | |
1756 | if (event_trb != ep_ring->dequeue) { | |
1757 | /* The event was for the status stage */ | |
1758 | if (event_trb == td->last_trb) { | |
1759 | if (td->urb->actual_length != 0) { | |
1760 | /* Don't overwrite a previously set error code | |
1761 | */ | |
1762 | if ((*status == -EINPROGRESS || *status == 0) && | |
1763 | (td->urb->transfer_flags | |
1764 | & URB_SHORT_NOT_OK)) | |
1765 | /* Did we already see a short data | |
1766 | * stage? */ | |
1767 | *status = -EREMOTEIO; | |
1768 | } else { | |
1769 | td->urb->actual_length = | |
1770 | td->urb->transfer_buffer_length; | |
1771 | } | |
1772 | } else { | |
1773 | /* Maybe the event was for the data stage? */ | |
3abeca99 SS |
1774 | td->urb->actual_length = |
1775 | td->urb->transfer_buffer_length - | |
1776 | TRB_LEN(le32_to_cpu(event->transfer_len)); | |
1777 | xhci_dbg(xhci, "Waiting for status " | |
1778 | "stage event\n"); | |
1779 | return 0; | |
8af56be1 AX |
1780 | } |
1781 | } | |
1782 | ||
1783 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
1784 | } | |
1785 | ||
04e51901 AX |
1786 | /* |
1787 | * Process isochronous tds, update urb packet status and actual_length. | |
1788 | */ | |
1789 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1790 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1791 | struct xhci_virt_ep *ep, int *status) | |
1792 | { | |
1793 | struct xhci_ring *ep_ring; | |
1794 | struct urb_priv *urb_priv; | |
1795 | int idx; | |
1796 | int len = 0; | |
04e51901 AX |
1797 | union xhci_trb *cur_trb; |
1798 | struct xhci_segment *cur_seg; | |
926008c9 | 1799 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 1800 | u32 trb_comp_code; |
926008c9 | 1801 | bool skip_td = false; |
04e51901 | 1802 | |
28ccd296 ME |
1803 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
1804 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
04e51901 AX |
1805 | urb_priv = td->urb->hcpriv; |
1806 | idx = urb_priv->td_cnt; | |
926008c9 | 1807 | frame = &td->urb->iso_frame_desc[idx]; |
04e51901 | 1808 | |
926008c9 DT |
1809 | /* handle completion code */ |
1810 | switch (trb_comp_code) { | |
1811 | case COMP_SUCCESS: | |
1530bbc6 SS |
1812 | if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) { |
1813 | frame->status = 0; | |
1814 | break; | |
1815 | } | |
1816 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) | |
1817 | trb_comp_code = COMP_SHORT_TX; | |
926008c9 DT |
1818 | case COMP_SHORT_TX: |
1819 | frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
1820 | -EREMOTEIO : 0; | |
1821 | break; | |
1822 | case COMP_BW_OVER: | |
1823 | frame->status = -ECOMM; | |
1824 | skip_td = true; | |
1825 | break; | |
1826 | case COMP_BUFF_OVER: | |
1827 | case COMP_BABBLE: | |
1828 | frame->status = -EOVERFLOW; | |
1829 | skip_td = true; | |
1830 | break; | |
f6ba6fe2 | 1831 | case COMP_DEV_ERR: |
926008c9 | 1832 | case COMP_STALL: |
9c745995 | 1833 | case COMP_TX_ERR: |
926008c9 DT |
1834 | frame->status = -EPROTO; |
1835 | skip_td = true; | |
1836 | break; | |
1837 | case COMP_STOP: | |
1838 | case COMP_STOP_INVAL: | |
1839 | break; | |
1840 | default: | |
1841 | frame->status = -1; | |
1842 | break; | |
04e51901 AX |
1843 | } |
1844 | ||
926008c9 DT |
1845 | if (trb_comp_code == COMP_SUCCESS || skip_td) { |
1846 | frame->actual_length = frame->length; | |
1847 | td->urb->actual_length += frame->length; | |
04e51901 AX |
1848 | } else { |
1849 | for (cur_trb = ep_ring->dequeue, | |
1850 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; | |
1851 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 ME |
1852 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
1853 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) | |
28ccd296 | 1854 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
04e51901 | 1855 | } |
28ccd296 ME |
1856 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1857 | TRB_LEN(le32_to_cpu(event->transfer_len)); | |
04e51901 AX |
1858 | |
1859 | if (trb_comp_code != COMP_STOP_INVAL) { | |
926008c9 | 1860 | frame->actual_length = len; |
04e51901 AX |
1861 | td->urb->actual_length += len; |
1862 | } | |
1863 | } | |
1864 | ||
04e51901 AX |
1865 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
1866 | } | |
1867 | ||
926008c9 DT |
1868 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
1869 | struct xhci_transfer_event *event, | |
1870 | struct xhci_virt_ep *ep, int *status) | |
1871 | { | |
1872 | struct xhci_ring *ep_ring; | |
1873 | struct urb_priv *urb_priv; | |
1874 | struct usb_iso_packet_descriptor *frame; | |
1875 | int idx; | |
1876 | ||
f6975314 | 1877 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
926008c9 DT |
1878 | urb_priv = td->urb->hcpriv; |
1879 | idx = urb_priv->td_cnt; | |
1880 | frame = &td->urb->iso_frame_desc[idx]; | |
1881 | ||
b3df3f9c | 1882 | /* The transfer is partly done. */ |
926008c9 DT |
1883 | frame->status = -EXDEV; |
1884 | ||
1885 | /* calc actual length */ | |
1886 | frame->actual_length = 0; | |
1887 | ||
1888 | /* Update ring dequeue pointer */ | |
1889 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
1890 | inc_deq(xhci, ep_ring); |
1891 | inc_deq(xhci, ep_ring); | |
926008c9 DT |
1892 | |
1893 | return finish_td(xhci, td, NULL, event, ep, status, true); | |
1894 | } | |
1895 | ||
22405ed2 AX |
1896 | /* |
1897 | * Process bulk and interrupt tds, update urb status and actual_length. | |
1898 | */ | |
1899 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1900 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1901 | struct xhci_virt_ep *ep, int *status) | |
1902 | { | |
1903 | struct xhci_ring *ep_ring; | |
1904 | union xhci_trb *cur_trb; | |
1905 | struct xhci_segment *cur_seg; | |
1906 | u32 trb_comp_code; | |
1907 | ||
28ccd296 ME |
1908 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
1909 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
22405ed2 AX |
1910 | |
1911 | switch (trb_comp_code) { | |
1912 | case COMP_SUCCESS: | |
1913 | /* Double check that the HW transferred everything. */ | |
1530bbc6 SS |
1914 | if (event_trb != td->last_trb || |
1915 | TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { | |
22405ed2 AX |
1916 | xhci_warn(xhci, "WARN Successful completion " |
1917 | "on short TX\n"); | |
1918 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1919 | *status = -EREMOTEIO; | |
1920 | else | |
1921 | *status = 0; | |
1530bbc6 SS |
1922 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) |
1923 | trb_comp_code = COMP_SHORT_TX; | |
22405ed2 | 1924 | } else { |
22405ed2 AX |
1925 | *status = 0; |
1926 | } | |
1927 | break; | |
1928 | case COMP_SHORT_TX: | |
1929 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1930 | *status = -EREMOTEIO; | |
1931 | else | |
1932 | *status = 0; | |
1933 | break; | |
1934 | default: | |
1935 | /* Others already handled above */ | |
1936 | break; | |
1937 | } | |
f444ff27 SS |
1938 | if (trb_comp_code == COMP_SHORT_TX) |
1939 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, " | |
1940 | "%d bytes untransferred\n", | |
1941 | td->urb->ep->desc.bEndpointAddress, | |
1942 | td->urb->transfer_buffer_length, | |
1943 | TRB_LEN(le32_to_cpu(event->transfer_len))); | |
22405ed2 AX |
1944 | /* Fast path - was this the last TRB in the TD for this URB? */ |
1945 | if (event_trb == td->last_trb) { | |
28ccd296 | 1946 | if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
22405ed2 AX |
1947 | td->urb->actual_length = |
1948 | td->urb->transfer_buffer_length - | |
28ccd296 | 1949 | TRB_LEN(le32_to_cpu(event->transfer_len)); |
22405ed2 AX |
1950 | if (td->urb->transfer_buffer_length < |
1951 | td->urb->actual_length) { | |
1952 | xhci_warn(xhci, "HC gave bad length " | |
1953 | "of %d bytes left\n", | |
28ccd296 | 1954 | TRB_LEN(le32_to_cpu(event->transfer_len))); |
22405ed2 AX |
1955 | td->urb->actual_length = 0; |
1956 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1957 | *status = -EREMOTEIO; | |
1958 | else | |
1959 | *status = 0; | |
1960 | } | |
1961 | /* Don't overwrite a previously set error code */ | |
1962 | if (*status == -EINPROGRESS) { | |
1963 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1964 | *status = -EREMOTEIO; | |
1965 | else | |
1966 | *status = 0; | |
1967 | } | |
1968 | } else { | |
1969 | td->urb->actual_length = | |
1970 | td->urb->transfer_buffer_length; | |
1971 | /* Ignore a short packet completion if the | |
1972 | * untransferred length was zero. | |
1973 | */ | |
1974 | if (*status == -EREMOTEIO) | |
1975 | *status = 0; | |
1976 | } | |
1977 | } else { | |
1978 | /* Slow path - walk the list, starting from the dequeue | |
1979 | * pointer, to get the actual length transferred. | |
1980 | */ | |
1981 | td->urb->actual_length = 0; | |
1982 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; | |
1983 | cur_trb != event_trb; | |
1984 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 ME |
1985 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
1986 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) | |
22405ed2 | 1987 | td->urb->actual_length += |
28ccd296 | 1988 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
22405ed2 AX |
1989 | } |
1990 | /* If the ring didn't stop on a Link or No-op TRB, add | |
1991 | * in the actual bytes transferred from the Normal TRB | |
1992 | */ | |
1993 | if (trb_comp_code != COMP_STOP_INVAL) | |
1994 | td->urb->actual_length += | |
28ccd296 ME |
1995 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1996 | TRB_LEN(le32_to_cpu(event->transfer_len)); | |
22405ed2 AX |
1997 | } |
1998 | ||
1999 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
2000 | } | |
2001 | ||
d0e96f5a SS |
2002 | /* |
2003 | * If this function returns an error condition, it means it got a Transfer | |
2004 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2005 | * At this point, the host controller is probably hosed and should be reset. | |
2006 | */ | |
2007 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2008 | struct xhci_transfer_event *event) | |
2009 | { | |
2010 | struct xhci_virt_device *xdev; | |
63a0d9ab | 2011 | struct xhci_virt_ep *ep; |
d0e96f5a | 2012 | struct xhci_ring *ep_ring; |
82d1009f | 2013 | unsigned int slot_id; |
d0e96f5a | 2014 | int ep_index; |
326b4810 | 2015 | struct xhci_td *td = NULL; |
d0e96f5a SS |
2016 | dma_addr_t event_dma; |
2017 | struct xhci_segment *event_seg; | |
2018 | union xhci_trb *event_trb; | |
326b4810 | 2019 | struct urb *urb = NULL; |
d0e96f5a | 2020 | int status = -EINPROGRESS; |
8e51adcc | 2021 | struct urb_priv *urb_priv; |
d115b048 | 2022 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2023 | struct list_head *tmp; |
66d1eebc | 2024 | u32 trb_comp_code; |
4422da61 | 2025 | int ret = 0; |
c2d7b49f | 2026 | int td_num = 0; |
d0e96f5a | 2027 | |
28ccd296 | 2028 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
82d1009f | 2029 | xdev = xhci->devs[slot_id]; |
d0e96f5a SS |
2030 | if (!xdev) { |
2031 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | |
9258c0b2 | 2032 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2033 | (unsigned long long) xhci_trb_virt_to_dma( |
2034 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2035 | xhci->event_ring->dequeue), |
2036 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2037 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2038 | le32_to_cpu(event->transfer_len), | |
2039 | le32_to_cpu(event->flags)); | |
2040 | xhci_dbg(xhci, "Event ring:\n"); | |
2041 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2042 | return -ENODEV; |
2043 | } | |
2044 | ||
2045 | /* Endpoint ID is 1 based, our index is zero based */ | |
28ccd296 | 2046 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
63a0d9ab | 2047 | ep = &xdev->eps[ep_index]; |
28ccd296 | 2048 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
d115b048 | 2049 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
986a92d4 | 2050 | if (!ep_ring || |
28ccd296 ME |
2051 | (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == |
2052 | EP_STATE_DISABLED) { | |
e9df17eb SS |
2053 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
2054 | "or incorrect stream ring\n"); | |
9258c0b2 | 2055 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2056 | (unsigned long long) xhci_trb_virt_to_dma( |
2057 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2058 | xhci->event_ring->dequeue), |
2059 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2060 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2061 | le32_to_cpu(event->transfer_len), | |
2062 | le32_to_cpu(event->flags)); | |
2063 | xhci_dbg(xhci, "Event ring:\n"); | |
2064 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2065 | return -ENODEV; |
2066 | } | |
2067 | ||
c2d7b49f AX |
2068 | /* Count current td numbers if ep->skip is set */ |
2069 | if (ep->skip) { | |
2070 | list_for_each(tmp, &ep_ring->td_list) | |
2071 | td_num++; | |
2072 | } | |
2073 | ||
28ccd296 ME |
2074 | event_dma = le64_to_cpu(event->buffer); |
2075 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
986a92d4 | 2076 | /* Look for common error cases */ |
66d1eebc | 2077 | switch (trb_comp_code) { |
b10de142 SS |
2078 | /* Skip codes that require special handling depending on |
2079 | * transfer type | |
2080 | */ | |
2081 | case COMP_SUCCESS: | |
1530bbc6 SS |
2082 | if (TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
2083 | break; | |
2084 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2085 | trb_comp_code = COMP_SHORT_TX; | |
2086 | else | |
8202ce2e SS |
2087 | xhci_warn_ratelimited(xhci, |
2088 | "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n"); | |
b10de142 SS |
2089 | case COMP_SHORT_TX: |
2090 | break; | |
ae636747 SS |
2091 | case COMP_STOP: |
2092 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); | |
2093 | break; | |
2094 | case COMP_STOP_INVAL: | |
2095 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); | |
2096 | break; | |
b10de142 | 2097 | case COMP_STALL: |
2a9227a5 | 2098 | xhci_dbg(xhci, "Stalled endpoint\n"); |
63a0d9ab | 2099 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
2100 | status = -EPIPE; |
2101 | break; | |
2102 | case COMP_TRB_ERR: | |
2103 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); | |
2104 | status = -EILSEQ; | |
2105 | break; | |
ec74e403 | 2106 | case COMP_SPLIT_ERR: |
b10de142 | 2107 | case COMP_TX_ERR: |
2a9227a5 | 2108 | xhci_dbg(xhci, "Transfer error on endpoint\n"); |
b10de142 SS |
2109 | status = -EPROTO; |
2110 | break; | |
4a73143c | 2111 | case COMP_BABBLE: |
2a9227a5 | 2112 | xhci_dbg(xhci, "Babble error on endpoint\n"); |
4a73143c SS |
2113 | status = -EOVERFLOW; |
2114 | break; | |
b10de142 SS |
2115 | case COMP_DB_ERR: |
2116 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); | |
2117 | status = -ENOSR; | |
2118 | break; | |
986a92d4 AX |
2119 | case COMP_BW_OVER: |
2120 | xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); | |
2121 | break; | |
2122 | case COMP_BUFF_OVER: | |
2123 | xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); | |
2124 | break; | |
2125 | case COMP_UNDERRUN: | |
2126 | /* | |
2127 | * When the Isoch ring is empty, the xHC will generate | |
2128 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2129 | * Underrun Event for OUT Isoch endpoint. | |
2130 | */ | |
2131 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2132 | if (!list_empty(&ep_ring->td_list)) | |
2133 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2134 | "still with TDs queued?\n", | |
28ccd296 ME |
2135 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2136 | ep_index); | |
986a92d4 AX |
2137 | goto cleanup; |
2138 | case COMP_OVERRUN: | |
2139 | xhci_dbg(xhci, "overrun event on endpoint\n"); | |
2140 | if (!list_empty(&ep_ring->td_list)) | |
2141 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2142 | "still with TDs queued?\n", | |
28ccd296 ME |
2143 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2144 | ep_index); | |
986a92d4 | 2145 | goto cleanup; |
f6ba6fe2 AH |
2146 | case COMP_DEV_ERR: |
2147 | xhci_warn(xhci, "WARN: detect an incompatible device"); | |
2148 | status = -EPROTO; | |
2149 | break; | |
d18240db AX |
2150 | case COMP_MISSED_INT: |
2151 | /* | |
2152 | * When encounter missed service error, one or more isoc tds | |
2153 | * may be missed by xHC. | |
2154 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2155 | * short transfer when process the ep_ring next time. | |
2156 | */ | |
2157 | ep->skip = true; | |
2158 | xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); | |
2159 | goto cleanup; | |
b10de142 | 2160 | default: |
b45b5069 | 2161 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2162 | status = 0; |
2163 | break; | |
2164 | } | |
986a92d4 AX |
2165 | xhci_warn(xhci, "ERROR Unknown event condition, HC probably " |
2166 | "busted\n"); | |
2167 | goto cleanup; | |
2168 | } | |
2169 | ||
d18240db AX |
2170 | do { |
2171 | /* This TRB should be in the TD at the head of this ring's | |
2172 | * TD list. | |
2173 | */ | |
2174 | if (list_empty(&ep_ring->td_list)) { | |
2175 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d " | |
2176 | "with no TDs queued?\n", | |
28ccd296 ME |
2177 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2178 | ep_index); | |
d18240db | 2179 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", |
f5960b69 ME |
2180 | (le32_to_cpu(event->flags) & |
2181 | TRB_TYPE_BITMASK)>>10); | |
d18240db AX |
2182 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); |
2183 | if (ep->skip) { | |
2184 | ep->skip = false; | |
2185 | xhci_dbg(xhci, "td_list is empty while skip " | |
2186 | "flag set. Clear skip flag.\n"); | |
2187 | } | |
2188 | ret = 0; | |
2189 | goto cleanup; | |
2190 | } | |
986a92d4 | 2191 | |
c2d7b49f AX |
2192 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2193 | if (ep->skip && td_num == 0) { | |
2194 | ep->skip = false; | |
2195 | xhci_dbg(xhci, "All tds on the ep_ring skipped. " | |
2196 | "Clear skip flag.\n"); | |
2197 | ret = 0; | |
2198 | goto cleanup; | |
2199 | } | |
2200 | ||
d18240db | 2201 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
c2d7b49f AX |
2202 | if (ep->skip) |
2203 | td_num--; | |
926008c9 | 2204 | |
d18240db AX |
2205 | /* Is this a TRB in the currently executing TD? */ |
2206 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, | |
2207 | td->last_trb, event_dma); | |
e1cf486d AH |
2208 | |
2209 | /* | |
2210 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2211 | * is not in the current TD pointed by ep_ring->dequeue because | |
2212 | * that the hardware dequeue pointer still at the previous TRB | |
2213 | * of the current TD. The previous TRB maybe a Link TD or the | |
2214 | * last TRB of the previous TD. The command completion handle | |
2215 | * will take care the rest. | |
2216 | */ | |
2217 | if (!event_seg && trb_comp_code == COMP_STOP_INVAL) { | |
2218 | ret = 0; | |
2219 | goto cleanup; | |
2220 | } | |
2221 | ||
926008c9 DT |
2222 | if (!event_seg) { |
2223 | if (!ep->skip || | |
2224 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2225 | /* Some host controllers give a spurious |
2226 | * successful event after a short transfer. | |
2227 | * Ignore it. | |
2228 | */ | |
2229 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && | |
2230 | ep_ring->last_td_was_short) { | |
2231 | ep_ring->last_td_was_short = false; | |
2232 | ret = 0; | |
2233 | goto cleanup; | |
2234 | } | |
926008c9 DT |
2235 | /* HC is busted, give up! */ |
2236 | xhci_err(xhci, | |
2237 | "ERROR Transfer event TRB DMA ptr not " | |
2238 | "part of current TD\n"); | |
2239 | return -ESHUTDOWN; | |
2240 | } | |
2241 | ||
2242 | ret = skip_isoc_td(xhci, td, event, ep, &status); | |
2243 | goto cleanup; | |
2244 | } | |
ad808333 SS |
2245 | if (trb_comp_code == COMP_SHORT_TX) |
2246 | ep_ring->last_td_was_short = true; | |
2247 | else | |
2248 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2249 | |
2250 | if (ep->skip) { | |
d18240db AX |
2251 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); |
2252 | ep->skip = false; | |
2253 | } | |
678539cf | 2254 | |
926008c9 DT |
2255 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / |
2256 | sizeof(*event_trb)]; | |
2257 | /* | |
2258 | * No-op TRB should not trigger interrupts. | |
2259 | * If event_trb is a no-op TRB, it means the | |
2260 | * corresponding TD has been cancelled. Just ignore | |
2261 | * the TD. | |
2262 | */ | |
f5960b69 | 2263 | if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) { |
926008c9 DT |
2264 | xhci_dbg(xhci, |
2265 | "event_trb is a no-op TRB. Skip it\n"); | |
2266 | goto cleanup; | |
d18240db | 2267 | } |
4422da61 | 2268 | |
d18240db AX |
2269 | /* Now update the urb's actual_length and give back to |
2270 | * the core | |
82d1009f | 2271 | */ |
d18240db AX |
2272 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
2273 | ret = process_ctrl_td(xhci, td, event_trb, event, ep, | |
2274 | &status); | |
04e51901 AX |
2275 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
2276 | ret = process_isoc_td(xhci, td, event_trb, event, ep, | |
2277 | &status); | |
d18240db AX |
2278 | else |
2279 | ret = process_bulk_intr_td(xhci, td, event_trb, event, | |
2280 | ep, &status); | |
2281 | ||
2282 | cleanup: | |
2283 | /* | |
2284 | * Do not update event ring dequeue pointer if ep->skip is set. | |
2285 | * Will roll back to continue process missed tds. | |
2286 | */ | |
2287 | if (trb_comp_code == COMP_MISSED_INT || !ep->skip) { | |
3b72fca0 | 2288 | inc_deq(xhci, xhci->event_ring); |
d18240db AX |
2289 | } |
2290 | ||
2291 | if (ret) { | |
2292 | urb = td->urb; | |
8e51adcc | 2293 | urb_priv = urb->hcpriv; |
d18240db AX |
2294 | /* Leave the TD around for the reset endpoint function |
2295 | * to use(but only if it's not a control endpoint, | |
2296 | * since we already queued the Set TR dequeue pointer | |
2297 | * command for stalled control endpoints). | |
2298 | */ | |
2299 | if (usb_endpoint_xfer_control(&urb->ep->desc) || | |
2300 | (trb_comp_code != COMP_STALL && | |
2301 | trb_comp_code != COMP_BABBLE)) | |
8e51adcc | 2302 | xhci_urb_free_priv(xhci, urb_priv); |
d18240db | 2303 | |
214f76f7 | 2304 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
f444ff27 SS |
2305 | if ((urb->actual_length != urb->transfer_buffer_length && |
2306 | (urb->transfer_flags & | |
2307 | URB_SHORT_NOT_OK)) || | |
fd984d24 SS |
2308 | (status != 0 && |
2309 | !usb_endpoint_xfer_isoc(&urb->ep->desc))) | |
f444ff27 | 2310 | xhci_dbg(xhci, "Giveback URB %p, len = %d, " |
1949f9e2 | 2311 | "expected = %d, status = %d\n", |
f444ff27 SS |
2312 | urb, urb->actual_length, |
2313 | urb->transfer_buffer_length, | |
2314 | status); | |
d18240db | 2315 | spin_unlock(&xhci->lock); |
b3df3f9c SS |
2316 | /* EHCI, UHCI, and OHCI always unconditionally set the |
2317 | * urb->status of an isochronous endpoint to 0. | |
2318 | */ | |
2319 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
2320 | status = 0; | |
214f76f7 | 2321 | usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); |
d18240db AX |
2322 | spin_lock(&xhci->lock); |
2323 | } | |
2324 | ||
2325 | /* | |
2326 | * If ep->skip is set, it means there are missed tds on the | |
2327 | * endpoint ring need to take care of. | |
2328 | * Process them as short transfer until reach the td pointed by | |
2329 | * the event. | |
2330 | */ | |
2331 | } while (ep->skip && trb_comp_code != COMP_MISSED_INT); | |
2332 | ||
d0e96f5a SS |
2333 | return 0; |
2334 | } | |
2335 | ||
0f2a7930 SS |
2336 | /* |
2337 | * This function handles all OS-owned events on the event ring. It may drop | |
2338 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2339 | * Returns >0 for "possibly more events to process" (caller should call again), |
2340 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2341 | */ |
9dee9a21 | 2342 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2343 | { |
2344 | union xhci_trb *event; | |
0f2a7930 | 2345 | int update_ptrs = 1; |
d0e96f5a | 2346 | int ret; |
7f84eef0 SS |
2347 | |
2348 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { | |
2349 | xhci->error_bitmask |= 1 << 1; | |
9dee9a21 | 2350 | return 0; |
7f84eef0 SS |
2351 | } |
2352 | ||
2353 | event = xhci->event_ring->dequeue; | |
2354 | /* Does the HC or OS own the TRB? */ | |
28ccd296 ME |
2355 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
2356 | xhci->event_ring->cycle_state) { | |
7f84eef0 | 2357 | xhci->error_bitmask |= 1 << 2; |
9dee9a21 | 2358 | return 0; |
7f84eef0 SS |
2359 | } |
2360 | ||
92a3da41 ME |
2361 | /* |
2362 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2363 | * speculative reads of the event's flags/data below. | |
2364 | */ | |
2365 | rmb(); | |
0f2a7930 | 2366 | /* FIXME: Handle more event types. */ |
28ccd296 | 2367 | switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { |
7f84eef0 SS |
2368 | case TRB_TYPE(TRB_COMPLETION): |
2369 | handle_cmd_completion(xhci, &event->event_cmd); | |
2370 | break; | |
0f2a7930 SS |
2371 | case TRB_TYPE(TRB_PORT_STATUS): |
2372 | handle_port_status(xhci, event); | |
2373 | update_ptrs = 0; | |
2374 | break; | |
d0e96f5a SS |
2375 | case TRB_TYPE(TRB_TRANSFER): |
2376 | ret = handle_tx_event(xhci, &event->trans_event); | |
2377 | if (ret < 0) | |
2378 | xhci->error_bitmask |= 1 << 9; | |
2379 | else | |
2380 | update_ptrs = 0; | |
2381 | break; | |
623bef9e SS |
2382 | case TRB_TYPE(TRB_DEV_NOTE): |
2383 | handle_device_notification(xhci, event); | |
2384 | break; | |
7f84eef0 | 2385 | default: |
28ccd296 ME |
2386 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2387 | TRB_TYPE(48)) | |
0238634d SS |
2388 | handle_vendor_event(xhci, event); |
2389 | else | |
2390 | xhci->error_bitmask |= 1 << 3; | |
7f84eef0 | 2391 | } |
6f5165cf SS |
2392 | /* Any of the above functions may drop and re-acquire the lock, so check |
2393 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2394 | */ | |
2395 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2396 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2397 | "event handler.\n"); | |
9dee9a21 | 2398 | return 0; |
6f5165cf | 2399 | } |
7f84eef0 | 2400 | |
c06d68b8 SS |
2401 | if (update_ptrs) |
2402 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 2403 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 2404 | |
9dee9a21 ME |
2405 | /* Are there more items on the event ring? Caller will call us again to |
2406 | * check. | |
2407 | */ | |
2408 | return 1; | |
7f84eef0 | 2409 | } |
9032cd52 SS |
2410 | |
2411 | /* | |
2412 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2413 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2414 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2415 | */ | |
2416 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2417 | { | |
2418 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c21599a3 | 2419 | u32 status; |
9032cd52 | 2420 | union xhci_trb *trb; |
bda53145 | 2421 | u64 temp_64; |
c06d68b8 SS |
2422 | union xhci_trb *event_ring_deq; |
2423 | dma_addr_t deq; | |
9032cd52 SS |
2424 | |
2425 | spin_lock(&xhci->lock); | |
2426 | trb = xhci->event_ring->dequeue; | |
2427 | /* Check if the xHC generated the interrupt, or the irq is shared */ | |
27e0dd4d | 2428 | status = xhci_readl(xhci, &xhci->op_regs->status); |
c21599a3 | 2429 | if (status == 0xffffffff) |
9032cd52 SS |
2430 | goto hw_died; |
2431 | ||
c21599a3 | 2432 | if (!(status & STS_EINT)) { |
9032cd52 | 2433 | spin_unlock(&xhci->lock); |
9032cd52 SS |
2434 | return IRQ_NONE; |
2435 | } | |
27e0dd4d | 2436 | if (status & STS_FATAL) { |
9032cd52 SS |
2437 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2438 | xhci_halt(xhci); | |
2439 | hw_died: | |
9032cd52 SS |
2440 | spin_unlock(&xhci->lock); |
2441 | return -ESHUTDOWN; | |
2442 | } | |
2443 | ||
bda53145 SS |
2444 | /* |
2445 | * Clear the op reg interrupt status first, | |
2446 | * so we can receive interrupts from other MSI-X interrupters. | |
2447 | * Write 1 to clear the interrupt status. | |
2448 | */ | |
27e0dd4d SS |
2449 | status |= STS_EINT; |
2450 | xhci_writel(xhci, status, &xhci->op_regs->status); | |
bda53145 SS |
2451 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
2452 | /* Clear the MSI-X event interrupt status */ | |
2453 | ||
cd70469d | 2454 | if (hcd->irq) { |
c21599a3 SS |
2455 | u32 irq_pending; |
2456 | /* Acknowledge the PCI interrupt */ | |
2457 | irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending); | |
4e833c0b | 2458 | irq_pending |= IMAN_IP; |
c21599a3 SS |
2459 | xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending); |
2460 | } | |
bda53145 | 2461 | |
c06d68b8 | 2462 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
bda53145 SS |
2463 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2464 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2465 | /* Clear the event handler busy flag (RW1C); |
2466 | * the event ring should be empty. | |
bda53145 | 2467 | */ |
c06d68b8 SS |
2468 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
2469 | xhci_write_64(xhci, temp_64 | ERST_EHB, | |
2470 | &xhci->ir_set->erst_dequeue); | |
2471 | spin_unlock(&xhci->lock); | |
2472 | ||
2473 | return IRQ_HANDLED; | |
2474 | } | |
2475 | ||
2476 | event_ring_deq = xhci->event_ring->dequeue; | |
2477 | /* FIXME this should be a delayed service routine | |
2478 | * that clears the EHB. | |
2479 | */ | |
9dee9a21 | 2480 | while (xhci_handle_event(xhci) > 0) {} |
bda53145 | 2481 | |
bda53145 | 2482 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2483 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2484 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2485 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2486 | xhci->event_ring->dequeue); | |
2487 | if (deq == 0) | |
2488 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2489 | "ring dequeue ptr.\n"); | |
2490 | /* Update HC event ring dequeue pointer */ | |
2491 | temp_64 &= ERST_PTR_MASK; | |
2492 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2493 | } | |
2494 | ||
2495 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2496 | temp_64 |= ERST_EHB; | |
2497 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); | |
2498 | ||
9032cd52 SS |
2499 | spin_unlock(&xhci->lock); |
2500 | ||
2501 | return IRQ_HANDLED; | |
2502 | } | |
2503 | ||
2504 | irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd) | |
2505 | { | |
968b822c | 2506 | return xhci_irq(hcd); |
9032cd52 | 2507 | } |
7f84eef0 | 2508 | |
d0e96f5a SS |
2509 | /**** Endpoint Ring Operations ****/ |
2510 | ||
7f84eef0 SS |
2511 | /* |
2512 | * Generic function for queueing a TRB on a ring. | |
2513 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2514 | * |
2515 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2516 | * prepare_transfer()? | |
7f84eef0 SS |
2517 | */ |
2518 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 2519 | bool more_trbs_coming, |
7f84eef0 SS |
2520 | u32 field1, u32 field2, u32 field3, u32 field4) |
2521 | { | |
2522 | struct xhci_generic_trb *trb; | |
2523 | ||
2524 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
2525 | trb->field[0] = cpu_to_le32(field1); |
2526 | trb->field[1] = cpu_to_le32(field2); | |
2527 | trb->field[2] = cpu_to_le32(field3); | |
2528 | trb->field[3] = cpu_to_le32(field4); | |
3b72fca0 | 2529 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
2530 | } |
2531 | ||
d0e96f5a SS |
2532 | /* |
2533 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2534 | * FIXME allocate segments if the ring is full. | |
2535 | */ | |
2536 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 2537 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 2538 | { |
8dfec614 AX |
2539 | unsigned int num_trbs_needed; |
2540 | ||
d0e96f5a | 2541 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
2542 | switch (ep_state) { |
2543 | case EP_STATE_DISABLED: | |
2544 | /* | |
2545 | * USB core changed config/interfaces without notifying us, | |
2546 | * or hardware is reporting the wrong state. | |
2547 | */ | |
2548 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2549 | return -ENOENT; | |
d0e96f5a | 2550 | case EP_STATE_ERROR: |
c92bcfa7 | 2551 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
2552 | /* FIXME event handling code for error needs to clear it */ |
2553 | /* XXX not sure if this should be -ENOENT or not */ | |
2554 | return -EINVAL; | |
c92bcfa7 SS |
2555 | case EP_STATE_HALTED: |
2556 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
2557 | case EP_STATE_STOPPED: |
2558 | case EP_STATE_RUNNING: | |
2559 | break; | |
2560 | default: | |
2561 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
2562 | /* | |
2563 | * FIXME issue Configure Endpoint command to try to get the HC | |
2564 | * back into a known state. | |
2565 | */ | |
2566 | return -EINVAL; | |
2567 | } | |
8dfec614 AX |
2568 | |
2569 | while (1) { | |
2570 | if (room_on_ring(xhci, ep_ring, num_trbs)) | |
2571 | break; | |
2572 | ||
2573 | if (ep_ring == xhci->cmd_ring) { | |
2574 | xhci_err(xhci, "Do not support expand command ring\n"); | |
2575 | return -ENOMEM; | |
2576 | } | |
2577 | ||
8dfec614 AX |
2578 | xhci_dbg(xhci, "ERROR no room on ep ring, " |
2579 | "try ring expansion\n"); | |
2580 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; | |
2581 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
2582 | mem_flags)) { | |
2583 | xhci_err(xhci, "Ring expansion failed\n"); | |
2584 | return -ENOMEM; | |
2585 | } | |
2586 | }; | |
6c12db90 JY |
2587 | |
2588 | if (enqueue_is_link_trb(ep_ring)) { | |
2589 | struct xhci_ring *ring = ep_ring; | |
2590 | union xhci_trb *next; | |
6c12db90 | 2591 | |
6c12db90 JY |
2592 | next = ring->enqueue; |
2593 | ||
2594 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
7e393a83 AX |
2595 | /* If we're not dealing with 0.95 hardware or isoc rings |
2596 | * on AMD 0.96 host, clear the chain bit. | |
6c12db90 | 2597 | */ |
3b72fca0 AX |
2598 | if (!xhci_link_trb_quirk(xhci) && |
2599 | !(ring->type == TYPE_ISOC && | |
2600 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
28ccd296 | 2601 | next->link.control &= cpu_to_le32(~TRB_CHAIN); |
6c12db90 | 2602 | else |
28ccd296 | 2603 | next->link.control |= cpu_to_le32(TRB_CHAIN); |
6c12db90 JY |
2604 | |
2605 | wmb(); | |
f5960b69 | 2606 | next->link.control ^= cpu_to_le32(TRB_CYCLE); |
6c12db90 JY |
2607 | |
2608 | /* Toggle the cycle bit after the last ring segment. */ | |
2609 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
2610 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
6c12db90 JY |
2611 | } |
2612 | ring->enq_seg = ring->enq_seg->next; | |
2613 | ring->enqueue = ring->enq_seg->trbs; | |
2614 | next = ring->enqueue; | |
2615 | } | |
2616 | } | |
2617 | ||
d0e96f5a SS |
2618 | return 0; |
2619 | } | |
2620 | ||
23e3be11 | 2621 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
2622 | struct xhci_virt_device *xdev, |
2623 | unsigned int ep_index, | |
e9df17eb | 2624 | unsigned int stream_id, |
d0e96f5a SS |
2625 | unsigned int num_trbs, |
2626 | struct urb *urb, | |
8e51adcc | 2627 | unsigned int td_index, |
d0e96f5a SS |
2628 | gfp_t mem_flags) |
2629 | { | |
2630 | int ret; | |
8e51adcc AX |
2631 | struct urb_priv *urb_priv; |
2632 | struct xhci_td *td; | |
e9df17eb | 2633 | struct xhci_ring *ep_ring; |
d115b048 | 2634 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
2635 | |
2636 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
2637 | if (!ep_ring) { | |
2638 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
2639 | stream_id); | |
2640 | return -EINVAL; | |
2641 | } | |
2642 | ||
2643 | ret = prepare_ring(xhci, ep_ring, | |
28ccd296 | 2644 | le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3b72fca0 | 2645 | num_trbs, mem_flags); |
d0e96f5a SS |
2646 | if (ret) |
2647 | return ret; | |
d0e96f5a | 2648 | |
8e51adcc AX |
2649 | urb_priv = urb->hcpriv; |
2650 | td = urb_priv->td[td_index]; | |
2651 | ||
2652 | INIT_LIST_HEAD(&td->td_list); | |
2653 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
2654 | ||
2655 | if (td_index == 0) { | |
214f76f7 | 2656 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 2657 | if (unlikely(ret)) |
8e51adcc | 2658 | return ret; |
d0e96f5a SS |
2659 | } |
2660 | ||
8e51adcc | 2661 | td->urb = urb; |
d0e96f5a | 2662 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
2663 | list_add_tail(&td->td_list, &ep_ring->td_list); |
2664 | td->start_seg = ep_ring->enq_seg; | |
2665 | td->first_trb = ep_ring->enqueue; | |
2666 | ||
2667 | urb_priv->td[td_index] = td; | |
d0e96f5a SS |
2668 | |
2669 | return 0; | |
2670 | } | |
2671 | ||
23e3be11 | 2672 | static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) |
8a96c052 SS |
2673 | { |
2674 | int num_sgs, num_trbs, running_total, temp, i; | |
2675 | struct scatterlist *sg; | |
2676 | ||
2677 | sg = NULL; | |
bc677d5b | 2678 | num_sgs = urb->num_mapped_sgs; |
8a96c052 SS |
2679 | temp = urb->transfer_buffer_length; |
2680 | ||
8a96c052 | 2681 | num_trbs = 0; |
910f8d0c | 2682 | for_each_sg(urb->sg, sg, num_sgs, i) { |
8a96c052 SS |
2683 | unsigned int len = sg_dma_len(sg); |
2684 | ||
2685 | /* Scatter gather list entries may cross 64KB boundaries */ | |
2686 | running_total = TRB_MAX_BUFF_SIZE - | |
a2490187 | 2687 | (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 2688 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
8a96c052 SS |
2689 | if (running_total != 0) |
2690 | num_trbs++; | |
2691 | ||
2692 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
bcd2fde0 | 2693 | while (running_total < sg_dma_len(sg) && running_total < temp) { |
8a96c052 SS |
2694 | num_trbs++; |
2695 | running_total += TRB_MAX_BUFF_SIZE; | |
2696 | } | |
8a96c052 SS |
2697 | len = min_t(int, len, temp); |
2698 | temp -= len; | |
2699 | if (temp == 0) | |
2700 | break; | |
2701 | } | |
8a96c052 SS |
2702 | return num_trbs; |
2703 | } | |
2704 | ||
23e3be11 | 2705 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
8a96c052 SS |
2706 | { |
2707 | if (num_trbs != 0) | |
a2490187 | 2708 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " |
8a96c052 SS |
2709 | "TRBs, %d left\n", __func__, |
2710 | urb->ep->desc.bEndpointAddress, num_trbs); | |
2711 | if (running_total != urb->transfer_buffer_length) | |
a2490187 | 2712 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
2713 | "queued %#x (%d), asked for %#x (%d)\n", |
2714 | __func__, | |
2715 | urb->ep->desc.bEndpointAddress, | |
2716 | running_total, running_total, | |
2717 | urb->transfer_buffer_length, | |
2718 | urb->transfer_buffer_length); | |
2719 | } | |
2720 | ||
23e3be11 | 2721 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 2722 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 2723 | struct xhci_generic_trb *start_trb) |
8a96c052 | 2724 | { |
8a96c052 SS |
2725 | /* |
2726 | * Pass all the TRBs to the hardware at once and make sure this write | |
2727 | * isn't reordered. | |
2728 | */ | |
2729 | wmb(); | |
50f7b52a | 2730 | if (start_cycle) |
28ccd296 | 2731 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 2732 | else |
28ccd296 | 2733 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 2734 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
2735 | } |
2736 | ||
624defa1 SS |
2737 | /* |
2738 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
2739 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
2740 | * (comprised of sg list entries) can take several service intervals to | |
2741 | * transmit. | |
2742 | */ | |
2743 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
2744 | struct urb *urb, int slot_id, unsigned int ep_index) | |
2745 | { | |
2746 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, | |
2747 | xhci->devs[slot_id]->out_ctx, ep_index); | |
2748 | int xhci_interval; | |
2749 | int ep_interval; | |
2750 | ||
28ccd296 | 2751 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 SS |
2752 | ep_interval = urb->interval; |
2753 | /* Convert to microframes */ | |
2754 | if (urb->dev->speed == USB_SPEED_LOW || | |
2755 | urb->dev->speed == USB_SPEED_FULL) | |
2756 | ep_interval *= 8; | |
2757 | /* FIXME change this to a warning and a suggestion to use the new API | |
2758 | * to set the polling interval (once the API is added). | |
2759 | */ | |
2760 | if (xhci_interval != ep_interval) { | |
7961acd7 | 2761 | if (printk_ratelimit()) |
624defa1 SS |
2762 | dev_dbg(&urb->dev->dev, "Driver uses different interval" |
2763 | " (%d microframe%s) than xHCI " | |
2764 | "(%d microframe%s)\n", | |
2765 | ep_interval, | |
2766 | ep_interval == 1 ? "" : "s", | |
2767 | xhci_interval, | |
2768 | xhci_interval == 1 ? "" : "s"); | |
2769 | urb->interval = xhci_interval; | |
2770 | /* Convert back to frames for LS/FS devices */ | |
2771 | if (urb->dev->speed == USB_SPEED_LOW || | |
2772 | urb->dev->speed == USB_SPEED_FULL) | |
2773 | urb->interval /= 8; | |
2774 | } | |
3fc8206d | 2775 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
2776 | } |
2777 | ||
04dd950d SS |
2778 | /* |
2779 | * The TD size is the number of bytes remaining in the TD (including this TRB), | |
2780 | * right shifted by 10. | |
2781 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
2782 | */ | |
2783 | static u32 xhci_td_remainder(unsigned int remainder) | |
2784 | { | |
2785 | u32 max = (1 << (21 - 17 + 1)) - 1; | |
2786 | ||
2787 | if ((remainder >> 10) >= max) | |
2788 | return max << 17; | |
2789 | else | |
2790 | return (remainder >> 10) << 17; | |
2791 | } | |
2792 | ||
4da6e6f2 SS |
2793 | /* |
2794 | * For xHCI 1.0 host controllers, TD size is the number of packets remaining in | |
2795 | * the TD (*not* including this TRB). | |
2796 | * | |
2797 | * Total TD packet count = total_packet_count = | |
2798 | * roundup(TD size in bytes / wMaxPacketSize) | |
2799 | * | |
2800 | * Packets transferred up to and including this TRB = packets_transferred = | |
2801 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
2802 | * | |
2803 | * TD size = total_packet_count - packets_transferred | |
2804 | * | |
2805 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
2806 | */ | |
2807 | ||
2808 | static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len, | |
2809 | unsigned int total_packet_count, struct urb *urb) | |
2810 | { | |
2811 | int packets_transferred; | |
2812 | ||
48df4a6f SS |
2813 | /* One TRB with a zero-length data packet. */ |
2814 | if (running_total == 0 && trb_buff_len == 0) | |
2815 | return 0; | |
2816 | ||
4da6e6f2 SS |
2817 | /* All the TRB queueing functions don't count the current TRB in |
2818 | * running_total. | |
2819 | */ | |
2820 | packets_transferred = (running_total + trb_buff_len) / | |
29cc8897 | 2821 | usb_endpoint_maxp(&urb->ep->desc); |
4da6e6f2 SS |
2822 | |
2823 | return xhci_td_remainder(total_packet_count - packets_transferred); | |
2824 | } | |
2825 | ||
23e3be11 | 2826 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
8a96c052 SS |
2827 | struct urb *urb, int slot_id, unsigned int ep_index) |
2828 | { | |
2829 | struct xhci_ring *ep_ring; | |
2830 | unsigned int num_trbs; | |
8e51adcc | 2831 | struct urb_priv *urb_priv; |
8a96c052 SS |
2832 | struct xhci_td *td; |
2833 | struct scatterlist *sg; | |
2834 | int num_sgs; | |
2835 | int trb_buff_len, this_sg_len, running_total; | |
4da6e6f2 | 2836 | unsigned int total_packet_count; |
8a96c052 SS |
2837 | bool first_trb; |
2838 | u64 addr; | |
6cc30d85 | 2839 | bool more_trbs_coming; |
8a96c052 SS |
2840 | |
2841 | struct xhci_generic_trb *start_trb; | |
2842 | int start_cycle; | |
2843 | ||
e9df17eb SS |
2844 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
2845 | if (!ep_ring) | |
2846 | return -EINVAL; | |
2847 | ||
8a96c052 | 2848 | num_trbs = count_sg_trbs_needed(xhci, urb); |
bc677d5b | 2849 | num_sgs = urb->num_mapped_sgs; |
4da6e6f2 | 2850 | total_packet_count = roundup(urb->transfer_buffer_length, |
29cc8897 | 2851 | usb_endpoint_maxp(&urb->ep->desc)); |
8a96c052 | 2852 | |
23e3be11 | 2853 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 2854 | ep_index, urb->stream_id, |
3b72fca0 | 2855 | num_trbs, urb, 0, mem_flags); |
8a96c052 SS |
2856 | if (trb_buff_len < 0) |
2857 | return trb_buff_len; | |
8e51adcc AX |
2858 | |
2859 | urb_priv = urb->hcpriv; | |
2860 | td = urb_priv->td[0]; | |
2861 | ||
8a96c052 SS |
2862 | /* |
2863 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
2864 | * until we've finished creating all the other TRBs. The ring's cycle | |
2865 | * state may change as we enqueue the other TRBs, so save it too. | |
2866 | */ | |
2867 | start_trb = &ep_ring->enqueue->generic; | |
2868 | start_cycle = ep_ring->cycle_state; | |
2869 | ||
2870 | running_total = 0; | |
2871 | /* | |
2872 | * How much data is in the first TRB? | |
2873 | * | |
2874 | * There are three forces at work for TRB buffer pointers and lengths: | |
2875 | * 1. We don't want to walk off the end of this sg-list entry buffer. | |
2876 | * 2. The transfer length that the driver requested may be smaller than | |
2877 | * the amount of memory allocated for this scatter-gather list. | |
2878 | * 3. TRBs buffers can't cross 64KB boundaries. | |
2879 | */ | |
910f8d0c | 2880 | sg = urb->sg; |
8a96c052 SS |
2881 | addr = (u64) sg_dma_address(sg); |
2882 | this_sg_len = sg_dma_len(sg); | |
a2490187 | 2883 | trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1)); |
8a96c052 SS |
2884 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
2885 | if (trb_buff_len > urb->transfer_buffer_length) | |
2886 | trb_buff_len = urb->transfer_buffer_length; | |
8a96c052 SS |
2887 | |
2888 | first_trb = true; | |
2889 | /* Queue the first TRB, even if it's zero-length */ | |
2890 | do { | |
2891 | u32 field = 0; | |
f9dc68fe | 2892 | u32 length_field = 0; |
04dd950d | 2893 | u32 remainder = 0; |
8a96c052 SS |
2894 | |
2895 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 2896 | if (first_trb) { |
8a96c052 | 2897 | first_trb = false; |
50f7b52a AX |
2898 | if (start_cycle == 0) |
2899 | field |= 0x1; | |
2900 | } else | |
8a96c052 SS |
2901 | field |= ep_ring->cycle_state; |
2902 | ||
2903 | /* Chain all the TRBs together; clear the chain bit in the last | |
2904 | * TRB to indicate it's the last TRB in the chain. | |
2905 | */ | |
2906 | if (num_trbs > 1) { | |
2907 | field |= TRB_CHAIN; | |
2908 | } else { | |
2909 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
2910 | td->last_trb = ep_ring->enqueue; | |
2911 | field |= TRB_IOC; | |
2912 | } | |
af8b9e63 SS |
2913 | |
2914 | /* Only set interrupt on short packet for IN endpoints */ | |
2915 | if (usb_urb_dir_in(urb)) | |
2916 | field |= TRB_ISP; | |
2917 | ||
8a96c052 | 2918 | if (TRB_MAX_BUFF_SIZE - |
a2490187 | 2919 | (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) { |
8a96c052 SS |
2920 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); |
2921 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", | |
2922 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
2923 | (unsigned int) addr + trb_buff_len); | |
2924 | } | |
4da6e6f2 SS |
2925 | |
2926 | /* Set the TRB length, TD size, and interrupter fields. */ | |
2927 | if (xhci->hci_version < 0x100) { | |
2928 | remainder = xhci_td_remainder( | |
2929 | urb->transfer_buffer_length - | |
2930 | running_total); | |
2931 | } else { | |
2932 | remainder = xhci_v1_0_td_remainder(running_total, | |
2933 | trb_buff_len, total_packet_count, urb); | |
2934 | } | |
f9dc68fe | 2935 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 2936 | remainder | |
f9dc68fe | 2937 | TRB_INTR_TARGET(0); |
4da6e6f2 | 2938 | |
6cc30d85 SS |
2939 | if (num_trbs > 1) |
2940 | more_trbs_coming = true; | |
2941 | else | |
2942 | more_trbs_coming = false; | |
3b72fca0 | 2943 | queue_trb(xhci, ep_ring, more_trbs_coming, |
8e595a5d SS |
2944 | lower_32_bits(addr), |
2945 | upper_32_bits(addr), | |
f9dc68fe | 2946 | length_field, |
af8b9e63 | 2947 | field | TRB_TYPE(TRB_NORMAL)); |
8a96c052 SS |
2948 | --num_trbs; |
2949 | running_total += trb_buff_len; | |
2950 | ||
2951 | /* Calculate length for next transfer -- | |
2952 | * Are we done queueing all the TRBs for this sg entry? | |
2953 | */ | |
2954 | this_sg_len -= trb_buff_len; | |
2955 | if (this_sg_len == 0) { | |
2956 | --num_sgs; | |
2957 | if (num_sgs == 0) | |
2958 | break; | |
2959 | sg = sg_next(sg); | |
2960 | addr = (u64) sg_dma_address(sg); | |
2961 | this_sg_len = sg_dma_len(sg); | |
2962 | } else { | |
2963 | addr += trb_buff_len; | |
2964 | } | |
2965 | ||
2966 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
a2490187 | 2967 | (addr & (TRB_MAX_BUFF_SIZE - 1)); |
8a96c052 SS |
2968 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
2969 | if (running_total + trb_buff_len > urb->transfer_buffer_length) | |
2970 | trb_buff_len = | |
2971 | urb->transfer_buffer_length - running_total; | |
2972 | } while (running_total < urb->transfer_buffer_length); | |
2973 | ||
2974 | check_trb_math(urb, num_trbs, running_total); | |
e9df17eb | 2975 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 2976 | start_cycle, start_trb); |
8a96c052 SS |
2977 | return 0; |
2978 | } | |
2979 | ||
b10de142 | 2980 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
23e3be11 | 2981 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
b10de142 SS |
2982 | struct urb *urb, int slot_id, unsigned int ep_index) |
2983 | { | |
2984 | struct xhci_ring *ep_ring; | |
8e51adcc | 2985 | struct urb_priv *urb_priv; |
b10de142 SS |
2986 | struct xhci_td *td; |
2987 | int num_trbs; | |
2988 | struct xhci_generic_trb *start_trb; | |
2989 | bool first_trb; | |
6cc30d85 | 2990 | bool more_trbs_coming; |
b10de142 | 2991 | int start_cycle; |
f9dc68fe | 2992 | u32 field, length_field; |
b10de142 SS |
2993 | |
2994 | int running_total, trb_buff_len, ret; | |
4da6e6f2 | 2995 | unsigned int total_packet_count; |
b10de142 SS |
2996 | u64 addr; |
2997 | ||
ff9c895f | 2998 | if (urb->num_sgs) |
8a96c052 SS |
2999 | return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); |
3000 | ||
e9df17eb SS |
3001 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3002 | if (!ep_ring) | |
3003 | return -EINVAL; | |
b10de142 SS |
3004 | |
3005 | num_trbs = 0; | |
3006 | /* How much data is (potentially) left before the 64KB boundary? */ | |
3007 | running_total = TRB_MAX_BUFF_SIZE - | |
a2490187 | 3008 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 3009 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
b10de142 SS |
3010 | |
3011 | /* If there's some data on this 64KB chunk, or we have to send a | |
3012 | * zero-length transfer, we need at least one TRB | |
3013 | */ | |
3014 | if (running_total != 0 || urb->transfer_buffer_length == 0) | |
3015 | num_trbs++; | |
3016 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
3017 | while (running_total < urb->transfer_buffer_length) { | |
3018 | num_trbs++; | |
3019 | running_total += TRB_MAX_BUFF_SIZE; | |
3020 | } | |
3021 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ | |
3022 | ||
e9df17eb SS |
3023 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3024 | ep_index, urb->stream_id, | |
3b72fca0 | 3025 | num_trbs, urb, 0, mem_flags); |
b10de142 SS |
3026 | if (ret < 0) |
3027 | return ret; | |
3028 | ||
8e51adcc AX |
3029 | urb_priv = urb->hcpriv; |
3030 | td = urb_priv->td[0]; | |
3031 | ||
b10de142 SS |
3032 | /* |
3033 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3034 | * until we've finished creating all the other TRBs. The ring's cycle | |
3035 | * state may change as we enqueue the other TRBs, so save it too. | |
3036 | */ | |
3037 | start_trb = &ep_ring->enqueue->generic; | |
3038 | start_cycle = ep_ring->cycle_state; | |
3039 | ||
3040 | running_total = 0; | |
4da6e6f2 | 3041 | total_packet_count = roundup(urb->transfer_buffer_length, |
29cc8897 | 3042 | usb_endpoint_maxp(&urb->ep->desc)); |
b10de142 SS |
3043 | /* How much data is in the first TRB? */ |
3044 | addr = (u64) urb->transfer_dma; | |
3045 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
a2490187 PZ |
3046 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
3047 | if (trb_buff_len > urb->transfer_buffer_length) | |
b10de142 SS |
3048 | trb_buff_len = urb->transfer_buffer_length; |
3049 | ||
3050 | first_trb = true; | |
3051 | ||
3052 | /* Queue the first TRB, even if it's zero-length */ | |
3053 | do { | |
04dd950d | 3054 | u32 remainder = 0; |
b10de142 SS |
3055 | field = 0; |
3056 | ||
3057 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 3058 | if (first_trb) { |
b10de142 | 3059 | first_trb = false; |
50f7b52a AX |
3060 | if (start_cycle == 0) |
3061 | field |= 0x1; | |
3062 | } else | |
b10de142 SS |
3063 | field |= ep_ring->cycle_state; |
3064 | ||
3065 | /* Chain all the TRBs together; clear the chain bit in the last | |
3066 | * TRB to indicate it's the last TRB in the chain. | |
3067 | */ | |
3068 | if (num_trbs > 1) { | |
3069 | field |= TRB_CHAIN; | |
3070 | } else { | |
3071 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
3072 | td->last_trb = ep_ring->enqueue; | |
3073 | field |= TRB_IOC; | |
3074 | } | |
af8b9e63 SS |
3075 | |
3076 | /* Only set interrupt on short packet for IN endpoints */ | |
3077 | if (usb_urb_dir_in(urb)) | |
3078 | field |= TRB_ISP; | |
3079 | ||
4da6e6f2 SS |
3080 | /* Set the TRB length, TD size, and interrupter fields. */ |
3081 | if (xhci->hci_version < 0x100) { | |
3082 | remainder = xhci_td_remainder( | |
3083 | urb->transfer_buffer_length - | |
3084 | running_total); | |
3085 | } else { | |
3086 | remainder = xhci_v1_0_td_remainder(running_total, | |
3087 | trb_buff_len, total_packet_count, urb); | |
3088 | } | |
f9dc68fe | 3089 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 3090 | remainder | |
f9dc68fe | 3091 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3092 | |
6cc30d85 SS |
3093 | if (num_trbs > 1) |
3094 | more_trbs_coming = true; | |
3095 | else | |
3096 | more_trbs_coming = false; | |
3b72fca0 | 3097 | queue_trb(xhci, ep_ring, more_trbs_coming, |
8e595a5d SS |
3098 | lower_32_bits(addr), |
3099 | upper_32_bits(addr), | |
f9dc68fe | 3100 | length_field, |
af8b9e63 | 3101 | field | TRB_TYPE(TRB_NORMAL)); |
b10de142 SS |
3102 | --num_trbs; |
3103 | running_total += trb_buff_len; | |
3104 | ||
3105 | /* Calculate length for next transfer */ | |
3106 | addr += trb_buff_len; | |
3107 | trb_buff_len = urb->transfer_buffer_length - running_total; | |
3108 | if (trb_buff_len > TRB_MAX_BUFF_SIZE) | |
3109 | trb_buff_len = TRB_MAX_BUFF_SIZE; | |
3110 | } while (running_total < urb->transfer_buffer_length); | |
3111 | ||
8a96c052 | 3112 | check_trb_math(urb, num_trbs, running_total); |
e9df17eb | 3113 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3114 | start_cycle, start_trb); |
b10de142 SS |
3115 | return 0; |
3116 | } | |
3117 | ||
d0e96f5a | 3118 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3119 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3120 | struct urb *urb, int slot_id, unsigned int ep_index) |
3121 | { | |
3122 | struct xhci_ring *ep_ring; | |
3123 | int num_trbs; | |
3124 | int ret; | |
3125 | struct usb_ctrlrequest *setup; | |
3126 | struct xhci_generic_trb *start_trb; | |
3127 | int start_cycle; | |
f9dc68fe | 3128 | u32 field, length_field; |
8e51adcc | 3129 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3130 | struct xhci_td *td; |
3131 | ||
e9df17eb SS |
3132 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3133 | if (!ep_ring) | |
3134 | return -EINVAL; | |
d0e96f5a SS |
3135 | |
3136 | /* | |
3137 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3138 | * DMA address. | |
3139 | */ | |
3140 | if (!urb->setup_packet) | |
3141 | return -EINVAL; | |
3142 | ||
d0e96f5a SS |
3143 | /* 1 TRB for setup, 1 for status */ |
3144 | num_trbs = 2; | |
3145 | /* | |
3146 | * Don't need to check if we need additional event data and normal TRBs, | |
3147 | * since data in control transfers will never get bigger than 16MB | |
3148 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3149 | */ | |
3150 | if (urb->transfer_buffer_length > 0) | |
3151 | num_trbs++; | |
e9df17eb SS |
3152 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3153 | ep_index, urb->stream_id, | |
3b72fca0 | 3154 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3155 | if (ret < 0) |
3156 | return ret; | |
3157 | ||
8e51adcc AX |
3158 | urb_priv = urb->hcpriv; |
3159 | td = urb_priv->td[0]; | |
3160 | ||
d0e96f5a SS |
3161 | /* |
3162 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3163 | * until we've finished creating all the other TRBs. The ring's cycle | |
3164 | * state may change as we enqueue the other TRBs, so save it too. | |
3165 | */ | |
3166 | start_trb = &ep_ring->enqueue->generic; | |
3167 | start_cycle = ep_ring->cycle_state; | |
3168 | ||
3169 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3170 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3171 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3172 | field = 0; |
3173 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3174 | if (start_cycle == 0) | |
3175 | field |= 0x1; | |
b83cdc8f AX |
3176 | |
3177 | /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ | |
3178 | if (xhci->hci_version == 0x100) { | |
3179 | if (urb->transfer_buffer_length > 0) { | |
3180 | if (setup->bRequestType & USB_DIR_IN) | |
3181 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3182 | else | |
3183 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3184 | } | |
3185 | } | |
3186 | ||
3b72fca0 | 3187 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3188 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3189 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3190 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3191 | /* Immediate data in pointer */ | |
3192 | field); | |
d0e96f5a SS |
3193 | |
3194 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3195 | /* Only set interrupt on short packet for IN endpoints */ |
3196 | if (usb_urb_dir_in(urb)) | |
3197 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3198 | else | |
3199 | field = TRB_TYPE(TRB_DATA); | |
3200 | ||
f9dc68fe | 3201 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
04dd950d | 3202 | xhci_td_remainder(urb->transfer_buffer_length) | |
f9dc68fe | 3203 | TRB_INTR_TARGET(0); |
d0e96f5a SS |
3204 | if (urb->transfer_buffer_length > 0) { |
3205 | if (setup->bRequestType & USB_DIR_IN) | |
3206 | field |= TRB_DIR_IN; | |
3b72fca0 | 3207 | queue_trb(xhci, ep_ring, true, |
d0e96f5a SS |
3208 | lower_32_bits(urb->transfer_dma), |
3209 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 3210 | length_field, |
af8b9e63 | 3211 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3212 | } |
3213 | ||
3214 | /* Save the DMA address of the last TRB in the TD */ | |
3215 | td->last_trb = ep_ring->enqueue; | |
3216 | ||
3217 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3218 | /* If the device sent data, the status stage is an OUT transfer */ | |
3219 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3220 | field = 0; | |
3221 | else | |
3222 | field = TRB_DIR_IN; | |
3b72fca0 | 3223 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3224 | 0, |
3225 | 0, | |
3226 | TRB_INTR_TARGET(0), | |
3227 | /* Event on completion */ | |
3228 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3229 | ||
e9df17eb | 3230 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3231 | start_cycle, start_trb); |
d0e96f5a SS |
3232 | return 0; |
3233 | } | |
3234 | ||
04e51901 AX |
3235 | static int count_isoc_trbs_needed(struct xhci_hcd *xhci, |
3236 | struct urb *urb, int i) | |
3237 | { | |
3238 | int num_trbs = 0; | |
48df4a6f | 3239 | u64 addr, td_len; |
04e51901 AX |
3240 | |
3241 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
3242 | td_len = urb->iso_frame_desc[i].length; | |
3243 | ||
48df4a6f SS |
3244 | num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)), |
3245 | TRB_MAX_BUFF_SIZE); | |
3246 | if (num_trbs == 0) | |
04e51901 | 3247 | num_trbs++; |
04e51901 AX |
3248 | |
3249 | return num_trbs; | |
3250 | } | |
3251 | ||
5cd43e33 SS |
3252 | /* |
3253 | * The transfer burst count field of the isochronous TRB defines the number of | |
3254 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3255 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3256 | * This field is zero based, meaning a value of zero in the field means one | |
3257 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3258 | * zero. Only xHCI 1.0 host controllers support this field. | |
3259 | */ | |
3260 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
3261 | struct usb_device *udev, | |
3262 | struct urb *urb, unsigned int total_packet_count) | |
3263 | { | |
3264 | unsigned int max_burst; | |
3265 | ||
3266 | if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER) | |
3267 | return 0; | |
3268 | ||
3269 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3270 | return roundup(total_packet_count, max_burst + 1) - 1; | |
3271 | } | |
3272 | ||
b61d378f SS |
3273 | /* |
3274 | * Returns the number of packets in the last "burst" of packets. This field is | |
3275 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3276 | * the last burst packet count is equal to the total number of packets in the | |
3277 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3278 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3279 | * contain 1 to (bMaxBurst + 1) packets. | |
3280 | */ | |
3281 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
3282 | struct usb_device *udev, | |
3283 | struct urb *urb, unsigned int total_packet_count) | |
3284 | { | |
3285 | unsigned int max_burst; | |
3286 | unsigned int residue; | |
3287 | ||
3288 | if (xhci->hci_version < 0x100) | |
3289 | return 0; | |
3290 | ||
3291 | switch (udev->speed) { | |
3292 | case USB_SPEED_SUPER: | |
3293 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ | |
3294 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3295 | residue = total_packet_count % (max_burst + 1); | |
3296 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3297 | * number of packets, but the TLBPC field is zero-based. | |
3298 | */ | |
3299 | if (residue == 0) | |
3300 | return max_burst; | |
3301 | return residue - 1; | |
3302 | default: | |
3303 | if (total_packet_count == 0) | |
3304 | return 0; | |
3305 | return total_packet_count - 1; | |
3306 | } | |
3307 | } | |
3308 | ||
04e51901 AX |
3309 | /* This is for isoc transfer */ |
3310 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3311 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3312 | { | |
3313 | struct xhci_ring *ep_ring; | |
3314 | struct urb_priv *urb_priv; | |
3315 | struct xhci_td *td; | |
3316 | int num_tds, trbs_per_td; | |
3317 | struct xhci_generic_trb *start_trb; | |
3318 | bool first_trb; | |
3319 | int start_cycle; | |
3320 | u32 field, length_field; | |
3321 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
3322 | u64 start_addr, addr; | |
3323 | int i, j; | |
47cbf692 | 3324 | bool more_trbs_coming; |
04e51901 AX |
3325 | |
3326 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; | |
3327 | ||
3328 | num_tds = urb->number_of_packets; | |
3329 | if (num_tds < 1) { | |
3330 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
3331 | return -EINVAL; | |
3332 | } | |
3333 | ||
04e51901 AX |
3334 | start_addr = (u64) urb->transfer_dma; |
3335 | start_trb = &ep_ring->enqueue->generic; | |
3336 | start_cycle = ep_ring->cycle_state; | |
3337 | ||
522989a2 | 3338 | urb_priv = urb->hcpriv; |
04e51901 AX |
3339 | /* Queue the first TRB, even if it's zero-length */ |
3340 | for (i = 0; i < num_tds; i++) { | |
4da6e6f2 | 3341 | unsigned int total_packet_count; |
5cd43e33 | 3342 | unsigned int burst_count; |
b61d378f | 3343 | unsigned int residue; |
04e51901 | 3344 | |
4da6e6f2 | 3345 | first_trb = true; |
04e51901 AX |
3346 | running_total = 0; |
3347 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
3348 | td_len = urb->iso_frame_desc[i].length; | |
3349 | td_remain_len = td_len; | |
4da6e6f2 | 3350 | total_packet_count = roundup(td_len, |
29cc8897 | 3351 | usb_endpoint_maxp(&urb->ep->desc)); |
48df4a6f SS |
3352 | /* A zero-length transfer still involves at least one packet. */ |
3353 | if (total_packet_count == 0) | |
3354 | total_packet_count++; | |
5cd43e33 SS |
3355 | burst_count = xhci_get_burst_count(xhci, urb->dev, urb, |
3356 | total_packet_count); | |
b61d378f SS |
3357 | residue = xhci_get_last_burst_packet_count(xhci, |
3358 | urb->dev, urb, total_packet_count); | |
04e51901 AX |
3359 | |
3360 | trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); | |
3361 | ||
3362 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 3363 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
3364 | if (ret < 0) { |
3365 | if (i == 0) | |
3366 | return ret; | |
3367 | goto cleanup; | |
3368 | } | |
04e51901 | 3369 | |
04e51901 | 3370 | td = urb_priv->td[i]; |
04e51901 AX |
3371 | for (j = 0; j < trbs_per_td; j++) { |
3372 | u32 remainder = 0; | |
b61d378f | 3373 | field = TRB_TBC(burst_count) | TRB_TLBPC(residue); |
04e51901 AX |
3374 | |
3375 | if (first_trb) { | |
3376 | /* Queue the isoc TRB */ | |
3377 | field |= TRB_TYPE(TRB_ISOC); | |
3378 | /* Assume URB_ISO_ASAP is set */ | |
3379 | field |= TRB_SIA; | |
50f7b52a AX |
3380 | if (i == 0) { |
3381 | if (start_cycle == 0) | |
3382 | field |= 0x1; | |
3383 | } else | |
04e51901 AX |
3384 | field |= ep_ring->cycle_state; |
3385 | first_trb = false; | |
3386 | } else { | |
3387 | /* Queue other normal TRBs */ | |
3388 | field |= TRB_TYPE(TRB_NORMAL); | |
3389 | field |= ep_ring->cycle_state; | |
3390 | } | |
3391 | ||
af8b9e63 SS |
3392 | /* Only set interrupt on short packet for IN EPs */ |
3393 | if (usb_urb_dir_in(urb)) | |
3394 | field |= TRB_ISP; | |
3395 | ||
04e51901 AX |
3396 | /* Chain all the TRBs together; clear the chain bit in |
3397 | * the last TRB to indicate it's the last TRB in the | |
3398 | * chain. | |
3399 | */ | |
3400 | if (j < trbs_per_td - 1) { | |
3401 | field |= TRB_CHAIN; | |
47cbf692 | 3402 | more_trbs_coming = true; |
04e51901 AX |
3403 | } else { |
3404 | td->last_trb = ep_ring->enqueue; | |
3405 | field |= TRB_IOC; | |
ad106f29 AX |
3406 | if (xhci->hci_version == 0x100) { |
3407 | /* Set BEI bit except for the last td */ | |
3408 | if (i < num_tds - 1) | |
3409 | field |= TRB_BEI; | |
3410 | } | |
47cbf692 | 3411 | more_trbs_coming = false; |
04e51901 AX |
3412 | } |
3413 | ||
3414 | /* Calculate TRB length */ | |
3415 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
3416 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
3417 | if (trb_buff_len > td_remain_len) | |
3418 | trb_buff_len = td_remain_len; | |
3419 | ||
4da6e6f2 SS |
3420 | /* Set the TRB length, TD size, & interrupter fields. */ |
3421 | if (xhci->hci_version < 0x100) { | |
3422 | remainder = xhci_td_remainder( | |
3423 | td_len - running_total); | |
3424 | } else { | |
3425 | remainder = xhci_v1_0_td_remainder( | |
3426 | running_total, trb_buff_len, | |
3427 | total_packet_count, urb); | |
3428 | } | |
04e51901 AX |
3429 | length_field = TRB_LEN(trb_buff_len) | |
3430 | remainder | | |
3431 | TRB_INTR_TARGET(0); | |
4da6e6f2 | 3432 | |
3b72fca0 | 3433 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
3434 | lower_32_bits(addr), |
3435 | upper_32_bits(addr), | |
3436 | length_field, | |
af8b9e63 | 3437 | field); |
04e51901 AX |
3438 | running_total += trb_buff_len; |
3439 | ||
3440 | addr += trb_buff_len; | |
3441 | td_remain_len -= trb_buff_len; | |
3442 | } | |
3443 | ||
3444 | /* Check TD length */ | |
3445 | if (running_total != td_len) { | |
3446 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
3447 | ret = -EINVAL; |
3448 | goto cleanup; | |
04e51901 AX |
3449 | } |
3450 | } | |
3451 | ||
c41136b0 AX |
3452 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
3453 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
3454 | usb_amd_quirk_pll_disable(); | |
3455 | } | |
3456 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
3457 | ||
e1eab2e0 AX |
3458 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3459 | start_cycle, start_trb); | |
04e51901 | 3460 | return 0; |
522989a2 SS |
3461 | cleanup: |
3462 | /* Clean up a partially enqueued isoc transfer. */ | |
3463 | ||
3464 | for (i--; i >= 0; i--) | |
585df1d9 | 3465 | list_del_init(&urb_priv->td[i]->td_list); |
522989a2 SS |
3466 | |
3467 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
3468 | * into No-ops with a software-owned cycle bit. That way the hardware | |
3469 | * won't accidentally start executing bogus TDs when we partially | |
3470 | * overwrite them. td->first_trb and td->start_seg are already set. | |
3471 | */ | |
3472 | urb_priv->td[0]->last_trb = ep_ring->enqueue; | |
3473 | /* Every TRB except the first & last will have its cycle bit flipped. */ | |
3474 | td_to_noop(xhci, ep_ring, urb_priv->td[0], true); | |
3475 | ||
3476 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
3477 | ep_ring->enqueue = urb_priv->td[0]->first_trb; | |
3478 | ep_ring->enq_seg = urb_priv->td[0]->start_seg; | |
3479 | ep_ring->cycle_state = start_cycle; | |
b008df60 | 3480 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
3481 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
3482 | return ret; | |
04e51901 AX |
3483 | } |
3484 | ||
3485 | /* | |
3486 | * Check transfer ring to guarantee there is enough room for the urb. | |
3487 | * Update ISO URB start_frame and interval. | |
3488 | * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to | |
3489 | * update the urb->start_frame by now. | |
3490 | * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input. | |
3491 | */ | |
3492 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3493 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3494 | { | |
3495 | struct xhci_virt_device *xdev; | |
3496 | struct xhci_ring *ep_ring; | |
3497 | struct xhci_ep_ctx *ep_ctx; | |
3498 | int start_frame; | |
3499 | int xhci_interval; | |
3500 | int ep_interval; | |
3501 | int num_tds, num_trbs, i; | |
3502 | int ret; | |
3503 | ||
3504 | xdev = xhci->devs[slot_id]; | |
3505 | ep_ring = xdev->eps[ep_index].ring; | |
3506 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3507 | ||
3508 | num_trbs = 0; | |
3509 | num_tds = urb->number_of_packets; | |
3510 | for (i = 0; i < num_tds; i++) | |
3511 | num_trbs += count_isoc_trbs_needed(xhci, urb, i); | |
3512 | ||
3513 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3514 | * Do not insert any td of the urb to the ring if the check failed. | |
3515 | */ | |
28ccd296 | 3516 | ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3b72fca0 | 3517 | num_trbs, mem_flags); |
04e51901 AX |
3518 | if (ret) |
3519 | return ret; | |
3520 | ||
3521 | start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index); | |
3522 | start_frame &= 0x3fff; | |
3523 | ||
3524 | urb->start_frame = start_frame; | |
3525 | if (urb->dev->speed == USB_SPEED_LOW || | |
3526 | urb->dev->speed == USB_SPEED_FULL) | |
3527 | urb->start_frame >>= 3; | |
3528 | ||
28ccd296 | 3529 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
04e51901 AX |
3530 | ep_interval = urb->interval; |
3531 | /* Convert to microframes */ | |
3532 | if (urb->dev->speed == USB_SPEED_LOW || | |
3533 | urb->dev->speed == USB_SPEED_FULL) | |
3534 | ep_interval *= 8; | |
3535 | /* FIXME change this to a warning and a suggestion to use the new API | |
3536 | * to set the polling interval (once the API is added). | |
3537 | */ | |
3538 | if (xhci_interval != ep_interval) { | |
7961acd7 | 3539 | if (printk_ratelimit()) |
04e51901 AX |
3540 | dev_dbg(&urb->dev->dev, "Driver uses different interval" |
3541 | " (%d microframe%s) than xHCI " | |
3542 | "(%d microframe%s)\n", | |
3543 | ep_interval, | |
3544 | ep_interval == 1 ? "" : "s", | |
3545 | xhci_interval, | |
3546 | xhci_interval == 1 ? "" : "s"); | |
3547 | urb->interval = xhci_interval; | |
3548 | /* Convert back to frames for LS/FS devices */ | |
3549 | if (urb->dev->speed == USB_SPEED_LOW || | |
3550 | urb->dev->speed == USB_SPEED_FULL) | |
3551 | urb->interval /= 8; | |
3552 | } | |
b008df60 AX |
3553 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
3554 | ||
3fc8206d | 3555 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
3556 | } |
3557 | ||
d0e96f5a SS |
3558 | /**** Command Ring Operations ****/ |
3559 | ||
913a8a34 SS |
3560 | /* Generic function for queueing a command TRB on the command ring. |
3561 | * Check to make sure there's room on the command ring for one command TRB. | |
3562 | * Also check that there's room reserved for commands that must not fail. | |
3563 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
3564 | * then only check for the number of reserved spots. | |
3565 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
3566 | * because the command event handler may want to resubmit a failed command. | |
3567 | */ | |
3568 | static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, | |
3569 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 3570 | { |
913a8a34 | 3571 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a SS |
3572 | int ret; |
3573 | ||
913a8a34 SS |
3574 | if (!command_must_succeed) |
3575 | reserved_trbs++; | |
3576 | ||
d1dc908a | 3577 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 3578 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
3579 | if (ret < 0) { |
3580 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
3581 | if (command_must_succeed) |
3582 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
3583 | "unfailable commands failed.\n"); | |
d1dc908a | 3584 | return ret; |
7f84eef0 | 3585 | } |
3b72fca0 AX |
3586 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
3587 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
3588 | return 0; |
3589 | } | |
3590 | ||
3ffbba95 | 3591 | /* Queue a slot enable or disable request on the command ring */ |
23e3be11 | 3592 | int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id) |
3ffbba95 SS |
3593 | { |
3594 | return queue_command(xhci, 0, 0, 0, | |
913a8a34 | 3595 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
3596 | } |
3597 | ||
3598 | /* Queue an address device command TRB */ | |
23e3be11 SS |
3599 | int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
3600 | u32 slot_id) | |
3ffbba95 | 3601 | { |
8e595a5d SS |
3602 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
3603 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 | 3604 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id), |
2a8f82c4 SS |
3605 | false); |
3606 | } | |
3607 | ||
0238634d SS |
3608 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, |
3609 | u32 field1, u32 field2, u32 field3, u32 field4) | |
3610 | { | |
3611 | return queue_command(xhci, field1, field2, field3, field4, false); | |
3612 | } | |
3613 | ||
2a8f82c4 SS |
3614 | /* Queue a reset device command TRB */ |
3615 | int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id) | |
3616 | { | |
3617 | return queue_command(xhci, 0, 0, 0, | |
3618 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), | |
913a8a34 | 3619 | false); |
3ffbba95 | 3620 | } |
f94e0186 SS |
3621 | |
3622 | /* Queue a configure endpoint command TRB */ | |
23e3be11 | 3623 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, |
913a8a34 | 3624 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 3625 | { |
8e595a5d SS |
3626 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), |
3627 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 SS |
3628 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
3629 | command_must_succeed); | |
f94e0186 | 3630 | } |
ae636747 | 3631 | |
f2217e8e SS |
3632 | /* Queue an evaluate context command TRB */ |
3633 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr, | |
4b266541 | 3634 | u32 slot_id, bool command_must_succeed) |
f2217e8e SS |
3635 | { |
3636 | return queue_command(xhci, lower_32_bits(in_ctx_ptr), | |
3637 | upper_32_bits(in_ctx_ptr), 0, | |
913a8a34 | 3638 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 3639 | command_must_succeed); |
f2217e8e SS |
3640 | } |
3641 | ||
be88fe4f AX |
3642 | /* |
3643 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
3644 | * activity on an endpoint that is about to be suspended. | |
3645 | */ | |
23e3be11 | 3646 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 3647 | unsigned int ep_index, int suspend) |
ae636747 SS |
3648 | { |
3649 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3650 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3651 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 3652 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 SS |
3653 | |
3654 | return queue_command(xhci, 0, 0, 0, | |
be88fe4f | 3655 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
3656 | } |
3657 | ||
3658 | /* Set Transfer Ring Dequeue Pointer command. | |
3659 | * This should not be used for endpoints that have streams enabled. | |
3660 | */ | |
3661 | static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id, | |
e9df17eb SS |
3662 | unsigned int ep_index, unsigned int stream_id, |
3663 | struct xhci_segment *deq_seg, | |
ae636747 SS |
3664 | union xhci_trb *deq_ptr, u32 cycle_state) |
3665 | { | |
3666 | dma_addr_t addr; | |
3667 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3668 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
e9df17eb | 3669 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
ae636747 | 3670 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
bf161e85 | 3671 | struct xhci_virt_ep *ep; |
ae636747 | 3672 | |
23e3be11 | 3673 | addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); |
c92bcfa7 | 3674 | if (addr == 0) { |
ae636747 | 3675 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 GKH |
3676 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
3677 | deq_seg, deq_ptr); | |
c92bcfa7 SS |
3678 | return 0; |
3679 | } | |
bf161e85 SS |
3680 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
3681 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
3682 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | |
3683 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | |
3684 | return 0; | |
3685 | } | |
3686 | ep->queued_deq_seg = deq_seg; | |
3687 | ep->queued_deq_ptr = deq_ptr; | |
8e595a5d | 3688 | return queue_command(xhci, lower_32_bits(addr) | cycle_state, |
e9df17eb | 3689 | upper_32_bits(addr), trb_stream_id, |
913a8a34 | 3690 | trb_slot_id | trb_ep_index | type, false); |
ae636747 | 3691 | } |
a1587d97 SS |
3692 | |
3693 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id, | |
3694 | unsigned int ep_index) | |
3695 | { | |
3696 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3697 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3698 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
3699 | ||
913a8a34 SS |
3700 | return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type, |
3701 | false); | |
a1587d97 | 3702 | } |