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Commit | Line | Data |
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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
7f84eef0 | 69 | #include "xhci.h" |
3a7fa5be | 70 | #include "xhci-trace.h" |
7f84eef0 | 71 | |
be88fe4f AX |
72 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, |
73 | struct xhci_virt_device *virt_dev, | |
74 | struct xhci_event_cmd *event); | |
75 | ||
7f84eef0 SS |
76 | /* |
77 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
78 | * address of the TRB. | |
79 | */ | |
23e3be11 | 80 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
81 | union xhci_trb *trb) |
82 | { | |
6071d836 | 83 | unsigned long segment_offset; |
7f84eef0 | 84 | |
6071d836 | 85 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 86 | return 0; |
6071d836 SS |
87 | /* offset in TRBs */ |
88 | segment_offset = trb - seg->trbs; | |
89 | if (segment_offset > TRBS_PER_SEGMENT) | |
7f84eef0 | 90 | return 0; |
6071d836 | 91 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
92 | } |
93 | ||
94 | /* Does this link TRB point to the first segment in a ring, | |
95 | * or was the previous TRB the last TRB on the last segment in the ERST? | |
96 | */ | |
575688e1 | 97 | static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
98 | struct xhci_segment *seg, union xhci_trb *trb) |
99 | { | |
100 | if (ring == xhci->event_ring) | |
101 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && | |
102 | (seg->next == xhci->event_ring->first_seg); | |
103 | else | |
28ccd296 | 104 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; |
7f84eef0 SS |
105 | } |
106 | ||
107 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring | |
108 | * segment? I.e. would the updated event TRB pointer step off the end of the | |
109 | * event seg? | |
110 | */ | |
575688e1 | 111 | static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
112 | struct xhci_segment *seg, union xhci_trb *trb) |
113 | { | |
114 | if (ring == xhci->event_ring) | |
115 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; | |
116 | else | |
f5960b69 | 117 | return TRB_TYPE_LINK_LE32(trb->link.control); |
7f84eef0 SS |
118 | } |
119 | ||
575688e1 | 120 | static int enqueue_is_link_trb(struct xhci_ring *ring) |
6c12db90 JY |
121 | { |
122 | struct xhci_link_trb *link = &ring->enqueue->link; | |
f5960b69 | 123 | return TRB_TYPE_LINK_LE32(link->control); |
6c12db90 JY |
124 | } |
125 | ||
ae636747 SS |
126 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
127 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
128 | * effect the ring dequeue or enqueue pointers. | |
129 | */ | |
130 | static void next_trb(struct xhci_hcd *xhci, | |
131 | struct xhci_ring *ring, | |
132 | struct xhci_segment **seg, | |
133 | union xhci_trb **trb) | |
134 | { | |
135 | if (last_trb(xhci, ring, *seg, *trb)) { | |
136 | *seg = (*seg)->next; | |
137 | *trb = ((*seg)->trbs); | |
138 | } else { | |
a1669b2c | 139 | (*trb)++; |
ae636747 SS |
140 | } |
141 | } | |
142 | ||
7f84eef0 SS |
143 | /* |
144 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
145 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
146 | */ | |
3b72fca0 | 147 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 148 | { |
7f84eef0 | 149 | ring->deq_updates++; |
b008df60 | 150 | |
50d0206f SS |
151 | /* |
152 | * If this is not event ring, and the dequeue pointer | |
153 | * is not on a link TRB, there is one more usable TRB | |
154 | */ | |
b008df60 AX |
155 | if (ring->type != TYPE_EVENT && |
156 | !last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) | |
157 | ring->num_trbs_free++; | |
b008df60 | 158 | |
50d0206f SS |
159 | do { |
160 | /* | |
161 | * Update the dequeue pointer further if that was a link TRB or | |
162 | * we're at the end of an event ring segment (which doesn't have | |
163 | * link TRBS) | |
164 | */ | |
165 | if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) { | |
166 | if (ring->type == TYPE_EVENT && | |
167 | last_trb_on_last_seg(xhci, ring, | |
168 | ring->deq_seg, ring->dequeue)) { | |
4e341818 | 169 | ring->cycle_state ^= 1; |
50d0206f SS |
170 | } |
171 | ring->deq_seg = ring->deq_seg->next; | |
172 | ring->dequeue = ring->deq_seg->trbs; | |
173 | } else { | |
174 | ring->dequeue++; | |
7f84eef0 | 175 | } |
50d0206f | 176 | } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)); |
7f84eef0 SS |
177 | } |
178 | ||
179 | /* | |
180 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
181 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
182 | * | |
183 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
184 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
185 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
186 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
187 | * | |
188 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
189 | * set, but other sections talk about dealing with the chain bit set. This was |
190 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
191 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
192 | * |
193 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
194 | * prepare_transfer()? | |
7f84eef0 | 195 | */ |
6cc30d85 | 196 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 197 | bool more_trbs_coming) |
7f84eef0 SS |
198 | { |
199 | u32 chain; | |
200 | union xhci_trb *next; | |
201 | ||
28ccd296 | 202 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 AX |
203 | /* If this is not event ring, there is one less usable TRB */ |
204 | if (ring->type != TYPE_EVENT && | |
205 | !last_trb(xhci, ring, ring->enq_seg, ring->enqueue)) | |
206 | ring->num_trbs_free--; | |
7f84eef0 SS |
207 | next = ++(ring->enqueue); |
208 | ||
209 | ring->enq_updates++; | |
210 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
211 | * the end of an event ring segment (which doesn't have link TRBS) | |
212 | */ | |
213 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
3b72fca0 AX |
214 | if (ring->type != TYPE_EVENT) { |
215 | /* | |
216 | * If the caller doesn't plan on enqueueing more | |
217 | * TDs before ringing the doorbell, then we | |
218 | * don't want to give the link TRB to the | |
219 | * hardware just yet. We'll give the link TRB | |
220 | * back in prepare_ring() just before we enqueue | |
221 | * the TD at the top of the ring. | |
222 | */ | |
223 | if (!chain && !more_trbs_coming) | |
224 | break; | |
6cc30d85 | 225 | |
3b72fca0 AX |
226 | /* If we're not dealing with 0.95 hardware or |
227 | * isoc rings on AMD 0.96 host, | |
228 | * carry over the chain bit of the previous TRB | |
229 | * (which may mean the chain bit is cleared). | |
230 | */ | |
231 | if (!(ring->type == TYPE_ISOC && | |
232 | (xhci->quirks & XHCI_AMD_0x96_HOST)) | |
7e393a83 | 233 | && !xhci_link_trb_quirk(xhci)) { |
3b72fca0 AX |
234 | next->link.control &= |
235 | cpu_to_le32(~TRB_CHAIN); | |
236 | next->link.control |= | |
237 | cpu_to_le32(chain); | |
7f84eef0 | 238 | } |
3b72fca0 AX |
239 | /* Give this link TRB to the hardware */ |
240 | wmb(); | |
241 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
242 | ||
7f84eef0 SS |
243 | /* Toggle the cycle bit after the last ring segment. */ |
244 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
245 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
7f84eef0 SS |
246 | } |
247 | } | |
248 | ring->enq_seg = ring->enq_seg->next; | |
249 | ring->enqueue = ring->enq_seg->trbs; | |
250 | next = ring->enqueue; | |
251 | } | |
252 | } | |
253 | ||
254 | /* | |
085deb16 AX |
255 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
256 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 257 | */ |
b008df60 | 258 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
259 | unsigned int num_trbs) |
260 | { | |
085deb16 | 261 | int num_trbs_in_deq_seg; |
b008df60 | 262 | |
085deb16 AX |
263 | if (ring->num_trbs_free < num_trbs) |
264 | return 0; | |
265 | ||
266 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
267 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
268 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
269 | return 0; | |
270 | } | |
271 | ||
272 | return 1; | |
7f84eef0 SS |
273 | } |
274 | ||
7f84eef0 | 275 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 276 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 277 | { |
c181bc5b EF |
278 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
279 | return; | |
280 | ||
7f84eef0 | 281 | xhci_dbg(xhci, "// Ding dong!\n"); |
204b7793 | 282 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 | 283 | /* Flush PCI posted writes */ |
b0ba9720 | 284 | readl(&xhci->dba->doorbell[0]); |
7f84eef0 SS |
285 | } |
286 | ||
b92cc66c EF |
287 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci) |
288 | { | |
289 | u64 temp_64; | |
290 | int ret; | |
291 | ||
292 | xhci_dbg(xhci, "Abort command ring\n"); | |
293 | ||
294 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) { | |
295 | xhci_dbg(xhci, "The command ring isn't running, " | |
296 | "Have the command ring been stopped?\n"); | |
297 | return 0; | |
298 | } | |
299 | ||
f7b2e403 | 300 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
b92cc66c EF |
301 | if (!(temp_64 & CMD_RING_RUNNING)) { |
302 | xhci_dbg(xhci, "Command ring had been stopped\n"); | |
303 | return 0; | |
304 | } | |
305 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; | |
477632df SS |
306 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, |
307 | &xhci->op_regs->cmd_ring); | |
b92cc66c EF |
308 | |
309 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should | |
310 | * time the completion od all xHCI commands, including | |
311 | * the Command Abort operation. If software doesn't see | |
312 | * CRR negated in a timely manner (e.g. longer than 5 | |
313 | * seconds), then it should assume that the there are | |
314 | * larger problems with the xHC and assert HCRST. | |
315 | */ | |
2611bd18 | 316 | ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring, |
b92cc66c EF |
317 | CMD_RING_RUNNING, 0, 5 * 1000 * 1000); |
318 | if (ret < 0) { | |
319 | xhci_err(xhci, "Stopped the command ring failed, " | |
320 | "maybe the host is dead\n"); | |
321 | xhci->xhc_state |= XHCI_STATE_DYING; | |
322 | xhci_quiesce(xhci); | |
323 | xhci_halt(xhci); | |
324 | return -ESHUTDOWN; | |
325 | } | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
330 | static int xhci_queue_cd(struct xhci_hcd *xhci, | |
331 | struct xhci_command *command, | |
332 | union xhci_trb *cmd_trb) | |
333 | { | |
334 | struct xhci_cd *cd; | |
335 | cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC); | |
336 | if (!cd) | |
337 | return -ENOMEM; | |
338 | INIT_LIST_HEAD(&cd->cancel_cmd_list); | |
339 | ||
340 | cd->command = command; | |
341 | cd->cmd_trb = cmd_trb; | |
342 | list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list); | |
343 | ||
344 | return 0; | |
345 | } | |
346 | ||
347 | /* | |
348 | * Cancel the command which has issue. | |
349 | * | |
350 | * Some commands may hang due to waiting for acknowledgement from | |
351 | * usb device. It is outside of the xHC's ability to control and | |
352 | * will cause the command ring is blocked. When it occurs software | |
353 | * should intervene to recover the command ring. | |
354 | * See Section 4.6.1.1 and 4.6.1.2 | |
355 | */ | |
356 | int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command, | |
357 | union xhci_trb *cmd_trb) | |
358 | { | |
359 | int retval = 0; | |
360 | unsigned long flags; | |
361 | ||
362 | spin_lock_irqsave(&xhci->lock, flags); | |
363 | ||
364 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
365 | xhci_warn(xhci, "Abort the command ring," | |
366 | " but the xHCI is dead.\n"); | |
367 | retval = -ESHUTDOWN; | |
368 | goto fail; | |
369 | } | |
370 | ||
371 | /* queue the cmd desriptor to cancel_cmd_list */ | |
372 | retval = xhci_queue_cd(xhci, command, cmd_trb); | |
373 | if (retval) { | |
374 | xhci_warn(xhci, "Queuing command descriptor failed.\n"); | |
375 | goto fail; | |
376 | } | |
377 | ||
378 | /* abort command ring */ | |
379 | retval = xhci_abort_cmd_ring(xhci); | |
380 | if (retval) { | |
381 | xhci_err(xhci, "Abort command ring failed\n"); | |
382 | if (unlikely(retval == -ESHUTDOWN)) { | |
383 | spin_unlock_irqrestore(&xhci->lock, flags); | |
384 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); | |
385 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); | |
386 | return retval; | |
387 | } | |
388 | } | |
389 | ||
390 | fail: | |
391 | spin_unlock_irqrestore(&xhci->lock, flags); | |
392 | return retval; | |
393 | } | |
394 | ||
be88fe4f | 395 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 396 | unsigned int slot_id, |
e9df17eb SS |
397 | unsigned int ep_index, |
398 | unsigned int stream_id) | |
ae636747 | 399 | { |
28ccd296 | 400 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
401 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
402 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 403 | |
ae636747 | 404 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 405 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
406 | * We don't want to restart any stream rings if there's a set dequeue |
407 | * pointer command pending because the device can choose to start any | |
408 | * stream once the endpoint is on the HW schedule. | |
409 | * FIXME - check all the stream rings for pending cancellations. | |
ae636747 | 410 | */ |
50d64676 MW |
411 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
412 | (ep_state & EP_HALTED)) | |
413 | return; | |
204b7793 | 414 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
50d64676 MW |
415 | /* The CPU has better things to do at this point than wait for a |
416 | * write-posting flush. It'll get there soon enough. | |
417 | */ | |
ae636747 SS |
418 | } |
419 | ||
e9df17eb SS |
420 | /* Ring the doorbell for any rings with pending URBs */ |
421 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
422 | unsigned int slot_id, | |
423 | unsigned int ep_index) | |
424 | { | |
425 | unsigned int stream_id; | |
426 | struct xhci_virt_ep *ep; | |
427 | ||
428 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
429 | ||
430 | /* A ring has pending URBs if its TD list is not empty */ | |
431 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
d66eaf9f | 432 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
be88fe4f | 433 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
434 | return; |
435 | } | |
436 | ||
437 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
438 | stream_id++) { | |
439 | struct xhci_stream_info *stream_info = ep->stream_info; | |
440 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
441 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
442 | stream_id); | |
e9df17eb SS |
443 | } |
444 | } | |
445 | ||
ae636747 SS |
446 | /* |
447 | * Find the segment that trb is in. Start searching in start_seg. | |
448 | * If we must move past a segment that has a link TRB with a toggle cycle state | |
449 | * bit set, then we will toggle the value pointed at by cycle_state. | |
450 | */ | |
451 | static struct xhci_segment *find_trb_seg( | |
452 | struct xhci_segment *start_seg, | |
453 | union xhci_trb *trb, int *cycle_state) | |
454 | { | |
455 | struct xhci_segment *cur_seg = start_seg; | |
456 | struct xhci_generic_trb *generic_trb; | |
457 | ||
458 | while (cur_seg->trbs > trb || | |
459 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) { | |
460 | generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic; | |
f5960b69 | 461 | if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE)) |
ba0a4d9a | 462 | *cycle_state ^= 0x1; |
ae636747 SS |
463 | cur_seg = cur_seg->next; |
464 | if (cur_seg == start_seg) | |
465 | /* Looped over the entire list. Oops! */ | |
326b4810 | 466 | return NULL; |
ae636747 SS |
467 | } |
468 | return cur_seg; | |
469 | } | |
470 | ||
021bff91 SS |
471 | |
472 | static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
473 | unsigned int slot_id, unsigned int ep_index, | |
474 | unsigned int stream_id) | |
475 | { | |
476 | struct xhci_virt_ep *ep; | |
477 | ||
478 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
479 | /* Common case: no streams */ | |
480 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
481 | return ep->ring; | |
482 | ||
483 | if (stream_id == 0) { | |
484 | xhci_warn(xhci, | |
485 | "WARN: Slot ID %u, ep index %u has streams, " | |
486 | "but URB has no stream ID.\n", | |
487 | slot_id, ep_index); | |
488 | return NULL; | |
489 | } | |
490 | ||
491 | if (stream_id < ep->stream_info->num_streams) | |
492 | return ep->stream_info->stream_rings[stream_id]; | |
493 | ||
494 | xhci_warn(xhci, | |
495 | "WARN: Slot ID %u, ep index %u has " | |
496 | "stream IDs 1 to %u allocated, " | |
497 | "but stream ID %u is requested.\n", | |
498 | slot_id, ep_index, | |
499 | ep->stream_info->num_streams - 1, | |
500 | stream_id); | |
501 | return NULL; | |
502 | } | |
503 | ||
504 | /* Get the right ring for the given URB. | |
505 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
506 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
507 | */ | |
508 | static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, | |
509 | struct urb *urb) | |
510 | { | |
511 | return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, | |
512 | xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id); | |
513 | } | |
514 | ||
ae636747 SS |
515 | /* |
516 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
517 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
518 | * dequeue pointer, and new consumer cycle state in state. | |
519 | * Update our internal representation of the ring's dequeue pointer. | |
520 | * | |
521 | * We do this in three jumps: | |
522 | * - First we update our new ring state to be the same as when the xHC stopped. | |
523 | * - Then we traverse the ring to find the segment that contains | |
524 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
525 | * any link TRBs with the toggle cycle bit set. | |
526 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
527 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
28ccd296 ME |
528 | * |
529 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | |
530 | * with correct __le32 accesses they should work fine. Only users of this are | |
531 | * in here. | |
ae636747 | 532 | */ |
c92bcfa7 | 533 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 534 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
535 | unsigned int stream_id, struct xhci_td *cur_td, |
536 | struct xhci_dequeue_state *state) | |
ae636747 SS |
537 | { |
538 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
c4bedb77 | 539 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; |
e9df17eb | 540 | struct xhci_ring *ep_ring; |
ae636747 | 541 | struct xhci_generic_trb *trb; |
c92bcfa7 | 542 | dma_addr_t addr; |
1f81b6d2 | 543 | u64 hw_dequeue; |
ae636747 | 544 | |
e9df17eb SS |
545 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
546 | ep_index, stream_id); | |
547 | if (!ep_ring) { | |
548 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
549 | "for invalid stream ID %u.\n", | |
550 | stream_id); | |
551 | return; | |
552 | } | |
68e41c5d | 553 | |
ae636747 | 554 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
aa50b290 XR |
555 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
556 | "Finding endpoint context"); | |
c4bedb77 HG |
557 | /* 4.6.9 the css flag is written to the stream context for streams */ |
558 | if (ep->ep_state & EP_HAS_STREAMS) { | |
559 | struct xhci_stream_ctx *ctx = | |
560 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1f81b6d2 | 561 | hw_dequeue = le64_to_cpu(ctx->stream_ring); |
c4bedb77 HG |
562 | } else { |
563 | struct xhci_ep_ctx *ep_ctx | |
564 | = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); | |
1f81b6d2 | 565 | hw_dequeue = le64_to_cpu(ep_ctx->deq); |
c4bedb77 | 566 | } |
ae636747 | 567 | |
1f81b6d2 JW |
568 | /* Find virtual address and segment of hardware dequeue pointer */ |
569 | state->new_deq_seg = ep_ring->deq_seg; | |
570 | state->new_deq_ptr = ep_ring->dequeue; | |
571 | while (xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr) | |
572 | != (dma_addr_t)(hw_dequeue & ~0xf)) { | |
573 | next_trb(xhci, ep_ring, &state->new_deq_seg, | |
574 | &state->new_deq_ptr); | |
575 | if (state->new_deq_ptr == ep_ring->dequeue) { | |
576 | WARN_ON(1); | |
577 | return; | |
578 | } | |
579 | } | |
580 | /* | |
581 | * Find cycle state for last_trb, starting at old cycle state of | |
582 | * hw_dequeue. If there is only one segment ring, find_trb_seg() will | |
583 | * return immediately and cannot toggle the cycle state if this search | |
584 | * wraps around, so add one more toggle manually in that case. | |
585 | */ | |
586 | state->new_cycle_state = hw_dequeue & 0x1; | |
587 | if (ep_ring->first_seg == ep_ring->first_seg->next && | |
588 | cur_td->last_trb < state->new_deq_ptr) | |
589 | state->new_cycle_state ^= 0x1; | |
590 | ||
ae636747 | 591 | state->new_deq_ptr = cur_td->last_trb; |
aa50b290 XR |
592 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
593 | "Finding segment containing last TRB in TD."); | |
ae636747 | 594 | state->new_deq_seg = find_trb_seg(state->new_deq_seg, |
1f81b6d2 | 595 | state->new_deq_ptr, &state->new_cycle_state); |
68e41c5d PZ |
596 | if (!state->new_deq_seg) { |
597 | WARN_ON(1); | |
598 | return; | |
599 | } | |
ae636747 | 600 | |
1f81b6d2 | 601 | /* Increment to find next TRB after last_trb. Cycle if appropriate. */ |
ae636747 | 602 | trb = &state->new_deq_ptr->generic; |
f5960b69 ME |
603 | if (TRB_TYPE_LINK_LE32(trb->field[3]) && |
604 | (trb->field[3] & cpu_to_le32(LINK_TOGGLE))) | |
ba0a4d9a | 605 | state->new_cycle_state ^= 0x1; |
ae636747 SS |
606 | next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr); |
607 | ||
1f81b6d2 | 608 | /* Don't update the ring cycle state for the producer (us). */ |
aa50b290 XR |
609 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
610 | "Cycle state = 0x%x", state->new_cycle_state); | |
01a1fdb9 | 611 | |
aa50b290 XR |
612 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
613 | "New dequeue segment = %p (virtual)", | |
c92bcfa7 SS |
614 | state->new_deq_seg); |
615 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
aa50b290 XR |
616 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
617 | "New dequeue pointer = 0x%llx (DMA)", | |
c92bcfa7 | 618 | (unsigned long long) addr); |
ae636747 SS |
619 | } |
620 | ||
522989a2 SS |
621 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
622 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
623 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
624 | */ | |
23e3be11 | 625 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
522989a2 | 626 | struct xhci_td *cur_td, bool flip_cycle) |
ae636747 SS |
627 | { |
628 | struct xhci_segment *cur_seg; | |
629 | union xhci_trb *cur_trb; | |
630 | ||
631 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; | |
632 | true; | |
633 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 | 634 | if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) { |
ae636747 SS |
635 | /* Unchain any chained Link TRBs, but |
636 | * leave the pointers intact. | |
637 | */ | |
28ccd296 | 638 | cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN); |
522989a2 SS |
639 | /* Flip the cycle bit (link TRBs can't be the first |
640 | * or last TRB). | |
641 | */ | |
642 | if (flip_cycle) | |
643 | cur_trb->generic.field[3] ^= | |
644 | cpu_to_le32(TRB_CYCLE); | |
aa50b290 XR |
645 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
646 | "Cancel (unchain) link TRB"); | |
647 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
648 | "Address = %p (0x%llx dma); " | |
649 | "in seg %p (0x%llx dma)", | |
700e2052 | 650 | cur_trb, |
23e3be11 | 651 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
652 | cur_seg, |
653 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
654 | } else { |
655 | cur_trb->generic.field[0] = 0; | |
656 | cur_trb->generic.field[1] = 0; | |
657 | cur_trb->generic.field[2] = 0; | |
658 | /* Preserve only the cycle bit of this TRB */ | |
28ccd296 | 659 | cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); |
522989a2 SS |
660 | /* Flip the cycle bit except on the first or last TRB */ |
661 | if (flip_cycle && cur_trb != cur_td->first_trb && | |
662 | cur_trb != cur_td->last_trb) | |
663 | cur_trb->generic.field[3] ^= | |
664 | cpu_to_le32(TRB_CYCLE); | |
28ccd296 ME |
665 | cur_trb->generic.field[3] |= cpu_to_le32( |
666 | TRB_TYPE(TRB_TR_NOOP)); | |
aa50b290 XR |
667 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
668 | "TRB to noop at offset 0x%llx", | |
79688acf SS |
669 | (unsigned long long) |
670 | xhci_trb_virt_to_dma(cur_seg, cur_trb)); | |
ae636747 SS |
671 | } |
672 | if (cur_trb == cur_td->last_trb) | |
673 | break; | |
674 | } | |
675 | } | |
676 | ||
ddba5cd0 MN |
677 | static int queue_set_tr_deq(struct xhci_hcd *xhci, |
678 | struct xhci_command *cmd, int slot_id, | |
e9df17eb SS |
679 | unsigned int ep_index, unsigned int stream_id, |
680 | struct xhci_segment *deq_seg, | |
ae636747 SS |
681 | union xhci_trb *deq_ptr, u32 cycle_state); |
682 | ||
c92bcfa7 | 683 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
ddba5cd0 | 684 | struct xhci_command *cmd, |
63a0d9ab | 685 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb | 686 | unsigned int stream_id, |
63a0d9ab | 687 | struct xhci_dequeue_state *deq_state) |
c92bcfa7 | 688 | { |
63a0d9ab SS |
689 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
690 | ||
aa50b290 XR |
691 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
692 | "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), " | |
693 | "new deq ptr = %p (0x%llx dma), new cycle = %u", | |
c92bcfa7 SS |
694 | deq_state->new_deq_seg, |
695 | (unsigned long long)deq_state->new_deq_seg->dma, | |
696 | deq_state->new_deq_ptr, | |
697 | (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
698 | deq_state->new_cycle_state); | |
ddba5cd0 | 699 | queue_set_tr_deq(xhci, cmd, slot_id, ep_index, stream_id, |
c92bcfa7 SS |
700 | deq_state->new_deq_seg, |
701 | deq_state->new_deq_ptr, | |
702 | (u32) deq_state->new_cycle_state); | |
703 | /* Stop the TD queueing code from ringing the doorbell until | |
704 | * this command completes. The HC won't set the dequeue pointer | |
705 | * if the ring is running, and ringing the doorbell starts the | |
706 | * ring running. | |
707 | */ | |
63a0d9ab | 708 | ep->ep_state |= SET_DEQ_PENDING; |
c92bcfa7 SS |
709 | } |
710 | ||
575688e1 | 711 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
712 | struct xhci_virt_ep *ep) |
713 | { | |
714 | ep->ep_state &= ~EP_HALT_PENDING; | |
715 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the | |
716 | * timer is running on another CPU, we don't decrement stop_cmds_pending | |
717 | * (since we didn't successfully stop the watchdog timer). | |
718 | */ | |
719 | if (del_timer(&ep->stop_cmd_timer)) | |
720 | ep->stop_cmds_pending--; | |
721 | } | |
722 | ||
723 | /* Must be called with xhci->lock held in interrupt context */ | |
724 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | |
07a37e9e | 725 | struct xhci_td *cur_td, int status) |
6f5165cf | 726 | { |
214f76f7 | 727 | struct usb_hcd *hcd; |
8e51adcc AX |
728 | struct urb *urb; |
729 | struct urb_priv *urb_priv; | |
6f5165cf | 730 | |
8e51adcc AX |
731 | urb = cur_td->urb; |
732 | urb_priv = urb->hcpriv; | |
733 | urb_priv->td_cnt++; | |
214f76f7 | 734 | hcd = bus_to_hcd(urb->dev->bus); |
6f5165cf | 735 | |
8e51adcc AX |
736 | /* Only giveback urb when this is the last td in urb */ |
737 | if (urb_priv->td_cnt == urb_priv->length) { | |
c41136b0 AX |
738 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
739 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
740 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
741 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
742 | usb_amd_quirk_pll_enable(); | |
743 | } | |
744 | } | |
8e51adcc | 745 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
8e51adcc AX |
746 | |
747 | spin_unlock(&xhci->lock); | |
748 | usb_hcd_giveback_urb(hcd, urb, status); | |
749 | xhci_urb_free_priv(xhci, urb_priv); | |
750 | spin_lock(&xhci->lock); | |
8e51adcc | 751 | } |
6f5165cf SS |
752 | } |
753 | ||
ae636747 SS |
754 | /* |
755 | * When we get a command completion for a Stop Endpoint Command, we need to | |
756 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
757 | * | |
758 | * 1. If the HW was in the middle of processing the TD that needs to be | |
759 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
760 | * in the TD with a Set Dequeue Pointer Command. | |
761 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
762 | * bit cleared) so that the HW will skip over them. | |
763 | */ | |
b8200c94 | 764 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 765 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 | 766 | { |
ae636747 | 767 | unsigned int ep_index; |
be88fe4f | 768 | struct xhci_virt_device *virt_dev; |
ae636747 | 769 | struct xhci_ring *ep_ring; |
63a0d9ab | 770 | struct xhci_virt_ep *ep; |
ae636747 | 771 | struct list_head *entry; |
326b4810 | 772 | struct xhci_td *cur_td = NULL; |
ae636747 SS |
773 | struct xhci_td *last_unlinked_td; |
774 | ||
c92bcfa7 | 775 | struct xhci_dequeue_state deq_state; |
ae636747 | 776 | |
bc752bde | 777 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
be88fe4f AX |
778 | virt_dev = xhci->devs[slot_id]; |
779 | if (virt_dev) | |
780 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, | |
781 | event); | |
782 | else | |
783 | xhci_warn(xhci, "Stop endpoint command " | |
784 | "completion for disabled slot %u\n", | |
785 | slot_id); | |
786 | return; | |
787 | } | |
788 | ||
ae636747 | 789 | memset(&deq_state, 0, sizeof(deq_state)); |
28ccd296 | 790 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
63a0d9ab | 791 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
ae636747 | 792 | |
678539cf | 793 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 794 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
0714a57c | 795 | ep->stopped_td = NULL; |
e9df17eb | 796 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 797 | return; |
678539cf | 798 | } |
ae636747 SS |
799 | |
800 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
801 | * We have the xHCI lock, so nothing can modify this list until we drop | |
802 | * it. We're also in the event handler, so we can't get re-interrupted | |
803 | * if another Stop Endpoint command completes | |
804 | */ | |
63a0d9ab | 805 | list_for_each(entry, &ep->cancelled_td_list) { |
ae636747 | 806 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
aa50b290 XR |
807 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
808 | "Removing canceled TD starting at 0x%llx (dma).", | |
79688acf SS |
809 | (unsigned long long)xhci_trb_virt_to_dma( |
810 | cur_td->start_seg, cur_td->first_trb)); | |
e9df17eb SS |
811 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
812 | if (!ep_ring) { | |
813 | /* This shouldn't happen unless a driver is mucking | |
814 | * with the stream ID after submission. This will | |
815 | * leave the TD on the hardware ring, and the hardware | |
816 | * will try to execute it, and may access a buffer | |
817 | * that has already been freed. In the best case, the | |
818 | * hardware will execute it, and the event handler will | |
819 | * ignore the completion event for that TD, since it was | |
820 | * removed from the td_list for that endpoint. In | |
821 | * short, don't muck with the stream ID after | |
822 | * submission. | |
823 | */ | |
824 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
825 | "has invalid stream ID %u.\n", | |
826 | cur_td->urb, | |
827 | cur_td->urb->stream_id); | |
828 | goto remove_finished_td; | |
829 | } | |
ae636747 SS |
830 | /* |
831 | * If we stopped on the TD we need to cancel, then we have to | |
832 | * move the xHC endpoint ring dequeue pointer past this TD. | |
833 | */ | |
63a0d9ab | 834 | if (cur_td == ep->stopped_td) |
e9df17eb SS |
835 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
836 | cur_td->urb->stream_id, | |
837 | cur_td, &deq_state); | |
ae636747 | 838 | else |
522989a2 | 839 | td_to_noop(xhci, ep_ring, cur_td, false); |
e9df17eb | 840 | remove_finished_td: |
ae636747 SS |
841 | /* |
842 | * The event handler won't see a completion for this TD anymore, | |
843 | * so remove it from the endpoint ring's TD list. Keep it in | |
844 | * the cancelled TD list for URB completion later. | |
845 | */ | |
585df1d9 | 846 | list_del_init(&cur_td->td_list); |
ae636747 SS |
847 | } |
848 | last_unlinked_td = cur_td; | |
6f5165cf | 849 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
850 | |
851 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
852 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
ddba5cd0 MN |
853 | struct xhci_command *command; |
854 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
855 | xhci_queue_new_dequeue_state(xhci, command, | |
e9df17eb SS |
856 | slot_id, ep_index, |
857 | ep->stopped_td->urb->stream_id, | |
858 | &deq_state); | |
ac9d8fe7 | 859 | xhci_ring_cmd_db(xhci); |
ae636747 | 860 | } else { |
e9df17eb SS |
861 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
862 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 863 | } |
526867c3 | 864 | |
1f81b6d2 JW |
865 | /* Clear stopped_td if endpoint is not halted */ |
866 | if (!(ep->ep_state & EP_HALTED)) | |
526867c3 | 867 | ep->stopped_td = NULL; |
ae636747 SS |
868 | |
869 | /* | |
870 | * Drop the lock and complete the URBs in the cancelled TD list. | |
871 | * New TDs to be cancelled might be added to the end of the list before | |
872 | * we can complete all the URBs for the TDs we already unlinked. | |
873 | * So stop when we've completed the URB for the last TD we unlinked. | |
874 | */ | |
875 | do { | |
63a0d9ab | 876 | cur_td = list_entry(ep->cancelled_td_list.next, |
ae636747 | 877 | struct xhci_td, cancelled_td_list); |
585df1d9 | 878 | list_del_init(&cur_td->cancelled_td_list); |
ae636747 SS |
879 | |
880 | /* Clean up the cancelled URB */ | |
ae636747 SS |
881 | /* Doesn't matter what we pass for status, since the core will |
882 | * just overwrite it (because the URB has been unlinked). | |
883 | */ | |
07a37e9e | 884 | xhci_giveback_urb_in_irq(xhci, cur_td, 0); |
ae636747 | 885 | |
6f5165cf SS |
886 | /* Stop processing the cancelled list if the watchdog timer is |
887 | * running. | |
888 | */ | |
889 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
890 | return; | |
ae636747 SS |
891 | } while (cur_td != last_unlinked_td); |
892 | ||
893 | /* Return to the event handler with xhci->lock re-acquired */ | |
894 | } | |
895 | ||
50e8725e SS |
896 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
897 | { | |
898 | struct xhci_td *cur_td; | |
899 | ||
900 | while (!list_empty(&ring->td_list)) { | |
901 | cur_td = list_first_entry(&ring->td_list, | |
902 | struct xhci_td, td_list); | |
903 | list_del_init(&cur_td->td_list); | |
904 | if (!list_empty(&cur_td->cancelled_td_list)) | |
905 | list_del_init(&cur_td->cancelled_td_list); | |
906 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
907 | } | |
908 | } | |
909 | ||
910 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, | |
911 | int slot_id, int ep_index) | |
912 | { | |
913 | struct xhci_td *cur_td; | |
914 | struct xhci_virt_ep *ep; | |
915 | struct xhci_ring *ring; | |
916 | ||
917 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
21d0e51b SS |
918 | if ((ep->ep_state & EP_HAS_STREAMS) || |
919 | (ep->ep_state & EP_GETTING_NO_STREAMS)) { | |
920 | int stream_id; | |
921 | ||
922 | for (stream_id = 0; stream_id < ep->stream_info->num_streams; | |
923 | stream_id++) { | |
924 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
925 | "Killing URBs for slot ID %u, ep index %u, stream %u", | |
926 | slot_id, ep_index, stream_id + 1); | |
927 | xhci_kill_ring_urbs(xhci, | |
928 | ep->stream_info->stream_rings[stream_id]); | |
929 | } | |
930 | } else { | |
931 | ring = ep->ring; | |
932 | if (!ring) | |
933 | return; | |
934 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
935 | "Killing URBs for slot ID %u, ep index %u", | |
936 | slot_id, ep_index); | |
937 | xhci_kill_ring_urbs(xhci, ring); | |
938 | } | |
50e8725e SS |
939 | while (!list_empty(&ep->cancelled_td_list)) { |
940 | cur_td = list_first_entry(&ep->cancelled_td_list, | |
941 | struct xhci_td, cancelled_td_list); | |
942 | list_del_init(&cur_td->cancelled_td_list); | |
943 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
944 | } | |
945 | } | |
946 | ||
6f5165cf SS |
947 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
948 | * In this case, we assume the host controller is broken or dying or dead. The | |
949 | * host may still be completing some other events, so we have to be careful to | |
950 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
951 | * through xhci->state. | |
952 | * | |
953 | * The timer may also fire if the host takes a very long time to respond to the | |
954 | * command, and the stop endpoint command completion handler cannot delete the | |
955 | * timer before the timer function is called. Another endpoint cancellation may | |
956 | * sneak in before the timer function can grab the lock, and that may queue | |
957 | * another stop endpoint command and add the timer back. So we cannot use a | |
958 | * simple flag to say whether there is a pending stop endpoint command for a | |
959 | * particular endpoint. | |
960 | * | |
961 | * Instead we use a combination of that flag and a counter for the number of | |
962 | * pending stop endpoint commands. If the timer is the tail end of the last | |
963 | * stop endpoint command, and the endpoint's command is still pending, we assume | |
964 | * the host is dying. | |
965 | */ | |
966 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
967 | { | |
968 | struct xhci_hcd *xhci; | |
969 | struct xhci_virt_ep *ep; | |
6f5165cf | 970 | int ret, i, j; |
f43d6231 | 971 | unsigned long flags; |
6f5165cf SS |
972 | |
973 | ep = (struct xhci_virt_ep *) arg; | |
974 | xhci = ep->xhci; | |
975 | ||
f43d6231 | 976 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
977 | |
978 | ep->stop_cmds_pending--; | |
979 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
aa50b290 XR |
980 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
981 | "Stop EP timer ran, but another timer marked " | |
982 | "xHCI as DYING, exiting."); | |
f43d6231 | 983 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
984 | return; |
985 | } | |
986 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { | |
aa50b290 XR |
987 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
988 | "Stop EP timer ran, but no command pending, " | |
989 | "exiting."); | |
f43d6231 | 990 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
991 | return; |
992 | } | |
993 | ||
994 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
995 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
996 | /* Oops, HC is dead or dying or at least not responding to the stop | |
997 | * endpoint command. | |
998 | */ | |
999 | xhci->xhc_state |= XHCI_STATE_DYING; | |
1000 | /* Disable interrupts from the host controller and start halting it */ | |
1001 | xhci_quiesce(xhci); | |
f43d6231 | 1002 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
1003 | |
1004 | ret = xhci_halt(xhci); | |
1005 | ||
f43d6231 | 1006 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
1007 | if (ret < 0) { |
1008 | /* This is bad; the host is not responding to commands and it's | |
1009 | * not allowing itself to be halted. At least interrupts are | |
ac04e6ff | 1010 | * disabled. If we call usb_hc_died(), it will attempt to |
6f5165cf SS |
1011 | * disconnect all device drivers under this host. Those |
1012 | * disconnect() methods will wait for all URBs to be unlinked, | |
1013 | * so we must complete them. | |
1014 | */ | |
1015 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
1016 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
1017 | /* We could turn all TDs on the rings to no-ops. This won't | |
1018 | * help if the host has cached part of the ring, and is slow if | |
1019 | * we want to preserve the cycle bit. Skip it and hope the host | |
1020 | * doesn't touch the memory. | |
1021 | */ | |
1022 | } | |
1023 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
1024 | if (!xhci->devs[i]) | |
1025 | continue; | |
50e8725e SS |
1026 | for (j = 0; j < 31; j++) |
1027 | xhci_kill_endpoint_urbs(xhci, i, j); | |
6f5165cf | 1028 | } |
f43d6231 | 1029 | spin_unlock_irqrestore(&xhci->lock, flags); |
aa50b290 XR |
1030 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1031 | "Calling usb_hc_died()"); | |
f6ff0ac8 | 1032 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); |
aa50b290 XR |
1033 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1034 | "xHCI host controller is dead."); | |
6f5165cf SS |
1035 | } |
1036 | ||
b008df60 AX |
1037 | |
1038 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, | |
1039 | struct xhci_virt_device *dev, | |
1040 | struct xhci_ring *ep_ring, | |
1041 | unsigned int ep_index) | |
1042 | { | |
1043 | union xhci_trb *dequeue_temp; | |
1044 | int num_trbs_free_temp; | |
1045 | bool revert = false; | |
1046 | ||
1047 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
1048 | dequeue_temp = ep_ring->dequeue; | |
1049 | ||
0d9f78a9 SS |
1050 | /* If we get two back-to-back stalls, and the first stalled transfer |
1051 | * ends just before a link TRB, the dequeue pointer will be left on | |
1052 | * the link TRB by the code in the while loop. So we have to update | |
1053 | * the dequeue pointer one segment further, or we'll jump off | |
1054 | * the segment into la-la-land. | |
1055 | */ | |
1056 | if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) { | |
1057 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
1058 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
1059 | } | |
1060 | ||
b008df60 AX |
1061 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
1062 | /* We have more usable TRBs */ | |
1063 | ep_ring->num_trbs_free++; | |
1064 | ep_ring->dequeue++; | |
1065 | if (last_trb(xhci, ep_ring, ep_ring->deq_seg, | |
1066 | ep_ring->dequeue)) { | |
1067 | if (ep_ring->dequeue == | |
1068 | dev->eps[ep_index].queued_deq_ptr) | |
1069 | break; | |
1070 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
1071 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
1072 | } | |
1073 | if (ep_ring->dequeue == dequeue_temp) { | |
1074 | revert = true; | |
1075 | break; | |
1076 | } | |
1077 | } | |
1078 | ||
1079 | if (revert) { | |
1080 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
1081 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
1082 | } | |
1083 | } | |
1084 | ||
ae636747 SS |
1085 | /* |
1086 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
1087 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
1088 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
1089 | * endpoint doorbell to restart the ring, but only if there aren't more | |
1090 | * cancellations pending. | |
1091 | */ | |
b8200c94 | 1092 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1093 | union xhci_trb *trb, u32 cmd_comp_code) |
ae636747 | 1094 | { |
ae636747 | 1095 | unsigned int ep_index; |
e9df17eb | 1096 | unsigned int stream_id; |
ae636747 SS |
1097 | struct xhci_ring *ep_ring; |
1098 | struct xhci_virt_device *dev; | |
9aad95e2 | 1099 | struct xhci_virt_ep *ep; |
d115b048 JY |
1100 | struct xhci_ep_ctx *ep_ctx; |
1101 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 | 1102 | |
28ccd296 ME |
1103 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
1104 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
ae636747 | 1105 | dev = xhci->devs[slot_id]; |
9aad95e2 | 1106 | ep = &dev->eps[ep_index]; |
e9df17eb SS |
1107 | |
1108 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
1109 | if (!ep_ring) { | |
e587b8b2 | 1110 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
e9df17eb SS |
1111 | stream_id); |
1112 | /* XXX: Harmless??? */ | |
1113 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; | |
1114 | return; | |
1115 | } | |
1116 | ||
d115b048 JY |
1117 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
1118 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
ae636747 | 1119 | |
c69a0597 | 1120 | if (cmd_comp_code != COMP_SUCCESS) { |
ae636747 SS |
1121 | unsigned int ep_state; |
1122 | unsigned int slot_state; | |
1123 | ||
c69a0597 | 1124 | switch (cmd_comp_code) { |
ae636747 | 1125 | case COMP_TRB_ERR: |
e587b8b2 | 1126 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
ae636747 SS |
1127 | break; |
1128 | case COMP_CTX_STATE: | |
e587b8b2 | 1129 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
28ccd296 | 1130 | ep_state = le32_to_cpu(ep_ctx->ep_info); |
ae636747 | 1131 | ep_state &= EP_STATE_MASK; |
28ccd296 | 1132 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 | 1133 | slot_state = GET_SLOT_STATE(slot_state); |
aa50b290 XR |
1134 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1135 | "Slot state = %u, EP state = %u", | |
ae636747 SS |
1136 | slot_state, ep_state); |
1137 | break; | |
1138 | case COMP_EBADSLT: | |
e587b8b2 ON |
1139 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
1140 | slot_id); | |
ae636747 SS |
1141 | break; |
1142 | default: | |
e587b8b2 ON |
1143 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
1144 | cmd_comp_code); | |
ae636747 SS |
1145 | break; |
1146 | } | |
1147 | /* OK what do we do now? The endpoint state is hosed, and we | |
1148 | * should never get to this point if the synchronization between | |
1149 | * queueing, and endpoint state are correct. This might happen | |
1150 | * if the device gets disconnected after we've finished | |
1151 | * cancelling URBs, which might not be an error... | |
1152 | */ | |
1153 | } else { | |
9aad95e2 HG |
1154 | u64 deq; |
1155 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ | |
1156 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1157 | struct xhci_stream_ctx *ctx = | |
1158 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1159 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; | |
1160 | } else { | |
1161 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; | |
1162 | } | |
aa50b290 | 1163 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
9aad95e2 HG |
1164 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
1165 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, | |
1166 | ep->queued_deq_ptr) == deq) { | |
bf161e85 SS |
1167 | /* Update the ring's dequeue segment and dequeue pointer |
1168 | * to reflect the new position. | |
1169 | */ | |
b008df60 AX |
1170 | update_ring_for_set_deq_completion(xhci, dev, |
1171 | ep_ring, ep_index); | |
bf161e85 | 1172 | } else { |
e587b8b2 | 1173 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
bf161e85 | 1174 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
9aad95e2 | 1175 | ep->queued_deq_seg, ep->queued_deq_ptr); |
bf161e85 | 1176 | } |
ae636747 SS |
1177 | } |
1178 | ||
63a0d9ab | 1179 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
bf161e85 SS |
1180 | dev->eps[ep_index].queued_deq_seg = NULL; |
1181 | dev->eps[ep_index].queued_deq_ptr = NULL; | |
e9df17eb SS |
1182 | /* Restart any rings with pending URBs */ |
1183 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1184 | } |
1185 | ||
b8200c94 | 1186 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1187 | union xhci_trb *trb, u32 cmd_comp_code) |
a1587d97 | 1188 | { |
a1587d97 SS |
1189 | unsigned int ep_index; |
1190 | ||
28ccd296 | 1191 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
a1587d97 SS |
1192 | /* This command will only fail if the endpoint wasn't halted, |
1193 | * but we don't care. | |
1194 | */ | |
a0254324 | 1195 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
c69a0597 | 1196 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
a1587d97 | 1197 | |
ac9d8fe7 SS |
1198 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
1199 | * command complete before the endpoint can be used. Queue that here | |
1200 | * because the HW can't handle two commands being queued in a row. | |
1201 | */ | |
1202 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
ddba5cd0 MN |
1203 | struct xhci_command *command; |
1204 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
4bdfe4c3 XR |
1205 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1206 | "Queueing configure endpoint command"); | |
ddba5cd0 | 1207 | xhci_queue_configure_endpoint(xhci, command, |
913a8a34 SS |
1208 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
1209 | false); | |
ac9d8fe7 SS |
1210 | xhci_ring_cmd_db(xhci); |
1211 | } else { | |
e9df17eb | 1212 | /* Clear our internal halted state and restart the ring(s) */ |
63a0d9ab | 1213 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
e9df17eb | 1214 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ac9d8fe7 | 1215 | } |
a1587d97 | 1216 | } |
ae636747 | 1217 | |
b63f4053 EF |
1218 | /* Complete the command and detele it from the devcie's command queue. |
1219 | */ | |
1220 | static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | |
1221 | struct xhci_command *command, u32 status) | |
1222 | { | |
1223 | command->status = status; | |
1224 | list_del(&command->cmd_list); | |
1225 | if (command->completion) | |
1226 | complete(command->completion); | |
1227 | else | |
1228 | xhci_free_command(xhci, command); | |
1229 | } | |
1230 | ||
1231 | ||
a50c8aa9 SS |
1232 | /* Check to see if a command in the device's command queue matches this one. |
1233 | * Signal the completion or free the command, and return 1. Return 0 if the | |
1234 | * completed command isn't at the head of the command list. | |
1235 | */ | |
1236 | static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci, | |
1237 | struct xhci_virt_device *virt_dev, | |
1238 | struct xhci_event_cmd *event) | |
1239 | { | |
1240 | struct xhci_command *command; | |
1241 | ||
1242 | if (list_empty(&virt_dev->cmd_list)) | |
1243 | return 0; | |
1244 | ||
1245 | command = list_entry(virt_dev->cmd_list.next, | |
1246 | struct xhci_command, cmd_list); | |
1247 | if (xhci->cmd_ring->dequeue != command->command_trb) | |
1248 | return 0; | |
1249 | ||
b63f4053 EF |
1250 | xhci_complete_cmd_in_cmd_wait_list(xhci, command, |
1251 | GET_COMP_CODE(le32_to_cpu(event->status))); | |
a50c8aa9 SS |
1252 | return 1; |
1253 | } | |
1254 | ||
b63f4053 EF |
1255 | /* |
1256 | * Finding the command trb need to be cancelled and modifying it to | |
1257 | * NO OP command. And if the command is in device's command wait | |
1258 | * list, finishing and freeing it. | |
1259 | * | |
1260 | * If we can't find the command trb, we think it had already been | |
1261 | * executed. | |
1262 | */ | |
1263 | static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd) | |
1264 | { | |
1265 | struct xhci_segment *cur_seg; | |
1266 | union xhci_trb *cmd_trb; | |
1267 | u32 cycle_state; | |
1268 | ||
1269 | if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue) | |
1270 | return; | |
1271 | ||
1272 | /* find the current segment of command ring */ | |
1273 | cur_seg = find_trb_seg(xhci->cmd_ring->first_seg, | |
1274 | xhci->cmd_ring->dequeue, &cycle_state); | |
1275 | ||
43a09f7f SS |
1276 | if (!cur_seg) { |
1277 | xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n", | |
1278 | xhci->cmd_ring->dequeue, | |
1279 | (unsigned long long) | |
1280 | xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | |
1281 | xhci->cmd_ring->dequeue)); | |
1282 | xhci_debug_ring(xhci, xhci->cmd_ring); | |
1283 | xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring); | |
1284 | return; | |
1285 | } | |
1286 | ||
b63f4053 EF |
1287 | /* find the command trb matched by cd from command ring */ |
1288 | for (cmd_trb = xhci->cmd_ring->dequeue; | |
1289 | cmd_trb != xhci->cmd_ring->enqueue; | |
1290 | next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) { | |
1291 | /* If the trb is link trb, continue */ | |
1292 | if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3])) | |
1293 | continue; | |
1294 | ||
1295 | if (cur_cd->cmd_trb == cmd_trb) { | |
1296 | ||
1297 | /* If the command in device's command list, we should | |
1298 | * finish it and free the command structure. | |
1299 | */ | |
1300 | if (cur_cd->command) | |
1301 | xhci_complete_cmd_in_cmd_wait_list(xhci, | |
1302 | cur_cd->command, COMP_CMD_STOP); | |
1303 | ||
1304 | /* get cycle state from the origin command trb */ | |
1305 | cycle_state = le32_to_cpu(cmd_trb->generic.field[3]) | |
1306 | & TRB_CYCLE; | |
1307 | ||
1308 | /* modify the command trb to NO OP command */ | |
1309 | cmd_trb->generic.field[0] = 0; | |
1310 | cmd_trb->generic.field[1] = 0; | |
1311 | cmd_trb->generic.field[2] = 0; | |
1312 | cmd_trb->generic.field[3] = cpu_to_le32( | |
1313 | TRB_TYPE(TRB_CMD_NOOP) | cycle_state); | |
1314 | break; | |
1315 | } | |
1316 | } | |
1317 | } | |
1318 | ||
1319 | static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci) | |
1320 | { | |
1321 | struct xhci_cd *cur_cd, *next_cd; | |
1322 | ||
1323 | if (list_empty(&xhci->cancel_cmd_list)) | |
1324 | return; | |
1325 | ||
1326 | list_for_each_entry_safe(cur_cd, next_cd, | |
1327 | &xhci->cancel_cmd_list, cancel_cmd_list) { | |
1328 | xhci_cmd_to_noop(xhci, cur_cd); | |
1329 | list_del(&cur_cd->cancel_cmd_list); | |
1330 | kfree(cur_cd); | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | /* | |
1335 | * traversing the cancel_cmd_list. If the command descriptor according | |
1336 | * to cmd_trb is found, the function free it and return 1, otherwise | |
1337 | * return 0. | |
1338 | */ | |
1339 | static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci, | |
1340 | union xhci_trb *cmd_trb) | |
1341 | { | |
1342 | struct xhci_cd *cur_cd, *next_cd; | |
1343 | ||
1344 | if (list_empty(&xhci->cancel_cmd_list)) | |
1345 | return 0; | |
1346 | ||
1347 | list_for_each_entry_safe(cur_cd, next_cd, | |
1348 | &xhci->cancel_cmd_list, cancel_cmd_list) { | |
1349 | if (cur_cd->cmd_trb == cmd_trb) { | |
1350 | if (cur_cd->command) | |
1351 | xhci_complete_cmd_in_cmd_wait_list(xhci, | |
1352 | cur_cd->command, COMP_CMD_STOP); | |
1353 | list_del(&cur_cd->cancel_cmd_list); | |
1354 | kfree(cur_cd); | |
1355 | return 1; | |
1356 | } | |
1357 | } | |
1358 | ||
1359 | return 0; | |
1360 | } | |
1361 | ||
1362 | /* | |
1363 | * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the | |
1364 | * trb pointed by the command ring dequeue pointer is the trb we want to | |
1365 | * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will | |
1366 | * traverse the cancel_cmd_list to trun the all of the commands according | |
1367 | * to command descriptor to NO-OP trb. | |
1368 | */ | |
1369 | static int handle_stopped_cmd_ring(struct xhci_hcd *xhci, | |
1370 | int cmd_trb_comp_code) | |
1371 | { | |
1372 | int cur_trb_is_good = 0; | |
1373 | ||
1374 | /* Searching the cmd trb pointed by the command ring dequeue | |
1375 | * pointer in command descriptor list. If it is found, free it. | |
1376 | */ | |
1377 | cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci, | |
1378 | xhci->cmd_ring->dequeue); | |
1379 | ||
1380 | if (cmd_trb_comp_code == COMP_CMD_ABORT) | |
1381 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
1382 | else if (cmd_trb_comp_code == COMP_CMD_STOP) { | |
1383 | /* traversing the cancel_cmd_list and canceling | |
1384 | * the command according to command descriptor | |
1385 | */ | |
1386 | xhci_cancel_cmd_in_cd_list(xhci); | |
1387 | ||
1388 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; | |
1389 | /* | |
1390 | * ring command ring doorbell again to restart the | |
1391 | * command ring | |
1392 | */ | |
1393 | if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) | |
1394 | xhci_ring_cmd_db(xhci); | |
1395 | } | |
1396 | return cur_trb_is_good; | |
1397 | } | |
1398 | ||
b244b431 XR |
1399 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
1400 | u32 cmd_comp_code) | |
1401 | { | |
1402 | if (cmd_comp_code == COMP_SUCCESS) | |
1403 | xhci->slot_id = slot_id; | |
1404 | else | |
1405 | xhci->slot_id = 0; | |
1406 | complete(&xhci->addr_dev); | |
1407 | } | |
1408 | ||
6c02dd14 XR |
1409 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
1410 | { | |
1411 | struct xhci_virt_device *virt_dev; | |
1412 | ||
1413 | virt_dev = xhci->devs[slot_id]; | |
1414 | if (!virt_dev) | |
1415 | return; | |
1416 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) | |
1417 | /* Delete default control endpoint resources */ | |
1418 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); | |
1419 | xhci_free_virt_device(xhci, slot_id); | |
1420 | } | |
1421 | ||
6ed46d33 XR |
1422 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
1423 | struct xhci_event_cmd *event, u32 cmd_comp_code) | |
1424 | { | |
1425 | struct xhci_virt_device *virt_dev; | |
1426 | struct xhci_input_control_ctx *ctrl_ctx; | |
1427 | unsigned int ep_index; | |
1428 | unsigned int ep_state; | |
1429 | u32 add_flags, drop_flags; | |
1430 | ||
1431 | virt_dev = xhci->devs[slot_id]; | |
1432 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) | |
1433 | return; | |
1434 | /* | |
1435 | * Configure endpoint commands can come from the USB core | |
1436 | * configuration or alt setting changes, or because the HW | |
1437 | * needed an extra configure endpoint command after a reset | |
1438 | * endpoint command or streams were being configured. | |
1439 | * If the command was for a halted endpoint, the xHCI driver | |
1440 | * is not waiting on the configure endpoint command. | |
1441 | */ | |
1442 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); | |
1443 | if (!ctrl_ctx) { | |
1444 | xhci_warn(xhci, "Could not get input context, bad type.\n"); | |
1445 | return; | |
1446 | } | |
1447 | ||
1448 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
1449 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
1450 | /* Input ctx add_flags are the endpoint index plus one */ | |
1451 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; | |
1452 | ||
1453 | /* A usb_set_interface() call directly after clearing a halted | |
1454 | * condition may race on this quirky hardware. Not worth | |
1455 | * worrying about, since this is prototype hardware. Not sure | |
1456 | * if this will work for streams, but streams support was | |
1457 | * untested on this prototype. | |
1458 | */ | |
1459 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
1460 | ep_index != (unsigned int) -1 && | |
1461 | add_flags - SLOT_FLAG == drop_flags) { | |
1462 | ep_state = virt_dev->eps[ep_index].ep_state; | |
1463 | if (!(ep_state & EP_HALTED)) | |
ddba5cd0 | 1464 | return; |
6ed46d33 XR |
1465 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1466 | "Completed config ep cmd - " | |
1467 | "last ep index = %d, state = %d", | |
1468 | ep_index, ep_state); | |
1469 | /* Clear internal halted state and restart ring(s) */ | |
1470 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; | |
1471 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
1472 | return; | |
1473 | } | |
6ed46d33 XR |
1474 | return; |
1475 | } | |
1476 | ||
07948a8d XR |
1477 | static void xhci_handle_cmd_eval_ctx(struct xhci_hcd *xhci, int slot_id, |
1478 | struct xhci_event_cmd *event, u32 cmd_comp_code) | |
1479 | { | |
1480 | struct xhci_virt_device *virt_dev; | |
1481 | ||
1482 | virt_dev = xhci->devs[slot_id]; | |
1483 | if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event)) | |
1484 | return; | |
1485 | virt_dev->cmd_status = cmd_comp_code; | |
1486 | complete(&virt_dev->cmd_completion); | |
1487 | } | |
1488 | ||
9b3103ac XR |
1489 | static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id, |
1490 | u32 cmd_comp_code) | |
1491 | { | |
1492 | xhci->devs[slot_id]->cmd_status = cmd_comp_code; | |
1493 | complete(&xhci->addr_dev); | |
1494 | } | |
1495 | ||
f681321b XR |
1496 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, |
1497 | struct xhci_event_cmd *event) | |
1498 | { | |
1499 | struct xhci_virt_device *virt_dev; | |
1500 | ||
1501 | xhci_dbg(xhci, "Completed reset device command.\n"); | |
1502 | virt_dev = xhci->devs[slot_id]; | |
1503 | if (virt_dev) | |
1504 | handle_cmd_in_cmd_wait_list(xhci, virt_dev, event); | |
1505 | else | |
1506 | xhci_warn(xhci, "Reset device command completion " | |
1507 | "for disabled slot %u\n", slot_id); | |
1508 | } | |
1509 | ||
2c070821 XR |
1510 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
1511 | struct xhci_event_cmd *event) | |
1512 | { | |
1513 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
1514 | xhci->error_bitmask |= 1 << 6; | |
1515 | return; | |
1516 | } | |
1517 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1518 | "NEC firmware version %2x.%02x", | |
1519 | NEC_FW_MAJOR(le32_to_cpu(event->status)), | |
1520 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
1521 | } | |
1522 | ||
c9aa1a2d MN |
1523 | static void xhci_del_and_free_cmd(struct xhci_command *cmd) |
1524 | { | |
1525 | list_del(&cmd->cmd_list); | |
1526 | if (!cmd->completion) | |
1527 | kfree(cmd); | |
1528 | } | |
1529 | ||
1530 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci) | |
1531 | { | |
1532 | struct xhci_command *cur_cmd, *tmp_cmd; | |
1533 | list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) | |
1534 | xhci_del_and_free_cmd(cur_cmd); | |
1535 | } | |
1536 | ||
7f84eef0 SS |
1537 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1538 | struct xhci_event_cmd *event) | |
1539 | { | |
28ccd296 | 1540 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1541 | u64 cmd_dma; |
1542 | dma_addr_t cmd_dequeue_dma; | |
e7a79a1d | 1543 | u32 cmd_comp_code; |
9124b121 | 1544 | union xhci_trb *cmd_trb; |
c9aa1a2d | 1545 | struct xhci_command *cmd; |
b54fc46d | 1546 | u32 cmd_type; |
7f84eef0 | 1547 | |
28ccd296 | 1548 | cmd_dma = le64_to_cpu(event->cmd_trb); |
9124b121 | 1549 | cmd_trb = xhci->cmd_ring->dequeue; |
23e3be11 | 1550 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
9124b121 | 1551 | cmd_trb); |
7f84eef0 SS |
1552 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ |
1553 | if (cmd_dequeue_dma == 0) { | |
1554 | xhci->error_bitmask |= 1 << 4; | |
1555 | return; | |
1556 | } | |
1557 | /* Does the DMA address match our internal dequeue pointer address? */ | |
1558 | if (cmd_dma != (u64) cmd_dequeue_dma) { | |
1559 | xhci->error_bitmask |= 1 << 5; | |
1560 | return; | |
1561 | } | |
b63f4053 | 1562 | |
c9aa1a2d MN |
1563 | cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list); |
1564 | ||
1565 | if (cmd->command_trb != xhci->cmd_ring->dequeue) { | |
1566 | xhci_err(xhci, | |
1567 | "Command completion event does not match command\n"); | |
1568 | return; | |
1569 | } | |
9124b121 | 1570 | trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event); |
63a23b9a | 1571 | |
e7a79a1d XR |
1572 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
1573 | if (cmd_comp_code == COMP_CMD_ABORT || cmd_comp_code == COMP_CMD_STOP) { | |
b63f4053 EF |
1574 | /* If the return value is 0, we think the trb pointed by |
1575 | * command ring dequeue pointer is a good trb. The good | |
1576 | * trb means we don't want to cancel the trb, but it have | |
1577 | * been stopped by host. So we should handle it normally. | |
1578 | * Otherwise, driver should invoke inc_deq() and return. | |
1579 | */ | |
e7a79a1d | 1580 | if (handle_stopped_cmd_ring(xhci, cmd_comp_code)) { |
b63f4053 EF |
1581 | inc_deq(xhci, xhci->cmd_ring); |
1582 | return; | |
1583 | } | |
284d2055 MN |
1584 | /* There is no command to handle if we get a stop event when the |
1585 | * command ring is empty, event->cmd_trb points to the next | |
1586 | * unset command | |
1587 | */ | |
1588 | if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue) | |
1589 | return; | |
b63f4053 EF |
1590 | } |
1591 | ||
b54fc46d XR |
1592 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
1593 | switch (cmd_type) { | |
1594 | case TRB_ENABLE_SLOT: | |
e7a79a1d | 1595 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code); |
3ffbba95 | 1596 | break; |
b54fc46d | 1597 | case TRB_DISABLE_SLOT: |
6c02dd14 | 1598 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
3ffbba95 | 1599 | break; |
b54fc46d | 1600 | case TRB_CONFIG_EP: |
e7a79a1d | 1601 | xhci_handle_cmd_config_ep(xhci, slot_id, event, cmd_comp_code); |
f94e0186 | 1602 | break; |
b54fc46d | 1603 | case TRB_EVAL_CONTEXT: |
e7a79a1d | 1604 | xhci_handle_cmd_eval_ctx(xhci, slot_id, event, cmd_comp_code); |
2d3f1fac | 1605 | break; |
b54fc46d | 1606 | case TRB_ADDR_DEV: |
e7a79a1d | 1607 | xhci_handle_cmd_addr_dev(xhci, slot_id, cmd_comp_code); |
3ffbba95 | 1608 | break; |
b54fc46d | 1609 | case TRB_STOP_RING: |
b8200c94 XR |
1610 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1611 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
1612 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); | |
ae636747 | 1613 | break; |
b54fc46d | 1614 | case TRB_SET_DEQ: |
b8200c94 XR |
1615 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1616 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1617 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
ae636747 | 1618 | break; |
b54fc46d | 1619 | case TRB_CMD_NOOP: |
7f84eef0 | 1620 | break; |
b54fc46d | 1621 | case TRB_RESET_EP: |
b8200c94 XR |
1622 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1623 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1624 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
a1587d97 | 1625 | break; |
b54fc46d | 1626 | case TRB_RESET_DEV: |
20e7acb1 | 1627 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
9124b121 | 1628 | le32_to_cpu(cmd_trb->generic.field[3]))); |
f681321b | 1629 | xhci_handle_cmd_reset_dev(xhci, slot_id, event); |
2a8f82c4 | 1630 | break; |
b54fc46d | 1631 | case TRB_NEC_GET_FW: |
2c070821 | 1632 | xhci_handle_cmd_nec_get_fw(xhci, event); |
0238634d | 1633 | break; |
7f84eef0 SS |
1634 | default: |
1635 | /* Skip over unknown commands on the event ring */ | |
1636 | xhci->error_bitmask |= 1 << 6; | |
1637 | break; | |
1638 | } | |
c9aa1a2d MN |
1639 | |
1640 | xhci_del_and_free_cmd(cmd); | |
1641 | ||
3b72fca0 | 1642 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1643 | } |
1644 | ||
0238634d SS |
1645 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1646 | union xhci_trb *event) | |
1647 | { | |
1648 | u32 trb_type; | |
1649 | ||
28ccd296 | 1650 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
0238634d SS |
1651 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1652 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1653 | handle_cmd_completion(xhci, &event->event_cmd); | |
1654 | } | |
1655 | ||
f6ff0ac8 SS |
1656 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
1657 | * port registers -- USB 3.0 and USB 2.0). | |
1658 | * | |
1659 | * Returns a zero-based port number, which is suitable for indexing into each of | |
1660 | * the split roothubs' port arrays and bus state arrays. | |
d0cd5d48 | 1661 | * Add one to it in order to call xhci_find_slot_id_by_port. |
f6ff0ac8 SS |
1662 | */ |
1663 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, | |
1664 | struct xhci_hcd *xhci, u32 port_id) | |
1665 | { | |
1666 | unsigned int i; | |
1667 | unsigned int num_similar_speed_ports = 0; | |
1668 | ||
1669 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], | |
1670 | * and usb2_ports are 0-based indexes. Count the number of similar | |
1671 | * speed ports, up to 1 port before this port. | |
1672 | */ | |
1673 | for (i = 0; i < (port_id - 1); i++) { | |
1674 | u8 port_speed = xhci->port_array[i]; | |
1675 | ||
1676 | /* | |
1677 | * Skip ports that don't have known speeds, or have duplicate | |
1678 | * Extended Capabilities port speed entries. | |
1679 | */ | |
22e04870 | 1680 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
1681 | continue; |
1682 | ||
1683 | /* | |
1684 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
1685 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
1686 | * matches the device speed, it's a similar speed port. | |
1687 | */ | |
1688 | if ((port_speed == 0x03) == (hcd->speed == HCD_USB3)) | |
1689 | num_similar_speed_ports++; | |
1690 | } | |
1691 | return num_similar_speed_ports; | |
1692 | } | |
1693 | ||
623bef9e SS |
1694 | static void handle_device_notification(struct xhci_hcd *xhci, |
1695 | union xhci_trb *event) | |
1696 | { | |
1697 | u32 slot_id; | |
4ee823b8 | 1698 | struct usb_device *udev; |
623bef9e | 1699 | |
7e76ad43 | 1700 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
4ee823b8 | 1701 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1702 | xhci_warn(xhci, "Device Notification event for " |
1703 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1704 | return; |
1705 | } | |
1706 | ||
1707 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1708 | slot_id); | |
1709 | udev = xhci->devs[slot_id]->udev; | |
1710 | if (udev && udev->parent) | |
1711 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1712 | } |
1713 | ||
0f2a7930 SS |
1714 | static void handle_port_status(struct xhci_hcd *xhci, |
1715 | union xhci_trb *event) | |
1716 | { | |
f6ff0ac8 | 1717 | struct usb_hcd *hcd; |
0f2a7930 | 1718 | u32 port_id; |
56192531 | 1719 | u32 temp, temp1; |
518e848e | 1720 | int max_ports; |
56192531 | 1721 | int slot_id; |
5308a91b | 1722 | unsigned int faked_port_index; |
f6ff0ac8 | 1723 | u8 major_revision; |
20b67cf5 | 1724 | struct xhci_bus_state *bus_state; |
28ccd296 | 1725 | __le32 __iomem **port_array; |
386139d7 | 1726 | bool bogus_port_status = false; |
0f2a7930 SS |
1727 | |
1728 | /* Port status change events always have a successful completion code */ | |
28ccd296 | 1729 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) { |
0f2a7930 SS |
1730 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); |
1731 | xhci->error_bitmask |= 1 << 8; | |
1732 | } | |
28ccd296 | 1733 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
0f2a7930 SS |
1734 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
1735 | ||
518e848e SS |
1736 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1737 | if ((port_id <= 0) || (port_id > max_ports)) { | |
56192531 | 1738 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
09ce0c0c PC |
1739 | inc_deq(xhci, xhci->event_ring); |
1740 | return; | |
56192531 AX |
1741 | } |
1742 | ||
f6ff0ac8 SS |
1743 | /* Figure out which usb_hcd this port is attached to: |
1744 | * is it a USB 3.0 port or a USB 2.0/1.1 port? | |
1745 | */ | |
1746 | major_revision = xhci->port_array[port_id - 1]; | |
09ce0c0c PC |
1747 | |
1748 | /* Find the right roothub. */ | |
1749 | hcd = xhci_to_hcd(xhci); | |
1750 | if ((major_revision == 0x03) != (hcd->speed == HCD_USB3)) | |
1751 | hcd = xhci->shared_hcd; | |
1752 | ||
f6ff0ac8 SS |
1753 | if (major_revision == 0) { |
1754 | xhci_warn(xhci, "Event for port %u not in " | |
1755 | "Extended Capabilities, ignoring.\n", | |
1756 | port_id); | |
386139d7 | 1757 | bogus_port_status = true; |
f6ff0ac8 | 1758 | goto cleanup; |
5308a91b | 1759 | } |
22e04870 | 1760 | if (major_revision == DUPLICATE_ENTRY) { |
f6ff0ac8 SS |
1761 | xhci_warn(xhci, "Event for port %u duplicated in" |
1762 | "Extended Capabilities, ignoring.\n", | |
1763 | port_id); | |
386139d7 | 1764 | bogus_port_status = true; |
f6ff0ac8 SS |
1765 | goto cleanup; |
1766 | } | |
1767 | ||
1768 | /* | |
1769 | * Hardware port IDs reported by a Port Status Change Event include USB | |
1770 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a | |
1771 | * resume event, but we first need to translate the hardware port ID | |
1772 | * into the index into the ports on the correct split roothub, and the | |
1773 | * correct bus_state structure. | |
1774 | */ | |
f6ff0ac8 SS |
1775 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
1776 | if (hcd->speed == HCD_USB3) | |
1777 | port_array = xhci->usb3_ports; | |
1778 | else | |
1779 | port_array = xhci->usb2_ports; | |
1780 | /* Find the faked port hub number */ | |
1781 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, | |
1782 | port_id); | |
5308a91b | 1783 | |
b0ba9720 | 1784 | temp = readl(port_array[faked_port_index]); |
7111ebc9 | 1785 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1786 | xhci_dbg(xhci, "resume root hub\n"); |
1787 | usb_hcd_resume_root_hub(hcd); | |
1788 | } | |
1789 | ||
1790 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { | |
1791 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | |
1792 | ||
b0ba9720 | 1793 | temp1 = readl(&xhci->op_regs->command); |
56192531 AX |
1794 | if (!(temp1 & CMD_RUN)) { |
1795 | xhci_warn(xhci, "xHC is not running.\n"); | |
1796 | goto cleanup; | |
1797 | } | |
1798 | ||
1799 | if (DEV_SUPERSPEED(temp)) { | |
d93814cf | 1800 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1801 | /* Set a flag to say the port signaled remote wakeup, |
1802 | * so we can tell the difference between the end of | |
1803 | * device and host initiated resume. | |
1804 | */ | |
1805 | bus_state->port_remote_wakeup |= 1 << faked_port_index; | |
d93814cf SS |
1806 | xhci_test_and_clear_bit(xhci, port_array, |
1807 | faked_port_index, PORT_PLC); | |
c9682dff AX |
1808 | xhci_set_link_state(xhci, port_array, faked_port_index, |
1809 | XDEV_U0); | |
d93814cf SS |
1810 | /* Need to wait until the next link state change |
1811 | * indicates the device is actually in U0. | |
1812 | */ | |
1813 | bogus_port_status = true; | |
1814 | goto cleanup; | |
56192531 AX |
1815 | } else { |
1816 | xhci_dbg(xhci, "resume HS port %d\n", port_id); | |
f6ff0ac8 | 1817 | bus_state->resume_done[faked_port_index] = jiffies + |
56192531 | 1818 | msecs_to_jiffies(20); |
f370b996 | 1819 | set_bit(faked_port_index, &bus_state->resuming_ports); |
56192531 | 1820 | mod_timer(&hcd->rh_timer, |
f6ff0ac8 | 1821 | bus_state->resume_done[faked_port_index]); |
56192531 AX |
1822 | /* Do the rest in GetPortStatus */ |
1823 | } | |
1824 | } | |
d93814cf SS |
1825 | |
1826 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && | |
1827 | DEV_SUPERSPEED(temp)) { | |
1828 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); | |
4ee823b8 SS |
1829 | /* We've just brought the device into U0 through either the |
1830 | * Resume state after a device remote wakeup, or through the | |
1831 | * U3Exit state after a host-initiated resume. If it's a device | |
1832 | * initiated remote wake, don't pass up the link state change, | |
1833 | * so the roothub behavior is consistent with external | |
1834 | * USB 3.0 hub behavior. | |
1835 | */ | |
d93814cf SS |
1836 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1837 | faked_port_index + 1); | |
1838 | if (slot_id && xhci->devs[slot_id]) | |
1839 | xhci_ring_device(xhci, slot_id); | |
ba7b5c22 | 1840 | if (bus_state->port_remote_wakeup & (1 << faked_port_index)) { |
4ee823b8 SS |
1841 | bus_state->port_remote_wakeup &= |
1842 | ~(1 << faked_port_index); | |
1843 | xhci_test_and_clear_bit(xhci, port_array, | |
1844 | faked_port_index, PORT_PLC); | |
1845 | usb_wakeup_notification(hcd->self.root_hub, | |
1846 | faked_port_index + 1); | |
1847 | bogus_port_status = true; | |
1848 | goto cleanup; | |
1849 | } | |
d93814cf | 1850 | } |
56192531 | 1851 | |
8b3d4570 SS |
1852 | /* |
1853 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or | |
1854 | * RExit to a disconnect state). If so, let the the driver know it's | |
1855 | * out of the RExit state. | |
1856 | */ | |
1857 | if (!DEV_SUPERSPEED(temp) && | |
1858 | test_and_clear_bit(faked_port_index, | |
1859 | &bus_state->rexit_ports)) { | |
1860 | complete(&bus_state->rexit_done[faked_port_index]); | |
1861 | bogus_port_status = true; | |
1862 | goto cleanup; | |
1863 | } | |
1864 | ||
6fd45621 AX |
1865 | if (hcd->speed != HCD_USB3) |
1866 | xhci_test_and_clear_bit(xhci, port_array, faked_port_index, | |
1867 | PORT_PLC); | |
1868 | ||
56192531 | 1869 | cleanup: |
0f2a7930 | 1870 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 1871 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 1872 | |
386139d7 SS |
1873 | /* Don't make the USB core poll the roothub if we got a bad port status |
1874 | * change event. Besides, at that point we can't tell which roothub | |
1875 | * (USB 2.0 or USB 3.0) to kick. | |
1876 | */ | |
1877 | if (bogus_port_status) | |
1878 | return; | |
1879 | ||
c52804a4 SS |
1880 | /* |
1881 | * xHCI port-status-change events occur when the "or" of all the | |
1882 | * status-change bits in the portsc register changes from 0 to 1. | |
1883 | * New status changes won't cause an event if any other change | |
1884 | * bits are still set. When an event occurs, switch over to | |
1885 | * polling to avoid losing status changes. | |
1886 | */ | |
1887 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1888 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1889 | spin_unlock(&xhci->lock); |
1890 | /* Pass this up to the core */ | |
f6ff0ac8 | 1891 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
1892 | spin_lock(&xhci->lock); |
1893 | } | |
1894 | ||
d0e96f5a SS |
1895 | /* |
1896 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1897 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1898 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1899 | * returns 0. | |
1900 | */ | |
6648f29d | 1901 | struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, |
d0e96f5a SS |
1902 | union xhci_trb *start_trb, |
1903 | union xhci_trb *end_trb, | |
1904 | dma_addr_t suspect_dma) | |
1905 | { | |
1906 | dma_addr_t start_dma; | |
1907 | dma_addr_t end_seg_dma; | |
1908 | dma_addr_t end_trb_dma; | |
1909 | struct xhci_segment *cur_seg; | |
1910 | ||
23e3be11 | 1911 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1912 | cur_seg = start_seg; |
1913 | ||
1914 | do { | |
2fa88daa | 1915 | if (start_dma == 0) |
326b4810 | 1916 | return NULL; |
ae636747 | 1917 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1918 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1919 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1920 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1921 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a SS |
1922 | |
1923 | if (end_trb_dma > 0) { | |
1924 | /* The end TRB is in this segment, so suspect should be here */ | |
1925 | if (start_dma <= end_trb_dma) { | |
1926 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1927 | return cur_seg; | |
1928 | } else { | |
1929 | /* Case for one segment with | |
1930 | * a TD wrapped around to the top | |
1931 | */ | |
1932 | if ((suspect_dma >= start_dma && | |
1933 | suspect_dma <= end_seg_dma) || | |
1934 | (suspect_dma >= cur_seg->dma && | |
1935 | suspect_dma <= end_trb_dma)) | |
1936 | return cur_seg; | |
1937 | } | |
326b4810 | 1938 | return NULL; |
d0e96f5a SS |
1939 | } else { |
1940 | /* Might still be somewhere in this segment */ | |
1941 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1942 | return cur_seg; | |
1943 | } | |
1944 | cur_seg = cur_seg->next; | |
23e3be11 | 1945 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1946 | } while (cur_seg != start_seg); |
d0e96f5a | 1947 | |
326b4810 | 1948 | return NULL; |
d0e96f5a SS |
1949 | } |
1950 | ||
bcef3fd5 SS |
1951 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1952 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1953 | unsigned int stream_id, |
bcef3fd5 SS |
1954 | struct xhci_td *td, union xhci_trb *event_trb) |
1955 | { | |
1956 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
ddba5cd0 MN |
1957 | struct xhci_command *command; |
1958 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
1959 | if (!command) | |
1960 | return; | |
1961 | ||
bcef3fd5 SS |
1962 | ep->ep_state |= EP_HALTED; |
1963 | ep->stopped_td = td; | |
e9df17eb | 1964 | ep->stopped_stream = stream_id; |
1624ae1c | 1965 | |
ddba5cd0 | 1966 | xhci_queue_reset_ep(xhci, command, slot_id, ep_index); |
bcef3fd5 | 1967 | xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); |
1624ae1c SS |
1968 | |
1969 | ep->stopped_td = NULL; | |
5e5cf6fc | 1970 | ep->stopped_stream = 0; |
1624ae1c | 1971 | |
bcef3fd5 SS |
1972 | xhci_ring_cmd_db(xhci); |
1973 | } | |
1974 | ||
1975 | /* Check if an error has halted the endpoint ring. The class driver will | |
1976 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1977 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1978 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1979 | * Ring Dequeue Pointer command manually. | |
1980 | */ | |
1981 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1982 | struct xhci_ep_ctx *ep_ctx, | |
1983 | unsigned int trb_comp_code) | |
1984 | { | |
1985 | /* TRB completion codes that may require a manual halt cleanup */ | |
1986 | if (trb_comp_code == COMP_TX_ERR || | |
1987 | trb_comp_code == COMP_BABBLE || | |
1988 | trb_comp_code == COMP_SPLIT_ERR) | |
1989 | /* The 0.96 spec says a babbling control endpoint | |
1990 | * is not halted. The 0.96 spec says it is. Some HW | |
1991 | * claims to be 0.95 compliant, but it halts the control | |
1992 | * endpoint anyway. Check if a babble halted the | |
1993 | * endpoint. | |
1994 | */ | |
f5960b69 ME |
1995 | if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == |
1996 | cpu_to_le32(EP_STATE_HALTED)) | |
bcef3fd5 SS |
1997 | return 1; |
1998 | ||
1999 | return 0; | |
2000 | } | |
2001 | ||
b45b5069 SS |
2002 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
2003 | { | |
2004 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
2005 | /* Vendor defined "informational" completion code, | |
2006 | * treat as not-an-error. | |
2007 | */ | |
2008 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
2009 | trb_comp_code); | |
2010 | xhci_dbg(xhci, "Treating code as success.\n"); | |
2011 | return 1; | |
2012 | } | |
2013 | return 0; | |
2014 | } | |
2015 | ||
4422da61 AX |
2016 | /* |
2017 | * Finish the td processing, remove the td from td list; | |
2018 | * Return 1 if the urb can be given back. | |
2019 | */ | |
2020 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
2021 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
2022 | struct xhci_virt_ep *ep, int *status, bool skip) | |
2023 | { | |
2024 | struct xhci_virt_device *xdev; | |
2025 | struct xhci_ring *ep_ring; | |
2026 | unsigned int slot_id; | |
2027 | int ep_index; | |
2028 | struct urb *urb = NULL; | |
2029 | struct xhci_ep_ctx *ep_ctx; | |
2030 | int ret = 0; | |
8e51adcc | 2031 | struct urb_priv *urb_priv; |
4422da61 AX |
2032 | u32 trb_comp_code; |
2033 | ||
28ccd296 | 2034 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
4422da61 | 2035 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
2036 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
2037 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
4422da61 | 2038 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 2039 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
4422da61 AX |
2040 | |
2041 | if (skip) | |
2042 | goto td_cleanup; | |
2043 | ||
2044 | if (trb_comp_code == COMP_STOP_INVAL || | |
2045 | trb_comp_code == COMP_STOP) { | |
2046 | /* The Endpoint Stop Command completion will take care of any | |
2047 | * stopped TDs. A stopped TD may be restarted, so don't update | |
2048 | * the ring dequeue pointer or take this TD off any lists yet. | |
2049 | */ | |
2050 | ep->stopped_td = td; | |
4422da61 AX |
2051 | return 0; |
2052 | } else { | |
2053 | if (trb_comp_code == COMP_STALL) { | |
2054 | /* The transfer is completed from the driver's | |
2055 | * perspective, but we need to issue a set dequeue | |
2056 | * command for this stalled endpoint to move the dequeue | |
2057 | * pointer past the TD. We can't do that here because | |
2058 | * the halt condition must be cleared first. Let the | |
2059 | * USB class driver clear the stall later. | |
2060 | */ | |
2061 | ep->stopped_td = td; | |
4422da61 AX |
2062 | ep->stopped_stream = ep_ring->stream_id; |
2063 | } else if (xhci_requires_manual_halt_cleanup(xhci, | |
2064 | ep_ctx, trb_comp_code)) { | |
2065 | /* Other types of errors halt the endpoint, but the | |
2066 | * class driver doesn't call usb_reset_endpoint() unless | |
2067 | * the error is -EPIPE. Clear the halted status in the | |
2068 | * xHCI hardware manually. | |
2069 | */ | |
2070 | xhci_cleanup_halted_endpoint(xhci, | |
2071 | slot_id, ep_index, ep_ring->stream_id, | |
2072 | td, event_trb); | |
2073 | } else { | |
2074 | /* Update ring dequeue pointer */ | |
2075 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
2076 | inc_deq(xhci, ep_ring); |
2077 | inc_deq(xhci, ep_ring); | |
4422da61 AX |
2078 | } |
2079 | ||
2080 | td_cleanup: | |
2081 | /* Clean up the endpoint's TD list */ | |
2082 | urb = td->urb; | |
8e51adcc | 2083 | urb_priv = urb->hcpriv; |
4422da61 AX |
2084 | |
2085 | /* Do one last check of the actual transfer length. | |
2086 | * If the host controller said we transferred more data than | |
2087 | * the buffer length, urb->actual_length will be a very big | |
2088 | * number (since it's unsigned). Play it safe and say we didn't | |
2089 | * transfer anything. | |
2090 | */ | |
2091 | if (urb->actual_length > urb->transfer_buffer_length) { | |
2092 | xhci_warn(xhci, "URB transfer length is wrong, " | |
2093 | "xHC issue? req. len = %u, " | |
2094 | "act. len = %u\n", | |
2095 | urb->transfer_buffer_length, | |
2096 | urb->actual_length); | |
2097 | urb->actual_length = 0; | |
2098 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2099 | *status = -EREMOTEIO; | |
2100 | else | |
2101 | *status = 0; | |
2102 | } | |
585df1d9 | 2103 | list_del_init(&td->td_list); |
4422da61 AX |
2104 | /* Was this TD slated to be cancelled but completed anyway? */ |
2105 | if (!list_empty(&td->cancelled_td_list)) | |
585df1d9 | 2106 | list_del_init(&td->cancelled_td_list); |
4422da61 | 2107 | |
8e51adcc AX |
2108 | urb_priv->td_cnt++; |
2109 | /* Giveback the urb when all the tds are completed */ | |
c41136b0 | 2110 | if (urb_priv->td_cnt == urb_priv->length) { |
8e51adcc | 2111 | ret = 1; |
c41136b0 AX |
2112 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
2113 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
2114 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs | |
2115 | == 0) { | |
2116 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
2117 | usb_amd_quirk_pll_enable(); | |
2118 | } | |
2119 | } | |
2120 | } | |
4422da61 AX |
2121 | } |
2122 | ||
2123 | return ret; | |
2124 | } | |
2125 | ||
8af56be1 AX |
2126 | /* |
2127 | * Process control tds, update urb status and actual_length. | |
2128 | */ | |
2129 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
2130 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
2131 | struct xhci_virt_ep *ep, int *status) | |
2132 | { | |
2133 | struct xhci_virt_device *xdev; | |
2134 | struct xhci_ring *ep_ring; | |
2135 | unsigned int slot_id; | |
2136 | int ep_index; | |
2137 | struct xhci_ep_ctx *ep_ctx; | |
2138 | u32 trb_comp_code; | |
2139 | ||
28ccd296 | 2140 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
8af56be1 | 2141 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
2142 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
2143 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
8af56be1 | 2144 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 2145 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
8af56be1 | 2146 | |
8af56be1 AX |
2147 | switch (trb_comp_code) { |
2148 | case COMP_SUCCESS: | |
2149 | if (event_trb == ep_ring->dequeue) { | |
2150 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB " | |
2151 | "without IOC set??\n"); | |
2152 | *status = -ESHUTDOWN; | |
2153 | } else if (event_trb != td->last_trb) { | |
2154 | xhci_warn(xhci, "WARN: Success on ctrl data TRB " | |
2155 | "without IOC set??\n"); | |
2156 | *status = -ESHUTDOWN; | |
2157 | } else { | |
8af56be1 AX |
2158 | *status = 0; |
2159 | } | |
2160 | break; | |
2161 | case COMP_SHORT_TX: | |
8af56be1 AX |
2162 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
2163 | *status = -EREMOTEIO; | |
2164 | else | |
2165 | *status = 0; | |
2166 | break; | |
3abeca99 SS |
2167 | case COMP_STOP_INVAL: |
2168 | case COMP_STOP: | |
2169 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
8af56be1 AX |
2170 | default: |
2171 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
2172 | ep_ctx, trb_comp_code)) | |
2173 | break; | |
2174 | xhci_dbg(xhci, "TRB error code %u, " | |
2175 | "halted endpoint index = %u\n", | |
2176 | trb_comp_code, ep_index); | |
2177 | /* else fall through */ | |
2178 | case COMP_STALL: | |
2179 | /* Did we transfer part of the data (middle) phase? */ | |
2180 | if (event_trb != ep_ring->dequeue && | |
2181 | event_trb != td->last_trb) | |
2182 | td->urb->actual_length = | |
1c11a172 VG |
2183 | td->urb->transfer_buffer_length - |
2184 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
8af56be1 AX |
2185 | else |
2186 | td->urb->actual_length = 0; | |
2187 | ||
2188 | xhci_cleanup_halted_endpoint(xhci, | |
2189 | slot_id, ep_index, 0, td, event_trb); | |
2190 | return finish_td(xhci, td, event_trb, event, ep, status, true); | |
2191 | } | |
2192 | /* | |
2193 | * Did we transfer any data, despite the errors that might have | |
2194 | * happened? I.e. did we get past the setup stage? | |
2195 | */ | |
2196 | if (event_trb != ep_ring->dequeue) { | |
2197 | /* The event was for the status stage */ | |
2198 | if (event_trb == td->last_trb) { | |
2199 | if (td->urb->actual_length != 0) { | |
2200 | /* Don't overwrite a previously set error code | |
2201 | */ | |
2202 | if ((*status == -EINPROGRESS || *status == 0) && | |
2203 | (td->urb->transfer_flags | |
2204 | & URB_SHORT_NOT_OK)) | |
2205 | /* Did we already see a short data | |
2206 | * stage? */ | |
2207 | *status = -EREMOTEIO; | |
2208 | } else { | |
2209 | td->urb->actual_length = | |
2210 | td->urb->transfer_buffer_length; | |
2211 | } | |
2212 | } else { | |
2213 | /* Maybe the event was for the data stage? */ | |
3abeca99 SS |
2214 | td->urb->actual_length = |
2215 | td->urb->transfer_buffer_length - | |
1c11a172 | 2216 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
3abeca99 SS |
2217 | xhci_dbg(xhci, "Waiting for status " |
2218 | "stage event\n"); | |
2219 | return 0; | |
8af56be1 AX |
2220 | } |
2221 | } | |
2222 | ||
2223 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
2224 | } | |
2225 | ||
04e51901 AX |
2226 | /* |
2227 | * Process isochronous tds, update urb packet status and actual_length. | |
2228 | */ | |
2229 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
2230 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
2231 | struct xhci_virt_ep *ep, int *status) | |
2232 | { | |
2233 | struct xhci_ring *ep_ring; | |
2234 | struct urb_priv *urb_priv; | |
2235 | int idx; | |
2236 | int len = 0; | |
04e51901 AX |
2237 | union xhci_trb *cur_trb; |
2238 | struct xhci_segment *cur_seg; | |
926008c9 | 2239 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 2240 | u32 trb_comp_code; |
926008c9 | 2241 | bool skip_td = false; |
04e51901 | 2242 | |
28ccd296 ME |
2243 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2244 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
04e51901 AX |
2245 | urb_priv = td->urb->hcpriv; |
2246 | idx = urb_priv->td_cnt; | |
926008c9 | 2247 | frame = &td->urb->iso_frame_desc[idx]; |
04e51901 | 2248 | |
926008c9 DT |
2249 | /* handle completion code */ |
2250 | switch (trb_comp_code) { | |
2251 | case COMP_SUCCESS: | |
1c11a172 | 2252 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) { |
1530bbc6 SS |
2253 | frame->status = 0; |
2254 | break; | |
2255 | } | |
2256 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) | |
2257 | trb_comp_code = COMP_SHORT_TX; | |
926008c9 DT |
2258 | case COMP_SHORT_TX: |
2259 | frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
2260 | -EREMOTEIO : 0; | |
2261 | break; | |
2262 | case COMP_BW_OVER: | |
2263 | frame->status = -ECOMM; | |
2264 | skip_td = true; | |
2265 | break; | |
2266 | case COMP_BUFF_OVER: | |
2267 | case COMP_BABBLE: | |
2268 | frame->status = -EOVERFLOW; | |
2269 | skip_td = true; | |
2270 | break; | |
f6ba6fe2 | 2271 | case COMP_DEV_ERR: |
926008c9 | 2272 | case COMP_STALL: |
9c745995 | 2273 | case COMP_TX_ERR: |
926008c9 DT |
2274 | frame->status = -EPROTO; |
2275 | skip_td = true; | |
2276 | break; | |
2277 | case COMP_STOP: | |
2278 | case COMP_STOP_INVAL: | |
2279 | break; | |
2280 | default: | |
2281 | frame->status = -1; | |
2282 | break; | |
04e51901 AX |
2283 | } |
2284 | ||
926008c9 DT |
2285 | if (trb_comp_code == COMP_SUCCESS || skip_td) { |
2286 | frame->actual_length = frame->length; | |
2287 | td->urb->actual_length += frame->length; | |
04e51901 AX |
2288 | } else { |
2289 | for (cur_trb = ep_ring->dequeue, | |
2290 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; | |
2291 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 ME |
2292 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
2293 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) | |
28ccd296 | 2294 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
04e51901 | 2295 | } |
28ccd296 | 2296 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1c11a172 | 2297 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
04e51901 AX |
2298 | |
2299 | if (trb_comp_code != COMP_STOP_INVAL) { | |
926008c9 | 2300 | frame->actual_length = len; |
04e51901 AX |
2301 | td->urb->actual_length += len; |
2302 | } | |
2303 | } | |
2304 | ||
04e51901 AX |
2305 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
2306 | } | |
2307 | ||
926008c9 DT |
2308 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
2309 | struct xhci_transfer_event *event, | |
2310 | struct xhci_virt_ep *ep, int *status) | |
2311 | { | |
2312 | struct xhci_ring *ep_ring; | |
2313 | struct urb_priv *urb_priv; | |
2314 | struct usb_iso_packet_descriptor *frame; | |
2315 | int idx; | |
2316 | ||
f6975314 | 2317 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
926008c9 DT |
2318 | urb_priv = td->urb->hcpriv; |
2319 | idx = urb_priv->td_cnt; | |
2320 | frame = &td->urb->iso_frame_desc[idx]; | |
2321 | ||
b3df3f9c | 2322 | /* The transfer is partly done. */ |
926008c9 DT |
2323 | frame->status = -EXDEV; |
2324 | ||
2325 | /* calc actual length */ | |
2326 | frame->actual_length = 0; | |
2327 | ||
2328 | /* Update ring dequeue pointer */ | |
2329 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
2330 | inc_deq(xhci, ep_ring); |
2331 | inc_deq(xhci, ep_ring); | |
926008c9 DT |
2332 | |
2333 | return finish_td(xhci, td, NULL, event, ep, status, true); | |
2334 | } | |
2335 | ||
22405ed2 AX |
2336 | /* |
2337 | * Process bulk and interrupt tds, update urb status and actual_length. | |
2338 | */ | |
2339 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
2340 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
2341 | struct xhci_virt_ep *ep, int *status) | |
2342 | { | |
2343 | struct xhci_ring *ep_ring; | |
2344 | union xhci_trb *cur_trb; | |
2345 | struct xhci_segment *cur_seg; | |
2346 | u32 trb_comp_code; | |
2347 | ||
28ccd296 ME |
2348 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2349 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
22405ed2 AX |
2350 | |
2351 | switch (trb_comp_code) { | |
2352 | case COMP_SUCCESS: | |
2353 | /* Double check that the HW transferred everything. */ | |
1530bbc6 | 2354 | if (event_trb != td->last_trb || |
1c11a172 | 2355 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
22405ed2 AX |
2356 | xhci_warn(xhci, "WARN Successful completion " |
2357 | "on short TX\n"); | |
2358 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2359 | *status = -EREMOTEIO; | |
2360 | else | |
2361 | *status = 0; | |
1530bbc6 SS |
2362 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) |
2363 | trb_comp_code = COMP_SHORT_TX; | |
22405ed2 | 2364 | } else { |
22405ed2 AX |
2365 | *status = 0; |
2366 | } | |
2367 | break; | |
2368 | case COMP_SHORT_TX: | |
2369 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2370 | *status = -EREMOTEIO; | |
2371 | else | |
2372 | *status = 0; | |
2373 | break; | |
2374 | default: | |
2375 | /* Others already handled above */ | |
2376 | break; | |
2377 | } | |
f444ff27 SS |
2378 | if (trb_comp_code == COMP_SHORT_TX) |
2379 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, " | |
2380 | "%d bytes untransferred\n", | |
2381 | td->urb->ep->desc.bEndpointAddress, | |
2382 | td->urb->transfer_buffer_length, | |
1c11a172 | 2383 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
22405ed2 AX |
2384 | /* Fast path - was this the last TRB in the TD for this URB? */ |
2385 | if (event_trb == td->last_trb) { | |
1c11a172 | 2386 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
22405ed2 AX |
2387 | td->urb->actual_length = |
2388 | td->urb->transfer_buffer_length - | |
1c11a172 | 2389 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
22405ed2 AX |
2390 | if (td->urb->transfer_buffer_length < |
2391 | td->urb->actual_length) { | |
2392 | xhci_warn(xhci, "HC gave bad length " | |
2393 | "of %d bytes left\n", | |
1c11a172 | 2394 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
22405ed2 AX |
2395 | td->urb->actual_length = 0; |
2396 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2397 | *status = -EREMOTEIO; | |
2398 | else | |
2399 | *status = 0; | |
2400 | } | |
2401 | /* Don't overwrite a previously set error code */ | |
2402 | if (*status == -EINPROGRESS) { | |
2403 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2404 | *status = -EREMOTEIO; | |
2405 | else | |
2406 | *status = 0; | |
2407 | } | |
2408 | } else { | |
2409 | td->urb->actual_length = | |
2410 | td->urb->transfer_buffer_length; | |
2411 | /* Ignore a short packet completion if the | |
2412 | * untransferred length was zero. | |
2413 | */ | |
2414 | if (*status == -EREMOTEIO) | |
2415 | *status = 0; | |
2416 | } | |
2417 | } else { | |
2418 | /* Slow path - walk the list, starting from the dequeue | |
2419 | * pointer, to get the actual length transferred. | |
2420 | */ | |
2421 | td->urb->actual_length = 0; | |
2422 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; | |
2423 | cur_trb != event_trb; | |
2424 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 ME |
2425 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
2426 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) | |
22405ed2 | 2427 | td->urb->actual_length += |
28ccd296 | 2428 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
22405ed2 AX |
2429 | } |
2430 | /* If the ring didn't stop on a Link or No-op TRB, add | |
2431 | * in the actual bytes transferred from the Normal TRB | |
2432 | */ | |
2433 | if (trb_comp_code != COMP_STOP_INVAL) | |
2434 | td->urb->actual_length += | |
28ccd296 | 2435 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1c11a172 | 2436 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
22405ed2 AX |
2437 | } |
2438 | ||
2439 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
2440 | } | |
2441 | ||
d0e96f5a SS |
2442 | /* |
2443 | * If this function returns an error condition, it means it got a Transfer | |
2444 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2445 | * At this point, the host controller is probably hosed and should be reset. | |
2446 | */ | |
2447 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2448 | struct xhci_transfer_event *event) | |
ed384bd3 FB |
2449 | __releases(&xhci->lock) |
2450 | __acquires(&xhci->lock) | |
d0e96f5a SS |
2451 | { |
2452 | struct xhci_virt_device *xdev; | |
63a0d9ab | 2453 | struct xhci_virt_ep *ep; |
d0e96f5a | 2454 | struct xhci_ring *ep_ring; |
82d1009f | 2455 | unsigned int slot_id; |
d0e96f5a | 2456 | int ep_index; |
326b4810 | 2457 | struct xhci_td *td = NULL; |
d0e96f5a SS |
2458 | dma_addr_t event_dma; |
2459 | struct xhci_segment *event_seg; | |
2460 | union xhci_trb *event_trb; | |
326b4810 | 2461 | struct urb *urb = NULL; |
d0e96f5a | 2462 | int status = -EINPROGRESS; |
8e51adcc | 2463 | struct urb_priv *urb_priv; |
d115b048 | 2464 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2465 | struct list_head *tmp; |
66d1eebc | 2466 | u32 trb_comp_code; |
4422da61 | 2467 | int ret = 0; |
c2d7b49f | 2468 | int td_num = 0; |
d0e96f5a | 2469 | |
28ccd296 | 2470 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
82d1009f | 2471 | xdev = xhci->devs[slot_id]; |
d0e96f5a SS |
2472 | if (!xdev) { |
2473 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | |
9258c0b2 | 2474 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2475 | (unsigned long long) xhci_trb_virt_to_dma( |
2476 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2477 | xhci->event_ring->dequeue), |
2478 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2479 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2480 | le32_to_cpu(event->transfer_len), | |
2481 | le32_to_cpu(event->flags)); | |
2482 | xhci_dbg(xhci, "Event ring:\n"); | |
2483 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2484 | return -ENODEV; |
2485 | } | |
2486 | ||
2487 | /* Endpoint ID is 1 based, our index is zero based */ | |
28ccd296 | 2488 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
63a0d9ab | 2489 | ep = &xdev->eps[ep_index]; |
28ccd296 | 2490 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
d115b048 | 2491 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
986a92d4 | 2492 | if (!ep_ring || |
28ccd296 ME |
2493 | (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == |
2494 | EP_STATE_DISABLED) { | |
e9df17eb SS |
2495 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
2496 | "or incorrect stream ring\n"); | |
9258c0b2 | 2497 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2498 | (unsigned long long) xhci_trb_virt_to_dma( |
2499 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2500 | xhci->event_ring->dequeue), |
2501 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2502 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2503 | le32_to_cpu(event->transfer_len), | |
2504 | le32_to_cpu(event->flags)); | |
2505 | xhci_dbg(xhci, "Event ring:\n"); | |
2506 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2507 | return -ENODEV; |
2508 | } | |
2509 | ||
c2d7b49f AX |
2510 | /* Count current td numbers if ep->skip is set */ |
2511 | if (ep->skip) { | |
2512 | list_for_each(tmp, &ep_ring->td_list) | |
2513 | td_num++; | |
2514 | } | |
2515 | ||
28ccd296 ME |
2516 | event_dma = le64_to_cpu(event->buffer); |
2517 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
986a92d4 | 2518 | /* Look for common error cases */ |
66d1eebc | 2519 | switch (trb_comp_code) { |
b10de142 SS |
2520 | /* Skip codes that require special handling depending on |
2521 | * transfer type | |
2522 | */ | |
2523 | case COMP_SUCCESS: | |
1c11a172 | 2524 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
1530bbc6 SS |
2525 | break; |
2526 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2527 | trb_comp_code = COMP_SHORT_TX; | |
2528 | else | |
8202ce2e SS |
2529 | xhci_warn_ratelimited(xhci, |
2530 | "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n"); | |
b10de142 SS |
2531 | case COMP_SHORT_TX: |
2532 | break; | |
ae636747 SS |
2533 | case COMP_STOP: |
2534 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); | |
2535 | break; | |
2536 | case COMP_STOP_INVAL: | |
2537 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); | |
2538 | break; | |
b10de142 | 2539 | case COMP_STALL: |
2a9227a5 | 2540 | xhci_dbg(xhci, "Stalled endpoint\n"); |
63a0d9ab | 2541 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
2542 | status = -EPIPE; |
2543 | break; | |
2544 | case COMP_TRB_ERR: | |
2545 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); | |
2546 | status = -EILSEQ; | |
2547 | break; | |
ec74e403 | 2548 | case COMP_SPLIT_ERR: |
b10de142 | 2549 | case COMP_TX_ERR: |
2a9227a5 | 2550 | xhci_dbg(xhci, "Transfer error on endpoint\n"); |
b10de142 SS |
2551 | status = -EPROTO; |
2552 | break; | |
4a73143c | 2553 | case COMP_BABBLE: |
2a9227a5 | 2554 | xhci_dbg(xhci, "Babble error on endpoint\n"); |
4a73143c SS |
2555 | status = -EOVERFLOW; |
2556 | break; | |
b10de142 SS |
2557 | case COMP_DB_ERR: |
2558 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); | |
2559 | status = -ENOSR; | |
2560 | break; | |
986a92d4 AX |
2561 | case COMP_BW_OVER: |
2562 | xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); | |
2563 | break; | |
2564 | case COMP_BUFF_OVER: | |
2565 | xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); | |
2566 | break; | |
2567 | case COMP_UNDERRUN: | |
2568 | /* | |
2569 | * When the Isoch ring is empty, the xHC will generate | |
2570 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2571 | * Underrun Event for OUT Isoch endpoint. | |
2572 | */ | |
2573 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2574 | if (!list_empty(&ep_ring->td_list)) | |
2575 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2576 | "still with TDs queued?\n", | |
28ccd296 ME |
2577 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2578 | ep_index); | |
986a92d4 AX |
2579 | goto cleanup; |
2580 | case COMP_OVERRUN: | |
2581 | xhci_dbg(xhci, "overrun event on endpoint\n"); | |
2582 | if (!list_empty(&ep_ring->td_list)) | |
2583 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2584 | "still with TDs queued?\n", | |
28ccd296 ME |
2585 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2586 | ep_index); | |
986a92d4 | 2587 | goto cleanup; |
f6ba6fe2 AH |
2588 | case COMP_DEV_ERR: |
2589 | xhci_warn(xhci, "WARN: detect an incompatible device"); | |
2590 | status = -EPROTO; | |
2591 | break; | |
d18240db AX |
2592 | case COMP_MISSED_INT: |
2593 | /* | |
2594 | * When encounter missed service error, one or more isoc tds | |
2595 | * may be missed by xHC. | |
2596 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2597 | * short transfer when process the ep_ring next time. | |
2598 | */ | |
2599 | ep->skip = true; | |
2600 | xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); | |
2601 | goto cleanup; | |
b10de142 | 2602 | default: |
b45b5069 | 2603 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2604 | status = 0; |
2605 | break; | |
2606 | } | |
986a92d4 AX |
2607 | xhci_warn(xhci, "ERROR Unknown event condition, HC probably " |
2608 | "busted\n"); | |
2609 | goto cleanup; | |
2610 | } | |
2611 | ||
d18240db AX |
2612 | do { |
2613 | /* This TRB should be in the TD at the head of this ring's | |
2614 | * TD list. | |
2615 | */ | |
2616 | if (list_empty(&ep_ring->td_list)) { | |
a83d6755 SS |
2617 | /* |
2618 | * A stopped endpoint may generate an extra completion | |
2619 | * event if the device was suspended. Don't print | |
2620 | * warnings. | |
2621 | */ | |
2622 | if (!(trb_comp_code == COMP_STOP || | |
2623 | trb_comp_code == COMP_STOP_INVAL)) { | |
2624 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", | |
2625 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), | |
2626 | ep_index); | |
2627 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", | |
2628 | (le32_to_cpu(event->flags) & | |
2629 | TRB_TYPE_BITMASK)>>10); | |
2630 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); | |
2631 | } | |
d18240db AX |
2632 | if (ep->skip) { |
2633 | ep->skip = false; | |
2634 | xhci_dbg(xhci, "td_list is empty while skip " | |
2635 | "flag set. Clear skip flag.\n"); | |
2636 | } | |
2637 | ret = 0; | |
2638 | goto cleanup; | |
2639 | } | |
986a92d4 | 2640 | |
c2d7b49f AX |
2641 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2642 | if (ep->skip && td_num == 0) { | |
2643 | ep->skip = false; | |
2644 | xhci_dbg(xhci, "All tds on the ep_ring skipped. " | |
2645 | "Clear skip flag.\n"); | |
2646 | ret = 0; | |
2647 | goto cleanup; | |
2648 | } | |
2649 | ||
d18240db | 2650 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
c2d7b49f AX |
2651 | if (ep->skip) |
2652 | td_num--; | |
926008c9 | 2653 | |
d18240db AX |
2654 | /* Is this a TRB in the currently executing TD? */ |
2655 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, | |
2656 | td->last_trb, event_dma); | |
e1cf486d AH |
2657 | |
2658 | /* | |
2659 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2660 | * is not in the current TD pointed by ep_ring->dequeue because | |
2661 | * that the hardware dequeue pointer still at the previous TRB | |
2662 | * of the current TD. The previous TRB maybe a Link TD or the | |
2663 | * last TRB of the previous TD. The command completion handle | |
2664 | * will take care the rest. | |
2665 | */ | |
2666 | if (!event_seg && trb_comp_code == COMP_STOP_INVAL) { | |
2667 | ret = 0; | |
2668 | goto cleanup; | |
2669 | } | |
2670 | ||
926008c9 DT |
2671 | if (!event_seg) { |
2672 | if (!ep->skip || | |
2673 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2674 | /* Some host controllers give a spurious |
2675 | * successful event after a short transfer. | |
2676 | * Ignore it. | |
2677 | */ | |
ddba5cd0 | 2678 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
ad808333 SS |
2679 | ep_ring->last_td_was_short) { |
2680 | ep_ring->last_td_was_short = false; | |
2681 | ret = 0; | |
2682 | goto cleanup; | |
2683 | } | |
926008c9 DT |
2684 | /* HC is busted, give up! */ |
2685 | xhci_err(xhci, | |
2686 | "ERROR Transfer event TRB DMA ptr not " | |
2687 | "part of current TD\n"); | |
2688 | return -ESHUTDOWN; | |
2689 | } | |
2690 | ||
2691 | ret = skip_isoc_td(xhci, td, event, ep, &status); | |
2692 | goto cleanup; | |
2693 | } | |
ad808333 SS |
2694 | if (trb_comp_code == COMP_SHORT_TX) |
2695 | ep_ring->last_td_was_short = true; | |
2696 | else | |
2697 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2698 | |
2699 | if (ep->skip) { | |
d18240db AX |
2700 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); |
2701 | ep->skip = false; | |
2702 | } | |
678539cf | 2703 | |
926008c9 DT |
2704 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / |
2705 | sizeof(*event_trb)]; | |
2706 | /* | |
2707 | * No-op TRB should not trigger interrupts. | |
2708 | * If event_trb is a no-op TRB, it means the | |
2709 | * corresponding TD has been cancelled. Just ignore | |
2710 | * the TD. | |
2711 | */ | |
f5960b69 | 2712 | if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) { |
926008c9 DT |
2713 | xhci_dbg(xhci, |
2714 | "event_trb is a no-op TRB. Skip it\n"); | |
2715 | goto cleanup; | |
d18240db | 2716 | } |
4422da61 | 2717 | |
d18240db AX |
2718 | /* Now update the urb's actual_length and give back to |
2719 | * the core | |
82d1009f | 2720 | */ |
d18240db AX |
2721 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
2722 | ret = process_ctrl_td(xhci, td, event_trb, event, ep, | |
2723 | &status); | |
04e51901 AX |
2724 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
2725 | ret = process_isoc_td(xhci, td, event_trb, event, ep, | |
2726 | &status); | |
d18240db AX |
2727 | else |
2728 | ret = process_bulk_intr_td(xhci, td, event_trb, event, | |
2729 | ep, &status); | |
2730 | ||
2731 | cleanup: | |
2732 | /* | |
2733 | * Do not update event ring dequeue pointer if ep->skip is set. | |
2734 | * Will roll back to continue process missed tds. | |
2735 | */ | |
2736 | if (trb_comp_code == COMP_MISSED_INT || !ep->skip) { | |
3b72fca0 | 2737 | inc_deq(xhci, xhci->event_ring); |
d18240db AX |
2738 | } |
2739 | ||
2740 | if (ret) { | |
2741 | urb = td->urb; | |
8e51adcc | 2742 | urb_priv = urb->hcpriv; |
d18240db AX |
2743 | /* Leave the TD around for the reset endpoint function |
2744 | * to use(but only if it's not a control endpoint, | |
2745 | * since we already queued the Set TR dequeue pointer | |
2746 | * command for stalled control endpoints). | |
2747 | */ | |
2748 | if (usb_endpoint_xfer_control(&urb->ep->desc) || | |
2749 | (trb_comp_code != COMP_STALL && | |
2750 | trb_comp_code != COMP_BABBLE)) | |
8e51adcc | 2751 | xhci_urb_free_priv(xhci, urb_priv); |
48c3375c AS |
2752 | else |
2753 | kfree(urb_priv); | |
d18240db | 2754 | |
214f76f7 | 2755 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
f444ff27 SS |
2756 | if ((urb->actual_length != urb->transfer_buffer_length && |
2757 | (urb->transfer_flags & | |
2758 | URB_SHORT_NOT_OK)) || | |
fd984d24 SS |
2759 | (status != 0 && |
2760 | !usb_endpoint_xfer_isoc(&urb->ep->desc))) | |
f444ff27 | 2761 | xhci_dbg(xhci, "Giveback URB %p, len = %d, " |
1949f9e2 | 2762 | "expected = %d, status = %d\n", |
f444ff27 SS |
2763 | urb, urb->actual_length, |
2764 | urb->transfer_buffer_length, | |
2765 | status); | |
d18240db | 2766 | spin_unlock(&xhci->lock); |
b3df3f9c SS |
2767 | /* EHCI, UHCI, and OHCI always unconditionally set the |
2768 | * urb->status of an isochronous endpoint to 0. | |
2769 | */ | |
2770 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
2771 | status = 0; | |
214f76f7 | 2772 | usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); |
d18240db AX |
2773 | spin_lock(&xhci->lock); |
2774 | } | |
2775 | ||
2776 | /* | |
2777 | * If ep->skip is set, it means there are missed tds on the | |
2778 | * endpoint ring need to take care of. | |
2779 | * Process them as short transfer until reach the td pointed by | |
2780 | * the event. | |
2781 | */ | |
2782 | } while (ep->skip && trb_comp_code != COMP_MISSED_INT); | |
2783 | ||
d0e96f5a SS |
2784 | return 0; |
2785 | } | |
2786 | ||
0f2a7930 SS |
2787 | /* |
2788 | * This function handles all OS-owned events on the event ring. It may drop | |
2789 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2790 | * Returns >0 for "possibly more events to process" (caller should call again), |
2791 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2792 | */ |
9dee9a21 | 2793 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2794 | { |
2795 | union xhci_trb *event; | |
0f2a7930 | 2796 | int update_ptrs = 1; |
d0e96f5a | 2797 | int ret; |
7f84eef0 SS |
2798 | |
2799 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { | |
2800 | xhci->error_bitmask |= 1 << 1; | |
9dee9a21 | 2801 | return 0; |
7f84eef0 SS |
2802 | } |
2803 | ||
2804 | event = xhci->event_ring->dequeue; | |
2805 | /* Does the HC or OS own the TRB? */ | |
28ccd296 ME |
2806 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
2807 | xhci->event_ring->cycle_state) { | |
7f84eef0 | 2808 | xhci->error_bitmask |= 1 << 2; |
9dee9a21 | 2809 | return 0; |
7f84eef0 SS |
2810 | } |
2811 | ||
92a3da41 ME |
2812 | /* |
2813 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2814 | * speculative reads of the event's flags/data below. | |
2815 | */ | |
2816 | rmb(); | |
0f2a7930 | 2817 | /* FIXME: Handle more event types. */ |
28ccd296 | 2818 | switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { |
7f84eef0 SS |
2819 | case TRB_TYPE(TRB_COMPLETION): |
2820 | handle_cmd_completion(xhci, &event->event_cmd); | |
2821 | break; | |
0f2a7930 SS |
2822 | case TRB_TYPE(TRB_PORT_STATUS): |
2823 | handle_port_status(xhci, event); | |
2824 | update_ptrs = 0; | |
2825 | break; | |
d0e96f5a SS |
2826 | case TRB_TYPE(TRB_TRANSFER): |
2827 | ret = handle_tx_event(xhci, &event->trans_event); | |
2828 | if (ret < 0) | |
2829 | xhci->error_bitmask |= 1 << 9; | |
2830 | else | |
2831 | update_ptrs = 0; | |
2832 | break; | |
623bef9e SS |
2833 | case TRB_TYPE(TRB_DEV_NOTE): |
2834 | handle_device_notification(xhci, event); | |
2835 | break; | |
7f84eef0 | 2836 | default: |
28ccd296 ME |
2837 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2838 | TRB_TYPE(48)) | |
0238634d SS |
2839 | handle_vendor_event(xhci, event); |
2840 | else | |
2841 | xhci->error_bitmask |= 1 << 3; | |
7f84eef0 | 2842 | } |
6f5165cf SS |
2843 | /* Any of the above functions may drop and re-acquire the lock, so check |
2844 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2845 | */ | |
2846 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2847 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2848 | "event handler.\n"); | |
9dee9a21 | 2849 | return 0; |
6f5165cf | 2850 | } |
7f84eef0 | 2851 | |
c06d68b8 SS |
2852 | if (update_ptrs) |
2853 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 2854 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 2855 | |
9dee9a21 ME |
2856 | /* Are there more items on the event ring? Caller will call us again to |
2857 | * check. | |
2858 | */ | |
2859 | return 1; | |
7f84eef0 | 2860 | } |
9032cd52 SS |
2861 | |
2862 | /* | |
2863 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2864 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2865 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2866 | */ | |
2867 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2868 | { | |
2869 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c21599a3 | 2870 | u32 status; |
bda53145 | 2871 | u64 temp_64; |
c06d68b8 SS |
2872 | union xhci_trb *event_ring_deq; |
2873 | dma_addr_t deq; | |
9032cd52 SS |
2874 | |
2875 | spin_lock(&xhci->lock); | |
9032cd52 | 2876 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
b0ba9720 | 2877 | status = readl(&xhci->op_regs->status); |
c21599a3 | 2878 | if (status == 0xffffffff) |
9032cd52 SS |
2879 | goto hw_died; |
2880 | ||
c21599a3 | 2881 | if (!(status & STS_EINT)) { |
9032cd52 | 2882 | spin_unlock(&xhci->lock); |
9032cd52 SS |
2883 | return IRQ_NONE; |
2884 | } | |
27e0dd4d | 2885 | if (status & STS_FATAL) { |
9032cd52 SS |
2886 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2887 | xhci_halt(xhci); | |
2888 | hw_died: | |
9032cd52 SS |
2889 | spin_unlock(&xhci->lock); |
2890 | return -ESHUTDOWN; | |
2891 | } | |
2892 | ||
bda53145 SS |
2893 | /* |
2894 | * Clear the op reg interrupt status first, | |
2895 | * so we can receive interrupts from other MSI-X interrupters. | |
2896 | * Write 1 to clear the interrupt status. | |
2897 | */ | |
27e0dd4d | 2898 | status |= STS_EINT; |
204b7793 | 2899 | writel(status, &xhci->op_regs->status); |
bda53145 SS |
2900 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
2901 | /* Clear the MSI-X event interrupt status */ | |
2902 | ||
cd70469d | 2903 | if (hcd->irq) { |
c21599a3 SS |
2904 | u32 irq_pending; |
2905 | /* Acknowledge the PCI interrupt */ | |
b0ba9720 | 2906 | irq_pending = readl(&xhci->ir_set->irq_pending); |
4e833c0b | 2907 | irq_pending |= IMAN_IP; |
204b7793 | 2908 | writel(irq_pending, &xhci->ir_set->irq_pending); |
c21599a3 | 2909 | } |
bda53145 | 2910 | |
c06d68b8 | 2911 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
bda53145 SS |
2912 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2913 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2914 | /* Clear the event handler busy flag (RW1C); |
2915 | * the event ring should be empty. | |
bda53145 | 2916 | */ |
f7b2e403 | 2917 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
477632df SS |
2918 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
2919 | &xhci->ir_set->erst_dequeue); | |
c06d68b8 SS |
2920 | spin_unlock(&xhci->lock); |
2921 | ||
2922 | return IRQ_HANDLED; | |
2923 | } | |
2924 | ||
2925 | event_ring_deq = xhci->event_ring->dequeue; | |
2926 | /* FIXME this should be a delayed service routine | |
2927 | * that clears the EHB. | |
2928 | */ | |
9dee9a21 | 2929 | while (xhci_handle_event(xhci) > 0) {} |
bda53145 | 2930 | |
f7b2e403 | 2931 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2932 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2933 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2934 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2935 | xhci->event_ring->dequeue); | |
2936 | if (deq == 0) | |
2937 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2938 | "ring dequeue ptr.\n"); | |
2939 | /* Update HC event ring dequeue pointer */ | |
2940 | temp_64 &= ERST_PTR_MASK; | |
2941 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2942 | } | |
2943 | ||
2944 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2945 | temp_64 |= ERST_EHB; | |
477632df | 2946 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
c06d68b8 | 2947 | |
9032cd52 SS |
2948 | spin_unlock(&xhci->lock); |
2949 | ||
2950 | return IRQ_HANDLED; | |
2951 | } | |
2952 | ||
851ec164 | 2953 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
9032cd52 | 2954 | { |
968b822c | 2955 | return xhci_irq(hcd); |
9032cd52 | 2956 | } |
7f84eef0 | 2957 | |
d0e96f5a SS |
2958 | /**** Endpoint Ring Operations ****/ |
2959 | ||
7f84eef0 SS |
2960 | /* |
2961 | * Generic function for queueing a TRB on a ring. | |
2962 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2963 | * |
2964 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2965 | * prepare_transfer()? | |
7f84eef0 SS |
2966 | */ |
2967 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 2968 | bool more_trbs_coming, |
7f84eef0 SS |
2969 | u32 field1, u32 field2, u32 field3, u32 field4) |
2970 | { | |
2971 | struct xhci_generic_trb *trb; | |
2972 | ||
2973 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
2974 | trb->field[0] = cpu_to_le32(field1); |
2975 | trb->field[1] = cpu_to_le32(field2); | |
2976 | trb->field[2] = cpu_to_le32(field3); | |
2977 | trb->field[3] = cpu_to_le32(field4); | |
3b72fca0 | 2978 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
2979 | } |
2980 | ||
d0e96f5a SS |
2981 | /* |
2982 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2983 | * FIXME allocate segments if the ring is full. | |
2984 | */ | |
2985 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 2986 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 2987 | { |
8dfec614 AX |
2988 | unsigned int num_trbs_needed; |
2989 | ||
d0e96f5a | 2990 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
2991 | switch (ep_state) { |
2992 | case EP_STATE_DISABLED: | |
2993 | /* | |
2994 | * USB core changed config/interfaces without notifying us, | |
2995 | * or hardware is reporting the wrong state. | |
2996 | */ | |
2997 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2998 | return -ENOENT; | |
d0e96f5a | 2999 | case EP_STATE_ERROR: |
c92bcfa7 | 3000 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
3001 | /* FIXME event handling code for error needs to clear it */ |
3002 | /* XXX not sure if this should be -ENOENT or not */ | |
3003 | return -EINVAL; | |
c92bcfa7 SS |
3004 | case EP_STATE_HALTED: |
3005 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
3006 | case EP_STATE_STOPPED: |
3007 | case EP_STATE_RUNNING: | |
3008 | break; | |
3009 | default: | |
3010 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
3011 | /* | |
3012 | * FIXME issue Configure Endpoint command to try to get the HC | |
3013 | * back into a known state. | |
3014 | */ | |
3015 | return -EINVAL; | |
3016 | } | |
8dfec614 AX |
3017 | |
3018 | while (1) { | |
3d4b81ed SS |
3019 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
3020 | break; | |
8dfec614 AX |
3021 | |
3022 | if (ep_ring == xhci->cmd_ring) { | |
3023 | xhci_err(xhci, "Do not support expand command ring\n"); | |
3024 | return -ENOMEM; | |
3025 | } | |
3026 | ||
68ffb011 XR |
3027 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
3028 | "ERROR no room on ep ring, try ring expansion"); | |
8dfec614 AX |
3029 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
3030 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
3031 | mem_flags)) { | |
3032 | xhci_err(xhci, "Ring expansion failed\n"); | |
3033 | return -ENOMEM; | |
3034 | } | |
261fa12b | 3035 | } |
6c12db90 JY |
3036 | |
3037 | if (enqueue_is_link_trb(ep_ring)) { | |
3038 | struct xhci_ring *ring = ep_ring; | |
3039 | union xhci_trb *next; | |
6c12db90 | 3040 | |
6c12db90 JY |
3041 | next = ring->enqueue; |
3042 | ||
3043 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
7e393a83 AX |
3044 | /* If we're not dealing with 0.95 hardware or isoc rings |
3045 | * on AMD 0.96 host, clear the chain bit. | |
6c12db90 | 3046 | */ |
3b72fca0 AX |
3047 | if (!xhci_link_trb_quirk(xhci) && |
3048 | !(ring->type == TYPE_ISOC && | |
3049 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
28ccd296 | 3050 | next->link.control &= cpu_to_le32(~TRB_CHAIN); |
6c12db90 | 3051 | else |
28ccd296 | 3052 | next->link.control |= cpu_to_le32(TRB_CHAIN); |
6c12db90 JY |
3053 | |
3054 | wmb(); | |
f5960b69 | 3055 | next->link.control ^= cpu_to_le32(TRB_CYCLE); |
6c12db90 JY |
3056 | |
3057 | /* Toggle the cycle bit after the last ring segment. */ | |
3058 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
3059 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
6c12db90 JY |
3060 | } |
3061 | ring->enq_seg = ring->enq_seg->next; | |
3062 | ring->enqueue = ring->enq_seg->trbs; | |
3063 | next = ring->enqueue; | |
3064 | } | |
3065 | } | |
3066 | ||
d0e96f5a SS |
3067 | return 0; |
3068 | } | |
3069 | ||
23e3be11 | 3070 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
3071 | struct xhci_virt_device *xdev, |
3072 | unsigned int ep_index, | |
e9df17eb | 3073 | unsigned int stream_id, |
d0e96f5a SS |
3074 | unsigned int num_trbs, |
3075 | struct urb *urb, | |
8e51adcc | 3076 | unsigned int td_index, |
d0e96f5a SS |
3077 | gfp_t mem_flags) |
3078 | { | |
3079 | int ret; | |
8e51adcc AX |
3080 | struct urb_priv *urb_priv; |
3081 | struct xhci_td *td; | |
e9df17eb | 3082 | struct xhci_ring *ep_ring; |
d115b048 | 3083 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
3084 | |
3085 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
3086 | if (!ep_ring) { | |
3087 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
3088 | stream_id); | |
3089 | return -EINVAL; | |
3090 | } | |
3091 | ||
3092 | ret = prepare_ring(xhci, ep_ring, | |
28ccd296 | 3093 | le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3b72fca0 | 3094 | num_trbs, mem_flags); |
d0e96f5a SS |
3095 | if (ret) |
3096 | return ret; | |
d0e96f5a | 3097 | |
8e51adcc AX |
3098 | urb_priv = urb->hcpriv; |
3099 | td = urb_priv->td[td_index]; | |
3100 | ||
3101 | INIT_LIST_HEAD(&td->td_list); | |
3102 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
3103 | ||
3104 | if (td_index == 0) { | |
214f76f7 | 3105 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 3106 | if (unlikely(ret)) |
8e51adcc | 3107 | return ret; |
d0e96f5a SS |
3108 | } |
3109 | ||
8e51adcc | 3110 | td->urb = urb; |
d0e96f5a | 3111 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
3112 | list_add_tail(&td->td_list, &ep_ring->td_list); |
3113 | td->start_seg = ep_ring->enq_seg; | |
3114 | td->first_trb = ep_ring->enqueue; | |
3115 | ||
3116 | urb_priv->td[td_index] = td; | |
d0e96f5a SS |
3117 | |
3118 | return 0; | |
3119 | } | |
3120 | ||
23e3be11 | 3121 | static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) |
8a96c052 SS |
3122 | { |
3123 | int num_sgs, num_trbs, running_total, temp, i; | |
3124 | struct scatterlist *sg; | |
3125 | ||
3126 | sg = NULL; | |
bc677d5b | 3127 | num_sgs = urb->num_mapped_sgs; |
8a96c052 SS |
3128 | temp = urb->transfer_buffer_length; |
3129 | ||
8a96c052 | 3130 | num_trbs = 0; |
910f8d0c | 3131 | for_each_sg(urb->sg, sg, num_sgs, i) { |
8a96c052 SS |
3132 | unsigned int len = sg_dma_len(sg); |
3133 | ||
3134 | /* Scatter gather list entries may cross 64KB boundaries */ | |
3135 | running_total = TRB_MAX_BUFF_SIZE - | |
a2490187 | 3136 | (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 3137 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
8a96c052 SS |
3138 | if (running_total != 0) |
3139 | num_trbs++; | |
3140 | ||
3141 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
bcd2fde0 | 3142 | while (running_total < sg_dma_len(sg) && running_total < temp) { |
8a96c052 SS |
3143 | num_trbs++; |
3144 | running_total += TRB_MAX_BUFF_SIZE; | |
3145 | } | |
8a96c052 SS |
3146 | len = min_t(int, len, temp); |
3147 | temp -= len; | |
3148 | if (temp == 0) | |
3149 | break; | |
3150 | } | |
8a96c052 SS |
3151 | return num_trbs; |
3152 | } | |
3153 | ||
23e3be11 | 3154 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
8a96c052 SS |
3155 | { |
3156 | if (num_trbs != 0) | |
a2490187 | 3157 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " |
8a96c052 SS |
3158 | "TRBs, %d left\n", __func__, |
3159 | urb->ep->desc.bEndpointAddress, num_trbs); | |
3160 | if (running_total != urb->transfer_buffer_length) | |
a2490187 | 3161 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
3162 | "queued %#x (%d), asked for %#x (%d)\n", |
3163 | __func__, | |
3164 | urb->ep->desc.bEndpointAddress, | |
3165 | running_total, running_total, | |
3166 | urb->transfer_buffer_length, | |
3167 | urb->transfer_buffer_length); | |
3168 | } | |
3169 | ||
23e3be11 | 3170 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 3171 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 3172 | struct xhci_generic_trb *start_trb) |
8a96c052 | 3173 | { |
8a96c052 SS |
3174 | /* |
3175 | * Pass all the TRBs to the hardware at once and make sure this write | |
3176 | * isn't reordered. | |
3177 | */ | |
3178 | wmb(); | |
50f7b52a | 3179 | if (start_cycle) |
28ccd296 | 3180 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 3181 | else |
28ccd296 | 3182 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 3183 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
3184 | } |
3185 | ||
624defa1 SS |
3186 | /* |
3187 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
3188 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
3189 | * (comprised of sg list entries) can take several service intervals to | |
3190 | * transmit. | |
3191 | */ | |
3192 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3193 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3194 | { | |
3195 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, | |
3196 | xhci->devs[slot_id]->out_ctx, ep_index); | |
3197 | int xhci_interval; | |
3198 | int ep_interval; | |
3199 | ||
28ccd296 | 3200 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 SS |
3201 | ep_interval = urb->interval; |
3202 | /* Convert to microframes */ | |
3203 | if (urb->dev->speed == USB_SPEED_LOW || | |
3204 | urb->dev->speed == USB_SPEED_FULL) | |
3205 | ep_interval *= 8; | |
3206 | /* FIXME change this to a warning and a suggestion to use the new API | |
3207 | * to set the polling interval (once the API is added). | |
3208 | */ | |
3209 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3210 | dev_dbg_ratelimited(&urb->dev->dev, |
3211 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3212 | ep_interval, ep_interval == 1 ? "" : "s", | |
3213 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
624defa1 SS |
3214 | urb->interval = xhci_interval; |
3215 | /* Convert back to frames for LS/FS devices */ | |
3216 | if (urb->dev->speed == USB_SPEED_LOW || | |
3217 | urb->dev->speed == USB_SPEED_FULL) | |
3218 | urb->interval /= 8; | |
3219 | } | |
3fc8206d | 3220 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
3221 | } |
3222 | ||
04dd950d SS |
3223 | /* |
3224 | * The TD size is the number of bytes remaining in the TD (including this TRB), | |
3225 | * right shifted by 10. | |
3226 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
3227 | */ | |
3228 | static u32 xhci_td_remainder(unsigned int remainder) | |
3229 | { | |
3230 | u32 max = (1 << (21 - 17 + 1)) - 1; | |
3231 | ||
3232 | if ((remainder >> 10) >= max) | |
3233 | return max << 17; | |
3234 | else | |
3235 | return (remainder >> 10) << 17; | |
3236 | } | |
3237 | ||
4da6e6f2 | 3238 | /* |
4525c0a1 SS |
3239 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
3240 | * packets remaining in the TD (*not* including this TRB). | |
4da6e6f2 SS |
3241 | * |
3242 | * Total TD packet count = total_packet_count = | |
4525c0a1 | 3243 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
4da6e6f2 SS |
3244 | * |
3245 | * Packets transferred up to and including this TRB = packets_transferred = | |
3246 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
3247 | * | |
3248 | * TD size = total_packet_count - packets_transferred | |
3249 | * | |
3250 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
4525c0a1 | 3251 | * The last TRB in a TD must have the TD size set to zero. |
4da6e6f2 | 3252 | */ |
4da6e6f2 | 3253 | static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len, |
4525c0a1 SS |
3254 | unsigned int total_packet_count, struct urb *urb, |
3255 | unsigned int num_trbs_left) | |
4da6e6f2 SS |
3256 | { |
3257 | int packets_transferred; | |
3258 | ||
48df4a6f | 3259 | /* One TRB with a zero-length data packet. */ |
4525c0a1 | 3260 | if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0)) |
48df4a6f SS |
3261 | return 0; |
3262 | ||
4da6e6f2 SS |
3263 | /* All the TRB queueing functions don't count the current TRB in |
3264 | * running_total. | |
3265 | */ | |
3266 | packets_transferred = (running_total + trb_buff_len) / | |
f18f8ed2 | 3267 | GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); |
4da6e6f2 | 3268 | |
4525c0a1 SS |
3269 | if ((total_packet_count - packets_transferred) > 31) |
3270 | return 31 << 17; | |
3271 | return (total_packet_count - packets_transferred) << 17; | |
4da6e6f2 SS |
3272 | } |
3273 | ||
23e3be11 | 3274 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
8a96c052 SS |
3275 | struct urb *urb, int slot_id, unsigned int ep_index) |
3276 | { | |
3277 | struct xhci_ring *ep_ring; | |
3278 | unsigned int num_trbs; | |
8e51adcc | 3279 | struct urb_priv *urb_priv; |
8a96c052 SS |
3280 | struct xhci_td *td; |
3281 | struct scatterlist *sg; | |
3282 | int num_sgs; | |
3283 | int trb_buff_len, this_sg_len, running_total; | |
4da6e6f2 | 3284 | unsigned int total_packet_count; |
8a96c052 SS |
3285 | bool first_trb; |
3286 | u64 addr; | |
6cc30d85 | 3287 | bool more_trbs_coming; |
8a96c052 SS |
3288 | |
3289 | struct xhci_generic_trb *start_trb; | |
3290 | int start_cycle; | |
3291 | ||
e9df17eb SS |
3292 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3293 | if (!ep_ring) | |
3294 | return -EINVAL; | |
3295 | ||
8a96c052 | 3296 | num_trbs = count_sg_trbs_needed(xhci, urb); |
bc677d5b | 3297 | num_sgs = urb->num_mapped_sgs; |
4525c0a1 | 3298 | total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length, |
29cc8897 | 3299 | usb_endpoint_maxp(&urb->ep->desc)); |
8a96c052 | 3300 | |
23e3be11 | 3301 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 3302 | ep_index, urb->stream_id, |
3b72fca0 | 3303 | num_trbs, urb, 0, mem_flags); |
8a96c052 SS |
3304 | if (trb_buff_len < 0) |
3305 | return trb_buff_len; | |
8e51adcc AX |
3306 | |
3307 | urb_priv = urb->hcpriv; | |
3308 | td = urb_priv->td[0]; | |
3309 | ||
8a96c052 SS |
3310 | /* |
3311 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3312 | * until we've finished creating all the other TRBs. The ring's cycle | |
3313 | * state may change as we enqueue the other TRBs, so save it too. | |
3314 | */ | |
3315 | start_trb = &ep_ring->enqueue->generic; | |
3316 | start_cycle = ep_ring->cycle_state; | |
3317 | ||
3318 | running_total = 0; | |
3319 | /* | |
3320 | * How much data is in the first TRB? | |
3321 | * | |
3322 | * There are three forces at work for TRB buffer pointers and lengths: | |
3323 | * 1. We don't want to walk off the end of this sg-list entry buffer. | |
3324 | * 2. The transfer length that the driver requested may be smaller than | |
3325 | * the amount of memory allocated for this scatter-gather list. | |
3326 | * 3. TRBs buffers can't cross 64KB boundaries. | |
3327 | */ | |
910f8d0c | 3328 | sg = urb->sg; |
8a96c052 SS |
3329 | addr = (u64) sg_dma_address(sg); |
3330 | this_sg_len = sg_dma_len(sg); | |
a2490187 | 3331 | trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1)); |
8a96c052 SS |
3332 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
3333 | if (trb_buff_len > urb->transfer_buffer_length) | |
3334 | trb_buff_len = urb->transfer_buffer_length; | |
8a96c052 SS |
3335 | |
3336 | first_trb = true; | |
3337 | /* Queue the first TRB, even if it's zero-length */ | |
3338 | do { | |
3339 | u32 field = 0; | |
f9dc68fe | 3340 | u32 length_field = 0; |
04dd950d | 3341 | u32 remainder = 0; |
8a96c052 SS |
3342 | |
3343 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 3344 | if (first_trb) { |
8a96c052 | 3345 | first_trb = false; |
50f7b52a AX |
3346 | if (start_cycle == 0) |
3347 | field |= 0x1; | |
3348 | } else | |
8a96c052 SS |
3349 | field |= ep_ring->cycle_state; |
3350 | ||
3351 | /* Chain all the TRBs together; clear the chain bit in the last | |
3352 | * TRB to indicate it's the last TRB in the chain. | |
3353 | */ | |
3354 | if (num_trbs > 1) { | |
3355 | field |= TRB_CHAIN; | |
3356 | } else { | |
3357 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
3358 | td->last_trb = ep_ring->enqueue; | |
3359 | field |= TRB_IOC; | |
3360 | } | |
af8b9e63 SS |
3361 | |
3362 | /* Only set interrupt on short packet for IN endpoints */ | |
3363 | if (usb_urb_dir_in(urb)) | |
3364 | field |= TRB_ISP; | |
3365 | ||
8a96c052 | 3366 | if (TRB_MAX_BUFF_SIZE - |
a2490187 | 3367 | (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) { |
8a96c052 SS |
3368 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); |
3369 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", | |
3370 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
3371 | (unsigned int) addr + trb_buff_len); | |
3372 | } | |
4da6e6f2 SS |
3373 | |
3374 | /* Set the TRB length, TD size, and interrupter fields. */ | |
3375 | if (xhci->hci_version < 0x100) { | |
3376 | remainder = xhci_td_remainder( | |
3377 | urb->transfer_buffer_length - | |
3378 | running_total); | |
3379 | } else { | |
3380 | remainder = xhci_v1_0_td_remainder(running_total, | |
4525c0a1 SS |
3381 | trb_buff_len, total_packet_count, urb, |
3382 | num_trbs - 1); | |
4da6e6f2 | 3383 | } |
f9dc68fe | 3384 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 3385 | remainder | |
f9dc68fe | 3386 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3387 | |
6cc30d85 SS |
3388 | if (num_trbs > 1) |
3389 | more_trbs_coming = true; | |
3390 | else | |
3391 | more_trbs_coming = false; | |
3b72fca0 | 3392 | queue_trb(xhci, ep_ring, more_trbs_coming, |
8e595a5d SS |
3393 | lower_32_bits(addr), |
3394 | upper_32_bits(addr), | |
f9dc68fe | 3395 | length_field, |
af8b9e63 | 3396 | field | TRB_TYPE(TRB_NORMAL)); |
8a96c052 SS |
3397 | --num_trbs; |
3398 | running_total += trb_buff_len; | |
3399 | ||
3400 | /* Calculate length for next transfer -- | |
3401 | * Are we done queueing all the TRBs for this sg entry? | |
3402 | */ | |
3403 | this_sg_len -= trb_buff_len; | |
3404 | if (this_sg_len == 0) { | |
3405 | --num_sgs; | |
3406 | if (num_sgs == 0) | |
3407 | break; | |
3408 | sg = sg_next(sg); | |
3409 | addr = (u64) sg_dma_address(sg); | |
3410 | this_sg_len = sg_dma_len(sg); | |
3411 | } else { | |
3412 | addr += trb_buff_len; | |
3413 | } | |
3414 | ||
3415 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
a2490187 | 3416 | (addr & (TRB_MAX_BUFF_SIZE - 1)); |
8a96c052 SS |
3417 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
3418 | if (running_total + trb_buff_len > urb->transfer_buffer_length) | |
3419 | trb_buff_len = | |
3420 | urb->transfer_buffer_length - running_total; | |
3421 | } while (running_total < urb->transfer_buffer_length); | |
3422 | ||
3423 | check_trb_math(urb, num_trbs, running_total); | |
e9df17eb | 3424 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3425 | start_cycle, start_trb); |
8a96c052 SS |
3426 | return 0; |
3427 | } | |
3428 | ||
b10de142 | 3429 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
23e3be11 | 3430 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
b10de142 SS |
3431 | struct urb *urb, int slot_id, unsigned int ep_index) |
3432 | { | |
3433 | struct xhci_ring *ep_ring; | |
8e51adcc | 3434 | struct urb_priv *urb_priv; |
b10de142 SS |
3435 | struct xhci_td *td; |
3436 | int num_trbs; | |
3437 | struct xhci_generic_trb *start_trb; | |
3438 | bool first_trb; | |
6cc30d85 | 3439 | bool more_trbs_coming; |
b10de142 | 3440 | int start_cycle; |
f9dc68fe | 3441 | u32 field, length_field; |
b10de142 SS |
3442 | |
3443 | int running_total, trb_buff_len, ret; | |
4da6e6f2 | 3444 | unsigned int total_packet_count; |
b10de142 SS |
3445 | u64 addr; |
3446 | ||
ff9c895f | 3447 | if (urb->num_sgs) |
8a96c052 SS |
3448 | return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); |
3449 | ||
e9df17eb SS |
3450 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3451 | if (!ep_ring) | |
3452 | return -EINVAL; | |
b10de142 SS |
3453 | |
3454 | num_trbs = 0; | |
3455 | /* How much data is (potentially) left before the 64KB boundary? */ | |
3456 | running_total = TRB_MAX_BUFF_SIZE - | |
a2490187 | 3457 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 3458 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
b10de142 SS |
3459 | |
3460 | /* If there's some data on this 64KB chunk, or we have to send a | |
3461 | * zero-length transfer, we need at least one TRB | |
3462 | */ | |
3463 | if (running_total != 0 || urb->transfer_buffer_length == 0) | |
3464 | num_trbs++; | |
3465 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
3466 | while (running_total < urb->transfer_buffer_length) { | |
3467 | num_trbs++; | |
3468 | running_total += TRB_MAX_BUFF_SIZE; | |
3469 | } | |
3470 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ | |
3471 | ||
e9df17eb SS |
3472 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3473 | ep_index, urb->stream_id, | |
3b72fca0 | 3474 | num_trbs, urb, 0, mem_flags); |
b10de142 SS |
3475 | if (ret < 0) |
3476 | return ret; | |
3477 | ||
8e51adcc AX |
3478 | urb_priv = urb->hcpriv; |
3479 | td = urb_priv->td[0]; | |
3480 | ||
b10de142 SS |
3481 | /* |
3482 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3483 | * until we've finished creating all the other TRBs. The ring's cycle | |
3484 | * state may change as we enqueue the other TRBs, so save it too. | |
3485 | */ | |
3486 | start_trb = &ep_ring->enqueue->generic; | |
3487 | start_cycle = ep_ring->cycle_state; | |
3488 | ||
3489 | running_total = 0; | |
4525c0a1 | 3490 | total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length, |
29cc8897 | 3491 | usb_endpoint_maxp(&urb->ep->desc)); |
b10de142 SS |
3492 | /* How much data is in the first TRB? */ |
3493 | addr = (u64) urb->transfer_dma; | |
3494 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
a2490187 PZ |
3495 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
3496 | if (trb_buff_len > urb->transfer_buffer_length) | |
b10de142 SS |
3497 | trb_buff_len = urb->transfer_buffer_length; |
3498 | ||
3499 | first_trb = true; | |
3500 | ||
3501 | /* Queue the first TRB, even if it's zero-length */ | |
3502 | do { | |
04dd950d | 3503 | u32 remainder = 0; |
b10de142 SS |
3504 | field = 0; |
3505 | ||
3506 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 3507 | if (first_trb) { |
b10de142 | 3508 | first_trb = false; |
50f7b52a AX |
3509 | if (start_cycle == 0) |
3510 | field |= 0x1; | |
3511 | } else | |
b10de142 SS |
3512 | field |= ep_ring->cycle_state; |
3513 | ||
3514 | /* Chain all the TRBs together; clear the chain bit in the last | |
3515 | * TRB to indicate it's the last TRB in the chain. | |
3516 | */ | |
3517 | if (num_trbs > 1) { | |
3518 | field |= TRB_CHAIN; | |
3519 | } else { | |
3520 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
3521 | td->last_trb = ep_ring->enqueue; | |
3522 | field |= TRB_IOC; | |
3523 | } | |
af8b9e63 SS |
3524 | |
3525 | /* Only set interrupt on short packet for IN endpoints */ | |
3526 | if (usb_urb_dir_in(urb)) | |
3527 | field |= TRB_ISP; | |
3528 | ||
4da6e6f2 SS |
3529 | /* Set the TRB length, TD size, and interrupter fields. */ |
3530 | if (xhci->hci_version < 0x100) { | |
3531 | remainder = xhci_td_remainder( | |
3532 | urb->transfer_buffer_length - | |
3533 | running_total); | |
3534 | } else { | |
3535 | remainder = xhci_v1_0_td_remainder(running_total, | |
4525c0a1 SS |
3536 | trb_buff_len, total_packet_count, urb, |
3537 | num_trbs - 1); | |
4da6e6f2 | 3538 | } |
f9dc68fe | 3539 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 3540 | remainder | |
f9dc68fe | 3541 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3542 | |
6cc30d85 SS |
3543 | if (num_trbs > 1) |
3544 | more_trbs_coming = true; | |
3545 | else | |
3546 | more_trbs_coming = false; | |
3b72fca0 | 3547 | queue_trb(xhci, ep_ring, more_trbs_coming, |
8e595a5d SS |
3548 | lower_32_bits(addr), |
3549 | upper_32_bits(addr), | |
f9dc68fe | 3550 | length_field, |
af8b9e63 | 3551 | field | TRB_TYPE(TRB_NORMAL)); |
b10de142 SS |
3552 | --num_trbs; |
3553 | running_total += trb_buff_len; | |
3554 | ||
3555 | /* Calculate length for next transfer */ | |
3556 | addr += trb_buff_len; | |
3557 | trb_buff_len = urb->transfer_buffer_length - running_total; | |
3558 | if (trb_buff_len > TRB_MAX_BUFF_SIZE) | |
3559 | trb_buff_len = TRB_MAX_BUFF_SIZE; | |
3560 | } while (running_total < urb->transfer_buffer_length); | |
3561 | ||
8a96c052 | 3562 | check_trb_math(urb, num_trbs, running_total); |
e9df17eb | 3563 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3564 | start_cycle, start_trb); |
b10de142 SS |
3565 | return 0; |
3566 | } | |
3567 | ||
d0e96f5a | 3568 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3569 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3570 | struct urb *urb, int slot_id, unsigned int ep_index) |
3571 | { | |
3572 | struct xhci_ring *ep_ring; | |
3573 | int num_trbs; | |
3574 | int ret; | |
3575 | struct usb_ctrlrequest *setup; | |
3576 | struct xhci_generic_trb *start_trb; | |
3577 | int start_cycle; | |
f9dc68fe | 3578 | u32 field, length_field; |
8e51adcc | 3579 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3580 | struct xhci_td *td; |
3581 | ||
e9df17eb SS |
3582 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3583 | if (!ep_ring) | |
3584 | return -EINVAL; | |
d0e96f5a SS |
3585 | |
3586 | /* | |
3587 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3588 | * DMA address. | |
3589 | */ | |
3590 | if (!urb->setup_packet) | |
3591 | return -EINVAL; | |
3592 | ||
d0e96f5a SS |
3593 | /* 1 TRB for setup, 1 for status */ |
3594 | num_trbs = 2; | |
3595 | /* | |
3596 | * Don't need to check if we need additional event data and normal TRBs, | |
3597 | * since data in control transfers will never get bigger than 16MB | |
3598 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3599 | */ | |
3600 | if (urb->transfer_buffer_length > 0) | |
3601 | num_trbs++; | |
e9df17eb SS |
3602 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3603 | ep_index, urb->stream_id, | |
3b72fca0 | 3604 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3605 | if (ret < 0) |
3606 | return ret; | |
3607 | ||
8e51adcc AX |
3608 | urb_priv = urb->hcpriv; |
3609 | td = urb_priv->td[0]; | |
3610 | ||
d0e96f5a SS |
3611 | /* |
3612 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3613 | * until we've finished creating all the other TRBs. The ring's cycle | |
3614 | * state may change as we enqueue the other TRBs, so save it too. | |
3615 | */ | |
3616 | start_trb = &ep_ring->enqueue->generic; | |
3617 | start_cycle = ep_ring->cycle_state; | |
3618 | ||
3619 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3620 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3621 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3622 | field = 0; |
3623 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3624 | if (start_cycle == 0) | |
3625 | field |= 0x1; | |
b83cdc8f AX |
3626 | |
3627 | /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ | |
3628 | if (xhci->hci_version == 0x100) { | |
3629 | if (urb->transfer_buffer_length > 0) { | |
3630 | if (setup->bRequestType & USB_DIR_IN) | |
3631 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3632 | else | |
3633 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3634 | } | |
3635 | } | |
3636 | ||
3b72fca0 | 3637 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3638 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3639 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3640 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3641 | /* Immediate data in pointer */ | |
3642 | field); | |
d0e96f5a SS |
3643 | |
3644 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3645 | /* Only set interrupt on short packet for IN endpoints */ |
3646 | if (usb_urb_dir_in(urb)) | |
3647 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3648 | else | |
3649 | field = TRB_TYPE(TRB_DATA); | |
3650 | ||
f9dc68fe | 3651 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
04dd950d | 3652 | xhci_td_remainder(urb->transfer_buffer_length) | |
f9dc68fe | 3653 | TRB_INTR_TARGET(0); |
d0e96f5a SS |
3654 | if (urb->transfer_buffer_length > 0) { |
3655 | if (setup->bRequestType & USB_DIR_IN) | |
3656 | field |= TRB_DIR_IN; | |
3b72fca0 | 3657 | queue_trb(xhci, ep_ring, true, |
d0e96f5a SS |
3658 | lower_32_bits(urb->transfer_dma), |
3659 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 3660 | length_field, |
af8b9e63 | 3661 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3662 | } |
3663 | ||
3664 | /* Save the DMA address of the last TRB in the TD */ | |
3665 | td->last_trb = ep_ring->enqueue; | |
3666 | ||
3667 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3668 | /* If the device sent data, the status stage is an OUT transfer */ | |
3669 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3670 | field = 0; | |
3671 | else | |
3672 | field = TRB_DIR_IN; | |
3b72fca0 | 3673 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3674 | 0, |
3675 | 0, | |
3676 | TRB_INTR_TARGET(0), | |
3677 | /* Event on completion */ | |
3678 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3679 | ||
e9df17eb | 3680 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3681 | start_cycle, start_trb); |
d0e96f5a SS |
3682 | return 0; |
3683 | } | |
3684 | ||
04e51901 AX |
3685 | static int count_isoc_trbs_needed(struct xhci_hcd *xhci, |
3686 | struct urb *urb, int i) | |
3687 | { | |
3688 | int num_trbs = 0; | |
48df4a6f | 3689 | u64 addr, td_len; |
04e51901 AX |
3690 | |
3691 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
3692 | td_len = urb->iso_frame_desc[i].length; | |
3693 | ||
48df4a6f SS |
3694 | num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)), |
3695 | TRB_MAX_BUFF_SIZE); | |
3696 | if (num_trbs == 0) | |
04e51901 | 3697 | num_trbs++; |
04e51901 AX |
3698 | |
3699 | return num_trbs; | |
3700 | } | |
3701 | ||
5cd43e33 SS |
3702 | /* |
3703 | * The transfer burst count field of the isochronous TRB defines the number of | |
3704 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3705 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3706 | * This field is zero based, meaning a value of zero in the field means one | |
3707 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3708 | * zero. Only xHCI 1.0 host controllers support this field. | |
3709 | */ | |
3710 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
3711 | struct usb_device *udev, | |
3712 | struct urb *urb, unsigned int total_packet_count) | |
3713 | { | |
3714 | unsigned int max_burst; | |
3715 | ||
3716 | if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER) | |
3717 | return 0; | |
3718 | ||
3719 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3720 | return roundup(total_packet_count, max_burst + 1) - 1; | |
3721 | } | |
3722 | ||
b61d378f SS |
3723 | /* |
3724 | * Returns the number of packets in the last "burst" of packets. This field is | |
3725 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3726 | * the last burst packet count is equal to the total number of packets in the | |
3727 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3728 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3729 | * contain 1 to (bMaxBurst + 1) packets. | |
3730 | */ | |
3731 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
3732 | struct usb_device *udev, | |
3733 | struct urb *urb, unsigned int total_packet_count) | |
3734 | { | |
3735 | unsigned int max_burst; | |
3736 | unsigned int residue; | |
3737 | ||
3738 | if (xhci->hci_version < 0x100) | |
3739 | return 0; | |
3740 | ||
3741 | switch (udev->speed) { | |
3742 | case USB_SPEED_SUPER: | |
3743 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ | |
3744 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3745 | residue = total_packet_count % (max_burst + 1); | |
3746 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3747 | * number of packets, but the TLBPC field is zero-based. | |
3748 | */ | |
3749 | if (residue == 0) | |
3750 | return max_burst; | |
3751 | return residue - 1; | |
3752 | default: | |
3753 | if (total_packet_count == 0) | |
3754 | return 0; | |
3755 | return total_packet_count - 1; | |
3756 | } | |
3757 | } | |
3758 | ||
04e51901 AX |
3759 | /* This is for isoc transfer */ |
3760 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3761 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3762 | { | |
3763 | struct xhci_ring *ep_ring; | |
3764 | struct urb_priv *urb_priv; | |
3765 | struct xhci_td *td; | |
3766 | int num_tds, trbs_per_td; | |
3767 | struct xhci_generic_trb *start_trb; | |
3768 | bool first_trb; | |
3769 | int start_cycle; | |
3770 | u32 field, length_field; | |
3771 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
3772 | u64 start_addr, addr; | |
3773 | int i, j; | |
47cbf692 | 3774 | bool more_trbs_coming; |
04e51901 AX |
3775 | |
3776 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; | |
3777 | ||
3778 | num_tds = urb->number_of_packets; | |
3779 | if (num_tds < 1) { | |
3780 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
3781 | return -EINVAL; | |
3782 | } | |
3783 | ||
04e51901 AX |
3784 | start_addr = (u64) urb->transfer_dma; |
3785 | start_trb = &ep_ring->enqueue->generic; | |
3786 | start_cycle = ep_ring->cycle_state; | |
3787 | ||
522989a2 | 3788 | urb_priv = urb->hcpriv; |
04e51901 AX |
3789 | /* Queue the first TRB, even if it's zero-length */ |
3790 | for (i = 0; i < num_tds; i++) { | |
4da6e6f2 | 3791 | unsigned int total_packet_count; |
5cd43e33 | 3792 | unsigned int burst_count; |
b61d378f | 3793 | unsigned int residue; |
04e51901 | 3794 | |
4da6e6f2 | 3795 | first_trb = true; |
04e51901 AX |
3796 | running_total = 0; |
3797 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
3798 | td_len = urb->iso_frame_desc[i].length; | |
3799 | td_remain_len = td_len; | |
4525c0a1 | 3800 | total_packet_count = DIV_ROUND_UP(td_len, |
f18f8ed2 SS |
3801 | GET_MAX_PACKET( |
3802 | usb_endpoint_maxp(&urb->ep->desc))); | |
48df4a6f SS |
3803 | /* A zero-length transfer still involves at least one packet. */ |
3804 | if (total_packet_count == 0) | |
3805 | total_packet_count++; | |
5cd43e33 SS |
3806 | burst_count = xhci_get_burst_count(xhci, urb->dev, urb, |
3807 | total_packet_count); | |
b61d378f SS |
3808 | residue = xhci_get_last_burst_packet_count(xhci, |
3809 | urb->dev, urb, total_packet_count); | |
04e51901 AX |
3810 | |
3811 | trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); | |
3812 | ||
3813 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 3814 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
3815 | if (ret < 0) { |
3816 | if (i == 0) | |
3817 | return ret; | |
3818 | goto cleanup; | |
3819 | } | |
04e51901 | 3820 | |
04e51901 | 3821 | td = urb_priv->td[i]; |
04e51901 AX |
3822 | for (j = 0; j < trbs_per_td; j++) { |
3823 | u32 remainder = 0; | |
760973d2 | 3824 | field = 0; |
04e51901 AX |
3825 | |
3826 | if (first_trb) { | |
760973d2 SS |
3827 | field = TRB_TBC(burst_count) | |
3828 | TRB_TLBPC(residue); | |
04e51901 AX |
3829 | /* Queue the isoc TRB */ |
3830 | field |= TRB_TYPE(TRB_ISOC); | |
3831 | /* Assume URB_ISO_ASAP is set */ | |
3832 | field |= TRB_SIA; | |
50f7b52a AX |
3833 | if (i == 0) { |
3834 | if (start_cycle == 0) | |
3835 | field |= 0x1; | |
3836 | } else | |
04e51901 AX |
3837 | field |= ep_ring->cycle_state; |
3838 | first_trb = false; | |
3839 | } else { | |
3840 | /* Queue other normal TRBs */ | |
3841 | field |= TRB_TYPE(TRB_NORMAL); | |
3842 | field |= ep_ring->cycle_state; | |
3843 | } | |
3844 | ||
af8b9e63 SS |
3845 | /* Only set interrupt on short packet for IN EPs */ |
3846 | if (usb_urb_dir_in(urb)) | |
3847 | field |= TRB_ISP; | |
3848 | ||
04e51901 AX |
3849 | /* Chain all the TRBs together; clear the chain bit in |
3850 | * the last TRB to indicate it's the last TRB in the | |
3851 | * chain. | |
3852 | */ | |
3853 | if (j < trbs_per_td - 1) { | |
3854 | field |= TRB_CHAIN; | |
47cbf692 | 3855 | more_trbs_coming = true; |
04e51901 AX |
3856 | } else { |
3857 | td->last_trb = ep_ring->enqueue; | |
3858 | field |= TRB_IOC; | |
80fab3b2 SS |
3859 | if (xhci->hci_version == 0x100 && |
3860 | !(xhci->quirks & | |
3861 | XHCI_AVOID_BEI)) { | |
ad106f29 AX |
3862 | /* Set BEI bit except for the last td */ |
3863 | if (i < num_tds - 1) | |
3864 | field |= TRB_BEI; | |
3865 | } | |
47cbf692 | 3866 | more_trbs_coming = false; |
04e51901 AX |
3867 | } |
3868 | ||
3869 | /* Calculate TRB length */ | |
3870 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
3871 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
3872 | if (trb_buff_len > td_remain_len) | |
3873 | trb_buff_len = td_remain_len; | |
3874 | ||
4da6e6f2 SS |
3875 | /* Set the TRB length, TD size, & interrupter fields. */ |
3876 | if (xhci->hci_version < 0x100) { | |
3877 | remainder = xhci_td_remainder( | |
3878 | td_len - running_total); | |
3879 | } else { | |
3880 | remainder = xhci_v1_0_td_remainder( | |
3881 | running_total, trb_buff_len, | |
4525c0a1 SS |
3882 | total_packet_count, urb, |
3883 | (trbs_per_td - j - 1)); | |
4da6e6f2 | 3884 | } |
04e51901 AX |
3885 | length_field = TRB_LEN(trb_buff_len) | |
3886 | remainder | | |
3887 | TRB_INTR_TARGET(0); | |
4da6e6f2 | 3888 | |
3b72fca0 | 3889 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
3890 | lower_32_bits(addr), |
3891 | upper_32_bits(addr), | |
3892 | length_field, | |
af8b9e63 | 3893 | field); |
04e51901 AX |
3894 | running_total += trb_buff_len; |
3895 | ||
3896 | addr += trb_buff_len; | |
3897 | td_remain_len -= trb_buff_len; | |
3898 | } | |
3899 | ||
3900 | /* Check TD length */ | |
3901 | if (running_total != td_len) { | |
3902 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
3903 | ret = -EINVAL; |
3904 | goto cleanup; | |
04e51901 AX |
3905 | } |
3906 | } | |
3907 | ||
c41136b0 AX |
3908 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
3909 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
3910 | usb_amd_quirk_pll_disable(); | |
3911 | } | |
3912 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
3913 | ||
e1eab2e0 AX |
3914 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3915 | start_cycle, start_trb); | |
04e51901 | 3916 | return 0; |
522989a2 SS |
3917 | cleanup: |
3918 | /* Clean up a partially enqueued isoc transfer. */ | |
3919 | ||
3920 | for (i--; i >= 0; i--) | |
585df1d9 | 3921 | list_del_init(&urb_priv->td[i]->td_list); |
522989a2 SS |
3922 | |
3923 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
3924 | * into No-ops with a software-owned cycle bit. That way the hardware | |
3925 | * won't accidentally start executing bogus TDs when we partially | |
3926 | * overwrite them. td->first_trb and td->start_seg are already set. | |
3927 | */ | |
3928 | urb_priv->td[0]->last_trb = ep_ring->enqueue; | |
3929 | /* Every TRB except the first & last will have its cycle bit flipped. */ | |
3930 | td_to_noop(xhci, ep_ring, urb_priv->td[0], true); | |
3931 | ||
3932 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
3933 | ep_ring->enqueue = urb_priv->td[0]->first_trb; | |
3934 | ep_ring->enq_seg = urb_priv->td[0]->start_seg; | |
3935 | ep_ring->cycle_state = start_cycle; | |
b008df60 | 3936 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
3937 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
3938 | return ret; | |
04e51901 AX |
3939 | } |
3940 | ||
3941 | /* | |
3942 | * Check transfer ring to guarantee there is enough room for the urb. | |
3943 | * Update ISO URB start_frame and interval. | |
3944 | * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to | |
3945 | * update the urb->start_frame by now. | |
3946 | * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input. | |
3947 | */ | |
3948 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3949 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3950 | { | |
3951 | struct xhci_virt_device *xdev; | |
3952 | struct xhci_ring *ep_ring; | |
3953 | struct xhci_ep_ctx *ep_ctx; | |
3954 | int start_frame; | |
3955 | int xhci_interval; | |
3956 | int ep_interval; | |
3957 | int num_tds, num_trbs, i; | |
3958 | int ret; | |
3959 | ||
3960 | xdev = xhci->devs[slot_id]; | |
3961 | ep_ring = xdev->eps[ep_index].ring; | |
3962 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3963 | ||
3964 | num_trbs = 0; | |
3965 | num_tds = urb->number_of_packets; | |
3966 | for (i = 0; i < num_tds; i++) | |
3967 | num_trbs += count_isoc_trbs_needed(xhci, urb, i); | |
3968 | ||
3969 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3970 | * Do not insert any td of the urb to the ring if the check failed. | |
3971 | */ | |
28ccd296 | 3972 | ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3b72fca0 | 3973 | num_trbs, mem_flags); |
04e51901 AX |
3974 | if (ret) |
3975 | return ret; | |
3976 | ||
b0ba9720 | 3977 | start_frame = readl(&xhci->run_regs->microframe_index); |
04e51901 AX |
3978 | start_frame &= 0x3fff; |
3979 | ||
3980 | urb->start_frame = start_frame; | |
3981 | if (urb->dev->speed == USB_SPEED_LOW || | |
3982 | urb->dev->speed == USB_SPEED_FULL) | |
3983 | urb->start_frame >>= 3; | |
3984 | ||
28ccd296 | 3985 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
04e51901 AX |
3986 | ep_interval = urb->interval; |
3987 | /* Convert to microframes */ | |
3988 | if (urb->dev->speed == USB_SPEED_LOW || | |
3989 | urb->dev->speed == USB_SPEED_FULL) | |
3990 | ep_interval *= 8; | |
3991 | /* FIXME change this to a warning and a suggestion to use the new API | |
3992 | * to set the polling interval (once the API is added). | |
3993 | */ | |
3994 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3995 | dev_dbg_ratelimited(&urb->dev->dev, |
3996 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3997 | ep_interval, ep_interval == 1 ? "" : "s", | |
3998 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
04e51901 AX |
3999 | urb->interval = xhci_interval; |
4000 | /* Convert back to frames for LS/FS devices */ | |
4001 | if (urb->dev->speed == USB_SPEED_LOW || | |
4002 | urb->dev->speed == USB_SPEED_FULL) | |
4003 | urb->interval /= 8; | |
4004 | } | |
b008df60 AX |
4005 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
4006 | ||
3fc8206d | 4007 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
4008 | } |
4009 | ||
d0e96f5a SS |
4010 | /**** Command Ring Operations ****/ |
4011 | ||
913a8a34 SS |
4012 | /* Generic function for queueing a command TRB on the command ring. |
4013 | * Check to make sure there's room on the command ring for one command TRB. | |
4014 | * Also check that there's room reserved for commands that must not fail. | |
4015 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
4016 | * then only check for the number of reserved spots. | |
4017 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
4018 | * because the command event handler may want to resubmit a failed command. | |
4019 | */ | |
ddba5cd0 MN |
4020 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4021 | u32 field1, u32 field2, | |
4022 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 4023 | { |
913a8a34 | 4024 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a | 4025 | int ret; |
c9aa1a2d MN |
4026 | if (xhci->xhc_state & XHCI_STATE_DYING) |
4027 | return -ESHUTDOWN; | |
d1dc908a | 4028 | |
913a8a34 SS |
4029 | if (!command_must_succeed) |
4030 | reserved_trbs++; | |
4031 | ||
d1dc908a | 4032 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 4033 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
4034 | if (ret < 0) { |
4035 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
4036 | if (command_must_succeed) |
4037 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
4038 | "unfailable commands failed.\n"); | |
d1dc908a | 4039 | return ret; |
7f84eef0 | 4040 | } |
c9aa1a2d MN |
4041 | |
4042 | cmd->command_trb = xhci->cmd_ring->enqueue; | |
4043 | list_add_tail(&cmd->cmd_list, &xhci->cmd_list); | |
ddba5cd0 | 4044 | |
3b72fca0 AX |
4045 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
4046 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
4047 | return 0; |
4048 | } | |
4049 | ||
3ffbba95 | 4050 | /* Queue a slot enable or disable request on the command ring */ |
ddba5cd0 MN |
4051 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4052 | u32 trb_type, u32 slot_id) | |
3ffbba95 | 4053 | { |
ddba5cd0 | 4054 | return queue_command(xhci, cmd, 0, 0, 0, |
913a8a34 | 4055 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
4056 | } |
4057 | ||
4058 | /* Queue an address device command TRB */ | |
ddba5cd0 MN |
4059 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4060 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) | |
3ffbba95 | 4061 | { |
ddba5cd0 | 4062 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 4063 | upper_32_bits(in_ctx_ptr), 0, |
48fc7dbd DW |
4064 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
4065 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); | |
2a8f82c4 SS |
4066 | } |
4067 | ||
ddba5cd0 | 4068 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
0238634d SS |
4069 | u32 field1, u32 field2, u32 field3, u32 field4) |
4070 | { | |
ddba5cd0 | 4071 | return queue_command(xhci, cmd, field1, field2, field3, field4, false); |
0238634d SS |
4072 | } |
4073 | ||
2a8f82c4 | 4074 | /* Queue a reset device command TRB */ |
ddba5cd0 MN |
4075 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4076 | u32 slot_id) | |
2a8f82c4 | 4077 | { |
ddba5cd0 | 4078 | return queue_command(xhci, cmd, 0, 0, 0, |
2a8f82c4 | 4079 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
913a8a34 | 4080 | false); |
3ffbba95 | 4081 | } |
f94e0186 SS |
4082 | |
4083 | /* Queue a configure endpoint command TRB */ | |
ddba5cd0 MN |
4084 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
4085 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, | |
913a8a34 | 4086 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 4087 | { |
ddba5cd0 | 4088 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 4089 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 SS |
4090 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
4091 | command_must_succeed); | |
f94e0186 | 4092 | } |
ae636747 | 4093 | |
f2217e8e | 4094 | /* Queue an evaluate context command TRB */ |
ddba5cd0 MN |
4095 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4096 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) | |
f2217e8e | 4097 | { |
ddba5cd0 | 4098 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
f2217e8e | 4099 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 | 4100 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 4101 | command_must_succeed); |
f2217e8e SS |
4102 | } |
4103 | ||
be88fe4f AX |
4104 | /* |
4105 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
4106 | * activity on an endpoint that is about to be suspended. | |
4107 | */ | |
ddba5cd0 MN |
4108 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4109 | int slot_id, unsigned int ep_index, int suspend) | |
ae636747 SS |
4110 | { |
4111 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4112 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4113 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 4114 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 | 4115 | |
ddba5cd0 | 4116 | return queue_command(xhci, cmd, 0, 0, 0, |
be88fe4f | 4117 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
4118 | } |
4119 | ||
4120 | /* Set Transfer Ring Dequeue Pointer command. | |
4121 | * This should not be used for endpoints that have streams enabled. | |
4122 | */ | |
ddba5cd0 MN |
4123 | static int queue_set_tr_deq(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4124 | int slot_id, | |
4125 | unsigned int ep_index, unsigned int stream_id, | |
4126 | struct xhci_segment *deq_seg, | |
4127 | union xhci_trb *deq_ptr, u32 cycle_state) | |
ae636747 SS |
4128 | { |
4129 | dma_addr_t addr; | |
4130 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4131 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
e9df17eb | 4132 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
95241dbd | 4133 | u32 trb_sct = 0; |
ae636747 | 4134 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
bf161e85 | 4135 | struct xhci_virt_ep *ep; |
ae636747 | 4136 | |
23e3be11 | 4137 | addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr); |
c92bcfa7 | 4138 | if (addr == 0) { |
ae636747 | 4139 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 GKH |
4140 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
4141 | deq_seg, deq_ptr); | |
c92bcfa7 SS |
4142 | return 0; |
4143 | } | |
bf161e85 SS |
4144 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
4145 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
4146 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | |
4147 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | |
4148 | return 0; | |
4149 | } | |
4150 | ep->queued_deq_seg = deq_seg; | |
4151 | ep->queued_deq_ptr = deq_ptr; | |
95241dbd HG |
4152 | if (stream_id) |
4153 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); | |
ddba5cd0 MN |
4154 | return queue_command(xhci, cmd, |
4155 | lower_32_bits(addr) | trb_sct | cycle_state, | |
e9df17eb | 4156 | upper_32_bits(addr), trb_stream_id, |
913a8a34 | 4157 | trb_slot_id | trb_ep_index | type, false); |
ae636747 | 4158 | } |
a1587d97 | 4159 | |
ddba5cd0 MN |
4160 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4161 | int slot_id, unsigned int ep_index) | |
a1587d97 SS |
4162 | { |
4163 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4164 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4165 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
4166 | ||
ddba5cd0 MN |
4167 | return queue_command(xhci, cmd, 0, 0, 0, |
4168 | trb_slot_id | trb_ep_index | type, false); | |
a1587d97 | 4169 | } |