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Commit | Line | Data |
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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
f9c589e1 | 69 | #include <linux/dma-mapping.h> |
7f84eef0 | 70 | #include "xhci.h" |
3a7fa5be | 71 | #include "xhci-trace.h" |
0cbd4b34 | 72 | #include "xhci-mtk.h" |
7f84eef0 SS |
73 | |
74 | /* | |
75 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
76 | * address of the TRB. | |
77 | */ | |
23e3be11 | 78 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
79 | union xhci_trb *trb) |
80 | { | |
6071d836 | 81 | unsigned long segment_offset; |
7f84eef0 | 82 | |
6071d836 | 83 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 84 | return 0; |
6071d836 SS |
85 | /* offset in TRBs */ |
86 | segment_offset = trb - seg->trbs; | |
7895086a | 87 | if (segment_offset >= TRBS_PER_SEGMENT) |
7f84eef0 | 88 | return 0; |
6071d836 | 89 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
90 | } |
91 | ||
0ce57499 MN |
92 | static bool trb_is_noop(union xhci_trb *trb) |
93 | { | |
94 | return TRB_TYPE_NOOP_LE32(trb->generic.field[3]); | |
95 | } | |
96 | ||
2d98ef40 MN |
97 | static bool trb_is_link(union xhci_trb *trb) |
98 | { | |
99 | return TRB_TYPE_LINK_LE32(trb->link.control); | |
100 | } | |
101 | ||
bd5e67f5 MN |
102 | static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) |
103 | { | |
104 | return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; | |
105 | } | |
106 | ||
107 | static bool last_trb_on_ring(struct xhci_ring *ring, | |
108 | struct xhci_segment *seg, union xhci_trb *trb) | |
109 | { | |
110 | return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); | |
111 | } | |
112 | ||
d0c77d84 MN |
113 | static bool link_trb_toggles_cycle(union xhci_trb *trb) |
114 | { | |
115 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; | |
116 | } | |
117 | ||
2a72126d MN |
118 | static bool last_td_in_urb(struct xhci_td *td) |
119 | { | |
120 | struct urb_priv *urb_priv = td->urb->hcpriv; | |
121 | ||
122 | return urb_priv->td_cnt == urb_priv->length; | |
123 | } | |
124 | ||
125 | static void inc_td_cnt(struct urb *urb) | |
126 | { | |
127 | struct urb_priv *urb_priv = urb->hcpriv; | |
128 | ||
129 | urb_priv->td_cnt++; | |
130 | } | |
131 | ||
ae636747 SS |
132 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
133 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
134 | * effect the ring dequeue or enqueue pointers. | |
135 | */ | |
136 | static void next_trb(struct xhci_hcd *xhci, | |
137 | struct xhci_ring *ring, | |
138 | struct xhci_segment **seg, | |
139 | union xhci_trb **trb) | |
140 | { | |
2d98ef40 | 141 | if (trb_is_link(*trb)) { |
ae636747 SS |
142 | *seg = (*seg)->next; |
143 | *trb = ((*seg)->trbs); | |
144 | } else { | |
a1669b2c | 145 | (*trb)++; |
ae636747 SS |
146 | } |
147 | } | |
148 | ||
7f84eef0 SS |
149 | /* |
150 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
151 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
152 | */ | |
3b72fca0 | 153 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 154 | { |
7f84eef0 | 155 | ring->deq_updates++; |
b008df60 | 156 | |
bd5e67f5 MN |
157 | /* event ring doesn't have link trbs, check for last trb */ |
158 | if (ring->type == TYPE_EVENT) { | |
159 | if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { | |
50d0206f | 160 | ring->dequeue++; |
bd5e67f5 | 161 | return; |
7f84eef0 | 162 | } |
bd5e67f5 MN |
163 | if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) |
164 | ring->cycle_state ^= 1; | |
165 | ring->deq_seg = ring->deq_seg->next; | |
166 | ring->dequeue = ring->deq_seg->trbs; | |
167 | return; | |
168 | } | |
169 | ||
170 | /* All other rings have link trbs */ | |
171 | if (!trb_is_link(ring->dequeue)) { | |
172 | ring->dequeue++; | |
173 | ring->num_trbs_free++; | |
174 | } | |
175 | while (trb_is_link(ring->dequeue)) { | |
176 | ring->deq_seg = ring->deq_seg->next; | |
177 | ring->dequeue = ring->deq_seg->trbs; | |
178 | } | |
179 | return; | |
7f84eef0 SS |
180 | } |
181 | ||
182 | /* | |
183 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
184 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
185 | * | |
186 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
187 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
188 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
189 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
190 | * | |
191 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
192 | * set, but other sections talk about dealing with the chain bit set. This was |
193 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
194 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
195 | * |
196 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
197 | * prepare_transfer()? | |
7f84eef0 | 198 | */ |
6cc30d85 | 199 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 200 | bool more_trbs_coming) |
7f84eef0 SS |
201 | { |
202 | u32 chain; | |
203 | union xhci_trb *next; | |
204 | ||
28ccd296 | 205 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 | 206 | /* If this is not event ring, there is one less usable TRB */ |
2d98ef40 | 207 | if (!trb_is_link(ring->enqueue)) |
b008df60 | 208 | ring->num_trbs_free--; |
7f84eef0 SS |
209 | next = ++(ring->enqueue); |
210 | ||
211 | ring->enq_updates++; | |
2251198b | 212 | /* Update the dequeue pointer further if that was a link TRB */ |
2d98ef40 | 213 | while (trb_is_link(next)) { |
6cc30d85 | 214 | |
2251198b MN |
215 | /* |
216 | * If the caller doesn't plan on enqueueing more TDs before | |
217 | * ringing the doorbell, then we don't want to give the link TRB | |
218 | * to the hardware just yet. We'll give the link TRB back in | |
219 | * prepare_ring() just before we enqueue the TD at the top of | |
220 | * the ring. | |
221 | */ | |
222 | if (!chain && !more_trbs_coming) | |
223 | break; | |
3b72fca0 | 224 | |
2251198b MN |
225 | /* If we're not dealing with 0.95 hardware or isoc rings on |
226 | * AMD 0.96 host, carry over the chain bit of the previous TRB | |
227 | * (which may mean the chain bit is cleared). | |
228 | */ | |
229 | if (!(ring->type == TYPE_ISOC && | |
230 | (xhci->quirks & XHCI_AMD_0x96_HOST)) && | |
231 | !xhci_link_trb_quirk(xhci)) { | |
232 | next->link.control &= cpu_to_le32(~TRB_CHAIN); | |
233 | next->link.control |= cpu_to_le32(chain); | |
7f84eef0 | 234 | } |
2251198b MN |
235 | /* Give this link TRB to the hardware */ |
236 | wmb(); | |
237 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
238 | ||
239 | /* Toggle the cycle bit after the last ring segment. */ | |
d0c77d84 | 240 | if (link_trb_toggles_cycle(next)) |
2251198b MN |
241 | ring->cycle_state ^= 1; |
242 | ||
7f84eef0 SS |
243 | ring->enq_seg = ring->enq_seg->next; |
244 | ring->enqueue = ring->enq_seg->trbs; | |
245 | next = ring->enqueue; | |
246 | } | |
247 | } | |
248 | ||
249 | /* | |
085deb16 AX |
250 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
251 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 252 | */ |
b008df60 | 253 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
254 | unsigned int num_trbs) |
255 | { | |
085deb16 | 256 | int num_trbs_in_deq_seg; |
b008df60 | 257 | |
085deb16 AX |
258 | if (ring->num_trbs_free < num_trbs) |
259 | return 0; | |
260 | ||
261 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
262 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
263 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
264 | return 0; | |
265 | } | |
266 | ||
267 | return 1; | |
7f84eef0 SS |
268 | } |
269 | ||
7f84eef0 | 270 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 271 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 272 | { |
c181bc5b EF |
273 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
274 | return; | |
275 | ||
7f84eef0 | 276 | xhci_dbg(xhci, "// Ding dong!\n"); |
204b7793 | 277 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 | 278 | /* Flush PCI posted writes */ |
b0ba9720 | 279 | readl(&xhci->dba->doorbell[0]); |
7f84eef0 SS |
280 | } |
281 | ||
cb4d5ce5 OH |
282 | static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay) |
283 | { | |
284 | return mod_delayed_work(system_wq, &xhci->cmd_timer, delay); | |
285 | } | |
286 | ||
b92cc66c EF |
287 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci) |
288 | { | |
289 | u64 temp_64; | |
290 | int ret; | |
291 | ||
292 | xhci_dbg(xhci, "Abort command ring\n"); | |
293 | ||
f7b2e403 | 294 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
b92cc66c | 295 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; |
3425aa03 MN |
296 | |
297 | /* | |
298 | * Writing the CMD_RING_ABORT bit should cause a cmd completion event, | |
299 | * however on some host hw the CMD_RING_RUNNING bit is correctly cleared | |
300 | * but the completion event in never sent. Use the cmd timeout timer to | |
301 | * handle those cases. Use twice the time to cover the bit polling retry | |
302 | */ | |
cb4d5ce5 | 303 | xhci_mod_cmd_timer(xhci, 2 * XHCI_CMD_DEFAULT_TIMEOUT); |
477632df SS |
304 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, |
305 | &xhci->op_regs->cmd_ring); | |
b92cc66c EF |
306 | |
307 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should | |
308 | * time the completion od all xHCI commands, including | |
309 | * the Command Abort operation. If software doesn't see | |
310 | * CRR negated in a timely manner (e.g. longer than 5 | |
311 | * seconds), then it should assume that the there are | |
312 | * larger problems with the xHC and assert HCRST. | |
313 | */ | |
dc0b177c | 314 | ret = xhci_handshake(&xhci->op_regs->cmd_ring, |
b92cc66c EF |
315 | CMD_RING_RUNNING, 0, 5 * 1000 * 1000); |
316 | if (ret < 0) { | |
a6809ffd MN |
317 | /* we are about to kill xhci, give it one more chance */ |
318 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, | |
319 | &xhci->op_regs->cmd_ring); | |
320 | udelay(1000); | |
321 | ret = xhci_handshake(&xhci->op_regs->cmd_ring, | |
322 | CMD_RING_RUNNING, 0, 3 * 1000 * 1000); | |
323 | if (ret == 0) | |
324 | return 0; | |
325 | ||
b92cc66c EF |
326 | xhci_err(xhci, "Stopped the command ring failed, " |
327 | "maybe the host is dead\n"); | |
cb4d5ce5 | 328 | cancel_delayed_work(&xhci->cmd_timer); |
b92cc66c | 329 | xhci->xhc_state |= XHCI_STATE_DYING; |
b92cc66c EF |
330 | xhci_halt(xhci); |
331 | return -ESHUTDOWN; | |
332 | } | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
be88fe4f | 337 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 338 | unsigned int slot_id, |
e9df17eb SS |
339 | unsigned int ep_index, |
340 | unsigned int stream_id) | |
ae636747 | 341 | { |
28ccd296 | 342 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
343 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
344 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 345 | |
ae636747 | 346 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 347 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
348 | * We don't want to restart any stream rings if there's a set dequeue |
349 | * pointer command pending because the device can choose to start any | |
350 | * stream once the endpoint is on the HW schedule. | |
ae636747 | 351 | */ |
50d64676 MW |
352 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
353 | (ep_state & EP_HALTED)) | |
354 | return; | |
204b7793 | 355 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
50d64676 MW |
356 | /* The CPU has better things to do at this point than wait for a |
357 | * write-posting flush. It'll get there soon enough. | |
358 | */ | |
ae636747 SS |
359 | } |
360 | ||
e9df17eb SS |
361 | /* Ring the doorbell for any rings with pending URBs */ |
362 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
363 | unsigned int slot_id, | |
364 | unsigned int ep_index) | |
365 | { | |
366 | unsigned int stream_id; | |
367 | struct xhci_virt_ep *ep; | |
368 | ||
369 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
370 | ||
371 | /* A ring has pending URBs if its TD list is not empty */ | |
372 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
d66eaf9f | 373 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
be88fe4f | 374 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
375 | return; |
376 | } | |
377 | ||
378 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
379 | stream_id++) { | |
380 | struct xhci_stream_info *stream_info = ep->stream_info; | |
381 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
382 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
383 | stream_id); | |
e9df17eb SS |
384 | } |
385 | } | |
386 | ||
75b040ec AI |
387 | /* Get the right ring for the given slot_id, ep_index and stream_id. |
388 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
389 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
390 | */ | |
391 | struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
021bff91 SS |
392 | unsigned int slot_id, unsigned int ep_index, |
393 | unsigned int stream_id) | |
394 | { | |
395 | struct xhci_virt_ep *ep; | |
396 | ||
397 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
398 | /* Common case: no streams */ | |
399 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
400 | return ep->ring; | |
401 | ||
402 | if (stream_id == 0) { | |
403 | xhci_warn(xhci, | |
404 | "WARN: Slot ID %u, ep index %u has streams, " | |
405 | "but URB has no stream ID.\n", | |
406 | slot_id, ep_index); | |
407 | return NULL; | |
408 | } | |
409 | ||
410 | if (stream_id < ep->stream_info->num_streams) | |
411 | return ep->stream_info->stream_rings[stream_id]; | |
412 | ||
413 | xhci_warn(xhci, | |
414 | "WARN: Slot ID %u, ep index %u has " | |
415 | "stream IDs 1 to %u allocated, " | |
416 | "but stream ID %u is requested.\n", | |
417 | slot_id, ep_index, | |
418 | ep->stream_info->num_streams - 1, | |
419 | stream_id); | |
420 | return NULL; | |
421 | } | |
422 | ||
ae636747 SS |
423 | /* |
424 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
425 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
426 | * dequeue pointer, and new consumer cycle state in state. | |
427 | * Update our internal representation of the ring's dequeue pointer. | |
428 | * | |
429 | * We do this in three jumps: | |
430 | * - First we update our new ring state to be the same as when the xHC stopped. | |
431 | * - Then we traverse the ring to find the segment that contains | |
432 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
433 | * any link TRBs with the toggle cycle bit set. | |
434 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
435 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
28ccd296 ME |
436 | * |
437 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | |
438 | * with correct __le32 accesses they should work fine. Only users of this are | |
439 | * in here. | |
ae636747 | 440 | */ |
c92bcfa7 | 441 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 442 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
443 | unsigned int stream_id, struct xhci_td *cur_td, |
444 | struct xhci_dequeue_state *state) | |
ae636747 SS |
445 | { |
446 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
c4bedb77 | 447 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; |
e9df17eb | 448 | struct xhci_ring *ep_ring; |
365038d8 MN |
449 | struct xhci_segment *new_seg; |
450 | union xhci_trb *new_deq; | |
c92bcfa7 | 451 | dma_addr_t addr; |
1f81b6d2 | 452 | u64 hw_dequeue; |
365038d8 MN |
453 | bool cycle_found = false; |
454 | bool td_last_trb_found = false; | |
ae636747 | 455 | |
e9df17eb SS |
456 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
457 | ep_index, stream_id); | |
458 | if (!ep_ring) { | |
459 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
460 | "for invalid stream ID %u.\n", | |
461 | stream_id); | |
462 | return; | |
463 | } | |
68e41c5d | 464 | |
ae636747 | 465 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
aa50b290 XR |
466 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
467 | "Finding endpoint context"); | |
c4bedb77 HG |
468 | /* 4.6.9 the css flag is written to the stream context for streams */ |
469 | if (ep->ep_state & EP_HAS_STREAMS) { | |
470 | struct xhci_stream_ctx *ctx = | |
471 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1f81b6d2 | 472 | hw_dequeue = le64_to_cpu(ctx->stream_ring); |
c4bedb77 HG |
473 | } else { |
474 | struct xhci_ep_ctx *ep_ctx | |
475 | = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); | |
1f81b6d2 | 476 | hw_dequeue = le64_to_cpu(ep_ctx->deq); |
c4bedb77 | 477 | } |
ae636747 | 478 | |
365038d8 MN |
479 | new_seg = ep_ring->deq_seg; |
480 | new_deq = ep_ring->dequeue; | |
481 | state->new_cycle_state = hw_dequeue & 0x1; | |
482 | ||
1f81b6d2 | 483 | /* |
365038d8 MN |
484 | * We want to find the pointer, segment and cycle state of the new trb |
485 | * (the one after current TD's last_trb). We know the cycle state at | |
486 | * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are | |
487 | * found. | |
1f81b6d2 | 488 | */ |
365038d8 MN |
489 | do { |
490 | if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) | |
491 | == (dma_addr_t)(hw_dequeue & ~0xf)) { | |
492 | cycle_found = true; | |
493 | if (td_last_trb_found) | |
494 | break; | |
495 | } | |
496 | if (new_deq == cur_td->last_trb) | |
497 | td_last_trb_found = true; | |
1f81b6d2 | 498 | |
3495e451 MN |
499 | if (cycle_found && trb_is_link(new_deq) && |
500 | link_trb_toggles_cycle(new_deq)) | |
365038d8 MN |
501 | state->new_cycle_state ^= 0x1; |
502 | ||
503 | next_trb(xhci, ep_ring, &new_seg, &new_deq); | |
504 | ||
505 | /* Search wrapped around, bail out */ | |
506 | if (new_deq == ep->ring->dequeue) { | |
507 | xhci_err(xhci, "Error: Failed finding new dequeue state\n"); | |
508 | state->new_deq_seg = NULL; | |
509 | state->new_deq_ptr = NULL; | |
510 | return; | |
511 | } | |
512 | ||
513 | } while (!cycle_found || !td_last_trb_found); | |
ae636747 | 514 | |
365038d8 MN |
515 | state->new_deq_seg = new_seg; |
516 | state->new_deq_ptr = new_deq; | |
ae636747 | 517 | |
1f81b6d2 | 518 | /* Don't update the ring cycle state for the producer (us). */ |
aa50b290 XR |
519 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
520 | "Cycle state = 0x%x", state->new_cycle_state); | |
01a1fdb9 | 521 | |
aa50b290 XR |
522 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
523 | "New dequeue segment = %p (virtual)", | |
c92bcfa7 SS |
524 | state->new_deq_seg); |
525 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
aa50b290 XR |
526 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
527 | "New dequeue pointer = 0x%llx (DMA)", | |
c92bcfa7 | 528 | (unsigned long long) addr); |
ae636747 SS |
529 | } |
530 | ||
522989a2 SS |
531 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
532 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
533 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
534 | */ | |
23e3be11 | 535 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
0d58a1a0 | 536 | struct xhci_td *td, bool flip_cycle) |
ae636747 | 537 | { |
0d58a1a0 MN |
538 | struct xhci_segment *seg = td->start_seg; |
539 | union xhci_trb *trb = td->first_trb; | |
540 | ||
541 | while (1) { | |
542 | if (trb_is_link(trb)) { | |
543 | /* unchain chained link TRBs */ | |
544 | trb->link.control &= cpu_to_le32(~TRB_CHAIN); | |
ae636747 | 545 | } else { |
0d58a1a0 MN |
546 | trb->generic.field[0] = 0; |
547 | trb->generic.field[1] = 0; | |
548 | trb->generic.field[2] = 0; | |
ae636747 | 549 | /* Preserve only the cycle bit of this TRB */ |
0d58a1a0 MN |
550 | trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); |
551 | trb->generic.field[3] |= cpu_to_le32( | |
28ccd296 | 552 | TRB_TYPE(TRB_TR_NOOP)); |
ae636747 | 553 | } |
0d58a1a0 MN |
554 | /* flip cycle if asked to */ |
555 | if (flip_cycle && trb != td->first_trb && trb != td->last_trb) | |
556 | trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE); | |
557 | ||
558 | if (trb == td->last_trb) | |
ae636747 | 559 | break; |
0d58a1a0 MN |
560 | |
561 | next_trb(xhci, ep_ring, &seg, &trb); | |
ae636747 SS |
562 | } |
563 | } | |
564 | ||
575688e1 | 565 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
566 | struct xhci_virt_ep *ep) |
567 | { | |
568 | ep->ep_state &= ~EP_HALT_PENDING; | |
569 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the | |
570 | * timer is running on another CPU, we don't decrement stop_cmds_pending | |
571 | * (since we didn't successfully stop the watchdog timer). | |
572 | */ | |
573 | if (del_timer(&ep->stop_cmd_timer)) | |
574 | ep->stop_cmds_pending--; | |
575 | } | |
576 | ||
2a72126d MN |
577 | /* |
578 | * Must be called with xhci->lock held in interrupt context, | |
579 | * releases and re-acquires xhci->lock | |
580 | */ | |
6f5165cf | 581 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, |
2a72126d | 582 | struct xhci_td *cur_td, int status) |
6f5165cf | 583 | { |
2a72126d MN |
584 | struct urb *urb = cur_td->urb; |
585 | struct urb_priv *urb_priv = urb->hcpriv; | |
586 | struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus); | |
587 | ||
588 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | |
589 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
590 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
591 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
592 | usb_amd_quirk_pll_enable(); | |
c41136b0 | 593 | } |
8e51adcc | 594 | } |
446b3141 | 595 | xhci_urb_free_priv(urb_priv); |
2a72126d | 596 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
446b3141 | 597 | spin_unlock(&xhci->lock); |
2a72126d | 598 | usb_hcd_giveback_urb(hcd, urb, status); |
446b3141 MN |
599 | spin_lock(&xhci->lock); |
600 | } | |
601 | ||
2d6d5769 WY |
602 | static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, |
603 | struct xhci_ring *ring, struct xhci_td *td) | |
f9c589e1 MN |
604 | { |
605 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
606 | struct xhci_segment *seg = td->bounce_seg; | |
607 | struct urb *urb = td->urb; | |
608 | ||
609 | if (!seg || !urb) | |
610 | return; | |
611 | ||
612 | if (usb_urb_dir_out(urb)) { | |
613 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
614 | DMA_TO_DEVICE); | |
615 | return; | |
616 | } | |
617 | ||
618 | /* for in tranfers we need to copy the data from bounce to sg */ | |
619 | sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf, | |
620 | seg->bounce_len, seg->bounce_offs); | |
621 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
622 | DMA_FROM_DEVICE); | |
623 | seg->bounce_len = 0; | |
624 | seg->bounce_offs = 0; | |
625 | } | |
626 | ||
ae636747 SS |
627 | /* |
628 | * When we get a command completion for a Stop Endpoint Command, we need to | |
629 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
630 | * | |
631 | * 1. If the HW was in the middle of processing the TD that needs to be | |
632 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
633 | * in the TD with a Set Dequeue Pointer Command. | |
634 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
635 | * bit cleared) so that the HW will skip over them. | |
636 | */ | |
b8200c94 | 637 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 638 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 | 639 | { |
ae636747 SS |
640 | unsigned int ep_index; |
641 | struct xhci_ring *ep_ring; | |
63a0d9ab | 642 | struct xhci_virt_ep *ep; |
ae636747 | 643 | struct list_head *entry; |
326b4810 | 644 | struct xhci_td *cur_td = NULL; |
ae636747 SS |
645 | struct xhci_td *last_unlinked_td; |
646 | ||
c92bcfa7 | 647 | struct xhci_dequeue_state deq_state; |
ae636747 | 648 | |
bc752bde | 649 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
9ea1833e | 650 | if (!xhci->devs[slot_id]) |
be88fe4f AX |
651 | xhci_warn(xhci, "Stop endpoint command " |
652 | "completion for disabled slot %u\n", | |
653 | slot_id); | |
654 | return; | |
655 | } | |
656 | ||
ae636747 | 657 | memset(&deq_state, 0, sizeof(deq_state)); |
28ccd296 | 658 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
63a0d9ab | 659 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
ae636747 | 660 | |
678539cf | 661 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 662 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
0714a57c | 663 | ep->stopped_td = NULL; |
e9df17eb | 664 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 665 | return; |
678539cf | 666 | } |
ae636747 SS |
667 | |
668 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
669 | * We have the xHCI lock, so nothing can modify this list until we drop | |
670 | * it. We're also in the event handler, so we can't get re-interrupted | |
671 | * if another Stop Endpoint command completes | |
672 | */ | |
63a0d9ab | 673 | list_for_each(entry, &ep->cancelled_td_list) { |
ae636747 | 674 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
aa50b290 XR |
675 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
676 | "Removing canceled TD starting at 0x%llx (dma).", | |
79688acf SS |
677 | (unsigned long long)xhci_trb_virt_to_dma( |
678 | cur_td->start_seg, cur_td->first_trb)); | |
e9df17eb SS |
679 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
680 | if (!ep_ring) { | |
681 | /* This shouldn't happen unless a driver is mucking | |
682 | * with the stream ID after submission. This will | |
683 | * leave the TD on the hardware ring, and the hardware | |
684 | * will try to execute it, and may access a buffer | |
685 | * that has already been freed. In the best case, the | |
686 | * hardware will execute it, and the event handler will | |
687 | * ignore the completion event for that TD, since it was | |
688 | * removed from the td_list for that endpoint. In | |
689 | * short, don't muck with the stream ID after | |
690 | * submission. | |
691 | */ | |
692 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
693 | "has invalid stream ID %u.\n", | |
694 | cur_td->urb, | |
695 | cur_td->urb->stream_id); | |
696 | goto remove_finished_td; | |
697 | } | |
ae636747 SS |
698 | /* |
699 | * If we stopped on the TD we need to cancel, then we have to | |
700 | * move the xHC endpoint ring dequeue pointer past this TD. | |
701 | */ | |
63a0d9ab | 702 | if (cur_td == ep->stopped_td) |
e9df17eb SS |
703 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
704 | cur_td->urb->stream_id, | |
705 | cur_td, &deq_state); | |
ae636747 | 706 | else |
522989a2 | 707 | td_to_noop(xhci, ep_ring, cur_td, false); |
e9df17eb | 708 | remove_finished_td: |
ae636747 SS |
709 | /* |
710 | * The event handler won't see a completion for this TD anymore, | |
711 | * so remove it from the endpoint ring's TD list. Keep it in | |
712 | * the cancelled TD list for URB completion later. | |
713 | */ | |
585df1d9 | 714 | list_del_init(&cur_td->td_list); |
ae636747 SS |
715 | } |
716 | last_unlinked_td = cur_td; | |
6f5165cf | 717 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
718 | |
719 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
720 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
1e3452e3 HG |
721 | xhci_queue_new_dequeue_state(xhci, slot_id, ep_index, |
722 | ep->stopped_td->urb->stream_id, &deq_state); | |
ac9d8fe7 | 723 | xhci_ring_cmd_db(xhci); |
ae636747 | 724 | } else { |
e9df17eb SS |
725 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
726 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 727 | } |
526867c3 | 728 | |
d97b4f8d | 729 | ep->stopped_td = NULL; |
ae636747 SS |
730 | |
731 | /* | |
732 | * Drop the lock and complete the URBs in the cancelled TD list. | |
733 | * New TDs to be cancelled might be added to the end of the list before | |
734 | * we can complete all the URBs for the TDs we already unlinked. | |
735 | * So stop when we've completed the URB for the last TD we unlinked. | |
736 | */ | |
737 | do { | |
63a0d9ab | 738 | cur_td = list_entry(ep->cancelled_td_list.next, |
ae636747 | 739 | struct xhci_td, cancelled_td_list); |
585df1d9 | 740 | list_del_init(&cur_td->cancelled_td_list); |
ae636747 SS |
741 | |
742 | /* Clean up the cancelled URB */ | |
ae636747 SS |
743 | /* Doesn't matter what we pass for status, since the core will |
744 | * just overwrite it (because the URB has been unlinked). | |
745 | */ | |
f76a28a6 | 746 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
f9c589e1 MN |
747 | if (ep_ring && cur_td->bounce_seg) |
748 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td); | |
2a72126d MN |
749 | inc_td_cnt(cur_td->urb); |
750 | if (last_td_in_urb(cur_td)) | |
751 | xhci_giveback_urb_in_irq(xhci, cur_td, 0); | |
ae636747 | 752 | |
6f5165cf SS |
753 | /* Stop processing the cancelled list if the watchdog timer is |
754 | * running. | |
755 | */ | |
756 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
757 | return; | |
ae636747 SS |
758 | } while (cur_td != last_unlinked_td); |
759 | ||
760 | /* Return to the event handler with xhci->lock re-acquired */ | |
761 | } | |
762 | ||
50e8725e SS |
763 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
764 | { | |
765 | struct xhci_td *cur_td; | |
766 | ||
767 | while (!list_empty(&ring->td_list)) { | |
768 | cur_td = list_first_entry(&ring->td_list, | |
769 | struct xhci_td, td_list); | |
770 | list_del_init(&cur_td->td_list); | |
771 | if (!list_empty(&cur_td->cancelled_td_list)) | |
772 | list_del_init(&cur_td->cancelled_td_list); | |
f9c589e1 MN |
773 | |
774 | if (cur_td->bounce_seg) | |
775 | xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); | |
2a72126d MN |
776 | |
777 | inc_td_cnt(cur_td->urb); | |
778 | if (last_td_in_urb(cur_td)) | |
779 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
780 | } |
781 | } | |
782 | ||
783 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, | |
784 | int slot_id, int ep_index) | |
785 | { | |
786 | struct xhci_td *cur_td; | |
787 | struct xhci_virt_ep *ep; | |
788 | struct xhci_ring *ring; | |
789 | ||
790 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
21d0e51b SS |
791 | if ((ep->ep_state & EP_HAS_STREAMS) || |
792 | (ep->ep_state & EP_GETTING_NO_STREAMS)) { | |
793 | int stream_id; | |
794 | ||
795 | for (stream_id = 0; stream_id < ep->stream_info->num_streams; | |
796 | stream_id++) { | |
797 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
798 | "Killing URBs for slot ID %u, ep index %u, stream %u", | |
799 | slot_id, ep_index, stream_id + 1); | |
800 | xhci_kill_ring_urbs(xhci, | |
801 | ep->stream_info->stream_rings[stream_id]); | |
802 | } | |
803 | } else { | |
804 | ring = ep->ring; | |
805 | if (!ring) | |
806 | return; | |
807 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
808 | "Killing URBs for slot ID %u, ep index %u", | |
809 | slot_id, ep_index); | |
810 | xhci_kill_ring_urbs(xhci, ring); | |
811 | } | |
50e8725e SS |
812 | while (!list_empty(&ep->cancelled_td_list)) { |
813 | cur_td = list_first_entry(&ep->cancelled_td_list, | |
814 | struct xhci_td, cancelled_td_list); | |
815 | list_del_init(&cur_td->cancelled_td_list); | |
2a72126d MN |
816 | |
817 | inc_td_cnt(cur_td->urb); | |
818 | if (last_td_in_urb(cur_td)) | |
819 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
820 | } |
821 | } | |
822 | ||
6f5165cf SS |
823 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
824 | * In this case, we assume the host controller is broken or dying or dead. The | |
825 | * host may still be completing some other events, so we have to be careful to | |
826 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
827 | * through xhci->state. | |
828 | * | |
829 | * The timer may also fire if the host takes a very long time to respond to the | |
830 | * command, and the stop endpoint command completion handler cannot delete the | |
831 | * timer before the timer function is called. Another endpoint cancellation may | |
832 | * sneak in before the timer function can grab the lock, and that may queue | |
833 | * another stop endpoint command and add the timer back. So we cannot use a | |
834 | * simple flag to say whether there is a pending stop endpoint command for a | |
835 | * particular endpoint. | |
836 | * | |
837 | * Instead we use a combination of that flag and a counter for the number of | |
838 | * pending stop endpoint commands. If the timer is the tail end of the last | |
839 | * stop endpoint command, and the endpoint's command is still pending, we assume | |
840 | * the host is dying. | |
841 | */ | |
842 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
843 | { | |
844 | struct xhci_hcd *xhci; | |
845 | struct xhci_virt_ep *ep; | |
6f5165cf | 846 | int ret, i, j; |
f43d6231 | 847 | unsigned long flags; |
6f5165cf SS |
848 | |
849 | ep = (struct xhci_virt_ep *) arg; | |
850 | xhci = ep->xhci; | |
851 | ||
f43d6231 | 852 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
853 | |
854 | ep->stop_cmds_pending--; | |
bcf42aa6 MN |
855 | if (xhci->xhc_state & XHCI_STATE_REMOVING) { |
856 | spin_unlock_irqrestore(&xhci->lock, flags); | |
857 | return; | |
858 | } | |
6f5165cf | 859 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
aa50b290 XR |
860 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
861 | "Stop EP timer ran, but another timer marked " | |
862 | "xHCI as DYING, exiting."); | |
f43d6231 | 863 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
864 | return; |
865 | } | |
866 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { | |
aa50b290 XR |
867 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
868 | "Stop EP timer ran, but no command pending, " | |
869 | "exiting."); | |
f43d6231 | 870 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
871 | return; |
872 | } | |
873 | ||
874 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
875 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
876 | /* Oops, HC is dead or dying or at least not responding to the stop | |
877 | * endpoint command. | |
878 | */ | |
879 | xhci->xhc_state |= XHCI_STATE_DYING; | |
880 | /* Disable interrupts from the host controller and start halting it */ | |
881 | xhci_quiesce(xhci); | |
f43d6231 | 882 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
883 | |
884 | ret = xhci_halt(xhci); | |
885 | ||
f43d6231 | 886 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
887 | if (ret < 0) { |
888 | /* This is bad; the host is not responding to commands and it's | |
889 | * not allowing itself to be halted. At least interrupts are | |
ac04e6ff | 890 | * disabled. If we call usb_hc_died(), it will attempt to |
6f5165cf SS |
891 | * disconnect all device drivers under this host. Those |
892 | * disconnect() methods will wait for all URBs to be unlinked, | |
893 | * so we must complete them. | |
894 | */ | |
895 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
896 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
897 | /* We could turn all TDs on the rings to no-ops. This won't | |
898 | * help if the host has cached part of the ring, and is slow if | |
899 | * we want to preserve the cycle bit. Skip it and hope the host | |
900 | * doesn't touch the memory. | |
901 | */ | |
902 | } | |
903 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
904 | if (!xhci->devs[i]) | |
905 | continue; | |
50e8725e SS |
906 | for (j = 0; j < 31; j++) |
907 | xhci_kill_endpoint_urbs(xhci, i, j); | |
6f5165cf | 908 | } |
f43d6231 | 909 | spin_unlock_irqrestore(&xhci->lock, flags); |
aa50b290 XR |
910 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
911 | "Calling usb_hc_died()"); | |
bcf42aa6 | 912 | usb_hc_died(xhci_to_hcd(xhci)); |
aa50b290 XR |
913 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
914 | "xHCI host controller is dead."); | |
6f5165cf SS |
915 | } |
916 | ||
b008df60 AX |
917 | |
918 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, | |
919 | struct xhci_virt_device *dev, | |
920 | struct xhci_ring *ep_ring, | |
921 | unsigned int ep_index) | |
922 | { | |
923 | union xhci_trb *dequeue_temp; | |
924 | int num_trbs_free_temp; | |
925 | bool revert = false; | |
926 | ||
927 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
928 | dequeue_temp = ep_ring->dequeue; | |
929 | ||
0d9f78a9 SS |
930 | /* If we get two back-to-back stalls, and the first stalled transfer |
931 | * ends just before a link TRB, the dequeue pointer will be left on | |
932 | * the link TRB by the code in the while loop. So we have to update | |
933 | * the dequeue pointer one segment further, or we'll jump off | |
934 | * the segment into la-la-land. | |
935 | */ | |
2d98ef40 | 936 | if (trb_is_link(ep_ring->dequeue)) { |
0d9f78a9 SS |
937 | ep_ring->deq_seg = ep_ring->deq_seg->next; |
938 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
939 | } | |
940 | ||
b008df60 AX |
941 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
942 | /* We have more usable TRBs */ | |
943 | ep_ring->num_trbs_free++; | |
944 | ep_ring->dequeue++; | |
2d98ef40 | 945 | if (trb_is_link(ep_ring->dequeue)) { |
b008df60 AX |
946 | if (ep_ring->dequeue == |
947 | dev->eps[ep_index].queued_deq_ptr) | |
948 | break; | |
949 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
950 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
951 | } | |
952 | if (ep_ring->dequeue == dequeue_temp) { | |
953 | revert = true; | |
954 | break; | |
955 | } | |
956 | } | |
957 | ||
958 | if (revert) { | |
959 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
960 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
961 | } | |
962 | } | |
963 | ||
ae636747 SS |
964 | /* |
965 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
966 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
967 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
968 | * endpoint doorbell to restart the ring, but only if there aren't more | |
969 | * cancellations pending. | |
970 | */ | |
b8200c94 | 971 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 972 | union xhci_trb *trb, u32 cmd_comp_code) |
ae636747 | 973 | { |
ae636747 | 974 | unsigned int ep_index; |
e9df17eb | 975 | unsigned int stream_id; |
ae636747 SS |
976 | struct xhci_ring *ep_ring; |
977 | struct xhci_virt_device *dev; | |
9aad95e2 | 978 | struct xhci_virt_ep *ep; |
d115b048 JY |
979 | struct xhci_ep_ctx *ep_ctx; |
980 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 | 981 | |
28ccd296 ME |
982 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
983 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
ae636747 | 984 | dev = xhci->devs[slot_id]; |
9aad95e2 | 985 | ep = &dev->eps[ep_index]; |
e9df17eb SS |
986 | |
987 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
988 | if (!ep_ring) { | |
e587b8b2 | 989 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
e9df17eb SS |
990 | stream_id); |
991 | /* XXX: Harmless??? */ | |
0d4976ec | 992 | goto cleanup; |
e9df17eb SS |
993 | } |
994 | ||
d115b048 JY |
995 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
996 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
ae636747 | 997 | |
c69a0597 | 998 | if (cmd_comp_code != COMP_SUCCESS) { |
ae636747 SS |
999 | unsigned int ep_state; |
1000 | unsigned int slot_state; | |
1001 | ||
c69a0597 | 1002 | switch (cmd_comp_code) { |
ae636747 | 1003 | case COMP_TRB_ERR: |
e587b8b2 | 1004 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
ae636747 SS |
1005 | break; |
1006 | case COMP_CTX_STATE: | |
e587b8b2 | 1007 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
5071e6b2 | 1008 | ep_state = GET_EP_CTX_STATE(ep_ctx); |
28ccd296 | 1009 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 | 1010 | slot_state = GET_SLOT_STATE(slot_state); |
aa50b290 XR |
1011 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1012 | "Slot state = %u, EP state = %u", | |
ae636747 SS |
1013 | slot_state, ep_state); |
1014 | break; | |
1015 | case COMP_EBADSLT: | |
e587b8b2 ON |
1016 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
1017 | slot_id); | |
ae636747 SS |
1018 | break; |
1019 | default: | |
e587b8b2 ON |
1020 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
1021 | cmd_comp_code); | |
ae636747 SS |
1022 | break; |
1023 | } | |
1024 | /* OK what do we do now? The endpoint state is hosed, and we | |
1025 | * should never get to this point if the synchronization between | |
1026 | * queueing, and endpoint state are correct. This might happen | |
1027 | * if the device gets disconnected after we've finished | |
1028 | * cancelling URBs, which might not be an error... | |
1029 | */ | |
1030 | } else { | |
9aad95e2 HG |
1031 | u64 deq; |
1032 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ | |
1033 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1034 | struct xhci_stream_ctx *ctx = | |
1035 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1036 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; | |
1037 | } else { | |
1038 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; | |
1039 | } | |
aa50b290 | 1040 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
9aad95e2 HG |
1041 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
1042 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, | |
1043 | ep->queued_deq_ptr) == deq) { | |
bf161e85 SS |
1044 | /* Update the ring's dequeue segment and dequeue pointer |
1045 | * to reflect the new position. | |
1046 | */ | |
b008df60 AX |
1047 | update_ring_for_set_deq_completion(xhci, dev, |
1048 | ep_ring, ep_index); | |
bf161e85 | 1049 | } else { |
e587b8b2 | 1050 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
bf161e85 | 1051 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
9aad95e2 | 1052 | ep->queued_deq_seg, ep->queued_deq_ptr); |
bf161e85 | 1053 | } |
ae636747 SS |
1054 | } |
1055 | ||
0d4976ec | 1056 | cleanup: |
63a0d9ab | 1057 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
bf161e85 SS |
1058 | dev->eps[ep_index].queued_deq_seg = NULL; |
1059 | dev->eps[ep_index].queued_deq_ptr = NULL; | |
e9df17eb SS |
1060 | /* Restart any rings with pending URBs */ |
1061 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1062 | } |
1063 | ||
b8200c94 | 1064 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1065 | union xhci_trb *trb, u32 cmd_comp_code) |
a1587d97 | 1066 | { |
a1587d97 SS |
1067 | unsigned int ep_index; |
1068 | ||
28ccd296 | 1069 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
a1587d97 SS |
1070 | /* This command will only fail if the endpoint wasn't halted, |
1071 | * but we don't care. | |
1072 | */ | |
a0254324 | 1073 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
c69a0597 | 1074 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
a1587d97 | 1075 | |
ac9d8fe7 SS |
1076 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
1077 | * command complete before the endpoint can be used. Queue that here | |
1078 | * because the HW can't handle two commands being queued in a row. | |
1079 | */ | |
1080 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
ddba5cd0 MN |
1081 | struct xhci_command *command; |
1082 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
a0ee619f HG |
1083 | if (!command) { |
1084 | xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n"); | |
1085 | return; | |
1086 | } | |
4bdfe4c3 XR |
1087 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1088 | "Queueing configure endpoint command"); | |
ddba5cd0 | 1089 | xhci_queue_configure_endpoint(xhci, command, |
913a8a34 SS |
1090 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
1091 | false); | |
ac9d8fe7 SS |
1092 | xhci_ring_cmd_db(xhci); |
1093 | } else { | |
c3492dbf | 1094 | /* Clear our internal halted state */ |
63a0d9ab | 1095 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
ac9d8fe7 | 1096 | } |
a1587d97 | 1097 | } |
ae636747 | 1098 | |
b244b431 | 1099 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
c2d3d49b | 1100 | struct xhci_command *command, u32 cmd_comp_code) |
b244b431 XR |
1101 | { |
1102 | if (cmd_comp_code == COMP_SUCCESS) | |
c2d3d49b | 1103 | command->slot_id = slot_id; |
b244b431 | 1104 | else |
c2d3d49b | 1105 | command->slot_id = 0; |
b244b431 XR |
1106 | } |
1107 | ||
6c02dd14 XR |
1108 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
1109 | { | |
1110 | struct xhci_virt_device *virt_dev; | |
1111 | ||
1112 | virt_dev = xhci->devs[slot_id]; | |
1113 | if (!virt_dev) | |
1114 | return; | |
1115 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) | |
1116 | /* Delete default control endpoint resources */ | |
1117 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); | |
1118 | xhci_free_virt_device(xhci, slot_id); | |
1119 | } | |
1120 | ||
6ed46d33 XR |
1121 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
1122 | struct xhci_event_cmd *event, u32 cmd_comp_code) | |
1123 | { | |
1124 | struct xhci_virt_device *virt_dev; | |
1125 | struct xhci_input_control_ctx *ctrl_ctx; | |
1126 | unsigned int ep_index; | |
1127 | unsigned int ep_state; | |
1128 | u32 add_flags, drop_flags; | |
1129 | ||
6ed46d33 XR |
1130 | /* |
1131 | * Configure endpoint commands can come from the USB core | |
1132 | * configuration or alt setting changes, or because the HW | |
1133 | * needed an extra configure endpoint command after a reset | |
1134 | * endpoint command or streams were being configured. | |
1135 | * If the command was for a halted endpoint, the xHCI driver | |
1136 | * is not waiting on the configure endpoint command. | |
1137 | */ | |
9ea1833e | 1138 | virt_dev = xhci->devs[slot_id]; |
4daf9df5 | 1139 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
6ed46d33 XR |
1140 | if (!ctrl_ctx) { |
1141 | xhci_warn(xhci, "Could not get input context, bad type.\n"); | |
1142 | return; | |
1143 | } | |
1144 | ||
1145 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
1146 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
1147 | /* Input ctx add_flags are the endpoint index plus one */ | |
1148 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; | |
1149 | ||
1150 | /* A usb_set_interface() call directly after clearing a halted | |
1151 | * condition may race on this quirky hardware. Not worth | |
1152 | * worrying about, since this is prototype hardware. Not sure | |
1153 | * if this will work for streams, but streams support was | |
1154 | * untested on this prototype. | |
1155 | */ | |
1156 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
1157 | ep_index != (unsigned int) -1 && | |
1158 | add_flags - SLOT_FLAG == drop_flags) { | |
1159 | ep_state = virt_dev->eps[ep_index].ep_state; | |
1160 | if (!(ep_state & EP_HALTED)) | |
ddba5cd0 | 1161 | return; |
6ed46d33 XR |
1162 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1163 | "Completed config ep cmd - " | |
1164 | "last ep index = %d, state = %d", | |
1165 | ep_index, ep_state); | |
1166 | /* Clear internal halted state and restart ring(s) */ | |
1167 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; | |
1168 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
1169 | return; | |
1170 | } | |
6ed46d33 XR |
1171 | return; |
1172 | } | |
1173 | ||
f681321b XR |
1174 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, |
1175 | struct xhci_event_cmd *event) | |
1176 | { | |
f681321b | 1177 | xhci_dbg(xhci, "Completed reset device command.\n"); |
9ea1833e | 1178 | if (!xhci->devs[slot_id]) |
f681321b XR |
1179 | xhci_warn(xhci, "Reset device command completion " |
1180 | "for disabled slot %u\n", slot_id); | |
1181 | } | |
1182 | ||
2c070821 XR |
1183 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
1184 | struct xhci_event_cmd *event) | |
1185 | { | |
1186 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
f4c8f03c | 1187 | xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n"); |
2c070821 XR |
1188 | return; |
1189 | } | |
1190 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1191 | "NEC firmware version %2x.%02x", | |
1192 | NEC_FW_MAJOR(le32_to_cpu(event->status)), | |
1193 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
1194 | } | |
1195 | ||
9ea1833e | 1196 | static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) |
c9aa1a2d MN |
1197 | { |
1198 | list_del(&cmd->cmd_list); | |
9ea1833e MN |
1199 | |
1200 | if (cmd->completion) { | |
1201 | cmd->status = status; | |
1202 | complete(cmd->completion); | |
1203 | } else { | |
c9aa1a2d | 1204 | kfree(cmd); |
9ea1833e | 1205 | } |
c9aa1a2d MN |
1206 | } |
1207 | ||
1208 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci) | |
1209 | { | |
1210 | struct xhci_command *cur_cmd, *tmp_cmd; | |
1211 | list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) | |
9ea1833e | 1212 | xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT); |
c9aa1a2d MN |
1213 | } |
1214 | ||
c311e391 MN |
1215 | /* |
1216 | * Turn all commands on command ring with status set to "aborted" to no-op trbs. | |
1217 | * If there are other commands waiting then restart the ring and kick the timer. | |
1218 | * This must be called with command ring stopped and xhci->lock held. | |
1219 | */ | |
1220 | static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, | |
1221 | struct xhci_command *cur_cmd) | |
1222 | { | |
1223 | struct xhci_command *i_cmd, *tmp_cmd; | |
1224 | u32 cycle_state; | |
1225 | ||
1226 | /* Turn all aborted commands in list to no-ops, then restart */ | |
1227 | list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list, | |
1228 | cmd_list) { | |
1229 | ||
1230 | if (i_cmd->status != COMP_CMD_ABORT) | |
1231 | continue; | |
1232 | ||
1233 | i_cmd->status = COMP_CMD_STOP; | |
1234 | ||
1235 | xhci_dbg(xhci, "Turn aborted command %p to no-op\n", | |
1236 | i_cmd->command_trb); | |
1237 | /* get cycle state from the original cmd trb */ | |
1238 | cycle_state = le32_to_cpu( | |
1239 | i_cmd->command_trb->generic.field[3]) & TRB_CYCLE; | |
1240 | /* modify the command trb to no-op command */ | |
1241 | i_cmd->command_trb->generic.field[0] = 0; | |
1242 | i_cmd->command_trb->generic.field[1] = 0; | |
1243 | i_cmd->command_trb->generic.field[2] = 0; | |
1244 | i_cmd->command_trb->generic.field[3] = cpu_to_le32( | |
1245 | TRB_TYPE(TRB_CMD_NOOP) | cycle_state); | |
1246 | ||
1247 | /* | |
1248 | * caller waiting for completion is called when command | |
1249 | * completion event is received for these no-op commands | |
1250 | */ | |
1251 | } | |
1252 | ||
1253 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; | |
1254 | ||
1255 | /* ring command ring doorbell to restart the command ring */ | |
1256 | if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && | |
1257 | !(xhci->xhc_state & XHCI_STATE_DYING)) { | |
1258 | xhci->current_cmd = cur_cmd; | |
cb4d5ce5 | 1259 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
c311e391 MN |
1260 | xhci_ring_cmd_db(xhci); |
1261 | } | |
1262 | return; | |
1263 | } | |
1264 | ||
1265 | ||
cb4d5ce5 | 1266 | void xhci_handle_command_timeout(struct work_struct *work) |
c311e391 MN |
1267 | { |
1268 | struct xhci_hcd *xhci; | |
1269 | int ret; | |
1270 | unsigned long flags; | |
1271 | u64 hw_ring_state; | |
3425aa03 | 1272 | bool second_timeout = false; |
cb4d5ce5 OH |
1273 | |
1274 | xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer); | |
c311e391 | 1275 | |
c311e391 | 1276 | spin_lock_irqsave(&xhci->lock, flags); |
2b985467 | 1277 | |
a5a1b951 MN |
1278 | /* |
1279 | * If timeout work is pending, or current_cmd is NULL, it means we | |
1280 | * raced with command completion. Command is handled so just return. | |
1281 | */ | |
cb4d5ce5 | 1282 | if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) { |
2b985467 LB |
1283 | spin_unlock_irqrestore(&xhci->lock, flags); |
1284 | return; | |
c311e391 MN |
1285 | } |
1286 | ||
2b985467 LB |
1287 | /* mark this command to be cancelled */ |
1288 | if (xhci->current_cmd->status == COMP_CMD_ABORT) | |
1289 | second_timeout = true; | |
1290 | xhci->current_cmd->status = COMP_CMD_ABORT; | |
1291 | ||
c311e391 MN |
1292 | /* Make sure command ring is running before aborting it */ |
1293 | hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | |
1294 | if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && | |
1295 | (hw_ring_state & CMD_RING_RUNNING)) { | |
c311e391 MN |
1296 | xhci_dbg(xhci, "Command timeout\n"); |
1297 | ret = xhci_abort_cmd_ring(xhci); | |
1298 | if (unlikely(ret == -ESHUTDOWN)) { | |
1299 | xhci_err(xhci, "Abort command ring failed\n"); | |
1300 | xhci_cleanup_command_queue(xhci); | |
4dea7077 | 1301 | spin_unlock_irqrestore(&xhci->lock, flags); |
c311e391 MN |
1302 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); |
1303 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); | |
4dea7077 LB |
1304 | |
1305 | return; | |
c311e391 | 1306 | } |
4dea7077 LB |
1307 | |
1308 | goto time_out_completed; | |
c311e391 | 1309 | } |
3425aa03 MN |
1310 | |
1311 | /* command ring failed to restart, or host removed. Bail out */ | |
1312 | if (second_timeout || xhci->xhc_state & XHCI_STATE_REMOVING) { | |
3425aa03 MN |
1313 | xhci_dbg(xhci, "command timed out twice, ring start fail?\n"); |
1314 | xhci_cleanup_command_queue(xhci); | |
4dea7077 LB |
1315 | |
1316 | goto time_out_completed; | |
3425aa03 MN |
1317 | } |
1318 | ||
c311e391 MN |
1319 | /* command timeout on stopped ring, ring can't be aborted */ |
1320 | xhci_dbg(xhci, "Command timeout on stopped ring\n"); | |
1321 | xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); | |
4dea7077 LB |
1322 | |
1323 | time_out_completed: | |
c311e391 MN |
1324 | spin_unlock_irqrestore(&xhci->lock, flags); |
1325 | return; | |
1326 | } | |
1327 | ||
7f84eef0 SS |
1328 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1329 | struct xhci_event_cmd *event) | |
1330 | { | |
28ccd296 | 1331 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1332 | u64 cmd_dma; |
1333 | dma_addr_t cmd_dequeue_dma; | |
e7a79a1d | 1334 | u32 cmd_comp_code; |
9124b121 | 1335 | union xhci_trb *cmd_trb; |
c9aa1a2d | 1336 | struct xhci_command *cmd; |
b54fc46d | 1337 | u32 cmd_type; |
7f84eef0 | 1338 | |
28ccd296 | 1339 | cmd_dma = le64_to_cpu(event->cmd_trb); |
9124b121 | 1340 | cmd_trb = xhci->cmd_ring->dequeue; |
23e3be11 | 1341 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
9124b121 | 1342 | cmd_trb); |
f4c8f03c LB |
1343 | /* |
1344 | * Check whether the completion event is for our internal kept | |
1345 | * command. | |
1346 | */ | |
1347 | if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) { | |
1348 | xhci_warn(xhci, | |
1349 | "ERROR mismatched command completion event\n"); | |
7f84eef0 SS |
1350 | return; |
1351 | } | |
b63f4053 | 1352 | |
c9aa1a2d MN |
1353 | cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list); |
1354 | ||
cb4d5ce5 | 1355 | cancel_delayed_work(&xhci->cmd_timer); |
c311e391 | 1356 | |
9124b121 | 1357 | trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event); |
63a23b9a | 1358 | |
e7a79a1d | 1359 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
c311e391 MN |
1360 | |
1361 | /* If CMD ring stopped we own the trbs between enqueue and dequeue */ | |
1362 | if (cmd_comp_code == COMP_CMD_STOP) { | |
1363 | xhci_handle_stopped_cmd_ring(xhci, cmd); | |
1364 | return; | |
1365 | } | |
33be1265 MN |
1366 | |
1367 | if (cmd->command_trb != xhci->cmd_ring->dequeue) { | |
1368 | xhci_err(xhci, | |
1369 | "Command completion event does not match command\n"); | |
1370 | return; | |
1371 | } | |
1372 | ||
c311e391 MN |
1373 | /* |
1374 | * Host aborted the command ring, check if the current command was | |
1375 | * supposed to be aborted, otherwise continue normally. | |
1376 | * The command ring is stopped now, but the xHC will issue a Command | |
1377 | * Ring Stopped event which will cause us to restart it. | |
1378 | */ | |
1379 | if (cmd_comp_code == COMP_CMD_ABORT) { | |
1380 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
2a7cfdf3 BW |
1381 | if (cmd->status == COMP_CMD_ABORT) { |
1382 | if (xhci->current_cmd == cmd) | |
1383 | xhci->current_cmd = NULL; | |
c311e391 | 1384 | goto event_handled; |
2a7cfdf3 | 1385 | } |
b63f4053 EF |
1386 | } |
1387 | ||
b54fc46d XR |
1388 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
1389 | switch (cmd_type) { | |
1390 | case TRB_ENABLE_SLOT: | |
c2d3d49b | 1391 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code); |
3ffbba95 | 1392 | break; |
b54fc46d | 1393 | case TRB_DISABLE_SLOT: |
6c02dd14 | 1394 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
3ffbba95 | 1395 | break; |
b54fc46d | 1396 | case TRB_CONFIG_EP: |
9ea1833e MN |
1397 | if (!cmd->completion) |
1398 | xhci_handle_cmd_config_ep(xhci, slot_id, event, | |
1399 | cmd_comp_code); | |
f94e0186 | 1400 | break; |
b54fc46d | 1401 | case TRB_EVAL_CONTEXT: |
2d3f1fac | 1402 | break; |
b54fc46d | 1403 | case TRB_ADDR_DEV: |
3ffbba95 | 1404 | break; |
b54fc46d | 1405 | case TRB_STOP_RING: |
b8200c94 XR |
1406 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1407 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
1408 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); | |
ae636747 | 1409 | break; |
b54fc46d | 1410 | case TRB_SET_DEQ: |
b8200c94 XR |
1411 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1412 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1413 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
ae636747 | 1414 | break; |
b54fc46d | 1415 | case TRB_CMD_NOOP: |
c311e391 MN |
1416 | /* Is this an aborted command turned to NO-OP? */ |
1417 | if (cmd->status == COMP_CMD_STOP) | |
1418 | cmd_comp_code = COMP_CMD_STOP; | |
7f84eef0 | 1419 | break; |
b54fc46d | 1420 | case TRB_RESET_EP: |
b8200c94 XR |
1421 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1422 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1423 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
a1587d97 | 1424 | break; |
b54fc46d | 1425 | case TRB_RESET_DEV: |
6fcfb0d6 MN |
1426 | /* SLOT_ID field in reset device cmd completion event TRB is 0. |
1427 | * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) | |
1428 | */ | |
1429 | slot_id = TRB_TO_SLOT_ID( | |
1430 | le32_to_cpu(cmd_trb->generic.field[3])); | |
f681321b | 1431 | xhci_handle_cmd_reset_dev(xhci, slot_id, event); |
2a8f82c4 | 1432 | break; |
b54fc46d | 1433 | case TRB_NEC_GET_FW: |
2c070821 | 1434 | xhci_handle_cmd_nec_get_fw(xhci, event); |
0238634d | 1435 | break; |
7f84eef0 SS |
1436 | default: |
1437 | /* Skip over unknown commands on the event ring */ | |
f4c8f03c | 1438 | xhci_info(xhci, "INFO unknown command type %d\n", cmd_type); |
7f84eef0 SS |
1439 | break; |
1440 | } | |
c9aa1a2d | 1441 | |
c311e391 MN |
1442 | /* restart timer if this wasn't the last command */ |
1443 | if (cmd->cmd_list.next != &xhci->cmd_list) { | |
1444 | xhci->current_cmd = list_entry(cmd->cmd_list.next, | |
1445 | struct xhci_command, cmd_list); | |
cb4d5ce5 | 1446 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
2b985467 LB |
1447 | } else if (xhci->current_cmd == cmd) { |
1448 | xhci->current_cmd = NULL; | |
c311e391 MN |
1449 | } |
1450 | ||
1451 | event_handled: | |
9ea1833e | 1452 | xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); |
c9aa1a2d | 1453 | |
3b72fca0 | 1454 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1455 | } |
1456 | ||
0238634d SS |
1457 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1458 | union xhci_trb *event) | |
1459 | { | |
1460 | u32 trb_type; | |
1461 | ||
28ccd296 | 1462 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
0238634d SS |
1463 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1464 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1465 | handle_cmd_completion(xhci, &event->event_cmd); | |
1466 | } | |
1467 | ||
f6ff0ac8 SS |
1468 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
1469 | * port registers -- USB 3.0 and USB 2.0). | |
1470 | * | |
1471 | * Returns a zero-based port number, which is suitable for indexing into each of | |
1472 | * the split roothubs' port arrays and bus state arrays. | |
d0cd5d48 | 1473 | * Add one to it in order to call xhci_find_slot_id_by_port. |
f6ff0ac8 SS |
1474 | */ |
1475 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, | |
1476 | struct xhci_hcd *xhci, u32 port_id) | |
1477 | { | |
1478 | unsigned int i; | |
1479 | unsigned int num_similar_speed_ports = 0; | |
1480 | ||
1481 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], | |
1482 | * and usb2_ports are 0-based indexes. Count the number of similar | |
1483 | * speed ports, up to 1 port before this port. | |
1484 | */ | |
1485 | for (i = 0; i < (port_id - 1); i++) { | |
1486 | u8 port_speed = xhci->port_array[i]; | |
1487 | ||
1488 | /* | |
1489 | * Skip ports that don't have known speeds, or have duplicate | |
1490 | * Extended Capabilities port speed entries. | |
1491 | */ | |
22e04870 | 1492 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
1493 | continue; |
1494 | ||
1495 | /* | |
1496 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
1497 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
1498 | * matches the device speed, it's a similar speed port. | |
1499 | */ | |
b50107bb | 1500 | if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3)) |
f6ff0ac8 SS |
1501 | num_similar_speed_ports++; |
1502 | } | |
1503 | return num_similar_speed_ports; | |
1504 | } | |
1505 | ||
623bef9e SS |
1506 | static void handle_device_notification(struct xhci_hcd *xhci, |
1507 | union xhci_trb *event) | |
1508 | { | |
1509 | u32 slot_id; | |
4ee823b8 | 1510 | struct usb_device *udev; |
623bef9e | 1511 | |
7e76ad43 | 1512 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
4ee823b8 | 1513 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1514 | xhci_warn(xhci, "Device Notification event for " |
1515 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1516 | return; |
1517 | } | |
1518 | ||
1519 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1520 | slot_id); | |
1521 | udev = xhci->devs[slot_id]->udev; | |
1522 | if (udev && udev->parent) | |
1523 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1524 | } |
1525 | ||
0f2a7930 SS |
1526 | static void handle_port_status(struct xhci_hcd *xhci, |
1527 | union xhci_trb *event) | |
1528 | { | |
f6ff0ac8 | 1529 | struct usb_hcd *hcd; |
0f2a7930 | 1530 | u32 port_id; |
56192531 | 1531 | u32 temp, temp1; |
518e848e | 1532 | int max_ports; |
56192531 | 1533 | int slot_id; |
5308a91b | 1534 | unsigned int faked_port_index; |
f6ff0ac8 | 1535 | u8 major_revision; |
20b67cf5 | 1536 | struct xhci_bus_state *bus_state; |
28ccd296 | 1537 | __le32 __iomem **port_array; |
386139d7 | 1538 | bool bogus_port_status = false; |
0f2a7930 SS |
1539 | |
1540 | /* Port status change events always have a successful completion code */ | |
f4c8f03c LB |
1541 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) |
1542 | xhci_warn(xhci, | |
1543 | "WARN: xHC returned failed port status event\n"); | |
1544 | ||
28ccd296 | 1545 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
0f2a7930 SS |
1546 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
1547 | ||
518e848e SS |
1548 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1549 | if ((port_id <= 0) || (port_id > max_ports)) { | |
56192531 | 1550 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
09ce0c0c PC |
1551 | inc_deq(xhci, xhci->event_ring); |
1552 | return; | |
56192531 AX |
1553 | } |
1554 | ||
f6ff0ac8 SS |
1555 | /* Figure out which usb_hcd this port is attached to: |
1556 | * is it a USB 3.0 port or a USB 2.0/1.1 port? | |
1557 | */ | |
1558 | major_revision = xhci->port_array[port_id - 1]; | |
09ce0c0c PC |
1559 | |
1560 | /* Find the right roothub. */ | |
1561 | hcd = xhci_to_hcd(xhci); | |
b50107bb | 1562 | if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3)) |
09ce0c0c PC |
1563 | hcd = xhci->shared_hcd; |
1564 | ||
f6ff0ac8 SS |
1565 | if (major_revision == 0) { |
1566 | xhci_warn(xhci, "Event for port %u not in " | |
1567 | "Extended Capabilities, ignoring.\n", | |
1568 | port_id); | |
386139d7 | 1569 | bogus_port_status = true; |
f6ff0ac8 | 1570 | goto cleanup; |
5308a91b | 1571 | } |
22e04870 | 1572 | if (major_revision == DUPLICATE_ENTRY) { |
f6ff0ac8 SS |
1573 | xhci_warn(xhci, "Event for port %u duplicated in" |
1574 | "Extended Capabilities, ignoring.\n", | |
1575 | port_id); | |
386139d7 | 1576 | bogus_port_status = true; |
f6ff0ac8 SS |
1577 | goto cleanup; |
1578 | } | |
1579 | ||
1580 | /* | |
1581 | * Hardware port IDs reported by a Port Status Change Event include USB | |
1582 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a | |
1583 | * resume event, but we first need to translate the hardware port ID | |
1584 | * into the index into the ports on the correct split roothub, and the | |
1585 | * correct bus_state structure. | |
1586 | */ | |
f6ff0ac8 | 1587 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
b50107bb | 1588 | if (hcd->speed >= HCD_USB3) |
f6ff0ac8 SS |
1589 | port_array = xhci->usb3_ports; |
1590 | else | |
1591 | port_array = xhci->usb2_ports; | |
1592 | /* Find the faked port hub number */ | |
1593 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, | |
1594 | port_id); | |
5308a91b | 1595 | |
b0ba9720 | 1596 | temp = readl(port_array[faked_port_index]); |
7111ebc9 | 1597 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1598 | xhci_dbg(xhci, "resume root hub\n"); |
1599 | usb_hcd_resume_root_hub(hcd); | |
1600 | } | |
1601 | ||
b50107bb | 1602 | if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE) |
fac4271d ZJC |
1603 | bus_state->port_remote_wakeup &= ~(1 << faked_port_index); |
1604 | ||
56192531 AX |
1605 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { |
1606 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | |
1607 | ||
b0ba9720 | 1608 | temp1 = readl(&xhci->op_regs->command); |
56192531 AX |
1609 | if (!(temp1 & CMD_RUN)) { |
1610 | xhci_warn(xhci, "xHC is not running.\n"); | |
1611 | goto cleanup; | |
1612 | } | |
1613 | ||
2338b9e4 | 1614 | if (DEV_SUPERSPEED_ANY(temp)) { |
d93814cf | 1615 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1616 | /* Set a flag to say the port signaled remote wakeup, |
1617 | * so we can tell the difference between the end of | |
1618 | * device and host initiated resume. | |
1619 | */ | |
1620 | bus_state->port_remote_wakeup |= 1 << faked_port_index; | |
d93814cf SS |
1621 | xhci_test_and_clear_bit(xhci, port_array, |
1622 | faked_port_index, PORT_PLC); | |
c9682dff AX |
1623 | xhci_set_link_state(xhci, port_array, faked_port_index, |
1624 | XDEV_U0); | |
d93814cf SS |
1625 | /* Need to wait until the next link state change |
1626 | * indicates the device is actually in U0. | |
1627 | */ | |
1628 | bogus_port_status = true; | |
1629 | goto cleanup; | |
f69115fd MN |
1630 | } else if (!test_bit(faked_port_index, |
1631 | &bus_state->resuming_ports)) { | |
56192531 | 1632 | xhci_dbg(xhci, "resume HS port %d\n", port_id); |
f6ff0ac8 | 1633 | bus_state->resume_done[faked_port_index] = jiffies + |
b9e45188 | 1634 | msecs_to_jiffies(USB_RESUME_TIMEOUT); |
f370b996 | 1635 | set_bit(faked_port_index, &bus_state->resuming_ports); |
56192531 | 1636 | mod_timer(&hcd->rh_timer, |
f6ff0ac8 | 1637 | bus_state->resume_done[faked_port_index]); |
56192531 AX |
1638 | /* Do the rest in GetPortStatus */ |
1639 | } | |
1640 | } | |
d93814cf SS |
1641 | |
1642 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && | |
2338b9e4 | 1643 | DEV_SUPERSPEED_ANY(temp)) { |
d93814cf | 1644 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); |
4ee823b8 SS |
1645 | /* We've just brought the device into U0 through either the |
1646 | * Resume state after a device remote wakeup, or through the | |
1647 | * U3Exit state after a host-initiated resume. If it's a device | |
1648 | * initiated remote wake, don't pass up the link state change, | |
1649 | * so the roothub behavior is consistent with external | |
1650 | * USB 3.0 hub behavior. | |
1651 | */ | |
d93814cf SS |
1652 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1653 | faked_port_index + 1); | |
1654 | if (slot_id && xhci->devs[slot_id]) | |
1655 | xhci_ring_device(xhci, slot_id); | |
ba7b5c22 | 1656 | if (bus_state->port_remote_wakeup & (1 << faked_port_index)) { |
4ee823b8 SS |
1657 | bus_state->port_remote_wakeup &= |
1658 | ~(1 << faked_port_index); | |
1659 | xhci_test_and_clear_bit(xhci, port_array, | |
1660 | faked_port_index, PORT_PLC); | |
1661 | usb_wakeup_notification(hcd->self.root_hub, | |
1662 | faked_port_index + 1); | |
1663 | bogus_port_status = true; | |
1664 | goto cleanup; | |
1665 | } | |
d93814cf | 1666 | } |
56192531 | 1667 | |
8b3d4570 SS |
1668 | /* |
1669 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or | |
1670 | * RExit to a disconnect state). If so, let the the driver know it's | |
1671 | * out of the RExit state. | |
1672 | */ | |
2338b9e4 | 1673 | if (!DEV_SUPERSPEED_ANY(temp) && |
8b3d4570 SS |
1674 | test_and_clear_bit(faked_port_index, |
1675 | &bus_state->rexit_ports)) { | |
1676 | complete(&bus_state->rexit_done[faked_port_index]); | |
1677 | bogus_port_status = true; | |
1678 | goto cleanup; | |
1679 | } | |
1680 | ||
b50107bb | 1681 | if (hcd->speed < HCD_USB3) |
6fd45621 AX |
1682 | xhci_test_and_clear_bit(xhci, port_array, faked_port_index, |
1683 | PORT_PLC); | |
1684 | ||
56192531 | 1685 | cleanup: |
0f2a7930 | 1686 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 1687 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 1688 | |
386139d7 SS |
1689 | /* Don't make the USB core poll the roothub if we got a bad port status |
1690 | * change event. Besides, at that point we can't tell which roothub | |
1691 | * (USB 2.0 or USB 3.0) to kick. | |
1692 | */ | |
1693 | if (bogus_port_status) | |
1694 | return; | |
1695 | ||
c52804a4 SS |
1696 | /* |
1697 | * xHCI port-status-change events occur when the "or" of all the | |
1698 | * status-change bits in the portsc register changes from 0 to 1. | |
1699 | * New status changes won't cause an event if any other change | |
1700 | * bits are still set. When an event occurs, switch over to | |
1701 | * polling to avoid losing status changes. | |
1702 | */ | |
1703 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1704 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1705 | spin_unlock(&xhci->lock); |
1706 | /* Pass this up to the core */ | |
f6ff0ac8 | 1707 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
1708 | spin_lock(&xhci->lock); |
1709 | } | |
1710 | ||
d0e96f5a SS |
1711 | /* |
1712 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1713 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1714 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1715 | * returns 0. | |
1716 | */ | |
cffb9be8 HG |
1717 | struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, |
1718 | struct xhci_segment *start_seg, | |
d0e96f5a SS |
1719 | union xhci_trb *start_trb, |
1720 | union xhci_trb *end_trb, | |
cffb9be8 HG |
1721 | dma_addr_t suspect_dma, |
1722 | bool debug) | |
d0e96f5a SS |
1723 | { |
1724 | dma_addr_t start_dma; | |
1725 | dma_addr_t end_seg_dma; | |
1726 | dma_addr_t end_trb_dma; | |
1727 | struct xhci_segment *cur_seg; | |
1728 | ||
23e3be11 | 1729 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1730 | cur_seg = start_seg; |
1731 | ||
1732 | do { | |
2fa88daa | 1733 | if (start_dma == 0) |
326b4810 | 1734 | return NULL; |
ae636747 | 1735 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1736 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1737 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1738 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1739 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a | 1740 | |
cffb9be8 HG |
1741 | if (debug) |
1742 | xhci_warn(xhci, | |
1743 | "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", | |
1744 | (unsigned long long)suspect_dma, | |
1745 | (unsigned long long)start_dma, | |
1746 | (unsigned long long)end_trb_dma, | |
1747 | (unsigned long long)cur_seg->dma, | |
1748 | (unsigned long long)end_seg_dma); | |
1749 | ||
d0e96f5a SS |
1750 | if (end_trb_dma > 0) { |
1751 | /* The end TRB is in this segment, so suspect should be here */ | |
1752 | if (start_dma <= end_trb_dma) { | |
1753 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1754 | return cur_seg; | |
1755 | } else { | |
1756 | /* Case for one segment with | |
1757 | * a TD wrapped around to the top | |
1758 | */ | |
1759 | if ((suspect_dma >= start_dma && | |
1760 | suspect_dma <= end_seg_dma) || | |
1761 | (suspect_dma >= cur_seg->dma && | |
1762 | suspect_dma <= end_trb_dma)) | |
1763 | return cur_seg; | |
1764 | } | |
326b4810 | 1765 | return NULL; |
d0e96f5a SS |
1766 | } else { |
1767 | /* Might still be somewhere in this segment */ | |
1768 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1769 | return cur_seg; | |
1770 | } | |
1771 | cur_seg = cur_seg->next; | |
23e3be11 | 1772 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1773 | } while (cur_seg != start_seg); |
d0e96f5a | 1774 | |
326b4810 | 1775 | return NULL; |
d0e96f5a SS |
1776 | } |
1777 | ||
bcef3fd5 SS |
1778 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1779 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1780 | unsigned int stream_id, |
f97c08ae | 1781 | struct xhci_td *td, union xhci_trb *ep_trb) |
bcef3fd5 SS |
1782 | { |
1783 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
ddba5cd0 MN |
1784 | struct xhci_command *command; |
1785 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
1786 | if (!command) | |
1787 | return; | |
1788 | ||
d0167ad2 | 1789 | ep->ep_state |= EP_HALTED; |
e9df17eb | 1790 | ep->stopped_stream = stream_id; |
1624ae1c | 1791 | |
ddba5cd0 | 1792 | xhci_queue_reset_ep(xhci, command, slot_id, ep_index); |
d97b4f8d | 1793 | xhci_cleanup_stalled_ring(xhci, ep_index, td); |
1624ae1c | 1794 | |
5e5cf6fc | 1795 | ep->stopped_stream = 0; |
1624ae1c | 1796 | |
bcef3fd5 SS |
1797 | xhci_ring_cmd_db(xhci); |
1798 | } | |
1799 | ||
1800 | /* Check if an error has halted the endpoint ring. The class driver will | |
1801 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1802 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1803 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1804 | * Ring Dequeue Pointer command manually. | |
1805 | */ | |
1806 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1807 | struct xhci_ep_ctx *ep_ctx, | |
1808 | unsigned int trb_comp_code) | |
1809 | { | |
1810 | /* TRB completion codes that may require a manual halt cleanup */ | |
1811 | if (trb_comp_code == COMP_TX_ERR || | |
1812 | trb_comp_code == COMP_BABBLE || | |
1813 | trb_comp_code == COMP_SPLIT_ERR) | |
d4fc8bf5 | 1814 | /* The 0.95 spec says a babbling control endpoint |
bcef3fd5 SS |
1815 | * is not halted. The 0.96 spec says it is. Some HW |
1816 | * claims to be 0.95 compliant, but it halts the control | |
1817 | * endpoint anyway. Check if a babble halted the | |
1818 | * endpoint. | |
1819 | */ | |
5071e6b2 | 1820 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED) |
bcef3fd5 SS |
1821 | return 1; |
1822 | ||
1823 | return 0; | |
1824 | } | |
1825 | ||
b45b5069 SS |
1826 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1827 | { | |
1828 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1829 | /* Vendor defined "informational" completion code, | |
1830 | * treat as not-an-error. | |
1831 | */ | |
1832 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1833 | trb_comp_code); | |
1834 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1835 | return 1; | |
1836 | } | |
1837 | return 0; | |
1838 | } | |
1839 | ||
4422da61 AX |
1840 | /* |
1841 | * Finish the td processing, remove the td from td list; | |
1842 | * Return 1 if the urb can be given back. | |
1843 | */ | |
1844 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 1845 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
4422da61 AX |
1846 | struct xhci_virt_ep *ep, int *status, bool skip) |
1847 | { | |
1848 | struct xhci_virt_device *xdev; | |
1849 | struct xhci_ring *ep_ring; | |
1850 | unsigned int slot_id; | |
1851 | int ep_index; | |
1852 | struct urb *urb = NULL; | |
1853 | struct xhci_ep_ctx *ep_ctx; | |
8e51adcc | 1854 | struct urb_priv *urb_priv; |
4422da61 AX |
1855 | u32 trb_comp_code; |
1856 | ||
28ccd296 | 1857 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
4422da61 | 1858 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1859 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1860 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
4422da61 | 1861 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1862 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
4422da61 AX |
1863 | |
1864 | if (skip) | |
1865 | goto td_cleanup; | |
1866 | ||
40a3b775 LB |
1867 | if (trb_comp_code == COMP_STOP_INVAL || |
1868 | trb_comp_code == COMP_STOP || | |
1869 | trb_comp_code == COMP_STOP_SHORT) { | |
4422da61 AX |
1870 | /* The Endpoint Stop Command completion will take care of any |
1871 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1872 | * the ring dequeue pointer or take this TD off any lists yet. | |
1873 | */ | |
1874 | ep->stopped_td = td; | |
4422da61 | 1875 | return 0; |
69defe04 MN |
1876 | } |
1877 | if (trb_comp_code == COMP_STALL || | |
1878 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, | |
1879 | trb_comp_code)) { | |
1880 | /* Issue a reset endpoint command to clear the host side | |
1881 | * halt, followed by a set dequeue command to move the | |
1882 | * dequeue pointer past the TD. | |
1883 | * The class driver clears the device side halt later. | |
1884 | */ | |
1885 | xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, | |
f97c08ae | 1886 | ep_ring->stream_id, td, ep_trb); |
4422da61 | 1887 | } else { |
69defe04 MN |
1888 | /* Update ring dequeue pointer */ |
1889 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 | 1890 | inc_deq(xhci, ep_ring); |
69defe04 MN |
1891 | inc_deq(xhci, ep_ring); |
1892 | } | |
4422da61 AX |
1893 | |
1894 | td_cleanup: | |
69defe04 MN |
1895 | /* Clean up the endpoint's TD list */ |
1896 | urb = td->urb; | |
1897 | urb_priv = urb->hcpriv; | |
1898 | ||
f9c589e1 MN |
1899 | /* if a bounce buffer was used to align this td then unmap it */ |
1900 | if (td->bounce_seg) | |
1901 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); | |
1902 | ||
69defe04 MN |
1903 | /* Do one last check of the actual transfer length. |
1904 | * If the host controller said we transferred more data than the buffer | |
1905 | * length, urb->actual_length will be a very big number (since it's | |
1906 | * unsigned). Play it safe and say we didn't transfer anything. | |
1907 | */ | |
1908 | if (urb->actual_length > urb->transfer_buffer_length) { | |
2a72126d MN |
1909 | xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", |
1910 | urb->transfer_buffer_length, urb->actual_length); | |
69defe04 | 1911 | urb->actual_length = 0; |
2a72126d | 1912 | *status = 0; |
69defe04 MN |
1913 | } |
1914 | list_del_init(&td->td_list); | |
1915 | /* Was this TD slated to be cancelled but completed anyway? */ | |
1916 | if (!list_empty(&td->cancelled_td_list)) | |
1917 | list_del_init(&td->cancelled_td_list); | |
1918 | ||
2a72126d | 1919 | inc_td_cnt(urb); |
69defe04 | 1920 | /* Giveback the urb when all the tds are completed */ |
2a72126d MN |
1921 | if (last_td_in_urb(td)) { |
1922 | if ((urb->actual_length != urb->transfer_buffer_length && | |
1923 | (urb->transfer_flags & URB_SHORT_NOT_OK)) || | |
1924 | (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) | |
1925 | xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", | |
1926 | urb, urb->actual_length, | |
1927 | urb->transfer_buffer_length, *status); | |
1928 | ||
1929 | /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ | |
1930 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
1931 | *status = 0; | |
1932 | xhci_giveback_urb_in_irq(xhci, td, *status); | |
4422da61 | 1933 | } |
0c03d89d | 1934 | return 0; |
4422da61 AX |
1935 | } |
1936 | ||
30a65b45 MN |
1937 | /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */ |
1938 | static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
1939 | union xhci_trb *stop_trb) | |
1940 | { | |
1941 | u32 sum; | |
1942 | union xhci_trb *trb = ring->dequeue; | |
1943 | struct xhci_segment *seg = ring->deq_seg; | |
1944 | ||
1945 | for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) { | |
1946 | if (!trb_is_noop(trb) && !trb_is_link(trb)) | |
1947 | sum += TRB_LEN(le32_to_cpu(trb->generic.field[2])); | |
1948 | } | |
1949 | return sum; | |
1950 | } | |
1951 | ||
8af56be1 AX |
1952 | /* |
1953 | * Process control tds, update urb status and actual_length. | |
1954 | */ | |
1955 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 1956 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
8af56be1 AX |
1957 | struct xhci_virt_ep *ep, int *status) |
1958 | { | |
1959 | struct xhci_virt_device *xdev; | |
1960 | struct xhci_ring *ep_ring; | |
1961 | unsigned int slot_id; | |
1962 | int ep_index; | |
1963 | struct xhci_ep_ctx *ep_ctx; | |
1964 | u32 trb_comp_code; | |
0b6c324c MN |
1965 | u32 remaining, requested; |
1966 | bool on_data_stage; | |
8af56be1 | 1967 | |
28ccd296 | 1968 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
8af56be1 | 1969 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1970 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1971 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
8af56be1 | 1972 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1973 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
0b6c324c MN |
1974 | requested = td->urb->transfer_buffer_length; |
1975 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
1976 | ||
1977 | /* not setup (dequeue), or status stage means we are at data stage */ | |
f97c08ae | 1978 | on_data_stage = (ep_trb != ep_ring->dequeue && ep_trb != td->last_trb); |
8af56be1 | 1979 | |
8af56be1 AX |
1980 | switch (trb_comp_code) { |
1981 | case COMP_SUCCESS: | |
f97c08ae | 1982 | if (ep_trb != td->last_trb) { |
0b6c324c MN |
1983 | xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n", |
1984 | on_data_stage ? "data" : "setup"); | |
8af56be1 | 1985 | *status = -ESHUTDOWN; |
0b6c324c | 1986 | break; |
8af56be1 | 1987 | } |
0b6c324c | 1988 | *status = 0; |
8af56be1 AX |
1989 | break; |
1990 | case COMP_SHORT_TX: | |
0b6c324c | 1991 | *status = 0; |
8af56be1 | 1992 | break; |
40a3b775 | 1993 | case COMP_STOP_SHORT: |
0b6c324c MN |
1994 | if (on_data_stage) |
1995 | td->urb->actual_length = remaining; | |
40a3b775 | 1996 | else |
0b6c324c MN |
1997 | xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); |
1998 | goto finish_td; | |
3abeca99 | 1999 | case COMP_STOP: |
0b6c324c MN |
2000 | if (on_data_stage) |
2001 | td->urb->actual_length = requested - remaining; | |
2002 | goto finish_td; | |
40a3b775 | 2003 | case COMP_STOP_INVAL: |
0b6c324c | 2004 | goto finish_td; |
8af56be1 AX |
2005 | default: |
2006 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
0b6c324c | 2007 | ep_ctx, trb_comp_code)) |
8af56be1 | 2008 | break; |
0b6c324c MN |
2009 | xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n", |
2010 | trb_comp_code, ep_index); | |
8af56be1 AX |
2011 | /* else fall through */ |
2012 | case COMP_STALL: | |
2013 | /* Did we transfer part of the data (middle) phase? */ | |
0b6c324c MN |
2014 | if (on_data_stage) |
2015 | td->urb->actual_length = requested - remaining; | |
22ae47e6 | 2016 | else if (!td->urb_length_set) |
8af56be1 | 2017 | td->urb->actual_length = 0; |
0b6c324c | 2018 | goto finish_td; |
8af56be1 | 2019 | } |
0b6c324c MN |
2020 | |
2021 | /* stopped at setup stage, no data transferred */ | |
f97c08ae | 2022 | if (ep_trb == ep_ring->dequeue) |
0b6c324c MN |
2023 | goto finish_td; |
2024 | ||
8af56be1 | 2025 | /* |
0b6c324c MN |
2026 | * if on data stage then update the actual_length of the URB and flag it |
2027 | * as set, so it won't be overwritten in the event for the last TRB. | |
8af56be1 | 2028 | */ |
0b6c324c MN |
2029 | if (on_data_stage) { |
2030 | td->urb_length_set = true; | |
2031 | td->urb->actual_length = requested - remaining; | |
2032 | xhci_dbg(xhci, "Waiting for status stage event\n"); | |
2033 | return 0; | |
8af56be1 AX |
2034 | } |
2035 | ||
0b6c324c MN |
2036 | /* at status stage */ |
2037 | if (!td->urb_length_set) | |
2038 | td->urb->actual_length = requested; | |
2039 | ||
2040 | finish_td: | |
f97c08ae | 2041 | return finish_td(xhci, td, ep_trb, event, ep, status, false); |
8af56be1 AX |
2042 | } |
2043 | ||
04e51901 AX |
2044 | /* |
2045 | * Process isochronous tds, update urb packet status and actual_length. | |
2046 | */ | |
2047 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 2048 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
04e51901 AX |
2049 | struct xhci_virt_ep *ep, int *status) |
2050 | { | |
2051 | struct xhci_ring *ep_ring; | |
2052 | struct urb_priv *urb_priv; | |
2053 | int idx; | |
926008c9 | 2054 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 2055 | u32 trb_comp_code; |
36da3a1d MN |
2056 | bool sum_trbs_for_length = false; |
2057 | u32 remaining, requested, ep_trb_len; | |
2058 | int short_framestatus; | |
04e51901 | 2059 | |
28ccd296 ME |
2060 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2061 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
04e51901 AX |
2062 | urb_priv = td->urb->hcpriv; |
2063 | idx = urb_priv->td_cnt; | |
926008c9 | 2064 | frame = &td->urb->iso_frame_desc[idx]; |
36da3a1d MN |
2065 | requested = frame->length; |
2066 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2067 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); | |
2068 | short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
2069 | -EREMOTEIO : 0; | |
04e51901 | 2070 | |
926008c9 DT |
2071 | /* handle completion code */ |
2072 | switch (trb_comp_code) { | |
2073 | case COMP_SUCCESS: | |
36da3a1d MN |
2074 | if (remaining) { |
2075 | frame->status = short_framestatus; | |
2076 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2077 | sum_trbs_for_length = true; | |
1530bbc6 SS |
2078 | break; |
2079 | } | |
36da3a1d MN |
2080 | frame->status = 0; |
2081 | break; | |
926008c9 | 2082 | case COMP_SHORT_TX: |
36da3a1d MN |
2083 | frame->status = short_framestatus; |
2084 | sum_trbs_for_length = true; | |
926008c9 DT |
2085 | break; |
2086 | case COMP_BW_OVER: | |
2087 | frame->status = -ECOMM; | |
926008c9 DT |
2088 | break; |
2089 | case COMP_BUFF_OVER: | |
2090 | case COMP_BABBLE: | |
2091 | frame->status = -EOVERFLOW; | |
926008c9 | 2092 | break; |
f6ba6fe2 | 2093 | case COMP_DEV_ERR: |
926008c9 | 2094 | case COMP_STALL: |
d104d015 | 2095 | frame->status = -EPROTO; |
d104d015 | 2096 | break; |
9c745995 | 2097 | case COMP_TX_ERR: |
926008c9 | 2098 | frame->status = -EPROTO; |
f97c08ae | 2099 | if (ep_trb != td->last_trb) |
d104d015 | 2100 | return 0; |
926008c9 DT |
2101 | break; |
2102 | case COMP_STOP: | |
36da3a1d MN |
2103 | sum_trbs_for_length = true; |
2104 | break; | |
2105 | case COMP_STOP_SHORT: | |
2106 | /* field normally containing residue now contains tranferred */ | |
2107 | frame->status = short_framestatus; | |
2108 | requested = remaining; | |
2109 | break; | |
926008c9 | 2110 | case COMP_STOP_INVAL: |
36da3a1d MN |
2111 | requested = 0; |
2112 | remaining = 0; | |
926008c9 DT |
2113 | break; |
2114 | default: | |
36da3a1d | 2115 | sum_trbs_for_length = true; |
926008c9 DT |
2116 | frame->status = -1; |
2117 | break; | |
04e51901 AX |
2118 | } |
2119 | ||
36da3a1d MN |
2120 | if (sum_trbs_for_length) |
2121 | frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) + | |
2122 | ep_trb_len - remaining; | |
2123 | else | |
2124 | frame->actual_length = requested; | |
04e51901 | 2125 | |
36da3a1d | 2126 | td->urb->actual_length += frame->actual_length; |
04e51901 | 2127 | |
f97c08ae | 2128 | return finish_td(xhci, td, ep_trb, event, ep, status, false); |
04e51901 AX |
2129 | } |
2130 | ||
926008c9 DT |
2131 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
2132 | struct xhci_transfer_event *event, | |
2133 | struct xhci_virt_ep *ep, int *status) | |
2134 | { | |
2135 | struct xhci_ring *ep_ring; | |
2136 | struct urb_priv *urb_priv; | |
2137 | struct usb_iso_packet_descriptor *frame; | |
2138 | int idx; | |
2139 | ||
f6975314 | 2140 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
926008c9 DT |
2141 | urb_priv = td->urb->hcpriv; |
2142 | idx = urb_priv->td_cnt; | |
2143 | frame = &td->urb->iso_frame_desc[idx]; | |
2144 | ||
b3df3f9c | 2145 | /* The transfer is partly done. */ |
926008c9 DT |
2146 | frame->status = -EXDEV; |
2147 | ||
2148 | /* calc actual length */ | |
2149 | frame->actual_length = 0; | |
2150 | ||
2151 | /* Update ring dequeue pointer */ | |
2152 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
2153 | inc_deq(xhci, ep_ring); |
2154 | inc_deq(xhci, ep_ring); | |
926008c9 DT |
2155 | |
2156 | return finish_td(xhci, td, NULL, event, ep, status, true); | |
2157 | } | |
2158 | ||
22405ed2 AX |
2159 | /* |
2160 | * Process bulk and interrupt tds, update urb status and actual_length. | |
2161 | */ | |
2162 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 2163 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
22405ed2 AX |
2164 | struct xhci_virt_ep *ep, int *status) |
2165 | { | |
2166 | struct xhci_ring *ep_ring; | |
22405ed2 | 2167 | u32 trb_comp_code; |
f97c08ae | 2168 | u32 remaining, requested, ep_trb_len; |
22405ed2 | 2169 | |
28ccd296 ME |
2170 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2171 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
30a65b45 | 2172 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
f97c08ae | 2173 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); |
30a65b45 | 2174 | requested = td->urb->transfer_buffer_length; |
22405ed2 AX |
2175 | |
2176 | switch (trb_comp_code) { | |
2177 | case COMP_SUCCESS: | |
30a65b45 | 2178 | /* handle success with untransferred data as short packet */ |
f97c08ae | 2179 | if (ep_trb != td->last_trb || remaining) { |
52ab8685 | 2180 | xhci_warn(xhci, "WARN Successful completion on short TX\n"); |
30a65b45 MN |
2181 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2182 | td->urb->ep->desc.bEndpointAddress, | |
2183 | requested, remaining); | |
22405ed2 | 2184 | } |
52ab8685 | 2185 | *status = 0; |
22405ed2 AX |
2186 | break; |
2187 | case COMP_SHORT_TX: | |
30a65b45 MN |
2188 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2189 | td->urb->ep->desc.bEndpointAddress, | |
2190 | requested, remaining); | |
52ab8685 | 2191 | *status = 0; |
22405ed2 | 2192 | break; |
30a65b45 MN |
2193 | case COMP_STOP_SHORT: |
2194 | td->urb->actual_length = remaining; | |
2195 | goto finish_td; | |
2196 | case COMP_STOP_INVAL: | |
2197 | /* stopped on ep trb with invalid length, exclude it */ | |
f97c08ae | 2198 | ep_trb_len = 0; |
30a65b45 MN |
2199 | remaining = 0; |
2200 | break; | |
22405ed2 | 2201 | default: |
30a65b45 | 2202 | /* do nothing */ |
22405ed2 AX |
2203 | break; |
2204 | } | |
40a3b775 | 2205 | |
f97c08ae | 2206 | if (ep_trb == td->last_trb) |
30a65b45 MN |
2207 | td->urb->actual_length = requested - remaining; |
2208 | else | |
2209 | td->urb->actual_length = | |
f97c08ae MN |
2210 | sum_trb_lengths(xhci, ep_ring, ep_trb) + |
2211 | ep_trb_len - remaining; | |
30a65b45 MN |
2212 | finish_td: |
2213 | if (remaining > requested) { | |
2214 | xhci_warn(xhci, "bad transfer trb length %d in event trb\n", | |
2215 | remaining); | |
22405ed2 | 2216 | td->urb->actual_length = 0; |
22405ed2 | 2217 | } |
f97c08ae | 2218 | return finish_td(xhci, td, ep_trb, event, ep, status, false); |
22405ed2 AX |
2219 | } |
2220 | ||
d0e96f5a SS |
2221 | /* |
2222 | * If this function returns an error condition, it means it got a Transfer | |
2223 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2224 | * At this point, the host controller is probably hosed and should be reset. | |
2225 | */ | |
2226 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2227 | struct xhci_transfer_event *event) | |
ed384bd3 FB |
2228 | __releases(&xhci->lock) |
2229 | __acquires(&xhci->lock) | |
d0e96f5a SS |
2230 | { |
2231 | struct xhci_virt_device *xdev; | |
63a0d9ab | 2232 | struct xhci_virt_ep *ep; |
d0e96f5a | 2233 | struct xhci_ring *ep_ring; |
82d1009f | 2234 | unsigned int slot_id; |
d0e96f5a | 2235 | int ep_index; |
326b4810 | 2236 | struct xhci_td *td = NULL; |
f97c08ae MN |
2237 | dma_addr_t ep_trb_dma; |
2238 | struct xhci_segment *ep_seg; | |
2239 | union xhci_trb *ep_trb; | |
d0e96f5a | 2240 | int status = -EINPROGRESS; |
d115b048 | 2241 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2242 | struct list_head *tmp; |
66d1eebc | 2243 | u32 trb_comp_code; |
c2d7b49f | 2244 | int td_num = 0; |
3b4739b8 | 2245 | bool handling_skipped_tds = false; |
d0e96f5a | 2246 | |
28ccd296 | 2247 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
82d1009f | 2248 | xdev = xhci->devs[slot_id]; |
d0e96f5a SS |
2249 | if (!xdev) { |
2250 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | |
9258c0b2 | 2251 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2252 | (unsigned long long) xhci_trb_virt_to_dma( |
2253 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2254 | xhci->event_ring->dequeue), |
2255 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2256 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2257 | le32_to_cpu(event->transfer_len), | |
2258 | le32_to_cpu(event->flags)); | |
2259 | xhci_dbg(xhci, "Event ring:\n"); | |
2260 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2261 | return -ENODEV; |
2262 | } | |
2263 | ||
2264 | /* Endpoint ID is 1 based, our index is zero based */ | |
28ccd296 | 2265 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
63a0d9ab | 2266 | ep = &xdev->eps[ep_index]; |
28ccd296 | 2267 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
d115b048 | 2268 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
5071e6b2 | 2269 | if (!ep_ring || GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) { |
e9df17eb SS |
2270 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
2271 | "or incorrect stream ring\n"); | |
9258c0b2 | 2272 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2273 | (unsigned long long) xhci_trb_virt_to_dma( |
2274 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2275 | xhci->event_ring->dequeue), |
2276 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2277 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2278 | le32_to_cpu(event->transfer_len), | |
2279 | le32_to_cpu(event->flags)); | |
2280 | xhci_dbg(xhci, "Event ring:\n"); | |
2281 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2282 | return -ENODEV; |
2283 | } | |
2284 | ||
c2d7b49f AX |
2285 | /* Count current td numbers if ep->skip is set */ |
2286 | if (ep->skip) { | |
2287 | list_for_each(tmp, &ep_ring->td_list) | |
2288 | td_num++; | |
2289 | } | |
2290 | ||
f97c08ae | 2291 | ep_trb_dma = le64_to_cpu(event->buffer); |
28ccd296 | 2292 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
986a92d4 | 2293 | /* Look for common error cases */ |
66d1eebc | 2294 | switch (trb_comp_code) { |
b10de142 SS |
2295 | /* Skip codes that require special handling depending on |
2296 | * transfer type | |
2297 | */ | |
2298 | case COMP_SUCCESS: | |
1c11a172 | 2299 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
1530bbc6 SS |
2300 | break; |
2301 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2302 | trb_comp_code = COMP_SHORT_TX; | |
2303 | else | |
8202ce2e SS |
2304 | xhci_warn_ratelimited(xhci, |
2305 | "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n"); | |
b10de142 SS |
2306 | case COMP_SHORT_TX: |
2307 | break; | |
ae636747 SS |
2308 | case COMP_STOP: |
2309 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); | |
2310 | break; | |
2311 | case COMP_STOP_INVAL: | |
2312 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); | |
2313 | break; | |
40a3b775 LB |
2314 | case COMP_STOP_SHORT: |
2315 | xhci_dbg(xhci, "Stopped with short packet transfer detected\n"); | |
2316 | break; | |
b10de142 | 2317 | case COMP_STALL: |
2a9227a5 | 2318 | xhci_dbg(xhci, "Stalled endpoint\n"); |
63a0d9ab | 2319 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
2320 | status = -EPIPE; |
2321 | break; | |
2322 | case COMP_TRB_ERR: | |
2323 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); | |
2324 | status = -EILSEQ; | |
2325 | break; | |
ec74e403 | 2326 | case COMP_SPLIT_ERR: |
b10de142 | 2327 | case COMP_TX_ERR: |
2a9227a5 | 2328 | xhci_dbg(xhci, "Transfer error on endpoint\n"); |
b10de142 SS |
2329 | status = -EPROTO; |
2330 | break; | |
4a73143c | 2331 | case COMP_BABBLE: |
2a9227a5 | 2332 | xhci_dbg(xhci, "Babble error on endpoint\n"); |
4a73143c SS |
2333 | status = -EOVERFLOW; |
2334 | break; | |
b10de142 SS |
2335 | case COMP_DB_ERR: |
2336 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); | |
2337 | status = -ENOSR; | |
2338 | break; | |
986a92d4 AX |
2339 | case COMP_BW_OVER: |
2340 | xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); | |
2341 | break; | |
2342 | case COMP_BUFF_OVER: | |
2343 | xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); | |
2344 | break; | |
2345 | case COMP_UNDERRUN: | |
2346 | /* | |
2347 | * When the Isoch ring is empty, the xHC will generate | |
2348 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2349 | * Underrun Event for OUT Isoch endpoint. | |
2350 | */ | |
2351 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2352 | if (!list_empty(&ep_ring->td_list)) | |
2353 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2354 | "still with TDs queued?\n", | |
28ccd296 ME |
2355 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2356 | ep_index); | |
986a92d4 AX |
2357 | goto cleanup; |
2358 | case COMP_OVERRUN: | |
2359 | xhci_dbg(xhci, "overrun event on endpoint\n"); | |
2360 | if (!list_empty(&ep_ring->td_list)) | |
2361 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2362 | "still with TDs queued?\n", | |
28ccd296 ME |
2363 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2364 | ep_index); | |
986a92d4 | 2365 | goto cleanup; |
f6ba6fe2 AH |
2366 | case COMP_DEV_ERR: |
2367 | xhci_warn(xhci, "WARN: detect an incompatible device"); | |
2368 | status = -EPROTO; | |
2369 | break; | |
d18240db AX |
2370 | case COMP_MISSED_INT: |
2371 | /* | |
2372 | * When encounter missed service error, one or more isoc tds | |
2373 | * may be missed by xHC. | |
2374 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2375 | * short transfer when process the ep_ring next time. | |
2376 | */ | |
2377 | ep->skip = true; | |
2378 | xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); | |
2379 | goto cleanup; | |
3b4739b8 MN |
2380 | case COMP_PING_ERR: |
2381 | ep->skip = true; | |
2382 | xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n"); | |
2383 | goto cleanup; | |
b10de142 | 2384 | default: |
b45b5069 | 2385 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2386 | status = 0; |
2387 | break; | |
2388 | } | |
86cd740a MN |
2389 | xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n", |
2390 | trb_comp_code); | |
986a92d4 AX |
2391 | goto cleanup; |
2392 | } | |
2393 | ||
d18240db AX |
2394 | do { |
2395 | /* This TRB should be in the TD at the head of this ring's | |
2396 | * TD list. | |
2397 | */ | |
2398 | if (list_empty(&ep_ring->td_list)) { | |
a83d6755 SS |
2399 | /* |
2400 | * A stopped endpoint may generate an extra completion | |
2401 | * event if the device was suspended. Don't print | |
2402 | * warnings. | |
2403 | */ | |
2404 | if (!(trb_comp_code == COMP_STOP || | |
2405 | trb_comp_code == COMP_STOP_INVAL)) { | |
2406 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", | |
2407 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), | |
2408 | ep_index); | |
2409 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", | |
2410 | (le32_to_cpu(event->flags) & | |
2411 | TRB_TYPE_BITMASK)>>10); | |
2412 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); | |
2413 | } | |
d18240db AX |
2414 | if (ep->skip) { |
2415 | ep->skip = false; | |
2416 | xhci_dbg(xhci, "td_list is empty while skip " | |
2417 | "flag set. Clear skip flag.\n"); | |
2418 | } | |
d18240db AX |
2419 | goto cleanup; |
2420 | } | |
986a92d4 | 2421 | |
c2d7b49f AX |
2422 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2423 | if (ep->skip && td_num == 0) { | |
2424 | ep->skip = false; | |
2425 | xhci_dbg(xhci, "All tds on the ep_ring skipped. " | |
2426 | "Clear skip flag.\n"); | |
c2d7b49f AX |
2427 | goto cleanup; |
2428 | } | |
2429 | ||
d18240db | 2430 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
c2d7b49f AX |
2431 | if (ep->skip) |
2432 | td_num--; | |
926008c9 | 2433 | |
d18240db | 2434 | /* Is this a TRB in the currently executing TD? */ |
f97c08ae MN |
2435 | ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, |
2436 | td->last_trb, ep_trb_dma, false); | |
e1cf486d AH |
2437 | |
2438 | /* | |
2439 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2440 | * is not in the current TD pointed by ep_ring->dequeue because | |
2441 | * that the hardware dequeue pointer still at the previous TRB | |
2442 | * of the current TD. The previous TRB maybe a Link TD or the | |
2443 | * last TRB of the previous TD. The command completion handle | |
2444 | * will take care the rest. | |
2445 | */ | |
f97c08ae | 2446 | if (!ep_seg && (trb_comp_code == COMP_STOP || |
9a548863 | 2447 | trb_comp_code == COMP_STOP_INVAL)) { |
e1cf486d AH |
2448 | goto cleanup; |
2449 | } | |
2450 | ||
f97c08ae | 2451 | if (!ep_seg) { |
926008c9 DT |
2452 | if (!ep->skip || |
2453 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2454 | /* Some host controllers give a spurious |
2455 | * successful event after a short transfer. | |
2456 | * Ignore it. | |
2457 | */ | |
ddba5cd0 | 2458 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
ad808333 SS |
2459 | ep_ring->last_td_was_short) { |
2460 | ep_ring->last_td_was_short = false; | |
ad808333 SS |
2461 | goto cleanup; |
2462 | } | |
926008c9 DT |
2463 | /* HC is busted, give up! */ |
2464 | xhci_err(xhci, | |
2465 | "ERROR Transfer event TRB DMA ptr not " | |
cffb9be8 HG |
2466 | "part of current TD ep_index %d " |
2467 | "comp_code %u\n", ep_index, | |
2468 | trb_comp_code); | |
2469 | trb_in_td(xhci, ep_ring->deq_seg, | |
2470 | ep_ring->dequeue, td->last_trb, | |
f97c08ae | 2471 | ep_trb_dma, true); |
926008c9 DT |
2472 | return -ESHUTDOWN; |
2473 | } | |
2474 | ||
0c03d89d | 2475 | skip_isoc_td(xhci, td, event, ep, &status); |
926008c9 DT |
2476 | goto cleanup; |
2477 | } | |
ad808333 SS |
2478 | if (trb_comp_code == COMP_SHORT_TX) |
2479 | ep_ring->last_td_was_short = true; | |
2480 | else | |
2481 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2482 | |
2483 | if (ep->skip) { | |
d18240db AX |
2484 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); |
2485 | ep->skip = false; | |
2486 | } | |
678539cf | 2487 | |
f97c08ae MN |
2488 | ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / |
2489 | sizeof(*ep_trb)]; | |
926008c9 DT |
2490 | /* |
2491 | * No-op TRB should not trigger interrupts. | |
f97c08ae | 2492 | * If ep_trb is a no-op TRB, it means the |
926008c9 DT |
2493 | * corresponding TD has been cancelled. Just ignore |
2494 | * the TD. | |
2495 | */ | |
f97c08ae MN |
2496 | if (trb_is_noop(ep_trb)) { |
2497 | xhci_dbg(xhci, "ep_trb is a no-op TRB. Skip it\n"); | |
926008c9 | 2498 | goto cleanup; |
d18240db | 2499 | } |
4422da61 | 2500 | |
0c03d89d | 2501 | /* update the urb's actual_length and give back to the core */ |
d18240db | 2502 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
0c03d89d | 2503 | process_ctrl_td(xhci, td, ep_trb, event, ep, &status); |
04e51901 | 2504 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
0c03d89d | 2505 | process_isoc_td(xhci, td, ep_trb, event, ep, &status); |
d18240db | 2506 | else |
0c03d89d MN |
2507 | process_bulk_intr_td(xhci, td, ep_trb, event, ep, |
2508 | &status); | |
d18240db | 2509 | cleanup: |
3b4739b8 MN |
2510 | handling_skipped_tds = ep->skip && |
2511 | trb_comp_code != COMP_MISSED_INT && | |
2512 | trb_comp_code != COMP_PING_ERR; | |
2513 | ||
d18240db | 2514 | /* |
3b4739b8 MN |
2515 | * Do not update event ring dequeue pointer if we're in a loop |
2516 | * processing missed tds. | |
d18240db | 2517 | */ |
3b4739b8 | 2518 | if (!handling_skipped_tds) |
3b72fca0 | 2519 | inc_deq(xhci, xhci->event_ring); |
d18240db | 2520 | |
d18240db AX |
2521 | /* |
2522 | * If ep->skip is set, it means there are missed tds on the | |
2523 | * endpoint ring need to take care of. | |
2524 | * Process them as short transfer until reach the td pointed by | |
2525 | * the event. | |
2526 | */ | |
3b4739b8 | 2527 | } while (handling_skipped_tds); |
d18240db | 2528 | |
d0e96f5a SS |
2529 | return 0; |
2530 | } | |
2531 | ||
0f2a7930 SS |
2532 | /* |
2533 | * This function handles all OS-owned events on the event ring. It may drop | |
2534 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2535 | * Returns >0 for "possibly more events to process" (caller should call again), |
2536 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2537 | */ |
9dee9a21 | 2538 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2539 | { |
2540 | union xhci_trb *event; | |
0f2a7930 | 2541 | int update_ptrs = 1; |
d0e96f5a | 2542 | int ret; |
7f84eef0 | 2543 | |
f4c8f03c | 2544 | /* Event ring hasn't been allocated yet. */ |
7f84eef0 | 2545 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
f4c8f03c LB |
2546 | xhci_err(xhci, "ERROR event ring not ready\n"); |
2547 | return -ENOMEM; | |
7f84eef0 SS |
2548 | } |
2549 | ||
2550 | event = xhci->event_ring->dequeue; | |
2551 | /* Does the HC or OS own the TRB? */ | |
28ccd296 | 2552 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
f4c8f03c | 2553 | xhci->event_ring->cycle_state) |
9dee9a21 | 2554 | return 0; |
7f84eef0 | 2555 | |
92a3da41 ME |
2556 | /* |
2557 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2558 | * speculative reads of the event's flags/data below. | |
2559 | */ | |
2560 | rmb(); | |
0f2a7930 | 2561 | /* FIXME: Handle more event types. */ |
f4c8f03c | 2562 | switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) { |
7f84eef0 SS |
2563 | case TRB_TYPE(TRB_COMPLETION): |
2564 | handle_cmd_completion(xhci, &event->event_cmd); | |
2565 | break; | |
0f2a7930 SS |
2566 | case TRB_TYPE(TRB_PORT_STATUS): |
2567 | handle_port_status(xhci, event); | |
2568 | update_ptrs = 0; | |
2569 | break; | |
d0e96f5a SS |
2570 | case TRB_TYPE(TRB_TRANSFER): |
2571 | ret = handle_tx_event(xhci, &event->trans_event); | |
f4c8f03c | 2572 | if (ret >= 0) |
d0e96f5a SS |
2573 | update_ptrs = 0; |
2574 | break; | |
623bef9e SS |
2575 | case TRB_TYPE(TRB_DEV_NOTE): |
2576 | handle_device_notification(xhci, event); | |
2577 | break; | |
7f84eef0 | 2578 | default: |
28ccd296 ME |
2579 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2580 | TRB_TYPE(48)) | |
0238634d SS |
2581 | handle_vendor_event(xhci, event); |
2582 | else | |
f4c8f03c LB |
2583 | xhci_warn(xhci, "ERROR unknown event type %d\n", |
2584 | TRB_FIELD_TO_TYPE( | |
2585 | le32_to_cpu(event->event_cmd.flags))); | |
7f84eef0 | 2586 | } |
6f5165cf SS |
2587 | /* Any of the above functions may drop and re-acquire the lock, so check |
2588 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2589 | */ | |
2590 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2591 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2592 | "event handler.\n"); | |
9dee9a21 | 2593 | return 0; |
6f5165cf | 2594 | } |
7f84eef0 | 2595 | |
c06d68b8 SS |
2596 | if (update_ptrs) |
2597 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 2598 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 2599 | |
9dee9a21 ME |
2600 | /* Are there more items on the event ring? Caller will call us again to |
2601 | * check. | |
2602 | */ | |
2603 | return 1; | |
7f84eef0 | 2604 | } |
9032cd52 SS |
2605 | |
2606 | /* | |
2607 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2608 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2609 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2610 | */ | |
2611 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2612 | { | |
2613 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c21599a3 | 2614 | u32 status; |
bda53145 | 2615 | u64 temp_64; |
c06d68b8 SS |
2616 | union xhci_trb *event_ring_deq; |
2617 | dma_addr_t deq; | |
9032cd52 SS |
2618 | |
2619 | spin_lock(&xhci->lock); | |
9032cd52 | 2620 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
b0ba9720 | 2621 | status = readl(&xhci->op_regs->status); |
c21599a3 | 2622 | if (status == 0xffffffff) |
9032cd52 SS |
2623 | goto hw_died; |
2624 | ||
c21599a3 | 2625 | if (!(status & STS_EINT)) { |
9032cd52 | 2626 | spin_unlock(&xhci->lock); |
9032cd52 SS |
2627 | return IRQ_NONE; |
2628 | } | |
27e0dd4d | 2629 | if (status & STS_FATAL) { |
9032cd52 SS |
2630 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2631 | xhci_halt(xhci); | |
2632 | hw_died: | |
9032cd52 | 2633 | spin_unlock(&xhci->lock); |
948fa135 | 2634 | return IRQ_HANDLED; |
9032cd52 SS |
2635 | } |
2636 | ||
bda53145 SS |
2637 | /* |
2638 | * Clear the op reg interrupt status first, | |
2639 | * so we can receive interrupts from other MSI-X interrupters. | |
2640 | * Write 1 to clear the interrupt status. | |
2641 | */ | |
27e0dd4d | 2642 | status |= STS_EINT; |
204b7793 | 2643 | writel(status, &xhci->op_regs->status); |
bda53145 SS |
2644 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
2645 | /* Clear the MSI-X event interrupt status */ | |
2646 | ||
cd70469d | 2647 | if (hcd->irq) { |
c21599a3 SS |
2648 | u32 irq_pending; |
2649 | /* Acknowledge the PCI interrupt */ | |
b0ba9720 | 2650 | irq_pending = readl(&xhci->ir_set->irq_pending); |
4e833c0b | 2651 | irq_pending |= IMAN_IP; |
204b7793 | 2652 | writel(irq_pending, &xhci->ir_set->irq_pending); |
c21599a3 | 2653 | } |
bda53145 | 2654 | |
27a41a83 GKB |
2655 | if (xhci->xhc_state & XHCI_STATE_DYING || |
2656 | xhci->xhc_state & XHCI_STATE_HALTED) { | |
bda53145 SS |
2657 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2658 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2659 | /* Clear the event handler busy flag (RW1C); |
2660 | * the event ring should be empty. | |
bda53145 | 2661 | */ |
f7b2e403 | 2662 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
477632df SS |
2663 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
2664 | &xhci->ir_set->erst_dequeue); | |
c06d68b8 SS |
2665 | spin_unlock(&xhci->lock); |
2666 | ||
2667 | return IRQ_HANDLED; | |
2668 | } | |
2669 | ||
2670 | event_ring_deq = xhci->event_ring->dequeue; | |
2671 | /* FIXME this should be a delayed service routine | |
2672 | * that clears the EHB. | |
2673 | */ | |
9dee9a21 | 2674 | while (xhci_handle_event(xhci) > 0) {} |
bda53145 | 2675 | |
f7b2e403 | 2676 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2677 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2678 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2679 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2680 | xhci->event_ring->dequeue); | |
2681 | if (deq == 0) | |
2682 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2683 | "ring dequeue ptr.\n"); | |
2684 | /* Update HC event ring dequeue pointer */ | |
2685 | temp_64 &= ERST_PTR_MASK; | |
2686 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2687 | } | |
2688 | ||
2689 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2690 | temp_64 |= ERST_EHB; | |
477632df | 2691 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
c06d68b8 | 2692 | |
9032cd52 SS |
2693 | spin_unlock(&xhci->lock); |
2694 | ||
2695 | return IRQ_HANDLED; | |
2696 | } | |
2697 | ||
851ec164 | 2698 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
9032cd52 | 2699 | { |
968b822c | 2700 | return xhci_irq(hcd); |
9032cd52 | 2701 | } |
7f84eef0 | 2702 | |
d0e96f5a SS |
2703 | /**** Endpoint Ring Operations ****/ |
2704 | ||
7f84eef0 SS |
2705 | /* |
2706 | * Generic function for queueing a TRB on a ring. | |
2707 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2708 | * |
2709 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2710 | * prepare_transfer()? | |
7f84eef0 SS |
2711 | */ |
2712 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 2713 | bool more_trbs_coming, |
7f84eef0 SS |
2714 | u32 field1, u32 field2, u32 field3, u32 field4) |
2715 | { | |
2716 | struct xhci_generic_trb *trb; | |
2717 | ||
2718 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
2719 | trb->field[0] = cpu_to_le32(field1); |
2720 | trb->field[1] = cpu_to_le32(field2); | |
2721 | trb->field[2] = cpu_to_le32(field3); | |
2722 | trb->field[3] = cpu_to_le32(field4); | |
3b72fca0 | 2723 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
2724 | } |
2725 | ||
d0e96f5a SS |
2726 | /* |
2727 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2728 | * FIXME allocate segments if the ring is full. | |
2729 | */ | |
2730 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 2731 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 2732 | { |
8dfec614 AX |
2733 | unsigned int num_trbs_needed; |
2734 | ||
d0e96f5a | 2735 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
2736 | switch (ep_state) { |
2737 | case EP_STATE_DISABLED: | |
2738 | /* | |
2739 | * USB core changed config/interfaces without notifying us, | |
2740 | * or hardware is reporting the wrong state. | |
2741 | */ | |
2742 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2743 | return -ENOENT; | |
d0e96f5a | 2744 | case EP_STATE_ERROR: |
c92bcfa7 | 2745 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
2746 | /* FIXME event handling code for error needs to clear it */ |
2747 | /* XXX not sure if this should be -ENOENT or not */ | |
2748 | return -EINVAL; | |
c92bcfa7 SS |
2749 | case EP_STATE_HALTED: |
2750 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
2751 | case EP_STATE_STOPPED: |
2752 | case EP_STATE_RUNNING: | |
2753 | break; | |
2754 | default: | |
2755 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
2756 | /* | |
2757 | * FIXME issue Configure Endpoint command to try to get the HC | |
2758 | * back into a known state. | |
2759 | */ | |
2760 | return -EINVAL; | |
2761 | } | |
8dfec614 AX |
2762 | |
2763 | while (1) { | |
3d4b81ed SS |
2764 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
2765 | break; | |
8dfec614 AX |
2766 | |
2767 | if (ep_ring == xhci->cmd_ring) { | |
2768 | xhci_err(xhci, "Do not support expand command ring\n"); | |
2769 | return -ENOMEM; | |
2770 | } | |
2771 | ||
68ffb011 XR |
2772 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
2773 | "ERROR no room on ep ring, try ring expansion"); | |
8dfec614 AX |
2774 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
2775 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
2776 | mem_flags)) { | |
2777 | xhci_err(xhci, "Ring expansion failed\n"); | |
2778 | return -ENOMEM; | |
2779 | } | |
261fa12b | 2780 | } |
6c12db90 | 2781 | |
d0c77d84 MN |
2782 | while (trb_is_link(ep_ring->enqueue)) { |
2783 | /* If we're not dealing with 0.95 hardware or isoc rings | |
2784 | * on AMD 0.96 host, clear the chain bit. | |
2785 | */ | |
2786 | if (!xhci_link_trb_quirk(xhci) && | |
2787 | !(ep_ring->type == TYPE_ISOC && | |
2788 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
2789 | ep_ring->enqueue->link.control &= | |
2790 | cpu_to_le32(~TRB_CHAIN); | |
2791 | else | |
2792 | ep_ring->enqueue->link.control |= | |
2793 | cpu_to_le32(TRB_CHAIN); | |
6c12db90 | 2794 | |
d0c77d84 MN |
2795 | wmb(); |
2796 | ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); | |
6c12db90 | 2797 | |
d0c77d84 MN |
2798 | /* Toggle the cycle bit after the last ring segment. */ |
2799 | if (link_trb_toggles_cycle(ep_ring->enqueue)) | |
2800 | ep_ring->cycle_state ^= 1; | |
6c12db90 | 2801 | |
d0c77d84 MN |
2802 | ep_ring->enq_seg = ep_ring->enq_seg->next; |
2803 | ep_ring->enqueue = ep_ring->enq_seg->trbs; | |
6c12db90 | 2804 | } |
d0e96f5a SS |
2805 | return 0; |
2806 | } | |
2807 | ||
23e3be11 | 2808 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
2809 | struct xhci_virt_device *xdev, |
2810 | unsigned int ep_index, | |
e9df17eb | 2811 | unsigned int stream_id, |
d0e96f5a SS |
2812 | unsigned int num_trbs, |
2813 | struct urb *urb, | |
8e51adcc | 2814 | unsigned int td_index, |
d0e96f5a SS |
2815 | gfp_t mem_flags) |
2816 | { | |
2817 | int ret; | |
8e51adcc AX |
2818 | struct urb_priv *urb_priv; |
2819 | struct xhci_td *td; | |
e9df17eb | 2820 | struct xhci_ring *ep_ring; |
d115b048 | 2821 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
2822 | |
2823 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
2824 | if (!ep_ring) { | |
2825 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
2826 | stream_id); | |
2827 | return -EINVAL; | |
2828 | } | |
2829 | ||
5071e6b2 | 2830 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 2831 | num_trbs, mem_flags); |
d0e96f5a SS |
2832 | if (ret) |
2833 | return ret; | |
d0e96f5a | 2834 | |
8e51adcc AX |
2835 | urb_priv = urb->hcpriv; |
2836 | td = urb_priv->td[td_index]; | |
2837 | ||
2838 | INIT_LIST_HEAD(&td->td_list); | |
2839 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
2840 | ||
2841 | if (td_index == 0) { | |
214f76f7 | 2842 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 2843 | if (unlikely(ret)) |
8e51adcc | 2844 | return ret; |
d0e96f5a SS |
2845 | } |
2846 | ||
8e51adcc | 2847 | td->urb = urb; |
d0e96f5a | 2848 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
2849 | list_add_tail(&td->td_list, &ep_ring->td_list); |
2850 | td->start_seg = ep_ring->enq_seg; | |
2851 | td->first_trb = ep_ring->enqueue; | |
2852 | ||
2853 | urb_priv->td[td_index] = td; | |
d0e96f5a SS |
2854 | |
2855 | return 0; | |
2856 | } | |
2857 | ||
d2510342 AI |
2858 | static unsigned int count_trbs(u64 addr, u64 len) |
2859 | { | |
2860 | unsigned int num_trbs; | |
2861 | ||
2862 | num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), | |
2863 | TRB_MAX_BUFF_SIZE); | |
2864 | if (num_trbs == 0) | |
2865 | num_trbs++; | |
2866 | ||
2867 | return num_trbs; | |
2868 | } | |
2869 | ||
2870 | static inline unsigned int count_trbs_needed(struct urb *urb) | |
2871 | { | |
2872 | return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); | |
2873 | } | |
2874 | ||
2875 | static unsigned int count_sg_trbs_needed(struct urb *urb) | |
8a96c052 | 2876 | { |
8a96c052 | 2877 | struct scatterlist *sg; |
d2510342 | 2878 | unsigned int i, len, full_len, num_trbs = 0; |
8a96c052 | 2879 | |
d2510342 | 2880 | full_len = urb->transfer_buffer_length; |
8a96c052 | 2881 | |
d2510342 AI |
2882 | for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { |
2883 | len = sg_dma_len(sg); | |
2884 | num_trbs += count_trbs(sg_dma_address(sg), len); | |
2885 | len = min_t(unsigned int, len, full_len); | |
2886 | full_len -= len; | |
2887 | if (full_len == 0) | |
8a96c052 SS |
2888 | break; |
2889 | } | |
d2510342 | 2890 | |
8a96c052 SS |
2891 | return num_trbs; |
2892 | } | |
2893 | ||
d2510342 AI |
2894 | static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) |
2895 | { | |
2896 | u64 addr, len; | |
2897 | ||
2898 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
2899 | len = urb->iso_frame_desc[i].length; | |
2900 | ||
2901 | return count_trbs(addr, len); | |
2902 | } | |
2903 | ||
2904 | static void check_trb_math(struct urb *urb, int running_total) | |
8a96c052 | 2905 | { |
d2510342 | 2906 | if (unlikely(running_total != urb->transfer_buffer_length)) |
a2490187 | 2907 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
2908 | "queued %#x (%d), asked for %#x (%d)\n", |
2909 | __func__, | |
2910 | urb->ep->desc.bEndpointAddress, | |
2911 | running_total, running_total, | |
2912 | urb->transfer_buffer_length, | |
2913 | urb->transfer_buffer_length); | |
2914 | } | |
2915 | ||
23e3be11 | 2916 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 2917 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 2918 | struct xhci_generic_trb *start_trb) |
8a96c052 | 2919 | { |
8a96c052 SS |
2920 | /* |
2921 | * Pass all the TRBs to the hardware at once and make sure this write | |
2922 | * isn't reordered. | |
2923 | */ | |
2924 | wmb(); | |
50f7b52a | 2925 | if (start_cycle) |
28ccd296 | 2926 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 2927 | else |
28ccd296 | 2928 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 2929 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
2930 | } |
2931 | ||
78140156 AI |
2932 | static void check_interval(struct xhci_hcd *xhci, struct urb *urb, |
2933 | struct xhci_ep_ctx *ep_ctx) | |
624defa1 | 2934 | { |
624defa1 SS |
2935 | int xhci_interval; |
2936 | int ep_interval; | |
2937 | ||
28ccd296 | 2938 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 | 2939 | ep_interval = urb->interval; |
78140156 | 2940 | |
624defa1 SS |
2941 | /* Convert to microframes */ |
2942 | if (urb->dev->speed == USB_SPEED_LOW || | |
2943 | urb->dev->speed == USB_SPEED_FULL) | |
2944 | ep_interval *= 8; | |
78140156 | 2945 | |
624defa1 SS |
2946 | /* FIXME change this to a warning and a suggestion to use the new API |
2947 | * to set the polling interval (once the API is added). | |
2948 | */ | |
2949 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
2950 | dev_dbg_ratelimited(&urb->dev->dev, |
2951 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
2952 | ep_interval, ep_interval == 1 ? "" : "s", | |
2953 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
624defa1 SS |
2954 | urb->interval = xhci_interval; |
2955 | /* Convert back to frames for LS/FS devices */ | |
2956 | if (urb->dev->speed == USB_SPEED_LOW || | |
2957 | urb->dev->speed == USB_SPEED_FULL) | |
2958 | urb->interval /= 8; | |
2959 | } | |
78140156 AI |
2960 | } |
2961 | ||
2962 | /* | |
2963 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
2964 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
2965 | * (comprised of sg list entries) can take several service intervals to | |
2966 | * transmit. | |
2967 | */ | |
2968 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
2969 | struct urb *urb, int slot_id, unsigned int ep_index) | |
2970 | { | |
2971 | struct xhci_ep_ctx *ep_ctx; | |
2972 | ||
2973 | ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); | |
2974 | check_interval(xhci, urb, ep_ctx); | |
2975 | ||
3fc8206d | 2976 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
2977 | } |
2978 | ||
4da6e6f2 | 2979 | /* |
4525c0a1 SS |
2980 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
2981 | * packets remaining in the TD (*not* including this TRB). | |
4da6e6f2 SS |
2982 | * |
2983 | * Total TD packet count = total_packet_count = | |
4525c0a1 | 2984 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
4da6e6f2 SS |
2985 | * |
2986 | * Packets transferred up to and including this TRB = packets_transferred = | |
2987 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
2988 | * | |
2989 | * TD size = total_packet_count - packets_transferred | |
2990 | * | |
c840d6ce MN |
2991 | * For xHCI 0.96 and older, TD size field should be the remaining bytes |
2992 | * including this TRB, right shifted by 10 | |
2993 | * | |
2994 | * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. | |
2995 | * This is taken care of in the TRB_TD_SIZE() macro | |
2996 | * | |
4525c0a1 | 2997 | * The last TRB in a TD must have the TD size set to zero. |
4da6e6f2 | 2998 | */ |
c840d6ce MN |
2999 | static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, |
3000 | int trb_buff_len, unsigned int td_total_len, | |
124c3937 | 3001 | struct urb *urb, bool more_trbs_coming) |
4da6e6f2 | 3002 | { |
c840d6ce MN |
3003 | u32 maxp, total_packet_count; |
3004 | ||
0cbd4b34 CY |
3005 | /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */ |
3006 | if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) | |
c840d6ce MN |
3007 | return ((td_total_len - transferred) >> 10); |
3008 | ||
48df4a6f | 3009 | /* One TRB with a zero-length data packet. */ |
124c3937 | 3010 | if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || |
c840d6ce | 3011 | trb_buff_len == td_total_len) |
48df4a6f SS |
3012 | return 0; |
3013 | ||
0cbd4b34 CY |
3014 | /* for MTK xHCI, TD size doesn't include this TRB */ |
3015 | if (xhci->quirks & XHCI_MTK_HOST) | |
3016 | trb_buff_len = 0; | |
3017 | ||
734d3ddd | 3018 | maxp = usb_endpoint_maxp(&urb->ep->desc); |
0cbd4b34 CY |
3019 | total_packet_count = DIV_ROUND_UP(td_total_len, maxp); |
3020 | ||
c840d6ce MN |
3021 | /* Queueing functions don't count the current TRB into transferred */ |
3022 | return (total_packet_count - ((transferred + trb_buff_len) / maxp)); | |
4da6e6f2 SS |
3023 | } |
3024 | ||
f9c589e1 | 3025 | |
474ed23a | 3026 | static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, |
f9c589e1 | 3027 | u32 *trb_buff_len, struct xhci_segment *seg) |
474ed23a | 3028 | { |
f9c589e1 | 3029 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
474ed23a MN |
3030 | unsigned int unalign; |
3031 | unsigned int max_pkt; | |
f9c589e1 | 3032 | u32 new_buff_len; |
474ed23a | 3033 | |
734d3ddd | 3034 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
474ed23a MN |
3035 | unalign = (enqd_len + *trb_buff_len) % max_pkt; |
3036 | ||
3037 | /* we got lucky, last normal TRB data on segment is packet aligned */ | |
3038 | if (unalign == 0) | |
3039 | return 0; | |
3040 | ||
f9c589e1 MN |
3041 | xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", |
3042 | unalign, *trb_buff_len); | |
3043 | ||
474ed23a MN |
3044 | /* is the last nornal TRB alignable by splitting it */ |
3045 | if (*trb_buff_len > unalign) { | |
3046 | *trb_buff_len -= unalign; | |
f9c589e1 | 3047 | xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); |
474ed23a MN |
3048 | return 0; |
3049 | } | |
f9c589e1 MN |
3050 | |
3051 | /* | |
3052 | * We want enqd_len + trb_buff_len to sum up to a number aligned to | |
3053 | * number which is divisible by the endpoint's wMaxPacketSize. IOW: | |
3054 | * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. | |
3055 | */ | |
3056 | new_buff_len = max_pkt - (enqd_len % max_pkt); | |
3057 | ||
3058 | if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) | |
3059 | new_buff_len = (urb->transfer_buffer_length - enqd_len); | |
3060 | ||
3061 | /* create a max max_pkt sized bounce buffer pointed to by last trb */ | |
3062 | if (usb_urb_dir_out(urb)) { | |
3063 | sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs, | |
3064 | seg->bounce_buf, new_buff_len, enqd_len); | |
3065 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3066 | max_pkt, DMA_TO_DEVICE); | |
3067 | } else { | |
3068 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3069 | max_pkt, DMA_FROM_DEVICE); | |
3070 | } | |
3071 | ||
3072 | if (dma_mapping_error(dev, seg->bounce_dma)) { | |
3073 | /* try without aligning. Some host controllers survive */ | |
3074 | xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); | |
3075 | return 0; | |
3076 | } | |
3077 | *trb_buff_len = new_buff_len; | |
3078 | seg->bounce_len = new_buff_len; | |
3079 | seg->bounce_offs = enqd_len; | |
3080 | ||
3081 | xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); | |
3082 | ||
474ed23a MN |
3083 | return 1; |
3084 | } | |
3085 | ||
d2510342 AI |
3086 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
3087 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
8a96c052 SS |
3088 | struct urb *urb, int slot_id, unsigned int ep_index) |
3089 | { | |
5a5a0b1a | 3090 | struct xhci_ring *ring; |
8e51adcc | 3091 | struct urb_priv *urb_priv; |
8a96c052 | 3092 | struct xhci_td *td; |
d2510342 AI |
3093 | struct xhci_generic_trb *start_trb; |
3094 | struct scatterlist *sg = NULL; | |
5a83f04a MN |
3095 | bool more_trbs_coming = true; |
3096 | bool need_zero_pkt = false; | |
86065c27 MN |
3097 | bool first_trb = true; |
3098 | unsigned int num_trbs; | |
d2510342 | 3099 | unsigned int start_cycle, num_sgs = 0; |
86065c27 | 3100 | unsigned int enqd_len, block_len, trb_buff_len, full_len; |
f9c589e1 | 3101 | int sent_len, ret; |
d2510342 | 3102 | u32 field, length_field, remainder; |
f9c589e1 | 3103 | u64 addr, send_addr; |
8a96c052 | 3104 | |
5a5a0b1a MN |
3105 | ring = xhci_urb_to_transfer_ring(xhci, urb); |
3106 | if (!ring) | |
e9df17eb SS |
3107 | return -EINVAL; |
3108 | ||
86065c27 | 3109 | full_len = urb->transfer_buffer_length; |
d2510342 AI |
3110 | /* If we have scatter/gather list, we use it. */ |
3111 | if (urb->num_sgs) { | |
3112 | num_sgs = urb->num_mapped_sgs; | |
3113 | sg = urb->sg; | |
86065c27 MN |
3114 | addr = (u64) sg_dma_address(sg); |
3115 | block_len = sg_dma_len(sg); | |
d2510342 | 3116 | num_trbs = count_sg_trbs_needed(urb); |
86065c27 | 3117 | } else { |
d2510342 | 3118 | num_trbs = count_trbs_needed(urb); |
86065c27 MN |
3119 | addr = (u64) urb->transfer_dma; |
3120 | block_len = full_len; | |
3121 | } | |
4758dcd1 | 3122 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 3123 | ep_index, urb->stream_id, |
3b72fca0 | 3124 | num_trbs, urb, 0, mem_flags); |
d2510342 | 3125 | if (unlikely(ret < 0)) |
4758dcd1 | 3126 | return ret; |
8e51adcc AX |
3127 | |
3128 | urb_priv = urb->hcpriv; | |
4758dcd1 RA |
3129 | |
3130 | /* Deal with URB_ZERO_PACKET - need one more td/trb */ | |
5a83f04a MN |
3131 | if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->length > 1) |
3132 | need_zero_pkt = true; | |
4758dcd1 | 3133 | |
8e51adcc AX |
3134 | td = urb_priv->td[0]; |
3135 | ||
8a96c052 SS |
3136 | /* |
3137 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3138 | * until we've finished creating all the other TRBs. The ring's cycle | |
3139 | * state may change as we enqueue the other TRBs, so save it too. | |
3140 | */ | |
5a5a0b1a MN |
3141 | start_trb = &ring->enqueue->generic; |
3142 | start_cycle = ring->cycle_state; | |
f9c589e1 | 3143 | send_addr = addr; |
8a96c052 | 3144 | |
d2510342 | 3145 | /* Queue the TRBs, even if they are zero-length */ |
0d2daade AB |
3146 | for (enqd_len = 0; first_trb || enqd_len < full_len; |
3147 | enqd_len += trb_buff_len) { | |
d2510342 | 3148 | field = TRB_TYPE(TRB_NORMAL); |
af8b9e63 | 3149 | |
86065c27 MN |
3150 | /* TRB buffer should not cross 64KB boundaries */ |
3151 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); | |
3152 | trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); | |
8a96c052 | 3153 | |
86065c27 MN |
3154 | if (enqd_len + trb_buff_len > full_len) |
3155 | trb_buff_len = full_len - enqd_len; | |
b10de142 SS |
3156 | |
3157 | /* Don't change the cycle bit of the first TRB until later */ | |
86065c27 MN |
3158 | if (first_trb) { |
3159 | first_trb = false; | |
50f7b52a | 3160 | if (start_cycle == 0) |
d2510342 | 3161 | field |= TRB_CYCLE; |
50f7b52a | 3162 | } else |
5a5a0b1a | 3163 | field |= ring->cycle_state; |
b10de142 SS |
3164 | |
3165 | /* Chain all the TRBs together; clear the chain bit in the last | |
3166 | * TRB to indicate it's the last TRB in the chain. | |
3167 | */ | |
86065c27 | 3168 | if (enqd_len + trb_buff_len < full_len) { |
b10de142 | 3169 | field |= TRB_CHAIN; |
2d98ef40 | 3170 | if (trb_is_link(ring->enqueue + 1)) { |
474ed23a | 3171 | if (xhci_align_td(xhci, urb, enqd_len, |
f9c589e1 MN |
3172 | &trb_buff_len, |
3173 | ring->enq_seg)) { | |
3174 | send_addr = ring->enq_seg->bounce_dma; | |
3175 | /* assuming TD won't span 2 segs */ | |
3176 | td->bounce_seg = ring->enq_seg; | |
3177 | } | |
474ed23a | 3178 | } |
f9c589e1 MN |
3179 | } |
3180 | if (enqd_len + trb_buff_len >= full_len) { | |
3181 | field &= ~TRB_CHAIN; | |
4758dcd1 | 3182 | field |= TRB_IOC; |
124c3937 | 3183 | more_trbs_coming = false; |
5a83f04a | 3184 | td->last_trb = ring->enqueue; |
b10de142 | 3185 | } |
af8b9e63 SS |
3186 | |
3187 | /* Only set interrupt on short packet for IN endpoints */ | |
3188 | if (usb_urb_dir_in(urb)) | |
3189 | field |= TRB_ISP; | |
3190 | ||
4da6e6f2 | 3191 | /* Set the TRB length, TD size, and interrupter fields. */ |
86065c27 MN |
3192 | remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, |
3193 | full_len, urb, more_trbs_coming); | |
3194 | ||
f9dc68fe | 3195 | length_field = TRB_LEN(trb_buff_len) | |
c840d6ce | 3196 | TRB_TD_SIZE(remainder) | |
f9dc68fe | 3197 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3198 | |
124c3937 | 3199 | queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, |
f9c589e1 MN |
3200 | lower_32_bits(send_addr), |
3201 | upper_32_bits(send_addr), | |
f9dc68fe | 3202 | length_field, |
d2510342 | 3203 | field); |
b10de142 | 3204 | |
b10de142 | 3205 | addr += trb_buff_len; |
f9c589e1 | 3206 | sent_len = trb_buff_len; |
d2510342 | 3207 | |
f9c589e1 | 3208 | while (sg && sent_len >= block_len) { |
86065c27 MN |
3209 | /* New sg entry */ |
3210 | --num_sgs; | |
f9c589e1 | 3211 | sent_len -= block_len; |
86065c27 | 3212 | if (num_sgs != 0) { |
d2510342 | 3213 | sg = sg_next(sg); |
86065c27 MN |
3214 | block_len = sg_dma_len(sg); |
3215 | addr = (u64) sg_dma_address(sg); | |
f9c589e1 | 3216 | addr += sent_len; |
d2510342 AI |
3217 | } |
3218 | } | |
f9c589e1 MN |
3219 | block_len -= sent_len; |
3220 | send_addr = addr; | |
d2510342 | 3221 | } |
b10de142 | 3222 | |
5a83f04a MN |
3223 | if (need_zero_pkt) { |
3224 | ret = prepare_transfer(xhci, xhci->devs[slot_id], | |
3225 | ep_index, urb->stream_id, | |
3226 | 1, urb, 1, mem_flags); | |
3227 | urb_priv->td[1]->last_trb = ring->enqueue; | |
3228 | field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; | |
3229 | queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); | |
3230 | } | |
3231 | ||
86065c27 | 3232 | check_trb_math(urb, enqd_len); |
e9df17eb | 3233 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3234 | start_cycle, start_trb); |
b10de142 SS |
3235 | return 0; |
3236 | } | |
3237 | ||
d0e96f5a | 3238 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3239 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3240 | struct urb *urb, int slot_id, unsigned int ep_index) |
3241 | { | |
3242 | struct xhci_ring *ep_ring; | |
3243 | int num_trbs; | |
3244 | int ret; | |
3245 | struct usb_ctrlrequest *setup; | |
3246 | struct xhci_generic_trb *start_trb; | |
3247 | int start_cycle; | |
c840d6ce | 3248 | u32 field, length_field, remainder; |
8e51adcc | 3249 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3250 | struct xhci_td *td; |
3251 | ||
e9df17eb SS |
3252 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3253 | if (!ep_ring) | |
3254 | return -EINVAL; | |
d0e96f5a SS |
3255 | |
3256 | /* | |
3257 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3258 | * DMA address. | |
3259 | */ | |
3260 | if (!urb->setup_packet) | |
3261 | return -EINVAL; | |
3262 | ||
d0e96f5a SS |
3263 | /* 1 TRB for setup, 1 for status */ |
3264 | num_trbs = 2; | |
3265 | /* | |
3266 | * Don't need to check if we need additional event data and normal TRBs, | |
3267 | * since data in control transfers will never get bigger than 16MB | |
3268 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3269 | */ | |
3270 | if (urb->transfer_buffer_length > 0) | |
3271 | num_trbs++; | |
e9df17eb SS |
3272 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3273 | ep_index, urb->stream_id, | |
3b72fca0 | 3274 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3275 | if (ret < 0) |
3276 | return ret; | |
3277 | ||
8e51adcc AX |
3278 | urb_priv = urb->hcpriv; |
3279 | td = urb_priv->td[0]; | |
3280 | ||
d0e96f5a SS |
3281 | /* |
3282 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3283 | * until we've finished creating all the other TRBs. The ring's cycle | |
3284 | * state may change as we enqueue the other TRBs, so save it too. | |
3285 | */ | |
3286 | start_trb = &ep_ring->enqueue->generic; | |
3287 | start_cycle = ep_ring->cycle_state; | |
3288 | ||
3289 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3290 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3291 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3292 | field = 0; |
3293 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3294 | if (start_cycle == 0) | |
3295 | field |= 0x1; | |
b83cdc8f | 3296 | |
dca77945 | 3297 | /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ |
0cbd4b34 | 3298 | if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { |
b83cdc8f AX |
3299 | if (urb->transfer_buffer_length > 0) { |
3300 | if (setup->bRequestType & USB_DIR_IN) | |
3301 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3302 | else | |
3303 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3304 | } | |
3305 | } | |
3306 | ||
3b72fca0 | 3307 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3308 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3309 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3310 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3311 | /* Immediate data in pointer */ | |
3312 | field); | |
d0e96f5a SS |
3313 | |
3314 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3315 | /* Only set interrupt on short packet for IN endpoints */ |
3316 | if (usb_urb_dir_in(urb)) | |
3317 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3318 | else | |
3319 | field = TRB_TYPE(TRB_DATA); | |
3320 | ||
c840d6ce MN |
3321 | remainder = xhci_td_remainder(xhci, 0, |
3322 | urb->transfer_buffer_length, | |
3323 | urb->transfer_buffer_length, | |
3324 | urb, 1); | |
3325 | ||
f9dc68fe | 3326 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
c840d6ce | 3327 | TRB_TD_SIZE(remainder) | |
f9dc68fe | 3328 | TRB_INTR_TARGET(0); |
c840d6ce | 3329 | |
d0e96f5a SS |
3330 | if (urb->transfer_buffer_length > 0) { |
3331 | if (setup->bRequestType & USB_DIR_IN) | |
3332 | field |= TRB_DIR_IN; | |
3b72fca0 | 3333 | queue_trb(xhci, ep_ring, true, |
d0e96f5a SS |
3334 | lower_32_bits(urb->transfer_dma), |
3335 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 3336 | length_field, |
af8b9e63 | 3337 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3338 | } |
3339 | ||
3340 | /* Save the DMA address of the last TRB in the TD */ | |
3341 | td->last_trb = ep_ring->enqueue; | |
3342 | ||
3343 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3344 | /* If the device sent data, the status stage is an OUT transfer */ | |
3345 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3346 | field = 0; | |
3347 | else | |
3348 | field = TRB_DIR_IN; | |
3b72fca0 | 3349 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3350 | 0, |
3351 | 0, | |
3352 | TRB_INTR_TARGET(0), | |
3353 | /* Event on completion */ | |
3354 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3355 | ||
e9df17eb | 3356 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3357 | start_cycle, start_trb); |
d0e96f5a SS |
3358 | return 0; |
3359 | } | |
3360 | ||
5cd43e33 SS |
3361 | /* |
3362 | * The transfer burst count field of the isochronous TRB defines the number of | |
3363 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3364 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3365 | * This field is zero based, meaning a value of zero in the field means one | |
3366 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3367 | * zero. Only xHCI 1.0 host controllers support this field. | |
3368 | */ | |
3369 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
5cd43e33 SS |
3370 | struct urb *urb, unsigned int total_packet_count) |
3371 | { | |
3372 | unsigned int max_burst; | |
3373 | ||
09c352ed | 3374 | if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) |
5cd43e33 SS |
3375 | return 0; |
3376 | ||
3377 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3213b151 | 3378 | return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; |
5cd43e33 SS |
3379 | } |
3380 | ||
b61d378f SS |
3381 | /* |
3382 | * Returns the number of packets in the last "burst" of packets. This field is | |
3383 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3384 | * the last burst packet count is equal to the total number of packets in the | |
3385 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3386 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3387 | * contain 1 to (bMaxBurst + 1) packets. | |
3388 | */ | |
3389 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
b61d378f SS |
3390 | struct urb *urb, unsigned int total_packet_count) |
3391 | { | |
3392 | unsigned int max_burst; | |
3393 | unsigned int residue; | |
3394 | ||
3395 | if (xhci->hci_version < 0x100) | |
3396 | return 0; | |
3397 | ||
09c352ed | 3398 | if (urb->dev->speed >= USB_SPEED_SUPER) { |
b61d378f SS |
3399 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ |
3400 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3401 | residue = total_packet_count % (max_burst + 1); | |
3402 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3403 | * number of packets, but the TLBPC field is zero-based. | |
3404 | */ | |
3405 | if (residue == 0) | |
3406 | return max_burst; | |
3407 | return residue - 1; | |
b61d378f | 3408 | } |
09c352ed MN |
3409 | if (total_packet_count == 0) |
3410 | return 0; | |
3411 | return total_packet_count - 1; | |
b61d378f SS |
3412 | } |
3413 | ||
79b8094f LB |
3414 | /* |
3415 | * Calculates Frame ID field of the isochronous TRB identifies the | |
3416 | * target frame that the Interval associated with this Isochronous | |
3417 | * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. | |
3418 | * | |
3419 | * Returns actual frame id on success, negative value on error. | |
3420 | */ | |
3421 | static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, | |
3422 | struct urb *urb, int index) | |
3423 | { | |
3424 | int start_frame, ist, ret = 0; | |
3425 | int start_frame_id, end_frame_id, current_frame_id; | |
3426 | ||
3427 | if (urb->dev->speed == USB_SPEED_LOW || | |
3428 | urb->dev->speed == USB_SPEED_FULL) | |
3429 | start_frame = urb->start_frame + index * urb->interval; | |
3430 | else | |
3431 | start_frame = (urb->start_frame + index * urb->interval) >> 3; | |
3432 | ||
3433 | /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): | |
3434 | * | |
3435 | * If bit [3] of IST is cleared to '0', software can add a TRB no | |
3436 | * later than IST[2:0] Microframes before that TRB is scheduled to | |
3437 | * be executed. | |
3438 | * If bit [3] of IST is set to '1', software can add a TRB no later | |
3439 | * than IST[2:0] Frames before that TRB is scheduled to be executed. | |
3440 | */ | |
3441 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3442 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3443 | ist <<= 3; | |
3444 | ||
3445 | /* Software shall not schedule an Isoch TD with a Frame ID value that | |
3446 | * is less than the Start Frame ID or greater than the End Frame ID, | |
3447 | * where: | |
3448 | * | |
3449 | * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 | |
3450 | * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 | |
3451 | * | |
3452 | * Both the End Frame ID and Start Frame ID values are calculated | |
3453 | * in microframes. When software determines the valid Frame ID value; | |
3454 | * The End Frame ID value should be rounded down to the nearest Frame | |
3455 | * boundary, and the Start Frame ID value should be rounded up to the | |
3456 | * nearest Frame boundary. | |
3457 | */ | |
3458 | current_frame_id = readl(&xhci->run_regs->microframe_index); | |
3459 | start_frame_id = roundup(current_frame_id + ist + 1, 8); | |
3460 | end_frame_id = rounddown(current_frame_id + 895 * 8, 8); | |
3461 | ||
3462 | start_frame &= 0x7ff; | |
3463 | start_frame_id = (start_frame_id >> 3) & 0x7ff; | |
3464 | end_frame_id = (end_frame_id >> 3) & 0x7ff; | |
3465 | ||
3466 | xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", | |
3467 | __func__, index, readl(&xhci->run_regs->microframe_index), | |
3468 | start_frame_id, end_frame_id, start_frame); | |
3469 | ||
3470 | if (start_frame_id < end_frame_id) { | |
3471 | if (start_frame > end_frame_id || | |
3472 | start_frame < start_frame_id) | |
3473 | ret = -EINVAL; | |
3474 | } else if (start_frame_id > end_frame_id) { | |
3475 | if ((start_frame > end_frame_id && | |
3476 | start_frame < start_frame_id)) | |
3477 | ret = -EINVAL; | |
3478 | } else { | |
3479 | ret = -EINVAL; | |
3480 | } | |
3481 | ||
3482 | if (index == 0) { | |
3483 | if (ret == -EINVAL || start_frame == start_frame_id) { | |
3484 | start_frame = start_frame_id + 1; | |
3485 | if (urb->dev->speed == USB_SPEED_LOW || | |
3486 | urb->dev->speed == USB_SPEED_FULL) | |
3487 | urb->start_frame = start_frame; | |
3488 | else | |
3489 | urb->start_frame = start_frame << 3; | |
3490 | ret = 0; | |
3491 | } | |
3492 | } | |
3493 | ||
3494 | if (ret) { | |
3495 | xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", | |
3496 | start_frame, current_frame_id, index, | |
3497 | start_frame_id, end_frame_id); | |
3498 | xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); | |
3499 | return ret; | |
3500 | } | |
3501 | ||
3502 | return start_frame; | |
3503 | } | |
3504 | ||
04e51901 AX |
3505 | /* This is for isoc transfer */ |
3506 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3507 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3508 | { | |
3509 | struct xhci_ring *ep_ring; | |
3510 | struct urb_priv *urb_priv; | |
3511 | struct xhci_td *td; | |
3512 | int num_tds, trbs_per_td; | |
3513 | struct xhci_generic_trb *start_trb; | |
3514 | bool first_trb; | |
3515 | int start_cycle; | |
3516 | u32 field, length_field; | |
3517 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
3518 | u64 start_addr, addr; | |
3519 | int i, j; | |
47cbf692 | 3520 | bool more_trbs_coming; |
79b8094f | 3521 | struct xhci_virt_ep *xep; |
09c352ed | 3522 | int frame_id; |
04e51901 | 3523 | |
79b8094f | 3524 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
3525 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
3526 | ||
3527 | num_tds = urb->number_of_packets; | |
3528 | if (num_tds < 1) { | |
3529 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
3530 | return -EINVAL; | |
3531 | } | |
04e51901 AX |
3532 | start_addr = (u64) urb->transfer_dma; |
3533 | start_trb = &ep_ring->enqueue->generic; | |
3534 | start_cycle = ep_ring->cycle_state; | |
3535 | ||
522989a2 | 3536 | urb_priv = urb->hcpriv; |
09c352ed | 3537 | /* Queue the TRBs for each TD, even if they are zero-length */ |
04e51901 | 3538 | for (i = 0; i < num_tds; i++) { |
09c352ed MN |
3539 | unsigned int total_pkt_count, max_pkt; |
3540 | unsigned int burst_count, last_burst_pkt_count; | |
3541 | u32 sia_frame_id; | |
04e51901 | 3542 | |
4da6e6f2 | 3543 | first_trb = true; |
04e51901 AX |
3544 | running_total = 0; |
3545 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
3546 | td_len = urb->iso_frame_desc[i].length; | |
3547 | td_remain_len = td_len; | |
734d3ddd | 3548 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
09c352ed MN |
3549 | total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); |
3550 | ||
48df4a6f | 3551 | /* A zero-length transfer still involves at least one packet. */ |
09c352ed MN |
3552 | if (total_pkt_count == 0) |
3553 | total_pkt_count++; | |
3554 | burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); | |
3555 | last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, | |
3556 | urb, total_pkt_count); | |
04e51901 | 3557 | |
d2510342 | 3558 | trbs_per_td = count_isoc_trbs_needed(urb, i); |
04e51901 AX |
3559 | |
3560 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 3561 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
3562 | if (ret < 0) { |
3563 | if (i == 0) | |
3564 | return ret; | |
3565 | goto cleanup; | |
3566 | } | |
04e51901 | 3567 | td = urb_priv->td[i]; |
09c352ed MN |
3568 | |
3569 | /* use SIA as default, if frame id is used overwrite it */ | |
3570 | sia_frame_id = TRB_SIA; | |
3571 | if (!(urb->transfer_flags & URB_ISO_ASAP) && | |
3572 | HCC_CFC(xhci->hcc_params)) { | |
3573 | frame_id = xhci_get_isoc_frame_id(xhci, urb, i); | |
3574 | if (frame_id >= 0) | |
3575 | sia_frame_id = TRB_FRAME_ID(frame_id); | |
3576 | } | |
3577 | /* | |
3578 | * Set isoc specific data for the first TRB in a TD. | |
3579 | * Prevent HW from getting the TRBs by keeping the cycle state | |
3580 | * inverted in the first TDs isoc TRB. | |
3581 | */ | |
2f6d3b65 | 3582 | field = TRB_TYPE(TRB_ISOC) | |
09c352ed MN |
3583 | TRB_TLBPC(last_burst_pkt_count) | |
3584 | sia_frame_id | | |
3585 | (i ? ep_ring->cycle_state : !start_cycle); | |
3586 | ||
2f6d3b65 MN |
3587 | /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ |
3588 | if (!xep->use_extended_tbc) | |
3589 | field |= TRB_TBC(burst_count); | |
3590 | ||
09c352ed | 3591 | /* fill the rest of the TRB fields, and remaining normal TRBs */ |
04e51901 AX |
3592 | for (j = 0; j < trbs_per_td; j++) { |
3593 | u32 remainder = 0; | |
09c352ed MN |
3594 | |
3595 | /* only first TRB is isoc, overwrite otherwise */ | |
3596 | if (!first_trb) | |
3597 | field = TRB_TYPE(TRB_NORMAL) | | |
3598 | ep_ring->cycle_state; | |
04e51901 | 3599 | |
af8b9e63 SS |
3600 | /* Only set interrupt on short packet for IN EPs */ |
3601 | if (usb_urb_dir_in(urb)) | |
3602 | field |= TRB_ISP; | |
3603 | ||
09c352ed | 3604 | /* Set the chain bit for all except the last TRB */ |
04e51901 | 3605 | if (j < trbs_per_td - 1) { |
47cbf692 | 3606 | more_trbs_coming = true; |
09c352ed | 3607 | field |= TRB_CHAIN; |
04e51901 | 3608 | } else { |
09c352ed | 3609 | more_trbs_coming = false; |
04e51901 AX |
3610 | td->last_trb = ep_ring->enqueue; |
3611 | field |= TRB_IOC; | |
09c352ed MN |
3612 | /* set BEI, except for the last TD */ |
3613 | if (xhci->hci_version >= 0x100 && | |
3614 | !(xhci->quirks & XHCI_AVOID_BEI) && | |
3615 | i < num_tds - 1) | |
3616 | field |= TRB_BEI; | |
04e51901 | 3617 | } |
04e51901 | 3618 | /* Calculate TRB length */ |
d2510342 | 3619 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); |
04e51901 AX |
3620 | if (trb_buff_len > td_remain_len) |
3621 | trb_buff_len = td_remain_len; | |
3622 | ||
4da6e6f2 | 3623 | /* Set the TRB length, TD size, & interrupter fields. */ |
c840d6ce MN |
3624 | remainder = xhci_td_remainder(xhci, running_total, |
3625 | trb_buff_len, td_len, | |
124c3937 | 3626 | urb, more_trbs_coming); |
c840d6ce | 3627 | |
04e51901 | 3628 | length_field = TRB_LEN(trb_buff_len) | |
04e51901 | 3629 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3630 | |
2f6d3b65 MN |
3631 | /* xhci 1.1 with ETE uses TD Size field for TBC */ |
3632 | if (first_trb && xep->use_extended_tbc) | |
3633 | length_field |= TRB_TD_SIZE_TBC(burst_count); | |
3634 | else | |
3635 | length_field |= TRB_TD_SIZE(remainder); | |
3636 | first_trb = false; | |
3637 | ||
3b72fca0 | 3638 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
3639 | lower_32_bits(addr), |
3640 | upper_32_bits(addr), | |
3641 | length_field, | |
af8b9e63 | 3642 | field); |
04e51901 AX |
3643 | running_total += trb_buff_len; |
3644 | ||
3645 | addr += trb_buff_len; | |
3646 | td_remain_len -= trb_buff_len; | |
3647 | } | |
3648 | ||
3649 | /* Check TD length */ | |
3650 | if (running_total != td_len) { | |
3651 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
3652 | ret = -EINVAL; |
3653 | goto cleanup; | |
04e51901 AX |
3654 | } |
3655 | } | |
3656 | ||
79b8094f LB |
3657 | /* store the next frame id */ |
3658 | if (HCC_CFC(xhci->hcc_params)) | |
3659 | xep->next_frame_id = urb->start_frame + num_tds * urb->interval; | |
3660 | ||
c41136b0 AX |
3661 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
3662 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
3663 | usb_amd_quirk_pll_disable(); | |
3664 | } | |
3665 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
3666 | ||
e1eab2e0 AX |
3667 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3668 | start_cycle, start_trb); | |
04e51901 | 3669 | return 0; |
522989a2 SS |
3670 | cleanup: |
3671 | /* Clean up a partially enqueued isoc transfer. */ | |
3672 | ||
3673 | for (i--; i >= 0; i--) | |
585df1d9 | 3674 | list_del_init(&urb_priv->td[i]->td_list); |
522989a2 SS |
3675 | |
3676 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
3677 | * into No-ops with a software-owned cycle bit. That way the hardware | |
3678 | * won't accidentally start executing bogus TDs when we partially | |
3679 | * overwrite them. td->first_trb and td->start_seg are already set. | |
3680 | */ | |
3681 | urb_priv->td[0]->last_trb = ep_ring->enqueue; | |
3682 | /* Every TRB except the first & last will have its cycle bit flipped. */ | |
3683 | td_to_noop(xhci, ep_ring, urb_priv->td[0], true); | |
3684 | ||
3685 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
3686 | ep_ring->enqueue = urb_priv->td[0]->first_trb; | |
3687 | ep_ring->enq_seg = urb_priv->td[0]->start_seg; | |
3688 | ep_ring->cycle_state = start_cycle; | |
b008df60 | 3689 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
3690 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
3691 | return ret; | |
04e51901 AX |
3692 | } |
3693 | ||
3694 | /* | |
3695 | * Check transfer ring to guarantee there is enough room for the urb. | |
3696 | * Update ISO URB start_frame and interval. | |
79b8094f LB |
3697 | * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to |
3698 | * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or | |
3699 | * Contiguous Frame ID is not supported by HC. | |
04e51901 AX |
3700 | */ |
3701 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3702 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3703 | { | |
3704 | struct xhci_virt_device *xdev; | |
3705 | struct xhci_ring *ep_ring; | |
3706 | struct xhci_ep_ctx *ep_ctx; | |
3707 | int start_frame; | |
04e51901 AX |
3708 | int num_tds, num_trbs, i; |
3709 | int ret; | |
79b8094f LB |
3710 | struct xhci_virt_ep *xep; |
3711 | int ist; | |
04e51901 AX |
3712 | |
3713 | xdev = xhci->devs[slot_id]; | |
79b8094f | 3714 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
3715 | ep_ring = xdev->eps[ep_index].ring; |
3716 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3717 | ||
3718 | num_trbs = 0; | |
3719 | num_tds = urb->number_of_packets; | |
3720 | for (i = 0; i < num_tds; i++) | |
d2510342 | 3721 | num_trbs += count_isoc_trbs_needed(urb, i); |
04e51901 AX |
3722 | |
3723 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3724 | * Do not insert any td of the urb to the ring if the check failed. | |
3725 | */ | |
5071e6b2 | 3726 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 3727 | num_trbs, mem_flags); |
04e51901 AX |
3728 | if (ret) |
3729 | return ret; | |
3730 | ||
79b8094f LB |
3731 | /* |
3732 | * Check interval value. This should be done before we start to | |
3733 | * calculate the start frame value. | |
3734 | */ | |
78140156 | 3735 | check_interval(xhci, urb, ep_ctx); |
79b8094f LB |
3736 | |
3737 | /* Calculate the start frame and put it in urb->start_frame. */ | |
42df7215 | 3738 | if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { |
5071e6b2 | 3739 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) { |
42df7215 LB |
3740 | urb->start_frame = xep->next_frame_id; |
3741 | goto skip_start_over; | |
3742 | } | |
79b8094f LB |
3743 | } |
3744 | ||
3745 | start_frame = readl(&xhci->run_regs->microframe_index); | |
3746 | start_frame &= 0x3fff; | |
3747 | /* | |
3748 | * Round up to the next frame and consider the time before trb really | |
3749 | * gets scheduled by hardare. | |
3750 | */ | |
3751 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3752 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3753 | ist <<= 3; | |
3754 | start_frame += ist + XHCI_CFC_DELAY; | |
3755 | start_frame = roundup(start_frame, 8); | |
3756 | ||
3757 | /* | |
3758 | * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT | |
3759 | * is greate than 8 microframes. | |
3760 | */ | |
3761 | if (urb->dev->speed == USB_SPEED_LOW || | |
3762 | urb->dev->speed == USB_SPEED_FULL) { | |
3763 | start_frame = roundup(start_frame, urb->interval << 3); | |
3764 | urb->start_frame = start_frame >> 3; | |
3765 | } else { | |
3766 | start_frame = roundup(start_frame, urb->interval); | |
3767 | urb->start_frame = start_frame; | |
3768 | } | |
3769 | ||
3770 | skip_start_over: | |
b008df60 AX |
3771 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
3772 | ||
3fc8206d | 3773 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
3774 | } |
3775 | ||
d0e96f5a SS |
3776 | /**** Command Ring Operations ****/ |
3777 | ||
913a8a34 SS |
3778 | /* Generic function for queueing a command TRB on the command ring. |
3779 | * Check to make sure there's room on the command ring for one command TRB. | |
3780 | * Also check that there's room reserved for commands that must not fail. | |
3781 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
3782 | * then only check for the number of reserved spots. | |
3783 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
3784 | * because the command event handler may want to resubmit a failed command. | |
3785 | */ | |
ddba5cd0 MN |
3786 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3787 | u32 field1, u32 field2, | |
3788 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 3789 | { |
913a8a34 | 3790 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a | 3791 | int ret; |
ad6b1d91 | 3792 | |
98d74f9c MN |
3793 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
3794 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
ad6b1d91 | 3795 | xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); |
c9aa1a2d | 3796 | return -ESHUTDOWN; |
ad6b1d91 | 3797 | } |
d1dc908a | 3798 | |
913a8a34 SS |
3799 | if (!command_must_succeed) |
3800 | reserved_trbs++; | |
3801 | ||
d1dc908a | 3802 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 3803 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
3804 | if (ret < 0) { |
3805 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
3806 | if (command_must_succeed) |
3807 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
3808 | "unfailable commands failed.\n"); | |
d1dc908a | 3809 | return ret; |
7f84eef0 | 3810 | } |
c9aa1a2d MN |
3811 | |
3812 | cmd->command_trb = xhci->cmd_ring->enqueue; | |
3813 | list_add_tail(&cmd->cmd_list, &xhci->cmd_list); | |
ddba5cd0 | 3814 | |
c311e391 MN |
3815 | /* if there are no other commands queued we start the timeout timer */ |
3816 | if (xhci->cmd_list.next == &cmd->cmd_list && | |
cb4d5ce5 | 3817 | !delayed_work_pending(&xhci->cmd_timer)) { |
c311e391 | 3818 | xhci->current_cmd = cmd; |
cb4d5ce5 | 3819 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
c311e391 MN |
3820 | } |
3821 | ||
3b72fca0 AX |
3822 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
3823 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
3824 | return 0; |
3825 | } | |
3826 | ||
3ffbba95 | 3827 | /* Queue a slot enable or disable request on the command ring */ |
ddba5cd0 MN |
3828 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3829 | u32 trb_type, u32 slot_id) | |
3ffbba95 | 3830 | { |
ddba5cd0 | 3831 | return queue_command(xhci, cmd, 0, 0, 0, |
913a8a34 | 3832 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
3833 | } |
3834 | ||
3835 | /* Queue an address device command TRB */ | |
ddba5cd0 MN |
3836 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3837 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) | |
3ffbba95 | 3838 | { |
ddba5cd0 | 3839 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3840 | upper_32_bits(in_ctx_ptr), 0, |
48fc7dbd DW |
3841 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
3842 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); | |
2a8f82c4 SS |
3843 | } |
3844 | ||
ddba5cd0 | 3845 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
0238634d SS |
3846 | u32 field1, u32 field2, u32 field3, u32 field4) |
3847 | { | |
ddba5cd0 | 3848 | return queue_command(xhci, cmd, field1, field2, field3, field4, false); |
0238634d SS |
3849 | } |
3850 | ||
2a8f82c4 | 3851 | /* Queue a reset device command TRB */ |
ddba5cd0 MN |
3852 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3853 | u32 slot_id) | |
2a8f82c4 | 3854 | { |
ddba5cd0 | 3855 | return queue_command(xhci, cmd, 0, 0, 0, |
2a8f82c4 | 3856 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
913a8a34 | 3857 | false); |
3ffbba95 | 3858 | } |
f94e0186 SS |
3859 | |
3860 | /* Queue a configure endpoint command TRB */ | |
ddba5cd0 MN |
3861 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
3862 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, | |
913a8a34 | 3863 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 3864 | { |
ddba5cd0 | 3865 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3866 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 SS |
3867 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
3868 | command_must_succeed); | |
f94e0186 | 3869 | } |
ae636747 | 3870 | |
f2217e8e | 3871 | /* Queue an evaluate context command TRB */ |
ddba5cd0 MN |
3872 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3873 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) | |
f2217e8e | 3874 | { |
ddba5cd0 | 3875 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
f2217e8e | 3876 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 | 3877 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 3878 | command_must_succeed); |
f2217e8e SS |
3879 | } |
3880 | ||
be88fe4f AX |
3881 | /* |
3882 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
3883 | * activity on an endpoint that is about to be suspended. | |
3884 | */ | |
ddba5cd0 MN |
3885 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3886 | int slot_id, unsigned int ep_index, int suspend) | |
ae636747 SS |
3887 | { |
3888 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3889 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3890 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 3891 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 | 3892 | |
ddba5cd0 | 3893 | return queue_command(xhci, cmd, 0, 0, 0, |
be88fe4f | 3894 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
3895 | } |
3896 | ||
d3a43e66 HG |
3897 | /* Set Transfer Ring Dequeue Pointer command */ |
3898 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, | |
3899 | unsigned int slot_id, unsigned int ep_index, | |
3900 | unsigned int stream_id, | |
3901 | struct xhci_dequeue_state *deq_state) | |
ae636747 SS |
3902 | { |
3903 | dma_addr_t addr; | |
3904 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3905 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
e9df17eb | 3906 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
95241dbd | 3907 | u32 trb_sct = 0; |
ae636747 | 3908 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
bf161e85 | 3909 | struct xhci_virt_ep *ep; |
1e3452e3 HG |
3910 | struct xhci_command *cmd; |
3911 | int ret; | |
ae636747 | 3912 | |
d3a43e66 HG |
3913 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
3914 | "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u", | |
3915 | deq_state->new_deq_seg, | |
3916 | (unsigned long long)deq_state->new_deq_seg->dma, | |
3917 | deq_state->new_deq_ptr, | |
3918 | (unsigned long long)xhci_trb_virt_to_dma( | |
3919 | deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
3920 | deq_state->new_cycle_state); | |
3921 | ||
3922 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
3923 | deq_state->new_deq_ptr); | |
c92bcfa7 | 3924 | if (addr == 0) { |
ae636747 | 3925 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 | 3926 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
d3a43e66 HG |
3927 | deq_state->new_deq_seg, deq_state->new_deq_ptr); |
3928 | return; | |
c92bcfa7 | 3929 | } |
bf161e85 SS |
3930 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
3931 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
3932 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | |
3933 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | |
d3a43e66 | 3934 | return; |
bf161e85 | 3935 | } |
1e3452e3 HG |
3936 | |
3937 | /* This function gets called from contexts where it cannot sleep */ | |
3938 | cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
3939 | if (!cmd) { | |
3940 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n"); | |
d3a43e66 | 3941 | return; |
1e3452e3 HG |
3942 | } |
3943 | ||
d3a43e66 HG |
3944 | ep->queued_deq_seg = deq_state->new_deq_seg; |
3945 | ep->queued_deq_ptr = deq_state->new_deq_ptr; | |
95241dbd HG |
3946 | if (stream_id) |
3947 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); | |
1e3452e3 | 3948 | ret = queue_command(xhci, cmd, |
d3a43e66 HG |
3949 | lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state, |
3950 | upper_32_bits(addr), trb_stream_id, | |
3951 | trb_slot_id | trb_ep_index | type, false); | |
1e3452e3 HG |
3952 | if (ret < 0) { |
3953 | xhci_free_command(xhci, cmd); | |
d3a43e66 | 3954 | return; |
1e3452e3 HG |
3955 | } |
3956 | ||
d3a43e66 HG |
3957 | /* Stop the TD queueing code from ringing the doorbell until |
3958 | * this command completes. The HC won't set the dequeue pointer | |
3959 | * if the ring is running, and ringing the doorbell starts the | |
3960 | * ring running. | |
3961 | */ | |
3962 | ep->ep_state |= SET_DEQ_PENDING; | |
ae636747 | 3963 | } |
a1587d97 | 3964 | |
ddba5cd0 MN |
3965 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3966 | int slot_id, unsigned int ep_index) | |
a1587d97 SS |
3967 | { |
3968 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3969 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3970 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
3971 | ||
ddba5cd0 MN |
3972 | return queue_command(xhci, cmd, 0, 0, 0, |
3973 | trb_slot_id | trb_ep_index | type, false); | |
a1587d97 | 3974 | } |