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Commit | Line | Data |
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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
f9c589e1 | 69 | #include <linux/dma-mapping.h> |
7f84eef0 | 70 | #include "xhci.h" |
3a7fa5be | 71 | #include "xhci-trace.h" |
0cbd4b34 | 72 | #include "xhci-mtk.h" |
7f84eef0 SS |
73 | |
74 | /* | |
75 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
76 | * address of the TRB. | |
77 | */ | |
23e3be11 | 78 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
79 | union xhci_trb *trb) |
80 | { | |
6071d836 | 81 | unsigned long segment_offset; |
7f84eef0 | 82 | |
6071d836 | 83 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 84 | return 0; |
6071d836 SS |
85 | /* offset in TRBs */ |
86 | segment_offset = trb - seg->trbs; | |
7895086a | 87 | if (segment_offset >= TRBS_PER_SEGMENT) |
7f84eef0 | 88 | return 0; |
6071d836 | 89 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
90 | } |
91 | ||
0ce57499 MN |
92 | static bool trb_is_noop(union xhci_trb *trb) |
93 | { | |
94 | return TRB_TYPE_NOOP_LE32(trb->generic.field[3]); | |
95 | } | |
96 | ||
2d98ef40 MN |
97 | static bool trb_is_link(union xhci_trb *trb) |
98 | { | |
99 | return TRB_TYPE_LINK_LE32(trb->link.control); | |
100 | } | |
101 | ||
bd5e67f5 MN |
102 | static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) |
103 | { | |
104 | return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; | |
105 | } | |
106 | ||
107 | static bool last_trb_on_ring(struct xhci_ring *ring, | |
108 | struct xhci_segment *seg, union xhci_trb *trb) | |
109 | { | |
110 | return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); | |
111 | } | |
112 | ||
d0c77d84 MN |
113 | static bool link_trb_toggles_cycle(union xhci_trb *trb) |
114 | { | |
115 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; | |
116 | } | |
117 | ||
2a72126d MN |
118 | static bool last_td_in_urb(struct xhci_td *td) |
119 | { | |
120 | struct urb_priv *urb_priv = td->urb->hcpriv; | |
121 | ||
9ef7fbbb | 122 | return urb_priv->num_tds_done == urb_priv->num_tds; |
2a72126d MN |
123 | } |
124 | ||
125 | static void inc_td_cnt(struct urb *urb) | |
126 | { | |
127 | struct urb_priv *urb_priv = urb->hcpriv; | |
128 | ||
9ef7fbbb | 129 | urb_priv->num_tds_done++; |
2a72126d MN |
130 | } |
131 | ||
ae1e3f07 MN |
132 | static void trb_to_noop(union xhci_trb *trb, u32 noop_type) |
133 | { | |
134 | if (trb_is_link(trb)) { | |
135 | /* unchain chained link TRBs */ | |
136 | trb->link.control &= cpu_to_le32(~TRB_CHAIN); | |
137 | } else { | |
138 | trb->generic.field[0] = 0; | |
139 | trb->generic.field[1] = 0; | |
140 | trb->generic.field[2] = 0; | |
141 | /* Preserve only the cycle bit of this TRB */ | |
142 | trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); | |
143 | trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type)); | |
144 | } | |
145 | } | |
146 | ||
ae636747 SS |
147 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
148 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
149 | * effect the ring dequeue or enqueue pointers. | |
150 | */ | |
151 | static void next_trb(struct xhci_hcd *xhci, | |
152 | struct xhci_ring *ring, | |
153 | struct xhci_segment **seg, | |
154 | union xhci_trb **trb) | |
155 | { | |
2d98ef40 | 156 | if (trb_is_link(*trb)) { |
ae636747 SS |
157 | *seg = (*seg)->next; |
158 | *trb = ((*seg)->trbs); | |
159 | } else { | |
a1669b2c | 160 | (*trb)++; |
ae636747 SS |
161 | } |
162 | } | |
163 | ||
7f84eef0 SS |
164 | /* |
165 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
166 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
167 | */ | |
3b72fca0 | 168 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 169 | { |
bd5e67f5 MN |
170 | /* event ring doesn't have link trbs, check for last trb */ |
171 | if (ring->type == TYPE_EVENT) { | |
172 | if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { | |
50d0206f | 173 | ring->dequeue++; |
bd5e67f5 | 174 | return; |
7f84eef0 | 175 | } |
bd5e67f5 MN |
176 | if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) |
177 | ring->cycle_state ^= 1; | |
178 | ring->deq_seg = ring->deq_seg->next; | |
179 | ring->dequeue = ring->deq_seg->trbs; | |
180 | return; | |
181 | } | |
182 | ||
183 | /* All other rings have link trbs */ | |
184 | if (!trb_is_link(ring->dequeue)) { | |
185 | ring->dequeue++; | |
186 | ring->num_trbs_free++; | |
187 | } | |
188 | while (trb_is_link(ring->dequeue)) { | |
189 | ring->deq_seg = ring->deq_seg->next; | |
190 | ring->dequeue = ring->deq_seg->trbs; | |
191 | } | |
b2d6edbb LB |
192 | |
193 | trace_xhci_inc_deq(ring); | |
194 | ||
bd5e67f5 | 195 | return; |
7f84eef0 SS |
196 | } |
197 | ||
198 | /* | |
199 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
200 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
201 | * | |
202 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
203 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
204 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
205 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
206 | * | |
207 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
208 | * set, but other sections talk about dealing with the chain bit set. This was |
209 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
210 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
211 | * |
212 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
213 | * prepare_transfer()? | |
7f84eef0 | 214 | */ |
6cc30d85 | 215 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 216 | bool more_trbs_coming) |
7f84eef0 SS |
217 | { |
218 | u32 chain; | |
219 | union xhci_trb *next; | |
220 | ||
28ccd296 | 221 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 | 222 | /* If this is not event ring, there is one less usable TRB */ |
2d98ef40 | 223 | if (!trb_is_link(ring->enqueue)) |
b008df60 | 224 | ring->num_trbs_free--; |
7f84eef0 SS |
225 | next = ++(ring->enqueue); |
226 | ||
2251198b | 227 | /* Update the dequeue pointer further if that was a link TRB */ |
2d98ef40 | 228 | while (trb_is_link(next)) { |
6cc30d85 | 229 | |
2251198b MN |
230 | /* |
231 | * If the caller doesn't plan on enqueueing more TDs before | |
232 | * ringing the doorbell, then we don't want to give the link TRB | |
233 | * to the hardware just yet. We'll give the link TRB back in | |
234 | * prepare_ring() just before we enqueue the TD at the top of | |
235 | * the ring. | |
236 | */ | |
237 | if (!chain && !more_trbs_coming) | |
238 | break; | |
3b72fca0 | 239 | |
2251198b MN |
240 | /* If we're not dealing with 0.95 hardware or isoc rings on |
241 | * AMD 0.96 host, carry over the chain bit of the previous TRB | |
242 | * (which may mean the chain bit is cleared). | |
243 | */ | |
244 | if (!(ring->type == TYPE_ISOC && | |
245 | (xhci->quirks & XHCI_AMD_0x96_HOST)) && | |
246 | !xhci_link_trb_quirk(xhci)) { | |
247 | next->link.control &= cpu_to_le32(~TRB_CHAIN); | |
248 | next->link.control |= cpu_to_le32(chain); | |
7f84eef0 | 249 | } |
2251198b MN |
250 | /* Give this link TRB to the hardware */ |
251 | wmb(); | |
252 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
253 | ||
254 | /* Toggle the cycle bit after the last ring segment. */ | |
d0c77d84 | 255 | if (link_trb_toggles_cycle(next)) |
2251198b MN |
256 | ring->cycle_state ^= 1; |
257 | ||
7f84eef0 SS |
258 | ring->enq_seg = ring->enq_seg->next; |
259 | ring->enqueue = ring->enq_seg->trbs; | |
260 | next = ring->enqueue; | |
261 | } | |
b2d6edbb LB |
262 | |
263 | trace_xhci_inc_enq(ring); | |
7f84eef0 SS |
264 | } |
265 | ||
266 | /* | |
085deb16 AX |
267 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
268 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 269 | */ |
b008df60 | 270 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
271 | unsigned int num_trbs) |
272 | { | |
085deb16 | 273 | int num_trbs_in_deq_seg; |
b008df60 | 274 | |
085deb16 AX |
275 | if (ring->num_trbs_free < num_trbs) |
276 | return 0; | |
277 | ||
278 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
279 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
280 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
281 | return 0; | |
282 | } | |
283 | ||
284 | return 1; | |
7f84eef0 SS |
285 | } |
286 | ||
7f84eef0 | 287 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 288 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 289 | { |
c181bc5b EF |
290 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
291 | return; | |
292 | ||
7f84eef0 | 293 | xhci_dbg(xhci, "// Ding dong!\n"); |
204b7793 | 294 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 | 295 | /* Flush PCI posted writes */ |
b0ba9720 | 296 | readl(&xhci->dba->doorbell[0]); |
7f84eef0 SS |
297 | } |
298 | ||
cb4d5ce5 OH |
299 | static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay) |
300 | { | |
301 | return mod_delayed_work(system_wq, &xhci->cmd_timer, delay); | |
302 | } | |
303 | ||
1c111b6c OH |
304 | static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci) |
305 | { | |
306 | return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command, | |
307 | cmd_list); | |
308 | } | |
309 | ||
310 | /* | |
311 | * Turn all commands on command ring with status set to "aborted" to no-op trbs. | |
312 | * If there are other commands waiting then restart the ring and kick the timer. | |
313 | * This must be called with command ring stopped and xhci->lock held. | |
314 | */ | |
315 | static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, | |
316 | struct xhci_command *cur_cmd) | |
317 | { | |
318 | struct xhci_command *i_cmd; | |
1c111b6c OH |
319 | |
320 | /* Turn all aborted commands in list to no-ops, then restart */ | |
321 | list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { | |
322 | ||
0b7c105a | 323 | if (i_cmd->status != COMP_COMMAND_ABORTED) |
1c111b6c OH |
324 | continue; |
325 | ||
604d02a2 | 326 | i_cmd->status = COMP_COMMAND_RING_STOPPED; |
1c111b6c OH |
327 | |
328 | xhci_dbg(xhci, "Turn aborted command %p to no-op\n", | |
329 | i_cmd->command_trb); | |
5278204c MN |
330 | |
331 | trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP); | |
1c111b6c OH |
332 | |
333 | /* | |
334 | * caller waiting for completion is called when command | |
335 | * completion event is received for these no-op commands | |
336 | */ | |
337 | } | |
338 | ||
339 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; | |
340 | ||
341 | /* ring command ring doorbell to restart the command ring */ | |
342 | if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && | |
343 | !(xhci->xhc_state & XHCI_STATE_DYING)) { | |
344 | xhci->current_cmd = cur_cmd; | |
345 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); | |
346 | xhci_ring_cmd_db(xhci); | |
347 | } | |
348 | } | |
349 | ||
350 | /* Must be called with xhci->lock held, releases and aquires lock back */ | |
351 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) | |
b92cc66c EF |
352 | { |
353 | u64 temp_64; | |
354 | int ret; | |
355 | ||
356 | xhci_dbg(xhci, "Abort command ring\n"); | |
357 | ||
1c111b6c | 358 | reinit_completion(&xhci->cmd_ring_stop_completion); |
3425aa03 | 359 | |
1c111b6c | 360 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
477632df SS |
361 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, |
362 | &xhci->op_regs->cmd_ring); | |
b92cc66c | 363 | |
d9f11ba9 MN |
364 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the |
365 | * completion of the Command Abort operation. If CRR is not negated in 5 | |
366 | * seconds then driver handles it as if host died (-ENODEV). | |
367 | * In the future we should distinguish between -ENODEV and -ETIMEDOUT | |
368 | * and try to recover a -ETIMEDOUT with a host controller reset. | |
b92cc66c | 369 | */ |
dc0b177c | 370 | ret = xhci_handshake(&xhci->op_regs->cmd_ring, |
b92cc66c EF |
371 | CMD_RING_RUNNING, 0, 5 * 1000 * 1000); |
372 | if (ret < 0) { | |
d9f11ba9 | 373 | xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret); |
1cc6d861 | 374 | xhci_halt(xhci); |
d9f11ba9 MN |
375 | xhci_hc_died(xhci); |
376 | return ret; | |
1c111b6c OH |
377 | } |
378 | /* | |
379 | * Writing the CMD_RING_ABORT bit should cause a cmd completion event, | |
380 | * however on some host hw the CMD_RING_RUNNING bit is correctly cleared | |
381 | * but the completion event in never sent. Wait 2 secs (arbitrary | |
382 | * number) to handle those cases after negation of CMD_RING_RUNNING. | |
383 | */ | |
384 | spin_unlock_irqrestore(&xhci->lock, flags); | |
385 | ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion, | |
386 | msecs_to_jiffies(2000)); | |
387 | spin_lock_irqsave(&xhci->lock, flags); | |
388 | if (!ret) { | |
389 | xhci_dbg(xhci, "No stop event for abort, ring start fail?\n"); | |
390 | xhci_cleanup_command_queue(xhci); | |
391 | } else { | |
392 | xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci)); | |
b92cc66c | 393 | } |
b92cc66c EF |
394 | return 0; |
395 | } | |
396 | ||
be88fe4f | 397 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 398 | unsigned int slot_id, |
e9df17eb SS |
399 | unsigned int ep_index, |
400 | unsigned int stream_id) | |
ae636747 | 401 | { |
28ccd296 | 402 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
403 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
404 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 405 | |
ae636747 | 406 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 407 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
408 | * We don't want to restart any stream rings if there's a set dequeue |
409 | * pointer command pending because the device can choose to start any | |
410 | * stream once the endpoint is on the HW schedule. | |
ae636747 | 411 | */ |
9983a5fc | 412 | if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) || |
50d64676 MW |
413 | (ep_state & EP_HALTED)) |
414 | return; | |
204b7793 | 415 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
50d64676 MW |
416 | /* The CPU has better things to do at this point than wait for a |
417 | * write-posting flush. It'll get there soon enough. | |
418 | */ | |
ae636747 SS |
419 | } |
420 | ||
e9df17eb SS |
421 | /* Ring the doorbell for any rings with pending URBs */ |
422 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
423 | unsigned int slot_id, | |
424 | unsigned int ep_index) | |
425 | { | |
426 | unsigned int stream_id; | |
427 | struct xhci_virt_ep *ep; | |
428 | ||
429 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
430 | ||
431 | /* A ring has pending URBs if its TD list is not empty */ | |
432 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
d66eaf9f | 433 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
be88fe4f | 434 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
435 | return; |
436 | } | |
437 | ||
438 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
439 | stream_id++) { | |
440 | struct xhci_stream_info *stream_info = ep->stream_info; | |
441 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
442 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
443 | stream_id); | |
e9df17eb SS |
444 | } |
445 | } | |
446 | ||
75b040ec AI |
447 | /* Get the right ring for the given slot_id, ep_index and stream_id. |
448 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
449 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
450 | */ | |
451 | struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
021bff91 SS |
452 | unsigned int slot_id, unsigned int ep_index, |
453 | unsigned int stream_id) | |
454 | { | |
455 | struct xhci_virt_ep *ep; | |
456 | ||
457 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
458 | /* Common case: no streams */ | |
459 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
460 | return ep->ring; | |
461 | ||
462 | if (stream_id == 0) { | |
463 | xhci_warn(xhci, | |
464 | "WARN: Slot ID %u, ep index %u has streams, " | |
465 | "but URB has no stream ID.\n", | |
466 | slot_id, ep_index); | |
467 | return NULL; | |
468 | } | |
469 | ||
470 | if (stream_id < ep->stream_info->num_streams) | |
471 | return ep->stream_info->stream_rings[stream_id]; | |
472 | ||
473 | xhci_warn(xhci, | |
474 | "WARN: Slot ID %u, ep index %u has " | |
475 | "stream IDs 1 to %u allocated, " | |
476 | "but stream ID %u is requested.\n", | |
477 | slot_id, ep_index, | |
478 | ep->stream_info->num_streams - 1, | |
479 | stream_id); | |
480 | return NULL; | |
481 | } | |
482 | ||
e6b20121 MN |
483 | |
484 | /* | |
485 | * Get the hw dequeue pointer xHC stopped on, either directly from the | |
486 | * endpoint context, or if streams are in use from the stream context. | |
487 | * The returned hw_dequeue contains the lowest four bits with cycle state | |
488 | * and possbile stream context type. | |
489 | */ | |
490 | static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev, | |
491 | unsigned int ep_index, unsigned int stream_id) | |
492 | { | |
493 | struct xhci_ep_ctx *ep_ctx; | |
494 | struct xhci_stream_ctx *st_ctx; | |
495 | struct xhci_virt_ep *ep; | |
496 | ||
497 | ep = &vdev->eps[ep_index]; | |
498 | ||
499 | if (ep->ep_state & EP_HAS_STREAMS) { | |
500 | st_ctx = &ep->stream_info->stream_ctx_array[stream_id]; | |
501 | return le64_to_cpu(st_ctx->stream_ring); | |
502 | } | |
503 | ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); | |
504 | return le64_to_cpu(ep_ctx->deq); | |
505 | } | |
506 | ||
ae636747 SS |
507 | /* |
508 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
509 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
8790736d | 510 | * dequeue pointer, stream id, and new consumer cycle state in state. |
ae636747 SS |
511 | * Update our internal representation of the ring's dequeue pointer. |
512 | * | |
513 | * We do this in three jumps: | |
514 | * - First we update our new ring state to be the same as when the xHC stopped. | |
515 | * - Then we traverse the ring to find the segment that contains | |
516 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
517 | * any link TRBs with the toggle cycle bit set. | |
518 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
519 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
28ccd296 ME |
520 | * |
521 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | |
522 | * with correct __le32 accesses they should work fine. Only users of this are | |
523 | * in here. | |
ae636747 | 524 | */ |
c92bcfa7 | 525 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 526 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
527 | unsigned int stream_id, struct xhci_td *cur_td, |
528 | struct xhci_dequeue_state *state) | |
ae636747 SS |
529 | { |
530 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
c4bedb77 | 531 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; |
e9df17eb | 532 | struct xhci_ring *ep_ring; |
365038d8 MN |
533 | struct xhci_segment *new_seg; |
534 | union xhci_trb *new_deq; | |
c92bcfa7 | 535 | dma_addr_t addr; |
1f81b6d2 | 536 | u64 hw_dequeue; |
365038d8 MN |
537 | bool cycle_found = false; |
538 | bool td_last_trb_found = false; | |
ae636747 | 539 | |
e9df17eb SS |
540 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
541 | ep_index, stream_id); | |
542 | if (!ep_ring) { | |
543 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
544 | "for invalid stream ID %u.\n", | |
545 | stream_id); | |
546 | return; | |
547 | } | |
ae636747 | 548 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
aa50b290 XR |
549 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
550 | "Finding endpoint context"); | |
ae636747 | 551 | |
e6b20121 | 552 | hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id); |
365038d8 MN |
553 | new_seg = ep_ring->deq_seg; |
554 | new_deq = ep_ring->dequeue; | |
555 | state->new_cycle_state = hw_dequeue & 0x1; | |
8790736d | 556 | state->stream_id = stream_id; |
365038d8 | 557 | |
1f81b6d2 | 558 | /* |
365038d8 MN |
559 | * We want to find the pointer, segment and cycle state of the new trb |
560 | * (the one after current TD's last_trb). We know the cycle state at | |
561 | * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are | |
562 | * found. | |
1f81b6d2 | 563 | */ |
365038d8 MN |
564 | do { |
565 | if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) | |
566 | == (dma_addr_t)(hw_dequeue & ~0xf)) { | |
567 | cycle_found = true; | |
568 | if (td_last_trb_found) | |
569 | break; | |
570 | } | |
571 | if (new_deq == cur_td->last_trb) | |
572 | td_last_trb_found = true; | |
1f81b6d2 | 573 | |
3495e451 MN |
574 | if (cycle_found && trb_is_link(new_deq) && |
575 | link_trb_toggles_cycle(new_deq)) | |
365038d8 MN |
576 | state->new_cycle_state ^= 0x1; |
577 | ||
578 | next_trb(xhci, ep_ring, &new_seg, &new_deq); | |
579 | ||
580 | /* Search wrapped around, bail out */ | |
581 | if (new_deq == ep->ring->dequeue) { | |
582 | xhci_err(xhci, "Error: Failed finding new dequeue state\n"); | |
583 | state->new_deq_seg = NULL; | |
584 | state->new_deq_ptr = NULL; | |
585 | return; | |
586 | } | |
587 | ||
588 | } while (!cycle_found || !td_last_trb_found); | |
ae636747 | 589 | |
365038d8 MN |
590 | state->new_deq_seg = new_seg; |
591 | state->new_deq_ptr = new_deq; | |
ae636747 | 592 | |
1f81b6d2 | 593 | /* Don't update the ring cycle state for the producer (us). */ |
aa50b290 XR |
594 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
595 | "Cycle state = 0x%x", state->new_cycle_state); | |
01a1fdb9 | 596 | |
aa50b290 XR |
597 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
598 | "New dequeue segment = %p (virtual)", | |
c92bcfa7 SS |
599 | state->new_deq_seg); |
600 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
aa50b290 XR |
601 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
602 | "New dequeue pointer = 0x%llx (DMA)", | |
c92bcfa7 | 603 | (unsigned long long) addr); |
ae636747 SS |
604 | } |
605 | ||
522989a2 SS |
606 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
607 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
608 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
609 | */ | |
23e3be11 | 610 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
0d58a1a0 | 611 | struct xhci_td *td, bool flip_cycle) |
ae636747 | 612 | { |
0d58a1a0 MN |
613 | struct xhci_segment *seg = td->start_seg; |
614 | union xhci_trb *trb = td->first_trb; | |
615 | ||
616 | while (1) { | |
ae1e3f07 MN |
617 | trb_to_noop(trb, TRB_TR_NOOP); |
618 | ||
0d58a1a0 MN |
619 | /* flip cycle if asked to */ |
620 | if (flip_cycle && trb != td->first_trb && trb != td->last_trb) | |
621 | trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE); | |
622 | ||
623 | if (trb == td->last_trb) | |
ae636747 | 624 | break; |
0d58a1a0 MN |
625 | |
626 | next_trb(xhci, ep_ring, &seg, &trb); | |
ae636747 SS |
627 | } |
628 | } | |
629 | ||
575688e1 | 630 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
631 | struct xhci_virt_ep *ep) |
632 | { | |
9983a5fc | 633 | ep->ep_state &= ~EP_STOP_CMD_PENDING; |
f9926596 MN |
634 | /* Can't del_timer_sync in interrupt */ |
635 | del_timer(&ep->stop_cmd_timer); | |
6f5165cf SS |
636 | } |
637 | ||
2a72126d MN |
638 | /* |
639 | * Must be called with xhci->lock held in interrupt context, | |
640 | * releases and re-acquires xhci->lock | |
641 | */ | |
6f5165cf | 642 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, |
2a72126d | 643 | struct xhci_td *cur_td, int status) |
6f5165cf | 644 | { |
2a72126d MN |
645 | struct urb *urb = cur_td->urb; |
646 | struct urb_priv *urb_priv = urb->hcpriv; | |
647 | struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus); | |
648 | ||
649 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | |
650 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
651 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
652 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
653 | usb_amd_quirk_pll_enable(); | |
c41136b0 | 654 | } |
8e51adcc | 655 | } |
446b3141 | 656 | xhci_urb_free_priv(urb_priv); |
2a72126d | 657 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
446b3141 | 658 | spin_unlock(&xhci->lock); |
5abdc2e6 | 659 | trace_xhci_urb_giveback(urb); |
7bc5d5af | 660 | usb_hcd_giveback_urb(hcd, urb, status); |
446b3141 MN |
661 | spin_lock(&xhci->lock); |
662 | } | |
663 | ||
2d6d5769 WY |
664 | static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, |
665 | struct xhci_ring *ring, struct xhci_td *td) | |
f9c589e1 MN |
666 | { |
667 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
668 | struct xhci_segment *seg = td->bounce_seg; | |
669 | struct urb *urb = td->urb; | |
670 | ||
f45e2a02 | 671 | if (!ring || !seg || !urb) |
f9c589e1 MN |
672 | return; |
673 | ||
674 | if (usb_urb_dir_out(urb)) { | |
675 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
676 | DMA_TO_DEVICE); | |
677 | return; | |
678 | } | |
679 | ||
680 | /* for in tranfers we need to copy the data from bounce to sg */ | |
681 | sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf, | |
682 | seg->bounce_len, seg->bounce_offs); | |
683 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
684 | DMA_FROM_DEVICE); | |
685 | seg->bounce_len = 0; | |
686 | seg->bounce_offs = 0; | |
687 | } | |
688 | ||
ae636747 SS |
689 | /* |
690 | * When we get a command completion for a Stop Endpoint Command, we need to | |
691 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
692 | * | |
693 | * 1. If the HW was in the middle of processing the TD that needs to be | |
694 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
695 | * in the TD with a Set Dequeue Pointer Command. | |
696 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
697 | * bit cleared) so that the HW will skip over them. | |
698 | */ | |
b8200c94 | 699 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 700 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 | 701 | { |
ae636747 SS |
702 | unsigned int ep_index; |
703 | struct xhci_ring *ep_ring; | |
63a0d9ab | 704 | struct xhci_virt_ep *ep; |
326b4810 | 705 | struct xhci_td *cur_td = NULL; |
ae636747 | 706 | struct xhci_td *last_unlinked_td; |
19a7d0d6 FB |
707 | struct xhci_ep_ctx *ep_ctx; |
708 | struct xhci_virt_device *vdev; | |
cdd504e1 | 709 | u64 hw_deq; |
c92bcfa7 | 710 | struct xhci_dequeue_state deq_state; |
ae636747 | 711 | |
bc752bde | 712 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
9ea1833e | 713 | if (!xhci->devs[slot_id]) |
be88fe4f AX |
714 | xhci_warn(xhci, "Stop endpoint command " |
715 | "completion for disabled slot %u\n", | |
716 | slot_id); | |
717 | return; | |
718 | } | |
719 | ||
ae636747 | 720 | memset(&deq_state, 0, sizeof(deq_state)); |
28ccd296 | 721 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
19a7d0d6 FB |
722 | |
723 | vdev = xhci->devs[slot_id]; | |
724 | ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); | |
725 | trace_xhci_handle_cmd_stop_ep(ep_ctx); | |
726 | ||
63a0d9ab | 727 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
04861f83 FB |
728 | last_unlinked_td = list_last_entry(&ep->cancelled_td_list, |
729 | struct xhci_td, cancelled_td_list); | |
ae636747 | 730 | |
678539cf | 731 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 732 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
e9df17eb | 733 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 734 | return; |
678539cf | 735 | } |
ae636747 SS |
736 | |
737 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
738 | * We have the xHCI lock, so nothing can modify this list until we drop | |
739 | * it. We're also in the event handler, so we can't get re-interrupted | |
740 | * if another Stop Endpoint command completes | |
741 | */ | |
04861f83 | 742 | list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) { |
aa50b290 XR |
743 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
744 | "Removing canceled TD starting at 0x%llx (dma).", | |
79688acf SS |
745 | (unsigned long long)xhci_trb_virt_to_dma( |
746 | cur_td->start_seg, cur_td->first_trb)); | |
e9df17eb SS |
747 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
748 | if (!ep_ring) { | |
749 | /* This shouldn't happen unless a driver is mucking | |
750 | * with the stream ID after submission. This will | |
751 | * leave the TD on the hardware ring, and the hardware | |
752 | * will try to execute it, and may access a buffer | |
753 | * that has already been freed. In the best case, the | |
754 | * hardware will execute it, and the event handler will | |
755 | * ignore the completion event for that TD, since it was | |
756 | * removed from the td_list for that endpoint. In | |
757 | * short, don't muck with the stream ID after | |
758 | * submission. | |
759 | */ | |
760 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
761 | "has invalid stream ID %u.\n", | |
762 | cur_td->urb, | |
763 | cur_td->urb->stream_id); | |
764 | goto remove_finished_td; | |
765 | } | |
ae636747 SS |
766 | /* |
767 | * If we stopped on the TD we need to cancel, then we have to | |
768 | * move the xHC endpoint ring dequeue pointer past this TD. | |
769 | */ | |
cdd504e1 MN |
770 | hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index, |
771 | cur_td->urb->stream_id); | |
772 | hw_deq &= ~0xf; | |
773 | ||
774 | if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb, | |
775 | cur_td->last_trb, hw_deq, false)) { | |
e9df17eb | 776 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
cdd504e1 MN |
777 | cur_td->urb->stream_id, |
778 | cur_td, &deq_state); | |
779 | } else { | |
522989a2 | 780 | td_to_noop(xhci, ep_ring, cur_td, false); |
cdd504e1 MN |
781 | } |
782 | ||
e9df17eb | 783 | remove_finished_td: |
ae636747 SS |
784 | /* |
785 | * The event handler won't see a completion for this TD anymore, | |
786 | * so remove it from the endpoint ring's TD list. Keep it in | |
787 | * the cancelled TD list for URB completion later. | |
788 | */ | |
585df1d9 | 789 | list_del_init(&cur_td->td_list); |
ae636747 | 790 | } |
04861f83 | 791 | |
6f5165cf | 792 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
793 | |
794 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
795 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
1e3452e3 | 796 | xhci_queue_new_dequeue_state(xhci, slot_id, ep_index, |
8790736d | 797 | &deq_state); |
ac9d8fe7 | 798 | xhci_ring_cmd_db(xhci); |
ae636747 | 799 | } else { |
e9df17eb SS |
800 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
801 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 802 | } |
526867c3 | 803 | |
ae636747 SS |
804 | /* |
805 | * Drop the lock and complete the URBs in the cancelled TD list. | |
806 | * New TDs to be cancelled might be added to the end of the list before | |
807 | * we can complete all the URBs for the TDs we already unlinked. | |
808 | * So stop when we've completed the URB for the last TD we unlinked. | |
809 | */ | |
810 | do { | |
04861f83 | 811 | cur_td = list_first_entry(&ep->cancelled_td_list, |
ae636747 | 812 | struct xhci_td, cancelled_td_list); |
585df1d9 | 813 | list_del_init(&cur_td->cancelled_td_list); |
ae636747 SS |
814 | |
815 | /* Clean up the cancelled URB */ | |
ae636747 SS |
816 | /* Doesn't matter what we pass for status, since the core will |
817 | * just overwrite it (because the URB has been unlinked). | |
818 | */ | |
f76a28a6 | 819 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
a60f2f2f | 820 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td); |
2a72126d MN |
821 | inc_td_cnt(cur_td->urb); |
822 | if (last_td_in_urb(cur_td)) | |
823 | xhci_giveback_urb_in_irq(xhci, cur_td, 0); | |
ae636747 | 824 | |
6f5165cf SS |
825 | /* Stop processing the cancelled list if the watchdog timer is |
826 | * running. | |
827 | */ | |
828 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
829 | return; | |
ae636747 SS |
830 | } while (cur_td != last_unlinked_td); |
831 | ||
832 | /* Return to the event handler with xhci->lock re-acquired */ | |
833 | } | |
834 | ||
50e8725e SS |
835 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
836 | { | |
837 | struct xhci_td *cur_td; | |
a54cfae3 | 838 | struct xhci_td *tmp; |
50e8725e | 839 | |
a54cfae3 | 840 | list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) { |
50e8725e | 841 | list_del_init(&cur_td->td_list); |
a54cfae3 | 842 | |
50e8725e SS |
843 | if (!list_empty(&cur_td->cancelled_td_list)) |
844 | list_del_init(&cur_td->cancelled_td_list); | |
f9c589e1 | 845 | |
a60f2f2f | 846 | xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); |
2a72126d MN |
847 | |
848 | inc_td_cnt(cur_td->urb); | |
849 | if (last_td_in_urb(cur_td)) | |
850 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
851 | } |
852 | } | |
853 | ||
854 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, | |
855 | int slot_id, int ep_index) | |
856 | { | |
857 | struct xhci_td *cur_td; | |
a54cfae3 | 858 | struct xhci_td *tmp; |
50e8725e SS |
859 | struct xhci_virt_ep *ep; |
860 | struct xhci_ring *ring; | |
861 | ||
862 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
21d0e51b SS |
863 | if ((ep->ep_state & EP_HAS_STREAMS) || |
864 | (ep->ep_state & EP_GETTING_NO_STREAMS)) { | |
865 | int stream_id; | |
866 | ||
867 | for (stream_id = 0; stream_id < ep->stream_info->num_streams; | |
868 | stream_id++) { | |
869 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
870 | "Killing URBs for slot ID %u, ep index %u, stream %u", | |
871 | slot_id, ep_index, stream_id + 1); | |
872 | xhci_kill_ring_urbs(xhci, | |
873 | ep->stream_info->stream_rings[stream_id]); | |
874 | } | |
875 | } else { | |
876 | ring = ep->ring; | |
877 | if (!ring) | |
878 | return; | |
879 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
880 | "Killing URBs for slot ID %u, ep index %u", | |
881 | slot_id, ep_index); | |
882 | xhci_kill_ring_urbs(xhci, ring); | |
883 | } | |
2a72126d | 884 | |
a54cfae3 FB |
885 | list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list, |
886 | cancelled_td_list) { | |
887 | list_del_init(&cur_td->cancelled_td_list); | |
2a72126d | 888 | inc_td_cnt(cur_td->urb); |
a54cfae3 | 889 | |
2a72126d MN |
890 | if (last_td_in_urb(cur_td)) |
891 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
892 | } |
893 | } | |
894 | ||
d9f11ba9 MN |
895 | /* |
896 | * host controller died, register read returns 0xffffffff | |
897 | * Complete pending commands, mark them ABORTED. | |
898 | * URBs need to be given back as usb core might be waiting with device locks | |
899 | * held for the URBs to finish during device disconnect, blocking host remove. | |
900 | * | |
901 | * Call with xhci->lock held. | |
902 | * lock is relased and re-acquired while giving back urb. | |
903 | */ | |
904 | void xhci_hc_died(struct xhci_hcd *xhci) | |
905 | { | |
906 | int i, j; | |
907 | ||
908 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
909 | return; | |
910 | ||
911 | xhci_err(xhci, "xHCI host controller not responding, assume dead\n"); | |
912 | xhci->xhc_state |= XHCI_STATE_DYING; | |
913 | ||
914 | xhci_cleanup_command_queue(xhci); | |
915 | ||
916 | /* return any pending urbs, remove may be waiting for them */ | |
917 | for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { | |
918 | if (!xhci->devs[i]) | |
919 | continue; | |
920 | for (j = 0; j < 31; j++) | |
921 | xhci_kill_endpoint_urbs(xhci, i, j); | |
922 | } | |
923 | ||
924 | /* inform usb core hc died if PCI remove isn't already handling it */ | |
925 | if (!(xhci->xhc_state & XHCI_STATE_REMOVING)) | |
926 | usb_hc_died(xhci_to_hcd(xhci)); | |
927 | } | |
928 | ||
6f5165cf SS |
929 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
930 | * In this case, we assume the host controller is broken or dying or dead. The | |
931 | * host may still be completing some other events, so we have to be careful to | |
932 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
933 | * through xhci->state. | |
934 | * | |
935 | * The timer may also fire if the host takes a very long time to respond to the | |
936 | * command, and the stop endpoint command completion handler cannot delete the | |
937 | * timer before the timer function is called. Another endpoint cancellation may | |
938 | * sneak in before the timer function can grab the lock, and that may queue | |
939 | * another stop endpoint command and add the timer back. So we cannot use a | |
940 | * simple flag to say whether there is a pending stop endpoint command for a | |
941 | * particular endpoint. | |
942 | * | |
f9926596 MN |
943 | * Instead we use a combination of that flag and checking if a new timer is |
944 | * pending. | |
6f5165cf SS |
945 | */ |
946 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
947 | { | |
948 | struct xhci_hcd *xhci; | |
949 | struct xhci_virt_ep *ep; | |
f43d6231 | 950 | unsigned long flags; |
6f5165cf SS |
951 | |
952 | ep = (struct xhci_virt_ep *) arg; | |
953 | xhci = ep->xhci; | |
954 | ||
f43d6231 | 955 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf | 956 | |
f9926596 MN |
957 | /* bail out if cmd completed but raced with stop ep watchdog timer.*/ |
958 | if (!(ep->ep_state & EP_STOP_CMD_PENDING) || | |
959 | timer_pending(&ep->stop_cmd_timer)) { | |
f43d6231 | 960 | spin_unlock_irqrestore(&xhci->lock, flags); |
f9926596 | 961 | xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit"); |
6f5165cf SS |
962 | return; |
963 | } | |
964 | ||
965 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
f9926596 MN |
966 | ep->ep_state &= ~EP_STOP_CMD_PENDING; |
967 | ||
d9f11ba9 | 968 | xhci_halt(xhci); |
6f5165cf | 969 | |
d9f11ba9 MN |
970 | /* |
971 | * handle a stop endpoint cmd timeout as if host died (-ENODEV). | |
972 | * In the future we could distinguish between -ENODEV and -ETIMEDOUT | |
973 | * and try to recover a -ETIMEDOUT with a host controller reset | |
974 | */ | |
975 | xhci_hc_died(xhci); | |
6f5165cf | 976 | |
f43d6231 | 977 | spin_unlock_irqrestore(&xhci->lock, flags); |
aa50b290 XR |
978 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
979 | "xHCI host controller is dead."); | |
6f5165cf SS |
980 | } |
981 | ||
b008df60 AX |
982 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, |
983 | struct xhci_virt_device *dev, | |
984 | struct xhci_ring *ep_ring, | |
985 | unsigned int ep_index) | |
986 | { | |
987 | union xhci_trb *dequeue_temp; | |
988 | int num_trbs_free_temp; | |
989 | bool revert = false; | |
990 | ||
991 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
992 | dequeue_temp = ep_ring->dequeue; | |
993 | ||
0d9f78a9 SS |
994 | /* If we get two back-to-back stalls, and the first stalled transfer |
995 | * ends just before a link TRB, the dequeue pointer will be left on | |
996 | * the link TRB by the code in the while loop. So we have to update | |
997 | * the dequeue pointer one segment further, or we'll jump off | |
998 | * the segment into la-la-land. | |
999 | */ | |
2d98ef40 | 1000 | if (trb_is_link(ep_ring->dequeue)) { |
0d9f78a9 SS |
1001 | ep_ring->deq_seg = ep_ring->deq_seg->next; |
1002 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
1003 | } | |
1004 | ||
b008df60 AX |
1005 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
1006 | /* We have more usable TRBs */ | |
1007 | ep_ring->num_trbs_free++; | |
1008 | ep_ring->dequeue++; | |
2d98ef40 | 1009 | if (trb_is_link(ep_ring->dequeue)) { |
b008df60 AX |
1010 | if (ep_ring->dequeue == |
1011 | dev->eps[ep_index].queued_deq_ptr) | |
1012 | break; | |
1013 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
1014 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
1015 | } | |
1016 | if (ep_ring->dequeue == dequeue_temp) { | |
1017 | revert = true; | |
1018 | break; | |
1019 | } | |
1020 | } | |
1021 | ||
1022 | if (revert) { | |
1023 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
1024 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
1025 | } | |
1026 | } | |
1027 | ||
ae636747 SS |
1028 | /* |
1029 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
1030 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
1031 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
1032 | * endpoint doorbell to restart the ring, but only if there aren't more | |
1033 | * cancellations pending. | |
1034 | */ | |
b8200c94 | 1035 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1036 | union xhci_trb *trb, u32 cmd_comp_code) |
ae636747 | 1037 | { |
ae636747 | 1038 | unsigned int ep_index; |
e9df17eb | 1039 | unsigned int stream_id; |
ae636747 SS |
1040 | struct xhci_ring *ep_ring; |
1041 | struct xhci_virt_device *dev; | |
9aad95e2 | 1042 | struct xhci_virt_ep *ep; |
d115b048 JY |
1043 | struct xhci_ep_ctx *ep_ctx; |
1044 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 | 1045 | |
28ccd296 ME |
1046 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
1047 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
ae636747 | 1048 | dev = xhci->devs[slot_id]; |
9aad95e2 | 1049 | ep = &dev->eps[ep_index]; |
e9df17eb SS |
1050 | |
1051 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
1052 | if (!ep_ring) { | |
e587b8b2 | 1053 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
e9df17eb SS |
1054 | stream_id); |
1055 | /* XXX: Harmless??? */ | |
0d4976ec | 1056 | goto cleanup; |
e9df17eb SS |
1057 | } |
1058 | ||
d115b048 JY |
1059 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
1060 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
19a7d0d6 FB |
1061 | trace_xhci_handle_cmd_set_deq(slot_ctx); |
1062 | trace_xhci_handle_cmd_set_deq_ep(ep_ctx); | |
ae636747 | 1063 | |
c69a0597 | 1064 | if (cmd_comp_code != COMP_SUCCESS) { |
ae636747 SS |
1065 | unsigned int ep_state; |
1066 | unsigned int slot_state; | |
1067 | ||
c69a0597 | 1068 | switch (cmd_comp_code) { |
0b7c105a | 1069 | case COMP_TRB_ERROR: |
e587b8b2 | 1070 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
ae636747 | 1071 | break; |
0b7c105a | 1072 | case COMP_CONTEXT_STATE_ERROR: |
e587b8b2 | 1073 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
5071e6b2 | 1074 | ep_state = GET_EP_CTX_STATE(ep_ctx); |
28ccd296 | 1075 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 | 1076 | slot_state = GET_SLOT_STATE(slot_state); |
aa50b290 XR |
1077 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1078 | "Slot state = %u, EP state = %u", | |
ae636747 SS |
1079 | slot_state, ep_state); |
1080 | break; | |
0b7c105a | 1081 | case COMP_SLOT_NOT_ENABLED_ERROR: |
e587b8b2 ON |
1082 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
1083 | slot_id); | |
ae636747 SS |
1084 | break; |
1085 | default: | |
e587b8b2 ON |
1086 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
1087 | cmd_comp_code); | |
ae636747 SS |
1088 | break; |
1089 | } | |
1090 | /* OK what do we do now? The endpoint state is hosed, and we | |
1091 | * should never get to this point if the synchronization between | |
1092 | * queueing, and endpoint state are correct. This might happen | |
1093 | * if the device gets disconnected after we've finished | |
1094 | * cancelling URBs, which might not be an error... | |
1095 | */ | |
1096 | } else { | |
9aad95e2 HG |
1097 | u64 deq; |
1098 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ | |
1099 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1100 | struct xhci_stream_ctx *ctx = | |
1101 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1102 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; | |
1103 | } else { | |
1104 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; | |
1105 | } | |
aa50b290 | 1106 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
9aad95e2 HG |
1107 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
1108 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, | |
1109 | ep->queued_deq_ptr) == deq) { | |
bf161e85 SS |
1110 | /* Update the ring's dequeue segment and dequeue pointer |
1111 | * to reflect the new position. | |
1112 | */ | |
b008df60 AX |
1113 | update_ring_for_set_deq_completion(xhci, dev, |
1114 | ep_ring, ep_index); | |
bf161e85 | 1115 | } else { |
e587b8b2 | 1116 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
bf161e85 | 1117 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
9aad95e2 | 1118 | ep->queued_deq_seg, ep->queued_deq_ptr); |
bf161e85 | 1119 | } |
ae636747 SS |
1120 | } |
1121 | ||
0d4976ec | 1122 | cleanup: |
63a0d9ab | 1123 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
bf161e85 SS |
1124 | dev->eps[ep_index].queued_deq_seg = NULL; |
1125 | dev->eps[ep_index].queued_deq_ptr = NULL; | |
e9df17eb SS |
1126 | /* Restart any rings with pending URBs */ |
1127 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1128 | } |
1129 | ||
b8200c94 | 1130 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1131 | union xhci_trb *trb, u32 cmd_comp_code) |
a1587d97 | 1132 | { |
19a7d0d6 FB |
1133 | struct xhci_virt_device *vdev; |
1134 | struct xhci_ep_ctx *ep_ctx; | |
a1587d97 SS |
1135 | unsigned int ep_index; |
1136 | ||
28ccd296 | 1137 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
19a7d0d6 FB |
1138 | vdev = xhci->devs[slot_id]; |
1139 | ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); | |
1140 | trace_xhci_handle_cmd_reset_ep(ep_ctx); | |
1141 | ||
a1587d97 SS |
1142 | /* This command will only fail if the endpoint wasn't halted, |
1143 | * but we don't care. | |
1144 | */ | |
a0254324 | 1145 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
c69a0597 | 1146 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
a1587d97 | 1147 | |
ac9d8fe7 SS |
1148 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
1149 | * command complete before the endpoint can be used. Queue that here | |
1150 | * because the HW can't handle two commands being queued in a row. | |
1151 | */ | |
1152 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
ddba5cd0 | 1153 | struct xhci_command *command; |
74e0b564 | 1154 | |
ddba5cd0 | 1155 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); |
74e0b564 | 1156 | if (!command) |
a0ee619f | 1157 | return; |
74e0b564 | 1158 | |
4bdfe4c3 XR |
1159 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1160 | "Queueing configure endpoint command"); | |
ddba5cd0 | 1161 | xhci_queue_configure_endpoint(xhci, command, |
913a8a34 SS |
1162 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
1163 | false); | |
ac9d8fe7 SS |
1164 | xhci_ring_cmd_db(xhci); |
1165 | } else { | |
c3492dbf | 1166 | /* Clear our internal halted state */ |
63a0d9ab | 1167 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
ac9d8fe7 | 1168 | } |
a1587d97 | 1169 | } |
ae636747 | 1170 | |
b244b431 | 1171 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
c2d3d49b | 1172 | struct xhci_command *command, u32 cmd_comp_code) |
b244b431 XR |
1173 | { |
1174 | if (cmd_comp_code == COMP_SUCCESS) | |
c2d3d49b | 1175 | command->slot_id = slot_id; |
b244b431 | 1176 | else |
c2d3d49b | 1177 | command->slot_id = 0; |
b244b431 XR |
1178 | } |
1179 | ||
6c02dd14 XR |
1180 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
1181 | { | |
1182 | struct xhci_virt_device *virt_dev; | |
19a7d0d6 | 1183 | struct xhci_slot_ctx *slot_ctx; |
6c02dd14 XR |
1184 | |
1185 | virt_dev = xhci->devs[slot_id]; | |
1186 | if (!virt_dev) | |
1187 | return; | |
19a7d0d6 FB |
1188 | |
1189 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
1190 | trace_xhci_handle_cmd_disable_slot(slot_ctx); | |
1191 | ||
6c02dd14 XR |
1192 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) |
1193 | /* Delete default control endpoint resources */ | |
1194 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); | |
1195 | xhci_free_virt_device(xhci, slot_id); | |
1196 | } | |
1197 | ||
6ed46d33 XR |
1198 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
1199 | struct xhci_event_cmd *event, u32 cmd_comp_code) | |
1200 | { | |
1201 | struct xhci_virt_device *virt_dev; | |
1202 | struct xhci_input_control_ctx *ctrl_ctx; | |
19a7d0d6 | 1203 | struct xhci_ep_ctx *ep_ctx; |
6ed46d33 XR |
1204 | unsigned int ep_index; |
1205 | unsigned int ep_state; | |
1206 | u32 add_flags, drop_flags; | |
1207 | ||
6ed46d33 XR |
1208 | /* |
1209 | * Configure endpoint commands can come from the USB core | |
1210 | * configuration or alt setting changes, or because the HW | |
1211 | * needed an extra configure endpoint command after a reset | |
1212 | * endpoint command or streams were being configured. | |
1213 | * If the command was for a halted endpoint, the xHCI driver | |
1214 | * is not waiting on the configure endpoint command. | |
1215 | */ | |
9ea1833e | 1216 | virt_dev = xhci->devs[slot_id]; |
4daf9df5 | 1217 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
6ed46d33 XR |
1218 | if (!ctrl_ctx) { |
1219 | xhci_warn(xhci, "Could not get input context, bad type.\n"); | |
1220 | return; | |
1221 | } | |
1222 | ||
1223 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
1224 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
1225 | /* Input ctx add_flags are the endpoint index plus one */ | |
1226 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; | |
1227 | ||
19a7d0d6 FB |
1228 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index); |
1229 | trace_xhci_handle_cmd_config_ep(ep_ctx); | |
1230 | ||
6ed46d33 XR |
1231 | /* A usb_set_interface() call directly after clearing a halted |
1232 | * condition may race on this quirky hardware. Not worth | |
1233 | * worrying about, since this is prototype hardware. Not sure | |
1234 | * if this will work for streams, but streams support was | |
1235 | * untested on this prototype. | |
1236 | */ | |
1237 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
1238 | ep_index != (unsigned int) -1 && | |
1239 | add_flags - SLOT_FLAG == drop_flags) { | |
1240 | ep_state = virt_dev->eps[ep_index].ep_state; | |
1241 | if (!(ep_state & EP_HALTED)) | |
ddba5cd0 | 1242 | return; |
6ed46d33 XR |
1243 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1244 | "Completed config ep cmd - " | |
1245 | "last ep index = %d, state = %d", | |
1246 | ep_index, ep_state); | |
1247 | /* Clear internal halted state and restart ring(s) */ | |
1248 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; | |
1249 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
1250 | return; | |
1251 | } | |
6ed46d33 XR |
1252 | return; |
1253 | } | |
1254 | ||
19a7d0d6 FB |
1255 | static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id) |
1256 | { | |
1257 | struct xhci_virt_device *vdev; | |
1258 | struct xhci_slot_ctx *slot_ctx; | |
1259 | ||
1260 | vdev = xhci->devs[slot_id]; | |
1261 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); | |
1262 | trace_xhci_handle_cmd_addr_dev(slot_ctx); | |
1263 | } | |
1264 | ||
f681321b XR |
1265 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, |
1266 | struct xhci_event_cmd *event) | |
1267 | { | |
19a7d0d6 FB |
1268 | struct xhci_virt_device *vdev; |
1269 | struct xhci_slot_ctx *slot_ctx; | |
1270 | ||
1271 | vdev = xhci->devs[slot_id]; | |
1272 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); | |
1273 | trace_xhci_handle_cmd_reset_dev(slot_ctx); | |
1274 | ||
f681321b | 1275 | xhci_dbg(xhci, "Completed reset device command.\n"); |
9ea1833e | 1276 | if (!xhci->devs[slot_id]) |
f681321b XR |
1277 | xhci_warn(xhci, "Reset device command completion " |
1278 | "for disabled slot %u\n", slot_id); | |
1279 | } | |
1280 | ||
2c070821 XR |
1281 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
1282 | struct xhci_event_cmd *event) | |
1283 | { | |
1284 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
f4c8f03c | 1285 | xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n"); |
2c070821 XR |
1286 | return; |
1287 | } | |
1288 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1289 | "NEC firmware version %2x.%02x", | |
1290 | NEC_FW_MAJOR(le32_to_cpu(event->status)), | |
1291 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
1292 | } | |
1293 | ||
9ea1833e | 1294 | static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) |
c9aa1a2d MN |
1295 | { |
1296 | list_del(&cmd->cmd_list); | |
9ea1833e MN |
1297 | |
1298 | if (cmd->completion) { | |
1299 | cmd->status = status; | |
1300 | complete(cmd->completion); | |
1301 | } else { | |
c9aa1a2d | 1302 | kfree(cmd); |
9ea1833e | 1303 | } |
c9aa1a2d MN |
1304 | } |
1305 | ||
1306 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci) | |
1307 | { | |
1308 | struct xhci_command *cur_cmd, *tmp_cmd; | |
1309 | list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) | |
0b7c105a | 1310 | xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED); |
c9aa1a2d MN |
1311 | } |
1312 | ||
cb4d5ce5 | 1313 | void xhci_handle_command_timeout(struct work_struct *work) |
c311e391 MN |
1314 | { |
1315 | struct xhci_hcd *xhci; | |
c311e391 MN |
1316 | unsigned long flags; |
1317 | u64 hw_ring_state; | |
cb4d5ce5 OH |
1318 | |
1319 | xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer); | |
c311e391 | 1320 | |
c311e391 | 1321 | spin_lock_irqsave(&xhci->lock, flags); |
2b985467 | 1322 | |
a5a1b951 MN |
1323 | /* |
1324 | * If timeout work is pending, or current_cmd is NULL, it means we | |
1325 | * raced with command completion. Command is handled so just return. | |
1326 | */ | |
cb4d5ce5 | 1327 | if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) { |
2b985467 LB |
1328 | spin_unlock_irqrestore(&xhci->lock, flags); |
1329 | return; | |
c311e391 | 1330 | } |
2b985467 | 1331 | /* mark this command to be cancelled */ |
0b7c105a | 1332 | xhci->current_cmd->status = COMP_COMMAND_ABORTED; |
2b985467 | 1333 | |
c311e391 MN |
1334 | /* Make sure command ring is running before aborting it */ |
1335 | hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | |
d9f11ba9 MN |
1336 | if (hw_ring_state == ~(u64)0) { |
1337 | xhci_hc_died(xhci); | |
1338 | goto time_out_completed; | |
1339 | } | |
1340 | ||
c311e391 MN |
1341 | if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && |
1342 | (hw_ring_state & CMD_RING_RUNNING)) { | |
1c111b6c OH |
1343 | /* Prevent new doorbell, and start command abort */ |
1344 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; | |
c311e391 | 1345 | xhci_dbg(xhci, "Command timeout\n"); |
d9f11ba9 | 1346 | xhci_abort_cmd_ring(xhci, flags); |
4dea7077 | 1347 | goto time_out_completed; |
c311e391 | 1348 | } |
3425aa03 | 1349 | |
1c111b6c OH |
1350 | /* host removed. Bail out */ |
1351 | if (xhci->xhc_state & XHCI_STATE_REMOVING) { | |
1352 | xhci_dbg(xhci, "host removed, ring start fail?\n"); | |
3425aa03 | 1353 | xhci_cleanup_command_queue(xhci); |
4dea7077 LB |
1354 | |
1355 | goto time_out_completed; | |
3425aa03 MN |
1356 | } |
1357 | ||
c311e391 MN |
1358 | /* command timeout on stopped ring, ring can't be aborted */ |
1359 | xhci_dbg(xhci, "Command timeout on stopped ring\n"); | |
1360 | xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); | |
4dea7077 LB |
1361 | |
1362 | time_out_completed: | |
c311e391 MN |
1363 | spin_unlock_irqrestore(&xhci->lock, flags); |
1364 | return; | |
1365 | } | |
1366 | ||
7f84eef0 SS |
1367 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1368 | struct xhci_event_cmd *event) | |
1369 | { | |
28ccd296 | 1370 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1371 | u64 cmd_dma; |
1372 | dma_addr_t cmd_dequeue_dma; | |
e7a79a1d | 1373 | u32 cmd_comp_code; |
9124b121 | 1374 | union xhci_trb *cmd_trb; |
c9aa1a2d | 1375 | struct xhci_command *cmd; |
b54fc46d | 1376 | u32 cmd_type; |
7f84eef0 | 1377 | |
28ccd296 | 1378 | cmd_dma = le64_to_cpu(event->cmd_trb); |
9124b121 | 1379 | cmd_trb = xhci->cmd_ring->dequeue; |
a37c3f76 FB |
1380 | |
1381 | trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic); | |
1382 | ||
23e3be11 | 1383 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
9124b121 | 1384 | cmd_trb); |
f4c8f03c LB |
1385 | /* |
1386 | * Check whether the completion event is for our internal kept | |
1387 | * command. | |
1388 | */ | |
1389 | if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) { | |
1390 | xhci_warn(xhci, | |
1391 | "ERROR mismatched command completion event\n"); | |
7f84eef0 SS |
1392 | return; |
1393 | } | |
b63f4053 | 1394 | |
04861f83 | 1395 | cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list); |
c9aa1a2d | 1396 | |
cb4d5ce5 | 1397 | cancel_delayed_work(&xhci->cmd_timer); |
c311e391 | 1398 | |
e7a79a1d | 1399 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
c311e391 MN |
1400 | |
1401 | /* If CMD ring stopped we own the trbs between enqueue and dequeue */ | |
604d02a2 | 1402 | if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) { |
1c111b6c | 1403 | complete_all(&xhci->cmd_ring_stop_completion); |
c311e391 MN |
1404 | return; |
1405 | } | |
33be1265 MN |
1406 | |
1407 | if (cmd->command_trb != xhci->cmd_ring->dequeue) { | |
1408 | xhci_err(xhci, | |
1409 | "Command completion event does not match command\n"); | |
1410 | return; | |
1411 | } | |
1412 | ||
c311e391 MN |
1413 | /* |
1414 | * Host aborted the command ring, check if the current command was | |
1415 | * supposed to be aborted, otherwise continue normally. | |
1416 | * The command ring is stopped now, but the xHC will issue a Command | |
1417 | * Ring Stopped event which will cause us to restart it. | |
1418 | */ | |
0b7c105a | 1419 | if (cmd_comp_code == COMP_COMMAND_ABORTED) { |
c311e391 | 1420 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; |
0b7c105a | 1421 | if (cmd->status == COMP_COMMAND_ABORTED) { |
2a7cfdf3 BW |
1422 | if (xhci->current_cmd == cmd) |
1423 | xhci->current_cmd = NULL; | |
c311e391 | 1424 | goto event_handled; |
2a7cfdf3 | 1425 | } |
b63f4053 EF |
1426 | } |
1427 | ||
b54fc46d XR |
1428 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
1429 | switch (cmd_type) { | |
1430 | case TRB_ENABLE_SLOT: | |
c2d3d49b | 1431 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code); |
3ffbba95 | 1432 | break; |
b54fc46d | 1433 | case TRB_DISABLE_SLOT: |
6c02dd14 | 1434 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
3ffbba95 | 1435 | break; |
b54fc46d | 1436 | case TRB_CONFIG_EP: |
9ea1833e MN |
1437 | if (!cmd->completion) |
1438 | xhci_handle_cmd_config_ep(xhci, slot_id, event, | |
1439 | cmd_comp_code); | |
f94e0186 | 1440 | break; |
b54fc46d | 1441 | case TRB_EVAL_CONTEXT: |
2d3f1fac | 1442 | break; |
b54fc46d | 1443 | case TRB_ADDR_DEV: |
19a7d0d6 | 1444 | xhci_handle_cmd_addr_dev(xhci, slot_id); |
3ffbba95 | 1445 | break; |
b54fc46d | 1446 | case TRB_STOP_RING: |
b8200c94 XR |
1447 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1448 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
1449 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); | |
ae636747 | 1450 | break; |
b54fc46d | 1451 | case TRB_SET_DEQ: |
b8200c94 XR |
1452 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1453 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1454 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
ae636747 | 1455 | break; |
b54fc46d | 1456 | case TRB_CMD_NOOP: |
c311e391 | 1457 | /* Is this an aborted command turned to NO-OP? */ |
604d02a2 MN |
1458 | if (cmd->status == COMP_COMMAND_RING_STOPPED) |
1459 | cmd_comp_code = COMP_COMMAND_RING_STOPPED; | |
7f84eef0 | 1460 | break; |
b54fc46d | 1461 | case TRB_RESET_EP: |
b8200c94 XR |
1462 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1463 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1464 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
a1587d97 | 1465 | break; |
b54fc46d | 1466 | case TRB_RESET_DEV: |
6fcfb0d6 MN |
1467 | /* SLOT_ID field in reset device cmd completion event TRB is 0. |
1468 | * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) | |
1469 | */ | |
1470 | slot_id = TRB_TO_SLOT_ID( | |
1471 | le32_to_cpu(cmd_trb->generic.field[3])); | |
f681321b | 1472 | xhci_handle_cmd_reset_dev(xhci, slot_id, event); |
2a8f82c4 | 1473 | break; |
b54fc46d | 1474 | case TRB_NEC_GET_FW: |
2c070821 | 1475 | xhci_handle_cmd_nec_get_fw(xhci, event); |
0238634d | 1476 | break; |
7f84eef0 SS |
1477 | default: |
1478 | /* Skip over unknown commands on the event ring */ | |
f4c8f03c | 1479 | xhci_info(xhci, "INFO unknown command type %d\n", cmd_type); |
7f84eef0 SS |
1480 | break; |
1481 | } | |
c9aa1a2d | 1482 | |
c311e391 | 1483 | /* restart timer if this wasn't the last command */ |
daa47f21 | 1484 | if (!list_is_singular(&xhci->cmd_list)) { |
04861f83 FB |
1485 | xhci->current_cmd = list_first_entry(&cmd->cmd_list, |
1486 | struct xhci_command, cmd_list); | |
cb4d5ce5 | 1487 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
2b985467 LB |
1488 | } else if (xhci->current_cmd == cmd) { |
1489 | xhci->current_cmd = NULL; | |
c311e391 MN |
1490 | } |
1491 | ||
1492 | event_handled: | |
9ea1833e | 1493 | xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); |
c9aa1a2d | 1494 | |
3b72fca0 | 1495 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1496 | } |
1497 | ||
0238634d SS |
1498 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1499 | union xhci_trb *event) | |
1500 | { | |
1501 | u32 trb_type; | |
1502 | ||
28ccd296 | 1503 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
0238634d SS |
1504 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1505 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1506 | handle_cmd_completion(xhci, &event->event_cmd); | |
1507 | } | |
1508 | ||
f6ff0ac8 SS |
1509 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
1510 | * port registers -- USB 3.0 and USB 2.0). | |
1511 | * | |
1512 | * Returns a zero-based port number, which is suitable for indexing into each of | |
1513 | * the split roothubs' port arrays and bus state arrays. | |
d0cd5d48 | 1514 | * Add one to it in order to call xhci_find_slot_id_by_port. |
f6ff0ac8 SS |
1515 | */ |
1516 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, | |
1517 | struct xhci_hcd *xhci, u32 port_id) | |
1518 | { | |
1519 | unsigned int i; | |
1520 | unsigned int num_similar_speed_ports = 0; | |
1521 | ||
1522 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], | |
1523 | * and usb2_ports are 0-based indexes. Count the number of similar | |
1524 | * speed ports, up to 1 port before this port. | |
1525 | */ | |
1526 | for (i = 0; i < (port_id - 1); i++) { | |
1527 | u8 port_speed = xhci->port_array[i]; | |
1528 | ||
1529 | /* | |
1530 | * Skip ports that don't have known speeds, or have duplicate | |
1531 | * Extended Capabilities port speed entries. | |
1532 | */ | |
22e04870 | 1533 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
1534 | continue; |
1535 | ||
1536 | /* | |
1537 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
1538 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
1539 | * matches the device speed, it's a similar speed port. | |
1540 | */ | |
b50107bb | 1541 | if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3)) |
f6ff0ac8 SS |
1542 | num_similar_speed_ports++; |
1543 | } | |
1544 | return num_similar_speed_ports; | |
1545 | } | |
1546 | ||
623bef9e SS |
1547 | static void handle_device_notification(struct xhci_hcd *xhci, |
1548 | union xhci_trb *event) | |
1549 | { | |
1550 | u32 slot_id; | |
4ee823b8 | 1551 | struct usb_device *udev; |
623bef9e | 1552 | |
7e76ad43 | 1553 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
4ee823b8 | 1554 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1555 | xhci_warn(xhci, "Device Notification event for " |
1556 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1557 | return; |
1558 | } | |
1559 | ||
1560 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1561 | slot_id); | |
1562 | udev = xhci->devs[slot_id]->udev; | |
1563 | if (udev && udev->parent) | |
1564 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1565 | } |
1566 | ||
0f2a7930 SS |
1567 | static void handle_port_status(struct xhci_hcd *xhci, |
1568 | union xhci_trb *event) | |
1569 | { | |
f6ff0ac8 | 1570 | struct usb_hcd *hcd; |
0f2a7930 | 1571 | u32 port_id; |
56192531 | 1572 | u32 temp, temp1; |
518e848e | 1573 | int max_ports; |
56192531 | 1574 | int slot_id; |
5308a91b | 1575 | unsigned int faked_port_index; |
f6ff0ac8 | 1576 | u8 major_revision; |
20b67cf5 | 1577 | struct xhci_bus_state *bus_state; |
28ccd296 | 1578 | __le32 __iomem **port_array; |
386139d7 | 1579 | bool bogus_port_status = false; |
0f2a7930 SS |
1580 | |
1581 | /* Port status change events always have a successful completion code */ | |
f4c8f03c LB |
1582 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) |
1583 | xhci_warn(xhci, | |
1584 | "WARN: xHC returned failed port status event\n"); | |
1585 | ||
28ccd296 | 1586 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
0f2a7930 SS |
1587 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
1588 | ||
518e848e SS |
1589 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1590 | if ((port_id <= 0) || (port_id > max_ports)) { | |
56192531 | 1591 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
09ce0c0c PC |
1592 | inc_deq(xhci, xhci->event_ring); |
1593 | return; | |
56192531 AX |
1594 | } |
1595 | ||
f6ff0ac8 SS |
1596 | /* Figure out which usb_hcd this port is attached to: |
1597 | * is it a USB 3.0 port or a USB 2.0/1.1 port? | |
1598 | */ | |
1599 | major_revision = xhci->port_array[port_id - 1]; | |
09ce0c0c PC |
1600 | |
1601 | /* Find the right roothub. */ | |
1602 | hcd = xhci_to_hcd(xhci); | |
b50107bb | 1603 | if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3)) |
09ce0c0c PC |
1604 | hcd = xhci->shared_hcd; |
1605 | ||
f6ff0ac8 SS |
1606 | if (major_revision == 0) { |
1607 | xhci_warn(xhci, "Event for port %u not in " | |
1608 | "Extended Capabilities, ignoring.\n", | |
1609 | port_id); | |
386139d7 | 1610 | bogus_port_status = true; |
f6ff0ac8 | 1611 | goto cleanup; |
5308a91b | 1612 | } |
22e04870 | 1613 | if (major_revision == DUPLICATE_ENTRY) { |
f6ff0ac8 SS |
1614 | xhci_warn(xhci, "Event for port %u duplicated in" |
1615 | "Extended Capabilities, ignoring.\n", | |
1616 | port_id); | |
386139d7 | 1617 | bogus_port_status = true; |
f6ff0ac8 SS |
1618 | goto cleanup; |
1619 | } | |
1620 | ||
1621 | /* | |
1622 | * Hardware port IDs reported by a Port Status Change Event include USB | |
1623 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a | |
1624 | * resume event, but we first need to translate the hardware port ID | |
1625 | * into the index into the ports on the correct split roothub, and the | |
1626 | * correct bus_state structure. | |
1627 | */ | |
f6ff0ac8 | 1628 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
b50107bb | 1629 | if (hcd->speed >= HCD_USB3) |
f6ff0ac8 SS |
1630 | port_array = xhci->usb3_ports; |
1631 | else | |
1632 | port_array = xhci->usb2_ports; | |
1633 | /* Find the faked port hub number */ | |
1634 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, | |
1635 | port_id); | |
5308a91b | 1636 | |
b0ba9720 | 1637 | temp = readl(port_array[faked_port_index]); |
7111ebc9 | 1638 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1639 | xhci_dbg(xhci, "resume root hub\n"); |
1640 | usb_hcd_resume_root_hub(hcd); | |
1641 | } | |
1642 | ||
b50107bb | 1643 | if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE) |
fac4271d ZJC |
1644 | bus_state->port_remote_wakeup &= ~(1 << faked_port_index); |
1645 | ||
56192531 AX |
1646 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { |
1647 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | |
1648 | ||
b0ba9720 | 1649 | temp1 = readl(&xhci->op_regs->command); |
56192531 AX |
1650 | if (!(temp1 & CMD_RUN)) { |
1651 | xhci_warn(xhci, "xHC is not running.\n"); | |
1652 | goto cleanup; | |
1653 | } | |
1654 | ||
2338b9e4 | 1655 | if (DEV_SUPERSPEED_ANY(temp)) { |
d93814cf | 1656 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1657 | /* Set a flag to say the port signaled remote wakeup, |
1658 | * so we can tell the difference between the end of | |
1659 | * device and host initiated resume. | |
1660 | */ | |
1661 | bus_state->port_remote_wakeup |= 1 << faked_port_index; | |
d93814cf SS |
1662 | xhci_test_and_clear_bit(xhci, port_array, |
1663 | faked_port_index, PORT_PLC); | |
c9682dff AX |
1664 | xhci_set_link_state(xhci, port_array, faked_port_index, |
1665 | XDEV_U0); | |
d93814cf SS |
1666 | /* Need to wait until the next link state change |
1667 | * indicates the device is actually in U0. | |
1668 | */ | |
1669 | bogus_port_status = true; | |
1670 | goto cleanup; | |
f69115fd MN |
1671 | } else if (!test_bit(faked_port_index, |
1672 | &bus_state->resuming_ports)) { | |
56192531 | 1673 | xhci_dbg(xhci, "resume HS port %d\n", port_id); |
f6ff0ac8 | 1674 | bus_state->resume_done[faked_port_index] = jiffies + |
b9e45188 | 1675 | msecs_to_jiffies(USB_RESUME_TIMEOUT); |
f370b996 | 1676 | set_bit(faked_port_index, &bus_state->resuming_ports); |
56192531 | 1677 | mod_timer(&hcd->rh_timer, |
f6ff0ac8 | 1678 | bus_state->resume_done[faked_port_index]); |
56192531 AX |
1679 | /* Do the rest in GetPortStatus */ |
1680 | } | |
1681 | } | |
d93814cf SS |
1682 | |
1683 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && | |
2338b9e4 | 1684 | DEV_SUPERSPEED_ANY(temp)) { |
d93814cf | 1685 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); |
4ee823b8 SS |
1686 | /* We've just brought the device into U0 through either the |
1687 | * Resume state after a device remote wakeup, or through the | |
1688 | * U3Exit state after a host-initiated resume. If it's a device | |
1689 | * initiated remote wake, don't pass up the link state change, | |
1690 | * so the roothub behavior is consistent with external | |
1691 | * USB 3.0 hub behavior. | |
1692 | */ | |
d93814cf SS |
1693 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1694 | faked_port_index + 1); | |
1695 | if (slot_id && xhci->devs[slot_id]) | |
1696 | xhci_ring_device(xhci, slot_id); | |
ba7b5c22 | 1697 | if (bus_state->port_remote_wakeup & (1 << faked_port_index)) { |
4ee823b8 SS |
1698 | bus_state->port_remote_wakeup &= |
1699 | ~(1 << faked_port_index); | |
1700 | xhci_test_and_clear_bit(xhci, port_array, | |
1701 | faked_port_index, PORT_PLC); | |
1702 | usb_wakeup_notification(hcd->self.root_hub, | |
1703 | faked_port_index + 1); | |
1704 | bogus_port_status = true; | |
1705 | goto cleanup; | |
1706 | } | |
d93814cf | 1707 | } |
56192531 | 1708 | |
8b3d4570 SS |
1709 | /* |
1710 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or | |
1711 | * RExit to a disconnect state). If so, let the the driver know it's | |
1712 | * out of the RExit state. | |
1713 | */ | |
2338b9e4 | 1714 | if (!DEV_SUPERSPEED_ANY(temp) && |
8b3d4570 SS |
1715 | test_and_clear_bit(faked_port_index, |
1716 | &bus_state->rexit_ports)) { | |
1717 | complete(&bus_state->rexit_done[faked_port_index]); | |
1718 | bogus_port_status = true; | |
1719 | goto cleanup; | |
1720 | } | |
1721 | ||
b50107bb | 1722 | if (hcd->speed < HCD_USB3) |
6fd45621 AX |
1723 | xhci_test_and_clear_bit(xhci, port_array, faked_port_index, |
1724 | PORT_PLC); | |
1725 | ||
56192531 | 1726 | cleanup: |
0f2a7930 | 1727 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 1728 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 1729 | |
386139d7 SS |
1730 | /* Don't make the USB core poll the roothub if we got a bad port status |
1731 | * change event. Besides, at that point we can't tell which roothub | |
1732 | * (USB 2.0 or USB 3.0) to kick. | |
1733 | */ | |
1734 | if (bogus_port_status) | |
1735 | return; | |
1736 | ||
c52804a4 SS |
1737 | /* |
1738 | * xHCI port-status-change events occur when the "or" of all the | |
1739 | * status-change bits in the portsc register changes from 0 to 1. | |
1740 | * New status changes won't cause an event if any other change | |
1741 | * bits are still set. When an event occurs, switch over to | |
1742 | * polling to avoid losing status changes. | |
1743 | */ | |
1744 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1745 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1746 | spin_unlock(&xhci->lock); |
1747 | /* Pass this up to the core */ | |
f6ff0ac8 | 1748 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
1749 | spin_lock(&xhci->lock); |
1750 | } | |
1751 | ||
d0e96f5a SS |
1752 | /* |
1753 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1754 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1755 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1756 | * returns 0. | |
1757 | */ | |
cffb9be8 HG |
1758 | struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, |
1759 | struct xhci_segment *start_seg, | |
d0e96f5a SS |
1760 | union xhci_trb *start_trb, |
1761 | union xhci_trb *end_trb, | |
cffb9be8 HG |
1762 | dma_addr_t suspect_dma, |
1763 | bool debug) | |
d0e96f5a SS |
1764 | { |
1765 | dma_addr_t start_dma; | |
1766 | dma_addr_t end_seg_dma; | |
1767 | dma_addr_t end_trb_dma; | |
1768 | struct xhci_segment *cur_seg; | |
1769 | ||
23e3be11 | 1770 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1771 | cur_seg = start_seg; |
1772 | ||
1773 | do { | |
2fa88daa | 1774 | if (start_dma == 0) |
326b4810 | 1775 | return NULL; |
ae636747 | 1776 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1777 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1778 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1779 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1780 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a | 1781 | |
cffb9be8 HG |
1782 | if (debug) |
1783 | xhci_warn(xhci, | |
1784 | "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", | |
1785 | (unsigned long long)suspect_dma, | |
1786 | (unsigned long long)start_dma, | |
1787 | (unsigned long long)end_trb_dma, | |
1788 | (unsigned long long)cur_seg->dma, | |
1789 | (unsigned long long)end_seg_dma); | |
1790 | ||
d0e96f5a SS |
1791 | if (end_trb_dma > 0) { |
1792 | /* The end TRB is in this segment, so suspect should be here */ | |
1793 | if (start_dma <= end_trb_dma) { | |
1794 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1795 | return cur_seg; | |
1796 | } else { | |
1797 | /* Case for one segment with | |
1798 | * a TD wrapped around to the top | |
1799 | */ | |
1800 | if ((suspect_dma >= start_dma && | |
1801 | suspect_dma <= end_seg_dma) || | |
1802 | (suspect_dma >= cur_seg->dma && | |
1803 | suspect_dma <= end_trb_dma)) | |
1804 | return cur_seg; | |
1805 | } | |
326b4810 | 1806 | return NULL; |
d0e96f5a SS |
1807 | } else { |
1808 | /* Might still be somewhere in this segment */ | |
1809 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1810 | return cur_seg; | |
1811 | } | |
1812 | cur_seg = cur_seg->next; | |
23e3be11 | 1813 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1814 | } while (cur_seg != start_seg); |
d0e96f5a | 1815 | |
326b4810 | 1816 | return NULL; |
d0e96f5a SS |
1817 | } |
1818 | ||
bcef3fd5 SS |
1819 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1820 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1821 | unsigned int stream_id, |
5eee4b6b MN |
1822 | struct xhci_td *td, union xhci_trb *ep_trb, |
1823 | enum xhci_ep_reset_type reset_type) | |
bcef3fd5 SS |
1824 | { |
1825 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
ddba5cd0 MN |
1826 | struct xhci_command *command; |
1827 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
1828 | if (!command) | |
1829 | return; | |
1830 | ||
d0167ad2 | 1831 | ep->ep_state |= EP_HALTED; |
1624ae1c | 1832 | |
5eee4b6b | 1833 | xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type); |
1624ae1c | 1834 | |
d36374fd MN |
1835 | if (reset_type == EP_HARD_RESET) |
1836 | xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td); | |
1624ae1c | 1837 | |
bcef3fd5 SS |
1838 | xhci_ring_cmd_db(xhci); |
1839 | } | |
1840 | ||
1841 | /* Check if an error has halted the endpoint ring. The class driver will | |
1842 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1843 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1844 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1845 | * Ring Dequeue Pointer command manually. | |
1846 | */ | |
1847 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1848 | struct xhci_ep_ctx *ep_ctx, | |
1849 | unsigned int trb_comp_code) | |
1850 | { | |
1851 | /* TRB completion codes that may require a manual halt cleanup */ | |
0b7c105a FB |
1852 | if (trb_comp_code == COMP_USB_TRANSACTION_ERROR || |
1853 | trb_comp_code == COMP_BABBLE_DETECTED_ERROR || | |
1854 | trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR) | |
d4fc8bf5 | 1855 | /* The 0.95 spec says a babbling control endpoint |
bcef3fd5 SS |
1856 | * is not halted. The 0.96 spec says it is. Some HW |
1857 | * claims to be 0.95 compliant, but it halts the control | |
1858 | * endpoint anyway. Check if a babble halted the | |
1859 | * endpoint. | |
1860 | */ | |
5071e6b2 | 1861 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED) |
bcef3fd5 SS |
1862 | return 1; |
1863 | ||
1864 | return 0; | |
1865 | } | |
1866 | ||
b45b5069 SS |
1867 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1868 | { | |
1869 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1870 | /* Vendor defined "informational" completion code, | |
1871 | * treat as not-an-error. | |
1872 | */ | |
1873 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1874 | trb_comp_code); | |
1875 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1876 | return 1; | |
1877 | } | |
1878 | return 0; | |
1879 | } | |
1880 | ||
55fa4396 FB |
1881 | static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td, |
1882 | struct xhci_ring *ep_ring, int *status) | |
1883 | { | |
1884 | struct urb_priv *urb_priv; | |
1885 | struct urb *urb = NULL; | |
1886 | ||
1887 | /* Clean up the endpoint's TD list */ | |
1888 | urb = td->urb; | |
1889 | urb_priv = urb->hcpriv; | |
1890 | ||
1891 | /* if a bounce buffer was used to align this td then unmap it */ | |
a60f2f2f | 1892 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); |
55fa4396 FB |
1893 | |
1894 | /* Do one last check of the actual transfer length. | |
1895 | * If the host controller said we transferred more data than the buffer | |
1896 | * length, urb->actual_length will be a very big number (since it's | |
1897 | * unsigned). Play it safe and say we didn't transfer anything. | |
1898 | */ | |
1899 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1900 | xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", | |
1901 | urb->transfer_buffer_length, urb->actual_length); | |
1902 | urb->actual_length = 0; | |
1903 | *status = 0; | |
1904 | } | |
1905 | list_del_init(&td->td_list); | |
1906 | /* Was this TD slated to be cancelled but completed anyway? */ | |
1907 | if (!list_empty(&td->cancelled_td_list)) | |
1908 | list_del_init(&td->cancelled_td_list); | |
1909 | ||
1910 | inc_td_cnt(urb); | |
1911 | /* Giveback the urb when all the tds are completed */ | |
1912 | if (last_td_in_urb(td)) { | |
1913 | if ((urb->actual_length != urb->transfer_buffer_length && | |
1914 | (urb->transfer_flags & URB_SHORT_NOT_OK)) || | |
1915 | (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) | |
1916 | xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", | |
1917 | urb, urb->actual_length, | |
1918 | urb->transfer_buffer_length, *status); | |
1919 | ||
1920 | /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ | |
1921 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
1922 | *status = 0; | |
1923 | xhci_giveback_urb_in_irq(xhci, td, *status); | |
1924 | } | |
1925 | ||
1926 | return 0; | |
1927 | } | |
1928 | ||
4422da61 | 1929 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, |
f97c08ae | 1930 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
4422da61 AX |
1931 | struct xhci_virt_ep *ep, int *status, bool skip) |
1932 | { | |
1933 | struct xhci_virt_device *xdev; | |
4422da61 | 1934 | struct xhci_ep_ctx *ep_ctx; |
be0f50c2 | 1935 | struct xhci_ring *ep_ring; |
be0f50c2 | 1936 | unsigned int slot_id; |
4422da61 | 1937 | u32 trb_comp_code; |
be0f50c2 | 1938 | int ep_index; |
4422da61 | 1939 | |
28ccd296 | 1940 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
4422da61 | 1941 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1942 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1943 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
4422da61 | 1944 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1945 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
4422da61 AX |
1946 | |
1947 | if (skip) | |
1948 | goto td_cleanup; | |
1949 | ||
0b7c105a FB |
1950 | if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID || |
1951 | trb_comp_code == COMP_STOPPED || | |
1952 | trb_comp_code == COMP_STOPPED_SHORT_PACKET) { | |
4422da61 AX |
1953 | /* The Endpoint Stop Command completion will take care of any |
1954 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1955 | * the ring dequeue pointer or take this TD off any lists yet. | |
1956 | */ | |
4422da61 | 1957 | return 0; |
69defe04 | 1958 | } |
0b7c105a | 1959 | if (trb_comp_code == COMP_STALL_ERROR || |
69defe04 MN |
1960 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, |
1961 | trb_comp_code)) { | |
1962 | /* Issue a reset endpoint command to clear the host side | |
1963 | * halt, followed by a set dequeue command to move the | |
1964 | * dequeue pointer past the TD. | |
1965 | * The class driver clears the device side halt later. | |
1966 | */ | |
1967 | xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, | |
5eee4b6b MN |
1968 | ep_ring->stream_id, td, ep_trb, |
1969 | EP_HARD_RESET); | |
4422da61 | 1970 | } else { |
69defe04 MN |
1971 | /* Update ring dequeue pointer */ |
1972 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 | 1973 | inc_deq(xhci, ep_ring); |
69defe04 MN |
1974 | inc_deq(xhci, ep_ring); |
1975 | } | |
4422da61 AX |
1976 | |
1977 | td_cleanup: | |
55fa4396 | 1978 | return xhci_td_cleanup(xhci, td, ep_ring, status); |
4422da61 AX |
1979 | } |
1980 | ||
30a65b45 MN |
1981 | /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */ |
1982 | static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
1983 | union xhci_trb *stop_trb) | |
1984 | { | |
1985 | u32 sum; | |
1986 | union xhci_trb *trb = ring->dequeue; | |
1987 | struct xhci_segment *seg = ring->deq_seg; | |
1988 | ||
1989 | for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) { | |
1990 | if (!trb_is_noop(trb) && !trb_is_link(trb)) | |
1991 | sum += TRB_LEN(le32_to_cpu(trb->generic.field[2])); | |
1992 | } | |
1993 | return sum; | |
1994 | } | |
1995 | ||
8af56be1 AX |
1996 | /* |
1997 | * Process control tds, update urb status and actual_length. | |
1998 | */ | |
1999 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 2000 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
8af56be1 AX |
2001 | struct xhci_virt_ep *ep, int *status) |
2002 | { | |
2003 | struct xhci_virt_device *xdev; | |
2004 | struct xhci_ring *ep_ring; | |
2005 | unsigned int slot_id; | |
2006 | int ep_index; | |
2007 | struct xhci_ep_ctx *ep_ctx; | |
2008 | u32 trb_comp_code; | |
0b6c324c | 2009 | u32 remaining, requested; |
29fc1aa4 | 2010 | u32 trb_type; |
8af56be1 | 2011 | |
29fc1aa4 | 2012 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3])); |
28ccd296 | 2013 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
8af56be1 | 2014 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
2015 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
2016 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
8af56be1 | 2017 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 2018 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
0b6c324c MN |
2019 | requested = td->urb->transfer_buffer_length; |
2020 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2021 | ||
8af56be1 AX |
2022 | switch (trb_comp_code) { |
2023 | case COMP_SUCCESS: | |
29fc1aa4 | 2024 | if (trb_type != TRB_STATUS) { |
0b6c324c | 2025 | xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n", |
29fc1aa4 | 2026 | (trb_type == TRB_DATA) ? "data" : "setup"); |
8af56be1 | 2027 | *status = -ESHUTDOWN; |
0b6c324c | 2028 | break; |
8af56be1 | 2029 | } |
0b6c324c | 2030 | *status = 0; |
8af56be1 | 2031 | break; |
0b7c105a | 2032 | case COMP_SHORT_PACKET: |
0b6c324c | 2033 | *status = 0; |
8af56be1 | 2034 | break; |
0b7c105a | 2035 | case COMP_STOPPED_SHORT_PACKET: |
29fc1aa4 | 2036 | if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) |
0b6c324c | 2037 | td->urb->actual_length = remaining; |
40a3b775 | 2038 | else |
0b6c324c MN |
2039 | xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); |
2040 | goto finish_td; | |
0b7c105a | 2041 | case COMP_STOPPED: |
29fc1aa4 FB |
2042 | switch (trb_type) { |
2043 | case TRB_SETUP: | |
2044 | td->urb->actual_length = 0; | |
2045 | goto finish_td; | |
2046 | case TRB_DATA: | |
2047 | case TRB_NORMAL: | |
0b6c324c | 2048 | td->urb->actual_length = requested - remaining; |
29fc1aa4 | 2049 | goto finish_td; |
0ab2881a MN |
2050 | case TRB_STATUS: |
2051 | td->urb->actual_length = requested; | |
2052 | goto finish_td; | |
29fc1aa4 FB |
2053 | default: |
2054 | xhci_warn(xhci, "WARN: unexpected TRB Type %d\n", | |
2055 | trb_type); | |
2056 | goto finish_td; | |
2057 | } | |
0b7c105a | 2058 | case COMP_STOPPED_LENGTH_INVALID: |
0b6c324c | 2059 | goto finish_td; |
8af56be1 AX |
2060 | default: |
2061 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
0b6c324c | 2062 | ep_ctx, trb_comp_code)) |
8af56be1 | 2063 | break; |
0b6c324c MN |
2064 | xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n", |
2065 | trb_comp_code, ep_index); | |
8af56be1 | 2066 | /* else fall through */ |
0b7c105a | 2067 | case COMP_STALL_ERROR: |
8af56be1 | 2068 | /* Did we transfer part of the data (middle) phase? */ |
29fc1aa4 | 2069 | if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) |
0b6c324c | 2070 | td->urb->actual_length = requested - remaining; |
22ae47e6 | 2071 | else if (!td->urb_length_set) |
8af56be1 | 2072 | td->urb->actual_length = 0; |
0b6c324c | 2073 | goto finish_td; |
8af56be1 | 2074 | } |
0b6c324c MN |
2075 | |
2076 | /* stopped at setup stage, no data transferred */ | |
29fc1aa4 | 2077 | if (trb_type == TRB_SETUP) |
0b6c324c MN |
2078 | goto finish_td; |
2079 | ||
8af56be1 | 2080 | /* |
0b6c324c MN |
2081 | * if on data stage then update the actual_length of the URB and flag it |
2082 | * as set, so it won't be overwritten in the event for the last TRB. | |
8af56be1 | 2083 | */ |
29fc1aa4 FB |
2084 | if (trb_type == TRB_DATA || |
2085 | trb_type == TRB_NORMAL) { | |
0b6c324c MN |
2086 | td->urb_length_set = true; |
2087 | td->urb->actual_length = requested - remaining; | |
2088 | xhci_dbg(xhci, "Waiting for status stage event\n"); | |
2089 | return 0; | |
8af56be1 AX |
2090 | } |
2091 | ||
0b6c324c MN |
2092 | /* at status stage */ |
2093 | if (!td->urb_length_set) | |
2094 | td->urb->actual_length = requested; | |
2095 | ||
2096 | finish_td: | |
f97c08ae | 2097 | return finish_td(xhci, td, ep_trb, event, ep, status, false); |
8af56be1 AX |
2098 | } |
2099 | ||
04e51901 AX |
2100 | /* |
2101 | * Process isochronous tds, update urb packet status and actual_length. | |
2102 | */ | |
2103 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 2104 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
04e51901 AX |
2105 | struct xhci_virt_ep *ep, int *status) |
2106 | { | |
2107 | struct xhci_ring *ep_ring; | |
2108 | struct urb_priv *urb_priv; | |
2109 | int idx; | |
926008c9 | 2110 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 2111 | u32 trb_comp_code; |
36da3a1d MN |
2112 | bool sum_trbs_for_length = false; |
2113 | u32 remaining, requested, ep_trb_len; | |
2114 | int short_framestatus; | |
04e51901 | 2115 | |
28ccd296 ME |
2116 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2117 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
04e51901 | 2118 | urb_priv = td->urb->hcpriv; |
9ef7fbbb | 2119 | idx = urb_priv->num_tds_done; |
926008c9 | 2120 | frame = &td->urb->iso_frame_desc[idx]; |
36da3a1d MN |
2121 | requested = frame->length; |
2122 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2123 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); | |
2124 | short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
2125 | -EREMOTEIO : 0; | |
04e51901 | 2126 | |
926008c9 DT |
2127 | /* handle completion code */ |
2128 | switch (trb_comp_code) { | |
2129 | case COMP_SUCCESS: | |
36da3a1d MN |
2130 | if (remaining) { |
2131 | frame->status = short_framestatus; | |
2132 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2133 | sum_trbs_for_length = true; | |
1530bbc6 SS |
2134 | break; |
2135 | } | |
36da3a1d MN |
2136 | frame->status = 0; |
2137 | break; | |
0b7c105a | 2138 | case COMP_SHORT_PACKET: |
36da3a1d MN |
2139 | frame->status = short_framestatus; |
2140 | sum_trbs_for_length = true; | |
926008c9 | 2141 | break; |
0b7c105a | 2142 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
926008c9 | 2143 | frame->status = -ECOMM; |
926008c9 | 2144 | break; |
0b7c105a FB |
2145 | case COMP_ISOCH_BUFFER_OVERRUN: |
2146 | case COMP_BABBLE_DETECTED_ERROR: | |
926008c9 | 2147 | frame->status = -EOVERFLOW; |
926008c9 | 2148 | break; |
0b7c105a FB |
2149 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
2150 | case COMP_STALL_ERROR: | |
d104d015 | 2151 | frame->status = -EPROTO; |
d104d015 | 2152 | break; |
0b7c105a | 2153 | case COMP_USB_TRANSACTION_ERROR: |
926008c9 | 2154 | frame->status = -EPROTO; |
f97c08ae | 2155 | if (ep_trb != td->last_trb) |
d104d015 | 2156 | return 0; |
926008c9 | 2157 | break; |
0b7c105a | 2158 | case COMP_STOPPED: |
36da3a1d MN |
2159 | sum_trbs_for_length = true; |
2160 | break; | |
0b7c105a | 2161 | case COMP_STOPPED_SHORT_PACKET: |
36da3a1d MN |
2162 | /* field normally containing residue now contains tranferred */ |
2163 | frame->status = short_framestatus; | |
2164 | requested = remaining; | |
2165 | break; | |
0b7c105a | 2166 | case COMP_STOPPED_LENGTH_INVALID: |
36da3a1d MN |
2167 | requested = 0; |
2168 | remaining = 0; | |
926008c9 DT |
2169 | break; |
2170 | default: | |
36da3a1d | 2171 | sum_trbs_for_length = true; |
926008c9 DT |
2172 | frame->status = -1; |
2173 | break; | |
04e51901 AX |
2174 | } |
2175 | ||
36da3a1d MN |
2176 | if (sum_trbs_for_length) |
2177 | frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) + | |
2178 | ep_trb_len - remaining; | |
2179 | else | |
2180 | frame->actual_length = requested; | |
04e51901 | 2181 | |
36da3a1d | 2182 | td->urb->actual_length += frame->actual_length; |
04e51901 | 2183 | |
f97c08ae | 2184 | return finish_td(xhci, td, ep_trb, event, ep, status, false); |
04e51901 AX |
2185 | } |
2186 | ||
926008c9 DT |
2187 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
2188 | struct xhci_transfer_event *event, | |
2189 | struct xhci_virt_ep *ep, int *status) | |
2190 | { | |
2191 | struct xhci_ring *ep_ring; | |
2192 | struct urb_priv *urb_priv; | |
2193 | struct usb_iso_packet_descriptor *frame; | |
2194 | int idx; | |
2195 | ||
f6975314 | 2196 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
926008c9 | 2197 | urb_priv = td->urb->hcpriv; |
9ef7fbbb | 2198 | idx = urb_priv->num_tds_done; |
926008c9 DT |
2199 | frame = &td->urb->iso_frame_desc[idx]; |
2200 | ||
b3df3f9c | 2201 | /* The transfer is partly done. */ |
926008c9 DT |
2202 | frame->status = -EXDEV; |
2203 | ||
2204 | /* calc actual length */ | |
2205 | frame->actual_length = 0; | |
2206 | ||
2207 | /* Update ring dequeue pointer */ | |
2208 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
2209 | inc_deq(xhci, ep_ring); |
2210 | inc_deq(xhci, ep_ring); | |
926008c9 DT |
2211 | |
2212 | return finish_td(xhci, td, NULL, event, ep, status, true); | |
2213 | } | |
2214 | ||
22405ed2 AX |
2215 | /* |
2216 | * Process bulk and interrupt tds, update urb status and actual_length. | |
2217 | */ | |
2218 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 2219 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
22405ed2 AX |
2220 | struct xhci_virt_ep *ep, int *status) |
2221 | { | |
2222 | struct xhci_ring *ep_ring; | |
22405ed2 | 2223 | u32 trb_comp_code; |
f97c08ae | 2224 | u32 remaining, requested, ep_trb_len; |
22405ed2 | 2225 | |
28ccd296 ME |
2226 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2227 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
30a65b45 | 2228 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
f97c08ae | 2229 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); |
30a65b45 | 2230 | requested = td->urb->transfer_buffer_length; |
22405ed2 AX |
2231 | |
2232 | switch (trb_comp_code) { | |
2233 | case COMP_SUCCESS: | |
30a65b45 | 2234 | /* handle success with untransferred data as short packet */ |
f97c08ae | 2235 | if (ep_trb != td->last_trb || remaining) { |
52ab8685 | 2236 | xhci_warn(xhci, "WARN Successful completion on short TX\n"); |
30a65b45 MN |
2237 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2238 | td->urb->ep->desc.bEndpointAddress, | |
2239 | requested, remaining); | |
22405ed2 | 2240 | } |
52ab8685 | 2241 | *status = 0; |
22405ed2 | 2242 | break; |
0b7c105a | 2243 | case COMP_SHORT_PACKET: |
30a65b45 MN |
2244 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2245 | td->urb->ep->desc.bEndpointAddress, | |
2246 | requested, remaining); | |
52ab8685 | 2247 | *status = 0; |
22405ed2 | 2248 | break; |
0b7c105a | 2249 | case COMP_STOPPED_SHORT_PACKET: |
30a65b45 MN |
2250 | td->urb->actual_length = remaining; |
2251 | goto finish_td; | |
0b7c105a | 2252 | case COMP_STOPPED_LENGTH_INVALID: |
30a65b45 | 2253 | /* stopped on ep trb with invalid length, exclude it */ |
f97c08ae | 2254 | ep_trb_len = 0; |
30a65b45 MN |
2255 | remaining = 0; |
2256 | break; | |
22405ed2 | 2257 | default: |
30a65b45 | 2258 | /* do nothing */ |
22405ed2 AX |
2259 | break; |
2260 | } | |
40a3b775 | 2261 | |
f97c08ae | 2262 | if (ep_trb == td->last_trb) |
30a65b45 MN |
2263 | td->urb->actual_length = requested - remaining; |
2264 | else | |
2265 | td->urb->actual_length = | |
f97c08ae MN |
2266 | sum_trb_lengths(xhci, ep_ring, ep_trb) + |
2267 | ep_trb_len - remaining; | |
30a65b45 MN |
2268 | finish_td: |
2269 | if (remaining > requested) { | |
2270 | xhci_warn(xhci, "bad transfer trb length %d in event trb\n", | |
2271 | remaining); | |
22405ed2 | 2272 | td->urb->actual_length = 0; |
22405ed2 | 2273 | } |
f97c08ae | 2274 | return finish_td(xhci, td, ep_trb, event, ep, status, false); |
22405ed2 AX |
2275 | } |
2276 | ||
d0e96f5a SS |
2277 | /* |
2278 | * If this function returns an error condition, it means it got a Transfer | |
2279 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2280 | * At this point, the host controller is probably hosed and should be reset. | |
2281 | */ | |
2282 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2283 | struct xhci_transfer_event *event) | |
2284 | { | |
2285 | struct xhci_virt_device *xdev; | |
63a0d9ab | 2286 | struct xhci_virt_ep *ep; |
d0e96f5a | 2287 | struct xhci_ring *ep_ring; |
82d1009f | 2288 | unsigned int slot_id; |
d0e96f5a | 2289 | int ep_index; |
326b4810 | 2290 | struct xhci_td *td = NULL; |
f97c08ae MN |
2291 | dma_addr_t ep_trb_dma; |
2292 | struct xhci_segment *ep_seg; | |
2293 | union xhci_trb *ep_trb; | |
d0e96f5a | 2294 | int status = -EINPROGRESS; |
d115b048 | 2295 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2296 | struct list_head *tmp; |
66d1eebc | 2297 | u32 trb_comp_code; |
c2d7b49f | 2298 | int td_num = 0; |
3b4739b8 | 2299 | bool handling_skipped_tds = false; |
d0e96f5a | 2300 | |
28ccd296 | 2301 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
b3368382 MN |
2302 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
2303 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
2304 | ep_trb_dma = le64_to_cpu(event->buffer); | |
2305 | ||
82d1009f | 2306 | xdev = xhci->devs[slot_id]; |
d0e96f5a | 2307 | if (!xdev) { |
b7f769ae ZX |
2308 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n", |
2309 | slot_id); | |
b3368382 MN |
2310 | goto err_out; |
2311 | } | |
2312 | ||
63a0d9ab | 2313 | ep = &xdev->eps[ep_index]; |
b3368382 | 2314 | ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma); |
d115b048 | 2315 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
b3368382 | 2316 | |
ade2e3a1 | 2317 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) { |
b7f769ae | 2318 | xhci_err(xhci, |
ade2e3a1 | 2319 | "ERROR Transfer event for disabled endpoint slot %u ep %u\n", |
b7f769ae | 2320 | slot_id, ep_index); |
b3368382 | 2321 | goto err_out; |
d0e96f5a SS |
2322 | } |
2323 | ||
ade2e3a1 MN |
2324 | /* Some transfer events don't always point to a trb, see xhci 4.17.4 */ |
2325 | if (!ep_ring) { | |
2326 | switch (trb_comp_code) { | |
2327 | case COMP_STALL_ERROR: | |
2328 | case COMP_USB_TRANSACTION_ERROR: | |
2329 | case COMP_INVALID_STREAM_TYPE_ERROR: | |
2330 | case COMP_INVALID_STREAM_ID_ERROR: | |
2331 | xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0, | |
2332 | NULL, NULL, EP_SOFT_RESET); | |
2333 | goto cleanup; | |
2334 | case COMP_RING_UNDERRUN: | |
2335 | case COMP_RING_OVERRUN: | |
2336 | goto cleanup; | |
2337 | default: | |
2338 | xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n", | |
2339 | slot_id, ep_index); | |
2340 | goto err_out; | |
2341 | } | |
2342 | } | |
2343 | ||
c2d7b49f AX |
2344 | /* Count current td numbers if ep->skip is set */ |
2345 | if (ep->skip) { | |
2346 | list_for_each(tmp, &ep_ring->td_list) | |
2347 | td_num++; | |
2348 | } | |
2349 | ||
986a92d4 | 2350 | /* Look for common error cases */ |
66d1eebc | 2351 | switch (trb_comp_code) { |
b10de142 SS |
2352 | /* Skip codes that require special handling depending on |
2353 | * transfer type | |
2354 | */ | |
2355 | case COMP_SUCCESS: | |
1c11a172 | 2356 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
1530bbc6 SS |
2357 | break; |
2358 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
0b7c105a | 2359 | trb_comp_code = COMP_SHORT_PACKET; |
1530bbc6 | 2360 | else |
8202ce2e | 2361 | xhci_warn_ratelimited(xhci, |
b7f769ae ZX |
2362 | "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n", |
2363 | slot_id, ep_index); | |
0b7c105a | 2364 | case COMP_SHORT_PACKET: |
b10de142 | 2365 | break; |
b3368382 | 2366 | /* Completion codes for endpoint stopped state */ |
0b7c105a | 2367 | case COMP_STOPPED: |
b7f769ae ZX |
2368 | xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n", |
2369 | slot_id, ep_index); | |
ae636747 | 2370 | break; |
0b7c105a | 2371 | case COMP_STOPPED_LENGTH_INVALID: |
b7f769ae ZX |
2372 | xhci_dbg(xhci, |
2373 | "Stopped on No-op or Link TRB for slot %u ep %u\n", | |
2374 | slot_id, ep_index); | |
ae636747 | 2375 | break; |
0b7c105a | 2376 | case COMP_STOPPED_SHORT_PACKET: |
b7f769ae ZX |
2377 | xhci_dbg(xhci, |
2378 | "Stopped with short packet transfer detected for slot %u ep %u\n", | |
2379 | slot_id, ep_index); | |
40a3b775 | 2380 | break; |
b3368382 | 2381 | /* Completion codes for endpoint halted state */ |
0b7c105a | 2382 | case COMP_STALL_ERROR: |
b7f769ae ZX |
2383 | xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id, |
2384 | ep_index); | |
63a0d9ab | 2385 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
2386 | status = -EPIPE; |
2387 | break; | |
0b7c105a FB |
2388 | case COMP_SPLIT_TRANSACTION_ERROR: |
2389 | case COMP_USB_TRANSACTION_ERROR: | |
b7f769ae ZX |
2390 | xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n", |
2391 | slot_id, ep_index); | |
b10de142 SS |
2392 | status = -EPROTO; |
2393 | break; | |
0b7c105a | 2394 | case COMP_BABBLE_DETECTED_ERROR: |
b7f769ae ZX |
2395 | xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n", |
2396 | slot_id, ep_index); | |
4a73143c SS |
2397 | status = -EOVERFLOW; |
2398 | break; | |
b3368382 MN |
2399 | /* Completion codes for endpoint error state */ |
2400 | case COMP_TRB_ERROR: | |
2401 | xhci_warn(xhci, | |
2402 | "WARN: TRB error for slot %u ep %u on endpoint\n", | |
2403 | slot_id, ep_index); | |
2404 | status = -EILSEQ; | |
2405 | break; | |
2406 | /* completion codes not indicating endpoint state change */ | |
0b7c105a | 2407 | case COMP_DATA_BUFFER_ERROR: |
b7f769ae ZX |
2408 | xhci_warn(xhci, |
2409 | "WARN: HC couldn't access mem fast enough for slot %u ep %u\n", | |
2410 | slot_id, ep_index); | |
b10de142 SS |
2411 | status = -ENOSR; |
2412 | break; | |
0b7c105a | 2413 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
b7f769ae ZX |
2414 | xhci_warn(xhci, |
2415 | "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n", | |
2416 | slot_id, ep_index); | |
986a92d4 | 2417 | break; |
0b7c105a | 2418 | case COMP_ISOCH_BUFFER_OVERRUN: |
b7f769ae ZX |
2419 | xhci_warn(xhci, |
2420 | "WARN: buffer overrun event for slot %u ep %u on endpoint", | |
2421 | slot_id, ep_index); | |
986a92d4 | 2422 | break; |
0b7c105a | 2423 | case COMP_RING_UNDERRUN: |
986a92d4 AX |
2424 | /* |
2425 | * When the Isoch ring is empty, the xHC will generate | |
2426 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2427 | * Underrun Event for OUT Isoch endpoint. | |
2428 | */ | |
2429 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2430 | if (!list_empty(&ep_ring->td_list)) | |
2431 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2432 | "still with TDs queued?\n", | |
28ccd296 ME |
2433 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2434 | ep_index); | |
986a92d4 | 2435 | goto cleanup; |
0b7c105a | 2436 | case COMP_RING_OVERRUN: |
986a92d4 AX |
2437 | xhci_dbg(xhci, "overrun event on endpoint\n"); |
2438 | if (!list_empty(&ep_ring->td_list)) | |
2439 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2440 | "still with TDs queued?\n", | |
28ccd296 ME |
2441 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2442 | ep_index); | |
986a92d4 | 2443 | goto cleanup; |
0b7c105a | 2444 | case COMP_MISSED_SERVICE_ERROR: |
d18240db AX |
2445 | /* |
2446 | * When encounter missed service error, one or more isoc tds | |
2447 | * may be missed by xHC. | |
2448 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2449 | * short transfer when process the ep_ring next time. | |
2450 | */ | |
2451 | ep->skip = true; | |
b7f769ae ZX |
2452 | xhci_dbg(xhci, |
2453 | "Miss service interval error for slot %u ep %u, set skip flag\n", | |
2454 | slot_id, ep_index); | |
d18240db | 2455 | goto cleanup; |
0b7c105a | 2456 | case COMP_NO_PING_RESPONSE_ERROR: |
3b4739b8 | 2457 | ep->skip = true; |
b7f769ae ZX |
2458 | xhci_dbg(xhci, |
2459 | "No Ping response error for slot %u ep %u, Skip one Isoc TD\n", | |
2460 | slot_id, ep_index); | |
3b4739b8 | 2461 | goto cleanup; |
b3368382 MN |
2462 | |
2463 | case COMP_INCOMPATIBLE_DEVICE_ERROR: | |
2464 | /* needs disable slot command to recover */ | |
2465 | xhci_warn(xhci, | |
2466 | "WARN: detect an incompatible device for slot %u ep %u", | |
2467 | slot_id, ep_index); | |
2468 | status = -EPROTO; | |
2469 | break; | |
b10de142 | 2470 | default: |
b45b5069 | 2471 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2472 | status = 0; |
2473 | break; | |
2474 | } | |
b7f769ae ZX |
2475 | xhci_warn(xhci, |
2476 | "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n", | |
2477 | trb_comp_code, slot_id, ep_index); | |
986a92d4 AX |
2478 | goto cleanup; |
2479 | } | |
2480 | ||
d18240db AX |
2481 | do { |
2482 | /* This TRB should be in the TD at the head of this ring's | |
2483 | * TD list. | |
2484 | */ | |
2485 | if (list_empty(&ep_ring->td_list)) { | |
a83d6755 SS |
2486 | /* |
2487 | * A stopped endpoint may generate an extra completion | |
2488 | * event if the device was suspended. Don't print | |
2489 | * warnings. | |
2490 | */ | |
0b7c105a FB |
2491 | if (!(trb_comp_code == COMP_STOPPED || |
2492 | trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { | |
a83d6755 SS |
2493 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", |
2494 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), | |
2495 | ep_index); | |
a83d6755 | 2496 | } |
d18240db AX |
2497 | if (ep->skip) { |
2498 | ep->skip = false; | |
b7f769ae ZX |
2499 | xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n", |
2500 | slot_id, ep_index); | |
d18240db | 2501 | } |
d18240db AX |
2502 | goto cleanup; |
2503 | } | |
986a92d4 | 2504 | |
c2d7b49f AX |
2505 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2506 | if (ep->skip && td_num == 0) { | |
2507 | ep->skip = false; | |
b7f769ae ZX |
2508 | xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n", |
2509 | slot_id, ep_index); | |
c2d7b49f AX |
2510 | goto cleanup; |
2511 | } | |
2512 | ||
04861f83 FB |
2513 | td = list_first_entry(&ep_ring->td_list, struct xhci_td, |
2514 | td_list); | |
c2d7b49f AX |
2515 | if (ep->skip) |
2516 | td_num--; | |
926008c9 | 2517 | |
d18240db | 2518 | /* Is this a TRB in the currently executing TD? */ |
f97c08ae MN |
2519 | ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, |
2520 | td->last_trb, ep_trb_dma, false); | |
e1cf486d AH |
2521 | |
2522 | /* | |
2523 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2524 | * is not in the current TD pointed by ep_ring->dequeue because | |
2525 | * that the hardware dequeue pointer still at the previous TRB | |
2526 | * of the current TD. The previous TRB maybe a Link TD or the | |
2527 | * last TRB of the previous TD. The command completion handle | |
2528 | * will take care the rest. | |
2529 | */ | |
0b7c105a FB |
2530 | if (!ep_seg && (trb_comp_code == COMP_STOPPED || |
2531 | trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { | |
e1cf486d AH |
2532 | goto cleanup; |
2533 | } | |
2534 | ||
f97c08ae | 2535 | if (!ep_seg) { |
926008c9 DT |
2536 | if (!ep->skip || |
2537 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2538 | /* Some host controllers give a spurious |
2539 | * successful event after a short transfer. | |
2540 | * Ignore it. | |
2541 | */ | |
ddba5cd0 | 2542 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
ad808333 SS |
2543 | ep_ring->last_td_was_short) { |
2544 | ep_ring->last_td_was_short = false; | |
ad808333 SS |
2545 | goto cleanup; |
2546 | } | |
926008c9 DT |
2547 | /* HC is busted, give up! */ |
2548 | xhci_err(xhci, | |
2549 | "ERROR Transfer event TRB DMA ptr not " | |
cffb9be8 HG |
2550 | "part of current TD ep_index %d " |
2551 | "comp_code %u\n", ep_index, | |
2552 | trb_comp_code); | |
2553 | trb_in_td(xhci, ep_ring->deq_seg, | |
2554 | ep_ring->dequeue, td->last_trb, | |
f97c08ae | 2555 | ep_trb_dma, true); |
926008c9 DT |
2556 | return -ESHUTDOWN; |
2557 | } | |
2558 | ||
0c03d89d | 2559 | skip_isoc_td(xhci, td, event, ep, &status); |
926008c9 DT |
2560 | goto cleanup; |
2561 | } | |
0b7c105a | 2562 | if (trb_comp_code == COMP_SHORT_PACKET) |
ad808333 SS |
2563 | ep_ring->last_td_was_short = true; |
2564 | else | |
2565 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2566 | |
2567 | if (ep->skip) { | |
b7f769ae ZX |
2568 | xhci_dbg(xhci, |
2569 | "Found td. Clear skip flag for slot %u ep %u.\n", | |
2570 | slot_id, ep_index); | |
d18240db AX |
2571 | ep->skip = false; |
2572 | } | |
678539cf | 2573 | |
f97c08ae MN |
2574 | ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / |
2575 | sizeof(*ep_trb)]; | |
a37c3f76 FB |
2576 | |
2577 | trace_xhci_handle_transfer(ep_ring, | |
2578 | (struct xhci_generic_trb *) ep_trb); | |
2579 | ||
926008c9 DT |
2580 | /* |
2581 | * No-op TRB should not trigger interrupts. | |
f97c08ae | 2582 | * If ep_trb is a no-op TRB, it means the |
926008c9 DT |
2583 | * corresponding TD has been cancelled. Just ignore |
2584 | * the TD. | |
2585 | */ | |
f97c08ae | 2586 | if (trb_is_noop(ep_trb)) { |
b7f769ae ZX |
2587 | xhci_dbg(xhci, |
2588 | "ep_trb is a no-op TRB. Skip it for slot %u ep %u\n", | |
2589 | slot_id, ep_index); | |
926008c9 | 2590 | goto cleanup; |
d18240db | 2591 | } |
4422da61 | 2592 | |
0c03d89d | 2593 | /* update the urb's actual_length and give back to the core */ |
d18240db | 2594 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
0c03d89d | 2595 | process_ctrl_td(xhci, td, ep_trb, event, ep, &status); |
04e51901 | 2596 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
0c03d89d | 2597 | process_isoc_td(xhci, td, ep_trb, event, ep, &status); |
d18240db | 2598 | else |
0c03d89d MN |
2599 | process_bulk_intr_td(xhci, td, ep_trb, event, ep, |
2600 | &status); | |
d18240db | 2601 | cleanup: |
3b4739b8 | 2602 | handling_skipped_tds = ep->skip && |
0b7c105a FB |
2603 | trb_comp_code != COMP_MISSED_SERVICE_ERROR && |
2604 | trb_comp_code != COMP_NO_PING_RESPONSE_ERROR; | |
3b4739b8 | 2605 | |
d18240db | 2606 | /* |
3b4739b8 MN |
2607 | * Do not update event ring dequeue pointer if we're in a loop |
2608 | * processing missed tds. | |
d18240db | 2609 | */ |
3b4739b8 | 2610 | if (!handling_skipped_tds) |
3b72fca0 | 2611 | inc_deq(xhci, xhci->event_ring); |
d18240db | 2612 | |
d18240db AX |
2613 | /* |
2614 | * If ep->skip is set, it means there are missed tds on the | |
2615 | * endpoint ring need to take care of. | |
2616 | * Process them as short transfer until reach the td pointed by | |
2617 | * the event. | |
2618 | */ | |
3b4739b8 | 2619 | } while (handling_skipped_tds); |
d18240db | 2620 | |
d0e96f5a | 2621 | return 0; |
b3368382 MN |
2622 | |
2623 | err_out: | |
2624 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", | |
2625 | (unsigned long long) xhci_trb_virt_to_dma( | |
2626 | xhci->event_ring->deq_seg, | |
2627 | xhci->event_ring->dequeue), | |
2628 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2629 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2630 | le32_to_cpu(event->transfer_len), | |
2631 | le32_to_cpu(event->flags)); | |
2632 | return -ENODEV; | |
d0e96f5a SS |
2633 | } |
2634 | ||
0f2a7930 SS |
2635 | /* |
2636 | * This function handles all OS-owned events on the event ring. It may drop | |
2637 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2638 | * Returns >0 for "possibly more events to process" (caller should call again), |
2639 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2640 | */ |
9dee9a21 | 2641 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2642 | { |
2643 | union xhci_trb *event; | |
0f2a7930 | 2644 | int update_ptrs = 1; |
d0e96f5a | 2645 | int ret; |
7f84eef0 | 2646 | |
f4c8f03c | 2647 | /* Event ring hasn't been allocated yet. */ |
7f84eef0 | 2648 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
f4c8f03c LB |
2649 | xhci_err(xhci, "ERROR event ring not ready\n"); |
2650 | return -ENOMEM; | |
7f84eef0 SS |
2651 | } |
2652 | ||
2653 | event = xhci->event_ring->dequeue; | |
2654 | /* Does the HC or OS own the TRB? */ | |
28ccd296 | 2655 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
f4c8f03c | 2656 | xhci->event_ring->cycle_state) |
9dee9a21 | 2657 | return 0; |
7f84eef0 | 2658 | |
a37c3f76 FB |
2659 | trace_xhci_handle_event(xhci->event_ring, &event->generic); |
2660 | ||
92a3da41 ME |
2661 | /* |
2662 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2663 | * speculative reads of the event's flags/data below. | |
2664 | */ | |
2665 | rmb(); | |
0f2a7930 | 2666 | /* FIXME: Handle more event types. */ |
f4c8f03c | 2667 | switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) { |
7f84eef0 SS |
2668 | case TRB_TYPE(TRB_COMPLETION): |
2669 | handle_cmd_completion(xhci, &event->event_cmd); | |
2670 | break; | |
0f2a7930 SS |
2671 | case TRB_TYPE(TRB_PORT_STATUS): |
2672 | handle_port_status(xhci, event); | |
2673 | update_ptrs = 0; | |
2674 | break; | |
d0e96f5a SS |
2675 | case TRB_TYPE(TRB_TRANSFER): |
2676 | ret = handle_tx_event(xhci, &event->trans_event); | |
f4c8f03c | 2677 | if (ret >= 0) |
d0e96f5a SS |
2678 | update_ptrs = 0; |
2679 | break; | |
623bef9e SS |
2680 | case TRB_TYPE(TRB_DEV_NOTE): |
2681 | handle_device_notification(xhci, event); | |
2682 | break; | |
7f84eef0 | 2683 | default: |
28ccd296 ME |
2684 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2685 | TRB_TYPE(48)) | |
0238634d SS |
2686 | handle_vendor_event(xhci, event); |
2687 | else | |
f4c8f03c LB |
2688 | xhci_warn(xhci, "ERROR unknown event type %d\n", |
2689 | TRB_FIELD_TO_TYPE( | |
2690 | le32_to_cpu(event->event_cmd.flags))); | |
7f84eef0 | 2691 | } |
6f5165cf SS |
2692 | /* Any of the above functions may drop and re-acquire the lock, so check |
2693 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2694 | */ | |
2695 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2696 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2697 | "event handler.\n"); | |
9dee9a21 | 2698 | return 0; |
6f5165cf | 2699 | } |
7f84eef0 | 2700 | |
c06d68b8 SS |
2701 | if (update_ptrs) |
2702 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 2703 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 2704 | |
9dee9a21 ME |
2705 | /* Are there more items on the event ring? Caller will call us again to |
2706 | * check. | |
2707 | */ | |
2708 | return 1; | |
7f84eef0 | 2709 | } |
9032cd52 SS |
2710 | |
2711 | /* | |
2712 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2713 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2714 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2715 | */ | |
2716 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2717 | { | |
2718 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c06d68b8 | 2719 | union xhci_trb *event_ring_deq; |
76a35293 | 2720 | irqreturn_t ret = IRQ_NONE; |
63aea0db | 2721 | unsigned long flags; |
c06d68b8 | 2722 | dma_addr_t deq; |
76a35293 FB |
2723 | u64 temp_64; |
2724 | u32 status; | |
9032cd52 | 2725 | |
63aea0db | 2726 | spin_lock_irqsave(&xhci->lock, flags); |
9032cd52 | 2727 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
b0ba9720 | 2728 | status = readl(&xhci->op_regs->status); |
d9f11ba9 MN |
2729 | if (status == ~(u32)0) { |
2730 | xhci_hc_died(xhci); | |
76a35293 FB |
2731 | ret = IRQ_HANDLED; |
2732 | goto out; | |
9032cd52 | 2733 | } |
76a35293 FB |
2734 | |
2735 | if (!(status & STS_EINT)) | |
2736 | goto out; | |
2737 | ||
27e0dd4d | 2738 | if (status & STS_FATAL) { |
9032cd52 SS |
2739 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2740 | xhci_halt(xhci); | |
76a35293 FB |
2741 | ret = IRQ_HANDLED; |
2742 | goto out; | |
9032cd52 SS |
2743 | } |
2744 | ||
bda53145 SS |
2745 | /* |
2746 | * Clear the op reg interrupt status first, | |
2747 | * so we can receive interrupts from other MSI-X interrupters. | |
2748 | * Write 1 to clear the interrupt status. | |
2749 | */ | |
27e0dd4d | 2750 | status |= STS_EINT; |
204b7793 | 2751 | writel(status, &xhci->op_regs->status); |
bda53145 | 2752 | |
6a29beef | 2753 | if (!hcd->msi_enabled) { |
c21599a3 | 2754 | u32 irq_pending; |
b0ba9720 | 2755 | irq_pending = readl(&xhci->ir_set->irq_pending); |
4e833c0b | 2756 | irq_pending |= IMAN_IP; |
204b7793 | 2757 | writel(irq_pending, &xhci->ir_set->irq_pending); |
c21599a3 | 2758 | } |
bda53145 | 2759 | |
27a41a83 GKB |
2760 | if (xhci->xhc_state & XHCI_STATE_DYING || |
2761 | xhci->xhc_state & XHCI_STATE_HALTED) { | |
bda53145 SS |
2762 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2763 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2764 | /* Clear the event handler busy flag (RW1C); |
2765 | * the event ring should be empty. | |
bda53145 | 2766 | */ |
f7b2e403 | 2767 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
477632df SS |
2768 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
2769 | &xhci->ir_set->erst_dequeue); | |
76a35293 FB |
2770 | ret = IRQ_HANDLED; |
2771 | goto out; | |
c06d68b8 SS |
2772 | } |
2773 | ||
2774 | event_ring_deq = xhci->event_ring->dequeue; | |
2775 | /* FIXME this should be a delayed service routine | |
2776 | * that clears the EHB. | |
2777 | */ | |
9dee9a21 | 2778 | while (xhci_handle_event(xhci) > 0) {} |
bda53145 | 2779 | |
f7b2e403 | 2780 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2781 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2782 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2783 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2784 | xhci->event_ring->dequeue); | |
2785 | if (deq == 0) | |
2786 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2787 | "ring dequeue ptr.\n"); | |
2788 | /* Update HC event ring dequeue pointer */ | |
2789 | temp_64 &= ERST_PTR_MASK; | |
2790 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2791 | } | |
2792 | ||
2793 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2794 | temp_64 |= ERST_EHB; | |
477632df | 2795 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
76a35293 | 2796 | ret = IRQ_HANDLED; |
c06d68b8 | 2797 | |
76a35293 | 2798 | out: |
63aea0db | 2799 | spin_unlock_irqrestore(&xhci->lock, flags); |
9032cd52 | 2800 | |
76a35293 | 2801 | return ret; |
9032cd52 SS |
2802 | } |
2803 | ||
851ec164 | 2804 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
9032cd52 | 2805 | { |
968b822c | 2806 | return xhci_irq(hcd); |
9032cd52 | 2807 | } |
7f84eef0 | 2808 | |
d0e96f5a SS |
2809 | /**** Endpoint Ring Operations ****/ |
2810 | ||
7f84eef0 SS |
2811 | /* |
2812 | * Generic function for queueing a TRB on a ring. | |
2813 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2814 | * |
2815 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2816 | * prepare_transfer()? | |
7f84eef0 SS |
2817 | */ |
2818 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 2819 | bool more_trbs_coming, |
7f84eef0 SS |
2820 | u32 field1, u32 field2, u32 field3, u32 field4) |
2821 | { | |
2822 | struct xhci_generic_trb *trb; | |
2823 | ||
2824 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
2825 | trb->field[0] = cpu_to_le32(field1); |
2826 | trb->field[1] = cpu_to_le32(field2); | |
2827 | trb->field[2] = cpu_to_le32(field3); | |
2828 | trb->field[3] = cpu_to_le32(field4); | |
a37c3f76 FB |
2829 | |
2830 | trace_xhci_queue_trb(ring, trb); | |
2831 | ||
3b72fca0 | 2832 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
2833 | } |
2834 | ||
d0e96f5a SS |
2835 | /* |
2836 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2837 | * FIXME allocate segments if the ring is full. | |
2838 | */ | |
2839 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 2840 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 2841 | { |
8dfec614 AX |
2842 | unsigned int num_trbs_needed; |
2843 | ||
d0e96f5a | 2844 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
2845 | switch (ep_state) { |
2846 | case EP_STATE_DISABLED: | |
2847 | /* | |
2848 | * USB core changed config/interfaces without notifying us, | |
2849 | * or hardware is reporting the wrong state. | |
2850 | */ | |
2851 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2852 | return -ENOENT; | |
d0e96f5a | 2853 | case EP_STATE_ERROR: |
c92bcfa7 | 2854 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
2855 | /* FIXME event handling code for error needs to clear it */ |
2856 | /* XXX not sure if this should be -ENOENT or not */ | |
2857 | return -EINVAL; | |
c92bcfa7 SS |
2858 | case EP_STATE_HALTED: |
2859 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
2860 | case EP_STATE_STOPPED: |
2861 | case EP_STATE_RUNNING: | |
2862 | break; | |
2863 | default: | |
2864 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
2865 | /* | |
2866 | * FIXME issue Configure Endpoint command to try to get the HC | |
2867 | * back into a known state. | |
2868 | */ | |
2869 | return -EINVAL; | |
2870 | } | |
8dfec614 AX |
2871 | |
2872 | while (1) { | |
3d4b81ed SS |
2873 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
2874 | break; | |
8dfec614 AX |
2875 | |
2876 | if (ep_ring == xhci->cmd_ring) { | |
2877 | xhci_err(xhci, "Do not support expand command ring\n"); | |
2878 | return -ENOMEM; | |
2879 | } | |
2880 | ||
68ffb011 XR |
2881 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
2882 | "ERROR no room on ep ring, try ring expansion"); | |
8dfec614 AX |
2883 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
2884 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
2885 | mem_flags)) { | |
2886 | xhci_err(xhci, "Ring expansion failed\n"); | |
2887 | return -ENOMEM; | |
2888 | } | |
261fa12b | 2889 | } |
6c12db90 | 2890 | |
d0c77d84 MN |
2891 | while (trb_is_link(ep_ring->enqueue)) { |
2892 | /* If we're not dealing with 0.95 hardware or isoc rings | |
2893 | * on AMD 0.96 host, clear the chain bit. | |
2894 | */ | |
2895 | if (!xhci_link_trb_quirk(xhci) && | |
2896 | !(ep_ring->type == TYPE_ISOC && | |
2897 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
2898 | ep_ring->enqueue->link.control &= | |
2899 | cpu_to_le32(~TRB_CHAIN); | |
2900 | else | |
2901 | ep_ring->enqueue->link.control |= | |
2902 | cpu_to_le32(TRB_CHAIN); | |
6c12db90 | 2903 | |
d0c77d84 MN |
2904 | wmb(); |
2905 | ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); | |
6c12db90 | 2906 | |
d0c77d84 MN |
2907 | /* Toggle the cycle bit after the last ring segment. */ |
2908 | if (link_trb_toggles_cycle(ep_ring->enqueue)) | |
2909 | ep_ring->cycle_state ^= 1; | |
6c12db90 | 2910 | |
d0c77d84 MN |
2911 | ep_ring->enq_seg = ep_ring->enq_seg->next; |
2912 | ep_ring->enqueue = ep_ring->enq_seg->trbs; | |
6c12db90 | 2913 | } |
d0e96f5a SS |
2914 | return 0; |
2915 | } | |
2916 | ||
23e3be11 | 2917 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
2918 | struct xhci_virt_device *xdev, |
2919 | unsigned int ep_index, | |
e9df17eb | 2920 | unsigned int stream_id, |
d0e96f5a SS |
2921 | unsigned int num_trbs, |
2922 | struct urb *urb, | |
8e51adcc | 2923 | unsigned int td_index, |
d0e96f5a SS |
2924 | gfp_t mem_flags) |
2925 | { | |
2926 | int ret; | |
8e51adcc AX |
2927 | struct urb_priv *urb_priv; |
2928 | struct xhci_td *td; | |
e9df17eb | 2929 | struct xhci_ring *ep_ring; |
d115b048 | 2930 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
2931 | |
2932 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
2933 | if (!ep_ring) { | |
2934 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
2935 | stream_id); | |
2936 | return -EINVAL; | |
2937 | } | |
2938 | ||
5071e6b2 | 2939 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 2940 | num_trbs, mem_flags); |
d0e96f5a SS |
2941 | if (ret) |
2942 | return ret; | |
d0e96f5a | 2943 | |
8e51adcc | 2944 | urb_priv = urb->hcpriv; |
7e64b037 | 2945 | td = &urb_priv->td[td_index]; |
8e51adcc AX |
2946 | |
2947 | INIT_LIST_HEAD(&td->td_list); | |
2948 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
2949 | ||
2950 | if (td_index == 0) { | |
214f76f7 | 2951 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 2952 | if (unlikely(ret)) |
8e51adcc | 2953 | return ret; |
d0e96f5a SS |
2954 | } |
2955 | ||
8e51adcc | 2956 | td->urb = urb; |
d0e96f5a | 2957 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
2958 | list_add_tail(&td->td_list, &ep_ring->td_list); |
2959 | td->start_seg = ep_ring->enq_seg; | |
2960 | td->first_trb = ep_ring->enqueue; | |
2961 | ||
d0e96f5a SS |
2962 | return 0; |
2963 | } | |
2964 | ||
d2510342 AI |
2965 | static unsigned int count_trbs(u64 addr, u64 len) |
2966 | { | |
2967 | unsigned int num_trbs; | |
2968 | ||
2969 | num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), | |
2970 | TRB_MAX_BUFF_SIZE); | |
2971 | if (num_trbs == 0) | |
2972 | num_trbs++; | |
2973 | ||
2974 | return num_trbs; | |
2975 | } | |
2976 | ||
2977 | static inline unsigned int count_trbs_needed(struct urb *urb) | |
2978 | { | |
2979 | return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); | |
2980 | } | |
2981 | ||
2982 | static unsigned int count_sg_trbs_needed(struct urb *urb) | |
8a96c052 | 2983 | { |
8a96c052 | 2984 | struct scatterlist *sg; |
d2510342 | 2985 | unsigned int i, len, full_len, num_trbs = 0; |
8a96c052 | 2986 | |
d2510342 | 2987 | full_len = urb->transfer_buffer_length; |
8a96c052 | 2988 | |
d2510342 AI |
2989 | for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { |
2990 | len = sg_dma_len(sg); | |
2991 | num_trbs += count_trbs(sg_dma_address(sg), len); | |
2992 | len = min_t(unsigned int, len, full_len); | |
2993 | full_len -= len; | |
2994 | if (full_len == 0) | |
8a96c052 SS |
2995 | break; |
2996 | } | |
d2510342 | 2997 | |
8a96c052 SS |
2998 | return num_trbs; |
2999 | } | |
3000 | ||
d2510342 AI |
3001 | static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) |
3002 | { | |
3003 | u64 addr, len; | |
3004 | ||
3005 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
3006 | len = urb->iso_frame_desc[i].length; | |
3007 | ||
3008 | return count_trbs(addr, len); | |
3009 | } | |
3010 | ||
3011 | static void check_trb_math(struct urb *urb, int running_total) | |
8a96c052 | 3012 | { |
d2510342 | 3013 | if (unlikely(running_total != urb->transfer_buffer_length)) |
a2490187 | 3014 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
3015 | "queued %#x (%d), asked for %#x (%d)\n", |
3016 | __func__, | |
3017 | urb->ep->desc.bEndpointAddress, | |
3018 | running_total, running_total, | |
3019 | urb->transfer_buffer_length, | |
3020 | urb->transfer_buffer_length); | |
3021 | } | |
3022 | ||
23e3be11 | 3023 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 3024 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 3025 | struct xhci_generic_trb *start_trb) |
8a96c052 | 3026 | { |
8a96c052 SS |
3027 | /* |
3028 | * Pass all the TRBs to the hardware at once and make sure this write | |
3029 | * isn't reordered. | |
3030 | */ | |
3031 | wmb(); | |
50f7b52a | 3032 | if (start_cycle) |
28ccd296 | 3033 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 3034 | else |
28ccd296 | 3035 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 3036 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
3037 | } |
3038 | ||
78140156 AI |
3039 | static void check_interval(struct xhci_hcd *xhci, struct urb *urb, |
3040 | struct xhci_ep_ctx *ep_ctx) | |
624defa1 | 3041 | { |
624defa1 SS |
3042 | int xhci_interval; |
3043 | int ep_interval; | |
3044 | ||
28ccd296 | 3045 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 | 3046 | ep_interval = urb->interval; |
78140156 | 3047 | |
624defa1 SS |
3048 | /* Convert to microframes */ |
3049 | if (urb->dev->speed == USB_SPEED_LOW || | |
3050 | urb->dev->speed == USB_SPEED_FULL) | |
3051 | ep_interval *= 8; | |
78140156 | 3052 | |
624defa1 SS |
3053 | /* FIXME change this to a warning and a suggestion to use the new API |
3054 | * to set the polling interval (once the API is added). | |
3055 | */ | |
3056 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3057 | dev_dbg_ratelimited(&urb->dev->dev, |
3058 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3059 | ep_interval, ep_interval == 1 ? "" : "s", | |
3060 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
624defa1 SS |
3061 | urb->interval = xhci_interval; |
3062 | /* Convert back to frames for LS/FS devices */ | |
3063 | if (urb->dev->speed == USB_SPEED_LOW || | |
3064 | urb->dev->speed == USB_SPEED_FULL) | |
3065 | urb->interval /= 8; | |
3066 | } | |
78140156 AI |
3067 | } |
3068 | ||
3069 | /* | |
3070 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
3071 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
3072 | * (comprised of sg list entries) can take several service intervals to | |
3073 | * transmit. | |
3074 | */ | |
3075 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3076 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3077 | { | |
3078 | struct xhci_ep_ctx *ep_ctx; | |
3079 | ||
3080 | ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); | |
3081 | check_interval(xhci, urb, ep_ctx); | |
3082 | ||
3fc8206d | 3083 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
3084 | } |
3085 | ||
4da6e6f2 | 3086 | /* |
4525c0a1 SS |
3087 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
3088 | * packets remaining in the TD (*not* including this TRB). | |
4da6e6f2 SS |
3089 | * |
3090 | * Total TD packet count = total_packet_count = | |
4525c0a1 | 3091 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
4da6e6f2 SS |
3092 | * |
3093 | * Packets transferred up to and including this TRB = packets_transferred = | |
3094 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
3095 | * | |
3096 | * TD size = total_packet_count - packets_transferred | |
3097 | * | |
c840d6ce MN |
3098 | * For xHCI 0.96 and older, TD size field should be the remaining bytes |
3099 | * including this TRB, right shifted by 10 | |
3100 | * | |
3101 | * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. | |
3102 | * This is taken care of in the TRB_TD_SIZE() macro | |
3103 | * | |
4525c0a1 | 3104 | * The last TRB in a TD must have the TD size set to zero. |
4da6e6f2 | 3105 | */ |
c840d6ce MN |
3106 | static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, |
3107 | int trb_buff_len, unsigned int td_total_len, | |
124c3937 | 3108 | struct urb *urb, bool more_trbs_coming) |
4da6e6f2 | 3109 | { |
c840d6ce MN |
3110 | u32 maxp, total_packet_count; |
3111 | ||
0cbd4b34 CY |
3112 | /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */ |
3113 | if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) | |
c840d6ce MN |
3114 | return ((td_total_len - transferred) >> 10); |
3115 | ||
48df4a6f | 3116 | /* One TRB with a zero-length data packet. */ |
124c3937 | 3117 | if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || |
c840d6ce | 3118 | trb_buff_len == td_total_len) |
48df4a6f SS |
3119 | return 0; |
3120 | ||
0cbd4b34 CY |
3121 | /* for MTK xHCI, TD size doesn't include this TRB */ |
3122 | if (xhci->quirks & XHCI_MTK_HOST) | |
3123 | trb_buff_len = 0; | |
3124 | ||
734d3ddd | 3125 | maxp = usb_endpoint_maxp(&urb->ep->desc); |
0cbd4b34 CY |
3126 | total_packet_count = DIV_ROUND_UP(td_total_len, maxp); |
3127 | ||
c840d6ce MN |
3128 | /* Queueing functions don't count the current TRB into transferred */ |
3129 | return (total_packet_count - ((transferred + trb_buff_len) / maxp)); | |
4da6e6f2 SS |
3130 | } |
3131 | ||
f9c589e1 | 3132 | |
474ed23a | 3133 | static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, |
f9c589e1 | 3134 | u32 *trb_buff_len, struct xhci_segment *seg) |
474ed23a | 3135 | { |
f9c589e1 | 3136 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
474ed23a MN |
3137 | unsigned int unalign; |
3138 | unsigned int max_pkt; | |
f9c589e1 | 3139 | u32 new_buff_len; |
474ed23a | 3140 | |
734d3ddd | 3141 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
474ed23a MN |
3142 | unalign = (enqd_len + *trb_buff_len) % max_pkt; |
3143 | ||
3144 | /* we got lucky, last normal TRB data on segment is packet aligned */ | |
3145 | if (unalign == 0) | |
3146 | return 0; | |
3147 | ||
f9c589e1 MN |
3148 | xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", |
3149 | unalign, *trb_buff_len); | |
3150 | ||
474ed23a MN |
3151 | /* is the last nornal TRB alignable by splitting it */ |
3152 | if (*trb_buff_len > unalign) { | |
3153 | *trb_buff_len -= unalign; | |
f9c589e1 | 3154 | xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); |
474ed23a MN |
3155 | return 0; |
3156 | } | |
f9c589e1 MN |
3157 | |
3158 | /* | |
3159 | * We want enqd_len + trb_buff_len to sum up to a number aligned to | |
3160 | * number which is divisible by the endpoint's wMaxPacketSize. IOW: | |
3161 | * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. | |
3162 | */ | |
3163 | new_buff_len = max_pkt - (enqd_len % max_pkt); | |
3164 | ||
3165 | if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) | |
3166 | new_buff_len = (urb->transfer_buffer_length - enqd_len); | |
3167 | ||
3168 | /* create a max max_pkt sized bounce buffer pointed to by last trb */ | |
3169 | if (usb_urb_dir_out(urb)) { | |
3170 | sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs, | |
3171 | seg->bounce_buf, new_buff_len, enqd_len); | |
3172 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3173 | max_pkt, DMA_TO_DEVICE); | |
3174 | } else { | |
3175 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3176 | max_pkt, DMA_FROM_DEVICE); | |
3177 | } | |
3178 | ||
3179 | if (dma_mapping_error(dev, seg->bounce_dma)) { | |
3180 | /* try without aligning. Some host controllers survive */ | |
3181 | xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); | |
3182 | return 0; | |
3183 | } | |
3184 | *trb_buff_len = new_buff_len; | |
3185 | seg->bounce_len = new_buff_len; | |
3186 | seg->bounce_offs = enqd_len; | |
3187 | ||
3188 | xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); | |
3189 | ||
474ed23a MN |
3190 | return 1; |
3191 | } | |
3192 | ||
d2510342 AI |
3193 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
3194 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
8a96c052 SS |
3195 | struct urb *urb, int slot_id, unsigned int ep_index) |
3196 | { | |
5a5a0b1a | 3197 | struct xhci_ring *ring; |
8e51adcc | 3198 | struct urb_priv *urb_priv; |
8a96c052 | 3199 | struct xhci_td *td; |
d2510342 AI |
3200 | struct xhci_generic_trb *start_trb; |
3201 | struct scatterlist *sg = NULL; | |
5a83f04a MN |
3202 | bool more_trbs_coming = true; |
3203 | bool need_zero_pkt = false; | |
86065c27 MN |
3204 | bool first_trb = true; |
3205 | unsigned int num_trbs; | |
d2510342 | 3206 | unsigned int start_cycle, num_sgs = 0; |
86065c27 | 3207 | unsigned int enqd_len, block_len, trb_buff_len, full_len; |
f9c589e1 | 3208 | int sent_len, ret; |
d2510342 | 3209 | u32 field, length_field, remainder; |
f9c589e1 | 3210 | u64 addr, send_addr; |
8a96c052 | 3211 | |
5a5a0b1a MN |
3212 | ring = xhci_urb_to_transfer_ring(xhci, urb); |
3213 | if (!ring) | |
e9df17eb SS |
3214 | return -EINVAL; |
3215 | ||
86065c27 | 3216 | full_len = urb->transfer_buffer_length; |
d2510342 AI |
3217 | /* If we have scatter/gather list, we use it. */ |
3218 | if (urb->num_sgs) { | |
3219 | num_sgs = urb->num_mapped_sgs; | |
3220 | sg = urb->sg; | |
86065c27 MN |
3221 | addr = (u64) sg_dma_address(sg); |
3222 | block_len = sg_dma_len(sg); | |
d2510342 | 3223 | num_trbs = count_sg_trbs_needed(urb); |
86065c27 | 3224 | } else { |
d2510342 | 3225 | num_trbs = count_trbs_needed(urb); |
86065c27 MN |
3226 | addr = (u64) urb->transfer_dma; |
3227 | block_len = full_len; | |
3228 | } | |
4758dcd1 | 3229 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 3230 | ep_index, urb->stream_id, |
3b72fca0 | 3231 | num_trbs, urb, 0, mem_flags); |
d2510342 | 3232 | if (unlikely(ret < 0)) |
4758dcd1 | 3233 | return ret; |
8e51adcc AX |
3234 | |
3235 | urb_priv = urb->hcpriv; | |
4758dcd1 RA |
3236 | |
3237 | /* Deal with URB_ZERO_PACKET - need one more td/trb */ | |
9ef7fbbb | 3238 | if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1) |
5a83f04a | 3239 | need_zero_pkt = true; |
4758dcd1 | 3240 | |
7e64b037 | 3241 | td = &urb_priv->td[0]; |
8e51adcc | 3242 | |
8a96c052 SS |
3243 | /* |
3244 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3245 | * until we've finished creating all the other TRBs. The ring's cycle | |
3246 | * state may change as we enqueue the other TRBs, so save it too. | |
3247 | */ | |
5a5a0b1a MN |
3248 | start_trb = &ring->enqueue->generic; |
3249 | start_cycle = ring->cycle_state; | |
f9c589e1 | 3250 | send_addr = addr; |
8a96c052 | 3251 | |
d2510342 | 3252 | /* Queue the TRBs, even if they are zero-length */ |
0d2daade AB |
3253 | for (enqd_len = 0; first_trb || enqd_len < full_len; |
3254 | enqd_len += trb_buff_len) { | |
d2510342 | 3255 | field = TRB_TYPE(TRB_NORMAL); |
af8b9e63 | 3256 | |
86065c27 MN |
3257 | /* TRB buffer should not cross 64KB boundaries */ |
3258 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); | |
3259 | trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); | |
8a96c052 | 3260 | |
86065c27 MN |
3261 | if (enqd_len + trb_buff_len > full_len) |
3262 | trb_buff_len = full_len - enqd_len; | |
b10de142 SS |
3263 | |
3264 | /* Don't change the cycle bit of the first TRB until later */ | |
86065c27 MN |
3265 | if (first_trb) { |
3266 | first_trb = false; | |
50f7b52a | 3267 | if (start_cycle == 0) |
d2510342 | 3268 | field |= TRB_CYCLE; |
50f7b52a | 3269 | } else |
5a5a0b1a | 3270 | field |= ring->cycle_state; |
b10de142 SS |
3271 | |
3272 | /* Chain all the TRBs together; clear the chain bit in the last | |
3273 | * TRB to indicate it's the last TRB in the chain. | |
3274 | */ | |
86065c27 | 3275 | if (enqd_len + trb_buff_len < full_len) { |
b10de142 | 3276 | field |= TRB_CHAIN; |
2d98ef40 | 3277 | if (trb_is_link(ring->enqueue + 1)) { |
474ed23a | 3278 | if (xhci_align_td(xhci, urb, enqd_len, |
f9c589e1 MN |
3279 | &trb_buff_len, |
3280 | ring->enq_seg)) { | |
3281 | send_addr = ring->enq_seg->bounce_dma; | |
3282 | /* assuming TD won't span 2 segs */ | |
3283 | td->bounce_seg = ring->enq_seg; | |
3284 | } | |
474ed23a | 3285 | } |
f9c589e1 MN |
3286 | } |
3287 | if (enqd_len + trb_buff_len >= full_len) { | |
3288 | field &= ~TRB_CHAIN; | |
4758dcd1 | 3289 | field |= TRB_IOC; |
124c3937 | 3290 | more_trbs_coming = false; |
5a83f04a | 3291 | td->last_trb = ring->enqueue; |
b10de142 | 3292 | } |
af8b9e63 SS |
3293 | |
3294 | /* Only set interrupt on short packet for IN endpoints */ | |
3295 | if (usb_urb_dir_in(urb)) | |
3296 | field |= TRB_ISP; | |
3297 | ||
4da6e6f2 | 3298 | /* Set the TRB length, TD size, and interrupter fields. */ |
86065c27 MN |
3299 | remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, |
3300 | full_len, urb, more_trbs_coming); | |
3301 | ||
f9dc68fe | 3302 | length_field = TRB_LEN(trb_buff_len) | |
c840d6ce | 3303 | TRB_TD_SIZE(remainder) | |
f9dc68fe | 3304 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3305 | |
124c3937 | 3306 | queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, |
f9c589e1 MN |
3307 | lower_32_bits(send_addr), |
3308 | upper_32_bits(send_addr), | |
f9dc68fe | 3309 | length_field, |
d2510342 | 3310 | field); |
b10de142 | 3311 | |
b10de142 | 3312 | addr += trb_buff_len; |
f9c589e1 | 3313 | sent_len = trb_buff_len; |
d2510342 | 3314 | |
f9c589e1 | 3315 | while (sg && sent_len >= block_len) { |
86065c27 MN |
3316 | /* New sg entry */ |
3317 | --num_sgs; | |
f9c589e1 | 3318 | sent_len -= block_len; |
86065c27 | 3319 | if (num_sgs != 0) { |
d2510342 | 3320 | sg = sg_next(sg); |
86065c27 MN |
3321 | block_len = sg_dma_len(sg); |
3322 | addr = (u64) sg_dma_address(sg); | |
f9c589e1 | 3323 | addr += sent_len; |
d2510342 AI |
3324 | } |
3325 | } | |
f9c589e1 MN |
3326 | block_len -= sent_len; |
3327 | send_addr = addr; | |
d2510342 | 3328 | } |
b10de142 | 3329 | |
5a83f04a MN |
3330 | if (need_zero_pkt) { |
3331 | ret = prepare_transfer(xhci, xhci->devs[slot_id], | |
3332 | ep_index, urb->stream_id, | |
3333 | 1, urb, 1, mem_flags); | |
7e64b037 | 3334 | urb_priv->td[1].last_trb = ring->enqueue; |
5a83f04a MN |
3335 | field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; |
3336 | queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); | |
3337 | } | |
3338 | ||
86065c27 | 3339 | check_trb_math(urb, enqd_len); |
e9df17eb | 3340 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3341 | start_cycle, start_trb); |
b10de142 SS |
3342 | return 0; |
3343 | } | |
3344 | ||
d0e96f5a | 3345 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3346 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3347 | struct urb *urb, int slot_id, unsigned int ep_index) |
3348 | { | |
3349 | struct xhci_ring *ep_ring; | |
3350 | int num_trbs; | |
3351 | int ret; | |
3352 | struct usb_ctrlrequest *setup; | |
3353 | struct xhci_generic_trb *start_trb; | |
3354 | int start_cycle; | |
fb79a6da | 3355 | u32 field; |
8e51adcc | 3356 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3357 | struct xhci_td *td; |
3358 | ||
e9df17eb SS |
3359 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3360 | if (!ep_ring) | |
3361 | return -EINVAL; | |
d0e96f5a SS |
3362 | |
3363 | /* | |
3364 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3365 | * DMA address. | |
3366 | */ | |
3367 | if (!urb->setup_packet) | |
3368 | return -EINVAL; | |
3369 | ||
d0e96f5a SS |
3370 | /* 1 TRB for setup, 1 for status */ |
3371 | num_trbs = 2; | |
3372 | /* | |
3373 | * Don't need to check if we need additional event data and normal TRBs, | |
3374 | * since data in control transfers will never get bigger than 16MB | |
3375 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3376 | */ | |
3377 | if (urb->transfer_buffer_length > 0) | |
3378 | num_trbs++; | |
e9df17eb SS |
3379 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3380 | ep_index, urb->stream_id, | |
3b72fca0 | 3381 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3382 | if (ret < 0) |
3383 | return ret; | |
3384 | ||
8e51adcc | 3385 | urb_priv = urb->hcpriv; |
7e64b037 | 3386 | td = &urb_priv->td[0]; |
8e51adcc | 3387 | |
d0e96f5a SS |
3388 | /* |
3389 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3390 | * until we've finished creating all the other TRBs. The ring's cycle | |
3391 | * state may change as we enqueue the other TRBs, so save it too. | |
3392 | */ | |
3393 | start_trb = &ep_ring->enqueue->generic; | |
3394 | start_cycle = ep_ring->cycle_state; | |
3395 | ||
3396 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3397 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3398 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3399 | field = 0; |
3400 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3401 | if (start_cycle == 0) | |
3402 | field |= 0x1; | |
b83cdc8f | 3403 | |
dca77945 | 3404 | /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ |
0cbd4b34 | 3405 | if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { |
b83cdc8f AX |
3406 | if (urb->transfer_buffer_length > 0) { |
3407 | if (setup->bRequestType & USB_DIR_IN) | |
3408 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3409 | else | |
3410 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3411 | } | |
3412 | } | |
3413 | ||
3b72fca0 | 3414 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3415 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3416 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3417 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3418 | /* Immediate data in pointer */ | |
3419 | field); | |
d0e96f5a SS |
3420 | |
3421 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3422 | /* Only set interrupt on short packet for IN endpoints */ |
3423 | if (usb_urb_dir_in(urb)) | |
3424 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3425 | else | |
3426 | field = TRB_TYPE(TRB_DATA); | |
3427 | ||
d0e96f5a | 3428 | if (urb->transfer_buffer_length > 0) { |
fb79a6da LB |
3429 | u32 length_field, remainder; |
3430 | ||
3431 | remainder = xhci_td_remainder(xhci, 0, | |
3432 | urb->transfer_buffer_length, | |
3433 | urb->transfer_buffer_length, | |
3434 | urb, 1); | |
3435 | length_field = TRB_LEN(urb->transfer_buffer_length) | | |
3436 | TRB_TD_SIZE(remainder) | | |
3437 | TRB_INTR_TARGET(0); | |
d0e96f5a SS |
3438 | if (setup->bRequestType & USB_DIR_IN) |
3439 | field |= TRB_DIR_IN; | |
3b72fca0 | 3440 | queue_trb(xhci, ep_ring, true, |
d0e96f5a SS |
3441 | lower_32_bits(urb->transfer_dma), |
3442 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 3443 | length_field, |
af8b9e63 | 3444 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3445 | } |
3446 | ||
3447 | /* Save the DMA address of the last TRB in the TD */ | |
3448 | td->last_trb = ep_ring->enqueue; | |
3449 | ||
3450 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3451 | /* If the device sent data, the status stage is an OUT transfer */ | |
3452 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3453 | field = 0; | |
3454 | else | |
3455 | field = TRB_DIR_IN; | |
3b72fca0 | 3456 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3457 | 0, |
3458 | 0, | |
3459 | TRB_INTR_TARGET(0), | |
3460 | /* Event on completion */ | |
3461 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3462 | ||
e9df17eb | 3463 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3464 | start_cycle, start_trb); |
d0e96f5a SS |
3465 | return 0; |
3466 | } | |
3467 | ||
5cd43e33 SS |
3468 | /* |
3469 | * The transfer burst count field of the isochronous TRB defines the number of | |
3470 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3471 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3472 | * This field is zero based, meaning a value of zero in the field means one | |
3473 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3474 | * zero. Only xHCI 1.0 host controllers support this field. | |
3475 | */ | |
3476 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
5cd43e33 SS |
3477 | struct urb *urb, unsigned int total_packet_count) |
3478 | { | |
3479 | unsigned int max_burst; | |
3480 | ||
09c352ed | 3481 | if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) |
5cd43e33 SS |
3482 | return 0; |
3483 | ||
3484 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3213b151 | 3485 | return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; |
5cd43e33 SS |
3486 | } |
3487 | ||
b61d378f SS |
3488 | /* |
3489 | * Returns the number of packets in the last "burst" of packets. This field is | |
3490 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3491 | * the last burst packet count is equal to the total number of packets in the | |
3492 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3493 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3494 | * contain 1 to (bMaxBurst + 1) packets. | |
3495 | */ | |
3496 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
b61d378f SS |
3497 | struct urb *urb, unsigned int total_packet_count) |
3498 | { | |
3499 | unsigned int max_burst; | |
3500 | unsigned int residue; | |
3501 | ||
3502 | if (xhci->hci_version < 0x100) | |
3503 | return 0; | |
3504 | ||
09c352ed | 3505 | if (urb->dev->speed >= USB_SPEED_SUPER) { |
b61d378f SS |
3506 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ |
3507 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3508 | residue = total_packet_count % (max_burst + 1); | |
3509 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3510 | * number of packets, but the TLBPC field is zero-based. | |
3511 | */ | |
3512 | if (residue == 0) | |
3513 | return max_burst; | |
3514 | return residue - 1; | |
b61d378f | 3515 | } |
09c352ed MN |
3516 | if (total_packet_count == 0) |
3517 | return 0; | |
3518 | return total_packet_count - 1; | |
b61d378f SS |
3519 | } |
3520 | ||
79b8094f LB |
3521 | /* |
3522 | * Calculates Frame ID field of the isochronous TRB identifies the | |
3523 | * target frame that the Interval associated with this Isochronous | |
3524 | * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. | |
3525 | * | |
3526 | * Returns actual frame id on success, negative value on error. | |
3527 | */ | |
3528 | static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, | |
3529 | struct urb *urb, int index) | |
3530 | { | |
3531 | int start_frame, ist, ret = 0; | |
3532 | int start_frame_id, end_frame_id, current_frame_id; | |
3533 | ||
3534 | if (urb->dev->speed == USB_SPEED_LOW || | |
3535 | urb->dev->speed == USB_SPEED_FULL) | |
3536 | start_frame = urb->start_frame + index * urb->interval; | |
3537 | else | |
3538 | start_frame = (urb->start_frame + index * urb->interval) >> 3; | |
3539 | ||
3540 | /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): | |
3541 | * | |
3542 | * If bit [3] of IST is cleared to '0', software can add a TRB no | |
3543 | * later than IST[2:0] Microframes before that TRB is scheduled to | |
3544 | * be executed. | |
3545 | * If bit [3] of IST is set to '1', software can add a TRB no later | |
3546 | * than IST[2:0] Frames before that TRB is scheduled to be executed. | |
3547 | */ | |
3548 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3549 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3550 | ist <<= 3; | |
3551 | ||
3552 | /* Software shall not schedule an Isoch TD with a Frame ID value that | |
3553 | * is less than the Start Frame ID or greater than the End Frame ID, | |
3554 | * where: | |
3555 | * | |
3556 | * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 | |
3557 | * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 | |
3558 | * | |
3559 | * Both the End Frame ID and Start Frame ID values are calculated | |
3560 | * in microframes. When software determines the valid Frame ID value; | |
3561 | * The End Frame ID value should be rounded down to the nearest Frame | |
3562 | * boundary, and the Start Frame ID value should be rounded up to the | |
3563 | * nearest Frame boundary. | |
3564 | */ | |
3565 | current_frame_id = readl(&xhci->run_regs->microframe_index); | |
3566 | start_frame_id = roundup(current_frame_id + ist + 1, 8); | |
3567 | end_frame_id = rounddown(current_frame_id + 895 * 8, 8); | |
3568 | ||
3569 | start_frame &= 0x7ff; | |
3570 | start_frame_id = (start_frame_id >> 3) & 0x7ff; | |
3571 | end_frame_id = (end_frame_id >> 3) & 0x7ff; | |
3572 | ||
3573 | xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", | |
3574 | __func__, index, readl(&xhci->run_regs->microframe_index), | |
3575 | start_frame_id, end_frame_id, start_frame); | |
3576 | ||
3577 | if (start_frame_id < end_frame_id) { | |
3578 | if (start_frame > end_frame_id || | |
3579 | start_frame < start_frame_id) | |
3580 | ret = -EINVAL; | |
3581 | } else if (start_frame_id > end_frame_id) { | |
3582 | if ((start_frame > end_frame_id && | |
3583 | start_frame < start_frame_id)) | |
3584 | ret = -EINVAL; | |
3585 | } else { | |
3586 | ret = -EINVAL; | |
3587 | } | |
3588 | ||
3589 | if (index == 0) { | |
3590 | if (ret == -EINVAL || start_frame == start_frame_id) { | |
3591 | start_frame = start_frame_id + 1; | |
3592 | if (urb->dev->speed == USB_SPEED_LOW || | |
3593 | urb->dev->speed == USB_SPEED_FULL) | |
3594 | urb->start_frame = start_frame; | |
3595 | else | |
3596 | urb->start_frame = start_frame << 3; | |
3597 | ret = 0; | |
3598 | } | |
3599 | } | |
3600 | ||
3601 | if (ret) { | |
3602 | xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", | |
3603 | start_frame, current_frame_id, index, | |
3604 | start_frame_id, end_frame_id); | |
3605 | xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); | |
3606 | return ret; | |
3607 | } | |
3608 | ||
3609 | return start_frame; | |
3610 | } | |
3611 | ||
04e51901 AX |
3612 | /* This is for isoc transfer */ |
3613 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3614 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3615 | { | |
3616 | struct xhci_ring *ep_ring; | |
3617 | struct urb_priv *urb_priv; | |
3618 | struct xhci_td *td; | |
3619 | int num_tds, trbs_per_td; | |
3620 | struct xhci_generic_trb *start_trb; | |
3621 | bool first_trb; | |
3622 | int start_cycle; | |
3623 | u32 field, length_field; | |
3624 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
3625 | u64 start_addr, addr; | |
3626 | int i, j; | |
47cbf692 | 3627 | bool more_trbs_coming; |
79b8094f | 3628 | struct xhci_virt_ep *xep; |
09c352ed | 3629 | int frame_id; |
04e51901 | 3630 | |
79b8094f | 3631 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
3632 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
3633 | ||
3634 | num_tds = urb->number_of_packets; | |
3635 | if (num_tds < 1) { | |
3636 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
3637 | return -EINVAL; | |
3638 | } | |
04e51901 AX |
3639 | start_addr = (u64) urb->transfer_dma; |
3640 | start_trb = &ep_ring->enqueue->generic; | |
3641 | start_cycle = ep_ring->cycle_state; | |
3642 | ||
522989a2 | 3643 | urb_priv = urb->hcpriv; |
09c352ed | 3644 | /* Queue the TRBs for each TD, even if they are zero-length */ |
04e51901 | 3645 | for (i = 0; i < num_tds; i++) { |
09c352ed MN |
3646 | unsigned int total_pkt_count, max_pkt; |
3647 | unsigned int burst_count, last_burst_pkt_count; | |
3648 | u32 sia_frame_id; | |
04e51901 | 3649 | |
4da6e6f2 | 3650 | first_trb = true; |
04e51901 AX |
3651 | running_total = 0; |
3652 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
3653 | td_len = urb->iso_frame_desc[i].length; | |
3654 | td_remain_len = td_len; | |
734d3ddd | 3655 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
09c352ed MN |
3656 | total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); |
3657 | ||
48df4a6f | 3658 | /* A zero-length transfer still involves at least one packet. */ |
09c352ed MN |
3659 | if (total_pkt_count == 0) |
3660 | total_pkt_count++; | |
3661 | burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); | |
3662 | last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, | |
3663 | urb, total_pkt_count); | |
04e51901 | 3664 | |
d2510342 | 3665 | trbs_per_td = count_isoc_trbs_needed(urb, i); |
04e51901 AX |
3666 | |
3667 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 3668 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
3669 | if (ret < 0) { |
3670 | if (i == 0) | |
3671 | return ret; | |
3672 | goto cleanup; | |
3673 | } | |
7e64b037 | 3674 | td = &urb_priv->td[i]; |
09c352ed MN |
3675 | |
3676 | /* use SIA as default, if frame id is used overwrite it */ | |
3677 | sia_frame_id = TRB_SIA; | |
3678 | if (!(urb->transfer_flags & URB_ISO_ASAP) && | |
3679 | HCC_CFC(xhci->hcc_params)) { | |
3680 | frame_id = xhci_get_isoc_frame_id(xhci, urb, i); | |
3681 | if (frame_id >= 0) | |
3682 | sia_frame_id = TRB_FRAME_ID(frame_id); | |
3683 | } | |
3684 | /* | |
3685 | * Set isoc specific data for the first TRB in a TD. | |
3686 | * Prevent HW from getting the TRBs by keeping the cycle state | |
3687 | * inverted in the first TDs isoc TRB. | |
3688 | */ | |
2f6d3b65 | 3689 | field = TRB_TYPE(TRB_ISOC) | |
09c352ed MN |
3690 | TRB_TLBPC(last_burst_pkt_count) | |
3691 | sia_frame_id | | |
3692 | (i ? ep_ring->cycle_state : !start_cycle); | |
3693 | ||
2f6d3b65 MN |
3694 | /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ |
3695 | if (!xep->use_extended_tbc) | |
3696 | field |= TRB_TBC(burst_count); | |
3697 | ||
09c352ed | 3698 | /* fill the rest of the TRB fields, and remaining normal TRBs */ |
04e51901 AX |
3699 | for (j = 0; j < trbs_per_td; j++) { |
3700 | u32 remainder = 0; | |
09c352ed MN |
3701 | |
3702 | /* only first TRB is isoc, overwrite otherwise */ | |
3703 | if (!first_trb) | |
3704 | field = TRB_TYPE(TRB_NORMAL) | | |
3705 | ep_ring->cycle_state; | |
04e51901 | 3706 | |
af8b9e63 SS |
3707 | /* Only set interrupt on short packet for IN EPs */ |
3708 | if (usb_urb_dir_in(urb)) | |
3709 | field |= TRB_ISP; | |
3710 | ||
09c352ed | 3711 | /* Set the chain bit for all except the last TRB */ |
04e51901 | 3712 | if (j < trbs_per_td - 1) { |
47cbf692 | 3713 | more_trbs_coming = true; |
09c352ed | 3714 | field |= TRB_CHAIN; |
04e51901 | 3715 | } else { |
09c352ed | 3716 | more_trbs_coming = false; |
04e51901 AX |
3717 | td->last_trb = ep_ring->enqueue; |
3718 | field |= TRB_IOC; | |
09c352ed MN |
3719 | /* set BEI, except for the last TD */ |
3720 | if (xhci->hci_version >= 0x100 && | |
3721 | !(xhci->quirks & XHCI_AVOID_BEI) && | |
3722 | i < num_tds - 1) | |
3723 | field |= TRB_BEI; | |
04e51901 | 3724 | } |
04e51901 | 3725 | /* Calculate TRB length */ |
d2510342 | 3726 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); |
04e51901 AX |
3727 | if (trb_buff_len > td_remain_len) |
3728 | trb_buff_len = td_remain_len; | |
3729 | ||
4da6e6f2 | 3730 | /* Set the TRB length, TD size, & interrupter fields. */ |
c840d6ce MN |
3731 | remainder = xhci_td_remainder(xhci, running_total, |
3732 | trb_buff_len, td_len, | |
124c3937 | 3733 | urb, more_trbs_coming); |
c840d6ce | 3734 | |
04e51901 | 3735 | length_field = TRB_LEN(trb_buff_len) | |
04e51901 | 3736 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3737 | |
2f6d3b65 MN |
3738 | /* xhci 1.1 with ETE uses TD Size field for TBC */ |
3739 | if (first_trb && xep->use_extended_tbc) | |
3740 | length_field |= TRB_TD_SIZE_TBC(burst_count); | |
3741 | else | |
3742 | length_field |= TRB_TD_SIZE(remainder); | |
3743 | first_trb = false; | |
3744 | ||
3b72fca0 | 3745 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
3746 | lower_32_bits(addr), |
3747 | upper_32_bits(addr), | |
3748 | length_field, | |
af8b9e63 | 3749 | field); |
04e51901 AX |
3750 | running_total += trb_buff_len; |
3751 | ||
3752 | addr += trb_buff_len; | |
3753 | td_remain_len -= trb_buff_len; | |
3754 | } | |
3755 | ||
3756 | /* Check TD length */ | |
3757 | if (running_total != td_len) { | |
3758 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
3759 | ret = -EINVAL; |
3760 | goto cleanup; | |
04e51901 AX |
3761 | } |
3762 | } | |
3763 | ||
79b8094f LB |
3764 | /* store the next frame id */ |
3765 | if (HCC_CFC(xhci->hcc_params)) | |
3766 | xep->next_frame_id = urb->start_frame + num_tds * urb->interval; | |
3767 | ||
c41136b0 AX |
3768 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
3769 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
3770 | usb_amd_quirk_pll_disable(); | |
3771 | } | |
3772 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
3773 | ||
e1eab2e0 AX |
3774 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3775 | start_cycle, start_trb); | |
04e51901 | 3776 | return 0; |
522989a2 SS |
3777 | cleanup: |
3778 | /* Clean up a partially enqueued isoc transfer. */ | |
3779 | ||
3780 | for (i--; i >= 0; i--) | |
7e64b037 | 3781 | list_del_init(&urb_priv->td[i].td_list); |
522989a2 SS |
3782 | |
3783 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
3784 | * into No-ops with a software-owned cycle bit. That way the hardware | |
3785 | * won't accidentally start executing bogus TDs when we partially | |
3786 | * overwrite them. td->first_trb and td->start_seg are already set. | |
3787 | */ | |
7e64b037 | 3788 | urb_priv->td[0].last_trb = ep_ring->enqueue; |
522989a2 | 3789 | /* Every TRB except the first & last will have its cycle bit flipped. */ |
7e64b037 | 3790 | td_to_noop(xhci, ep_ring, &urb_priv->td[0], true); |
522989a2 SS |
3791 | |
3792 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
7e64b037 MN |
3793 | ep_ring->enqueue = urb_priv->td[0].first_trb; |
3794 | ep_ring->enq_seg = urb_priv->td[0].start_seg; | |
522989a2 | 3795 | ep_ring->cycle_state = start_cycle; |
b008df60 | 3796 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
3797 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
3798 | return ret; | |
04e51901 AX |
3799 | } |
3800 | ||
3801 | /* | |
3802 | * Check transfer ring to guarantee there is enough room for the urb. | |
3803 | * Update ISO URB start_frame and interval. | |
79b8094f LB |
3804 | * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to |
3805 | * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or | |
3806 | * Contiguous Frame ID is not supported by HC. | |
04e51901 AX |
3807 | */ |
3808 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3809 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3810 | { | |
3811 | struct xhci_virt_device *xdev; | |
3812 | struct xhci_ring *ep_ring; | |
3813 | struct xhci_ep_ctx *ep_ctx; | |
3814 | int start_frame; | |
04e51901 AX |
3815 | int num_tds, num_trbs, i; |
3816 | int ret; | |
79b8094f LB |
3817 | struct xhci_virt_ep *xep; |
3818 | int ist; | |
04e51901 AX |
3819 | |
3820 | xdev = xhci->devs[slot_id]; | |
79b8094f | 3821 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
3822 | ep_ring = xdev->eps[ep_index].ring; |
3823 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3824 | ||
3825 | num_trbs = 0; | |
3826 | num_tds = urb->number_of_packets; | |
3827 | for (i = 0; i < num_tds; i++) | |
d2510342 | 3828 | num_trbs += count_isoc_trbs_needed(urb, i); |
04e51901 AX |
3829 | |
3830 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3831 | * Do not insert any td of the urb to the ring if the check failed. | |
3832 | */ | |
5071e6b2 | 3833 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 3834 | num_trbs, mem_flags); |
04e51901 AX |
3835 | if (ret) |
3836 | return ret; | |
3837 | ||
79b8094f LB |
3838 | /* |
3839 | * Check interval value. This should be done before we start to | |
3840 | * calculate the start frame value. | |
3841 | */ | |
78140156 | 3842 | check_interval(xhci, urb, ep_ctx); |
79b8094f LB |
3843 | |
3844 | /* Calculate the start frame and put it in urb->start_frame. */ | |
42df7215 | 3845 | if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { |
5071e6b2 | 3846 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) { |
42df7215 LB |
3847 | urb->start_frame = xep->next_frame_id; |
3848 | goto skip_start_over; | |
3849 | } | |
79b8094f LB |
3850 | } |
3851 | ||
3852 | start_frame = readl(&xhci->run_regs->microframe_index); | |
3853 | start_frame &= 0x3fff; | |
3854 | /* | |
3855 | * Round up to the next frame and consider the time before trb really | |
3856 | * gets scheduled by hardare. | |
3857 | */ | |
3858 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3859 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3860 | ist <<= 3; | |
3861 | start_frame += ist + XHCI_CFC_DELAY; | |
3862 | start_frame = roundup(start_frame, 8); | |
3863 | ||
3864 | /* | |
3865 | * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT | |
3866 | * is greate than 8 microframes. | |
3867 | */ | |
3868 | if (urb->dev->speed == USB_SPEED_LOW || | |
3869 | urb->dev->speed == USB_SPEED_FULL) { | |
3870 | start_frame = roundup(start_frame, urb->interval << 3); | |
3871 | urb->start_frame = start_frame >> 3; | |
3872 | } else { | |
3873 | start_frame = roundup(start_frame, urb->interval); | |
3874 | urb->start_frame = start_frame; | |
3875 | } | |
3876 | ||
3877 | skip_start_over: | |
b008df60 AX |
3878 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
3879 | ||
3fc8206d | 3880 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
3881 | } |
3882 | ||
d0e96f5a SS |
3883 | /**** Command Ring Operations ****/ |
3884 | ||
913a8a34 SS |
3885 | /* Generic function for queueing a command TRB on the command ring. |
3886 | * Check to make sure there's room on the command ring for one command TRB. | |
3887 | * Also check that there's room reserved for commands that must not fail. | |
3888 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
3889 | * then only check for the number of reserved spots. | |
3890 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
3891 | * because the command event handler may want to resubmit a failed command. | |
3892 | */ | |
ddba5cd0 MN |
3893 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3894 | u32 field1, u32 field2, | |
3895 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 3896 | { |
913a8a34 | 3897 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a | 3898 | int ret; |
ad6b1d91 | 3899 | |
98d74f9c MN |
3900 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
3901 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
ad6b1d91 | 3902 | xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); |
c9aa1a2d | 3903 | return -ESHUTDOWN; |
ad6b1d91 | 3904 | } |
d1dc908a | 3905 | |
913a8a34 SS |
3906 | if (!command_must_succeed) |
3907 | reserved_trbs++; | |
3908 | ||
d1dc908a | 3909 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 3910 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
3911 | if (ret < 0) { |
3912 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
3913 | if (command_must_succeed) |
3914 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
3915 | "unfailable commands failed.\n"); | |
d1dc908a | 3916 | return ret; |
7f84eef0 | 3917 | } |
c9aa1a2d MN |
3918 | |
3919 | cmd->command_trb = xhci->cmd_ring->enqueue; | |
ddba5cd0 | 3920 | |
c311e391 | 3921 | /* if there are no other commands queued we start the timeout timer */ |
daa47f21 | 3922 | if (list_empty(&xhci->cmd_list)) { |
c311e391 | 3923 | xhci->current_cmd = cmd; |
cb4d5ce5 | 3924 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
c311e391 MN |
3925 | } |
3926 | ||
daa47f21 LB |
3927 | list_add_tail(&cmd->cmd_list, &xhci->cmd_list); |
3928 | ||
3b72fca0 AX |
3929 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
3930 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
3931 | return 0; |
3932 | } | |
3933 | ||
3ffbba95 | 3934 | /* Queue a slot enable or disable request on the command ring */ |
ddba5cd0 MN |
3935 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3936 | u32 trb_type, u32 slot_id) | |
3ffbba95 | 3937 | { |
ddba5cd0 | 3938 | return queue_command(xhci, cmd, 0, 0, 0, |
913a8a34 | 3939 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
3940 | } |
3941 | ||
3942 | /* Queue an address device command TRB */ | |
ddba5cd0 MN |
3943 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3944 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) | |
3ffbba95 | 3945 | { |
ddba5cd0 | 3946 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3947 | upper_32_bits(in_ctx_ptr), 0, |
48fc7dbd DW |
3948 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
3949 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); | |
2a8f82c4 SS |
3950 | } |
3951 | ||
ddba5cd0 | 3952 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
0238634d SS |
3953 | u32 field1, u32 field2, u32 field3, u32 field4) |
3954 | { | |
ddba5cd0 | 3955 | return queue_command(xhci, cmd, field1, field2, field3, field4, false); |
0238634d SS |
3956 | } |
3957 | ||
2a8f82c4 | 3958 | /* Queue a reset device command TRB */ |
ddba5cd0 MN |
3959 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3960 | u32 slot_id) | |
2a8f82c4 | 3961 | { |
ddba5cd0 | 3962 | return queue_command(xhci, cmd, 0, 0, 0, |
2a8f82c4 | 3963 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
913a8a34 | 3964 | false); |
3ffbba95 | 3965 | } |
f94e0186 SS |
3966 | |
3967 | /* Queue a configure endpoint command TRB */ | |
ddba5cd0 MN |
3968 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
3969 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, | |
913a8a34 | 3970 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 3971 | { |
ddba5cd0 | 3972 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3973 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 SS |
3974 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
3975 | command_must_succeed); | |
f94e0186 | 3976 | } |
ae636747 | 3977 | |
f2217e8e | 3978 | /* Queue an evaluate context command TRB */ |
ddba5cd0 MN |
3979 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3980 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) | |
f2217e8e | 3981 | { |
ddba5cd0 | 3982 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
f2217e8e | 3983 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 | 3984 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 3985 | command_must_succeed); |
f2217e8e SS |
3986 | } |
3987 | ||
be88fe4f AX |
3988 | /* |
3989 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
3990 | * activity on an endpoint that is about to be suspended. | |
3991 | */ | |
ddba5cd0 MN |
3992 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3993 | int slot_id, unsigned int ep_index, int suspend) | |
ae636747 SS |
3994 | { |
3995 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3996 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3997 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 3998 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 | 3999 | |
ddba5cd0 | 4000 | return queue_command(xhci, cmd, 0, 0, 0, |
be88fe4f | 4001 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
4002 | } |
4003 | ||
d3a43e66 HG |
4004 | /* Set Transfer Ring Dequeue Pointer command */ |
4005 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, | |
4006 | unsigned int slot_id, unsigned int ep_index, | |
d3a43e66 | 4007 | struct xhci_dequeue_state *deq_state) |
ae636747 SS |
4008 | { |
4009 | dma_addr_t addr; | |
4010 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4011 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
8790736d | 4012 | u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id); |
95241dbd | 4013 | u32 trb_sct = 0; |
ae636747 | 4014 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
bf161e85 | 4015 | struct xhci_virt_ep *ep; |
1e3452e3 HG |
4016 | struct xhci_command *cmd; |
4017 | int ret; | |
ae636747 | 4018 | |
d3a43e66 HG |
4019 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
4020 | "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u", | |
4021 | deq_state->new_deq_seg, | |
4022 | (unsigned long long)deq_state->new_deq_seg->dma, | |
4023 | deq_state->new_deq_ptr, | |
4024 | (unsigned long long)xhci_trb_virt_to_dma( | |
4025 | deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
4026 | deq_state->new_cycle_state); | |
4027 | ||
4028 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
4029 | deq_state->new_deq_ptr); | |
c92bcfa7 | 4030 | if (addr == 0) { |
ae636747 | 4031 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 | 4032 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
d3a43e66 HG |
4033 | deq_state->new_deq_seg, deq_state->new_deq_ptr); |
4034 | return; | |
c92bcfa7 | 4035 | } |
bf161e85 SS |
4036 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
4037 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
4038 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | |
4039 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | |
d3a43e66 | 4040 | return; |
bf161e85 | 4041 | } |
1e3452e3 HG |
4042 | |
4043 | /* This function gets called from contexts where it cannot sleep */ | |
4044 | cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
74e0b564 | 4045 | if (!cmd) |
d3a43e66 | 4046 | return; |
1e3452e3 | 4047 | |
d3a43e66 HG |
4048 | ep->queued_deq_seg = deq_state->new_deq_seg; |
4049 | ep->queued_deq_ptr = deq_state->new_deq_ptr; | |
8790736d | 4050 | if (deq_state->stream_id) |
95241dbd | 4051 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); |
1e3452e3 | 4052 | ret = queue_command(xhci, cmd, |
d3a43e66 HG |
4053 | lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state, |
4054 | upper_32_bits(addr), trb_stream_id, | |
4055 | trb_slot_id | trb_ep_index | type, false); | |
1e3452e3 HG |
4056 | if (ret < 0) { |
4057 | xhci_free_command(xhci, cmd); | |
d3a43e66 | 4058 | return; |
1e3452e3 HG |
4059 | } |
4060 | ||
d3a43e66 HG |
4061 | /* Stop the TD queueing code from ringing the doorbell until |
4062 | * this command completes. The HC won't set the dequeue pointer | |
4063 | * if the ring is running, and ringing the doorbell starts the | |
4064 | * ring running. | |
4065 | */ | |
4066 | ep->ep_state |= SET_DEQ_PENDING; | |
ae636747 | 4067 | } |
a1587d97 | 4068 | |
ddba5cd0 | 4069 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
21749148 MN |
4070 | int slot_id, unsigned int ep_index, |
4071 | enum xhci_ep_reset_type reset_type) | |
a1587d97 SS |
4072 | { |
4073 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4074 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4075 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
4076 | ||
21749148 MN |
4077 | if (reset_type == EP_SOFT_RESET) |
4078 | type |= TRB_TSP; | |
4079 | ||
ddba5cd0 MN |
4080 | return queue_command(xhci, cmd, 0, 0, 0, |
4081 | trb_slot_id | trb_ep_index | type, false); | |
a1587d97 | 4082 | } |