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Commit | Line | Data |
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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
7f84eef0 | 69 | #include "xhci.h" |
3a7fa5be | 70 | #include "xhci-trace.h" |
7f84eef0 SS |
71 | |
72 | /* | |
73 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
74 | * address of the TRB. | |
75 | */ | |
23e3be11 | 76 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
77 | union xhci_trb *trb) |
78 | { | |
6071d836 | 79 | unsigned long segment_offset; |
7f84eef0 | 80 | |
6071d836 | 81 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 82 | return 0; |
6071d836 SS |
83 | /* offset in TRBs */ |
84 | segment_offset = trb - seg->trbs; | |
85 | if (segment_offset > TRBS_PER_SEGMENT) | |
7f84eef0 | 86 | return 0; |
6071d836 | 87 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
88 | } |
89 | ||
90 | /* Does this link TRB point to the first segment in a ring, | |
91 | * or was the previous TRB the last TRB on the last segment in the ERST? | |
92 | */ | |
575688e1 | 93 | static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
94 | struct xhci_segment *seg, union xhci_trb *trb) |
95 | { | |
96 | if (ring == xhci->event_ring) | |
97 | return (trb == &seg->trbs[TRBS_PER_SEGMENT]) && | |
98 | (seg->next == xhci->event_ring->first_seg); | |
99 | else | |
28ccd296 | 100 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; |
7f84eef0 SS |
101 | } |
102 | ||
103 | /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring | |
104 | * segment? I.e. would the updated event TRB pointer step off the end of the | |
105 | * event seg? | |
106 | */ | |
575688e1 | 107 | static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
108 | struct xhci_segment *seg, union xhci_trb *trb) |
109 | { | |
110 | if (ring == xhci->event_ring) | |
111 | return trb == &seg->trbs[TRBS_PER_SEGMENT]; | |
112 | else | |
f5960b69 | 113 | return TRB_TYPE_LINK_LE32(trb->link.control); |
7f84eef0 SS |
114 | } |
115 | ||
575688e1 | 116 | static int enqueue_is_link_trb(struct xhci_ring *ring) |
6c12db90 JY |
117 | { |
118 | struct xhci_link_trb *link = &ring->enqueue->link; | |
f5960b69 | 119 | return TRB_TYPE_LINK_LE32(link->control); |
6c12db90 JY |
120 | } |
121 | ||
ae636747 SS |
122 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
123 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
124 | * effect the ring dequeue or enqueue pointers. | |
125 | */ | |
126 | static void next_trb(struct xhci_hcd *xhci, | |
127 | struct xhci_ring *ring, | |
128 | struct xhci_segment **seg, | |
129 | union xhci_trb **trb) | |
130 | { | |
131 | if (last_trb(xhci, ring, *seg, *trb)) { | |
132 | *seg = (*seg)->next; | |
133 | *trb = ((*seg)->trbs); | |
134 | } else { | |
a1669b2c | 135 | (*trb)++; |
ae636747 SS |
136 | } |
137 | } | |
138 | ||
7f84eef0 SS |
139 | /* |
140 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
141 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
142 | */ | |
3b72fca0 | 143 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 144 | { |
7f84eef0 | 145 | ring->deq_updates++; |
b008df60 | 146 | |
50d0206f SS |
147 | /* |
148 | * If this is not event ring, and the dequeue pointer | |
149 | * is not on a link TRB, there is one more usable TRB | |
150 | */ | |
b008df60 AX |
151 | if (ring->type != TYPE_EVENT && |
152 | !last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) | |
153 | ring->num_trbs_free++; | |
b008df60 | 154 | |
50d0206f SS |
155 | do { |
156 | /* | |
157 | * Update the dequeue pointer further if that was a link TRB or | |
158 | * we're at the end of an event ring segment (which doesn't have | |
159 | * link TRBS) | |
160 | */ | |
161 | if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) { | |
162 | if (ring->type == TYPE_EVENT && | |
163 | last_trb_on_last_seg(xhci, ring, | |
164 | ring->deq_seg, ring->dequeue)) { | |
4e341818 | 165 | ring->cycle_state ^= 1; |
50d0206f SS |
166 | } |
167 | ring->deq_seg = ring->deq_seg->next; | |
168 | ring->dequeue = ring->deq_seg->trbs; | |
169 | } else { | |
170 | ring->dequeue++; | |
7f84eef0 | 171 | } |
50d0206f | 172 | } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)); |
7f84eef0 SS |
173 | } |
174 | ||
175 | /* | |
176 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
177 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
178 | * | |
179 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
180 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
181 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
182 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
183 | * | |
184 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
185 | * set, but other sections talk about dealing with the chain bit set. This was |
186 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
187 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
188 | * |
189 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
190 | * prepare_transfer()? | |
7f84eef0 | 191 | */ |
6cc30d85 | 192 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 193 | bool more_trbs_coming) |
7f84eef0 SS |
194 | { |
195 | u32 chain; | |
196 | union xhci_trb *next; | |
197 | ||
28ccd296 | 198 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 AX |
199 | /* If this is not event ring, there is one less usable TRB */ |
200 | if (ring->type != TYPE_EVENT && | |
201 | !last_trb(xhci, ring, ring->enq_seg, ring->enqueue)) | |
202 | ring->num_trbs_free--; | |
7f84eef0 SS |
203 | next = ++(ring->enqueue); |
204 | ||
205 | ring->enq_updates++; | |
206 | /* Update the dequeue pointer further if that was a link TRB or we're at | |
207 | * the end of an event ring segment (which doesn't have link TRBS) | |
208 | */ | |
209 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
3b72fca0 AX |
210 | if (ring->type != TYPE_EVENT) { |
211 | /* | |
212 | * If the caller doesn't plan on enqueueing more | |
213 | * TDs before ringing the doorbell, then we | |
214 | * don't want to give the link TRB to the | |
215 | * hardware just yet. We'll give the link TRB | |
216 | * back in prepare_ring() just before we enqueue | |
217 | * the TD at the top of the ring. | |
218 | */ | |
219 | if (!chain && !more_trbs_coming) | |
220 | break; | |
6cc30d85 | 221 | |
3b72fca0 AX |
222 | /* If we're not dealing with 0.95 hardware or |
223 | * isoc rings on AMD 0.96 host, | |
224 | * carry over the chain bit of the previous TRB | |
225 | * (which may mean the chain bit is cleared). | |
226 | */ | |
227 | if (!(ring->type == TYPE_ISOC && | |
228 | (xhci->quirks & XHCI_AMD_0x96_HOST)) | |
7e393a83 | 229 | && !xhci_link_trb_quirk(xhci)) { |
3b72fca0 AX |
230 | next->link.control &= |
231 | cpu_to_le32(~TRB_CHAIN); | |
232 | next->link.control |= | |
233 | cpu_to_le32(chain); | |
7f84eef0 | 234 | } |
3b72fca0 AX |
235 | /* Give this link TRB to the hardware */ |
236 | wmb(); | |
237 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
238 | ||
7f84eef0 SS |
239 | /* Toggle the cycle bit after the last ring segment. */ |
240 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
241 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
7f84eef0 SS |
242 | } |
243 | } | |
244 | ring->enq_seg = ring->enq_seg->next; | |
245 | ring->enqueue = ring->enq_seg->trbs; | |
246 | next = ring->enqueue; | |
247 | } | |
248 | } | |
249 | ||
250 | /* | |
085deb16 AX |
251 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
252 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 253 | */ |
b008df60 | 254 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
255 | unsigned int num_trbs) |
256 | { | |
085deb16 | 257 | int num_trbs_in_deq_seg; |
b008df60 | 258 | |
085deb16 AX |
259 | if (ring->num_trbs_free < num_trbs) |
260 | return 0; | |
261 | ||
262 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
263 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
264 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
265 | return 0; | |
266 | } | |
267 | ||
268 | return 1; | |
7f84eef0 SS |
269 | } |
270 | ||
7f84eef0 | 271 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 272 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 273 | { |
c181bc5b EF |
274 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
275 | return; | |
276 | ||
7f84eef0 | 277 | xhci_dbg(xhci, "// Ding dong!\n"); |
204b7793 | 278 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 | 279 | /* Flush PCI posted writes */ |
b0ba9720 | 280 | readl(&xhci->dba->doorbell[0]); |
7f84eef0 SS |
281 | } |
282 | ||
b92cc66c EF |
283 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci) |
284 | { | |
285 | u64 temp_64; | |
286 | int ret; | |
287 | ||
288 | xhci_dbg(xhci, "Abort command ring\n"); | |
289 | ||
f7b2e403 | 290 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
b92cc66c | 291 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; |
477632df SS |
292 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, |
293 | &xhci->op_regs->cmd_ring); | |
b92cc66c EF |
294 | |
295 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should | |
296 | * time the completion od all xHCI commands, including | |
297 | * the Command Abort operation. If software doesn't see | |
298 | * CRR negated in a timely manner (e.g. longer than 5 | |
299 | * seconds), then it should assume that the there are | |
300 | * larger problems with the xHC and assert HCRST. | |
301 | */ | |
2611bd18 | 302 | ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring, |
b92cc66c EF |
303 | CMD_RING_RUNNING, 0, 5 * 1000 * 1000); |
304 | if (ret < 0) { | |
305 | xhci_err(xhci, "Stopped the command ring failed, " | |
306 | "maybe the host is dead\n"); | |
307 | xhci->xhc_state |= XHCI_STATE_DYING; | |
308 | xhci_quiesce(xhci); | |
309 | xhci_halt(xhci); | |
310 | return -ESHUTDOWN; | |
311 | } | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
be88fe4f | 316 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 317 | unsigned int slot_id, |
e9df17eb SS |
318 | unsigned int ep_index, |
319 | unsigned int stream_id) | |
ae636747 | 320 | { |
28ccd296 | 321 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
322 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
323 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 324 | |
ae636747 | 325 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 326 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
327 | * We don't want to restart any stream rings if there's a set dequeue |
328 | * pointer command pending because the device can choose to start any | |
329 | * stream once the endpoint is on the HW schedule. | |
330 | * FIXME - check all the stream rings for pending cancellations. | |
ae636747 | 331 | */ |
50d64676 MW |
332 | if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) || |
333 | (ep_state & EP_HALTED)) | |
334 | return; | |
204b7793 | 335 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
50d64676 MW |
336 | /* The CPU has better things to do at this point than wait for a |
337 | * write-posting flush. It'll get there soon enough. | |
338 | */ | |
ae636747 SS |
339 | } |
340 | ||
e9df17eb SS |
341 | /* Ring the doorbell for any rings with pending URBs */ |
342 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
343 | unsigned int slot_id, | |
344 | unsigned int ep_index) | |
345 | { | |
346 | unsigned int stream_id; | |
347 | struct xhci_virt_ep *ep; | |
348 | ||
349 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
350 | ||
351 | /* A ring has pending URBs if its TD list is not empty */ | |
352 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
d66eaf9f | 353 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
be88fe4f | 354 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
355 | return; |
356 | } | |
357 | ||
358 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
359 | stream_id++) { | |
360 | struct xhci_stream_info *stream_info = ep->stream_info; | |
361 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
362 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
363 | stream_id); | |
e9df17eb SS |
364 | } |
365 | } | |
366 | ||
021bff91 SS |
367 | static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, |
368 | unsigned int slot_id, unsigned int ep_index, | |
369 | unsigned int stream_id) | |
370 | { | |
371 | struct xhci_virt_ep *ep; | |
372 | ||
373 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
374 | /* Common case: no streams */ | |
375 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
376 | return ep->ring; | |
377 | ||
378 | if (stream_id == 0) { | |
379 | xhci_warn(xhci, | |
380 | "WARN: Slot ID %u, ep index %u has streams, " | |
381 | "but URB has no stream ID.\n", | |
382 | slot_id, ep_index); | |
383 | return NULL; | |
384 | } | |
385 | ||
386 | if (stream_id < ep->stream_info->num_streams) | |
387 | return ep->stream_info->stream_rings[stream_id]; | |
388 | ||
389 | xhci_warn(xhci, | |
390 | "WARN: Slot ID %u, ep index %u has " | |
391 | "stream IDs 1 to %u allocated, " | |
392 | "but stream ID %u is requested.\n", | |
393 | slot_id, ep_index, | |
394 | ep->stream_info->num_streams - 1, | |
395 | stream_id); | |
396 | return NULL; | |
397 | } | |
398 | ||
399 | /* Get the right ring for the given URB. | |
400 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
401 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
402 | */ | |
403 | static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, | |
404 | struct urb *urb) | |
405 | { | |
406 | return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, | |
407 | xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id); | |
408 | } | |
409 | ||
ae636747 SS |
410 | /* |
411 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
412 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
413 | * dequeue pointer, and new consumer cycle state in state. | |
414 | * Update our internal representation of the ring's dequeue pointer. | |
415 | * | |
416 | * We do this in three jumps: | |
417 | * - First we update our new ring state to be the same as when the xHC stopped. | |
418 | * - Then we traverse the ring to find the segment that contains | |
419 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
420 | * any link TRBs with the toggle cycle bit set. | |
421 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
422 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
28ccd296 ME |
423 | * |
424 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | |
425 | * with correct __le32 accesses they should work fine. Only users of this are | |
426 | * in here. | |
ae636747 | 427 | */ |
c92bcfa7 | 428 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 429 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
430 | unsigned int stream_id, struct xhci_td *cur_td, |
431 | struct xhci_dequeue_state *state) | |
ae636747 SS |
432 | { |
433 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
c4bedb77 | 434 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; |
e9df17eb | 435 | struct xhci_ring *ep_ring; |
365038d8 MN |
436 | struct xhci_segment *new_seg; |
437 | union xhci_trb *new_deq; | |
c92bcfa7 | 438 | dma_addr_t addr; |
1f81b6d2 | 439 | u64 hw_dequeue; |
365038d8 MN |
440 | bool cycle_found = false; |
441 | bool td_last_trb_found = false; | |
ae636747 | 442 | |
e9df17eb SS |
443 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
444 | ep_index, stream_id); | |
445 | if (!ep_ring) { | |
446 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
447 | "for invalid stream ID %u.\n", | |
448 | stream_id); | |
449 | return; | |
450 | } | |
68e41c5d | 451 | |
ae636747 | 452 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
aa50b290 XR |
453 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
454 | "Finding endpoint context"); | |
c4bedb77 HG |
455 | /* 4.6.9 the css flag is written to the stream context for streams */ |
456 | if (ep->ep_state & EP_HAS_STREAMS) { | |
457 | struct xhci_stream_ctx *ctx = | |
458 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1f81b6d2 | 459 | hw_dequeue = le64_to_cpu(ctx->stream_ring); |
c4bedb77 HG |
460 | } else { |
461 | struct xhci_ep_ctx *ep_ctx | |
462 | = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); | |
1f81b6d2 | 463 | hw_dequeue = le64_to_cpu(ep_ctx->deq); |
c4bedb77 | 464 | } |
ae636747 | 465 | |
365038d8 MN |
466 | new_seg = ep_ring->deq_seg; |
467 | new_deq = ep_ring->dequeue; | |
468 | state->new_cycle_state = hw_dequeue & 0x1; | |
469 | ||
1f81b6d2 | 470 | /* |
365038d8 MN |
471 | * We want to find the pointer, segment and cycle state of the new trb |
472 | * (the one after current TD's last_trb). We know the cycle state at | |
473 | * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are | |
474 | * found. | |
1f81b6d2 | 475 | */ |
365038d8 MN |
476 | do { |
477 | if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) | |
478 | == (dma_addr_t)(hw_dequeue & ~0xf)) { | |
479 | cycle_found = true; | |
480 | if (td_last_trb_found) | |
481 | break; | |
482 | } | |
483 | if (new_deq == cur_td->last_trb) | |
484 | td_last_trb_found = true; | |
1f81b6d2 | 485 | |
365038d8 MN |
486 | if (cycle_found && |
487 | TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) && | |
488 | new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE)) | |
489 | state->new_cycle_state ^= 0x1; | |
490 | ||
491 | next_trb(xhci, ep_ring, &new_seg, &new_deq); | |
492 | ||
493 | /* Search wrapped around, bail out */ | |
494 | if (new_deq == ep->ring->dequeue) { | |
495 | xhci_err(xhci, "Error: Failed finding new dequeue state\n"); | |
496 | state->new_deq_seg = NULL; | |
497 | state->new_deq_ptr = NULL; | |
498 | return; | |
499 | } | |
500 | ||
501 | } while (!cycle_found || !td_last_trb_found); | |
ae636747 | 502 | |
365038d8 MN |
503 | state->new_deq_seg = new_seg; |
504 | state->new_deq_ptr = new_deq; | |
ae636747 | 505 | |
1f81b6d2 | 506 | /* Don't update the ring cycle state for the producer (us). */ |
aa50b290 XR |
507 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
508 | "Cycle state = 0x%x", state->new_cycle_state); | |
01a1fdb9 | 509 | |
aa50b290 XR |
510 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
511 | "New dequeue segment = %p (virtual)", | |
c92bcfa7 SS |
512 | state->new_deq_seg); |
513 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
aa50b290 XR |
514 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
515 | "New dequeue pointer = 0x%llx (DMA)", | |
c92bcfa7 | 516 | (unsigned long long) addr); |
ae636747 SS |
517 | } |
518 | ||
522989a2 SS |
519 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
520 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
521 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
522 | */ | |
23e3be11 | 523 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
522989a2 | 524 | struct xhci_td *cur_td, bool flip_cycle) |
ae636747 SS |
525 | { |
526 | struct xhci_segment *cur_seg; | |
527 | union xhci_trb *cur_trb; | |
528 | ||
529 | for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb; | |
530 | true; | |
531 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 | 532 | if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) { |
ae636747 SS |
533 | /* Unchain any chained Link TRBs, but |
534 | * leave the pointers intact. | |
535 | */ | |
28ccd296 | 536 | cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN); |
522989a2 SS |
537 | /* Flip the cycle bit (link TRBs can't be the first |
538 | * or last TRB). | |
539 | */ | |
540 | if (flip_cycle) | |
541 | cur_trb->generic.field[3] ^= | |
542 | cpu_to_le32(TRB_CYCLE); | |
aa50b290 XR |
543 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
544 | "Cancel (unchain) link TRB"); | |
545 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
546 | "Address = %p (0x%llx dma); " | |
547 | "in seg %p (0x%llx dma)", | |
700e2052 | 548 | cur_trb, |
23e3be11 | 549 | (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb), |
700e2052 GKH |
550 | cur_seg, |
551 | (unsigned long long)cur_seg->dma); | |
ae636747 SS |
552 | } else { |
553 | cur_trb->generic.field[0] = 0; | |
554 | cur_trb->generic.field[1] = 0; | |
555 | cur_trb->generic.field[2] = 0; | |
556 | /* Preserve only the cycle bit of this TRB */ | |
28ccd296 | 557 | cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); |
522989a2 SS |
558 | /* Flip the cycle bit except on the first or last TRB */ |
559 | if (flip_cycle && cur_trb != cur_td->first_trb && | |
560 | cur_trb != cur_td->last_trb) | |
561 | cur_trb->generic.field[3] ^= | |
562 | cpu_to_le32(TRB_CYCLE); | |
28ccd296 ME |
563 | cur_trb->generic.field[3] |= cpu_to_le32( |
564 | TRB_TYPE(TRB_TR_NOOP)); | |
aa50b290 XR |
565 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
566 | "TRB to noop at offset 0x%llx", | |
79688acf SS |
567 | (unsigned long long) |
568 | xhci_trb_virt_to_dma(cur_seg, cur_trb)); | |
ae636747 SS |
569 | } |
570 | if (cur_trb == cur_td->last_trb) | |
571 | break; | |
572 | } | |
573 | } | |
574 | ||
575688e1 | 575 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
576 | struct xhci_virt_ep *ep) |
577 | { | |
578 | ep->ep_state &= ~EP_HALT_PENDING; | |
579 | /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the | |
580 | * timer is running on another CPU, we don't decrement stop_cmds_pending | |
581 | * (since we didn't successfully stop the watchdog timer). | |
582 | */ | |
583 | if (del_timer(&ep->stop_cmd_timer)) | |
584 | ep->stop_cmds_pending--; | |
585 | } | |
586 | ||
587 | /* Must be called with xhci->lock held in interrupt context */ | |
588 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, | |
07a37e9e | 589 | struct xhci_td *cur_td, int status) |
6f5165cf | 590 | { |
214f76f7 | 591 | struct usb_hcd *hcd; |
8e51adcc AX |
592 | struct urb *urb; |
593 | struct urb_priv *urb_priv; | |
6f5165cf | 594 | |
8e51adcc AX |
595 | urb = cur_td->urb; |
596 | urb_priv = urb->hcpriv; | |
597 | urb_priv->td_cnt++; | |
214f76f7 | 598 | hcd = bus_to_hcd(urb->dev->bus); |
6f5165cf | 599 | |
8e51adcc AX |
600 | /* Only giveback urb when this is the last td in urb */ |
601 | if (urb_priv->td_cnt == urb_priv->length) { | |
c41136b0 AX |
602 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
603 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
604 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
605 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
606 | usb_amd_quirk_pll_enable(); | |
607 | } | |
608 | } | |
8e51adcc | 609 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
8e51adcc AX |
610 | |
611 | spin_unlock(&xhci->lock); | |
612 | usb_hcd_giveback_urb(hcd, urb, status); | |
613 | xhci_urb_free_priv(xhci, urb_priv); | |
614 | spin_lock(&xhci->lock); | |
8e51adcc | 615 | } |
6f5165cf SS |
616 | } |
617 | ||
ae636747 SS |
618 | /* |
619 | * When we get a command completion for a Stop Endpoint Command, we need to | |
620 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
621 | * | |
622 | * 1. If the HW was in the middle of processing the TD that needs to be | |
623 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
624 | * in the TD with a Set Dequeue Pointer Command. | |
625 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
626 | * bit cleared) so that the HW will skip over them. | |
627 | */ | |
b8200c94 | 628 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 629 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 | 630 | { |
ae636747 SS |
631 | unsigned int ep_index; |
632 | struct xhci_ring *ep_ring; | |
63a0d9ab | 633 | struct xhci_virt_ep *ep; |
ae636747 | 634 | struct list_head *entry; |
326b4810 | 635 | struct xhci_td *cur_td = NULL; |
ae636747 SS |
636 | struct xhci_td *last_unlinked_td; |
637 | ||
c92bcfa7 | 638 | struct xhci_dequeue_state deq_state; |
ae636747 | 639 | |
bc752bde | 640 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
9ea1833e | 641 | if (!xhci->devs[slot_id]) |
be88fe4f AX |
642 | xhci_warn(xhci, "Stop endpoint command " |
643 | "completion for disabled slot %u\n", | |
644 | slot_id); | |
645 | return; | |
646 | } | |
647 | ||
ae636747 | 648 | memset(&deq_state, 0, sizeof(deq_state)); |
28ccd296 | 649 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
63a0d9ab | 650 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
ae636747 | 651 | |
678539cf | 652 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 653 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
0714a57c | 654 | ep->stopped_td = NULL; |
e9df17eb | 655 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 656 | return; |
678539cf | 657 | } |
ae636747 SS |
658 | |
659 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
660 | * We have the xHCI lock, so nothing can modify this list until we drop | |
661 | * it. We're also in the event handler, so we can't get re-interrupted | |
662 | * if another Stop Endpoint command completes | |
663 | */ | |
63a0d9ab | 664 | list_for_each(entry, &ep->cancelled_td_list) { |
ae636747 | 665 | cur_td = list_entry(entry, struct xhci_td, cancelled_td_list); |
aa50b290 XR |
666 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
667 | "Removing canceled TD starting at 0x%llx (dma).", | |
79688acf SS |
668 | (unsigned long long)xhci_trb_virt_to_dma( |
669 | cur_td->start_seg, cur_td->first_trb)); | |
e9df17eb SS |
670 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
671 | if (!ep_ring) { | |
672 | /* This shouldn't happen unless a driver is mucking | |
673 | * with the stream ID after submission. This will | |
674 | * leave the TD on the hardware ring, and the hardware | |
675 | * will try to execute it, and may access a buffer | |
676 | * that has already been freed. In the best case, the | |
677 | * hardware will execute it, and the event handler will | |
678 | * ignore the completion event for that TD, since it was | |
679 | * removed from the td_list for that endpoint. In | |
680 | * short, don't muck with the stream ID after | |
681 | * submission. | |
682 | */ | |
683 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
684 | "has invalid stream ID %u.\n", | |
685 | cur_td->urb, | |
686 | cur_td->urb->stream_id); | |
687 | goto remove_finished_td; | |
688 | } | |
ae636747 SS |
689 | /* |
690 | * If we stopped on the TD we need to cancel, then we have to | |
691 | * move the xHC endpoint ring dequeue pointer past this TD. | |
692 | */ | |
63a0d9ab | 693 | if (cur_td == ep->stopped_td) |
e9df17eb SS |
694 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
695 | cur_td->urb->stream_id, | |
696 | cur_td, &deq_state); | |
ae636747 | 697 | else |
522989a2 | 698 | td_to_noop(xhci, ep_ring, cur_td, false); |
e9df17eb | 699 | remove_finished_td: |
ae636747 SS |
700 | /* |
701 | * The event handler won't see a completion for this TD anymore, | |
702 | * so remove it from the endpoint ring's TD list. Keep it in | |
703 | * the cancelled TD list for URB completion later. | |
704 | */ | |
585df1d9 | 705 | list_del_init(&cur_td->td_list); |
ae636747 SS |
706 | } |
707 | last_unlinked_td = cur_td; | |
6f5165cf | 708 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
709 | |
710 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
711 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
1e3452e3 HG |
712 | xhci_queue_new_dequeue_state(xhci, slot_id, ep_index, |
713 | ep->stopped_td->urb->stream_id, &deq_state); | |
ac9d8fe7 | 714 | xhci_ring_cmd_db(xhci); |
ae636747 | 715 | } else { |
e9df17eb SS |
716 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
717 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 718 | } |
526867c3 | 719 | |
1f81b6d2 JW |
720 | /* Clear stopped_td if endpoint is not halted */ |
721 | if (!(ep->ep_state & EP_HALTED)) | |
526867c3 | 722 | ep->stopped_td = NULL; |
ae636747 SS |
723 | |
724 | /* | |
725 | * Drop the lock and complete the URBs in the cancelled TD list. | |
726 | * New TDs to be cancelled might be added to the end of the list before | |
727 | * we can complete all the URBs for the TDs we already unlinked. | |
728 | * So stop when we've completed the URB for the last TD we unlinked. | |
729 | */ | |
730 | do { | |
63a0d9ab | 731 | cur_td = list_entry(ep->cancelled_td_list.next, |
ae636747 | 732 | struct xhci_td, cancelled_td_list); |
585df1d9 | 733 | list_del_init(&cur_td->cancelled_td_list); |
ae636747 SS |
734 | |
735 | /* Clean up the cancelled URB */ | |
ae636747 SS |
736 | /* Doesn't matter what we pass for status, since the core will |
737 | * just overwrite it (because the URB has been unlinked). | |
738 | */ | |
07a37e9e | 739 | xhci_giveback_urb_in_irq(xhci, cur_td, 0); |
ae636747 | 740 | |
6f5165cf SS |
741 | /* Stop processing the cancelled list if the watchdog timer is |
742 | * running. | |
743 | */ | |
744 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
745 | return; | |
ae636747 SS |
746 | } while (cur_td != last_unlinked_td); |
747 | ||
748 | /* Return to the event handler with xhci->lock re-acquired */ | |
749 | } | |
750 | ||
50e8725e SS |
751 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
752 | { | |
753 | struct xhci_td *cur_td; | |
754 | ||
755 | while (!list_empty(&ring->td_list)) { | |
756 | cur_td = list_first_entry(&ring->td_list, | |
757 | struct xhci_td, td_list); | |
758 | list_del_init(&cur_td->td_list); | |
759 | if (!list_empty(&cur_td->cancelled_td_list)) | |
760 | list_del_init(&cur_td->cancelled_td_list); | |
761 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
762 | } | |
763 | } | |
764 | ||
765 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, | |
766 | int slot_id, int ep_index) | |
767 | { | |
768 | struct xhci_td *cur_td; | |
769 | struct xhci_virt_ep *ep; | |
770 | struct xhci_ring *ring; | |
771 | ||
772 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
21d0e51b SS |
773 | if ((ep->ep_state & EP_HAS_STREAMS) || |
774 | (ep->ep_state & EP_GETTING_NO_STREAMS)) { | |
775 | int stream_id; | |
776 | ||
777 | for (stream_id = 0; stream_id < ep->stream_info->num_streams; | |
778 | stream_id++) { | |
779 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
780 | "Killing URBs for slot ID %u, ep index %u, stream %u", | |
781 | slot_id, ep_index, stream_id + 1); | |
782 | xhci_kill_ring_urbs(xhci, | |
783 | ep->stream_info->stream_rings[stream_id]); | |
784 | } | |
785 | } else { | |
786 | ring = ep->ring; | |
787 | if (!ring) | |
788 | return; | |
789 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
790 | "Killing URBs for slot ID %u, ep index %u", | |
791 | slot_id, ep_index); | |
792 | xhci_kill_ring_urbs(xhci, ring); | |
793 | } | |
50e8725e SS |
794 | while (!list_empty(&ep->cancelled_td_list)) { |
795 | cur_td = list_first_entry(&ep->cancelled_td_list, | |
796 | struct xhci_td, cancelled_td_list); | |
797 | list_del_init(&cur_td->cancelled_td_list); | |
798 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
799 | } | |
800 | } | |
801 | ||
6f5165cf SS |
802 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
803 | * In this case, we assume the host controller is broken or dying or dead. The | |
804 | * host may still be completing some other events, so we have to be careful to | |
805 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
806 | * through xhci->state. | |
807 | * | |
808 | * The timer may also fire if the host takes a very long time to respond to the | |
809 | * command, and the stop endpoint command completion handler cannot delete the | |
810 | * timer before the timer function is called. Another endpoint cancellation may | |
811 | * sneak in before the timer function can grab the lock, and that may queue | |
812 | * another stop endpoint command and add the timer back. So we cannot use a | |
813 | * simple flag to say whether there is a pending stop endpoint command for a | |
814 | * particular endpoint. | |
815 | * | |
816 | * Instead we use a combination of that flag and a counter for the number of | |
817 | * pending stop endpoint commands. If the timer is the tail end of the last | |
818 | * stop endpoint command, and the endpoint's command is still pending, we assume | |
819 | * the host is dying. | |
820 | */ | |
821 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
822 | { | |
823 | struct xhci_hcd *xhci; | |
824 | struct xhci_virt_ep *ep; | |
6f5165cf | 825 | int ret, i, j; |
f43d6231 | 826 | unsigned long flags; |
6f5165cf SS |
827 | |
828 | ep = (struct xhci_virt_ep *) arg; | |
829 | xhci = ep->xhci; | |
830 | ||
f43d6231 | 831 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
832 | |
833 | ep->stop_cmds_pending--; | |
834 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
aa50b290 XR |
835 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
836 | "Stop EP timer ran, but another timer marked " | |
837 | "xHCI as DYING, exiting."); | |
f43d6231 | 838 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
839 | return; |
840 | } | |
841 | if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) { | |
aa50b290 XR |
842 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
843 | "Stop EP timer ran, but no command pending, " | |
844 | "exiting."); | |
f43d6231 | 845 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
846 | return; |
847 | } | |
848 | ||
849 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
850 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
851 | /* Oops, HC is dead or dying or at least not responding to the stop | |
852 | * endpoint command. | |
853 | */ | |
854 | xhci->xhc_state |= XHCI_STATE_DYING; | |
855 | /* Disable interrupts from the host controller and start halting it */ | |
856 | xhci_quiesce(xhci); | |
f43d6231 | 857 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
858 | |
859 | ret = xhci_halt(xhci); | |
860 | ||
f43d6231 | 861 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
862 | if (ret < 0) { |
863 | /* This is bad; the host is not responding to commands and it's | |
864 | * not allowing itself to be halted. At least interrupts are | |
ac04e6ff | 865 | * disabled. If we call usb_hc_died(), it will attempt to |
6f5165cf SS |
866 | * disconnect all device drivers under this host. Those |
867 | * disconnect() methods will wait for all URBs to be unlinked, | |
868 | * so we must complete them. | |
869 | */ | |
870 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
871 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
872 | /* We could turn all TDs on the rings to no-ops. This won't | |
873 | * help if the host has cached part of the ring, and is slow if | |
874 | * we want to preserve the cycle bit. Skip it and hope the host | |
875 | * doesn't touch the memory. | |
876 | */ | |
877 | } | |
878 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
879 | if (!xhci->devs[i]) | |
880 | continue; | |
50e8725e SS |
881 | for (j = 0; j < 31; j++) |
882 | xhci_kill_endpoint_urbs(xhci, i, j); | |
6f5165cf | 883 | } |
f43d6231 | 884 | spin_unlock_irqrestore(&xhci->lock, flags); |
aa50b290 XR |
885 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
886 | "Calling usb_hc_died()"); | |
f6ff0ac8 | 887 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); |
aa50b290 XR |
888 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
889 | "xHCI host controller is dead."); | |
6f5165cf SS |
890 | } |
891 | ||
b008df60 AX |
892 | |
893 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, | |
894 | struct xhci_virt_device *dev, | |
895 | struct xhci_ring *ep_ring, | |
896 | unsigned int ep_index) | |
897 | { | |
898 | union xhci_trb *dequeue_temp; | |
899 | int num_trbs_free_temp; | |
900 | bool revert = false; | |
901 | ||
902 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
903 | dequeue_temp = ep_ring->dequeue; | |
904 | ||
0d9f78a9 SS |
905 | /* If we get two back-to-back stalls, and the first stalled transfer |
906 | * ends just before a link TRB, the dequeue pointer will be left on | |
907 | * the link TRB by the code in the while loop. So we have to update | |
908 | * the dequeue pointer one segment further, or we'll jump off | |
909 | * the segment into la-la-land. | |
910 | */ | |
911 | if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) { | |
912 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
913 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
914 | } | |
915 | ||
b008df60 AX |
916 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
917 | /* We have more usable TRBs */ | |
918 | ep_ring->num_trbs_free++; | |
919 | ep_ring->dequeue++; | |
920 | if (last_trb(xhci, ep_ring, ep_ring->deq_seg, | |
921 | ep_ring->dequeue)) { | |
922 | if (ep_ring->dequeue == | |
923 | dev->eps[ep_index].queued_deq_ptr) | |
924 | break; | |
925 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
926 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
927 | } | |
928 | if (ep_ring->dequeue == dequeue_temp) { | |
929 | revert = true; | |
930 | break; | |
931 | } | |
932 | } | |
933 | ||
934 | if (revert) { | |
935 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
936 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
937 | } | |
938 | } | |
939 | ||
ae636747 SS |
940 | /* |
941 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
942 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
943 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
944 | * endpoint doorbell to restart the ring, but only if there aren't more | |
945 | * cancellations pending. | |
946 | */ | |
b8200c94 | 947 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 948 | union xhci_trb *trb, u32 cmd_comp_code) |
ae636747 | 949 | { |
ae636747 | 950 | unsigned int ep_index; |
e9df17eb | 951 | unsigned int stream_id; |
ae636747 SS |
952 | struct xhci_ring *ep_ring; |
953 | struct xhci_virt_device *dev; | |
9aad95e2 | 954 | struct xhci_virt_ep *ep; |
d115b048 JY |
955 | struct xhci_ep_ctx *ep_ctx; |
956 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 | 957 | |
28ccd296 ME |
958 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
959 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
ae636747 | 960 | dev = xhci->devs[slot_id]; |
9aad95e2 | 961 | ep = &dev->eps[ep_index]; |
e9df17eb SS |
962 | |
963 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
964 | if (!ep_ring) { | |
e587b8b2 | 965 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
e9df17eb SS |
966 | stream_id); |
967 | /* XXX: Harmless??? */ | |
968 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; | |
969 | return; | |
970 | } | |
971 | ||
d115b048 JY |
972 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
973 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
ae636747 | 974 | |
c69a0597 | 975 | if (cmd_comp_code != COMP_SUCCESS) { |
ae636747 SS |
976 | unsigned int ep_state; |
977 | unsigned int slot_state; | |
978 | ||
c69a0597 | 979 | switch (cmd_comp_code) { |
ae636747 | 980 | case COMP_TRB_ERR: |
e587b8b2 | 981 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
ae636747 SS |
982 | break; |
983 | case COMP_CTX_STATE: | |
e587b8b2 | 984 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
28ccd296 | 985 | ep_state = le32_to_cpu(ep_ctx->ep_info); |
ae636747 | 986 | ep_state &= EP_STATE_MASK; |
28ccd296 | 987 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 | 988 | slot_state = GET_SLOT_STATE(slot_state); |
aa50b290 XR |
989 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
990 | "Slot state = %u, EP state = %u", | |
ae636747 SS |
991 | slot_state, ep_state); |
992 | break; | |
993 | case COMP_EBADSLT: | |
e587b8b2 ON |
994 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
995 | slot_id); | |
ae636747 SS |
996 | break; |
997 | default: | |
e587b8b2 ON |
998 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
999 | cmd_comp_code); | |
ae636747 SS |
1000 | break; |
1001 | } | |
1002 | /* OK what do we do now? The endpoint state is hosed, and we | |
1003 | * should never get to this point if the synchronization between | |
1004 | * queueing, and endpoint state are correct. This might happen | |
1005 | * if the device gets disconnected after we've finished | |
1006 | * cancelling URBs, which might not be an error... | |
1007 | */ | |
1008 | } else { | |
9aad95e2 HG |
1009 | u64 deq; |
1010 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ | |
1011 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1012 | struct xhci_stream_ctx *ctx = | |
1013 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1014 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; | |
1015 | } else { | |
1016 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; | |
1017 | } | |
aa50b290 | 1018 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
9aad95e2 HG |
1019 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
1020 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, | |
1021 | ep->queued_deq_ptr) == deq) { | |
bf161e85 SS |
1022 | /* Update the ring's dequeue segment and dequeue pointer |
1023 | * to reflect the new position. | |
1024 | */ | |
b008df60 AX |
1025 | update_ring_for_set_deq_completion(xhci, dev, |
1026 | ep_ring, ep_index); | |
bf161e85 | 1027 | } else { |
e587b8b2 | 1028 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
bf161e85 | 1029 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
9aad95e2 | 1030 | ep->queued_deq_seg, ep->queued_deq_ptr); |
bf161e85 | 1031 | } |
ae636747 SS |
1032 | } |
1033 | ||
63a0d9ab | 1034 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
bf161e85 SS |
1035 | dev->eps[ep_index].queued_deq_seg = NULL; |
1036 | dev->eps[ep_index].queued_deq_ptr = NULL; | |
e9df17eb SS |
1037 | /* Restart any rings with pending URBs */ |
1038 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1039 | } |
1040 | ||
b8200c94 | 1041 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1042 | union xhci_trb *trb, u32 cmd_comp_code) |
a1587d97 | 1043 | { |
a1587d97 SS |
1044 | unsigned int ep_index; |
1045 | ||
28ccd296 | 1046 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
a1587d97 SS |
1047 | /* This command will only fail if the endpoint wasn't halted, |
1048 | * but we don't care. | |
1049 | */ | |
a0254324 | 1050 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
c69a0597 | 1051 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
a1587d97 | 1052 | |
ac9d8fe7 SS |
1053 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
1054 | * command complete before the endpoint can be used. Queue that here | |
1055 | * because the HW can't handle two commands being queued in a row. | |
1056 | */ | |
1057 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
ddba5cd0 MN |
1058 | struct xhci_command *command; |
1059 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
a0ee619f HG |
1060 | if (!command) { |
1061 | xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n"); | |
1062 | return; | |
1063 | } | |
4bdfe4c3 XR |
1064 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1065 | "Queueing configure endpoint command"); | |
ddba5cd0 | 1066 | xhci_queue_configure_endpoint(xhci, command, |
913a8a34 SS |
1067 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
1068 | false); | |
ac9d8fe7 SS |
1069 | xhci_ring_cmd_db(xhci); |
1070 | } else { | |
e9df17eb | 1071 | /* Clear our internal halted state and restart the ring(s) */ |
63a0d9ab | 1072 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
e9df17eb | 1073 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ac9d8fe7 | 1074 | } |
a1587d97 | 1075 | } |
ae636747 | 1076 | |
b244b431 XR |
1077 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
1078 | u32 cmd_comp_code) | |
1079 | { | |
1080 | if (cmd_comp_code == COMP_SUCCESS) | |
1081 | xhci->slot_id = slot_id; | |
1082 | else | |
1083 | xhci->slot_id = 0; | |
b244b431 XR |
1084 | } |
1085 | ||
6c02dd14 XR |
1086 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
1087 | { | |
1088 | struct xhci_virt_device *virt_dev; | |
1089 | ||
1090 | virt_dev = xhci->devs[slot_id]; | |
1091 | if (!virt_dev) | |
1092 | return; | |
1093 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) | |
1094 | /* Delete default control endpoint resources */ | |
1095 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); | |
1096 | xhci_free_virt_device(xhci, slot_id); | |
1097 | } | |
1098 | ||
6ed46d33 XR |
1099 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
1100 | struct xhci_event_cmd *event, u32 cmd_comp_code) | |
1101 | { | |
1102 | struct xhci_virt_device *virt_dev; | |
1103 | struct xhci_input_control_ctx *ctrl_ctx; | |
1104 | unsigned int ep_index; | |
1105 | unsigned int ep_state; | |
1106 | u32 add_flags, drop_flags; | |
1107 | ||
6ed46d33 XR |
1108 | /* |
1109 | * Configure endpoint commands can come from the USB core | |
1110 | * configuration or alt setting changes, or because the HW | |
1111 | * needed an extra configure endpoint command after a reset | |
1112 | * endpoint command or streams were being configured. | |
1113 | * If the command was for a halted endpoint, the xHCI driver | |
1114 | * is not waiting on the configure endpoint command. | |
1115 | */ | |
9ea1833e | 1116 | virt_dev = xhci->devs[slot_id]; |
6ed46d33 XR |
1117 | ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx); |
1118 | if (!ctrl_ctx) { | |
1119 | xhci_warn(xhci, "Could not get input context, bad type.\n"); | |
1120 | return; | |
1121 | } | |
1122 | ||
1123 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
1124 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
1125 | /* Input ctx add_flags are the endpoint index plus one */ | |
1126 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; | |
1127 | ||
1128 | /* A usb_set_interface() call directly after clearing a halted | |
1129 | * condition may race on this quirky hardware. Not worth | |
1130 | * worrying about, since this is prototype hardware. Not sure | |
1131 | * if this will work for streams, but streams support was | |
1132 | * untested on this prototype. | |
1133 | */ | |
1134 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
1135 | ep_index != (unsigned int) -1 && | |
1136 | add_flags - SLOT_FLAG == drop_flags) { | |
1137 | ep_state = virt_dev->eps[ep_index].ep_state; | |
1138 | if (!(ep_state & EP_HALTED)) | |
ddba5cd0 | 1139 | return; |
6ed46d33 XR |
1140 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1141 | "Completed config ep cmd - " | |
1142 | "last ep index = %d, state = %d", | |
1143 | ep_index, ep_state); | |
1144 | /* Clear internal halted state and restart ring(s) */ | |
1145 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; | |
1146 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
1147 | return; | |
1148 | } | |
6ed46d33 XR |
1149 | return; |
1150 | } | |
1151 | ||
f681321b XR |
1152 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, |
1153 | struct xhci_event_cmd *event) | |
1154 | { | |
f681321b | 1155 | xhci_dbg(xhci, "Completed reset device command.\n"); |
9ea1833e | 1156 | if (!xhci->devs[slot_id]) |
f681321b XR |
1157 | xhci_warn(xhci, "Reset device command completion " |
1158 | "for disabled slot %u\n", slot_id); | |
1159 | } | |
1160 | ||
2c070821 XR |
1161 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
1162 | struct xhci_event_cmd *event) | |
1163 | { | |
1164 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
1165 | xhci->error_bitmask |= 1 << 6; | |
1166 | return; | |
1167 | } | |
1168 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1169 | "NEC firmware version %2x.%02x", | |
1170 | NEC_FW_MAJOR(le32_to_cpu(event->status)), | |
1171 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
1172 | } | |
1173 | ||
9ea1833e | 1174 | static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) |
c9aa1a2d MN |
1175 | { |
1176 | list_del(&cmd->cmd_list); | |
9ea1833e MN |
1177 | |
1178 | if (cmd->completion) { | |
1179 | cmd->status = status; | |
1180 | complete(cmd->completion); | |
1181 | } else { | |
c9aa1a2d | 1182 | kfree(cmd); |
9ea1833e | 1183 | } |
c9aa1a2d MN |
1184 | } |
1185 | ||
1186 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci) | |
1187 | { | |
1188 | struct xhci_command *cur_cmd, *tmp_cmd; | |
1189 | list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) | |
9ea1833e | 1190 | xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT); |
c9aa1a2d MN |
1191 | } |
1192 | ||
c311e391 MN |
1193 | /* |
1194 | * Turn all commands on command ring with status set to "aborted" to no-op trbs. | |
1195 | * If there are other commands waiting then restart the ring and kick the timer. | |
1196 | * This must be called with command ring stopped and xhci->lock held. | |
1197 | */ | |
1198 | static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, | |
1199 | struct xhci_command *cur_cmd) | |
1200 | { | |
1201 | struct xhci_command *i_cmd, *tmp_cmd; | |
1202 | u32 cycle_state; | |
1203 | ||
1204 | /* Turn all aborted commands in list to no-ops, then restart */ | |
1205 | list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list, | |
1206 | cmd_list) { | |
1207 | ||
1208 | if (i_cmd->status != COMP_CMD_ABORT) | |
1209 | continue; | |
1210 | ||
1211 | i_cmd->status = COMP_CMD_STOP; | |
1212 | ||
1213 | xhci_dbg(xhci, "Turn aborted command %p to no-op\n", | |
1214 | i_cmd->command_trb); | |
1215 | /* get cycle state from the original cmd trb */ | |
1216 | cycle_state = le32_to_cpu( | |
1217 | i_cmd->command_trb->generic.field[3]) & TRB_CYCLE; | |
1218 | /* modify the command trb to no-op command */ | |
1219 | i_cmd->command_trb->generic.field[0] = 0; | |
1220 | i_cmd->command_trb->generic.field[1] = 0; | |
1221 | i_cmd->command_trb->generic.field[2] = 0; | |
1222 | i_cmd->command_trb->generic.field[3] = cpu_to_le32( | |
1223 | TRB_TYPE(TRB_CMD_NOOP) | cycle_state); | |
1224 | ||
1225 | /* | |
1226 | * caller waiting for completion is called when command | |
1227 | * completion event is received for these no-op commands | |
1228 | */ | |
1229 | } | |
1230 | ||
1231 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; | |
1232 | ||
1233 | /* ring command ring doorbell to restart the command ring */ | |
1234 | if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && | |
1235 | !(xhci->xhc_state & XHCI_STATE_DYING)) { | |
1236 | xhci->current_cmd = cur_cmd; | |
1237 | mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT); | |
1238 | xhci_ring_cmd_db(xhci); | |
1239 | } | |
1240 | return; | |
1241 | } | |
1242 | ||
1243 | ||
1244 | void xhci_handle_command_timeout(unsigned long data) | |
1245 | { | |
1246 | struct xhci_hcd *xhci; | |
1247 | int ret; | |
1248 | unsigned long flags; | |
1249 | u64 hw_ring_state; | |
1250 | struct xhci_command *cur_cmd = NULL; | |
1251 | xhci = (struct xhci_hcd *) data; | |
1252 | ||
1253 | /* mark this command to be cancelled */ | |
1254 | spin_lock_irqsave(&xhci->lock, flags); | |
1255 | if (xhci->current_cmd) { | |
1256 | cur_cmd = xhci->current_cmd; | |
1257 | cur_cmd->status = COMP_CMD_ABORT; | |
1258 | } | |
1259 | ||
1260 | ||
1261 | /* Make sure command ring is running before aborting it */ | |
1262 | hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | |
1263 | if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && | |
1264 | (hw_ring_state & CMD_RING_RUNNING)) { | |
1265 | ||
1266 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1267 | xhci_dbg(xhci, "Command timeout\n"); | |
1268 | ret = xhci_abort_cmd_ring(xhci); | |
1269 | if (unlikely(ret == -ESHUTDOWN)) { | |
1270 | xhci_err(xhci, "Abort command ring failed\n"); | |
1271 | xhci_cleanup_command_queue(xhci); | |
1272 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); | |
1273 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); | |
1274 | } | |
1275 | return; | |
1276 | } | |
1277 | /* command timeout on stopped ring, ring can't be aborted */ | |
1278 | xhci_dbg(xhci, "Command timeout on stopped ring\n"); | |
1279 | xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); | |
1280 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1281 | return; | |
1282 | } | |
1283 | ||
7f84eef0 SS |
1284 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1285 | struct xhci_event_cmd *event) | |
1286 | { | |
28ccd296 | 1287 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1288 | u64 cmd_dma; |
1289 | dma_addr_t cmd_dequeue_dma; | |
e7a79a1d | 1290 | u32 cmd_comp_code; |
9124b121 | 1291 | union xhci_trb *cmd_trb; |
c9aa1a2d | 1292 | struct xhci_command *cmd; |
b54fc46d | 1293 | u32 cmd_type; |
7f84eef0 | 1294 | |
28ccd296 | 1295 | cmd_dma = le64_to_cpu(event->cmd_trb); |
9124b121 | 1296 | cmd_trb = xhci->cmd_ring->dequeue; |
23e3be11 | 1297 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
9124b121 | 1298 | cmd_trb); |
7f84eef0 SS |
1299 | /* Is the command ring deq ptr out of sync with the deq seg ptr? */ |
1300 | if (cmd_dequeue_dma == 0) { | |
1301 | xhci->error_bitmask |= 1 << 4; | |
1302 | return; | |
1303 | } | |
1304 | /* Does the DMA address match our internal dequeue pointer address? */ | |
1305 | if (cmd_dma != (u64) cmd_dequeue_dma) { | |
1306 | xhci->error_bitmask |= 1 << 5; | |
1307 | return; | |
1308 | } | |
b63f4053 | 1309 | |
c9aa1a2d MN |
1310 | cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list); |
1311 | ||
1312 | if (cmd->command_trb != xhci->cmd_ring->dequeue) { | |
1313 | xhci_err(xhci, | |
1314 | "Command completion event does not match command\n"); | |
1315 | return; | |
1316 | } | |
c311e391 MN |
1317 | |
1318 | del_timer(&xhci->cmd_timer); | |
1319 | ||
9124b121 | 1320 | trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event); |
63a23b9a | 1321 | |
e7a79a1d | 1322 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
c311e391 MN |
1323 | |
1324 | /* If CMD ring stopped we own the trbs between enqueue and dequeue */ | |
1325 | if (cmd_comp_code == COMP_CMD_STOP) { | |
1326 | xhci_handle_stopped_cmd_ring(xhci, cmd); | |
1327 | return; | |
1328 | } | |
1329 | /* | |
1330 | * Host aborted the command ring, check if the current command was | |
1331 | * supposed to be aborted, otherwise continue normally. | |
1332 | * The command ring is stopped now, but the xHC will issue a Command | |
1333 | * Ring Stopped event which will cause us to restart it. | |
1334 | */ | |
1335 | if (cmd_comp_code == COMP_CMD_ABORT) { | |
1336 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
1337 | if (cmd->status == COMP_CMD_ABORT) | |
1338 | goto event_handled; | |
b63f4053 EF |
1339 | } |
1340 | ||
b54fc46d XR |
1341 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
1342 | switch (cmd_type) { | |
1343 | case TRB_ENABLE_SLOT: | |
e7a79a1d | 1344 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code); |
3ffbba95 | 1345 | break; |
b54fc46d | 1346 | case TRB_DISABLE_SLOT: |
6c02dd14 | 1347 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
3ffbba95 | 1348 | break; |
b54fc46d | 1349 | case TRB_CONFIG_EP: |
9ea1833e MN |
1350 | if (!cmd->completion) |
1351 | xhci_handle_cmd_config_ep(xhci, slot_id, event, | |
1352 | cmd_comp_code); | |
f94e0186 | 1353 | break; |
b54fc46d | 1354 | case TRB_EVAL_CONTEXT: |
2d3f1fac | 1355 | break; |
b54fc46d | 1356 | case TRB_ADDR_DEV: |
3ffbba95 | 1357 | break; |
b54fc46d | 1358 | case TRB_STOP_RING: |
b8200c94 XR |
1359 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1360 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
1361 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); | |
ae636747 | 1362 | break; |
b54fc46d | 1363 | case TRB_SET_DEQ: |
b8200c94 XR |
1364 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1365 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1366 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
ae636747 | 1367 | break; |
b54fc46d | 1368 | case TRB_CMD_NOOP: |
c311e391 MN |
1369 | /* Is this an aborted command turned to NO-OP? */ |
1370 | if (cmd->status == COMP_CMD_STOP) | |
1371 | cmd_comp_code = COMP_CMD_STOP; | |
7f84eef0 | 1372 | break; |
b54fc46d | 1373 | case TRB_RESET_EP: |
b8200c94 XR |
1374 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1375 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1376 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
a1587d97 | 1377 | break; |
b54fc46d | 1378 | case TRB_RESET_DEV: |
6fcfb0d6 MN |
1379 | /* SLOT_ID field in reset device cmd completion event TRB is 0. |
1380 | * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) | |
1381 | */ | |
1382 | slot_id = TRB_TO_SLOT_ID( | |
1383 | le32_to_cpu(cmd_trb->generic.field[3])); | |
f681321b | 1384 | xhci_handle_cmd_reset_dev(xhci, slot_id, event); |
2a8f82c4 | 1385 | break; |
b54fc46d | 1386 | case TRB_NEC_GET_FW: |
2c070821 | 1387 | xhci_handle_cmd_nec_get_fw(xhci, event); |
0238634d | 1388 | break; |
7f84eef0 SS |
1389 | default: |
1390 | /* Skip over unknown commands on the event ring */ | |
1391 | xhci->error_bitmask |= 1 << 6; | |
1392 | break; | |
1393 | } | |
c9aa1a2d | 1394 | |
c311e391 MN |
1395 | /* restart timer if this wasn't the last command */ |
1396 | if (cmd->cmd_list.next != &xhci->cmd_list) { | |
1397 | xhci->current_cmd = list_entry(cmd->cmd_list.next, | |
1398 | struct xhci_command, cmd_list); | |
1399 | mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT); | |
1400 | } | |
1401 | ||
1402 | event_handled: | |
9ea1833e | 1403 | xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); |
c9aa1a2d | 1404 | |
3b72fca0 | 1405 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1406 | } |
1407 | ||
0238634d SS |
1408 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1409 | union xhci_trb *event) | |
1410 | { | |
1411 | u32 trb_type; | |
1412 | ||
28ccd296 | 1413 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
0238634d SS |
1414 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1415 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1416 | handle_cmd_completion(xhci, &event->event_cmd); | |
1417 | } | |
1418 | ||
f6ff0ac8 SS |
1419 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
1420 | * port registers -- USB 3.0 and USB 2.0). | |
1421 | * | |
1422 | * Returns a zero-based port number, which is suitable for indexing into each of | |
1423 | * the split roothubs' port arrays and bus state arrays. | |
d0cd5d48 | 1424 | * Add one to it in order to call xhci_find_slot_id_by_port. |
f6ff0ac8 SS |
1425 | */ |
1426 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, | |
1427 | struct xhci_hcd *xhci, u32 port_id) | |
1428 | { | |
1429 | unsigned int i; | |
1430 | unsigned int num_similar_speed_ports = 0; | |
1431 | ||
1432 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], | |
1433 | * and usb2_ports are 0-based indexes. Count the number of similar | |
1434 | * speed ports, up to 1 port before this port. | |
1435 | */ | |
1436 | for (i = 0; i < (port_id - 1); i++) { | |
1437 | u8 port_speed = xhci->port_array[i]; | |
1438 | ||
1439 | /* | |
1440 | * Skip ports that don't have known speeds, or have duplicate | |
1441 | * Extended Capabilities port speed entries. | |
1442 | */ | |
22e04870 | 1443 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
1444 | continue; |
1445 | ||
1446 | /* | |
1447 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
1448 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
1449 | * matches the device speed, it's a similar speed port. | |
1450 | */ | |
1451 | if ((port_speed == 0x03) == (hcd->speed == HCD_USB3)) | |
1452 | num_similar_speed_ports++; | |
1453 | } | |
1454 | return num_similar_speed_ports; | |
1455 | } | |
1456 | ||
623bef9e SS |
1457 | static void handle_device_notification(struct xhci_hcd *xhci, |
1458 | union xhci_trb *event) | |
1459 | { | |
1460 | u32 slot_id; | |
4ee823b8 | 1461 | struct usb_device *udev; |
623bef9e | 1462 | |
7e76ad43 | 1463 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
4ee823b8 | 1464 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1465 | xhci_warn(xhci, "Device Notification event for " |
1466 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1467 | return; |
1468 | } | |
1469 | ||
1470 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1471 | slot_id); | |
1472 | udev = xhci->devs[slot_id]->udev; | |
1473 | if (udev && udev->parent) | |
1474 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1475 | } |
1476 | ||
0f2a7930 SS |
1477 | static void handle_port_status(struct xhci_hcd *xhci, |
1478 | union xhci_trb *event) | |
1479 | { | |
f6ff0ac8 | 1480 | struct usb_hcd *hcd; |
0f2a7930 | 1481 | u32 port_id; |
56192531 | 1482 | u32 temp, temp1; |
518e848e | 1483 | int max_ports; |
56192531 | 1484 | int slot_id; |
5308a91b | 1485 | unsigned int faked_port_index; |
f6ff0ac8 | 1486 | u8 major_revision; |
20b67cf5 | 1487 | struct xhci_bus_state *bus_state; |
28ccd296 | 1488 | __le32 __iomem **port_array; |
386139d7 | 1489 | bool bogus_port_status = false; |
0f2a7930 SS |
1490 | |
1491 | /* Port status change events always have a successful completion code */ | |
28ccd296 | 1492 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) { |
0f2a7930 SS |
1493 | xhci_warn(xhci, "WARN: xHC returned failed port status event\n"); |
1494 | xhci->error_bitmask |= 1 << 8; | |
1495 | } | |
28ccd296 | 1496 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
0f2a7930 SS |
1497 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
1498 | ||
518e848e SS |
1499 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1500 | if ((port_id <= 0) || (port_id > max_ports)) { | |
56192531 | 1501 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
09ce0c0c PC |
1502 | inc_deq(xhci, xhci->event_ring); |
1503 | return; | |
56192531 AX |
1504 | } |
1505 | ||
f6ff0ac8 SS |
1506 | /* Figure out which usb_hcd this port is attached to: |
1507 | * is it a USB 3.0 port or a USB 2.0/1.1 port? | |
1508 | */ | |
1509 | major_revision = xhci->port_array[port_id - 1]; | |
09ce0c0c PC |
1510 | |
1511 | /* Find the right roothub. */ | |
1512 | hcd = xhci_to_hcd(xhci); | |
1513 | if ((major_revision == 0x03) != (hcd->speed == HCD_USB3)) | |
1514 | hcd = xhci->shared_hcd; | |
1515 | ||
f6ff0ac8 SS |
1516 | if (major_revision == 0) { |
1517 | xhci_warn(xhci, "Event for port %u not in " | |
1518 | "Extended Capabilities, ignoring.\n", | |
1519 | port_id); | |
386139d7 | 1520 | bogus_port_status = true; |
f6ff0ac8 | 1521 | goto cleanup; |
5308a91b | 1522 | } |
22e04870 | 1523 | if (major_revision == DUPLICATE_ENTRY) { |
f6ff0ac8 SS |
1524 | xhci_warn(xhci, "Event for port %u duplicated in" |
1525 | "Extended Capabilities, ignoring.\n", | |
1526 | port_id); | |
386139d7 | 1527 | bogus_port_status = true; |
f6ff0ac8 SS |
1528 | goto cleanup; |
1529 | } | |
1530 | ||
1531 | /* | |
1532 | * Hardware port IDs reported by a Port Status Change Event include USB | |
1533 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a | |
1534 | * resume event, but we first need to translate the hardware port ID | |
1535 | * into the index into the ports on the correct split roothub, and the | |
1536 | * correct bus_state structure. | |
1537 | */ | |
f6ff0ac8 SS |
1538 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
1539 | if (hcd->speed == HCD_USB3) | |
1540 | port_array = xhci->usb3_ports; | |
1541 | else | |
1542 | port_array = xhci->usb2_ports; | |
1543 | /* Find the faked port hub number */ | |
1544 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, | |
1545 | port_id); | |
5308a91b | 1546 | |
b0ba9720 | 1547 | temp = readl(port_array[faked_port_index]); |
7111ebc9 | 1548 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1549 | xhci_dbg(xhci, "resume root hub\n"); |
1550 | usb_hcd_resume_root_hub(hcd); | |
1551 | } | |
1552 | ||
1553 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { | |
1554 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | |
1555 | ||
b0ba9720 | 1556 | temp1 = readl(&xhci->op_regs->command); |
56192531 AX |
1557 | if (!(temp1 & CMD_RUN)) { |
1558 | xhci_warn(xhci, "xHC is not running.\n"); | |
1559 | goto cleanup; | |
1560 | } | |
1561 | ||
1562 | if (DEV_SUPERSPEED(temp)) { | |
d93814cf | 1563 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1564 | /* Set a flag to say the port signaled remote wakeup, |
1565 | * so we can tell the difference between the end of | |
1566 | * device and host initiated resume. | |
1567 | */ | |
1568 | bus_state->port_remote_wakeup |= 1 << faked_port_index; | |
d93814cf SS |
1569 | xhci_test_and_clear_bit(xhci, port_array, |
1570 | faked_port_index, PORT_PLC); | |
c9682dff AX |
1571 | xhci_set_link_state(xhci, port_array, faked_port_index, |
1572 | XDEV_U0); | |
d93814cf SS |
1573 | /* Need to wait until the next link state change |
1574 | * indicates the device is actually in U0. | |
1575 | */ | |
1576 | bogus_port_status = true; | |
1577 | goto cleanup; | |
56192531 AX |
1578 | } else { |
1579 | xhci_dbg(xhci, "resume HS port %d\n", port_id); | |
f6ff0ac8 | 1580 | bus_state->resume_done[faked_port_index] = jiffies + |
56192531 | 1581 | msecs_to_jiffies(20); |
f370b996 | 1582 | set_bit(faked_port_index, &bus_state->resuming_ports); |
56192531 | 1583 | mod_timer(&hcd->rh_timer, |
f6ff0ac8 | 1584 | bus_state->resume_done[faked_port_index]); |
56192531 AX |
1585 | /* Do the rest in GetPortStatus */ |
1586 | } | |
1587 | } | |
d93814cf SS |
1588 | |
1589 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && | |
1590 | DEV_SUPERSPEED(temp)) { | |
1591 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); | |
4ee823b8 SS |
1592 | /* We've just brought the device into U0 through either the |
1593 | * Resume state after a device remote wakeup, or through the | |
1594 | * U3Exit state after a host-initiated resume. If it's a device | |
1595 | * initiated remote wake, don't pass up the link state change, | |
1596 | * so the roothub behavior is consistent with external | |
1597 | * USB 3.0 hub behavior. | |
1598 | */ | |
d93814cf SS |
1599 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1600 | faked_port_index + 1); | |
1601 | if (slot_id && xhci->devs[slot_id]) | |
1602 | xhci_ring_device(xhci, slot_id); | |
ba7b5c22 | 1603 | if (bus_state->port_remote_wakeup & (1 << faked_port_index)) { |
4ee823b8 SS |
1604 | bus_state->port_remote_wakeup &= |
1605 | ~(1 << faked_port_index); | |
1606 | xhci_test_and_clear_bit(xhci, port_array, | |
1607 | faked_port_index, PORT_PLC); | |
1608 | usb_wakeup_notification(hcd->self.root_hub, | |
1609 | faked_port_index + 1); | |
1610 | bogus_port_status = true; | |
1611 | goto cleanup; | |
1612 | } | |
d93814cf | 1613 | } |
56192531 | 1614 | |
8b3d4570 SS |
1615 | /* |
1616 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or | |
1617 | * RExit to a disconnect state). If so, let the the driver know it's | |
1618 | * out of the RExit state. | |
1619 | */ | |
1620 | if (!DEV_SUPERSPEED(temp) && | |
1621 | test_and_clear_bit(faked_port_index, | |
1622 | &bus_state->rexit_ports)) { | |
1623 | complete(&bus_state->rexit_done[faked_port_index]); | |
1624 | bogus_port_status = true; | |
1625 | goto cleanup; | |
1626 | } | |
1627 | ||
6fd45621 AX |
1628 | if (hcd->speed != HCD_USB3) |
1629 | xhci_test_and_clear_bit(xhci, port_array, faked_port_index, | |
1630 | PORT_PLC); | |
1631 | ||
56192531 | 1632 | cleanup: |
0f2a7930 | 1633 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 1634 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 1635 | |
386139d7 SS |
1636 | /* Don't make the USB core poll the roothub if we got a bad port status |
1637 | * change event. Besides, at that point we can't tell which roothub | |
1638 | * (USB 2.0 or USB 3.0) to kick. | |
1639 | */ | |
1640 | if (bogus_port_status) | |
1641 | return; | |
1642 | ||
c52804a4 SS |
1643 | /* |
1644 | * xHCI port-status-change events occur when the "or" of all the | |
1645 | * status-change bits in the portsc register changes from 0 to 1. | |
1646 | * New status changes won't cause an event if any other change | |
1647 | * bits are still set. When an event occurs, switch over to | |
1648 | * polling to avoid losing status changes. | |
1649 | */ | |
1650 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1651 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1652 | spin_unlock(&xhci->lock); |
1653 | /* Pass this up to the core */ | |
f6ff0ac8 | 1654 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
1655 | spin_lock(&xhci->lock); |
1656 | } | |
1657 | ||
d0e96f5a SS |
1658 | /* |
1659 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1660 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1661 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1662 | * returns 0. | |
1663 | */ | |
6648f29d | 1664 | struct xhci_segment *trb_in_td(struct xhci_segment *start_seg, |
d0e96f5a SS |
1665 | union xhci_trb *start_trb, |
1666 | union xhci_trb *end_trb, | |
1667 | dma_addr_t suspect_dma) | |
1668 | { | |
1669 | dma_addr_t start_dma; | |
1670 | dma_addr_t end_seg_dma; | |
1671 | dma_addr_t end_trb_dma; | |
1672 | struct xhci_segment *cur_seg; | |
1673 | ||
23e3be11 | 1674 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1675 | cur_seg = start_seg; |
1676 | ||
1677 | do { | |
2fa88daa | 1678 | if (start_dma == 0) |
326b4810 | 1679 | return NULL; |
ae636747 | 1680 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1681 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1682 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1683 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1684 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a SS |
1685 | |
1686 | if (end_trb_dma > 0) { | |
1687 | /* The end TRB is in this segment, so suspect should be here */ | |
1688 | if (start_dma <= end_trb_dma) { | |
1689 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1690 | return cur_seg; | |
1691 | } else { | |
1692 | /* Case for one segment with | |
1693 | * a TD wrapped around to the top | |
1694 | */ | |
1695 | if ((suspect_dma >= start_dma && | |
1696 | suspect_dma <= end_seg_dma) || | |
1697 | (suspect_dma >= cur_seg->dma && | |
1698 | suspect_dma <= end_trb_dma)) | |
1699 | return cur_seg; | |
1700 | } | |
326b4810 | 1701 | return NULL; |
d0e96f5a SS |
1702 | } else { |
1703 | /* Might still be somewhere in this segment */ | |
1704 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1705 | return cur_seg; | |
1706 | } | |
1707 | cur_seg = cur_seg->next; | |
23e3be11 | 1708 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1709 | } while (cur_seg != start_seg); |
d0e96f5a | 1710 | |
326b4810 | 1711 | return NULL; |
d0e96f5a SS |
1712 | } |
1713 | ||
bcef3fd5 SS |
1714 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1715 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1716 | unsigned int stream_id, |
bcef3fd5 SS |
1717 | struct xhci_td *td, union xhci_trb *event_trb) |
1718 | { | |
1719 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
ddba5cd0 MN |
1720 | struct xhci_command *command; |
1721 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
1722 | if (!command) | |
1723 | return; | |
1724 | ||
bcef3fd5 SS |
1725 | ep->ep_state |= EP_HALTED; |
1726 | ep->stopped_td = td; | |
e9df17eb | 1727 | ep->stopped_stream = stream_id; |
1624ae1c | 1728 | |
ddba5cd0 | 1729 | xhci_queue_reset_ep(xhci, command, slot_id, ep_index); |
bcef3fd5 | 1730 | xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index); |
1624ae1c SS |
1731 | |
1732 | ep->stopped_td = NULL; | |
5e5cf6fc | 1733 | ep->stopped_stream = 0; |
1624ae1c | 1734 | |
bcef3fd5 SS |
1735 | xhci_ring_cmd_db(xhci); |
1736 | } | |
1737 | ||
1738 | /* Check if an error has halted the endpoint ring. The class driver will | |
1739 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1740 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1741 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1742 | * Ring Dequeue Pointer command manually. | |
1743 | */ | |
1744 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1745 | struct xhci_ep_ctx *ep_ctx, | |
1746 | unsigned int trb_comp_code) | |
1747 | { | |
1748 | /* TRB completion codes that may require a manual halt cleanup */ | |
1749 | if (trb_comp_code == COMP_TX_ERR || | |
1750 | trb_comp_code == COMP_BABBLE || | |
1751 | trb_comp_code == COMP_SPLIT_ERR) | |
1752 | /* The 0.96 spec says a babbling control endpoint | |
1753 | * is not halted. The 0.96 spec says it is. Some HW | |
1754 | * claims to be 0.95 compliant, but it halts the control | |
1755 | * endpoint anyway. Check if a babble halted the | |
1756 | * endpoint. | |
1757 | */ | |
f5960b69 ME |
1758 | if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) == |
1759 | cpu_to_le32(EP_STATE_HALTED)) | |
bcef3fd5 SS |
1760 | return 1; |
1761 | ||
1762 | return 0; | |
1763 | } | |
1764 | ||
b45b5069 SS |
1765 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1766 | { | |
1767 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1768 | /* Vendor defined "informational" completion code, | |
1769 | * treat as not-an-error. | |
1770 | */ | |
1771 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1772 | trb_comp_code); | |
1773 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1774 | return 1; | |
1775 | } | |
1776 | return 0; | |
1777 | } | |
1778 | ||
4422da61 AX |
1779 | /* |
1780 | * Finish the td processing, remove the td from td list; | |
1781 | * Return 1 if the urb can be given back. | |
1782 | */ | |
1783 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1784 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1785 | struct xhci_virt_ep *ep, int *status, bool skip) | |
1786 | { | |
1787 | struct xhci_virt_device *xdev; | |
1788 | struct xhci_ring *ep_ring; | |
1789 | unsigned int slot_id; | |
1790 | int ep_index; | |
1791 | struct urb *urb = NULL; | |
1792 | struct xhci_ep_ctx *ep_ctx; | |
1793 | int ret = 0; | |
8e51adcc | 1794 | struct urb_priv *urb_priv; |
4422da61 AX |
1795 | u32 trb_comp_code; |
1796 | ||
28ccd296 | 1797 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
4422da61 | 1798 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1799 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1800 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
4422da61 | 1801 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1802 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
4422da61 AX |
1803 | |
1804 | if (skip) | |
1805 | goto td_cleanup; | |
1806 | ||
1807 | if (trb_comp_code == COMP_STOP_INVAL || | |
1808 | trb_comp_code == COMP_STOP) { | |
1809 | /* The Endpoint Stop Command completion will take care of any | |
1810 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1811 | * the ring dequeue pointer or take this TD off any lists yet. | |
1812 | */ | |
1813 | ep->stopped_td = td; | |
4422da61 AX |
1814 | return 0; |
1815 | } else { | |
1816 | if (trb_comp_code == COMP_STALL) { | |
1817 | /* The transfer is completed from the driver's | |
1818 | * perspective, but we need to issue a set dequeue | |
1819 | * command for this stalled endpoint to move the dequeue | |
1820 | * pointer past the TD. We can't do that here because | |
1821 | * the halt condition must be cleared first. Let the | |
1822 | * USB class driver clear the stall later. | |
1823 | */ | |
1824 | ep->stopped_td = td; | |
4422da61 AX |
1825 | ep->stopped_stream = ep_ring->stream_id; |
1826 | } else if (xhci_requires_manual_halt_cleanup(xhci, | |
1827 | ep_ctx, trb_comp_code)) { | |
1828 | /* Other types of errors halt the endpoint, but the | |
1829 | * class driver doesn't call usb_reset_endpoint() unless | |
1830 | * the error is -EPIPE. Clear the halted status in the | |
1831 | * xHCI hardware manually. | |
1832 | */ | |
1833 | xhci_cleanup_halted_endpoint(xhci, | |
1834 | slot_id, ep_index, ep_ring->stream_id, | |
1835 | td, event_trb); | |
1836 | } else { | |
1837 | /* Update ring dequeue pointer */ | |
1838 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
1839 | inc_deq(xhci, ep_ring); |
1840 | inc_deq(xhci, ep_ring); | |
4422da61 AX |
1841 | } |
1842 | ||
1843 | td_cleanup: | |
1844 | /* Clean up the endpoint's TD list */ | |
1845 | urb = td->urb; | |
8e51adcc | 1846 | urb_priv = urb->hcpriv; |
4422da61 AX |
1847 | |
1848 | /* Do one last check of the actual transfer length. | |
1849 | * If the host controller said we transferred more data than | |
1850 | * the buffer length, urb->actual_length will be a very big | |
1851 | * number (since it's unsigned). Play it safe and say we didn't | |
1852 | * transfer anything. | |
1853 | */ | |
1854 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1855 | xhci_warn(xhci, "URB transfer length is wrong, " | |
1856 | "xHC issue? req. len = %u, " | |
1857 | "act. len = %u\n", | |
1858 | urb->transfer_buffer_length, | |
1859 | urb->actual_length); | |
1860 | urb->actual_length = 0; | |
1861 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
1862 | *status = -EREMOTEIO; | |
1863 | else | |
1864 | *status = 0; | |
1865 | } | |
585df1d9 | 1866 | list_del_init(&td->td_list); |
4422da61 AX |
1867 | /* Was this TD slated to be cancelled but completed anyway? */ |
1868 | if (!list_empty(&td->cancelled_td_list)) | |
585df1d9 | 1869 | list_del_init(&td->cancelled_td_list); |
4422da61 | 1870 | |
8e51adcc AX |
1871 | urb_priv->td_cnt++; |
1872 | /* Giveback the urb when all the tds are completed */ | |
c41136b0 | 1873 | if (urb_priv->td_cnt == urb_priv->length) { |
8e51adcc | 1874 | ret = 1; |
c41136b0 AX |
1875 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { |
1876 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
1877 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs | |
1878 | == 0) { | |
1879 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
1880 | usb_amd_quirk_pll_enable(); | |
1881 | } | |
1882 | } | |
1883 | } | |
4422da61 AX |
1884 | } |
1885 | ||
1886 | return ret; | |
1887 | } | |
1888 | ||
8af56be1 AX |
1889 | /* |
1890 | * Process control tds, update urb status and actual_length. | |
1891 | */ | |
1892 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1893 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1894 | struct xhci_virt_ep *ep, int *status) | |
1895 | { | |
1896 | struct xhci_virt_device *xdev; | |
1897 | struct xhci_ring *ep_ring; | |
1898 | unsigned int slot_id; | |
1899 | int ep_index; | |
1900 | struct xhci_ep_ctx *ep_ctx; | |
1901 | u32 trb_comp_code; | |
1902 | ||
28ccd296 | 1903 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
8af56be1 | 1904 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1905 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1906 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
8af56be1 | 1907 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1908 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
8af56be1 | 1909 | |
8af56be1 AX |
1910 | switch (trb_comp_code) { |
1911 | case COMP_SUCCESS: | |
1912 | if (event_trb == ep_ring->dequeue) { | |
1913 | xhci_warn(xhci, "WARN: Success on ctrl setup TRB " | |
1914 | "without IOC set??\n"); | |
1915 | *status = -ESHUTDOWN; | |
1916 | } else if (event_trb != td->last_trb) { | |
1917 | xhci_warn(xhci, "WARN: Success on ctrl data TRB " | |
1918 | "without IOC set??\n"); | |
1919 | *status = -ESHUTDOWN; | |
1920 | } else { | |
8af56be1 AX |
1921 | *status = 0; |
1922 | } | |
1923 | break; | |
1924 | case COMP_SHORT_TX: | |
8af56be1 AX |
1925 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) |
1926 | *status = -EREMOTEIO; | |
1927 | else | |
1928 | *status = 0; | |
1929 | break; | |
3abeca99 SS |
1930 | case COMP_STOP_INVAL: |
1931 | case COMP_STOP: | |
1932 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
8af56be1 AX |
1933 | default: |
1934 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
1935 | ep_ctx, trb_comp_code)) | |
1936 | break; | |
1937 | xhci_dbg(xhci, "TRB error code %u, " | |
1938 | "halted endpoint index = %u\n", | |
1939 | trb_comp_code, ep_index); | |
1940 | /* else fall through */ | |
1941 | case COMP_STALL: | |
1942 | /* Did we transfer part of the data (middle) phase? */ | |
1943 | if (event_trb != ep_ring->dequeue && | |
1944 | event_trb != td->last_trb) | |
1945 | td->urb->actual_length = | |
1c11a172 VG |
1946 | td->urb->transfer_buffer_length - |
1947 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
8af56be1 AX |
1948 | else |
1949 | td->urb->actual_length = 0; | |
1950 | ||
1951 | xhci_cleanup_halted_endpoint(xhci, | |
1952 | slot_id, ep_index, 0, td, event_trb); | |
1953 | return finish_td(xhci, td, event_trb, event, ep, status, true); | |
1954 | } | |
1955 | /* | |
1956 | * Did we transfer any data, despite the errors that might have | |
1957 | * happened? I.e. did we get past the setup stage? | |
1958 | */ | |
1959 | if (event_trb != ep_ring->dequeue) { | |
1960 | /* The event was for the status stage */ | |
1961 | if (event_trb == td->last_trb) { | |
1962 | if (td->urb->actual_length != 0) { | |
1963 | /* Don't overwrite a previously set error code | |
1964 | */ | |
1965 | if ((*status == -EINPROGRESS || *status == 0) && | |
1966 | (td->urb->transfer_flags | |
1967 | & URB_SHORT_NOT_OK)) | |
1968 | /* Did we already see a short data | |
1969 | * stage? */ | |
1970 | *status = -EREMOTEIO; | |
1971 | } else { | |
1972 | td->urb->actual_length = | |
1973 | td->urb->transfer_buffer_length; | |
1974 | } | |
1975 | } else { | |
1976 | /* Maybe the event was for the data stage? */ | |
3abeca99 SS |
1977 | td->urb->actual_length = |
1978 | td->urb->transfer_buffer_length - | |
1c11a172 | 1979 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
3abeca99 SS |
1980 | xhci_dbg(xhci, "Waiting for status " |
1981 | "stage event\n"); | |
1982 | return 0; | |
8af56be1 AX |
1983 | } |
1984 | } | |
1985 | ||
1986 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
1987 | } | |
1988 | ||
04e51901 AX |
1989 | /* |
1990 | * Process isochronous tds, update urb packet status and actual_length. | |
1991 | */ | |
1992 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
1993 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
1994 | struct xhci_virt_ep *ep, int *status) | |
1995 | { | |
1996 | struct xhci_ring *ep_ring; | |
1997 | struct urb_priv *urb_priv; | |
1998 | int idx; | |
1999 | int len = 0; | |
04e51901 AX |
2000 | union xhci_trb *cur_trb; |
2001 | struct xhci_segment *cur_seg; | |
926008c9 | 2002 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 2003 | u32 trb_comp_code; |
926008c9 | 2004 | bool skip_td = false; |
04e51901 | 2005 | |
28ccd296 ME |
2006 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2007 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
04e51901 AX |
2008 | urb_priv = td->urb->hcpriv; |
2009 | idx = urb_priv->td_cnt; | |
926008c9 | 2010 | frame = &td->urb->iso_frame_desc[idx]; |
04e51901 | 2011 | |
926008c9 DT |
2012 | /* handle completion code */ |
2013 | switch (trb_comp_code) { | |
2014 | case COMP_SUCCESS: | |
1c11a172 | 2015 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) { |
1530bbc6 SS |
2016 | frame->status = 0; |
2017 | break; | |
2018 | } | |
2019 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) | |
2020 | trb_comp_code = COMP_SHORT_TX; | |
926008c9 DT |
2021 | case COMP_SHORT_TX: |
2022 | frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
2023 | -EREMOTEIO : 0; | |
2024 | break; | |
2025 | case COMP_BW_OVER: | |
2026 | frame->status = -ECOMM; | |
2027 | skip_td = true; | |
2028 | break; | |
2029 | case COMP_BUFF_OVER: | |
2030 | case COMP_BABBLE: | |
2031 | frame->status = -EOVERFLOW; | |
2032 | skip_td = true; | |
2033 | break; | |
f6ba6fe2 | 2034 | case COMP_DEV_ERR: |
926008c9 | 2035 | case COMP_STALL: |
9c745995 | 2036 | case COMP_TX_ERR: |
926008c9 DT |
2037 | frame->status = -EPROTO; |
2038 | skip_td = true; | |
2039 | break; | |
2040 | case COMP_STOP: | |
2041 | case COMP_STOP_INVAL: | |
2042 | break; | |
2043 | default: | |
2044 | frame->status = -1; | |
2045 | break; | |
04e51901 AX |
2046 | } |
2047 | ||
926008c9 DT |
2048 | if (trb_comp_code == COMP_SUCCESS || skip_td) { |
2049 | frame->actual_length = frame->length; | |
2050 | td->urb->actual_length += frame->length; | |
04e51901 AX |
2051 | } else { |
2052 | for (cur_trb = ep_ring->dequeue, | |
2053 | cur_seg = ep_ring->deq_seg; cur_trb != event_trb; | |
2054 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 ME |
2055 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
2056 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) | |
28ccd296 | 2057 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
04e51901 | 2058 | } |
28ccd296 | 2059 | len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1c11a172 | 2060 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
04e51901 AX |
2061 | |
2062 | if (trb_comp_code != COMP_STOP_INVAL) { | |
926008c9 | 2063 | frame->actual_length = len; |
04e51901 AX |
2064 | td->urb->actual_length += len; |
2065 | } | |
2066 | } | |
2067 | ||
04e51901 AX |
2068 | return finish_td(xhci, td, event_trb, event, ep, status, false); |
2069 | } | |
2070 | ||
926008c9 DT |
2071 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
2072 | struct xhci_transfer_event *event, | |
2073 | struct xhci_virt_ep *ep, int *status) | |
2074 | { | |
2075 | struct xhci_ring *ep_ring; | |
2076 | struct urb_priv *urb_priv; | |
2077 | struct usb_iso_packet_descriptor *frame; | |
2078 | int idx; | |
2079 | ||
f6975314 | 2080 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
926008c9 DT |
2081 | urb_priv = td->urb->hcpriv; |
2082 | idx = urb_priv->td_cnt; | |
2083 | frame = &td->urb->iso_frame_desc[idx]; | |
2084 | ||
b3df3f9c | 2085 | /* The transfer is partly done. */ |
926008c9 DT |
2086 | frame->status = -EXDEV; |
2087 | ||
2088 | /* calc actual length */ | |
2089 | frame->actual_length = 0; | |
2090 | ||
2091 | /* Update ring dequeue pointer */ | |
2092 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
2093 | inc_deq(xhci, ep_ring); |
2094 | inc_deq(xhci, ep_ring); | |
926008c9 DT |
2095 | |
2096 | return finish_td(xhci, td, NULL, event, ep, status, true); | |
2097 | } | |
2098 | ||
22405ed2 AX |
2099 | /* |
2100 | * Process bulk and interrupt tds, update urb status and actual_length. | |
2101 | */ | |
2102 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
2103 | union xhci_trb *event_trb, struct xhci_transfer_event *event, | |
2104 | struct xhci_virt_ep *ep, int *status) | |
2105 | { | |
2106 | struct xhci_ring *ep_ring; | |
2107 | union xhci_trb *cur_trb; | |
2108 | struct xhci_segment *cur_seg; | |
2109 | u32 trb_comp_code; | |
2110 | ||
28ccd296 ME |
2111 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2112 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
22405ed2 AX |
2113 | |
2114 | switch (trb_comp_code) { | |
2115 | case COMP_SUCCESS: | |
2116 | /* Double check that the HW transferred everything. */ | |
1530bbc6 | 2117 | if (event_trb != td->last_trb || |
1c11a172 | 2118 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
22405ed2 AX |
2119 | xhci_warn(xhci, "WARN Successful completion " |
2120 | "on short TX\n"); | |
2121 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2122 | *status = -EREMOTEIO; | |
2123 | else | |
2124 | *status = 0; | |
1530bbc6 SS |
2125 | if ((xhci->quirks & XHCI_TRUST_TX_LENGTH)) |
2126 | trb_comp_code = COMP_SHORT_TX; | |
22405ed2 | 2127 | } else { |
22405ed2 AX |
2128 | *status = 0; |
2129 | } | |
2130 | break; | |
2131 | case COMP_SHORT_TX: | |
2132 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2133 | *status = -EREMOTEIO; | |
2134 | else | |
2135 | *status = 0; | |
2136 | break; | |
2137 | default: | |
2138 | /* Others already handled above */ | |
2139 | break; | |
2140 | } | |
f444ff27 SS |
2141 | if (trb_comp_code == COMP_SHORT_TX) |
2142 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, " | |
2143 | "%d bytes untransferred\n", | |
2144 | td->urb->ep->desc.bEndpointAddress, | |
2145 | td->urb->transfer_buffer_length, | |
1c11a172 | 2146 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
22405ed2 AX |
2147 | /* Fast path - was this the last TRB in the TD for this URB? */ |
2148 | if (event_trb == td->last_trb) { | |
1c11a172 | 2149 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) { |
22405ed2 AX |
2150 | td->urb->actual_length = |
2151 | td->urb->transfer_buffer_length - | |
1c11a172 | 2152 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
22405ed2 AX |
2153 | if (td->urb->transfer_buffer_length < |
2154 | td->urb->actual_length) { | |
2155 | xhci_warn(xhci, "HC gave bad length " | |
2156 | "of %d bytes left\n", | |
1c11a172 | 2157 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len))); |
22405ed2 AX |
2158 | td->urb->actual_length = 0; |
2159 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2160 | *status = -EREMOTEIO; | |
2161 | else | |
2162 | *status = 0; | |
2163 | } | |
2164 | /* Don't overwrite a previously set error code */ | |
2165 | if (*status == -EINPROGRESS) { | |
2166 | if (td->urb->transfer_flags & URB_SHORT_NOT_OK) | |
2167 | *status = -EREMOTEIO; | |
2168 | else | |
2169 | *status = 0; | |
2170 | } | |
2171 | } else { | |
2172 | td->urb->actual_length = | |
2173 | td->urb->transfer_buffer_length; | |
2174 | /* Ignore a short packet completion if the | |
2175 | * untransferred length was zero. | |
2176 | */ | |
2177 | if (*status == -EREMOTEIO) | |
2178 | *status = 0; | |
2179 | } | |
2180 | } else { | |
2181 | /* Slow path - walk the list, starting from the dequeue | |
2182 | * pointer, to get the actual length transferred. | |
2183 | */ | |
2184 | td->urb->actual_length = 0; | |
2185 | for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg; | |
2186 | cur_trb != event_trb; | |
2187 | next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) { | |
f5960b69 ME |
2188 | if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) && |
2189 | !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) | |
22405ed2 | 2190 | td->urb->actual_length += |
28ccd296 | 2191 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])); |
22405ed2 AX |
2192 | } |
2193 | /* If the ring didn't stop on a Link or No-op TRB, add | |
2194 | * in the actual bytes transferred from the Normal TRB | |
2195 | */ | |
2196 | if (trb_comp_code != COMP_STOP_INVAL) | |
2197 | td->urb->actual_length += | |
28ccd296 | 2198 | TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) - |
1c11a172 | 2199 | EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
22405ed2 AX |
2200 | } |
2201 | ||
2202 | return finish_td(xhci, td, event_trb, event, ep, status, false); | |
2203 | } | |
2204 | ||
d0e96f5a SS |
2205 | /* |
2206 | * If this function returns an error condition, it means it got a Transfer | |
2207 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2208 | * At this point, the host controller is probably hosed and should be reset. | |
2209 | */ | |
2210 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2211 | struct xhci_transfer_event *event) | |
ed384bd3 FB |
2212 | __releases(&xhci->lock) |
2213 | __acquires(&xhci->lock) | |
d0e96f5a SS |
2214 | { |
2215 | struct xhci_virt_device *xdev; | |
63a0d9ab | 2216 | struct xhci_virt_ep *ep; |
d0e96f5a | 2217 | struct xhci_ring *ep_ring; |
82d1009f | 2218 | unsigned int slot_id; |
d0e96f5a | 2219 | int ep_index; |
326b4810 | 2220 | struct xhci_td *td = NULL; |
d0e96f5a SS |
2221 | dma_addr_t event_dma; |
2222 | struct xhci_segment *event_seg; | |
2223 | union xhci_trb *event_trb; | |
326b4810 | 2224 | struct urb *urb = NULL; |
d0e96f5a | 2225 | int status = -EINPROGRESS; |
8e51adcc | 2226 | struct urb_priv *urb_priv; |
d115b048 | 2227 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2228 | struct list_head *tmp; |
66d1eebc | 2229 | u32 trb_comp_code; |
4422da61 | 2230 | int ret = 0; |
c2d7b49f | 2231 | int td_num = 0; |
d0e96f5a | 2232 | |
28ccd296 | 2233 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
82d1009f | 2234 | xdev = xhci->devs[slot_id]; |
d0e96f5a SS |
2235 | if (!xdev) { |
2236 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n"); | |
9258c0b2 | 2237 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2238 | (unsigned long long) xhci_trb_virt_to_dma( |
2239 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2240 | xhci->event_ring->dequeue), |
2241 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2242 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2243 | le32_to_cpu(event->transfer_len), | |
2244 | le32_to_cpu(event->flags)); | |
2245 | xhci_dbg(xhci, "Event ring:\n"); | |
2246 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2247 | return -ENODEV; |
2248 | } | |
2249 | ||
2250 | /* Endpoint ID is 1 based, our index is zero based */ | |
28ccd296 | 2251 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
63a0d9ab | 2252 | ep = &xdev->eps[ep_index]; |
28ccd296 | 2253 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
d115b048 | 2254 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
986a92d4 | 2255 | if (!ep_ring || |
28ccd296 ME |
2256 | (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == |
2257 | EP_STATE_DISABLED) { | |
e9df17eb SS |
2258 | xhci_err(xhci, "ERROR Transfer event for disabled endpoint " |
2259 | "or incorrect stream ring\n"); | |
9258c0b2 | 2260 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2261 | (unsigned long long) xhci_trb_virt_to_dma( |
2262 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2263 | xhci->event_ring->dequeue), |
2264 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2265 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2266 | le32_to_cpu(event->transfer_len), | |
2267 | le32_to_cpu(event->flags)); | |
2268 | xhci_dbg(xhci, "Event ring:\n"); | |
2269 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2270 | return -ENODEV; |
2271 | } | |
2272 | ||
c2d7b49f AX |
2273 | /* Count current td numbers if ep->skip is set */ |
2274 | if (ep->skip) { | |
2275 | list_for_each(tmp, &ep_ring->td_list) | |
2276 | td_num++; | |
2277 | } | |
2278 | ||
28ccd296 ME |
2279 | event_dma = le64_to_cpu(event->buffer); |
2280 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
986a92d4 | 2281 | /* Look for common error cases */ |
66d1eebc | 2282 | switch (trb_comp_code) { |
b10de142 SS |
2283 | /* Skip codes that require special handling depending on |
2284 | * transfer type | |
2285 | */ | |
2286 | case COMP_SUCCESS: | |
1c11a172 | 2287 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
1530bbc6 SS |
2288 | break; |
2289 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2290 | trb_comp_code = COMP_SHORT_TX; | |
2291 | else | |
8202ce2e SS |
2292 | xhci_warn_ratelimited(xhci, |
2293 | "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n"); | |
b10de142 SS |
2294 | case COMP_SHORT_TX: |
2295 | break; | |
ae636747 SS |
2296 | case COMP_STOP: |
2297 | xhci_dbg(xhci, "Stopped on Transfer TRB\n"); | |
2298 | break; | |
2299 | case COMP_STOP_INVAL: | |
2300 | xhci_dbg(xhci, "Stopped on No-op or Link TRB\n"); | |
2301 | break; | |
b10de142 | 2302 | case COMP_STALL: |
2a9227a5 | 2303 | xhci_dbg(xhci, "Stalled endpoint\n"); |
63a0d9ab | 2304 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
2305 | status = -EPIPE; |
2306 | break; | |
2307 | case COMP_TRB_ERR: | |
2308 | xhci_warn(xhci, "WARN: TRB error on endpoint\n"); | |
2309 | status = -EILSEQ; | |
2310 | break; | |
ec74e403 | 2311 | case COMP_SPLIT_ERR: |
b10de142 | 2312 | case COMP_TX_ERR: |
2a9227a5 | 2313 | xhci_dbg(xhci, "Transfer error on endpoint\n"); |
b10de142 SS |
2314 | status = -EPROTO; |
2315 | break; | |
4a73143c | 2316 | case COMP_BABBLE: |
2a9227a5 | 2317 | xhci_dbg(xhci, "Babble error on endpoint\n"); |
4a73143c SS |
2318 | status = -EOVERFLOW; |
2319 | break; | |
b10de142 SS |
2320 | case COMP_DB_ERR: |
2321 | xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n"); | |
2322 | status = -ENOSR; | |
2323 | break; | |
986a92d4 AX |
2324 | case COMP_BW_OVER: |
2325 | xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n"); | |
2326 | break; | |
2327 | case COMP_BUFF_OVER: | |
2328 | xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n"); | |
2329 | break; | |
2330 | case COMP_UNDERRUN: | |
2331 | /* | |
2332 | * When the Isoch ring is empty, the xHC will generate | |
2333 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2334 | * Underrun Event for OUT Isoch endpoint. | |
2335 | */ | |
2336 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2337 | if (!list_empty(&ep_ring->td_list)) | |
2338 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2339 | "still with TDs queued?\n", | |
28ccd296 ME |
2340 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2341 | ep_index); | |
986a92d4 AX |
2342 | goto cleanup; |
2343 | case COMP_OVERRUN: | |
2344 | xhci_dbg(xhci, "overrun event on endpoint\n"); | |
2345 | if (!list_empty(&ep_ring->td_list)) | |
2346 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2347 | "still with TDs queued?\n", | |
28ccd296 ME |
2348 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2349 | ep_index); | |
986a92d4 | 2350 | goto cleanup; |
f6ba6fe2 AH |
2351 | case COMP_DEV_ERR: |
2352 | xhci_warn(xhci, "WARN: detect an incompatible device"); | |
2353 | status = -EPROTO; | |
2354 | break; | |
d18240db AX |
2355 | case COMP_MISSED_INT: |
2356 | /* | |
2357 | * When encounter missed service error, one or more isoc tds | |
2358 | * may be missed by xHC. | |
2359 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2360 | * short transfer when process the ep_ring next time. | |
2361 | */ | |
2362 | ep->skip = true; | |
2363 | xhci_dbg(xhci, "Miss service interval error, set skip flag\n"); | |
2364 | goto cleanup; | |
b10de142 | 2365 | default: |
b45b5069 | 2366 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2367 | status = 0; |
2368 | break; | |
2369 | } | |
986a92d4 AX |
2370 | xhci_warn(xhci, "ERROR Unknown event condition, HC probably " |
2371 | "busted\n"); | |
2372 | goto cleanup; | |
2373 | } | |
2374 | ||
d18240db AX |
2375 | do { |
2376 | /* This TRB should be in the TD at the head of this ring's | |
2377 | * TD list. | |
2378 | */ | |
2379 | if (list_empty(&ep_ring->td_list)) { | |
a83d6755 SS |
2380 | /* |
2381 | * A stopped endpoint may generate an extra completion | |
2382 | * event if the device was suspended. Don't print | |
2383 | * warnings. | |
2384 | */ | |
2385 | if (!(trb_comp_code == COMP_STOP || | |
2386 | trb_comp_code == COMP_STOP_INVAL)) { | |
2387 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", | |
2388 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), | |
2389 | ep_index); | |
2390 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", | |
2391 | (le32_to_cpu(event->flags) & | |
2392 | TRB_TYPE_BITMASK)>>10); | |
2393 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); | |
2394 | } | |
d18240db AX |
2395 | if (ep->skip) { |
2396 | ep->skip = false; | |
2397 | xhci_dbg(xhci, "td_list is empty while skip " | |
2398 | "flag set. Clear skip flag.\n"); | |
2399 | } | |
2400 | ret = 0; | |
2401 | goto cleanup; | |
2402 | } | |
986a92d4 | 2403 | |
c2d7b49f AX |
2404 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2405 | if (ep->skip && td_num == 0) { | |
2406 | ep->skip = false; | |
2407 | xhci_dbg(xhci, "All tds on the ep_ring skipped. " | |
2408 | "Clear skip flag.\n"); | |
2409 | ret = 0; | |
2410 | goto cleanup; | |
2411 | } | |
2412 | ||
d18240db | 2413 | td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list); |
c2d7b49f AX |
2414 | if (ep->skip) |
2415 | td_num--; | |
926008c9 | 2416 | |
d18240db AX |
2417 | /* Is this a TRB in the currently executing TD? */ |
2418 | event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue, | |
2419 | td->last_trb, event_dma); | |
e1cf486d AH |
2420 | |
2421 | /* | |
2422 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2423 | * is not in the current TD pointed by ep_ring->dequeue because | |
2424 | * that the hardware dequeue pointer still at the previous TRB | |
2425 | * of the current TD. The previous TRB maybe a Link TD or the | |
2426 | * last TRB of the previous TD. The command completion handle | |
2427 | * will take care the rest. | |
2428 | */ | |
9a548863 HG |
2429 | if (!event_seg && (trb_comp_code == COMP_STOP || |
2430 | trb_comp_code == COMP_STOP_INVAL)) { | |
e1cf486d AH |
2431 | ret = 0; |
2432 | goto cleanup; | |
2433 | } | |
2434 | ||
926008c9 DT |
2435 | if (!event_seg) { |
2436 | if (!ep->skip || | |
2437 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2438 | /* Some host controllers give a spurious |
2439 | * successful event after a short transfer. | |
2440 | * Ignore it. | |
2441 | */ | |
ddba5cd0 | 2442 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
ad808333 SS |
2443 | ep_ring->last_td_was_short) { |
2444 | ep_ring->last_td_was_short = false; | |
2445 | ret = 0; | |
2446 | goto cleanup; | |
2447 | } | |
926008c9 DT |
2448 | /* HC is busted, give up! */ |
2449 | xhci_err(xhci, | |
2450 | "ERROR Transfer event TRB DMA ptr not " | |
2451 | "part of current TD\n"); | |
2452 | return -ESHUTDOWN; | |
2453 | } | |
2454 | ||
2455 | ret = skip_isoc_td(xhci, td, event, ep, &status); | |
2456 | goto cleanup; | |
2457 | } | |
ad808333 SS |
2458 | if (trb_comp_code == COMP_SHORT_TX) |
2459 | ep_ring->last_td_was_short = true; | |
2460 | else | |
2461 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2462 | |
2463 | if (ep->skip) { | |
d18240db AX |
2464 | xhci_dbg(xhci, "Found td. Clear skip flag.\n"); |
2465 | ep->skip = false; | |
2466 | } | |
678539cf | 2467 | |
926008c9 DT |
2468 | event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / |
2469 | sizeof(*event_trb)]; | |
2470 | /* | |
2471 | * No-op TRB should not trigger interrupts. | |
2472 | * If event_trb is a no-op TRB, it means the | |
2473 | * corresponding TD has been cancelled. Just ignore | |
2474 | * the TD. | |
2475 | */ | |
f5960b69 | 2476 | if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) { |
926008c9 DT |
2477 | xhci_dbg(xhci, |
2478 | "event_trb is a no-op TRB. Skip it\n"); | |
2479 | goto cleanup; | |
d18240db | 2480 | } |
4422da61 | 2481 | |
d18240db AX |
2482 | /* Now update the urb's actual_length and give back to |
2483 | * the core | |
82d1009f | 2484 | */ |
d18240db AX |
2485 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
2486 | ret = process_ctrl_td(xhci, td, event_trb, event, ep, | |
2487 | &status); | |
04e51901 AX |
2488 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
2489 | ret = process_isoc_td(xhci, td, event_trb, event, ep, | |
2490 | &status); | |
d18240db AX |
2491 | else |
2492 | ret = process_bulk_intr_td(xhci, td, event_trb, event, | |
2493 | ep, &status); | |
2494 | ||
2495 | cleanup: | |
2496 | /* | |
2497 | * Do not update event ring dequeue pointer if ep->skip is set. | |
2498 | * Will roll back to continue process missed tds. | |
2499 | */ | |
2500 | if (trb_comp_code == COMP_MISSED_INT || !ep->skip) { | |
3b72fca0 | 2501 | inc_deq(xhci, xhci->event_ring); |
d18240db AX |
2502 | } |
2503 | ||
2504 | if (ret) { | |
2505 | urb = td->urb; | |
8e51adcc | 2506 | urb_priv = urb->hcpriv; |
d18240db AX |
2507 | /* Leave the TD around for the reset endpoint function |
2508 | * to use(but only if it's not a control endpoint, | |
2509 | * since we already queued the Set TR dequeue pointer | |
2510 | * command for stalled control endpoints). | |
2511 | */ | |
2512 | if (usb_endpoint_xfer_control(&urb->ep->desc) || | |
2513 | (trb_comp_code != COMP_STALL && | |
2514 | trb_comp_code != COMP_BABBLE)) | |
8e51adcc | 2515 | xhci_urb_free_priv(xhci, urb_priv); |
48c3375c AS |
2516 | else |
2517 | kfree(urb_priv); | |
d18240db | 2518 | |
214f76f7 | 2519 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
f444ff27 SS |
2520 | if ((urb->actual_length != urb->transfer_buffer_length && |
2521 | (urb->transfer_flags & | |
2522 | URB_SHORT_NOT_OK)) || | |
fd984d24 SS |
2523 | (status != 0 && |
2524 | !usb_endpoint_xfer_isoc(&urb->ep->desc))) | |
f444ff27 | 2525 | xhci_dbg(xhci, "Giveback URB %p, len = %d, " |
1949f9e2 | 2526 | "expected = %d, status = %d\n", |
f444ff27 SS |
2527 | urb, urb->actual_length, |
2528 | urb->transfer_buffer_length, | |
2529 | status); | |
d18240db | 2530 | spin_unlock(&xhci->lock); |
b3df3f9c SS |
2531 | /* EHCI, UHCI, and OHCI always unconditionally set the |
2532 | * urb->status of an isochronous endpoint to 0. | |
2533 | */ | |
2534 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
2535 | status = 0; | |
214f76f7 | 2536 | usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status); |
d18240db AX |
2537 | spin_lock(&xhci->lock); |
2538 | } | |
2539 | ||
2540 | /* | |
2541 | * If ep->skip is set, it means there are missed tds on the | |
2542 | * endpoint ring need to take care of. | |
2543 | * Process them as short transfer until reach the td pointed by | |
2544 | * the event. | |
2545 | */ | |
2546 | } while (ep->skip && trb_comp_code != COMP_MISSED_INT); | |
2547 | ||
d0e96f5a SS |
2548 | return 0; |
2549 | } | |
2550 | ||
0f2a7930 SS |
2551 | /* |
2552 | * This function handles all OS-owned events on the event ring. It may drop | |
2553 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2554 | * Returns >0 for "possibly more events to process" (caller should call again), |
2555 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2556 | */ |
9dee9a21 | 2557 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2558 | { |
2559 | union xhci_trb *event; | |
0f2a7930 | 2560 | int update_ptrs = 1; |
d0e96f5a | 2561 | int ret; |
7f84eef0 SS |
2562 | |
2563 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { | |
2564 | xhci->error_bitmask |= 1 << 1; | |
9dee9a21 | 2565 | return 0; |
7f84eef0 SS |
2566 | } |
2567 | ||
2568 | event = xhci->event_ring->dequeue; | |
2569 | /* Does the HC or OS own the TRB? */ | |
28ccd296 ME |
2570 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
2571 | xhci->event_ring->cycle_state) { | |
7f84eef0 | 2572 | xhci->error_bitmask |= 1 << 2; |
9dee9a21 | 2573 | return 0; |
7f84eef0 SS |
2574 | } |
2575 | ||
92a3da41 ME |
2576 | /* |
2577 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2578 | * speculative reads of the event's flags/data below. | |
2579 | */ | |
2580 | rmb(); | |
0f2a7930 | 2581 | /* FIXME: Handle more event types. */ |
28ccd296 | 2582 | switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) { |
7f84eef0 SS |
2583 | case TRB_TYPE(TRB_COMPLETION): |
2584 | handle_cmd_completion(xhci, &event->event_cmd); | |
2585 | break; | |
0f2a7930 SS |
2586 | case TRB_TYPE(TRB_PORT_STATUS): |
2587 | handle_port_status(xhci, event); | |
2588 | update_ptrs = 0; | |
2589 | break; | |
d0e96f5a SS |
2590 | case TRB_TYPE(TRB_TRANSFER): |
2591 | ret = handle_tx_event(xhci, &event->trans_event); | |
2592 | if (ret < 0) | |
2593 | xhci->error_bitmask |= 1 << 9; | |
2594 | else | |
2595 | update_ptrs = 0; | |
2596 | break; | |
623bef9e SS |
2597 | case TRB_TYPE(TRB_DEV_NOTE): |
2598 | handle_device_notification(xhci, event); | |
2599 | break; | |
7f84eef0 | 2600 | default: |
28ccd296 ME |
2601 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2602 | TRB_TYPE(48)) | |
0238634d SS |
2603 | handle_vendor_event(xhci, event); |
2604 | else | |
2605 | xhci->error_bitmask |= 1 << 3; | |
7f84eef0 | 2606 | } |
6f5165cf SS |
2607 | /* Any of the above functions may drop and re-acquire the lock, so check |
2608 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2609 | */ | |
2610 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2611 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2612 | "event handler.\n"); | |
9dee9a21 | 2613 | return 0; |
6f5165cf | 2614 | } |
7f84eef0 | 2615 | |
c06d68b8 SS |
2616 | if (update_ptrs) |
2617 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 2618 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 2619 | |
9dee9a21 ME |
2620 | /* Are there more items on the event ring? Caller will call us again to |
2621 | * check. | |
2622 | */ | |
2623 | return 1; | |
7f84eef0 | 2624 | } |
9032cd52 SS |
2625 | |
2626 | /* | |
2627 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2628 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2629 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2630 | */ | |
2631 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2632 | { | |
2633 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c21599a3 | 2634 | u32 status; |
bda53145 | 2635 | u64 temp_64; |
c06d68b8 SS |
2636 | union xhci_trb *event_ring_deq; |
2637 | dma_addr_t deq; | |
9032cd52 SS |
2638 | |
2639 | spin_lock(&xhci->lock); | |
9032cd52 | 2640 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
b0ba9720 | 2641 | status = readl(&xhci->op_regs->status); |
c21599a3 | 2642 | if (status == 0xffffffff) |
9032cd52 SS |
2643 | goto hw_died; |
2644 | ||
c21599a3 | 2645 | if (!(status & STS_EINT)) { |
9032cd52 | 2646 | spin_unlock(&xhci->lock); |
9032cd52 SS |
2647 | return IRQ_NONE; |
2648 | } | |
27e0dd4d | 2649 | if (status & STS_FATAL) { |
9032cd52 SS |
2650 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2651 | xhci_halt(xhci); | |
2652 | hw_died: | |
9032cd52 SS |
2653 | spin_unlock(&xhci->lock); |
2654 | return -ESHUTDOWN; | |
2655 | } | |
2656 | ||
bda53145 SS |
2657 | /* |
2658 | * Clear the op reg interrupt status first, | |
2659 | * so we can receive interrupts from other MSI-X interrupters. | |
2660 | * Write 1 to clear the interrupt status. | |
2661 | */ | |
27e0dd4d | 2662 | status |= STS_EINT; |
204b7793 | 2663 | writel(status, &xhci->op_regs->status); |
bda53145 SS |
2664 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
2665 | /* Clear the MSI-X event interrupt status */ | |
2666 | ||
cd70469d | 2667 | if (hcd->irq) { |
c21599a3 SS |
2668 | u32 irq_pending; |
2669 | /* Acknowledge the PCI interrupt */ | |
b0ba9720 | 2670 | irq_pending = readl(&xhci->ir_set->irq_pending); |
4e833c0b | 2671 | irq_pending |= IMAN_IP; |
204b7793 | 2672 | writel(irq_pending, &xhci->ir_set->irq_pending); |
c21599a3 | 2673 | } |
bda53145 | 2674 | |
c06d68b8 | 2675 | if (xhci->xhc_state & XHCI_STATE_DYING) { |
bda53145 SS |
2676 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2677 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2678 | /* Clear the event handler busy flag (RW1C); |
2679 | * the event ring should be empty. | |
bda53145 | 2680 | */ |
f7b2e403 | 2681 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
477632df SS |
2682 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
2683 | &xhci->ir_set->erst_dequeue); | |
c06d68b8 SS |
2684 | spin_unlock(&xhci->lock); |
2685 | ||
2686 | return IRQ_HANDLED; | |
2687 | } | |
2688 | ||
2689 | event_ring_deq = xhci->event_ring->dequeue; | |
2690 | /* FIXME this should be a delayed service routine | |
2691 | * that clears the EHB. | |
2692 | */ | |
9dee9a21 | 2693 | while (xhci_handle_event(xhci) > 0) {} |
bda53145 | 2694 | |
f7b2e403 | 2695 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2696 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2697 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2698 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2699 | xhci->event_ring->dequeue); | |
2700 | if (deq == 0) | |
2701 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2702 | "ring dequeue ptr.\n"); | |
2703 | /* Update HC event ring dequeue pointer */ | |
2704 | temp_64 &= ERST_PTR_MASK; | |
2705 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2706 | } | |
2707 | ||
2708 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2709 | temp_64 |= ERST_EHB; | |
477632df | 2710 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
c06d68b8 | 2711 | |
9032cd52 SS |
2712 | spin_unlock(&xhci->lock); |
2713 | ||
2714 | return IRQ_HANDLED; | |
2715 | } | |
2716 | ||
851ec164 | 2717 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
9032cd52 | 2718 | { |
968b822c | 2719 | return xhci_irq(hcd); |
9032cd52 | 2720 | } |
7f84eef0 | 2721 | |
d0e96f5a SS |
2722 | /**** Endpoint Ring Operations ****/ |
2723 | ||
7f84eef0 SS |
2724 | /* |
2725 | * Generic function for queueing a TRB on a ring. | |
2726 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2727 | * |
2728 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2729 | * prepare_transfer()? | |
7f84eef0 SS |
2730 | */ |
2731 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 2732 | bool more_trbs_coming, |
7f84eef0 SS |
2733 | u32 field1, u32 field2, u32 field3, u32 field4) |
2734 | { | |
2735 | struct xhci_generic_trb *trb; | |
2736 | ||
2737 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
2738 | trb->field[0] = cpu_to_le32(field1); |
2739 | trb->field[1] = cpu_to_le32(field2); | |
2740 | trb->field[2] = cpu_to_le32(field3); | |
2741 | trb->field[3] = cpu_to_le32(field4); | |
3b72fca0 | 2742 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
2743 | } |
2744 | ||
d0e96f5a SS |
2745 | /* |
2746 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2747 | * FIXME allocate segments if the ring is full. | |
2748 | */ | |
2749 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 2750 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 2751 | { |
8dfec614 AX |
2752 | unsigned int num_trbs_needed; |
2753 | ||
d0e96f5a | 2754 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
2755 | switch (ep_state) { |
2756 | case EP_STATE_DISABLED: | |
2757 | /* | |
2758 | * USB core changed config/interfaces without notifying us, | |
2759 | * or hardware is reporting the wrong state. | |
2760 | */ | |
2761 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2762 | return -ENOENT; | |
d0e96f5a | 2763 | case EP_STATE_ERROR: |
c92bcfa7 | 2764 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
2765 | /* FIXME event handling code for error needs to clear it */ |
2766 | /* XXX not sure if this should be -ENOENT or not */ | |
2767 | return -EINVAL; | |
c92bcfa7 SS |
2768 | case EP_STATE_HALTED: |
2769 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
2770 | case EP_STATE_STOPPED: |
2771 | case EP_STATE_RUNNING: | |
2772 | break; | |
2773 | default: | |
2774 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
2775 | /* | |
2776 | * FIXME issue Configure Endpoint command to try to get the HC | |
2777 | * back into a known state. | |
2778 | */ | |
2779 | return -EINVAL; | |
2780 | } | |
8dfec614 AX |
2781 | |
2782 | while (1) { | |
3d4b81ed SS |
2783 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
2784 | break; | |
8dfec614 AX |
2785 | |
2786 | if (ep_ring == xhci->cmd_ring) { | |
2787 | xhci_err(xhci, "Do not support expand command ring\n"); | |
2788 | return -ENOMEM; | |
2789 | } | |
2790 | ||
68ffb011 XR |
2791 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
2792 | "ERROR no room on ep ring, try ring expansion"); | |
8dfec614 AX |
2793 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
2794 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
2795 | mem_flags)) { | |
2796 | xhci_err(xhci, "Ring expansion failed\n"); | |
2797 | return -ENOMEM; | |
2798 | } | |
261fa12b | 2799 | } |
6c12db90 JY |
2800 | |
2801 | if (enqueue_is_link_trb(ep_ring)) { | |
2802 | struct xhci_ring *ring = ep_ring; | |
2803 | union xhci_trb *next; | |
6c12db90 | 2804 | |
6c12db90 JY |
2805 | next = ring->enqueue; |
2806 | ||
2807 | while (last_trb(xhci, ring, ring->enq_seg, next)) { | |
7e393a83 AX |
2808 | /* If we're not dealing with 0.95 hardware or isoc rings |
2809 | * on AMD 0.96 host, clear the chain bit. | |
6c12db90 | 2810 | */ |
3b72fca0 AX |
2811 | if (!xhci_link_trb_quirk(xhci) && |
2812 | !(ring->type == TYPE_ISOC && | |
2813 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
28ccd296 | 2814 | next->link.control &= cpu_to_le32(~TRB_CHAIN); |
6c12db90 | 2815 | else |
28ccd296 | 2816 | next->link.control |= cpu_to_le32(TRB_CHAIN); |
6c12db90 JY |
2817 | |
2818 | wmb(); | |
f5960b69 | 2819 | next->link.control ^= cpu_to_le32(TRB_CYCLE); |
6c12db90 JY |
2820 | |
2821 | /* Toggle the cycle bit after the last ring segment. */ | |
2822 | if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) { | |
2823 | ring->cycle_state = (ring->cycle_state ? 0 : 1); | |
6c12db90 JY |
2824 | } |
2825 | ring->enq_seg = ring->enq_seg->next; | |
2826 | ring->enqueue = ring->enq_seg->trbs; | |
2827 | next = ring->enqueue; | |
2828 | } | |
2829 | } | |
2830 | ||
d0e96f5a SS |
2831 | return 0; |
2832 | } | |
2833 | ||
23e3be11 | 2834 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
2835 | struct xhci_virt_device *xdev, |
2836 | unsigned int ep_index, | |
e9df17eb | 2837 | unsigned int stream_id, |
d0e96f5a SS |
2838 | unsigned int num_trbs, |
2839 | struct urb *urb, | |
8e51adcc | 2840 | unsigned int td_index, |
d0e96f5a SS |
2841 | gfp_t mem_flags) |
2842 | { | |
2843 | int ret; | |
8e51adcc AX |
2844 | struct urb_priv *urb_priv; |
2845 | struct xhci_td *td; | |
e9df17eb | 2846 | struct xhci_ring *ep_ring; |
d115b048 | 2847 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
2848 | |
2849 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
2850 | if (!ep_ring) { | |
2851 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
2852 | stream_id); | |
2853 | return -EINVAL; | |
2854 | } | |
2855 | ||
2856 | ret = prepare_ring(xhci, ep_ring, | |
28ccd296 | 2857 | le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3b72fca0 | 2858 | num_trbs, mem_flags); |
d0e96f5a SS |
2859 | if (ret) |
2860 | return ret; | |
d0e96f5a | 2861 | |
8e51adcc AX |
2862 | urb_priv = urb->hcpriv; |
2863 | td = urb_priv->td[td_index]; | |
2864 | ||
2865 | INIT_LIST_HEAD(&td->td_list); | |
2866 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
2867 | ||
2868 | if (td_index == 0) { | |
214f76f7 | 2869 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 2870 | if (unlikely(ret)) |
8e51adcc | 2871 | return ret; |
d0e96f5a SS |
2872 | } |
2873 | ||
8e51adcc | 2874 | td->urb = urb; |
d0e96f5a | 2875 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
2876 | list_add_tail(&td->td_list, &ep_ring->td_list); |
2877 | td->start_seg = ep_ring->enq_seg; | |
2878 | td->first_trb = ep_ring->enqueue; | |
2879 | ||
2880 | urb_priv->td[td_index] = td; | |
d0e96f5a SS |
2881 | |
2882 | return 0; | |
2883 | } | |
2884 | ||
23e3be11 | 2885 | static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb) |
8a96c052 SS |
2886 | { |
2887 | int num_sgs, num_trbs, running_total, temp, i; | |
2888 | struct scatterlist *sg; | |
2889 | ||
2890 | sg = NULL; | |
bc677d5b | 2891 | num_sgs = urb->num_mapped_sgs; |
8a96c052 SS |
2892 | temp = urb->transfer_buffer_length; |
2893 | ||
8a96c052 | 2894 | num_trbs = 0; |
910f8d0c | 2895 | for_each_sg(urb->sg, sg, num_sgs, i) { |
8a96c052 SS |
2896 | unsigned int len = sg_dma_len(sg); |
2897 | ||
2898 | /* Scatter gather list entries may cross 64KB boundaries */ | |
2899 | running_total = TRB_MAX_BUFF_SIZE - | |
a2490187 | 2900 | (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 2901 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
8a96c052 SS |
2902 | if (running_total != 0) |
2903 | num_trbs++; | |
2904 | ||
2905 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
bcd2fde0 | 2906 | while (running_total < sg_dma_len(sg) && running_total < temp) { |
8a96c052 SS |
2907 | num_trbs++; |
2908 | running_total += TRB_MAX_BUFF_SIZE; | |
2909 | } | |
8a96c052 SS |
2910 | len = min_t(int, len, temp); |
2911 | temp -= len; | |
2912 | if (temp == 0) | |
2913 | break; | |
2914 | } | |
8a96c052 SS |
2915 | return num_trbs; |
2916 | } | |
2917 | ||
23e3be11 | 2918 | static void check_trb_math(struct urb *urb, int num_trbs, int running_total) |
8a96c052 SS |
2919 | { |
2920 | if (num_trbs != 0) | |
a2490187 | 2921 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of " |
8a96c052 SS |
2922 | "TRBs, %d left\n", __func__, |
2923 | urb->ep->desc.bEndpointAddress, num_trbs); | |
2924 | if (running_total != urb->transfer_buffer_length) | |
a2490187 | 2925 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
2926 | "queued %#x (%d), asked for %#x (%d)\n", |
2927 | __func__, | |
2928 | urb->ep->desc.bEndpointAddress, | |
2929 | running_total, running_total, | |
2930 | urb->transfer_buffer_length, | |
2931 | urb->transfer_buffer_length); | |
2932 | } | |
2933 | ||
23e3be11 | 2934 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 2935 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 2936 | struct xhci_generic_trb *start_trb) |
8a96c052 | 2937 | { |
8a96c052 SS |
2938 | /* |
2939 | * Pass all the TRBs to the hardware at once and make sure this write | |
2940 | * isn't reordered. | |
2941 | */ | |
2942 | wmb(); | |
50f7b52a | 2943 | if (start_cycle) |
28ccd296 | 2944 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 2945 | else |
28ccd296 | 2946 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 2947 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
2948 | } |
2949 | ||
624defa1 SS |
2950 | /* |
2951 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
2952 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
2953 | * (comprised of sg list entries) can take several service intervals to | |
2954 | * transmit. | |
2955 | */ | |
2956 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
2957 | struct urb *urb, int slot_id, unsigned int ep_index) | |
2958 | { | |
2959 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, | |
2960 | xhci->devs[slot_id]->out_ctx, ep_index); | |
2961 | int xhci_interval; | |
2962 | int ep_interval; | |
2963 | ||
28ccd296 | 2964 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 SS |
2965 | ep_interval = urb->interval; |
2966 | /* Convert to microframes */ | |
2967 | if (urb->dev->speed == USB_SPEED_LOW || | |
2968 | urb->dev->speed == USB_SPEED_FULL) | |
2969 | ep_interval *= 8; | |
2970 | /* FIXME change this to a warning and a suggestion to use the new API | |
2971 | * to set the polling interval (once the API is added). | |
2972 | */ | |
2973 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
2974 | dev_dbg_ratelimited(&urb->dev->dev, |
2975 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
2976 | ep_interval, ep_interval == 1 ? "" : "s", | |
2977 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
624defa1 SS |
2978 | urb->interval = xhci_interval; |
2979 | /* Convert back to frames for LS/FS devices */ | |
2980 | if (urb->dev->speed == USB_SPEED_LOW || | |
2981 | urb->dev->speed == USB_SPEED_FULL) | |
2982 | urb->interval /= 8; | |
2983 | } | |
3fc8206d | 2984 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
2985 | } |
2986 | ||
04dd950d SS |
2987 | /* |
2988 | * The TD size is the number of bytes remaining in the TD (including this TRB), | |
2989 | * right shifted by 10. | |
2990 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
2991 | */ | |
2992 | static u32 xhci_td_remainder(unsigned int remainder) | |
2993 | { | |
2994 | u32 max = (1 << (21 - 17 + 1)) - 1; | |
2995 | ||
2996 | if ((remainder >> 10) >= max) | |
2997 | return max << 17; | |
2998 | else | |
2999 | return (remainder >> 10) << 17; | |
3000 | } | |
3001 | ||
4da6e6f2 | 3002 | /* |
4525c0a1 SS |
3003 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
3004 | * packets remaining in the TD (*not* including this TRB). | |
4da6e6f2 SS |
3005 | * |
3006 | * Total TD packet count = total_packet_count = | |
4525c0a1 | 3007 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
4da6e6f2 SS |
3008 | * |
3009 | * Packets transferred up to and including this TRB = packets_transferred = | |
3010 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
3011 | * | |
3012 | * TD size = total_packet_count - packets_transferred | |
3013 | * | |
3014 | * It must fit in bits 21:17, so it can't be bigger than 31. | |
4525c0a1 | 3015 | * The last TRB in a TD must have the TD size set to zero. |
4da6e6f2 | 3016 | */ |
4da6e6f2 | 3017 | static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len, |
4525c0a1 SS |
3018 | unsigned int total_packet_count, struct urb *urb, |
3019 | unsigned int num_trbs_left) | |
4da6e6f2 SS |
3020 | { |
3021 | int packets_transferred; | |
3022 | ||
48df4a6f | 3023 | /* One TRB with a zero-length data packet. */ |
4525c0a1 | 3024 | if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0)) |
48df4a6f SS |
3025 | return 0; |
3026 | ||
4da6e6f2 SS |
3027 | /* All the TRB queueing functions don't count the current TRB in |
3028 | * running_total. | |
3029 | */ | |
3030 | packets_transferred = (running_total + trb_buff_len) / | |
f18f8ed2 | 3031 | GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc)); |
4da6e6f2 | 3032 | |
4525c0a1 SS |
3033 | if ((total_packet_count - packets_transferred) > 31) |
3034 | return 31 << 17; | |
3035 | return (total_packet_count - packets_transferred) << 17; | |
4da6e6f2 SS |
3036 | } |
3037 | ||
23e3be11 | 3038 | static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
8a96c052 SS |
3039 | struct urb *urb, int slot_id, unsigned int ep_index) |
3040 | { | |
3041 | struct xhci_ring *ep_ring; | |
3042 | unsigned int num_trbs; | |
8e51adcc | 3043 | struct urb_priv *urb_priv; |
8a96c052 SS |
3044 | struct xhci_td *td; |
3045 | struct scatterlist *sg; | |
3046 | int num_sgs; | |
3047 | int trb_buff_len, this_sg_len, running_total; | |
4da6e6f2 | 3048 | unsigned int total_packet_count; |
8a96c052 SS |
3049 | bool first_trb; |
3050 | u64 addr; | |
6cc30d85 | 3051 | bool more_trbs_coming; |
8a96c052 SS |
3052 | |
3053 | struct xhci_generic_trb *start_trb; | |
3054 | int start_cycle; | |
3055 | ||
e9df17eb SS |
3056 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3057 | if (!ep_ring) | |
3058 | return -EINVAL; | |
3059 | ||
8a96c052 | 3060 | num_trbs = count_sg_trbs_needed(xhci, urb); |
bc677d5b | 3061 | num_sgs = urb->num_mapped_sgs; |
4525c0a1 | 3062 | total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length, |
29cc8897 | 3063 | usb_endpoint_maxp(&urb->ep->desc)); |
8a96c052 | 3064 | |
23e3be11 | 3065 | trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 3066 | ep_index, urb->stream_id, |
3b72fca0 | 3067 | num_trbs, urb, 0, mem_flags); |
8a96c052 SS |
3068 | if (trb_buff_len < 0) |
3069 | return trb_buff_len; | |
8e51adcc AX |
3070 | |
3071 | urb_priv = urb->hcpriv; | |
3072 | td = urb_priv->td[0]; | |
3073 | ||
8a96c052 SS |
3074 | /* |
3075 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3076 | * until we've finished creating all the other TRBs. The ring's cycle | |
3077 | * state may change as we enqueue the other TRBs, so save it too. | |
3078 | */ | |
3079 | start_trb = &ep_ring->enqueue->generic; | |
3080 | start_cycle = ep_ring->cycle_state; | |
3081 | ||
3082 | running_total = 0; | |
3083 | /* | |
3084 | * How much data is in the first TRB? | |
3085 | * | |
3086 | * There are three forces at work for TRB buffer pointers and lengths: | |
3087 | * 1. We don't want to walk off the end of this sg-list entry buffer. | |
3088 | * 2. The transfer length that the driver requested may be smaller than | |
3089 | * the amount of memory allocated for this scatter-gather list. | |
3090 | * 3. TRBs buffers can't cross 64KB boundaries. | |
3091 | */ | |
910f8d0c | 3092 | sg = urb->sg; |
8a96c052 SS |
3093 | addr = (u64) sg_dma_address(sg); |
3094 | this_sg_len = sg_dma_len(sg); | |
a2490187 | 3095 | trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1)); |
8a96c052 SS |
3096 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
3097 | if (trb_buff_len > urb->transfer_buffer_length) | |
3098 | trb_buff_len = urb->transfer_buffer_length; | |
8a96c052 SS |
3099 | |
3100 | first_trb = true; | |
3101 | /* Queue the first TRB, even if it's zero-length */ | |
3102 | do { | |
3103 | u32 field = 0; | |
f9dc68fe | 3104 | u32 length_field = 0; |
04dd950d | 3105 | u32 remainder = 0; |
8a96c052 SS |
3106 | |
3107 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 3108 | if (first_trb) { |
8a96c052 | 3109 | first_trb = false; |
50f7b52a AX |
3110 | if (start_cycle == 0) |
3111 | field |= 0x1; | |
3112 | } else | |
8a96c052 SS |
3113 | field |= ep_ring->cycle_state; |
3114 | ||
3115 | /* Chain all the TRBs together; clear the chain bit in the last | |
3116 | * TRB to indicate it's the last TRB in the chain. | |
3117 | */ | |
3118 | if (num_trbs > 1) { | |
3119 | field |= TRB_CHAIN; | |
3120 | } else { | |
3121 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
3122 | td->last_trb = ep_ring->enqueue; | |
3123 | field |= TRB_IOC; | |
3124 | } | |
af8b9e63 SS |
3125 | |
3126 | /* Only set interrupt on short packet for IN endpoints */ | |
3127 | if (usb_urb_dir_in(urb)) | |
3128 | field |= TRB_ISP; | |
3129 | ||
8a96c052 | 3130 | if (TRB_MAX_BUFF_SIZE - |
a2490187 | 3131 | (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) { |
8a96c052 SS |
3132 | xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n"); |
3133 | xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n", | |
3134 | (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1), | |
3135 | (unsigned int) addr + trb_buff_len); | |
3136 | } | |
4da6e6f2 SS |
3137 | |
3138 | /* Set the TRB length, TD size, and interrupter fields. */ | |
3139 | if (xhci->hci_version < 0x100) { | |
3140 | remainder = xhci_td_remainder( | |
3141 | urb->transfer_buffer_length - | |
3142 | running_total); | |
3143 | } else { | |
3144 | remainder = xhci_v1_0_td_remainder(running_total, | |
4525c0a1 SS |
3145 | trb_buff_len, total_packet_count, urb, |
3146 | num_trbs - 1); | |
4da6e6f2 | 3147 | } |
f9dc68fe | 3148 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 3149 | remainder | |
f9dc68fe | 3150 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3151 | |
6cc30d85 SS |
3152 | if (num_trbs > 1) |
3153 | more_trbs_coming = true; | |
3154 | else | |
3155 | more_trbs_coming = false; | |
3b72fca0 | 3156 | queue_trb(xhci, ep_ring, more_trbs_coming, |
8e595a5d SS |
3157 | lower_32_bits(addr), |
3158 | upper_32_bits(addr), | |
f9dc68fe | 3159 | length_field, |
af8b9e63 | 3160 | field | TRB_TYPE(TRB_NORMAL)); |
8a96c052 SS |
3161 | --num_trbs; |
3162 | running_total += trb_buff_len; | |
3163 | ||
3164 | /* Calculate length for next transfer -- | |
3165 | * Are we done queueing all the TRBs for this sg entry? | |
3166 | */ | |
3167 | this_sg_len -= trb_buff_len; | |
3168 | if (this_sg_len == 0) { | |
3169 | --num_sgs; | |
3170 | if (num_sgs == 0) | |
3171 | break; | |
3172 | sg = sg_next(sg); | |
3173 | addr = (u64) sg_dma_address(sg); | |
3174 | this_sg_len = sg_dma_len(sg); | |
3175 | } else { | |
3176 | addr += trb_buff_len; | |
3177 | } | |
3178 | ||
3179 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
a2490187 | 3180 | (addr & (TRB_MAX_BUFF_SIZE - 1)); |
8a96c052 SS |
3181 | trb_buff_len = min_t(int, trb_buff_len, this_sg_len); |
3182 | if (running_total + trb_buff_len > urb->transfer_buffer_length) | |
3183 | trb_buff_len = | |
3184 | urb->transfer_buffer_length - running_total; | |
3185 | } while (running_total < urb->transfer_buffer_length); | |
3186 | ||
3187 | check_trb_math(urb, num_trbs, running_total); | |
e9df17eb | 3188 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3189 | start_cycle, start_trb); |
8a96c052 SS |
3190 | return 0; |
3191 | } | |
3192 | ||
b10de142 | 3193 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
23e3be11 | 3194 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
b10de142 SS |
3195 | struct urb *urb, int slot_id, unsigned int ep_index) |
3196 | { | |
3197 | struct xhci_ring *ep_ring; | |
8e51adcc | 3198 | struct urb_priv *urb_priv; |
b10de142 SS |
3199 | struct xhci_td *td; |
3200 | int num_trbs; | |
3201 | struct xhci_generic_trb *start_trb; | |
3202 | bool first_trb; | |
6cc30d85 | 3203 | bool more_trbs_coming; |
b10de142 | 3204 | int start_cycle; |
f9dc68fe | 3205 | u32 field, length_field; |
b10de142 SS |
3206 | |
3207 | int running_total, trb_buff_len, ret; | |
4da6e6f2 | 3208 | unsigned int total_packet_count; |
b10de142 SS |
3209 | u64 addr; |
3210 | ||
ff9c895f | 3211 | if (urb->num_sgs) |
8a96c052 SS |
3212 | return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index); |
3213 | ||
e9df17eb SS |
3214 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3215 | if (!ep_ring) | |
3216 | return -EINVAL; | |
b10de142 SS |
3217 | |
3218 | num_trbs = 0; | |
3219 | /* How much data is (potentially) left before the 64KB boundary? */ | |
3220 | running_total = TRB_MAX_BUFF_SIZE - | |
a2490187 | 3221 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
5807795b | 3222 | running_total &= TRB_MAX_BUFF_SIZE - 1; |
b10de142 SS |
3223 | |
3224 | /* If there's some data on this 64KB chunk, or we have to send a | |
3225 | * zero-length transfer, we need at least one TRB | |
3226 | */ | |
3227 | if (running_total != 0 || urb->transfer_buffer_length == 0) | |
3228 | num_trbs++; | |
3229 | /* How many more 64KB chunks to transfer, how many more TRBs? */ | |
3230 | while (running_total < urb->transfer_buffer_length) { | |
3231 | num_trbs++; | |
3232 | running_total += TRB_MAX_BUFF_SIZE; | |
3233 | } | |
3234 | /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */ | |
3235 | ||
e9df17eb SS |
3236 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3237 | ep_index, urb->stream_id, | |
3b72fca0 | 3238 | num_trbs, urb, 0, mem_flags); |
b10de142 SS |
3239 | if (ret < 0) |
3240 | return ret; | |
3241 | ||
8e51adcc AX |
3242 | urb_priv = urb->hcpriv; |
3243 | td = urb_priv->td[0]; | |
3244 | ||
b10de142 SS |
3245 | /* |
3246 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3247 | * until we've finished creating all the other TRBs. The ring's cycle | |
3248 | * state may change as we enqueue the other TRBs, so save it too. | |
3249 | */ | |
3250 | start_trb = &ep_ring->enqueue->generic; | |
3251 | start_cycle = ep_ring->cycle_state; | |
3252 | ||
3253 | running_total = 0; | |
4525c0a1 | 3254 | total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length, |
29cc8897 | 3255 | usb_endpoint_maxp(&urb->ep->desc)); |
b10de142 SS |
3256 | /* How much data is in the first TRB? */ |
3257 | addr = (u64) urb->transfer_dma; | |
3258 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
a2490187 PZ |
3259 | (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1)); |
3260 | if (trb_buff_len > urb->transfer_buffer_length) | |
b10de142 SS |
3261 | trb_buff_len = urb->transfer_buffer_length; |
3262 | ||
3263 | first_trb = true; | |
3264 | ||
3265 | /* Queue the first TRB, even if it's zero-length */ | |
3266 | do { | |
04dd950d | 3267 | u32 remainder = 0; |
b10de142 SS |
3268 | field = 0; |
3269 | ||
3270 | /* Don't change the cycle bit of the first TRB until later */ | |
50f7b52a | 3271 | if (first_trb) { |
b10de142 | 3272 | first_trb = false; |
50f7b52a AX |
3273 | if (start_cycle == 0) |
3274 | field |= 0x1; | |
3275 | } else | |
b10de142 SS |
3276 | field |= ep_ring->cycle_state; |
3277 | ||
3278 | /* Chain all the TRBs together; clear the chain bit in the last | |
3279 | * TRB to indicate it's the last TRB in the chain. | |
3280 | */ | |
3281 | if (num_trbs > 1) { | |
3282 | field |= TRB_CHAIN; | |
3283 | } else { | |
3284 | /* FIXME - add check for ZERO_PACKET flag before this */ | |
3285 | td->last_trb = ep_ring->enqueue; | |
3286 | field |= TRB_IOC; | |
3287 | } | |
af8b9e63 SS |
3288 | |
3289 | /* Only set interrupt on short packet for IN endpoints */ | |
3290 | if (usb_urb_dir_in(urb)) | |
3291 | field |= TRB_ISP; | |
3292 | ||
4da6e6f2 SS |
3293 | /* Set the TRB length, TD size, and interrupter fields. */ |
3294 | if (xhci->hci_version < 0x100) { | |
3295 | remainder = xhci_td_remainder( | |
3296 | urb->transfer_buffer_length - | |
3297 | running_total); | |
3298 | } else { | |
3299 | remainder = xhci_v1_0_td_remainder(running_total, | |
4525c0a1 SS |
3300 | trb_buff_len, total_packet_count, urb, |
3301 | num_trbs - 1); | |
4da6e6f2 | 3302 | } |
f9dc68fe | 3303 | length_field = TRB_LEN(trb_buff_len) | |
04dd950d | 3304 | remainder | |
f9dc68fe | 3305 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3306 | |
6cc30d85 SS |
3307 | if (num_trbs > 1) |
3308 | more_trbs_coming = true; | |
3309 | else | |
3310 | more_trbs_coming = false; | |
3b72fca0 | 3311 | queue_trb(xhci, ep_ring, more_trbs_coming, |
8e595a5d SS |
3312 | lower_32_bits(addr), |
3313 | upper_32_bits(addr), | |
f9dc68fe | 3314 | length_field, |
af8b9e63 | 3315 | field | TRB_TYPE(TRB_NORMAL)); |
b10de142 SS |
3316 | --num_trbs; |
3317 | running_total += trb_buff_len; | |
3318 | ||
3319 | /* Calculate length for next transfer */ | |
3320 | addr += trb_buff_len; | |
3321 | trb_buff_len = urb->transfer_buffer_length - running_total; | |
3322 | if (trb_buff_len > TRB_MAX_BUFF_SIZE) | |
3323 | trb_buff_len = TRB_MAX_BUFF_SIZE; | |
3324 | } while (running_total < urb->transfer_buffer_length); | |
3325 | ||
8a96c052 | 3326 | check_trb_math(urb, num_trbs, running_total); |
e9df17eb | 3327 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3328 | start_cycle, start_trb); |
b10de142 SS |
3329 | return 0; |
3330 | } | |
3331 | ||
d0e96f5a | 3332 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3333 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3334 | struct urb *urb, int slot_id, unsigned int ep_index) |
3335 | { | |
3336 | struct xhci_ring *ep_ring; | |
3337 | int num_trbs; | |
3338 | int ret; | |
3339 | struct usb_ctrlrequest *setup; | |
3340 | struct xhci_generic_trb *start_trb; | |
3341 | int start_cycle; | |
f9dc68fe | 3342 | u32 field, length_field; |
8e51adcc | 3343 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3344 | struct xhci_td *td; |
3345 | ||
e9df17eb SS |
3346 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3347 | if (!ep_ring) | |
3348 | return -EINVAL; | |
d0e96f5a SS |
3349 | |
3350 | /* | |
3351 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3352 | * DMA address. | |
3353 | */ | |
3354 | if (!urb->setup_packet) | |
3355 | return -EINVAL; | |
3356 | ||
d0e96f5a SS |
3357 | /* 1 TRB for setup, 1 for status */ |
3358 | num_trbs = 2; | |
3359 | /* | |
3360 | * Don't need to check if we need additional event data and normal TRBs, | |
3361 | * since data in control transfers will never get bigger than 16MB | |
3362 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3363 | */ | |
3364 | if (urb->transfer_buffer_length > 0) | |
3365 | num_trbs++; | |
e9df17eb SS |
3366 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3367 | ep_index, urb->stream_id, | |
3b72fca0 | 3368 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3369 | if (ret < 0) |
3370 | return ret; | |
3371 | ||
8e51adcc AX |
3372 | urb_priv = urb->hcpriv; |
3373 | td = urb_priv->td[0]; | |
3374 | ||
d0e96f5a SS |
3375 | /* |
3376 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3377 | * until we've finished creating all the other TRBs. The ring's cycle | |
3378 | * state may change as we enqueue the other TRBs, so save it too. | |
3379 | */ | |
3380 | start_trb = &ep_ring->enqueue->generic; | |
3381 | start_cycle = ep_ring->cycle_state; | |
3382 | ||
3383 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3384 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3385 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3386 | field = 0; |
3387 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3388 | if (start_cycle == 0) | |
3389 | field |= 0x1; | |
b83cdc8f AX |
3390 | |
3391 | /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ | |
3392 | if (xhci->hci_version == 0x100) { | |
3393 | if (urb->transfer_buffer_length > 0) { | |
3394 | if (setup->bRequestType & USB_DIR_IN) | |
3395 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3396 | else | |
3397 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3398 | } | |
3399 | } | |
3400 | ||
3b72fca0 | 3401 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3402 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3403 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3404 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3405 | /* Immediate data in pointer */ | |
3406 | field); | |
d0e96f5a SS |
3407 | |
3408 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3409 | /* Only set interrupt on short packet for IN endpoints */ |
3410 | if (usb_urb_dir_in(urb)) | |
3411 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3412 | else | |
3413 | field = TRB_TYPE(TRB_DATA); | |
3414 | ||
f9dc68fe | 3415 | length_field = TRB_LEN(urb->transfer_buffer_length) | |
04dd950d | 3416 | xhci_td_remainder(urb->transfer_buffer_length) | |
f9dc68fe | 3417 | TRB_INTR_TARGET(0); |
d0e96f5a SS |
3418 | if (urb->transfer_buffer_length > 0) { |
3419 | if (setup->bRequestType & USB_DIR_IN) | |
3420 | field |= TRB_DIR_IN; | |
3b72fca0 | 3421 | queue_trb(xhci, ep_ring, true, |
d0e96f5a SS |
3422 | lower_32_bits(urb->transfer_dma), |
3423 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 3424 | length_field, |
af8b9e63 | 3425 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3426 | } |
3427 | ||
3428 | /* Save the DMA address of the last TRB in the TD */ | |
3429 | td->last_trb = ep_ring->enqueue; | |
3430 | ||
3431 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3432 | /* If the device sent data, the status stage is an OUT transfer */ | |
3433 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3434 | field = 0; | |
3435 | else | |
3436 | field = TRB_DIR_IN; | |
3b72fca0 | 3437 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3438 | 0, |
3439 | 0, | |
3440 | TRB_INTR_TARGET(0), | |
3441 | /* Event on completion */ | |
3442 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3443 | ||
e9df17eb | 3444 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3445 | start_cycle, start_trb); |
d0e96f5a SS |
3446 | return 0; |
3447 | } | |
3448 | ||
04e51901 AX |
3449 | static int count_isoc_trbs_needed(struct xhci_hcd *xhci, |
3450 | struct urb *urb, int i) | |
3451 | { | |
3452 | int num_trbs = 0; | |
48df4a6f | 3453 | u64 addr, td_len; |
04e51901 AX |
3454 | |
3455 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
3456 | td_len = urb->iso_frame_desc[i].length; | |
3457 | ||
48df4a6f SS |
3458 | num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)), |
3459 | TRB_MAX_BUFF_SIZE); | |
3460 | if (num_trbs == 0) | |
04e51901 | 3461 | num_trbs++; |
04e51901 AX |
3462 | |
3463 | return num_trbs; | |
3464 | } | |
3465 | ||
5cd43e33 SS |
3466 | /* |
3467 | * The transfer burst count field of the isochronous TRB defines the number of | |
3468 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3469 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3470 | * This field is zero based, meaning a value of zero in the field means one | |
3471 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3472 | * zero. Only xHCI 1.0 host controllers support this field. | |
3473 | */ | |
3474 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
3475 | struct usb_device *udev, | |
3476 | struct urb *urb, unsigned int total_packet_count) | |
3477 | { | |
3478 | unsigned int max_burst; | |
3479 | ||
3480 | if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER) | |
3481 | return 0; | |
3482 | ||
3483 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3213b151 | 3484 | return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; |
5cd43e33 SS |
3485 | } |
3486 | ||
b61d378f SS |
3487 | /* |
3488 | * Returns the number of packets in the last "burst" of packets. This field is | |
3489 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3490 | * the last burst packet count is equal to the total number of packets in the | |
3491 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3492 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3493 | * contain 1 to (bMaxBurst + 1) packets. | |
3494 | */ | |
3495 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
3496 | struct usb_device *udev, | |
3497 | struct urb *urb, unsigned int total_packet_count) | |
3498 | { | |
3499 | unsigned int max_burst; | |
3500 | unsigned int residue; | |
3501 | ||
3502 | if (xhci->hci_version < 0x100) | |
3503 | return 0; | |
3504 | ||
3505 | switch (udev->speed) { | |
3506 | case USB_SPEED_SUPER: | |
3507 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ | |
3508 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3509 | residue = total_packet_count % (max_burst + 1); | |
3510 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3511 | * number of packets, but the TLBPC field is zero-based. | |
3512 | */ | |
3513 | if (residue == 0) | |
3514 | return max_burst; | |
3515 | return residue - 1; | |
3516 | default: | |
3517 | if (total_packet_count == 0) | |
3518 | return 0; | |
3519 | return total_packet_count - 1; | |
3520 | } | |
3521 | } | |
3522 | ||
04e51901 AX |
3523 | /* This is for isoc transfer */ |
3524 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3525 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3526 | { | |
3527 | struct xhci_ring *ep_ring; | |
3528 | struct urb_priv *urb_priv; | |
3529 | struct xhci_td *td; | |
3530 | int num_tds, trbs_per_td; | |
3531 | struct xhci_generic_trb *start_trb; | |
3532 | bool first_trb; | |
3533 | int start_cycle; | |
3534 | u32 field, length_field; | |
3535 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
3536 | u64 start_addr, addr; | |
3537 | int i, j; | |
47cbf692 | 3538 | bool more_trbs_coming; |
04e51901 AX |
3539 | |
3540 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; | |
3541 | ||
3542 | num_tds = urb->number_of_packets; | |
3543 | if (num_tds < 1) { | |
3544 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
3545 | return -EINVAL; | |
3546 | } | |
3547 | ||
04e51901 AX |
3548 | start_addr = (u64) urb->transfer_dma; |
3549 | start_trb = &ep_ring->enqueue->generic; | |
3550 | start_cycle = ep_ring->cycle_state; | |
3551 | ||
522989a2 | 3552 | urb_priv = urb->hcpriv; |
04e51901 AX |
3553 | /* Queue the first TRB, even if it's zero-length */ |
3554 | for (i = 0; i < num_tds; i++) { | |
4da6e6f2 | 3555 | unsigned int total_packet_count; |
5cd43e33 | 3556 | unsigned int burst_count; |
b61d378f | 3557 | unsigned int residue; |
04e51901 | 3558 | |
4da6e6f2 | 3559 | first_trb = true; |
04e51901 AX |
3560 | running_total = 0; |
3561 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
3562 | td_len = urb->iso_frame_desc[i].length; | |
3563 | td_remain_len = td_len; | |
4525c0a1 | 3564 | total_packet_count = DIV_ROUND_UP(td_len, |
f18f8ed2 SS |
3565 | GET_MAX_PACKET( |
3566 | usb_endpoint_maxp(&urb->ep->desc))); | |
48df4a6f SS |
3567 | /* A zero-length transfer still involves at least one packet. */ |
3568 | if (total_packet_count == 0) | |
3569 | total_packet_count++; | |
5cd43e33 SS |
3570 | burst_count = xhci_get_burst_count(xhci, urb->dev, urb, |
3571 | total_packet_count); | |
b61d378f SS |
3572 | residue = xhci_get_last_burst_packet_count(xhci, |
3573 | urb->dev, urb, total_packet_count); | |
04e51901 AX |
3574 | |
3575 | trbs_per_td = count_isoc_trbs_needed(xhci, urb, i); | |
3576 | ||
3577 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 3578 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
3579 | if (ret < 0) { |
3580 | if (i == 0) | |
3581 | return ret; | |
3582 | goto cleanup; | |
3583 | } | |
04e51901 | 3584 | |
04e51901 | 3585 | td = urb_priv->td[i]; |
04e51901 AX |
3586 | for (j = 0; j < trbs_per_td; j++) { |
3587 | u32 remainder = 0; | |
760973d2 | 3588 | field = 0; |
04e51901 AX |
3589 | |
3590 | if (first_trb) { | |
760973d2 SS |
3591 | field = TRB_TBC(burst_count) | |
3592 | TRB_TLBPC(residue); | |
04e51901 AX |
3593 | /* Queue the isoc TRB */ |
3594 | field |= TRB_TYPE(TRB_ISOC); | |
3595 | /* Assume URB_ISO_ASAP is set */ | |
3596 | field |= TRB_SIA; | |
50f7b52a AX |
3597 | if (i == 0) { |
3598 | if (start_cycle == 0) | |
3599 | field |= 0x1; | |
3600 | } else | |
04e51901 AX |
3601 | field |= ep_ring->cycle_state; |
3602 | first_trb = false; | |
3603 | } else { | |
3604 | /* Queue other normal TRBs */ | |
3605 | field |= TRB_TYPE(TRB_NORMAL); | |
3606 | field |= ep_ring->cycle_state; | |
3607 | } | |
3608 | ||
af8b9e63 SS |
3609 | /* Only set interrupt on short packet for IN EPs */ |
3610 | if (usb_urb_dir_in(urb)) | |
3611 | field |= TRB_ISP; | |
3612 | ||
04e51901 AX |
3613 | /* Chain all the TRBs together; clear the chain bit in |
3614 | * the last TRB to indicate it's the last TRB in the | |
3615 | * chain. | |
3616 | */ | |
3617 | if (j < trbs_per_td - 1) { | |
3618 | field |= TRB_CHAIN; | |
47cbf692 | 3619 | more_trbs_coming = true; |
04e51901 AX |
3620 | } else { |
3621 | td->last_trb = ep_ring->enqueue; | |
3622 | field |= TRB_IOC; | |
80fab3b2 SS |
3623 | if (xhci->hci_version == 0x100 && |
3624 | !(xhci->quirks & | |
3625 | XHCI_AVOID_BEI)) { | |
ad106f29 AX |
3626 | /* Set BEI bit except for the last td */ |
3627 | if (i < num_tds - 1) | |
3628 | field |= TRB_BEI; | |
3629 | } | |
47cbf692 | 3630 | more_trbs_coming = false; |
04e51901 AX |
3631 | } |
3632 | ||
3633 | /* Calculate TRB length */ | |
3634 | trb_buff_len = TRB_MAX_BUFF_SIZE - | |
3635 | (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)); | |
3636 | if (trb_buff_len > td_remain_len) | |
3637 | trb_buff_len = td_remain_len; | |
3638 | ||
4da6e6f2 SS |
3639 | /* Set the TRB length, TD size, & interrupter fields. */ |
3640 | if (xhci->hci_version < 0x100) { | |
3641 | remainder = xhci_td_remainder( | |
3642 | td_len - running_total); | |
3643 | } else { | |
3644 | remainder = xhci_v1_0_td_remainder( | |
3645 | running_total, trb_buff_len, | |
4525c0a1 SS |
3646 | total_packet_count, urb, |
3647 | (trbs_per_td - j - 1)); | |
4da6e6f2 | 3648 | } |
04e51901 AX |
3649 | length_field = TRB_LEN(trb_buff_len) | |
3650 | remainder | | |
3651 | TRB_INTR_TARGET(0); | |
4da6e6f2 | 3652 | |
3b72fca0 | 3653 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
3654 | lower_32_bits(addr), |
3655 | upper_32_bits(addr), | |
3656 | length_field, | |
af8b9e63 | 3657 | field); |
04e51901 AX |
3658 | running_total += trb_buff_len; |
3659 | ||
3660 | addr += trb_buff_len; | |
3661 | td_remain_len -= trb_buff_len; | |
3662 | } | |
3663 | ||
3664 | /* Check TD length */ | |
3665 | if (running_total != td_len) { | |
3666 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
3667 | ret = -EINVAL; |
3668 | goto cleanup; | |
04e51901 AX |
3669 | } |
3670 | } | |
3671 | ||
c41136b0 AX |
3672 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
3673 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
3674 | usb_amd_quirk_pll_disable(); | |
3675 | } | |
3676 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
3677 | ||
e1eab2e0 AX |
3678 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3679 | start_cycle, start_trb); | |
04e51901 | 3680 | return 0; |
522989a2 SS |
3681 | cleanup: |
3682 | /* Clean up a partially enqueued isoc transfer. */ | |
3683 | ||
3684 | for (i--; i >= 0; i--) | |
585df1d9 | 3685 | list_del_init(&urb_priv->td[i]->td_list); |
522989a2 SS |
3686 | |
3687 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
3688 | * into No-ops with a software-owned cycle bit. That way the hardware | |
3689 | * won't accidentally start executing bogus TDs when we partially | |
3690 | * overwrite them. td->first_trb and td->start_seg are already set. | |
3691 | */ | |
3692 | urb_priv->td[0]->last_trb = ep_ring->enqueue; | |
3693 | /* Every TRB except the first & last will have its cycle bit flipped. */ | |
3694 | td_to_noop(xhci, ep_ring, urb_priv->td[0], true); | |
3695 | ||
3696 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
3697 | ep_ring->enqueue = urb_priv->td[0]->first_trb; | |
3698 | ep_ring->enq_seg = urb_priv->td[0]->start_seg; | |
3699 | ep_ring->cycle_state = start_cycle; | |
b008df60 | 3700 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
3701 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
3702 | return ret; | |
04e51901 AX |
3703 | } |
3704 | ||
3705 | /* | |
3706 | * Check transfer ring to guarantee there is enough room for the urb. | |
3707 | * Update ISO URB start_frame and interval. | |
3708 | * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to | |
3709 | * update the urb->start_frame by now. | |
3710 | * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input. | |
3711 | */ | |
3712 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3713 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3714 | { | |
3715 | struct xhci_virt_device *xdev; | |
3716 | struct xhci_ring *ep_ring; | |
3717 | struct xhci_ep_ctx *ep_ctx; | |
3718 | int start_frame; | |
3719 | int xhci_interval; | |
3720 | int ep_interval; | |
3721 | int num_tds, num_trbs, i; | |
3722 | int ret; | |
3723 | ||
3724 | xdev = xhci->devs[slot_id]; | |
3725 | ep_ring = xdev->eps[ep_index].ring; | |
3726 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3727 | ||
3728 | num_trbs = 0; | |
3729 | num_tds = urb->number_of_packets; | |
3730 | for (i = 0; i < num_tds; i++) | |
3731 | num_trbs += count_isoc_trbs_needed(xhci, urb, i); | |
3732 | ||
3733 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3734 | * Do not insert any td of the urb to the ring if the check failed. | |
3735 | */ | |
28ccd296 | 3736 | ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK, |
3b72fca0 | 3737 | num_trbs, mem_flags); |
04e51901 AX |
3738 | if (ret) |
3739 | return ret; | |
3740 | ||
b0ba9720 | 3741 | start_frame = readl(&xhci->run_regs->microframe_index); |
04e51901 AX |
3742 | start_frame &= 0x3fff; |
3743 | ||
3744 | urb->start_frame = start_frame; | |
3745 | if (urb->dev->speed == USB_SPEED_LOW || | |
3746 | urb->dev->speed == USB_SPEED_FULL) | |
3747 | urb->start_frame >>= 3; | |
3748 | ||
28ccd296 | 3749 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
04e51901 AX |
3750 | ep_interval = urb->interval; |
3751 | /* Convert to microframes */ | |
3752 | if (urb->dev->speed == USB_SPEED_LOW || | |
3753 | urb->dev->speed == USB_SPEED_FULL) | |
3754 | ep_interval *= 8; | |
3755 | /* FIXME change this to a warning and a suggestion to use the new API | |
3756 | * to set the polling interval (once the API is added). | |
3757 | */ | |
3758 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3759 | dev_dbg_ratelimited(&urb->dev->dev, |
3760 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3761 | ep_interval, ep_interval == 1 ? "" : "s", | |
3762 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
04e51901 AX |
3763 | urb->interval = xhci_interval; |
3764 | /* Convert back to frames for LS/FS devices */ | |
3765 | if (urb->dev->speed == USB_SPEED_LOW || | |
3766 | urb->dev->speed == USB_SPEED_FULL) | |
3767 | urb->interval /= 8; | |
3768 | } | |
b008df60 AX |
3769 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
3770 | ||
3fc8206d | 3771 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
3772 | } |
3773 | ||
d0e96f5a SS |
3774 | /**** Command Ring Operations ****/ |
3775 | ||
913a8a34 SS |
3776 | /* Generic function for queueing a command TRB on the command ring. |
3777 | * Check to make sure there's room on the command ring for one command TRB. | |
3778 | * Also check that there's room reserved for commands that must not fail. | |
3779 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
3780 | * then only check for the number of reserved spots. | |
3781 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
3782 | * because the command event handler may want to resubmit a failed command. | |
3783 | */ | |
ddba5cd0 MN |
3784 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3785 | u32 field1, u32 field2, | |
3786 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 3787 | { |
913a8a34 | 3788 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a | 3789 | int ret; |
c9aa1a2d MN |
3790 | if (xhci->xhc_state & XHCI_STATE_DYING) |
3791 | return -ESHUTDOWN; | |
d1dc908a | 3792 | |
913a8a34 SS |
3793 | if (!command_must_succeed) |
3794 | reserved_trbs++; | |
3795 | ||
d1dc908a | 3796 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 3797 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
3798 | if (ret < 0) { |
3799 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
3800 | if (command_must_succeed) |
3801 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
3802 | "unfailable commands failed.\n"); | |
d1dc908a | 3803 | return ret; |
7f84eef0 | 3804 | } |
c9aa1a2d MN |
3805 | |
3806 | cmd->command_trb = xhci->cmd_ring->enqueue; | |
3807 | list_add_tail(&cmd->cmd_list, &xhci->cmd_list); | |
ddba5cd0 | 3808 | |
c311e391 MN |
3809 | /* if there are no other commands queued we start the timeout timer */ |
3810 | if (xhci->cmd_list.next == &cmd->cmd_list && | |
3811 | !timer_pending(&xhci->cmd_timer)) { | |
3812 | xhci->current_cmd = cmd; | |
3813 | mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT); | |
3814 | } | |
3815 | ||
3b72fca0 AX |
3816 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
3817 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
3818 | return 0; |
3819 | } | |
3820 | ||
3ffbba95 | 3821 | /* Queue a slot enable or disable request on the command ring */ |
ddba5cd0 MN |
3822 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3823 | u32 trb_type, u32 slot_id) | |
3ffbba95 | 3824 | { |
ddba5cd0 | 3825 | return queue_command(xhci, cmd, 0, 0, 0, |
913a8a34 | 3826 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
3827 | } |
3828 | ||
3829 | /* Queue an address device command TRB */ | |
ddba5cd0 MN |
3830 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3831 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) | |
3ffbba95 | 3832 | { |
ddba5cd0 | 3833 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3834 | upper_32_bits(in_ctx_ptr), 0, |
48fc7dbd DW |
3835 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
3836 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); | |
2a8f82c4 SS |
3837 | } |
3838 | ||
ddba5cd0 | 3839 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
0238634d SS |
3840 | u32 field1, u32 field2, u32 field3, u32 field4) |
3841 | { | |
ddba5cd0 | 3842 | return queue_command(xhci, cmd, field1, field2, field3, field4, false); |
0238634d SS |
3843 | } |
3844 | ||
2a8f82c4 | 3845 | /* Queue a reset device command TRB */ |
ddba5cd0 MN |
3846 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3847 | u32 slot_id) | |
2a8f82c4 | 3848 | { |
ddba5cd0 | 3849 | return queue_command(xhci, cmd, 0, 0, 0, |
2a8f82c4 | 3850 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
913a8a34 | 3851 | false); |
3ffbba95 | 3852 | } |
f94e0186 SS |
3853 | |
3854 | /* Queue a configure endpoint command TRB */ | |
ddba5cd0 MN |
3855 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
3856 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, | |
913a8a34 | 3857 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 3858 | { |
ddba5cd0 | 3859 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3860 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 SS |
3861 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
3862 | command_must_succeed); | |
f94e0186 | 3863 | } |
ae636747 | 3864 | |
f2217e8e | 3865 | /* Queue an evaluate context command TRB */ |
ddba5cd0 MN |
3866 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3867 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) | |
f2217e8e | 3868 | { |
ddba5cd0 | 3869 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
f2217e8e | 3870 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 | 3871 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 3872 | command_must_succeed); |
f2217e8e SS |
3873 | } |
3874 | ||
be88fe4f AX |
3875 | /* |
3876 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
3877 | * activity on an endpoint that is about to be suspended. | |
3878 | */ | |
ddba5cd0 MN |
3879 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3880 | int slot_id, unsigned int ep_index, int suspend) | |
ae636747 SS |
3881 | { |
3882 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3883 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3884 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 3885 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 | 3886 | |
ddba5cd0 | 3887 | return queue_command(xhci, cmd, 0, 0, 0, |
be88fe4f | 3888 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
3889 | } |
3890 | ||
d3a43e66 HG |
3891 | /* Set Transfer Ring Dequeue Pointer command */ |
3892 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, | |
3893 | unsigned int slot_id, unsigned int ep_index, | |
3894 | unsigned int stream_id, | |
3895 | struct xhci_dequeue_state *deq_state) | |
ae636747 SS |
3896 | { |
3897 | dma_addr_t addr; | |
3898 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3899 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
e9df17eb | 3900 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
95241dbd | 3901 | u32 trb_sct = 0; |
ae636747 | 3902 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
bf161e85 | 3903 | struct xhci_virt_ep *ep; |
1e3452e3 HG |
3904 | struct xhci_command *cmd; |
3905 | int ret; | |
ae636747 | 3906 | |
d3a43e66 HG |
3907 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
3908 | "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u", | |
3909 | deq_state->new_deq_seg, | |
3910 | (unsigned long long)deq_state->new_deq_seg->dma, | |
3911 | deq_state->new_deq_ptr, | |
3912 | (unsigned long long)xhci_trb_virt_to_dma( | |
3913 | deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
3914 | deq_state->new_cycle_state); | |
3915 | ||
3916 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
3917 | deq_state->new_deq_ptr); | |
c92bcfa7 | 3918 | if (addr == 0) { |
ae636747 | 3919 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 | 3920 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
d3a43e66 HG |
3921 | deq_state->new_deq_seg, deq_state->new_deq_ptr); |
3922 | return; | |
c92bcfa7 | 3923 | } |
bf161e85 SS |
3924 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
3925 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
3926 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | |
3927 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | |
d3a43e66 | 3928 | return; |
bf161e85 | 3929 | } |
1e3452e3 HG |
3930 | |
3931 | /* This function gets called from contexts where it cannot sleep */ | |
3932 | cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
3933 | if (!cmd) { | |
3934 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n"); | |
d3a43e66 | 3935 | return; |
1e3452e3 HG |
3936 | } |
3937 | ||
d3a43e66 HG |
3938 | ep->queued_deq_seg = deq_state->new_deq_seg; |
3939 | ep->queued_deq_ptr = deq_state->new_deq_ptr; | |
95241dbd HG |
3940 | if (stream_id) |
3941 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); | |
1e3452e3 | 3942 | ret = queue_command(xhci, cmd, |
d3a43e66 HG |
3943 | lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state, |
3944 | upper_32_bits(addr), trb_stream_id, | |
3945 | trb_slot_id | trb_ep_index | type, false); | |
1e3452e3 HG |
3946 | if (ret < 0) { |
3947 | xhci_free_command(xhci, cmd); | |
d3a43e66 | 3948 | return; |
1e3452e3 HG |
3949 | } |
3950 | ||
d3a43e66 HG |
3951 | /* Stop the TD queueing code from ringing the doorbell until |
3952 | * this command completes. The HC won't set the dequeue pointer | |
3953 | * if the ring is running, and ringing the doorbell starts the | |
3954 | * ring running. | |
3955 | */ | |
3956 | ep->ep_state |= SET_DEQ_PENDING; | |
ae636747 | 3957 | } |
a1587d97 | 3958 | |
ddba5cd0 MN |
3959 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3960 | int slot_id, unsigned int ep_index) | |
a1587d97 SS |
3961 | { |
3962 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3963 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3964 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
3965 | ||
ddba5cd0 MN |
3966 | return queue_command(xhci, cmd, 0, 0, 0, |
3967 | trb_slot_id | trb_ep_index | type, false); | |
a1587d97 | 3968 | } |