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Commit | Line | Data |
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7f84eef0 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ring initialization rules: | |
25 | * 1. Each segment is initialized to zero, except for link TRBs. | |
26 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
27 | * Consumer Cycle State (CCS), depending on ring function. | |
28 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
29 | * | |
30 | * Ring behavior rules: | |
31 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
32 | * least one free TRB in the ring. This is useful if you want to turn that | |
33 | * into a link TRB and expand the ring. | |
34 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
35 | * link TRB, then load the pointer with the address in the link TRB. If the | |
36 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
37 | * state (see cycle bit rules). You may have to do this multiple times | |
38 | * until you reach a non-link TRB. | |
39 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
40 | * equals the dequeue pointer. | |
41 | * | |
42 | * Cycle bit rules: | |
43 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
44 | * in a link TRB, it must toggle the ring cycle state. | |
45 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
46 | * in a link TRB, it must toggle the ring cycle state. | |
47 | * | |
48 | * Producer rules: | |
49 | * 1. Check if ring is full before you enqueue. | |
50 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
51 | * Update enqueue pointer between each write (which may update the ring | |
52 | * cycle state). | |
53 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
54 | * and endpoint rings. If HC is the producer for the event ring, | |
55 | * and it generates an interrupt according to interrupt modulation rules. | |
56 | * | |
57 | * Consumer rules: | |
58 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
59 | * the TRB is owned by the consumer. | |
60 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
61 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
62 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
63 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
64 | * endpoint rings; it generates events on the event ring for these. | |
65 | */ | |
66 | ||
8a96c052 | 67 | #include <linux/scatterlist.h> |
5a0e3ad6 | 68 | #include <linux/slab.h> |
f9c589e1 | 69 | #include <linux/dma-mapping.h> |
7f84eef0 | 70 | #include "xhci.h" |
3a7fa5be | 71 | #include "xhci-trace.h" |
0cbd4b34 | 72 | #include "xhci-mtk.h" |
7f84eef0 SS |
73 | |
74 | /* | |
75 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
76 | * address of the TRB. | |
77 | */ | |
23e3be11 | 78 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
79 | union xhci_trb *trb) |
80 | { | |
6071d836 | 81 | unsigned long segment_offset; |
7f84eef0 | 82 | |
6071d836 | 83 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 84 | return 0; |
6071d836 SS |
85 | /* offset in TRBs */ |
86 | segment_offset = trb - seg->trbs; | |
7895086a | 87 | if (segment_offset >= TRBS_PER_SEGMENT) |
7f84eef0 | 88 | return 0; |
6071d836 | 89 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
90 | } |
91 | ||
0ce57499 MN |
92 | static bool trb_is_noop(union xhci_trb *trb) |
93 | { | |
94 | return TRB_TYPE_NOOP_LE32(trb->generic.field[3]); | |
95 | } | |
96 | ||
2d98ef40 MN |
97 | static bool trb_is_link(union xhci_trb *trb) |
98 | { | |
99 | return TRB_TYPE_LINK_LE32(trb->link.control); | |
100 | } | |
101 | ||
bd5e67f5 MN |
102 | static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) |
103 | { | |
104 | return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; | |
105 | } | |
106 | ||
107 | static bool last_trb_on_ring(struct xhci_ring *ring, | |
108 | struct xhci_segment *seg, union xhci_trb *trb) | |
109 | { | |
110 | return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); | |
111 | } | |
112 | ||
d0c77d84 MN |
113 | static bool link_trb_toggles_cycle(union xhci_trb *trb) |
114 | { | |
115 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; | |
116 | } | |
117 | ||
2a72126d MN |
118 | static bool last_td_in_urb(struct xhci_td *td) |
119 | { | |
120 | struct urb_priv *urb_priv = td->urb->hcpriv; | |
121 | ||
9ef7fbbb | 122 | return urb_priv->num_tds_done == urb_priv->num_tds; |
2a72126d MN |
123 | } |
124 | ||
125 | static void inc_td_cnt(struct urb *urb) | |
126 | { | |
127 | struct urb_priv *urb_priv = urb->hcpriv; | |
128 | ||
9ef7fbbb | 129 | urb_priv->num_tds_done++; |
2a72126d MN |
130 | } |
131 | ||
ae1e3f07 MN |
132 | static void trb_to_noop(union xhci_trb *trb, u32 noop_type) |
133 | { | |
134 | if (trb_is_link(trb)) { | |
135 | /* unchain chained link TRBs */ | |
136 | trb->link.control &= cpu_to_le32(~TRB_CHAIN); | |
137 | } else { | |
138 | trb->generic.field[0] = 0; | |
139 | trb->generic.field[1] = 0; | |
140 | trb->generic.field[2] = 0; | |
141 | /* Preserve only the cycle bit of this TRB */ | |
142 | trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); | |
143 | trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type)); | |
144 | } | |
145 | } | |
146 | ||
ae636747 SS |
147 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
148 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
149 | * effect the ring dequeue or enqueue pointers. | |
150 | */ | |
151 | static void next_trb(struct xhci_hcd *xhci, | |
152 | struct xhci_ring *ring, | |
153 | struct xhci_segment **seg, | |
154 | union xhci_trb **trb) | |
155 | { | |
2d98ef40 | 156 | if (trb_is_link(*trb)) { |
ae636747 SS |
157 | *seg = (*seg)->next; |
158 | *trb = ((*seg)->trbs); | |
159 | } else { | |
a1669b2c | 160 | (*trb)++; |
ae636747 SS |
161 | } |
162 | } | |
163 | ||
7f84eef0 SS |
164 | /* |
165 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
166 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
167 | */ | |
3b72fca0 | 168 | static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 169 | { |
7f84eef0 | 170 | ring->deq_updates++; |
b008df60 | 171 | |
bd5e67f5 MN |
172 | /* event ring doesn't have link trbs, check for last trb */ |
173 | if (ring->type == TYPE_EVENT) { | |
174 | if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { | |
50d0206f | 175 | ring->dequeue++; |
bd5e67f5 | 176 | return; |
7f84eef0 | 177 | } |
bd5e67f5 MN |
178 | if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) |
179 | ring->cycle_state ^= 1; | |
180 | ring->deq_seg = ring->deq_seg->next; | |
181 | ring->dequeue = ring->deq_seg->trbs; | |
182 | return; | |
183 | } | |
184 | ||
185 | /* All other rings have link trbs */ | |
186 | if (!trb_is_link(ring->dequeue)) { | |
187 | ring->dequeue++; | |
188 | ring->num_trbs_free++; | |
189 | } | |
190 | while (trb_is_link(ring->dequeue)) { | |
191 | ring->deq_seg = ring->deq_seg->next; | |
192 | ring->dequeue = ring->deq_seg->trbs; | |
193 | } | |
194 | return; | |
7f84eef0 SS |
195 | } |
196 | ||
197 | /* | |
198 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
199 | * Don't make a ring full of link TRBs. That would be dumb and this would loop. | |
200 | * | |
201 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
202 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
203 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
204 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
205 | * | |
206 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
207 | * set, but other sections talk about dealing with the chain bit set. This was |
208 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
209 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
210 | * |
211 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
212 | * prepare_transfer()? | |
7f84eef0 | 213 | */ |
6cc30d85 | 214 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 215 | bool more_trbs_coming) |
7f84eef0 SS |
216 | { |
217 | u32 chain; | |
218 | union xhci_trb *next; | |
219 | ||
28ccd296 | 220 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 | 221 | /* If this is not event ring, there is one less usable TRB */ |
2d98ef40 | 222 | if (!trb_is_link(ring->enqueue)) |
b008df60 | 223 | ring->num_trbs_free--; |
7f84eef0 SS |
224 | next = ++(ring->enqueue); |
225 | ||
226 | ring->enq_updates++; | |
2251198b | 227 | /* Update the dequeue pointer further if that was a link TRB */ |
2d98ef40 | 228 | while (trb_is_link(next)) { |
6cc30d85 | 229 | |
2251198b MN |
230 | /* |
231 | * If the caller doesn't plan on enqueueing more TDs before | |
232 | * ringing the doorbell, then we don't want to give the link TRB | |
233 | * to the hardware just yet. We'll give the link TRB back in | |
234 | * prepare_ring() just before we enqueue the TD at the top of | |
235 | * the ring. | |
236 | */ | |
237 | if (!chain && !more_trbs_coming) | |
238 | break; | |
3b72fca0 | 239 | |
2251198b MN |
240 | /* If we're not dealing with 0.95 hardware or isoc rings on |
241 | * AMD 0.96 host, carry over the chain bit of the previous TRB | |
242 | * (which may mean the chain bit is cleared). | |
243 | */ | |
244 | if (!(ring->type == TYPE_ISOC && | |
245 | (xhci->quirks & XHCI_AMD_0x96_HOST)) && | |
246 | !xhci_link_trb_quirk(xhci)) { | |
247 | next->link.control &= cpu_to_le32(~TRB_CHAIN); | |
248 | next->link.control |= cpu_to_le32(chain); | |
7f84eef0 | 249 | } |
2251198b MN |
250 | /* Give this link TRB to the hardware */ |
251 | wmb(); | |
252 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
253 | ||
254 | /* Toggle the cycle bit after the last ring segment. */ | |
d0c77d84 | 255 | if (link_trb_toggles_cycle(next)) |
2251198b MN |
256 | ring->cycle_state ^= 1; |
257 | ||
7f84eef0 SS |
258 | ring->enq_seg = ring->enq_seg->next; |
259 | ring->enqueue = ring->enq_seg->trbs; | |
260 | next = ring->enqueue; | |
261 | } | |
262 | } | |
263 | ||
264 | /* | |
085deb16 AX |
265 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
266 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 267 | */ |
b008df60 | 268 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
269 | unsigned int num_trbs) |
270 | { | |
085deb16 | 271 | int num_trbs_in_deq_seg; |
b008df60 | 272 | |
085deb16 AX |
273 | if (ring->num_trbs_free < num_trbs) |
274 | return 0; | |
275 | ||
276 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
277 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
278 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
279 | return 0; | |
280 | } | |
281 | ||
282 | return 1; | |
7f84eef0 SS |
283 | } |
284 | ||
7f84eef0 | 285 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 286 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 287 | { |
c181bc5b EF |
288 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
289 | return; | |
290 | ||
7f84eef0 | 291 | xhci_dbg(xhci, "// Ding dong!\n"); |
204b7793 | 292 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 | 293 | /* Flush PCI posted writes */ |
b0ba9720 | 294 | readl(&xhci->dba->doorbell[0]); |
7f84eef0 SS |
295 | } |
296 | ||
cb4d5ce5 OH |
297 | static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay) |
298 | { | |
299 | return mod_delayed_work(system_wq, &xhci->cmd_timer, delay); | |
300 | } | |
301 | ||
1c111b6c OH |
302 | static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci) |
303 | { | |
304 | return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command, | |
305 | cmd_list); | |
306 | } | |
307 | ||
308 | /* | |
309 | * Turn all commands on command ring with status set to "aborted" to no-op trbs. | |
310 | * If there are other commands waiting then restart the ring and kick the timer. | |
311 | * This must be called with command ring stopped and xhci->lock held. | |
312 | */ | |
313 | static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, | |
314 | struct xhci_command *cur_cmd) | |
315 | { | |
316 | struct xhci_command *i_cmd; | |
1c111b6c OH |
317 | |
318 | /* Turn all aborted commands in list to no-ops, then restart */ | |
319 | list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { | |
320 | ||
0b7c105a | 321 | if (i_cmd->status != COMP_COMMAND_ABORTED) |
1c111b6c OH |
322 | continue; |
323 | ||
0b7c105a | 324 | i_cmd->status = COMP_STOPPED; |
1c111b6c OH |
325 | |
326 | xhci_dbg(xhci, "Turn aborted command %p to no-op\n", | |
327 | i_cmd->command_trb); | |
5278204c MN |
328 | |
329 | trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP); | |
1c111b6c OH |
330 | |
331 | /* | |
332 | * caller waiting for completion is called when command | |
333 | * completion event is received for these no-op commands | |
334 | */ | |
335 | } | |
336 | ||
337 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; | |
338 | ||
339 | /* ring command ring doorbell to restart the command ring */ | |
340 | if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && | |
341 | !(xhci->xhc_state & XHCI_STATE_DYING)) { | |
342 | xhci->current_cmd = cur_cmd; | |
343 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); | |
344 | xhci_ring_cmd_db(xhci); | |
345 | } | |
346 | } | |
347 | ||
348 | /* Must be called with xhci->lock held, releases and aquires lock back */ | |
349 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) | |
b92cc66c EF |
350 | { |
351 | u64 temp_64; | |
352 | int ret; | |
353 | ||
354 | xhci_dbg(xhci, "Abort command ring\n"); | |
355 | ||
1c111b6c | 356 | reinit_completion(&xhci->cmd_ring_stop_completion); |
3425aa03 | 357 | |
1c111b6c | 358 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
477632df SS |
359 | xhci_write_64(xhci, temp_64 | CMD_RING_ABORT, |
360 | &xhci->op_regs->cmd_ring); | |
b92cc66c EF |
361 | |
362 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should | |
363 | * time the completion od all xHCI commands, including | |
364 | * the Command Abort operation. If software doesn't see | |
365 | * CRR negated in a timely manner (e.g. longer than 5 | |
366 | * seconds), then it should assume that the there are | |
367 | * larger problems with the xHC and assert HCRST. | |
368 | */ | |
dc0b177c | 369 | ret = xhci_handshake(&xhci->op_regs->cmd_ring, |
b92cc66c EF |
370 | CMD_RING_RUNNING, 0, 5 * 1000 * 1000); |
371 | if (ret < 0) { | |
1cc6d861 LB |
372 | xhci_err(xhci, |
373 | "Stop command ring failed, maybe the host is dead\n"); | |
374 | xhci->xhc_state |= XHCI_STATE_DYING; | |
375 | xhci_halt(xhci); | |
376 | return -ESHUTDOWN; | |
1c111b6c OH |
377 | } |
378 | /* | |
379 | * Writing the CMD_RING_ABORT bit should cause a cmd completion event, | |
380 | * however on some host hw the CMD_RING_RUNNING bit is correctly cleared | |
381 | * but the completion event in never sent. Wait 2 secs (arbitrary | |
382 | * number) to handle those cases after negation of CMD_RING_RUNNING. | |
383 | */ | |
384 | spin_unlock_irqrestore(&xhci->lock, flags); | |
385 | ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion, | |
386 | msecs_to_jiffies(2000)); | |
387 | spin_lock_irqsave(&xhci->lock, flags); | |
388 | if (!ret) { | |
389 | xhci_dbg(xhci, "No stop event for abort, ring start fail?\n"); | |
390 | xhci_cleanup_command_queue(xhci); | |
391 | } else { | |
392 | xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci)); | |
b92cc66c | 393 | } |
b92cc66c EF |
394 | return 0; |
395 | } | |
396 | ||
be88fe4f | 397 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 398 | unsigned int slot_id, |
e9df17eb SS |
399 | unsigned int ep_index, |
400 | unsigned int stream_id) | |
ae636747 | 401 | { |
28ccd296 | 402 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
403 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
404 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 405 | |
ae636747 | 406 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 407 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
408 | * We don't want to restart any stream rings if there's a set dequeue |
409 | * pointer command pending because the device can choose to start any | |
410 | * stream once the endpoint is on the HW schedule. | |
ae636747 | 411 | */ |
9983a5fc | 412 | if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) || |
50d64676 MW |
413 | (ep_state & EP_HALTED)) |
414 | return; | |
204b7793 | 415 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
50d64676 MW |
416 | /* The CPU has better things to do at this point than wait for a |
417 | * write-posting flush. It'll get there soon enough. | |
418 | */ | |
ae636747 SS |
419 | } |
420 | ||
e9df17eb SS |
421 | /* Ring the doorbell for any rings with pending URBs */ |
422 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
423 | unsigned int slot_id, | |
424 | unsigned int ep_index) | |
425 | { | |
426 | unsigned int stream_id; | |
427 | struct xhci_virt_ep *ep; | |
428 | ||
429 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
430 | ||
431 | /* A ring has pending URBs if its TD list is not empty */ | |
432 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
d66eaf9f | 433 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
be88fe4f | 434 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
435 | return; |
436 | } | |
437 | ||
438 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
439 | stream_id++) { | |
440 | struct xhci_stream_info *stream_info = ep->stream_info; | |
441 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
442 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
443 | stream_id); | |
e9df17eb SS |
444 | } |
445 | } | |
446 | ||
75b040ec AI |
447 | /* Get the right ring for the given slot_id, ep_index and stream_id. |
448 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
449 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
450 | */ | |
451 | struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
021bff91 SS |
452 | unsigned int slot_id, unsigned int ep_index, |
453 | unsigned int stream_id) | |
454 | { | |
455 | struct xhci_virt_ep *ep; | |
456 | ||
457 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
458 | /* Common case: no streams */ | |
459 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
460 | return ep->ring; | |
461 | ||
462 | if (stream_id == 0) { | |
463 | xhci_warn(xhci, | |
464 | "WARN: Slot ID %u, ep index %u has streams, " | |
465 | "but URB has no stream ID.\n", | |
466 | slot_id, ep_index); | |
467 | return NULL; | |
468 | } | |
469 | ||
470 | if (stream_id < ep->stream_info->num_streams) | |
471 | return ep->stream_info->stream_rings[stream_id]; | |
472 | ||
473 | xhci_warn(xhci, | |
474 | "WARN: Slot ID %u, ep index %u has " | |
475 | "stream IDs 1 to %u allocated, " | |
476 | "but stream ID %u is requested.\n", | |
477 | slot_id, ep_index, | |
478 | ep->stream_info->num_streams - 1, | |
479 | stream_id); | |
480 | return NULL; | |
481 | } | |
482 | ||
ae636747 SS |
483 | /* |
484 | * Move the xHC's endpoint ring dequeue pointer past cur_td. | |
485 | * Record the new state of the xHC's endpoint ring dequeue segment, | |
486 | * dequeue pointer, and new consumer cycle state in state. | |
487 | * Update our internal representation of the ring's dequeue pointer. | |
488 | * | |
489 | * We do this in three jumps: | |
490 | * - First we update our new ring state to be the same as when the xHC stopped. | |
491 | * - Then we traverse the ring to find the segment that contains | |
492 | * the last TRB in the TD. We toggle the xHC's new cycle state when we pass | |
493 | * any link TRBs with the toggle cycle bit set. | |
494 | * - Finally we move the dequeue state one TRB further, toggling the cycle bit | |
495 | * if we've moved it past a link TRB with the toggle cycle bit set. | |
28ccd296 ME |
496 | * |
497 | * Some of the uses of xhci_generic_trb are grotty, but if they're done | |
498 | * with correct __le32 accesses they should work fine. Only users of this are | |
499 | * in here. | |
ae636747 | 500 | */ |
c92bcfa7 | 501 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
ae636747 | 502 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb SS |
503 | unsigned int stream_id, struct xhci_td *cur_td, |
504 | struct xhci_dequeue_state *state) | |
ae636747 SS |
505 | { |
506 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
c4bedb77 | 507 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; |
e9df17eb | 508 | struct xhci_ring *ep_ring; |
365038d8 MN |
509 | struct xhci_segment *new_seg; |
510 | union xhci_trb *new_deq; | |
c92bcfa7 | 511 | dma_addr_t addr; |
1f81b6d2 | 512 | u64 hw_dequeue; |
365038d8 MN |
513 | bool cycle_found = false; |
514 | bool td_last_trb_found = false; | |
ae636747 | 515 | |
e9df17eb SS |
516 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, |
517 | ep_index, stream_id); | |
518 | if (!ep_ring) { | |
519 | xhci_warn(xhci, "WARN can't find new dequeue state " | |
520 | "for invalid stream ID %u.\n", | |
521 | stream_id); | |
522 | return; | |
523 | } | |
68e41c5d | 524 | |
ae636747 | 525 | /* Dig out the cycle state saved by the xHC during the stop ep cmd */ |
aa50b290 XR |
526 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
527 | "Finding endpoint context"); | |
c4bedb77 HG |
528 | /* 4.6.9 the css flag is written to the stream context for streams */ |
529 | if (ep->ep_state & EP_HAS_STREAMS) { | |
530 | struct xhci_stream_ctx *ctx = | |
531 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1f81b6d2 | 532 | hw_dequeue = le64_to_cpu(ctx->stream_ring); |
c4bedb77 HG |
533 | } else { |
534 | struct xhci_ep_ctx *ep_ctx | |
535 | = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); | |
1f81b6d2 | 536 | hw_dequeue = le64_to_cpu(ep_ctx->deq); |
c4bedb77 | 537 | } |
ae636747 | 538 | |
365038d8 MN |
539 | new_seg = ep_ring->deq_seg; |
540 | new_deq = ep_ring->dequeue; | |
541 | state->new_cycle_state = hw_dequeue & 0x1; | |
542 | ||
1f81b6d2 | 543 | /* |
365038d8 MN |
544 | * We want to find the pointer, segment and cycle state of the new trb |
545 | * (the one after current TD's last_trb). We know the cycle state at | |
546 | * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are | |
547 | * found. | |
1f81b6d2 | 548 | */ |
365038d8 MN |
549 | do { |
550 | if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) | |
551 | == (dma_addr_t)(hw_dequeue & ~0xf)) { | |
552 | cycle_found = true; | |
553 | if (td_last_trb_found) | |
554 | break; | |
555 | } | |
556 | if (new_deq == cur_td->last_trb) | |
557 | td_last_trb_found = true; | |
1f81b6d2 | 558 | |
3495e451 MN |
559 | if (cycle_found && trb_is_link(new_deq) && |
560 | link_trb_toggles_cycle(new_deq)) | |
365038d8 MN |
561 | state->new_cycle_state ^= 0x1; |
562 | ||
563 | next_trb(xhci, ep_ring, &new_seg, &new_deq); | |
564 | ||
565 | /* Search wrapped around, bail out */ | |
566 | if (new_deq == ep->ring->dequeue) { | |
567 | xhci_err(xhci, "Error: Failed finding new dequeue state\n"); | |
568 | state->new_deq_seg = NULL; | |
569 | state->new_deq_ptr = NULL; | |
570 | return; | |
571 | } | |
572 | ||
573 | } while (!cycle_found || !td_last_trb_found); | |
ae636747 | 574 | |
365038d8 MN |
575 | state->new_deq_seg = new_seg; |
576 | state->new_deq_ptr = new_deq; | |
ae636747 | 577 | |
1f81b6d2 | 578 | /* Don't update the ring cycle state for the producer (us). */ |
aa50b290 XR |
579 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
580 | "Cycle state = 0x%x", state->new_cycle_state); | |
01a1fdb9 | 581 | |
aa50b290 XR |
582 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
583 | "New dequeue segment = %p (virtual)", | |
c92bcfa7 SS |
584 | state->new_deq_seg); |
585 | addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr); | |
aa50b290 XR |
586 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
587 | "New dequeue pointer = 0x%llx (DMA)", | |
c92bcfa7 | 588 | (unsigned long long) addr); |
ae636747 SS |
589 | } |
590 | ||
522989a2 SS |
591 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
592 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
593 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
594 | */ | |
23e3be11 | 595 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
0d58a1a0 | 596 | struct xhci_td *td, bool flip_cycle) |
ae636747 | 597 | { |
0d58a1a0 MN |
598 | struct xhci_segment *seg = td->start_seg; |
599 | union xhci_trb *trb = td->first_trb; | |
600 | ||
601 | while (1) { | |
ae1e3f07 MN |
602 | trb_to_noop(trb, TRB_TR_NOOP); |
603 | ||
0d58a1a0 MN |
604 | /* flip cycle if asked to */ |
605 | if (flip_cycle && trb != td->first_trb && trb != td->last_trb) | |
606 | trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE); | |
607 | ||
608 | if (trb == td->last_trb) | |
ae636747 | 609 | break; |
0d58a1a0 MN |
610 | |
611 | next_trb(xhci, ep_ring, &seg, &trb); | |
ae636747 SS |
612 | } |
613 | } | |
614 | ||
575688e1 | 615 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
616 | struct xhci_virt_ep *ep) |
617 | { | |
9983a5fc | 618 | ep->ep_state &= ~EP_STOP_CMD_PENDING; |
f9926596 MN |
619 | /* Can't del_timer_sync in interrupt */ |
620 | del_timer(&ep->stop_cmd_timer); | |
6f5165cf SS |
621 | } |
622 | ||
2a72126d MN |
623 | /* |
624 | * Must be called with xhci->lock held in interrupt context, | |
625 | * releases and re-acquires xhci->lock | |
626 | */ | |
6f5165cf | 627 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, |
2a72126d | 628 | struct xhci_td *cur_td, int status) |
6f5165cf | 629 | { |
2a72126d MN |
630 | struct urb *urb = cur_td->urb; |
631 | struct urb_priv *urb_priv = urb->hcpriv; | |
632 | struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus); | |
633 | ||
634 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | |
635 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
636 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
637 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
638 | usb_amd_quirk_pll_enable(); | |
c41136b0 | 639 | } |
8e51adcc | 640 | } |
446b3141 | 641 | xhci_urb_free_priv(urb_priv); |
2a72126d | 642 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
446b3141 | 643 | spin_unlock(&xhci->lock); |
2a72126d | 644 | usb_hcd_giveback_urb(hcd, urb, status); |
5abdc2e6 | 645 | trace_xhci_urb_giveback(urb); |
446b3141 MN |
646 | spin_lock(&xhci->lock); |
647 | } | |
648 | ||
2d6d5769 WY |
649 | static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, |
650 | struct xhci_ring *ring, struct xhci_td *td) | |
f9c589e1 MN |
651 | { |
652 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
653 | struct xhci_segment *seg = td->bounce_seg; | |
654 | struct urb *urb = td->urb; | |
655 | ||
f45e2a02 | 656 | if (!ring || !seg || !urb) |
f9c589e1 MN |
657 | return; |
658 | ||
659 | if (usb_urb_dir_out(urb)) { | |
660 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
661 | DMA_TO_DEVICE); | |
662 | return; | |
663 | } | |
664 | ||
665 | /* for in tranfers we need to copy the data from bounce to sg */ | |
666 | sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf, | |
667 | seg->bounce_len, seg->bounce_offs); | |
668 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
669 | DMA_FROM_DEVICE); | |
670 | seg->bounce_len = 0; | |
671 | seg->bounce_offs = 0; | |
672 | } | |
673 | ||
ae636747 SS |
674 | /* |
675 | * When we get a command completion for a Stop Endpoint Command, we need to | |
676 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
677 | * | |
678 | * 1. If the HW was in the middle of processing the TD that needs to be | |
679 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
680 | * in the TD with a Set Dequeue Pointer Command. | |
681 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
682 | * bit cleared) so that the HW will skip over them. | |
683 | */ | |
b8200c94 | 684 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
be88fe4f | 685 | union xhci_trb *trb, struct xhci_event_cmd *event) |
ae636747 | 686 | { |
ae636747 SS |
687 | unsigned int ep_index; |
688 | struct xhci_ring *ep_ring; | |
63a0d9ab | 689 | struct xhci_virt_ep *ep; |
326b4810 | 690 | struct xhci_td *cur_td = NULL; |
ae636747 | 691 | struct xhci_td *last_unlinked_td; |
19a7d0d6 FB |
692 | struct xhci_ep_ctx *ep_ctx; |
693 | struct xhci_virt_device *vdev; | |
ae636747 | 694 | |
c92bcfa7 | 695 | struct xhci_dequeue_state deq_state; |
ae636747 | 696 | |
bc752bde | 697 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
9ea1833e | 698 | if (!xhci->devs[slot_id]) |
be88fe4f AX |
699 | xhci_warn(xhci, "Stop endpoint command " |
700 | "completion for disabled slot %u\n", | |
701 | slot_id); | |
702 | return; | |
703 | } | |
704 | ||
ae636747 | 705 | memset(&deq_state, 0, sizeof(deq_state)); |
28ccd296 | 706 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
19a7d0d6 FB |
707 | |
708 | vdev = xhci->devs[slot_id]; | |
709 | ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); | |
710 | trace_xhci_handle_cmd_stop_ep(ep_ctx); | |
711 | ||
63a0d9ab | 712 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
04861f83 FB |
713 | last_unlinked_td = list_last_entry(&ep->cancelled_td_list, |
714 | struct xhci_td, cancelled_td_list); | |
ae636747 | 715 | |
678539cf | 716 | if (list_empty(&ep->cancelled_td_list)) { |
6f5165cf | 717 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
0714a57c | 718 | ep->stopped_td = NULL; |
e9df17eb | 719 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); |
ae636747 | 720 | return; |
678539cf | 721 | } |
ae636747 SS |
722 | |
723 | /* Fix up the ep ring first, so HW stops executing cancelled TDs. | |
724 | * We have the xHCI lock, so nothing can modify this list until we drop | |
725 | * it. We're also in the event handler, so we can't get re-interrupted | |
726 | * if another Stop Endpoint command completes | |
727 | */ | |
04861f83 | 728 | list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) { |
aa50b290 XR |
729 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
730 | "Removing canceled TD starting at 0x%llx (dma).", | |
79688acf SS |
731 | (unsigned long long)xhci_trb_virt_to_dma( |
732 | cur_td->start_seg, cur_td->first_trb)); | |
e9df17eb SS |
733 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
734 | if (!ep_ring) { | |
735 | /* This shouldn't happen unless a driver is mucking | |
736 | * with the stream ID after submission. This will | |
737 | * leave the TD on the hardware ring, and the hardware | |
738 | * will try to execute it, and may access a buffer | |
739 | * that has already been freed. In the best case, the | |
740 | * hardware will execute it, and the event handler will | |
741 | * ignore the completion event for that TD, since it was | |
742 | * removed from the td_list for that endpoint. In | |
743 | * short, don't muck with the stream ID after | |
744 | * submission. | |
745 | */ | |
746 | xhci_warn(xhci, "WARN Cancelled URB %p " | |
747 | "has invalid stream ID %u.\n", | |
748 | cur_td->urb, | |
749 | cur_td->urb->stream_id); | |
750 | goto remove_finished_td; | |
751 | } | |
ae636747 SS |
752 | /* |
753 | * If we stopped on the TD we need to cancel, then we have to | |
754 | * move the xHC endpoint ring dequeue pointer past this TD. | |
755 | */ | |
63a0d9ab | 756 | if (cur_td == ep->stopped_td) |
e9df17eb SS |
757 | xhci_find_new_dequeue_state(xhci, slot_id, ep_index, |
758 | cur_td->urb->stream_id, | |
759 | cur_td, &deq_state); | |
ae636747 | 760 | else |
522989a2 | 761 | td_to_noop(xhci, ep_ring, cur_td, false); |
e9df17eb | 762 | remove_finished_td: |
ae636747 SS |
763 | /* |
764 | * The event handler won't see a completion for this TD anymore, | |
765 | * so remove it from the endpoint ring's TD list. Keep it in | |
766 | * the cancelled TD list for URB completion later. | |
767 | */ | |
585df1d9 | 768 | list_del_init(&cur_td->td_list); |
ae636747 | 769 | } |
04861f83 | 770 | |
6f5165cf | 771 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 SS |
772 | |
773 | /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */ | |
774 | if (deq_state.new_deq_ptr && deq_state.new_deq_seg) { | |
1e3452e3 HG |
775 | xhci_queue_new_dequeue_state(xhci, slot_id, ep_index, |
776 | ep->stopped_td->urb->stream_id, &deq_state); | |
ac9d8fe7 | 777 | xhci_ring_cmd_db(xhci); |
ae636747 | 778 | } else { |
e9df17eb SS |
779 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
780 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 | 781 | } |
526867c3 | 782 | |
d97b4f8d | 783 | ep->stopped_td = NULL; |
ae636747 SS |
784 | |
785 | /* | |
786 | * Drop the lock and complete the URBs in the cancelled TD list. | |
787 | * New TDs to be cancelled might be added to the end of the list before | |
788 | * we can complete all the URBs for the TDs we already unlinked. | |
789 | * So stop when we've completed the URB for the last TD we unlinked. | |
790 | */ | |
791 | do { | |
04861f83 | 792 | cur_td = list_first_entry(&ep->cancelled_td_list, |
ae636747 | 793 | struct xhci_td, cancelled_td_list); |
585df1d9 | 794 | list_del_init(&cur_td->cancelled_td_list); |
ae636747 SS |
795 | |
796 | /* Clean up the cancelled URB */ | |
ae636747 SS |
797 | /* Doesn't matter what we pass for status, since the core will |
798 | * just overwrite it (because the URB has been unlinked). | |
799 | */ | |
f76a28a6 | 800 | ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb); |
a60f2f2f | 801 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td); |
2a72126d MN |
802 | inc_td_cnt(cur_td->urb); |
803 | if (last_td_in_urb(cur_td)) | |
804 | xhci_giveback_urb_in_irq(xhci, cur_td, 0); | |
ae636747 | 805 | |
6f5165cf SS |
806 | /* Stop processing the cancelled list if the watchdog timer is |
807 | * running. | |
808 | */ | |
809 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
810 | return; | |
ae636747 SS |
811 | } while (cur_td != last_unlinked_td); |
812 | ||
813 | /* Return to the event handler with xhci->lock re-acquired */ | |
814 | } | |
815 | ||
50e8725e SS |
816 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
817 | { | |
818 | struct xhci_td *cur_td; | |
a54cfae3 | 819 | struct xhci_td *tmp; |
50e8725e | 820 | |
a54cfae3 | 821 | list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) { |
50e8725e | 822 | list_del_init(&cur_td->td_list); |
a54cfae3 | 823 | |
50e8725e SS |
824 | if (!list_empty(&cur_td->cancelled_td_list)) |
825 | list_del_init(&cur_td->cancelled_td_list); | |
f9c589e1 | 826 | |
a60f2f2f | 827 | xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); |
2a72126d MN |
828 | |
829 | inc_td_cnt(cur_td->urb); | |
830 | if (last_td_in_urb(cur_td)) | |
831 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
832 | } |
833 | } | |
834 | ||
835 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, | |
836 | int slot_id, int ep_index) | |
837 | { | |
838 | struct xhci_td *cur_td; | |
a54cfae3 | 839 | struct xhci_td *tmp; |
50e8725e SS |
840 | struct xhci_virt_ep *ep; |
841 | struct xhci_ring *ring; | |
842 | ||
843 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
21d0e51b SS |
844 | if ((ep->ep_state & EP_HAS_STREAMS) || |
845 | (ep->ep_state & EP_GETTING_NO_STREAMS)) { | |
846 | int stream_id; | |
847 | ||
848 | for (stream_id = 0; stream_id < ep->stream_info->num_streams; | |
849 | stream_id++) { | |
850 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
851 | "Killing URBs for slot ID %u, ep index %u, stream %u", | |
852 | slot_id, ep_index, stream_id + 1); | |
853 | xhci_kill_ring_urbs(xhci, | |
854 | ep->stream_info->stream_rings[stream_id]); | |
855 | } | |
856 | } else { | |
857 | ring = ep->ring; | |
858 | if (!ring) | |
859 | return; | |
860 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
861 | "Killing URBs for slot ID %u, ep index %u", | |
862 | slot_id, ep_index); | |
863 | xhci_kill_ring_urbs(xhci, ring); | |
864 | } | |
2a72126d | 865 | |
a54cfae3 FB |
866 | list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list, |
867 | cancelled_td_list) { | |
868 | list_del_init(&cur_td->cancelled_td_list); | |
2a72126d | 869 | inc_td_cnt(cur_td->urb); |
a54cfae3 | 870 | |
2a72126d MN |
871 | if (last_td_in_urb(cur_td)) |
872 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
873 | } |
874 | } | |
875 | ||
6f5165cf SS |
876 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
877 | * In this case, we assume the host controller is broken or dying or dead. The | |
878 | * host may still be completing some other events, so we have to be careful to | |
879 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
880 | * through xhci->state. | |
881 | * | |
882 | * The timer may also fire if the host takes a very long time to respond to the | |
883 | * command, and the stop endpoint command completion handler cannot delete the | |
884 | * timer before the timer function is called. Another endpoint cancellation may | |
885 | * sneak in before the timer function can grab the lock, and that may queue | |
886 | * another stop endpoint command and add the timer back. So we cannot use a | |
887 | * simple flag to say whether there is a pending stop endpoint command for a | |
888 | * particular endpoint. | |
889 | * | |
f9926596 MN |
890 | * Instead we use a combination of that flag and checking if a new timer is |
891 | * pending. | |
6f5165cf SS |
892 | */ |
893 | void xhci_stop_endpoint_command_watchdog(unsigned long arg) | |
894 | { | |
895 | struct xhci_hcd *xhci; | |
896 | struct xhci_virt_ep *ep; | |
6f5165cf | 897 | int ret, i, j; |
f43d6231 | 898 | unsigned long flags; |
6f5165cf SS |
899 | |
900 | ep = (struct xhci_virt_ep *) arg; | |
901 | xhci = ep->xhci; | |
902 | ||
f43d6231 | 903 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf | 904 | |
f9926596 MN |
905 | /* bail out if cmd completed but raced with stop ep watchdog timer.*/ |
906 | if (!(ep->ep_state & EP_STOP_CMD_PENDING) || | |
907 | timer_pending(&ep->stop_cmd_timer)) { | |
f43d6231 | 908 | spin_unlock_irqrestore(&xhci->lock, flags); |
f9926596 | 909 | xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit"); |
6f5165cf SS |
910 | return; |
911 | } | |
912 | ||
913 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
914 | xhci_warn(xhci, "Assuming host is dying, halting host.\n"); | |
915 | /* Oops, HC is dead or dying or at least not responding to the stop | |
916 | * endpoint command. | |
917 | */ | |
f9926596 | 918 | |
6f5165cf | 919 | xhci->xhc_state |= XHCI_STATE_DYING; |
f9926596 MN |
920 | ep->ep_state &= ~EP_STOP_CMD_PENDING; |
921 | ||
6f5165cf SS |
922 | /* Disable interrupts from the host controller and start halting it */ |
923 | xhci_quiesce(xhci); | |
f43d6231 | 924 | spin_unlock_irqrestore(&xhci->lock, flags); |
6f5165cf SS |
925 | |
926 | ret = xhci_halt(xhci); | |
927 | ||
f43d6231 | 928 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf SS |
929 | if (ret < 0) { |
930 | /* This is bad; the host is not responding to commands and it's | |
931 | * not allowing itself to be halted. At least interrupts are | |
ac04e6ff | 932 | * disabled. If we call usb_hc_died(), it will attempt to |
6f5165cf SS |
933 | * disconnect all device drivers under this host. Those |
934 | * disconnect() methods will wait for all URBs to be unlinked, | |
935 | * so we must complete them. | |
936 | */ | |
937 | xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n"); | |
938 | xhci_warn(xhci, "Completing active URBs anyway.\n"); | |
939 | /* We could turn all TDs on the rings to no-ops. This won't | |
940 | * help if the host has cached part of the ring, and is slow if | |
941 | * we want to preserve the cycle bit. Skip it and hope the host | |
942 | * doesn't touch the memory. | |
943 | */ | |
944 | } | |
945 | for (i = 0; i < MAX_HC_SLOTS; i++) { | |
946 | if (!xhci->devs[i]) | |
947 | continue; | |
50e8725e SS |
948 | for (j = 0; j < 31; j++) |
949 | xhci_kill_endpoint_urbs(xhci, i, j); | |
6f5165cf | 950 | } |
f43d6231 | 951 | spin_unlock_irqrestore(&xhci->lock, flags); |
aa50b290 XR |
952 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
953 | "Calling usb_hc_died()"); | |
bcf42aa6 | 954 | usb_hc_died(xhci_to_hcd(xhci)); |
aa50b290 XR |
955 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
956 | "xHCI host controller is dead."); | |
6f5165cf SS |
957 | } |
958 | ||
b008df60 AX |
959 | |
960 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, | |
961 | struct xhci_virt_device *dev, | |
962 | struct xhci_ring *ep_ring, | |
963 | unsigned int ep_index) | |
964 | { | |
965 | union xhci_trb *dequeue_temp; | |
966 | int num_trbs_free_temp; | |
967 | bool revert = false; | |
968 | ||
969 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
970 | dequeue_temp = ep_ring->dequeue; | |
971 | ||
0d9f78a9 SS |
972 | /* If we get two back-to-back stalls, and the first stalled transfer |
973 | * ends just before a link TRB, the dequeue pointer will be left on | |
974 | * the link TRB by the code in the while loop. So we have to update | |
975 | * the dequeue pointer one segment further, or we'll jump off | |
976 | * the segment into la-la-land. | |
977 | */ | |
2d98ef40 | 978 | if (trb_is_link(ep_ring->dequeue)) { |
0d9f78a9 SS |
979 | ep_ring->deq_seg = ep_ring->deq_seg->next; |
980 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
981 | } | |
982 | ||
b008df60 AX |
983 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
984 | /* We have more usable TRBs */ | |
985 | ep_ring->num_trbs_free++; | |
986 | ep_ring->dequeue++; | |
2d98ef40 | 987 | if (trb_is_link(ep_ring->dequeue)) { |
b008df60 AX |
988 | if (ep_ring->dequeue == |
989 | dev->eps[ep_index].queued_deq_ptr) | |
990 | break; | |
991 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
992 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
993 | } | |
994 | if (ep_ring->dequeue == dequeue_temp) { | |
995 | revert = true; | |
996 | break; | |
997 | } | |
998 | } | |
999 | ||
1000 | if (revert) { | |
1001 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
1002 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
1003 | } | |
1004 | } | |
1005 | ||
ae636747 SS |
1006 | /* |
1007 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
1008 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
1009 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
1010 | * endpoint doorbell to restart the ring, but only if there aren't more | |
1011 | * cancellations pending. | |
1012 | */ | |
b8200c94 | 1013 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1014 | union xhci_trb *trb, u32 cmd_comp_code) |
ae636747 | 1015 | { |
ae636747 | 1016 | unsigned int ep_index; |
e9df17eb | 1017 | unsigned int stream_id; |
ae636747 SS |
1018 | struct xhci_ring *ep_ring; |
1019 | struct xhci_virt_device *dev; | |
9aad95e2 | 1020 | struct xhci_virt_ep *ep; |
d115b048 JY |
1021 | struct xhci_ep_ctx *ep_ctx; |
1022 | struct xhci_slot_ctx *slot_ctx; | |
ae636747 | 1023 | |
28ccd296 ME |
1024 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
1025 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
ae636747 | 1026 | dev = xhci->devs[slot_id]; |
9aad95e2 | 1027 | ep = &dev->eps[ep_index]; |
e9df17eb SS |
1028 | |
1029 | ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id); | |
1030 | if (!ep_ring) { | |
e587b8b2 | 1031 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
e9df17eb SS |
1032 | stream_id); |
1033 | /* XXX: Harmless??? */ | |
0d4976ec | 1034 | goto cleanup; |
e9df17eb SS |
1035 | } |
1036 | ||
d115b048 JY |
1037 | ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index); |
1038 | slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx); | |
19a7d0d6 FB |
1039 | trace_xhci_handle_cmd_set_deq(slot_ctx); |
1040 | trace_xhci_handle_cmd_set_deq_ep(ep_ctx); | |
ae636747 | 1041 | |
c69a0597 | 1042 | if (cmd_comp_code != COMP_SUCCESS) { |
ae636747 SS |
1043 | unsigned int ep_state; |
1044 | unsigned int slot_state; | |
1045 | ||
c69a0597 | 1046 | switch (cmd_comp_code) { |
0b7c105a | 1047 | case COMP_TRB_ERROR: |
e587b8b2 | 1048 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
ae636747 | 1049 | break; |
0b7c105a | 1050 | case COMP_CONTEXT_STATE_ERROR: |
e587b8b2 | 1051 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
5071e6b2 | 1052 | ep_state = GET_EP_CTX_STATE(ep_ctx); |
28ccd296 | 1053 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 | 1054 | slot_state = GET_SLOT_STATE(slot_state); |
aa50b290 XR |
1055 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1056 | "Slot state = %u, EP state = %u", | |
ae636747 SS |
1057 | slot_state, ep_state); |
1058 | break; | |
0b7c105a | 1059 | case COMP_SLOT_NOT_ENABLED_ERROR: |
e587b8b2 ON |
1060 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
1061 | slot_id); | |
ae636747 SS |
1062 | break; |
1063 | default: | |
e587b8b2 ON |
1064 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
1065 | cmd_comp_code); | |
ae636747 SS |
1066 | break; |
1067 | } | |
1068 | /* OK what do we do now? The endpoint state is hosed, and we | |
1069 | * should never get to this point if the synchronization between | |
1070 | * queueing, and endpoint state are correct. This might happen | |
1071 | * if the device gets disconnected after we've finished | |
1072 | * cancelling URBs, which might not be an error... | |
1073 | */ | |
1074 | } else { | |
9aad95e2 HG |
1075 | u64 deq; |
1076 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ | |
1077 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1078 | struct xhci_stream_ctx *ctx = | |
1079 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1080 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; | |
1081 | } else { | |
1082 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; | |
1083 | } | |
aa50b290 | 1084 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
9aad95e2 HG |
1085 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
1086 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, | |
1087 | ep->queued_deq_ptr) == deq) { | |
bf161e85 SS |
1088 | /* Update the ring's dequeue segment and dequeue pointer |
1089 | * to reflect the new position. | |
1090 | */ | |
b008df60 AX |
1091 | update_ring_for_set_deq_completion(xhci, dev, |
1092 | ep_ring, ep_index); | |
bf161e85 | 1093 | } else { |
e587b8b2 | 1094 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
bf161e85 | 1095 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
9aad95e2 | 1096 | ep->queued_deq_seg, ep->queued_deq_ptr); |
bf161e85 | 1097 | } |
ae636747 SS |
1098 | } |
1099 | ||
0d4976ec | 1100 | cleanup: |
63a0d9ab | 1101 | dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING; |
bf161e85 SS |
1102 | dev->eps[ep_index].queued_deq_seg = NULL; |
1103 | dev->eps[ep_index].queued_deq_ptr = NULL; | |
e9df17eb SS |
1104 | /* Restart any rings with pending URBs */ |
1105 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1106 | } |
1107 | ||
b8200c94 | 1108 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1109 | union xhci_trb *trb, u32 cmd_comp_code) |
a1587d97 | 1110 | { |
19a7d0d6 FB |
1111 | struct xhci_virt_device *vdev; |
1112 | struct xhci_ep_ctx *ep_ctx; | |
a1587d97 SS |
1113 | unsigned int ep_index; |
1114 | ||
28ccd296 | 1115 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
19a7d0d6 FB |
1116 | vdev = xhci->devs[slot_id]; |
1117 | ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); | |
1118 | trace_xhci_handle_cmd_reset_ep(ep_ctx); | |
1119 | ||
a1587d97 SS |
1120 | /* This command will only fail if the endpoint wasn't halted, |
1121 | * but we don't care. | |
1122 | */ | |
a0254324 | 1123 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
c69a0597 | 1124 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
a1587d97 | 1125 | |
ac9d8fe7 SS |
1126 | /* HW with the reset endpoint quirk needs to have a configure endpoint |
1127 | * command complete before the endpoint can be used. Queue that here | |
1128 | * because the HW can't handle two commands being queued in a row. | |
1129 | */ | |
1130 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) { | |
ddba5cd0 MN |
1131 | struct xhci_command *command; |
1132 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
a0ee619f HG |
1133 | if (!command) { |
1134 | xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n"); | |
1135 | return; | |
1136 | } | |
4bdfe4c3 XR |
1137 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1138 | "Queueing configure endpoint command"); | |
ddba5cd0 | 1139 | xhci_queue_configure_endpoint(xhci, command, |
913a8a34 SS |
1140 | xhci->devs[slot_id]->in_ctx->dma, slot_id, |
1141 | false); | |
ac9d8fe7 SS |
1142 | xhci_ring_cmd_db(xhci); |
1143 | } else { | |
c3492dbf | 1144 | /* Clear our internal halted state */ |
63a0d9ab | 1145 | xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED; |
ac9d8fe7 | 1146 | } |
a1587d97 | 1147 | } |
ae636747 | 1148 | |
b244b431 | 1149 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
c2d3d49b | 1150 | struct xhci_command *command, u32 cmd_comp_code) |
b244b431 XR |
1151 | { |
1152 | if (cmd_comp_code == COMP_SUCCESS) | |
c2d3d49b | 1153 | command->slot_id = slot_id; |
b244b431 | 1154 | else |
c2d3d49b | 1155 | command->slot_id = 0; |
b244b431 XR |
1156 | } |
1157 | ||
6c02dd14 XR |
1158 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
1159 | { | |
1160 | struct xhci_virt_device *virt_dev; | |
19a7d0d6 | 1161 | struct xhci_slot_ctx *slot_ctx; |
6c02dd14 XR |
1162 | |
1163 | virt_dev = xhci->devs[slot_id]; | |
1164 | if (!virt_dev) | |
1165 | return; | |
19a7d0d6 FB |
1166 | |
1167 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
1168 | trace_xhci_handle_cmd_disable_slot(slot_ctx); | |
1169 | ||
6c02dd14 XR |
1170 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) |
1171 | /* Delete default control endpoint resources */ | |
1172 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); | |
1173 | xhci_free_virt_device(xhci, slot_id); | |
1174 | } | |
1175 | ||
6ed46d33 XR |
1176 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
1177 | struct xhci_event_cmd *event, u32 cmd_comp_code) | |
1178 | { | |
1179 | struct xhci_virt_device *virt_dev; | |
1180 | struct xhci_input_control_ctx *ctrl_ctx; | |
19a7d0d6 | 1181 | struct xhci_ep_ctx *ep_ctx; |
6ed46d33 XR |
1182 | unsigned int ep_index; |
1183 | unsigned int ep_state; | |
1184 | u32 add_flags, drop_flags; | |
1185 | ||
6ed46d33 XR |
1186 | /* |
1187 | * Configure endpoint commands can come from the USB core | |
1188 | * configuration or alt setting changes, or because the HW | |
1189 | * needed an extra configure endpoint command after a reset | |
1190 | * endpoint command or streams were being configured. | |
1191 | * If the command was for a halted endpoint, the xHCI driver | |
1192 | * is not waiting on the configure endpoint command. | |
1193 | */ | |
9ea1833e | 1194 | virt_dev = xhci->devs[slot_id]; |
4daf9df5 | 1195 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
6ed46d33 XR |
1196 | if (!ctrl_ctx) { |
1197 | xhci_warn(xhci, "Could not get input context, bad type.\n"); | |
1198 | return; | |
1199 | } | |
1200 | ||
1201 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
1202 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
1203 | /* Input ctx add_flags are the endpoint index plus one */ | |
1204 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; | |
1205 | ||
19a7d0d6 FB |
1206 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index); |
1207 | trace_xhci_handle_cmd_config_ep(ep_ctx); | |
1208 | ||
6ed46d33 XR |
1209 | /* A usb_set_interface() call directly after clearing a halted |
1210 | * condition may race on this quirky hardware. Not worth | |
1211 | * worrying about, since this is prototype hardware. Not sure | |
1212 | * if this will work for streams, but streams support was | |
1213 | * untested on this prototype. | |
1214 | */ | |
1215 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
1216 | ep_index != (unsigned int) -1 && | |
1217 | add_flags - SLOT_FLAG == drop_flags) { | |
1218 | ep_state = virt_dev->eps[ep_index].ep_state; | |
1219 | if (!(ep_state & EP_HALTED)) | |
ddba5cd0 | 1220 | return; |
6ed46d33 XR |
1221 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1222 | "Completed config ep cmd - " | |
1223 | "last ep index = %d, state = %d", | |
1224 | ep_index, ep_state); | |
1225 | /* Clear internal halted state and restart ring(s) */ | |
1226 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; | |
1227 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
1228 | return; | |
1229 | } | |
6ed46d33 XR |
1230 | return; |
1231 | } | |
1232 | ||
19a7d0d6 FB |
1233 | static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id) |
1234 | { | |
1235 | struct xhci_virt_device *vdev; | |
1236 | struct xhci_slot_ctx *slot_ctx; | |
1237 | ||
1238 | vdev = xhci->devs[slot_id]; | |
1239 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); | |
1240 | trace_xhci_handle_cmd_addr_dev(slot_ctx); | |
1241 | } | |
1242 | ||
f681321b XR |
1243 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id, |
1244 | struct xhci_event_cmd *event) | |
1245 | { | |
19a7d0d6 FB |
1246 | struct xhci_virt_device *vdev; |
1247 | struct xhci_slot_ctx *slot_ctx; | |
1248 | ||
1249 | vdev = xhci->devs[slot_id]; | |
1250 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); | |
1251 | trace_xhci_handle_cmd_reset_dev(slot_ctx); | |
1252 | ||
f681321b | 1253 | xhci_dbg(xhci, "Completed reset device command.\n"); |
9ea1833e | 1254 | if (!xhci->devs[slot_id]) |
f681321b XR |
1255 | xhci_warn(xhci, "Reset device command completion " |
1256 | "for disabled slot %u\n", slot_id); | |
1257 | } | |
1258 | ||
2c070821 XR |
1259 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
1260 | struct xhci_event_cmd *event) | |
1261 | { | |
1262 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
f4c8f03c | 1263 | xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n"); |
2c070821 XR |
1264 | return; |
1265 | } | |
1266 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1267 | "NEC firmware version %2x.%02x", | |
1268 | NEC_FW_MAJOR(le32_to_cpu(event->status)), | |
1269 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
1270 | } | |
1271 | ||
9ea1833e | 1272 | static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) |
c9aa1a2d MN |
1273 | { |
1274 | list_del(&cmd->cmd_list); | |
9ea1833e MN |
1275 | |
1276 | if (cmd->completion) { | |
1277 | cmd->status = status; | |
1278 | complete(cmd->completion); | |
1279 | } else { | |
c9aa1a2d | 1280 | kfree(cmd); |
9ea1833e | 1281 | } |
c9aa1a2d MN |
1282 | } |
1283 | ||
1284 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci) | |
1285 | { | |
1286 | struct xhci_command *cur_cmd, *tmp_cmd; | |
1287 | list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) | |
0b7c105a | 1288 | xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED); |
c9aa1a2d MN |
1289 | } |
1290 | ||
cb4d5ce5 | 1291 | void xhci_handle_command_timeout(struct work_struct *work) |
c311e391 MN |
1292 | { |
1293 | struct xhci_hcd *xhci; | |
1294 | int ret; | |
1295 | unsigned long flags; | |
1296 | u64 hw_ring_state; | |
cb4d5ce5 OH |
1297 | |
1298 | xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer); | |
c311e391 | 1299 | |
c311e391 | 1300 | spin_lock_irqsave(&xhci->lock, flags); |
2b985467 | 1301 | |
a5a1b951 MN |
1302 | /* |
1303 | * If timeout work is pending, or current_cmd is NULL, it means we | |
1304 | * raced with command completion. Command is handled so just return. | |
1305 | */ | |
cb4d5ce5 | 1306 | if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) { |
2b985467 LB |
1307 | spin_unlock_irqrestore(&xhci->lock, flags); |
1308 | return; | |
c311e391 | 1309 | } |
2b985467 | 1310 | /* mark this command to be cancelled */ |
0b7c105a | 1311 | xhci->current_cmd->status = COMP_COMMAND_ABORTED; |
2b985467 | 1312 | |
c311e391 MN |
1313 | /* Make sure command ring is running before aborting it */ |
1314 | hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | |
1315 | if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && | |
1316 | (hw_ring_state & CMD_RING_RUNNING)) { | |
1c111b6c OH |
1317 | /* Prevent new doorbell, and start command abort */ |
1318 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; | |
c311e391 | 1319 | xhci_dbg(xhci, "Command timeout\n"); |
1c111b6c | 1320 | ret = xhci_abort_cmd_ring(xhci, flags); |
c311e391 MN |
1321 | if (unlikely(ret == -ESHUTDOWN)) { |
1322 | xhci_err(xhci, "Abort command ring failed\n"); | |
1323 | xhci_cleanup_command_queue(xhci); | |
4dea7077 | 1324 | spin_unlock_irqrestore(&xhci->lock, flags); |
c311e391 MN |
1325 | usb_hc_died(xhci_to_hcd(xhci)->primary_hcd); |
1326 | xhci_dbg(xhci, "xHCI host controller is dead.\n"); | |
4dea7077 LB |
1327 | |
1328 | return; | |
c311e391 | 1329 | } |
4dea7077 LB |
1330 | |
1331 | goto time_out_completed; | |
c311e391 | 1332 | } |
3425aa03 | 1333 | |
1c111b6c OH |
1334 | /* host removed. Bail out */ |
1335 | if (xhci->xhc_state & XHCI_STATE_REMOVING) { | |
1336 | xhci_dbg(xhci, "host removed, ring start fail?\n"); | |
3425aa03 | 1337 | xhci_cleanup_command_queue(xhci); |
4dea7077 LB |
1338 | |
1339 | goto time_out_completed; | |
3425aa03 MN |
1340 | } |
1341 | ||
c311e391 MN |
1342 | /* command timeout on stopped ring, ring can't be aborted */ |
1343 | xhci_dbg(xhci, "Command timeout on stopped ring\n"); | |
1344 | xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); | |
4dea7077 LB |
1345 | |
1346 | time_out_completed: | |
c311e391 MN |
1347 | spin_unlock_irqrestore(&xhci->lock, flags); |
1348 | return; | |
1349 | } | |
1350 | ||
7f84eef0 SS |
1351 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1352 | struct xhci_event_cmd *event) | |
1353 | { | |
28ccd296 | 1354 | int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1355 | u64 cmd_dma; |
1356 | dma_addr_t cmd_dequeue_dma; | |
e7a79a1d | 1357 | u32 cmd_comp_code; |
9124b121 | 1358 | union xhci_trb *cmd_trb; |
c9aa1a2d | 1359 | struct xhci_command *cmd; |
b54fc46d | 1360 | u32 cmd_type; |
7f84eef0 | 1361 | |
28ccd296 | 1362 | cmd_dma = le64_to_cpu(event->cmd_trb); |
9124b121 | 1363 | cmd_trb = xhci->cmd_ring->dequeue; |
a37c3f76 FB |
1364 | |
1365 | trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic); | |
1366 | ||
23e3be11 | 1367 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
9124b121 | 1368 | cmd_trb); |
f4c8f03c LB |
1369 | /* |
1370 | * Check whether the completion event is for our internal kept | |
1371 | * command. | |
1372 | */ | |
1373 | if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) { | |
1374 | xhci_warn(xhci, | |
1375 | "ERROR mismatched command completion event\n"); | |
7f84eef0 SS |
1376 | return; |
1377 | } | |
b63f4053 | 1378 | |
04861f83 | 1379 | cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list); |
c9aa1a2d | 1380 | |
cb4d5ce5 | 1381 | cancel_delayed_work(&xhci->cmd_timer); |
c311e391 | 1382 | |
e7a79a1d | 1383 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
c311e391 MN |
1384 | |
1385 | /* If CMD ring stopped we own the trbs between enqueue and dequeue */ | |
0b7c105a | 1386 | if (cmd_comp_code == COMP_STOPPED) { |
1c111b6c | 1387 | complete_all(&xhci->cmd_ring_stop_completion); |
c311e391 MN |
1388 | return; |
1389 | } | |
33be1265 MN |
1390 | |
1391 | if (cmd->command_trb != xhci->cmd_ring->dequeue) { | |
1392 | xhci_err(xhci, | |
1393 | "Command completion event does not match command\n"); | |
1394 | return; | |
1395 | } | |
1396 | ||
c311e391 MN |
1397 | /* |
1398 | * Host aborted the command ring, check if the current command was | |
1399 | * supposed to be aborted, otherwise continue normally. | |
1400 | * The command ring is stopped now, but the xHC will issue a Command | |
1401 | * Ring Stopped event which will cause us to restart it. | |
1402 | */ | |
0b7c105a | 1403 | if (cmd_comp_code == COMP_COMMAND_ABORTED) { |
c311e391 | 1404 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; |
0b7c105a | 1405 | if (cmd->status == COMP_COMMAND_ABORTED) { |
2a7cfdf3 BW |
1406 | if (xhci->current_cmd == cmd) |
1407 | xhci->current_cmd = NULL; | |
c311e391 | 1408 | goto event_handled; |
2a7cfdf3 | 1409 | } |
b63f4053 EF |
1410 | } |
1411 | ||
b54fc46d XR |
1412 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
1413 | switch (cmd_type) { | |
1414 | case TRB_ENABLE_SLOT: | |
c2d3d49b | 1415 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code); |
3ffbba95 | 1416 | break; |
b54fc46d | 1417 | case TRB_DISABLE_SLOT: |
6c02dd14 | 1418 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
3ffbba95 | 1419 | break; |
b54fc46d | 1420 | case TRB_CONFIG_EP: |
9ea1833e MN |
1421 | if (!cmd->completion) |
1422 | xhci_handle_cmd_config_ep(xhci, slot_id, event, | |
1423 | cmd_comp_code); | |
f94e0186 | 1424 | break; |
b54fc46d | 1425 | case TRB_EVAL_CONTEXT: |
2d3f1fac | 1426 | break; |
b54fc46d | 1427 | case TRB_ADDR_DEV: |
19a7d0d6 | 1428 | xhci_handle_cmd_addr_dev(xhci, slot_id); |
3ffbba95 | 1429 | break; |
b54fc46d | 1430 | case TRB_STOP_RING: |
b8200c94 XR |
1431 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1432 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
1433 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event); | |
ae636747 | 1434 | break; |
b54fc46d | 1435 | case TRB_SET_DEQ: |
b8200c94 XR |
1436 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1437 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1438 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
ae636747 | 1439 | break; |
b54fc46d | 1440 | case TRB_CMD_NOOP: |
c311e391 | 1441 | /* Is this an aborted command turned to NO-OP? */ |
0b7c105a FB |
1442 | if (cmd->status == COMP_STOPPED) |
1443 | cmd_comp_code = COMP_STOPPED; | |
7f84eef0 | 1444 | break; |
b54fc46d | 1445 | case TRB_RESET_EP: |
b8200c94 XR |
1446 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1447 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1448 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
a1587d97 | 1449 | break; |
b54fc46d | 1450 | case TRB_RESET_DEV: |
6fcfb0d6 MN |
1451 | /* SLOT_ID field in reset device cmd completion event TRB is 0. |
1452 | * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) | |
1453 | */ | |
1454 | slot_id = TRB_TO_SLOT_ID( | |
1455 | le32_to_cpu(cmd_trb->generic.field[3])); | |
f681321b | 1456 | xhci_handle_cmd_reset_dev(xhci, slot_id, event); |
2a8f82c4 | 1457 | break; |
b54fc46d | 1458 | case TRB_NEC_GET_FW: |
2c070821 | 1459 | xhci_handle_cmd_nec_get_fw(xhci, event); |
0238634d | 1460 | break; |
7f84eef0 SS |
1461 | default: |
1462 | /* Skip over unknown commands on the event ring */ | |
f4c8f03c | 1463 | xhci_info(xhci, "INFO unknown command type %d\n", cmd_type); |
7f84eef0 SS |
1464 | break; |
1465 | } | |
c9aa1a2d | 1466 | |
c311e391 | 1467 | /* restart timer if this wasn't the last command */ |
daa47f21 | 1468 | if (!list_is_singular(&xhci->cmd_list)) { |
04861f83 FB |
1469 | xhci->current_cmd = list_first_entry(&cmd->cmd_list, |
1470 | struct xhci_command, cmd_list); | |
cb4d5ce5 | 1471 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
2b985467 LB |
1472 | } else if (xhci->current_cmd == cmd) { |
1473 | xhci->current_cmd = NULL; | |
c311e391 MN |
1474 | } |
1475 | ||
1476 | event_handled: | |
9ea1833e | 1477 | xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); |
c9aa1a2d | 1478 | |
3b72fca0 | 1479 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1480 | } |
1481 | ||
0238634d SS |
1482 | static void handle_vendor_event(struct xhci_hcd *xhci, |
1483 | union xhci_trb *event) | |
1484 | { | |
1485 | u32 trb_type; | |
1486 | ||
28ccd296 | 1487 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3])); |
0238634d SS |
1488 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1489 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1490 | handle_cmd_completion(xhci, &event->event_cmd); | |
1491 | } | |
1492 | ||
f6ff0ac8 SS |
1493 | /* @port_id: the one-based port ID from the hardware (indexed from array of all |
1494 | * port registers -- USB 3.0 and USB 2.0). | |
1495 | * | |
1496 | * Returns a zero-based port number, which is suitable for indexing into each of | |
1497 | * the split roothubs' port arrays and bus state arrays. | |
d0cd5d48 | 1498 | * Add one to it in order to call xhci_find_slot_id_by_port. |
f6ff0ac8 SS |
1499 | */ |
1500 | static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd, | |
1501 | struct xhci_hcd *xhci, u32 port_id) | |
1502 | { | |
1503 | unsigned int i; | |
1504 | unsigned int num_similar_speed_ports = 0; | |
1505 | ||
1506 | /* port_id from the hardware is 1-based, but port_array[], usb3_ports[], | |
1507 | * and usb2_ports are 0-based indexes. Count the number of similar | |
1508 | * speed ports, up to 1 port before this port. | |
1509 | */ | |
1510 | for (i = 0; i < (port_id - 1); i++) { | |
1511 | u8 port_speed = xhci->port_array[i]; | |
1512 | ||
1513 | /* | |
1514 | * Skip ports that don't have known speeds, or have duplicate | |
1515 | * Extended Capabilities port speed entries. | |
1516 | */ | |
22e04870 | 1517 | if (port_speed == 0 || port_speed == DUPLICATE_ENTRY) |
f6ff0ac8 SS |
1518 | continue; |
1519 | ||
1520 | /* | |
1521 | * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and | |
1522 | * 1.1 ports are under the USB 2.0 hub. If the port speed | |
1523 | * matches the device speed, it's a similar speed port. | |
1524 | */ | |
b50107bb | 1525 | if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3)) |
f6ff0ac8 SS |
1526 | num_similar_speed_ports++; |
1527 | } | |
1528 | return num_similar_speed_ports; | |
1529 | } | |
1530 | ||
623bef9e SS |
1531 | static void handle_device_notification(struct xhci_hcd *xhci, |
1532 | union xhci_trb *event) | |
1533 | { | |
1534 | u32 slot_id; | |
4ee823b8 | 1535 | struct usb_device *udev; |
623bef9e | 1536 | |
7e76ad43 | 1537 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
4ee823b8 | 1538 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1539 | xhci_warn(xhci, "Device Notification event for " |
1540 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1541 | return; |
1542 | } | |
1543 | ||
1544 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1545 | slot_id); | |
1546 | udev = xhci->devs[slot_id]->udev; | |
1547 | if (udev && udev->parent) | |
1548 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1549 | } |
1550 | ||
0f2a7930 SS |
1551 | static void handle_port_status(struct xhci_hcd *xhci, |
1552 | union xhci_trb *event) | |
1553 | { | |
f6ff0ac8 | 1554 | struct usb_hcd *hcd; |
0f2a7930 | 1555 | u32 port_id; |
56192531 | 1556 | u32 temp, temp1; |
518e848e | 1557 | int max_ports; |
56192531 | 1558 | int slot_id; |
5308a91b | 1559 | unsigned int faked_port_index; |
f6ff0ac8 | 1560 | u8 major_revision; |
20b67cf5 | 1561 | struct xhci_bus_state *bus_state; |
28ccd296 | 1562 | __le32 __iomem **port_array; |
386139d7 | 1563 | bool bogus_port_status = false; |
0f2a7930 SS |
1564 | |
1565 | /* Port status change events always have a successful completion code */ | |
f4c8f03c LB |
1566 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) |
1567 | xhci_warn(xhci, | |
1568 | "WARN: xHC returned failed port status event\n"); | |
1569 | ||
28ccd296 | 1570 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
0f2a7930 SS |
1571 | xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id); |
1572 | ||
518e848e SS |
1573 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
1574 | if ((port_id <= 0) || (port_id > max_ports)) { | |
56192531 | 1575 | xhci_warn(xhci, "Invalid port id %d\n", port_id); |
09ce0c0c PC |
1576 | inc_deq(xhci, xhci->event_ring); |
1577 | return; | |
56192531 AX |
1578 | } |
1579 | ||
f6ff0ac8 SS |
1580 | /* Figure out which usb_hcd this port is attached to: |
1581 | * is it a USB 3.0 port or a USB 2.0/1.1 port? | |
1582 | */ | |
1583 | major_revision = xhci->port_array[port_id - 1]; | |
09ce0c0c PC |
1584 | |
1585 | /* Find the right roothub. */ | |
1586 | hcd = xhci_to_hcd(xhci); | |
b50107bb | 1587 | if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3)) |
09ce0c0c PC |
1588 | hcd = xhci->shared_hcd; |
1589 | ||
f6ff0ac8 SS |
1590 | if (major_revision == 0) { |
1591 | xhci_warn(xhci, "Event for port %u not in " | |
1592 | "Extended Capabilities, ignoring.\n", | |
1593 | port_id); | |
386139d7 | 1594 | bogus_port_status = true; |
f6ff0ac8 | 1595 | goto cleanup; |
5308a91b | 1596 | } |
22e04870 | 1597 | if (major_revision == DUPLICATE_ENTRY) { |
f6ff0ac8 SS |
1598 | xhci_warn(xhci, "Event for port %u duplicated in" |
1599 | "Extended Capabilities, ignoring.\n", | |
1600 | port_id); | |
386139d7 | 1601 | bogus_port_status = true; |
f6ff0ac8 SS |
1602 | goto cleanup; |
1603 | } | |
1604 | ||
1605 | /* | |
1606 | * Hardware port IDs reported by a Port Status Change Event include USB | |
1607 | * 3.0 and USB 2.0 ports. We want to check if the port has reported a | |
1608 | * resume event, but we first need to translate the hardware port ID | |
1609 | * into the index into the ports on the correct split roothub, and the | |
1610 | * correct bus_state structure. | |
1611 | */ | |
f6ff0ac8 | 1612 | bus_state = &xhci->bus_state[hcd_index(hcd)]; |
b50107bb | 1613 | if (hcd->speed >= HCD_USB3) |
f6ff0ac8 SS |
1614 | port_array = xhci->usb3_ports; |
1615 | else | |
1616 | port_array = xhci->usb2_ports; | |
1617 | /* Find the faked port hub number */ | |
1618 | faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci, | |
1619 | port_id); | |
5308a91b | 1620 | |
b0ba9720 | 1621 | temp = readl(port_array[faked_port_index]); |
7111ebc9 | 1622 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1623 | xhci_dbg(xhci, "resume root hub\n"); |
1624 | usb_hcd_resume_root_hub(hcd); | |
1625 | } | |
1626 | ||
b50107bb | 1627 | if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE) |
fac4271d ZJC |
1628 | bus_state->port_remote_wakeup &= ~(1 << faked_port_index); |
1629 | ||
56192531 AX |
1630 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) { |
1631 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); | |
1632 | ||
b0ba9720 | 1633 | temp1 = readl(&xhci->op_regs->command); |
56192531 AX |
1634 | if (!(temp1 & CMD_RUN)) { |
1635 | xhci_warn(xhci, "xHC is not running.\n"); | |
1636 | goto cleanup; | |
1637 | } | |
1638 | ||
2338b9e4 | 1639 | if (DEV_SUPERSPEED_ANY(temp)) { |
d93814cf | 1640 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1641 | /* Set a flag to say the port signaled remote wakeup, |
1642 | * so we can tell the difference between the end of | |
1643 | * device and host initiated resume. | |
1644 | */ | |
1645 | bus_state->port_remote_wakeup |= 1 << faked_port_index; | |
d93814cf SS |
1646 | xhci_test_and_clear_bit(xhci, port_array, |
1647 | faked_port_index, PORT_PLC); | |
c9682dff AX |
1648 | xhci_set_link_state(xhci, port_array, faked_port_index, |
1649 | XDEV_U0); | |
d93814cf SS |
1650 | /* Need to wait until the next link state change |
1651 | * indicates the device is actually in U0. | |
1652 | */ | |
1653 | bogus_port_status = true; | |
1654 | goto cleanup; | |
f69115fd MN |
1655 | } else if (!test_bit(faked_port_index, |
1656 | &bus_state->resuming_ports)) { | |
56192531 | 1657 | xhci_dbg(xhci, "resume HS port %d\n", port_id); |
f6ff0ac8 | 1658 | bus_state->resume_done[faked_port_index] = jiffies + |
b9e45188 | 1659 | msecs_to_jiffies(USB_RESUME_TIMEOUT); |
f370b996 | 1660 | set_bit(faked_port_index, &bus_state->resuming_ports); |
56192531 | 1661 | mod_timer(&hcd->rh_timer, |
f6ff0ac8 | 1662 | bus_state->resume_done[faked_port_index]); |
56192531 AX |
1663 | /* Do the rest in GetPortStatus */ |
1664 | } | |
1665 | } | |
d93814cf SS |
1666 | |
1667 | if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 && | |
2338b9e4 | 1668 | DEV_SUPERSPEED_ANY(temp)) { |
d93814cf | 1669 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); |
4ee823b8 SS |
1670 | /* We've just brought the device into U0 through either the |
1671 | * Resume state after a device remote wakeup, or through the | |
1672 | * U3Exit state after a host-initiated resume. If it's a device | |
1673 | * initiated remote wake, don't pass up the link state change, | |
1674 | * so the roothub behavior is consistent with external | |
1675 | * USB 3.0 hub behavior. | |
1676 | */ | |
d93814cf SS |
1677 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, |
1678 | faked_port_index + 1); | |
1679 | if (slot_id && xhci->devs[slot_id]) | |
1680 | xhci_ring_device(xhci, slot_id); | |
ba7b5c22 | 1681 | if (bus_state->port_remote_wakeup & (1 << faked_port_index)) { |
4ee823b8 SS |
1682 | bus_state->port_remote_wakeup &= |
1683 | ~(1 << faked_port_index); | |
1684 | xhci_test_and_clear_bit(xhci, port_array, | |
1685 | faked_port_index, PORT_PLC); | |
1686 | usb_wakeup_notification(hcd->self.root_hub, | |
1687 | faked_port_index + 1); | |
1688 | bogus_port_status = true; | |
1689 | goto cleanup; | |
1690 | } | |
d93814cf | 1691 | } |
56192531 | 1692 | |
8b3d4570 SS |
1693 | /* |
1694 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or | |
1695 | * RExit to a disconnect state). If so, let the the driver know it's | |
1696 | * out of the RExit state. | |
1697 | */ | |
2338b9e4 | 1698 | if (!DEV_SUPERSPEED_ANY(temp) && |
8b3d4570 SS |
1699 | test_and_clear_bit(faked_port_index, |
1700 | &bus_state->rexit_ports)) { | |
1701 | complete(&bus_state->rexit_done[faked_port_index]); | |
1702 | bogus_port_status = true; | |
1703 | goto cleanup; | |
1704 | } | |
1705 | ||
b50107bb | 1706 | if (hcd->speed < HCD_USB3) |
6fd45621 AX |
1707 | xhci_test_and_clear_bit(xhci, port_array, faked_port_index, |
1708 | PORT_PLC); | |
1709 | ||
56192531 | 1710 | cleanup: |
0f2a7930 | 1711 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 1712 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 1713 | |
386139d7 SS |
1714 | /* Don't make the USB core poll the roothub if we got a bad port status |
1715 | * change event. Besides, at that point we can't tell which roothub | |
1716 | * (USB 2.0 or USB 3.0) to kick. | |
1717 | */ | |
1718 | if (bogus_port_status) | |
1719 | return; | |
1720 | ||
c52804a4 SS |
1721 | /* |
1722 | * xHCI port-status-change events occur when the "or" of all the | |
1723 | * status-change bits in the portsc register changes from 0 to 1. | |
1724 | * New status changes won't cause an event if any other change | |
1725 | * bits are still set. When an event occurs, switch over to | |
1726 | * polling to avoid losing status changes. | |
1727 | */ | |
1728 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
1729 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
0f2a7930 SS |
1730 | spin_unlock(&xhci->lock); |
1731 | /* Pass this up to the core */ | |
f6ff0ac8 | 1732 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
1733 | spin_lock(&xhci->lock); |
1734 | } | |
1735 | ||
d0e96f5a SS |
1736 | /* |
1737 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
1738 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
1739 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
1740 | * returns 0. | |
1741 | */ | |
cffb9be8 HG |
1742 | struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, |
1743 | struct xhci_segment *start_seg, | |
d0e96f5a SS |
1744 | union xhci_trb *start_trb, |
1745 | union xhci_trb *end_trb, | |
cffb9be8 HG |
1746 | dma_addr_t suspect_dma, |
1747 | bool debug) | |
d0e96f5a SS |
1748 | { |
1749 | dma_addr_t start_dma; | |
1750 | dma_addr_t end_seg_dma; | |
1751 | dma_addr_t end_trb_dma; | |
1752 | struct xhci_segment *cur_seg; | |
1753 | ||
23e3be11 | 1754 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
1755 | cur_seg = start_seg; |
1756 | ||
1757 | do { | |
2fa88daa | 1758 | if (start_dma == 0) |
326b4810 | 1759 | return NULL; |
ae636747 | 1760 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 1761 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 1762 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 1763 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 1764 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a | 1765 | |
cffb9be8 HG |
1766 | if (debug) |
1767 | xhci_warn(xhci, | |
1768 | "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", | |
1769 | (unsigned long long)suspect_dma, | |
1770 | (unsigned long long)start_dma, | |
1771 | (unsigned long long)end_trb_dma, | |
1772 | (unsigned long long)cur_seg->dma, | |
1773 | (unsigned long long)end_seg_dma); | |
1774 | ||
d0e96f5a SS |
1775 | if (end_trb_dma > 0) { |
1776 | /* The end TRB is in this segment, so suspect should be here */ | |
1777 | if (start_dma <= end_trb_dma) { | |
1778 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
1779 | return cur_seg; | |
1780 | } else { | |
1781 | /* Case for one segment with | |
1782 | * a TD wrapped around to the top | |
1783 | */ | |
1784 | if ((suspect_dma >= start_dma && | |
1785 | suspect_dma <= end_seg_dma) || | |
1786 | (suspect_dma >= cur_seg->dma && | |
1787 | suspect_dma <= end_trb_dma)) | |
1788 | return cur_seg; | |
1789 | } | |
326b4810 | 1790 | return NULL; |
d0e96f5a SS |
1791 | } else { |
1792 | /* Might still be somewhere in this segment */ | |
1793 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
1794 | return cur_seg; | |
1795 | } | |
1796 | cur_seg = cur_seg->next; | |
23e3be11 | 1797 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 1798 | } while (cur_seg != start_seg); |
d0e96f5a | 1799 | |
326b4810 | 1800 | return NULL; |
d0e96f5a SS |
1801 | } |
1802 | ||
bcef3fd5 SS |
1803 | static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci, |
1804 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb | 1805 | unsigned int stream_id, |
f97c08ae | 1806 | struct xhci_td *td, union xhci_trb *ep_trb) |
bcef3fd5 SS |
1807 | { |
1808 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; | |
ddba5cd0 MN |
1809 | struct xhci_command *command; |
1810 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
1811 | if (!command) | |
1812 | return; | |
1813 | ||
d0167ad2 | 1814 | ep->ep_state |= EP_HALTED; |
e9df17eb | 1815 | ep->stopped_stream = stream_id; |
1624ae1c | 1816 | |
ddba5cd0 | 1817 | xhci_queue_reset_ep(xhci, command, slot_id, ep_index); |
d97b4f8d | 1818 | xhci_cleanup_stalled_ring(xhci, ep_index, td); |
1624ae1c | 1819 | |
5e5cf6fc | 1820 | ep->stopped_stream = 0; |
1624ae1c | 1821 | |
bcef3fd5 SS |
1822 | xhci_ring_cmd_db(xhci); |
1823 | } | |
1824 | ||
1825 | /* Check if an error has halted the endpoint ring. The class driver will | |
1826 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
1827 | * However, a babble and other errors also halt the endpoint ring, and the class | |
1828 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
1829 | * Ring Dequeue Pointer command manually. | |
1830 | */ | |
1831 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
1832 | struct xhci_ep_ctx *ep_ctx, | |
1833 | unsigned int trb_comp_code) | |
1834 | { | |
1835 | /* TRB completion codes that may require a manual halt cleanup */ | |
0b7c105a FB |
1836 | if (trb_comp_code == COMP_USB_TRANSACTION_ERROR || |
1837 | trb_comp_code == COMP_BABBLE_DETECTED_ERROR || | |
1838 | trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR) | |
d4fc8bf5 | 1839 | /* The 0.95 spec says a babbling control endpoint |
bcef3fd5 SS |
1840 | * is not halted. The 0.96 spec says it is. Some HW |
1841 | * claims to be 0.95 compliant, but it halts the control | |
1842 | * endpoint anyway. Check if a babble halted the | |
1843 | * endpoint. | |
1844 | */ | |
5071e6b2 | 1845 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED) |
bcef3fd5 SS |
1846 | return 1; |
1847 | ||
1848 | return 0; | |
1849 | } | |
1850 | ||
b45b5069 SS |
1851 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
1852 | { | |
1853 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
1854 | /* Vendor defined "informational" completion code, | |
1855 | * treat as not-an-error. | |
1856 | */ | |
1857 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
1858 | trb_comp_code); | |
1859 | xhci_dbg(xhci, "Treating code as success.\n"); | |
1860 | return 1; | |
1861 | } | |
1862 | return 0; | |
1863 | } | |
1864 | ||
55fa4396 FB |
1865 | static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td, |
1866 | struct xhci_ring *ep_ring, int *status) | |
1867 | { | |
1868 | struct urb_priv *urb_priv; | |
1869 | struct urb *urb = NULL; | |
1870 | ||
1871 | /* Clean up the endpoint's TD list */ | |
1872 | urb = td->urb; | |
1873 | urb_priv = urb->hcpriv; | |
1874 | ||
1875 | /* if a bounce buffer was used to align this td then unmap it */ | |
a60f2f2f | 1876 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); |
55fa4396 FB |
1877 | |
1878 | /* Do one last check of the actual transfer length. | |
1879 | * If the host controller said we transferred more data than the buffer | |
1880 | * length, urb->actual_length will be a very big number (since it's | |
1881 | * unsigned). Play it safe and say we didn't transfer anything. | |
1882 | */ | |
1883 | if (urb->actual_length > urb->transfer_buffer_length) { | |
1884 | xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", | |
1885 | urb->transfer_buffer_length, urb->actual_length); | |
1886 | urb->actual_length = 0; | |
1887 | *status = 0; | |
1888 | } | |
1889 | list_del_init(&td->td_list); | |
1890 | /* Was this TD slated to be cancelled but completed anyway? */ | |
1891 | if (!list_empty(&td->cancelled_td_list)) | |
1892 | list_del_init(&td->cancelled_td_list); | |
1893 | ||
1894 | inc_td_cnt(urb); | |
1895 | /* Giveback the urb when all the tds are completed */ | |
1896 | if (last_td_in_urb(td)) { | |
1897 | if ((urb->actual_length != urb->transfer_buffer_length && | |
1898 | (urb->transfer_flags & URB_SHORT_NOT_OK)) || | |
1899 | (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) | |
1900 | xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", | |
1901 | urb, urb->actual_length, | |
1902 | urb->transfer_buffer_length, *status); | |
1903 | ||
1904 | /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ | |
1905 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
1906 | *status = 0; | |
1907 | xhci_giveback_urb_in_irq(xhci, td, *status); | |
1908 | } | |
1909 | ||
1910 | return 0; | |
1911 | } | |
1912 | ||
4422da61 | 1913 | static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td, |
f97c08ae | 1914 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
4422da61 AX |
1915 | struct xhci_virt_ep *ep, int *status, bool skip) |
1916 | { | |
1917 | struct xhci_virt_device *xdev; | |
4422da61 | 1918 | struct xhci_ep_ctx *ep_ctx; |
be0f50c2 | 1919 | struct xhci_ring *ep_ring; |
be0f50c2 | 1920 | unsigned int slot_id; |
4422da61 | 1921 | u32 trb_comp_code; |
be0f50c2 | 1922 | int ep_index; |
4422da61 | 1923 | |
28ccd296 | 1924 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
4422da61 | 1925 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1926 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
1927 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
4422da61 | 1928 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 1929 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
4422da61 AX |
1930 | |
1931 | if (skip) | |
1932 | goto td_cleanup; | |
1933 | ||
0b7c105a FB |
1934 | if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID || |
1935 | trb_comp_code == COMP_STOPPED || | |
1936 | trb_comp_code == COMP_STOPPED_SHORT_PACKET) { | |
4422da61 AX |
1937 | /* The Endpoint Stop Command completion will take care of any |
1938 | * stopped TDs. A stopped TD may be restarted, so don't update | |
1939 | * the ring dequeue pointer or take this TD off any lists yet. | |
1940 | */ | |
1941 | ep->stopped_td = td; | |
4422da61 | 1942 | return 0; |
69defe04 | 1943 | } |
0b7c105a | 1944 | if (trb_comp_code == COMP_STALL_ERROR || |
69defe04 MN |
1945 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, |
1946 | trb_comp_code)) { | |
1947 | /* Issue a reset endpoint command to clear the host side | |
1948 | * halt, followed by a set dequeue command to move the | |
1949 | * dequeue pointer past the TD. | |
1950 | * The class driver clears the device side halt later. | |
1951 | */ | |
1952 | xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, | |
f97c08ae | 1953 | ep_ring->stream_id, td, ep_trb); |
4422da61 | 1954 | } else { |
69defe04 MN |
1955 | /* Update ring dequeue pointer */ |
1956 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 | 1957 | inc_deq(xhci, ep_ring); |
69defe04 MN |
1958 | inc_deq(xhci, ep_ring); |
1959 | } | |
4422da61 AX |
1960 | |
1961 | td_cleanup: | |
55fa4396 | 1962 | return xhci_td_cleanup(xhci, td, ep_ring, status); |
4422da61 AX |
1963 | } |
1964 | ||
30a65b45 MN |
1965 | /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */ |
1966 | static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
1967 | union xhci_trb *stop_trb) | |
1968 | { | |
1969 | u32 sum; | |
1970 | union xhci_trb *trb = ring->dequeue; | |
1971 | struct xhci_segment *seg = ring->deq_seg; | |
1972 | ||
1973 | for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) { | |
1974 | if (!trb_is_noop(trb) && !trb_is_link(trb)) | |
1975 | sum += TRB_LEN(le32_to_cpu(trb->generic.field[2])); | |
1976 | } | |
1977 | return sum; | |
1978 | } | |
1979 | ||
8af56be1 AX |
1980 | /* |
1981 | * Process control tds, update urb status and actual_length. | |
1982 | */ | |
1983 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 1984 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
8af56be1 AX |
1985 | struct xhci_virt_ep *ep, int *status) |
1986 | { | |
1987 | struct xhci_virt_device *xdev; | |
1988 | struct xhci_ring *ep_ring; | |
1989 | unsigned int slot_id; | |
1990 | int ep_index; | |
1991 | struct xhci_ep_ctx *ep_ctx; | |
1992 | u32 trb_comp_code; | |
0b6c324c | 1993 | u32 remaining, requested; |
29fc1aa4 | 1994 | u32 trb_type; |
8af56be1 | 1995 | |
29fc1aa4 | 1996 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3])); |
28ccd296 | 1997 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
8af56be1 | 1998 | xdev = xhci->devs[slot_id]; |
28ccd296 ME |
1999 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
2000 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); | |
8af56be1 | 2001 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
28ccd296 | 2002 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
0b6c324c MN |
2003 | requested = td->urb->transfer_buffer_length; |
2004 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2005 | ||
8af56be1 AX |
2006 | switch (trb_comp_code) { |
2007 | case COMP_SUCCESS: | |
29fc1aa4 | 2008 | if (trb_type != TRB_STATUS) { |
0b6c324c | 2009 | xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n", |
29fc1aa4 | 2010 | (trb_type == TRB_DATA) ? "data" : "setup"); |
8af56be1 | 2011 | *status = -ESHUTDOWN; |
0b6c324c | 2012 | break; |
8af56be1 | 2013 | } |
0b6c324c | 2014 | *status = 0; |
8af56be1 | 2015 | break; |
0b7c105a | 2016 | case COMP_SHORT_PACKET: |
0b6c324c | 2017 | *status = 0; |
8af56be1 | 2018 | break; |
0b7c105a | 2019 | case COMP_STOPPED_SHORT_PACKET: |
29fc1aa4 | 2020 | if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) |
0b6c324c | 2021 | td->urb->actual_length = remaining; |
40a3b775 | 2022 | else |
0b6c324c MN |
2023 | xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); |
2024 | goto finish_td; | |
0b7c105a | 2025 | case COMP_STOPPED: |
29fc1aa4 FB |
2026 | switch (trb_type) { |
2027 | case TRB_SETUP: | |
2028 | td->urb->actual_length = 0; | |
2029 | goto finish_td; | |
2030 | case TRB_DATA: | |
2031 | case TRB_NORMAL: | |
0b6c324c | 2032 | td->urb->actual_length = requested - remaining; |
29fc1aa4 | 2033 | goto finish_td; |
0ab2881a MN |
2034 | case TRB_STATUS: |
2035 | td->urb->actual_length = requested; | |
2036 | goto finish_td; | |
29fc1aa4 FB |
2037 | default: |
2038 | xhci_warn(xhci, "WARN: unexpected TRB Type %d\n", | |
2039 | trb_type); | |
2040 | goto finish_td; | |
2041 | } | |
0b7c105a | 2042 | case COMP_STOPPED_LENGTH_INVALID: |
0b6c324c | 2043 | goto finish_td; |
8af56be1 AX |
2044 | default: |
2045 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
0b6c324c | 2046 | ep_ctx, trb_comp_code)) |
8af56be1 | 2047 | break; |
0b6c324c MN |
2048 | xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n", |
2049 | trb_comp_code, ep_index); | |
8af56be1 | 2050 | /* else fall through */ |
0b7c105a | 2051 | case COMP_STALL_ERROR: |
8af56be1 | 2052 | /* Did we transfer part of the data (middle) phase? */ |
29fc1aa4 | 2053 | if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) |
0b6c324c | 2054 | td->urb->actual_length = requested - remaining; |
22ae47e6 | 2055 | else if (!td->urb_length_set) |
8af56be1 | 2056 | td->urb->actual_length = 0; |
0b6c324c | 2057 | goto finish_td; |
8af56be1 | 2058 | } |
0b6c324c MN |
2059 | |
2060 | /* stopped at setup stage, no data transferred */ | |
29fc1aa4 | 2061 | if (trb_type == TRB_SETUP) |
0b6c324c MN |
2062 | goto finish_td; |
2063 | ||
8af56be1 | 2064 | /* |
0b6c324c MN |
2065 | * if on data stage then update the actual_length of the URB and flag it |
2066 | * as set, so it won't be overwritten in the event for the last TRB. | |
8af56be1 | 2067 | */ |
29fc1aa4 FB |
2068 | if (trb_type == TRB_DATA || |
2069 | trb_type == TRB_NORMAL) { | |
0b6c324c MN |
2070 | td->urb_length_set = true; |
2071 | td->urb->actual_length = requested - remaining; | |
2072 | xhci_dbg(xhci, "Waiting for status stage event\n"); | |
2073 | return 0; | |
8af56be1 AX |
2074 | } |
2075 | ||
0b6c324c MN |
2076 | /* at status stage */ |
2077 | if (!td->urb_length_set) | |
2078 | td->urb->actual_length = requested; | |
2079 | ||
2080 | finish_td: | |
f97c08ae | 2081 | return finish_td(xhci, td, ep_trb, event, ep, status, false); |
8af56be1 AX |
2082 | } |
2083 | ||
04e51901 AX |
2084 | /* |
2085 | * Process isochronous tds, update urb packet status and actual_length. | |
2086 | */ | |
2087 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 2088 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
04e51901 AX |
2089 | struct xhci_virt_ep *ep, int *status) |
2090 | { | |
2091 | struct xhci_ring *ep_ring; | |
2092 | struct urb_priv *urb_priv; | |
2093 | int idx; | |
926008c9 | 2094 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 2095 | u32 trb_comp_code; |
36da3a1d MN |
2096 | bool sum_trbs_for_length = false; |
2097 | u32 remaining, requested, ep_trb_len; | |
2098 | int short_framestatus; | |
04e51901 | 2099 | |
28ccd296 ME |
2100 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2101 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
04e51901 | 2102 | urb_priv = td->urb->hcpriv; |
9ef7fbbb | 2103 | idx = urb_priv->num_tds_done; |
926008c9 | 2104 | frame = &td->urb->iso_frame_desc[idx]; |
36da3a1d MN |
2105 | requested = frame->length; |
2106 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2107 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); | |
2108 | short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
2109 | -EREMOTEIO : 0; | |
04e51901 | 2110 | |
926008c9 DT |
2111 | /* handle completion code */ |
2112 | switch (trb_comp_code) { | |
2113 | case COMP_SUCCESS: | |
36da3a1d MN |
2114 | if (remaining) { |
2115 | frame->status = short_framestatus; | |
2116 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2117 | sum_trbs_for_length = true; | |
1530bbc6 SS |
2118 | break; |
2119 | } | |
36da3a1d MN |
2120 | frame->status = 0; |
2121 | break; | |
0b7c105a | 2122 | case COMP_SHORT_PACKET: |
36da3a1d MN |
2123 | frame->status = short_framestatus; |
2124 | sum_trbs_for_length = true; | |
926008c9 | 2125 | break; |
0b7c105a | 2126 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
926008c9 | 2127 | frame->status = -ECOMM; |
926008c9 | 2128 | break; |
0b7c105a FB |
2129 | case COMP_ISOCH_BUFFER_OVERRUN: |
2130 | case COMP_BABBLE_DETECTED_ERROR: | |
926008c9 | 2131 | frame->status = -EOVERFLOW; |
926008c9 | 2132 | break; |
0b7c105a FB |
2133 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
2134 | case COMP_STALL_ERROR: | |
d104d015 | 2135 | frame->status = -EPROTO; |
d104d015 | 2136 | break; |
0b7c105a | 2137 | case COMP_USB_TRANSACTION_ERROR: |
926008c9 | 2138 | frame->status = -EPROTO; |
f97c08ae | 2139 | if (ep_trb != td->last_trb) |
d104d015 | 2140 | return 0; |
926008c9 | 2141 | break; |
0b7c105a | 2142 | case COMP_STOPPED: |
36da3a1d MN |
2143 | sum_trbs_for_length = true; |
2144 | break; | |
0b7c105a | 2145 | case COMP_STOPPED_SHORT_PACKET: |
36da3a1d MN |
2146 | /* field normally containing residue now contains tranferred */ |
2147 | frame->status = short_framestatus; | |
2148 | requested = remaining; | |
2149 | break; | |
0b7c105a | 2150 | case COMP_STOPPED_LENGTH_INVALID: |
36da3a1d MN |
2151 | requested = 0; |
2152 | remaining = 0; | |
926008c9 DT |
2153 | break; |
2154 | default: | |
36da3a1d | 2155 | sum_trbs_for_length = true; |
926008c9 DT |
2156 | frame->status = -1; |
2157 | break; | |
04e51901 AX |
2158 | } |
2159 | ||
36da3a1d MN |
2160 | if (sum_trbs_for_length) |
2161 | frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) + | |
2162 | ep_trb_len - remaining; | |
2163 | else | |
2164 | frame->actual_length = requested; | |
04e51901 | 2165 | |
36da3a1d | 2166 | td->urb->actual_length += frame->actual_length; |
04e51901 | 2167 | |
f97c08ae | 2168 | return finish_td(xhci, td, ep_trb, event, ep, status, false); |
04e51901 AX |
2169 | } |
2170 | ||
926008c9 DT |
2171 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
2172 | struct xhci_transfer_event *event, | |
2173 | struct xhci_virt_ep *ep, int *status) | |
2174 | { | |
2175 | struct xhci_ring *ep_ring; | |
2176 | struct urb_priv *urb_priv; | |
2177 | struct usb_iso_packet_descriptor *frame; | |
2178 | int idx; | |
2179 | ||
f6975314 | 2180 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
926008c9 | 2181 | urb_priv = td->urb->hcpriv; |
9ef7fbbb | 2182 | idx = urb_priv->num_tds_done; |
926008c9 DT |
2183 | frame = &td->urb->iso_frame_desc[idx]; |
2184 | ||
b3df3f9c | 2185 | /* The transfer is partly done. */ |
926008c9 DT |
2186 | frame->status = -EXDEV; |
2187 | ||
2188 | /* calc actual length */ | |
2189 | frame->actual_length = 0; | |
2190 | ||
2191 | /* Update ring dequeue pointer */ | |
2192 | while (ep_ring->dequeue != td->last_trb) | |
3b72fca0 AX |
2193 | inc_deq(xhci, ep_ring); |
2194 | inc_deq(xhci, ep_ring); | |
926008c9 DT |
2195 | |
2196 | return finish_td(xhci, td, NULL, event, ep, status, true); | |
2197 | } | |
2198 | ||
22405ed2 AX |
2199 | /* |
2200 | * Process bulk and interrupt tds, update urb status and actual_length. | |
2201 | */ | |
2202 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td, | |
f97c08ae | 2203 | union xhci_trb *ep_trb, struct xhci_transfer_event *event, |
22405ed2 AX |
2204 | struct xhci_virt_ep *ep, int *status) |
2205 | { | |
2206 | struct xhci_ring *ep_ring; | |
22405ed2 | 2207 | u32 trb_comp_code; |
f97c08ae | 2208 | u32 remaining, requested, ep_trb_len; |
22405ed2 | 2209 | |
28ccd296 ME |
2210 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
2211 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
30a65b45 | 2212 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
f97c08ae | 2213 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); |
30a65b45 | 2214 | requested = td->urb->transfer_buffer_length; |
22405ed2 AX |
2215 | |
2216 | switch (trb_comp_code) { | |
2217 | case COMP_SUCCESS: | |
30a65b45 | 2218 | /* handle success with untransferred data as short packet */ |
f97c08ae | 2219 | if (ep_trb != td->last_trb || remaining) { |
52ab8685 | 2220 | xhci_warn(xhci, "WARN Successful completion on short TX\n"); |
30a65b45 MN |
2221 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2222 | td->urb->ep->desc.bEndpointAddress, | |
2223 | requested, remaining); | |
22405ed2 | 2224 | } |
52ab8685 | 2225 | *status = 0; |
22405ed2 | 2226 | break; |
0b7c105a | 2227 | case COMP_SHORT_PACKET: |
30a65b45 MN |
2228 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2229 | td->urb->ep->desc.bEndpointAddress, | |
2230 | requested, remaining); | |
52ab8685 | 2231 | *status = 0; |
22405ed2 | 2232 | break; |
0b7c105a | 2233 | case COMP_STOPPED_SHORT_PACKET: |
30a65b45 MN |
2234 | td->urb->actual_length = remaining; |
2235 | goto finish_td; | |
0b7c105a | 2236 | case COMP_STOPPED_LENGTH_INVALID: |
30a65b45 | 2237 | /* stopped on ep trb with invalid length, exclude it */ |
f97c08ae | 2238 | ep_trb_len = 0; |
30a65b45 MN |
2239 | remaining = 0; |
2240 | break; | |
22405ed2 | 2241 | default: |
30a65b45 | 2242 | /* do nothing */ |
22405ed2 AX |
2243 | break; |
2244 | } | |
40a3b775 | 2245 | |
f97c08ae | 2246 | if (ep_trb == td->last_trb) |
30a65b45 MN |
2247 | td->urb->actual_length = requested - remaining; |
2248 | else | |
2249 | td->urb->actual_length = | |
f97c08ae MN |
2250 | sum_trb_lengths(xhci, ep_ring, ep_trb) + |
2251 | ep_trb_len - remaining; | |
30a65b45 MN |
2252 | finish_td: |
2253 | if (remaining > requested) { | |
2254 | xhci_warn(xhci, "bad transfer trb length %d in event trb\n", | |
2255 | remaining); | |
22405ed2 | 2256 | td->urb->actual_length = 0; |
22405ed2 | 2257 | } |
f97c08ae | 2258 | return finish_td(xhci, td, ep_trb, event, ep, status, false); |
22405ed2 AX |
2259 | } |
2260 | ||
d0e96f5a SS |
2261 | /* |
2262 | * If this function returns an error condition, it means it got a Transfer | |
2263 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2264 | * At this point, the host controller is probably hosed and should be reset. | |
2265 | */ | |
2266 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2267 | struct xhci_transfer_event *event) | |
2268 | { | |
2269 | struct xhci_virt_device *xdev; | |
63a0d9ab | 2270 | struct xhci_virt_ep *ep; |
d0e96f5a | 2271 | struct xhci_ring *ep_ring; |
82d1009f | 2272 | unsigned int slot_id; |
d0e96f5a | 2273 | int ep_index; |
326b4810 | 2274 | struct xhci_td *td = NULL; |
f97c08ae MN |
2275 | dma_addr_t ep_trb_dma; |
2276 | struct xhci_segment *ep_seg; | |
2277 | union xhci_trb *ep_trb; | |
d0e96f5a | 2278 | int status = -EINPROGRESS; |
d115b048 | 2279 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2280 | struct list_head *tmp; |
66d1eebc | 2281 | u32 trb_comp_code; |
c2d7b49f | 2282 | int td_num = 0; |
3b4739b8 | 2283 | bool handling_skipped_tds = false; |
d0e96f5a | 2284 | |
28ccd296 | 2285 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
82d1009f | 2286 | xdev = xhci->devs[slot_id]; |
d0e96f5a | 2287 | if (!xdev) { |
b7f769ae ZX |
2288 | xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n", |
2289 | slot_id); | |
9258c0b2 | 2290 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2291 | (unsigned long long) xhci_trb_virt_to_dma( |
2292 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2293 | xhci->event_ring->dequeue), |
2294 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2295 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2296 | le32_to_cpu(event->transfer_len), | |
2297 | le32_to_cpu(event->flags)); | |
2298 | xhci_dbg(xhci, "Event ring:\n"); | |
2299 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2300 | return -ENODEV; |
2301 | } | |
2302 | ||
2303 | /* Endpoint ID is 1 based, our index is zero based */ | |
28ccd296 | 2304 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
63a0d9ab | 2305 | ep = &xdev->eps[ep_index]; |
28ccd296 | 2306 | ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer)); |
d115b048 | 2307 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
5071e6b2 | 2308 | if (!ep_ring || GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) { |
b7f769ae ZX |
2309 | xhci_err(xhci, |
2310 | "ERROR Transfer event for disabled endpoint slot %u ep %u or incorrect stream ring\n", | |
2311 | slot_id, ep_index); | |
9258c0b2 | 2312 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", |
e910b440 SS |
2313 | (unsigned long long) xhci_trb_virt_to_dma( |
2314 | xhci->event_ring->deq_seg, | |
9258c0b2 SS |
2315 | xhci->event_ring->dequeue), |
2316 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2317 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2318 | le32_to_cpu(event->transfer_len), | |
2319 | le32_to_cpu(event->flags)); | |
2320 | xhci_dbg(xhci, "Event ring:\n"); | |
2321 | xhci_debug_segment(xhci, xhci->event_ring->deq_seg); | |
d0e96f5a SS |
2322 | return -ENODEV; |
2323 | } | |
2324 | ||
c2d7b49f AX |
2325 | /* Count current td numbers if ep->skip is set */ |
2326 | if (ep->skip) { | |
2327 | list_for_each(tmp, &ep_ring->td_list) | |
2328 | td_num++; | |
2329 | } | |
2330 | ||
f97c08ae | 2331 | ep_trb_dma = le64_to_cpu(event->buffer); |
28ccd296 | 2332 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
986a92d4 | 2333 | /* Look for common error cases */ |
66d1eebc | 2334 | switch (trb_comp_code) { |
b10de142 SS |
2335 | /* Skip codes that require special handling depending on |
2336 | * transfer type | |
2337 | */ | |
2338 | case COMP_SUCCESS: | |
1c11a172 | 2339 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
1530bbc6 SS |
2340 | break; |
2341 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
0b7c105a | 2342 | trb_comp_code = COMP_SHORT_PACKET; |
1530bbc6 | 2343 | else |
8202ce2e | 2344 | xhci_warn_ratelimited(xhci, |
b7f769ae ZX |
2345 | "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n", |
2346 | slot_id, ep_index); | |
0b7c105a | 2347 | case COMP_SHORT_PACKET: |
b10de142 | 2348 | break; |
0b7c105a | 2349 | case COMP_STOPPED: |
b7f769ae ZX |
2350 | xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n", |
2351 | slot_id, ep_index); | |
ae636747 | 2352 | break; |
0b7c105a | 2353 | case COMP_STOPPED_LENGTH_INVALID: |
b7f769ae ZX |
2354 | xhci_dbg(xhci, |
2355 | "Stopped on No-op or Link TRB for slot %u ep %u\n", | |
2356 | slot_id, ep_index); | |
ae636747 | 2357 | break; |
0b7c105a | 2358 | case COMP_STOPPED_SHORT_PACKET: |
b7f769ae ZX |
2359 | xhci_dbg(xhci, |
2360 | "Stopped with short packet transfer detected for slot %u ep %u\n", | |
2361 | slot_id, ep_index); | |
40a3b775 | 2362 | break; |
0b7c105a | 2363 | case COMP_STALL_ERROR: |
b7f769ae ZX |
2364 | xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id, |
2365 | ep_index); | |
63a0d9ab | 2366 | ep->ep_state |= EP_HALTED; |
b10de142 SS |
2367 | status = -EPIPE; |
2368 | break; | |
0b7c105a | 2369 | case COMP_TRB_ERROR: |
b7f769ae ZX |
2370 | xhci_warn(xhci, |
2371 | "WARN: TRB error for slot %u ep %u on endpoint\n", | |
2372 | slot_id, ep_index); | |
b10de142 SS |
2373 | status = -EILSEQ; |
2374 | break; | |
0b7c105a FB |
2375 | case COMP_SPLIT_TRANSACTION_ERROR: |
2376 | case COMP_USB_TRANSACTION_ERROR: | |
b7f769ae ZX |
2377 | xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n", |
2378 | slot_id, ep_index); | |
b10de142 SS |
2379 | status = -EPROTO; |
2380 | break; | |
0b7c105a | 2381 | case COMP_BABBLE_DETECTED_ERROR: |
b7f769ae ZX |
2382 | xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n", |
2383 | slot_id, ep_index); | |
4a73143c SS |
2384 | status = -EOVERFLOW; |
2385 | break; | |
0b7c105a | 2386 | case COMP_DATA_BUFFER_ERROR: |
b7f769ae ZX |
2387 | xhci_warn(xhci, |
2388 | "WARN: HC couldn't access mem fast enough for slot %u ep %u\n", | |
2389 | slot_id, ep_index); | |
b10de142 SS |
2390 | status = -ENOSR; |
2391 | break; | |
0b7c105a | 2392 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
b7f769ae ZX |
2393 | xhci_warn(xhci, |
2394 | "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n", | |
2395 | slot_id, ep_index); | |
986a92d4 | 2396 | break; |
0b7c105a | 2397 | case COMP_ISOCH_BUFFER_OVERRUN: |
b7f769ae ZX |
2398 | xhci_warn(xhci, |
2399 | "WARN: buffer overrun event for slot %u ep %u on endpoint", | |
2400 | slot_id, ep_index); | |
986a92d4 | 2401 | break; |
0b7c105a | 2402 | case COMP_RING_UNDERRUN: |
986a92d4 AX |
2403 | /* |
2404 | * When the Isoch ring is empty, the xHC will generate | |
2405 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2406 | * Underrun Event for OUT Isoch endpoint. | |
2407 | */ | |
2408 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2409 | if (!list_empty(&ep_ring->td_list)) | |
2410 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2411 | "still with TDs queued?\n", | |
28ccd296 ME |
2412 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2413 | ep_index); | |
986a92d4 | 2414 | goto cleanup; |
0b7c105a | 2415 | case COMP_RING_OVERRUN: |
986a92d4 AX |
2416 | xhci_dbg(xhci, "overrun event on endpoint\n"); |
2417 | if (!list_empty(&ep_ring->td_list)) | |
2418 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2419 | "still with TDs queued?\n", | |
28ccd296 ME |
2420 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2421 | ep_index); | |
986a92d4 | 2422 | goto cleanup; |
0b7c105a | 2423 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
b7f769ae ZX |
2424 | xhci_warn(xhci, |
2425 | "WARN: detect an incompatible device for slot %u ep %u", | |
2426 | slot_id, ep_index); | |
f6ba6fe2 AH |
2427 | status = -EPROTO; |
2428 | break; | |
0b7c105a | 2429 | case COMP_MISSED_SERVICE_ERROR: |
d18240db AX |
2430 | /* |
2431 | * When encounter missed service error, one or more isoc tds | |
2432 | * may be missed by xHC. | |
2433 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2434 | * short transfer when process the ep_ring next time. | |
2435 | */ | |
2436 | ep->skip = true; | |
b7f769ae ZX |
2437 | xhci_dbg(xhci, |
2438 | "Miss service interval error for slot %u ep %u, set skip flag\n", | |
2439 | slot_id, ep_index); | |
d18240db | 2440 | goto cleanup; |
0b7c105a | 2441 | case COMP_NO_PING_RESPONSE_ERROR: |
3b4739b8 | 2442 | ep->skip = true; |
b7f769ae ZX |
2443 | xhci_dbg(xhci, |
2444 | "No Ping response error for slot %u ep %u, Skip one Isoc TD\n", | |
2445 | slot_id, ep_index); | |
3b4739b8 | 2446 | goto cleanup; |
b10de142 | 2447 | default: |
b45b5069 | 2448 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2449 | status = 0; |
2450 | break; | |
2451 | } | |
b7f769ae ZX |
2452 | xhci_warn(xhci, |
2453 | "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n", | |
2454 | trb_comp_code, slot_id, ep_index); | |
986a92d4 AX |
2455 | goto cleanup; |
2456 | } | |
2457 | ||
d18240db AX |
2458 | do { |
2459 | /* This TRB should be in the TD at the head of this ring's | |
2460 | * TD list. | |
2461 | */ | |
2462 | if (list_empty(&ep_ring->td_list)) { | |
a83d6755 SS |
2463 | /* |
2464 | * A stopped endpoint may generate an extra completion | |
2465 | * event if the device was suspended. Don't print | |
2466 | * warnings. | |
2467 | */ | |
0b7c105a FB |
2468 | if (!(trb_comp_code == COMP_STOPPED || |
2469 | trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { | |
a83d6755 SS |
2470 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", |
2471 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), | |
2472 | ep_index); | |
2473 | xhci_dbg(xhci, "Event TRB with TRB type ID %u\n", | |
2474 | (le32_to_cpu(event->flags) & | |
2475 | TRB_TYPE_BITMASK)>>10); | |
2476 | xhci_print_trb_offsets(xhci, (union xhci_trb *) event); | |
2477 | } | |
d18240db AX |
2478 | if (ep->skip) { |
2479 | ep->skip = false; | |
b7f769ae ZX |
2480 | xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n", |
2481 | slot_id, ep_index); | |
d18240db | 2482 | } |
d18240db AX |
2483 | goto cleanup; |
2484 | } | |
986a92d4 | 2485 | |
c2d7b49f AX |
2486 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2487 | if (ep->skip && td_num == 0) { | |
2488 | ep->skip = false; | |
b7f769ae ZX |
2489 | xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n", |
2490 | slot_id, ep_index); | |
c2d7b49f AX |
2491 | goto cleanup; |
2492 | } | |
2493 | ||
04861f83 FB |
2494 | td = list_first_entry(&ep_ring->td_list, struct xhci_td, |
2495 | td_list); | |
c2d7b49f AX |
2496 | if (ep->skip) |
2497 | td_num--; | |
926008c9 | 2498 | |
d18240db | 2499 | /* Is this a TRB in the currently executing TD? */ |
f97c08ae MN |
2500 | ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, |
2501 | td->last_trb, ep_trb_dma, false); | |
e1cf486d AH |
2502 | |
2503 | /* | |
2504 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2505 | * is not in the current TD pointed by ep_ring->dequeue because | |
2506 | * that the hardware dequeue pointer still at the previous TRB | |
2507 | * of the current TD. The previous TRB maybe a Link TD or the | |
2508 | * last TRB of the previous TD. The command completion handle | |
2509 | * will take care the rest. | |
2510 | */ | |
0b7c105a FB |
2511 | if (!ep_seg && (trb_comp_code == COMP_STOPPED || |
2512 | trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { | |
e1cf486d AH |
2513 | goto cleanup; |
2514 | } | |
2515 | ||
f97c08ae | 2516 | if (!ep_seg) { |
926008c9 DT |
2517 | if (!ep->skip || |
2518 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2519 | /* Some host controllers give a spurious |
2520 | * successful event after a short transfer. | |
2521 | * Ignore it. | |
2522 | */ | |
ddba5cd0 | 2523 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
ad808333 SS |
2524 | ep_ring->last_td_was_short) { |
2525 | ep_ring->last_td_was_short = false; | |
ad808333 SS |
2526 | goto cleanup; |
2527 | } | |
926008c9 DT |
2528 | /* HC is busted, give up! */ |
2529 | xhci_err(xhci, | |
2530 | "ERROR Transfer event TRB DMA ptr not " | |
cffb9be8 HG |
2531 | "part of current TD ep_index %d " |
2532 | "comp_code %u\n", ep_index, | |
2533 | trb_comp_code); | |
2534 | trb_in_td(xhci, ep_ring->deq_seg, | |
2535 | ep_ring->dequeue, td->last_trb, | |
f97c08ae | 2536 | ep_trb_dma, true); |
926008c9 DT |
2537 | return -ESHUTDOWN; |
2538 | } | |
2539 | ||
0c03d89d | 2540 | skip_isoc_td(xhci, td, event, ep, &status); |
926008c9 DT |
2541 | goto cleanup; |
2542 | } | |
0b7c105a | 2543 | if (trb_comp_code == COMP_SHORT_PACKET) |
ad808333 SS |
2544 | ep_ring->last_td_was_short = true; |
2545 | else | |
2546 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2547 | |
2548 | if (ep->skip) { | |
b7f769ae ZX |
2549 | xhci_dbg(xhci, |
2550 | "Found td. Clear skip flag for slot %u ep %u.\n", | |
2551 | slot_id, ep_index); | |
d18240db AX |
2552 | ep->skip = false; |
2553 | } | |
678539cf | 2554 | |
f97c08ae MN |
2555 | ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / |
2556 | sizeof(*ep_trb)]; | |
a37c3f76 FB |
2557 | |
2558 | trace_xhci_handle_transfer(ep_ring, | |
2559 | (struct xhci_generic_trb *) ep_trb); | |
2560 | ||
926008c9 DT |
2561 | /* |
2562 | * No-op TRB should not trigger interrupts. | |
f97c08ae | 2563 | * If ep_trb is a no-op TRB, it means the |
926008c9 DT |
2564 | * corresponding TD has been cancelled. Just ignore |
2565 | * the TD. | |
2566 | */ | |
f97c08ae | 2567 | if (trb_is_noop(ep_trb)) { |
b7f769ae ZX |
2568 | xhci_dbg(xhci, |
2569 | "ep_trb is a no-op TRB. Skip it for slot %u ep %u\n", | |
2570 | slot_id, ep_index); | |
926008c9 | 2571 | goto cleanup; |
d18240db | 2572 | } |
4422da61 | 2573 | |
0c03d89d | 2574 | /* update the urb's actual_length and give back to the core */ |
d18240db | 2575 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
0c03d89d | 2576 | process_ctrl_td(xhci, td, ep_trb, event, ep, &status); |
04e51901 | 2577 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
0c03d89d | 2578 | process_isoc_td(xhci, td, ep_trb, event, ep, &status); |
d18240db | 2579 | else |
0c03d89d MN |
2580 | process_bulk_intr_td(xhci, td, ep_trb, event, ep, |
2581 | &status); | |
d18240db | 2582 | cleanup: |
3b4739b8 | 2583 | handling_skipped_tds = ep->skip && |
0b7c105a FB |
2584 | trb_comp_code != COMP_MISSED_SERVICE_ERROR && |
2585 | trb_comp_code != COMP_NO_PING_RESPONSE_ERROR; | |
3b4739b8 | 2586 | |
d18240db | 2587 | /* |
3b4739b8 MN |
2588 | * Do not update event ring dequeue pointer if we're in a loop |
2589 | * processing missed tds. | |
d18240db | 2590 | */ |
3b4739b8 | 2591 | if (!handling_skipped_tds) |
3b72fca0 | 2592 | inc_deq(xhci, xhci->event_ring); |
d18240db | 2593 | |
d18240db AX |
2594 | /* |
2595 | * If ep->skip is set, it means there are missed tds on the | |
2596 | * endpoint ring need to take care of. | |
2597 | * Process them as short transfer until reach the td pointed by | |
2598 | * the event. | |
2599 | */ | |
3b4739b8 | 2600 | } while (handling_skipped_tds); |
d18240db | 2601 | |
d0e96f5a SS |
2602 | return 0; |
2603 | } | |
2604 | ||
0f2a7930 SS |
2605 | /* |
2606 | * This function handles all OS-owned events on the event ring. It may drop | |
2607 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2608 | * Returns >0 for "possibly more events to process" (caller should call again), |
2609 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2610 | */ |
9dee9a21 | 2611 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2612 | { |
2613 | union xhci_trb *event; | |
0f2a7930 | 2614 | int update_ptrs = 1; |
d0e96f5a | 2615 | int ret; |
7f84eef0 | 2616 | |
f4c8f03c | 2617 | /* Event ring hasn't been allocated yet. */ |
7f84eef0 | 2618 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
f4c8f03c LB |
2619 | xhci_err(xhci, "ERROR event ring not ready\n"); |
2620 | return -ENOMEM; | |
7f84eef0 SS |
2621 | } |
2622 | ||
2623 | event = xhci->event_ring->dequeue; | |
2624 | /* Does the HC or OS own the TRB? */ | |
28ccd296 | 2625 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
f4c8f03c | 2626 | xhci->event_ring->cycle_state) |
9dee9a21 | 2627 | return 0; |
7f84eef0 | 2628 | |
a37c3f76 FB |
2629 | trace_xhci_handle_event(xhci->event_ring, &event->generic); |
2630 | ||
92a3da41 ME |
2631 | /* |
2632 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2633 | * speculative reads of the event's flags/data below. | |
2634 | */ | |
2635 | rmb(); | |
0f2a7930 | 2636 | /* FIXME: Handle more event types. */ |
f4c8f03c | 2637 | switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) { |
7f84eef0 SS |
2638 | case TRB_TYPE(TRB_COMPLETION): |
2639 | handle_cmd_completion(xhci, &event->event_cmd); | |
2640 | break; | |
0f2a7930 SS |
2641 | case TRB_TYPE(TRB_PORT_STATUS): |
2642 | handle_port_status(xhci, event); | |
2643 | update_ptrs = 0; | |
2644 | break; | |
d0e96f5a SS |
2645 | case TRB_TYPE(TRB_TRANSFER): |
2646 | ret = handle_tx_event(xhci, &event->trans_event); | |
f4c8f03c | 2647 | if (ret >= 0) |
d0e96f5a SS |
2648 | update_ptrs = 0; |
2649 | break; | |
623bef9e SS |
2650 | case TRB_TYPE(TRB_DEV_NOTE): |
2651 | handle_device_notification(xhci, event); | |
2652 | break; | |
7f84eef0 | 2653 | default: |
28ccd296 ME |
2654 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >= |
2655 | TRB_TYPE(48)) | |
0238634d SS |
2656 | handle_vendor_event(xhci, event); |
2657 | else | |
f4c8f03c LB |
2658 | xhci_warn(xhci, "ERROR unknown event type %d\n", |
2659 | TRB_FIELD_TO_TYPE( | |
2660 | le32_to_cpu(event->event_cmd.flags))); | |
7f84eef0 | 2661 | } |
6f5165cf SS |
2662 | /* Any of the above functions may drop and re-acquire the lock, so check |
2663 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
2664 | */ | |
2665 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2666 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
2667 | "event handler.\n"); | |
9dee9a21 | 2668 | return 0; |
6f5165cf | 2669 | } |
7f84eef0 | 2670 | |
c06d68b8 SS |
2671 | if (update_ptrs) |
2672 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 2673 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 2674 | |
9dee9a21 ME |
2675 | /* Are there more items on the event ring? Caller will call us again to |
2676 | * check. | |
2677 | */ | |
2678 | return 1; | |
7f84eef0 | 2679 | } |
9032cd52 SS |
2680 | |
2681 | /* | |
2682 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
2683 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
2684 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
2685 | */ | |
2686 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
2687 | { | |
2688 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c06d68b8 | 2689 | union xhci_trb *event_ring_deq; |
76a35293 | 2690 | irqreturn_t ret = IRQ_NONE; |
c06d68b8 | 2691 | dma_addr_t deq; |
76a35293 FB |
2692 | u64 temp_64; |
2693 | u32 status; | |
9032cd52 SS |
2694 | |
2695 | spin_lock(&xhci->lock); | |
9032cd52 | 2696 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
b0ba9720 | 2697 | status = readl(&xhci->op_regs->status); |
76a35293 FB |
2698 | if (status == 0xffffffff) { |
2699 | ret = IRQ_HANDLED; | |
2700 | goto out; | |
9032cd52 | 2701 | } |
76a35293 FB |
2702 | |
2703 | if (!(status & STS_EINT)) | |
2704 | goto out; | |
2705 | ||
27e0dd4d | 2706 | if (status & STS_FATAL) { |
9032cd52 SS |
2707 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
2708 | xhci_halt(xhci); | |
76a35293 FB |
2709 | ret = IRQ_HANDLED; |
2710 | goto out; | |
9032cd52 SS |
2711 | } |
2712 | ||
bda53145 SS |
2713 | /* |
2714 | * Clear the op reg interrupt status first, | |
2715 | * so we can receive interrupts from other MSI-X interrupters. | |
2716 | * Write 1 to clear the interrupt status. | |
2717 | */ | |
27e0dd4d | 2718 | status |= STS_EINT; |
204b7793 | 2719 | writel(status, &xhci->op_regs->status); |
bda53145 SS |
2720 | /* FIXME when MSI-X is supported and there are multiple vectors */ |
2721 | /* Clear the MSI-X event interrupt status */ | |
2722 | ||
cd70469d | 2723 | if (hcd->irq) { |
c21599a3 SS |
2724 | u32 irq_pending; |
2725 | /* Acknowledge the PCI interrupt */ | |
b0ba9720 | 2726 | irq_pending = readl(&xhci->ir_set->irq_pending); |
4e833c0b | 2727 | irq_pending |= IMAN_IP; |
204b7793 | 2728 | writel(irq_pending, &xhci->ir_set->irq_pending); |
c21599a3 | 2729 | } |
bda53145 | 2730 | |
27a41a83 GKB |
2731 | if (xhci->xhc_state & XHCI_STATE_DYING || |
2732 | xhci->xhc_state & XHCI_STATE_HALTED) { | |
bda53145 SS |
2733 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
2734 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
2735 | /* Clear the event handler busy flag (RW1C); |
2736 | * the event ring should be empty. | |
bda53145 | 2737 | */ |
f7b2e403 | 2738 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
477632df SS |
2739 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
2740 | &xhci->ir_set->erst_dequeue); | |
76a35293 FB |
2741 | ret = IRQ_HANDLED; |
2742 | goto out; | |
c06d68b8 SS |
2743 | } |
2744 | ||
2745 | event_ring_deq = xhci->event_ring->dequeue; | |
2746 | /* FIXME this should be a delayed service routine | |
2747 | * that clears the EHB. | |
2748 | */ | |
9dee9a21 | 2749 | while (xhci_handle_event(xhci) > 0) {} |
bda53145 | 2750 | |
f7b2e403 | 2751 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
c06d68b8 SS |
2752 | /* If necessary, update the HW's version of the event ring deq ptr. */ |
2753 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
2754 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
2755 | xhci->event_ring->dequeue); | |
2756 | if (deq == 0) | |
2757 | xhci_warn(xhci, "WARN something wrong with SW event " | |
2758 | "ring dequeue ptr.\n"); | |
2759 | /* Update HC event ring dequeue pointer */ | |
2760 | temp_64 &= ERST_PTR_MASK; | |
2761 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
2762 | } | |
2763 | ||
2764 | /* Clear the event handler busy flag (RW1C); event ring is empty. */ | |
2765 | temp_64 |= ERST_EHB; | |
477632df | 2766 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); |
76a35293 | 2767 | ret = IRQ_HANDLED; |
c06d68b8 | 2768 | |
76a35293 | 2769 | out: |
9032cd52 SS |
2770 | spin_unlock(&xhci->lock); |
2771 | ||
76a35293 | 2772 | return ret; |
9032cd52 SS |
2773 | } |
2774 | ||
851ec164 | 2775 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
9032cd52 | 2776 | { |
968b822c | 2777 | return xhci_irq(hcd); |
9032cd52 | 2778 | } |
7f84eef0 | 2779 | |
d0e96f5a SS |
2780 | /**** Endpoint Ring Operations ****/ |
2781 | ||
7f84eef0 SS |
2782 | /* |
2783 | * Generic function for queueing a TRB on a ring. | |
2784 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
2785 | * |
2786 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
2787 | * prepare_transfer()? | |
7f84eef0 SS |
2788 | */ |
2789 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 2790 | bool more_trbs_coming, |
7f84eef0 SS |
2791 | u32 field1, u32 field2, u32 field3, u32 field4) |
2792 | { | |
2793 | struct xhci_generic_trb *trb; | |
2794 | ||
2795 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
2796 | trb->field[0] = cpu_to_le32(field1); |
2797 | trb->field[1] = cpu_to_le32(field2); | |
2798 | trb->field[2] = cpu_to_le32(field3); | |
2799 | trb->field[3] = cpu_to_le32(field4); | |
a37c3f76 FB |
2800 | |
2801 | trace_xhci_queue_trb(ring, trb); | |
2802 | ||
3b72fca0 | 2803 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
2804 | } |
2805 | ||
d0e96f5a SS |
2806 | /* |
2807 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
2808 | * FIXME allocate segments if the ring is full. | |
2809 | */ | |
2810 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 2811 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 2812 | { |
8dfec614 AX |
2813 | unsigned int num_trbs_needed; |
2814 | ||
d0e96f5a | 2815 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
2816 | switch (ep_state) { |
2817 | case EP_STATE_DISABLED: | |
2818 | /* | |
2819 | * USB core changed config/interfaces without notifying us, | |
2820 | * or hardware is reporting the wrong state. | |
2821 | */ | |
2822 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
2823 | return -ENOENT; | |
d0e96f5a | 2824 | case EP_STATE_ERROR: |
c92bcfa7 | 2825 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
2826 | /* FIXME event handling code for error needs to clear it */ |
2827 | /* XXX not sure if this should be -ENOENT or not */ | |
2828 | return -EINVAL; | |
c92bcfa7 SS |
2829 | case EP_STATE_HALTED: |
2830 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
d0e96f5a SS |
2831 | case EP_STATE_STOPPED: |
2832 | case EP_STATE_RUNNING: | |
2833 | break; | |
2834 | default: | |
2835 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
2836 | /* | |
2837 | * FIXME issue Configure Endpoint command to try to get the HC | |
2838 | * back into a known state. | |
2839 | */ | |
2840 | return -EINVAL; | |
2841 | } | |
8dfec614 AX |
2842 | |
2843 | while (1) { | |
3d4b81ed SS |
2844 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
2845 | break; | |
8dfec614 AX |
2846 | |
2847 | if (ep_ring == xhci->cmd_ring) { | |
2848 | xhci_err(xhci, "Do not support expand command ring\n"); | |
2849 | return -ENOMEM; | |
2850 | } | |
2851 | ||
68ffb011 XR |
2852 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
2853 | "ERROR no room on ep ring, try ring expansion"); | |
8dfec614 AX |
2854 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
2855 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
2856 | mem_flags)) { | |
2857 | xhci_err(xhci, "Ring expansion failed\n"); | |
2858 | return -ENOMEM; | |
2859 | } | |
261fa12b | 2860 | } |
6c12db90 | 2861 | |
d0c77d84 MN |
2862 | while (trb_is_link(ep_ring->enqueue)) { |
2863 | /* If we're not dealing with 0.95 hardware or isoc rings | |
2864 | * on AMD 0.96 host, clear the chain bit. | |
2865 | */ | |
2866 | if (!xhci_link_trb_quirk(xhci) && | |
2867 | !(ep_ring->type == TYPE_ISOC && | |
2868 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
2869 | ep_ring->enqueue->link.control &= | |
2870 | cpu_to_le32(~TRB_CHAIN); | |
2871 | else | |
2872 | ep_ring->enqueue->link.control |= | |
2873 | cpu_to_le32(TRB_CHAIN); | |
6c12db90 | 2874 | |
d0c77d84 MN |
2875 | wmb(); |
2876 | ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); | |
6c12db90 | 2877 | |
d0c77d84 MN |
2878 | /* Toggle the cycle bit after the last ring segment. */ |
2879 | if (link_trb_toggles_cycle(ep_ring->enqueue)) | |
2880 | ep_ring->cycle_state ^= 1; | |
6c12db90 | 2881 | |
d0c77d84 MN |
2882 | ep_ring->enq_seg = ep_ring->enq_seg->next; |
2883 | ep_ring->enqueue = ep_ring->enq_seg->trbs; | |
6c12db90 | 2884 | } |
d0e96f5a SS |
2885 | return 0; |
2886 | } | |
2887 | ||
23e3be11 | 2888 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
2889 | struct xhci_virt_device *xdev, |
2890 | unsigned int ep_index, | |
e9df17eb | 2891 | unsigned int stream_id, |
d0e96f5a SS |
2892 | unsigned int num_trbs, |
2893 | struct urb *urb, | |
8e51adcc | 2894 | unsigned int td_index, |
d0e96f5a SS |
2895 | gfp_t mem_flags) |
2896 | { | |
2897 | int ret; | |
8e51adcc AX |
2898 | struct urb_priv *urb_priv; |
2899 | struct xhci_td *td; | |
e9df17eb | 2900 | struct xhci_ring *ep_ring; |
d115b048 | 2901 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb SS |
2902 | |
2903 | ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id); | |
2904 | if (!ep_ring) { | |
2905 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
2906 | stream_id); | |
2907 | return -EINVAL; | |
2908 | } | |
2909 | ||
5071e6b2 | 2910 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 2911 | num_trbs, mem_flags); |
d0e96f5a SS |
2912 | if (ret) |
2913 | return ret; | |
d0e96f5a | 2914 | |
8e51adcc | 2915 | urb_priv = urb->hcpriv; |
7e64b037 | 2916 | td = &urb_priv->td[td_index]; |
8e51adcc AX |
2917 | |
2918 | INIT_LIST_HEAD(&td->td_list); | |
2919 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
2920 | ||
2921 | if (td_index == 0) { | |
214f76f7 | 2922 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 2923 | if (unlikely(ret)) |
8e51adcc | 2924 | return ret; |
d0e96f5a SS |
2925 | } |
2926 | ||
8e51adcc | 2927 | td->urb = urb; |
d0e96f5a | 2928 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
2929 | list_add_tail(&td->td_list, &ep_ring->td_list); |
2930 | td->start_seg = ep_ring->enq_seg; | |
2931 | td->first_trb = ep_ring->enqueue; | |
2932 | ||
d0e96f5a SS |
2933 | return 0; |
2934 | } | |
2935 | ||
d2510342 AI |
2936 | static unsigned int count_trbs(u64 addr, u64 len) |
2937 | { | |
2938 | unsigned int num_trbs; | |
2939 | ||
2940 | num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), | |
2941 | TRB_MAX_BUFF_SIZE); | |
2942 | if (num_trbs == 0) | |
2943 | num_trbs++; | |
2944 | ||
2945 | return num_trbs; | |
2946 | } | |
2947 | ||
2948 | static inline unsigned int count_trbs_needed(struct urb *urb) | |
2949 | { | |
2950 | return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); | |
2951 | } | |
2952 | ||
2953 | static unsigned int count_sg_trbs_needed(struct urb *urb) | |
8a96c052 | 2954 | { |
8a96c052 | 2955 | struct scatterlist *sg; |
d2510342 | 2956 | unsigned int i, len, full_len, num_trbs = 0; |
8a96c052 | 2957 | |
d2510342 | 2958 | full_len = urb->transfer_buffer_length; |
8a96c052 | 2959 | |
d2510342 AI |
2960 | for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { |
2961 | len = sg_dma_len(sg); | |
2962 | num_trbs += count_trbs(sg_dma_address(sg), len); | |
2963 | len = min_t(unsigned int, len, full_len); | |
2964 | full_len -= len; | |
2965 | if (full_len == 0) | |
8a96c052 SS |
2966 | break; |
2967 | } | |
d2510342 | 2968 | |
8a96c052 SS |
2969 | return num_trbs; |
2970 | } | |
2971 | ||
d2510342 AI |
2972 | static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) |
2973 | { | |
2974 | u64 addr, len; | |
2975 | ||
2976 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
2977 | len = urb->iso_frame_desc[i].length; | |
2978 | ||
2979 | return count_trbs(addr, len); | |
2980 | } | |
2981 | ||
2982 | static void check_trb_math(struct urb *urb, int running_total) | |
8a96c052 | 2983 | { |
d2510342 | 2984 | if (unlikely(running_total != urb->transfer_buffer_length)) |
a2490187 | 2985 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
2986 | "queued %#x (%d), asked for %#x (%d)\n", |
2987 | __func__, | |
2988 | urb->ep->desc.bEndpointAddress, | |
2989 | running_total, running_total, | |
2990 | urb->transfer_buffer_length, | |
2991 | urb->transfer_buffer_length); | |
2992 | } | |
2993 | ||
23e3be11 | 2994 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 2995 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 2996 | struct xhci_generic_trb *start_trb) |
8a96c052 | 2997 | { |
8a96c052 SS |
2998 | /* |
2999 | * Pass all the TRBs to the hardware at once and make sure this write | |
3000 | * isn't reordered. | |
3001 | */ | |
3002 | wmb(); | |
50f7b52a | 3003 | if (start_cycle) |
28ccd296 | 3004 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 3005 | else |
28ccd296 | 3006 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 3007 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
3008 | } |
3009 | ||
78140156 AI |
3010 | static void check_interval(struct xhci_hcd *xhci, struct urb *urb, |
3011 | struct xhci_ep_ctx *ep_ctx) | |
624defa1 | 3012 | { |
624defa1 SS |
3013 | int xhci_interval; |
3014 | int ep_interval; | |
3015 | ||
28ccd296 | 3016 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 | 3017 | ep_interval = urb->interval; |
78140156 | 3018 | |
624defa1 SS |
3019 | /* Convert to microframes */ |
3020 | if (urb->dev->speed == USB_SPEED_LOW || | |
3021 | urb->dev->speed == USB_SPEED_FULL) | |
3022 | ep_interval *= 8; | |
78140156 | 3023 | |
624defa1 SS |
3024 | /* FIXME change this to a warning and a suggestion to use the new API |
3025 | * to set the polling interval (once the API is added). | |
3026 | */ | |
3027 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3028 | dev_dbg_ratelimited(&urb->dev->dev, |
3029 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3030 | ep_interval, ep_interval == 1 ? "" : "s", | |
3031 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
624defa1 SS |
3032 | urb->interval = xhci_interval; |
3033 | /* Convert back to frames for LS/FS devices */ | |
3034 | if (urb->dev->speed == USB_SPEED_LOW || | |
3035 | urb->dev->speed == USB_SPEED_FULL) | |
3036 | urb->interval /= 8; | |
3037 | } | |
78140156 AI |
3038 | } |
3039 | ||
3040 | /* | |
3041 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
3042 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
3043 | * (comprised of sg list entries) can take several service intervals to | |
3044 | * transmit. | |
3045 | */ | |
3046 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3047 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3048 | { | |
3049 | struct xhci_ep_ctx *ep_ctx; | |
3050 | ||
3051 | ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); | |
3052 | check_interval(xhci, urb, ep_ctx); | |
3053 | ||
3fc8206d | 3054 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
3055 | } |
3056 | ||
4da6e6f2 | 3057 | /* |
4525c0a1 SS |
3058 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
3059 | * packets remaining in the TD (*not* including this TRB). | |
4da6e6f2 SS |
3060 | * |
3061 | * Total TD packet count = total_packet_count = | |
4525c0a1 | 3062 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
4da6e6f2 SS |
3063 | * |
3064 | * Packets transferred up to and including this TRB = packets_transferred = | |
3065 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
3066 | * | |
3067 | * TD size = total_packet_count - packets_transferred | |
3068 | * | |
c840d6ce MN |
3069 | * For xHCI 0.96 and older, TD size field should be the remaining bytes |
3070 | * including this TRB, right shifted by 10 | |
3071 | * | |
3072 | * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. | |
3073 | * This is taken care of in the TRB_TD_SIZE() macro | |
3074 | * | |
4525c0a1 | 3075 | * The last TRB in a TD must have the TD size set to zero. |
4da6e6f2 | 3076 | */ |
c840d6ce MN |
3077 | static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, |
3078 | int trb_buff_len, unsigned int td_total_len, | |
124c3937 | 3079 | struct urb *urb, bool more_trbs_coming) |
4da6e6f2 | 3080 | { |
c840d6ce MN |
3081 | u32 maxp, total_packet_count; |
3082 | ||
0cbd4b34 CY |
3083 | /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */ |
3084 | if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) | |
c840d6ce MN |
3085 | return ((td_total_len - transferred) >> 10); |
3086 | ||
48df4a6f | 3087 | /* One TRB with a zero-length data packet. */ |
124c3937 | 3088 | if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || |
c840d6ce | 3089 | trb_buff_len == td_total_len) |
48df4a6f SS |
3090 | return 0; |
3091 | ||
0cbd4b34 CY |
3092 | /* for MTK xHCI, TD size doesn't include this TRB */ |
3093 | if (xhci->quirks & XHCI_MTK_HOST) | |
3094 | trb_buff_len = 0; | |
3095 | ||
734d3ddd | 3096 | maxp = usb_endpoint_maxp(&urb->ep->desc); |
0cbd4b34 CY |
3097 | total_packet_count = DIV_ROUND_UP(td_total_len, maxp); |
3098 | ||
c840d6ce MN |
3099 | /* Queueing functions don't count the current TRB into transferred */ |
3100 | return (total_packet_count - ((transferred + trb_buff_len) / maxp)); | |
4da6e6f2 SS |
3101 | } |
3102 | ||
f9c589e1 | 3103 | |
474ed23a | 3104 | static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, |
f9c589e1 | 3105 | u32 *trb_buff_len, struct xhci_segment *seg) |
474ed23a | 3106 | { |
f9c589e1 | 3107 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
474ed23a MN |
3108 | unsigned int unalign; |
3109 | unsigned int max_pkt; | |
f9c589e1 | 3110 | u32 new_buff_len; |
474ed23a | 3111 | |
734d3ddd | 3112 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
474ed23a MN |
3113 | unalign = (enqd_len + *trb_buff_len) % max_pkt; |
3114 | ||
3115 | /* we got lucky, last normal TRB data on segment is packet aligned */ | |
3116 | if (unalign == 0) | |
3117 | return 0; | |
3118 | ||
f9c589e1 MN |
3119 | xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", |
3120 | unalign, *trb_buff_len); | |
3121 | ||
474ed23a MN |
3122 | /* is the last nornal TRB alignable by splitting it */ |
3123 | if (*trb_buff_len > unalign) { | |
3124 | *trb_buff_len -= unalign; | |
f9c589e1 | 3125 | xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); |
474ed23a MN |
3126 | return 0; |
3127 | } | |
f9c589e1 MN |
3128 | |
3129 | /* | |
3130 | * We want enqd_len + trb_buff_len to sum up to a number aligned to | |
3131 | * number which is divisible by the endpoint's wMaxPacketSize. IOW: | |
3132 | * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. | |
3133 | */ | |
3134 | new_buff_len = max_pkt - (enqd_len % max_pkt); | |
3135 | ||
3136 | if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) | |
3137 | new_buff_len = (urb->transfer_buffer_length - enqd_len); | |
3138 | ||
3139 | /* create a max max_pkt sized bounce buffer pointed to by last trb */ | |
3140 | if (usb_urb_dir_out(urb)) { | |
3141 | sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs, | |
3142 | seg->bounce_buf, new_buff_len, enqd_len); | |
3143 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3144 | max_pkt, DMA_TO_DEVICE); | |
3145 | } else { | |
3146 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3147 | max_pkt, DMA_FROM_DEVICE); | |
3148 | } | |
3149 | ||
3150 | if (dma_mapping_error(dev, seg->bounce_dma)) { | |
3151 | /* try without aligning. Some host controllers survive */ | |
3152 | xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); | |
3153 | return 0; | |
3154 | } | |
3155 | *trb_buff_len = new_buff_len; | |
3156 | seg->bounce_len = new_buff_len; | |
3157 | seg->bounce_offs = enqd_len; | |
3158 | ||
3159 | xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); | |
3160 | ||
474ed23a MN |
3161 | return 1; |
3162 | } | |
3163 | ||
d2510342 AI |
3164 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
3165 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
8a96c052 SS |
3166 | struct urb *urb, int slot_id, unsigned int ep_index) |
3167 | { | |
5a5a0b1a | 3168 | struct xhci_ring *ring; |
8e51adcc | 3169 | struct urb_priv *urb_priv; |
8a96c052 | 3170 | struct xhci_td *td; |
d2510342 AI |
3171 | struct xhci_generic_trb *start_trb; |
3172 | struct scatterlist *sg = NULL; | |
5a83f04a MN |
3173 | bool more_trbs_coming = true; |
3174 | bool need_zero_pkt = false; | |
86065c27 MN |
3175 | bool first_trb = true; |
3176 | unsigned int num_trbs; | |
d2510342 | 3177 | unsigned int start_cycle, num_sgs = 0; |
86065c27 | 3178 | unsigned int enqd_len, block_len, trb_buff_len, full_len; |
f9c589e1 | 3179 | int sent_len, ret; |
d2510342 | 3180 | u32 field, length_field, remainder; |
f9c589e1 | 3181 | u64 addr, send_addr; |
8a96c052 | 3182 | |
5a5a0b1a MN |
3183 | ring = xhci_urb_to_transfer_ring(xhci, urb); |
3184 | if (!ring) | |
e9df17eb SS |
3185 | return -EINVAL; |
3186 | ||
86065c27 | 3187 | full_len = urb->transfer_buffer_length; |
d2510342 AI |
3188 | /* If we have scatter/gather list, we use it. */ |
3189 | if (urb->num_sgs) { | |
3190 | num_sgs = urb->num_mapped_sgs; | |
3191 | sg = urb->sg; | |
86065c27 MN |
3192 | addr = (u64) sg_dma_address(sg); |
3193 | block_len = sg_dma_len(sg); | |
d2510342 | 3194 | num_trbs = count_sg_trbs_needed(urb); |
86065c27 | 3195 | } else { |
d2510342 | 3196 | num_trbs = count_trbs_needed(urb); |
86065c27 MN |
3197 | addr = (u64) urb->transfer_dma; |
3198 | block_len = full_len; | |
3199 | } | |
4758dcd1 | 3200 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 3201 | ep_index, urb->stream_id, |
3b72fca0 | 3202 | num_trbs, urb, 0, mem_flags); |
d2510342 | 3203 | if (unlikely(ret < 0)) |
4758dcd1 | 3204 | return ret; |
8e51adcc AX |
3205 | |
3206 | urb_priv = urb->hcpriv; | |
4758dcd1 RA |
3207 | |
3208 | /* Deal with URB_ZERO_PACKET - need one more td/trb */ | |
9ef7fbbb | 3209 | if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1) |
5a83f04a | 3210 | need_zero_pkt = true; |
4758dcd1 | 3211 | |
7e64b037 | 3212 | td = &urb_priv->td[0]; |
8e51adcc | 3213 | |
8a96c052 SS |
3214 | /* |
3215 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3216 | * until we've finished creating all the other TRBs. The ring's cycle | |
3217 | * state may change as we enqueue the other TRBs, so save it too. | |
3218 | */ | |
5a5a0b1a MN |
3219 | start_trb = &ring->enqueue->generic; |
3220 | start_cycle = ring->cycle_state; | |
f9c589e1 | 3221 | send_addr = addr; |
8a96c052 | 3222 | |
d2510342 | 3223 | /* Queue the TRBs, even if they are zero-length */ |
0d2daade AB |
3224 | for (enqd_len = 0; first_trb || enqd_len < full_len; |
3225 | enqd_len += trb_buff_len) { | |
d2510342 | 3226 | field = TRB_TYPE(TRB_NORMAL); |
af8b9e63 | 3227 | |
86065c27 MN |
3228 | /* TRB buffer should not cross 64KB boundaries */ |
3229 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); | |
3230 | trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); | |
8a96c052 | 3231 | |
86065c27 MN |
3232 | if (enqd_len + trb_buff_len > full_len) |
3233 | trb_buff_len = full_len - enqd_len; | |
b10de142 SS |
3234 | |
3235 | /* Don't change the cycle bit of the first TRB until later */ | |
86065c27 MN |
3236 | if (first_trb) { |
3237 | first_trb = false; | |
50f7b52a | 3238 | if (start_cycle == 0) |
d2510342 | 3239 | field |= TRB_CYCLE; |
50f7b52a | 3240 | } else |
5a5a0b1a | 3241 | field |= ring->cycle_state; |
b10de142 SS |
3242 | |
3243 | /* Chain all the TRBs together; clear the chain bit in the last | |
3244 | * TRB to indicate it's the last TRB in the chain. | |
3245 | */ | |
86065c27 | 3246 | if (enqd_len + trb_buff_len < full_len) { |
b10de142 | 3247 | field |= TRB_CHAIN; |
2d98ef40 | 3248 | if (trb_is_link(ring->enqueue + 1)) { |
474ed23a | 3249 | if (xhci_align_td(xhci, urb, enqd_len, |
f9c589e1 MN |
3250 | &trb_buff_len, |
3251 | ring->enq_seg)) { | |
3252 | send_addr = ring->enq_seg->bounce_dma; | |
3253 | /* assuming TD won't span 2 segs */ | |
3254 | td->bounce_seg = ring->enq_seg; | |
3255 | } | |
474ed23a | 3256 | } |
f9c589e1 MN |
3257 | } |
3258 | if (enqd_len + trb_buff_len >= full_len) { | |
3259 | field &= ~TRB_CHAIN; | |
4758dcd1 | 3260 | field |= TRB_IOC; |
124c3937 | 3261 | more_trbs_coming = false; |
5a83f04a | 3262 | td->last_trb = ring->enqueue; |
b10de142 | 3263 | } |
af8b9e63 SS |
3264 | |
3265 | /* Only set interrupt on short packet for IN endpoints */ | |
3266 | if (usb_urb_dir_in(urb)) | |
3267 | field |= TRB_ISP; | |
3268 | ||
4da6e6f2 | 3269 | /* Set the TRB length, TD size, and interrupter fields. */ |
86065c27 MN |
3270 | remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, |
3271 | full_len, urb, more_trbs_coming); | |
3272 | ||
f9dc68fe | 3273 | length_field = TRB_LEN(trb_buff_len) | |
c840d6ce | 3274 | TRB_TD_SIZE(remainder) | |
f9dc68fe | 3275 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3276 | |
124c3937 | 3277 | queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, |
f9c589e1 MN |
3278 | lower_32_bits(send_addr), |
3279 | upper_32_bits(send_addr), | |
f9dc68fe | 3280 | length_field, |
d2510342 | 3281 | field); |
b10de142 | 3282 | |
b10de142 | 3283 | addr += trb_buff_len; |
f9c589e1 | 3284 | sent_len = trb_buff_len; |
d2510342 | 3285 | |
f9c589e1 | 3286 | while (sg && sent_len >= block_len) { |
86065c27 MN |
3287 | /* New sg entry */ |
3288 | --num_sgs; | |
f9c589e1 | 3289 | sent_len -= block_len; |
86065c27 | 3290 | if (num_sgs != 0) { |
d2510342 | 3291 | sg = sg_next(sg); |
86065c27 MN |
3292 | block_len = sg_dma_len(sg); |
3293 | addr = (u64) sg_dma_address(sg); | |
f9c589e1 | 3294 | addr += sent_len; |
d2510342 AI |
3295 | } |
3296 | } | |
f9c589e1 MN |
3297 | block_len -= sent_len; |
3298 | send_addr = addr; | |
d2510342 | 3299 | } |
b10de142 | 3300 | |
5a83f04a MN |
3301 | if (need_zero_pkt) { |
3302 | ret = prepare_transfer(xhci, xhci->devs[slot_id], | |
3303 | ep_index, urb->stream_id, | |
3304 | 1, urb, 1, mem_flags); | |
7e64b037 | 3305 | urb_priv->td[1].last_trb = ring->enqueue; |
5a83f04a MN |
3306 | field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; |
3307 | queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); | |
3308 | } | |
3309 | ||
86065c27 | 3310 | check_trb_math(urb, enqd_len); |
e9df17eb | 3311 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3312 | start_cycle, start_trb); |
b10de142 SS |
3313 | return 0; |
3314 | } | |
3315 | ||
d0e96f5a | 3316 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3317 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3318 | struct urb *urb, int slot_id, unsigned int ep_index) |
3319 | { | |
3320 | struct xhci_ring *ep_ring; | |
3321 | int num_trbs; | |
3322 | int ret; | |
3323 | struct usb_ctrlrequest *setup; | |
3324 | struct xhci_generic_trb *start_trb; | |
3325 | int start_cycle; | |
fb79a6da | 3326 | u32 field; |
8e51adcc | 3327 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3328 | struct xhci_td *td; |
3329 | ||
e9df17eb SS |
3330 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3331 | if (!ep_ring) | |
3332 | return -EINVAL; | |
d0e96f5a SS |
3333 | |
3334 | /* | |
3335 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3336 | * DMA address. | |
3337 | */ | |
3338 | if (!urb->setup_packet) | |
3339 | return -EINVAL; | |
3340 | ||
d0e96f5a SS |
3341 | /* 1 TRB for setup, 1 for status */ |
3342 | num_trbs = 2; | |
3343 | /* | |
3344 | * Don't need to check if we need additional event data and normal TRBs, | |
3345 | * since data in control transfers will never get bigger than 16MB | |
3346 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3347 | */ | |
3348 | if (urb->transfer_buffer_length > 0) | |
3349 | num_trbs++; | |
e9df17eb SS |
3350 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3351 | ep_index, urb->stream_id, | |
3b72fca0 | 3352 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3353 | if (ret < 0) |
3354 | return ret; | |
3355 | ||
8e51adcc | 3356 | urb_priv = urb->hcpriv; |
7e64b037 | 3357 | td = &urb_priv->td[0]; |
8e51adcc | 3358 | |
d0e96f5a SS |
3359 | /* |
3360 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3361 | * until we've finished creating all the other TRBs. The ring's cycle | |
3362 | * state may change as we enqueue the other TRBs, so save it too. | |
3363 | */ | |
3364 | start_trb = &ep_ring->enqueue->generic; | |
3365 | start_cycle = ep_ring->cycle_state; | |
3366 | ||
3367 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3368 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3369 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3370 | field = 0; |
3371 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3372 | if (start_cycle == 0) | |
3373 | field |= 0x1; | |
b83cdc8f | 3374 | |
dca77945 | 3375 | /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ |
0cbd4b34 | 3376 | if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { |
b83cdc8f AX |
3377 | if (urb->transfer_buffer_length > 0) { |
3378 | if (setup->bRequestType & USB_DIR_IN) | |
3379 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3380 | else | |
3381 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3382 | } | |
3383 | } | |
3384 | ||
3b72fca0 | 3385 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3386 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3387 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3388 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3389 | /* Immediate data in pointer */ | |
3390 | field); | |
d0e96f5a SS |
3391 | |
3392 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3393 | /* Only set interrupt on short packet for IN endpoints */ |
3394 | if (usb_urb_dir_in(urb)) | |
3395 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3396 | else | |
3397 | field = TRB_TYPE(TRB_DATA); | |
3398 | ||
d0e96f5a | 3399 | if (urb->transfer_buffer_length > 0) { |
fb79a6da LB |
3400 | u32 length_field, remainder; |
3401 | ||
3402 | remainder = xhci_td_remainder(xhci, 0, | |
3403 | urb->transfer_buffer_length, | |
3404 | urb->transfer_buffer_length, | |
3405 | urb, 1); | |
3406 | length_field = TRB_LEN(urb->transfer_buffer_length) | | |
3407 | TRB_TD_SIZE(remainder) | | |
3408 | TRB_INTR_TARGET(0); | |
d0e96f5a SS |
3409 | if (setup->bRequestType & USB_DIR_IN) |
3410 | field |= TRB_DIR_IN; | |
3b72fca0 | 3411 | queue_trb(xhci, ep_ring, true, |
d0e96f5a SS |
3412 | lower_32_bits(urb->transfer_dma), |
3413 | upper_32_bits(urb->transfer_dma), | |
f9dc68fe | 3414 | length_field, |
af8b9e63 | 3415 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3416 | } |
3417 | ||
3418 | /* Save the DMA address of the last TRB in the TD */ | |
3419 | td->last_trb = ep_ring->enqueue; | |
3420 | ||
3421 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3422 | /* If the device sent data, the status stage is an OUT transfer */ | |
3423 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3424 | field = 0; | |
3425 | else | |
3426 | field = TRB_DIR_IN; | |
3b72fca0 | 3427 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3428 | 0, |
3429 | 0, | |
3430 | TRB_INTR_TARGET(0), | |
3431 | /* Event on completion */ | |
3432 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3433 | ||
e9df17eb | 3434 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3435 | start_cycle, start_trb); |
d0e96f5a SS |
3436 | return 0; |
3437 | } | |
3438 | ||
5cd43e33 SS |
3439 | /* |
3440 | * The transfer burst count field of the isochronous TRB defines the number of | |
3441 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3442 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3443 | * This field is zero based, meaning a value of zero in the field means one | |
3444 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3445 | * zero. Only xHCI 1.0 host controllers support this field. | |
3446 | */ | |
3447 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
5cd43e33 SS |
3448 | struct urb *urb, unsigned int total_packet_count) |
3449 | { | |
3450 | unsigned int max_burst; | |
3451 | ||
09c352ed | 3452 | if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) |
5cd43e33 SS |
3453 | return 0; |
3454 | ||
3455 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3213b151 | 3456 | return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; |
5cd43e33 SS |
3457 | } |
3458 | ||
b61d378f SS |
3459 | /* |
3460 | * Returns the number of packets in the last "burst" of packets. This field is | |
3461 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3462 | * the last burst packet count is equal to the total number of packets in the | |
3463 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3464 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3465 | * contain 1 to (bMaxBurst + 1) packets. | |
3466 | */ | |
3467 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
b61d378f SS |
3468 | struct urb *urb, unsigned int total_packet_count) |
3469 | { | |
3470 | unsigned int max_burst; | |
3471 | unsigned int residue; | |
3472 | ||
3473 | if (xhci->hci_version < 0x100) | |
3474 | return 0; | |
3475 | ||
09c352ed | 3476 | if (urb->dev->speed >= USB_SPEED_SUPER) { |
b61d378f SS |
3477 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ |
3478 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3479 | residue = total_packet_count % (max_burst + 1); | |
3480 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3481 | * number of packets, but the TLBPC field is zero-based. | |
3482 | */ | |
3483 | if (residue == 0) | |
3484 | return max_burst; | |
3485 | return residue - 1; | |
b61d378f | 3486 | } |
09c352ed MN |
3487 | if (total_packet_count == 0) |
3488 | return 0; | |
3489 | return total_packet_count - 1; | |
b61d378f SS |
3490 | } |
3491 | ||
79b8094f LB |
3492 | /* |
3493 | * Calculates Frame ID field of the isochronous TRB identifies the | |
3494 | * target frame that the Interval associated with this Isochronous | |
3495 | * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. | |
3496 | * | |
3497 | * Returns actual frame id on success, negative value on error. | |
3498 | */ | |
3499 | static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, | |
3500 | struct urb *urb, int index) | |
3501 | { | |
3502 | int start_frame, ist, ret = 0; | |
3503 | int start_frame_id, end_frame_id, current_frame_id; | |
3504 | ||
3505 | if (urb->dev->speed == USB_SPEED_LOW || | |
3506 | urb->dev->speed == USB_SPEED_FULL) | |
3507 | start_frame = urb->start_frame + index * urb->interval; | |
3508 | else | |
3509 | start_frame = (urb->start_frame + index * urb->interval) >> 3; | |
3510 | ||
3511 | /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): | |
3512 | * | |
3513 | * If bit [3] of IST is cleared to '0', software can add a TRB no | |
3514 | * later than IST[2:0] Microframes before that TRB is scheduled to | |
3515 | * be executed. | |
3516 | * If bit [3] of IST is set to '1', software can add a TRB no later | |
3517 | * than IST[2:0] Frames before that TRB is scheduled to be executed. | |
3518 | */ | |
3519 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3520 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3521 | ist <<= 3; | |
3522 | ||
3523 | /* Software shall not schedule an Isoch TD with a Frame ID value that | |
3524 | * is less than the Start Frame ID or greater than the End Frame ID, | |
3525 | * where: | |
3526 | * | |
3527 | * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 | |
3528 | * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 | |
3529 | * | |
3530 | * Both the End Frame ID and Start Frame ID values are calculated | |
3531 | * in microframes. When software determines the valid Frame ID value; | |
3532 | * The End Frame ID value should be rounded down to the nearest Frame | |
3533 | * boundary, and the Start Frame ID value should be rounded up to the | |
3534 | * nearest Frame boundary. | |
3535 | */ | |
3536 | current_frame_id = readl(&xhci->run_regs->microframe_index); | |
3537 | start_frame_id = roundup(current_frame_id + ist + 1, 8); | |
3538 | end_frame_id = rounddown(current_frame_id + 895 * 8, 8); | |
3539 | ||
3540 | start_frame &= 0x7ff; | |
3541 | start_frame_id = (start_frame_id >> 3) & 0x7ff; | |
3542 | end_frame_id = (end_frame_id >> 3) & 0x7ff; | |
3543 | ||
3544 | xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", | |
3545 | __func__, index, readl(&xhci->run_regs->microframe_index), | |
3546 | start_frame_id, end_frame_id, start_frame); | |
3547 | ||
3548 | if (start_frame_id < end_frame_id) { | |
3549 | if (start_frame > end_frame_id || | |
3550 | start_frame < start_frame_id) | |
3551 | ret = -EINVAL; | |
3552 | } else if (start_frame_id > end_frame_id) { | |
3553 | if ((start_frame > end_frame_id && | |
3554 | start_frame < start_frame_id)) | |
3555 | ret = -EINVAL; | |
3556 | } else { | |
3557 | ret = -EINVAL; | |
3558 | } | |
3559 | ||
3560 | if (index == 0) { | |
3561 | if (ret == -EINVAL || start_frame == start_frame_id) { | |
3562 | start_frame = start_frame_id + 1; | |
3563 | if (urb->dev->speed == USB_SPEED_LOW || | |
3564 | urb->dev->speed == USB_SPEED_FULL) | |
3565 | urb->start_frame = start_frame; | |
3566 | else | |
3567 | urb->start_frame = start_frame << 3; | |
3568 | ret = 0; | |
3569 | } | |
3570 | } | |
3571 | ||
3572 | if (ret) { | |
3573 | xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", | |
3574 | start_frame, current_frame_id, index, | |
3575 | start_frame_id, end_frame_id); | |
3576 | xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); | |
3577 | return ret; | |
3578 | } | |
3579 | ||
3580 | return start_frame; | |
3581 | } | |
3582 | ||
04e51901 AX |
3583 | /* This is for isoc transfer */ |
3584 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3585 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3586 | { | |
3587 | struct xhci_ring *ep_ring; | |
3588 | struct urb_priv *urb_priv; | |
3589 | struct xhci_td *td; | |
3590 | int num_tds, trbs_per_td; | |
3591 | struct xhci_generic_trb *start_trb; | |
3592 | bool first_trb; | |
3593 | int start_cycle; | |
3594 | u32 field, length_field; | |
3595 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
3596 | u64 start_addr, addr; | |
3597 | int i, j; | |
47cbf692 | 3598 | bool more_trbs_coming; |
79b8094f | 3599 | struct xhci_virt_ep *xep; |
09c352ed | 3600 | int frame_id; |
04e51901 | 3601 | |
79b8094f | 3602 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
3603 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
3604 | ||
3605 | num_tds = urb->number_of_packets; | |
3606 | if (num_tds < 1) { | |
3607 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
3608 | return -EINVAL; | |
3609 | } | |
04e51901 AX |
3610 | start_addr = (u64) urb->transfer_dma; |
3611 | start_trb = &ep_ring->enqueue->generic; | |
3612 | start_cycle = ep_ring->cycle_state; | |
3613 | ||
522989a2 | 3614 | urb_priv = urb->hcpriv; |
09c352ed | 3615 | /* Queue the TRBs for each TD, even if they are zero-length */ |
04e51901 | 3616 | for (i = 0; i < num_tds; i++) { |
09c352ed MN |
3617 | unsigned int total_pkt_count, max_pkt; |
3618 | unsigned int burst_count, last_burst_pkt_count; | |
3619 | u32 sia_frame_id; | |
04e51901 | 3620 | |
4da6e6f2 | 3621 | first_trb = true; |
04e51901 AX |
3622 | running_total = 0; |
3623 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
3624 | td_len = urb->iso_frame_desc[i].length; | |
3625 | td_remain_len = td_len; | |
734d3ddd | 3626 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
09c352ed MN |
3627 | total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); |
3628 | ||
48df4a6f | 3629 | /* A zero-length transfer still involves at least one packet. */ |
09c352ed MN |
3630 | if (total_pkt_count == 0) |
3631 | total_pkt_count++; | |
3632 | burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); | |
3633 | last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, | |
3634 | urb, total_pkt_count); | |
04e51901 | 3635 | |
d2510342 | 3636 | trbs_per_td = count_isoc_trbs_needed(urb, i); |
04e51901 AX |
3637 | |
3638 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 3639 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
3640 | if (ret < 0) { |
3641 | if (i == 0) | |
3642 | return ret; | |
3643 | goto cleanup; | |
3644 | } | |
7e64b037 | 3645 | td = &urb_priv->td[i]; |
09c352ed MN |
3646 | |
3647 | /* use SIA as default, if frame id is used overwrite it */ | |
3648 | sia_frame_id = TRB_SIA; | |
3649 | if (!(urb->transfer_flags & URB_ISO_ASAP) && | |
3650 | HCC_CFC(xhci->hcc_params)) { | |
3651 | frame_id = xhci_get_isoc_frame_id(xhci, urb, i); | |
3652 | if (frame_id >= 0) | |
3653 | sia_frame_id = TRB_FRAME_ID(frame_id); | |
3654 | } | |
3655 | /* | |
3656 | * Set isoc specific data for the first TRB in a TD. | |
3657 | * Prevent HW from getting the TRBs by keeping the cycle state | |
3658 | * inverted in the first TDs isoc TRB. | |
3659 | */ | |
2f6d3b65 | 3660 | field = TRB_TYPE(TRB_ISOC) | |
09c352ed MN |
3661 | TRB_TLBPC(last_burst_pkt_count) | |
3662 | sia_frame_id | | |
3663 | (i ? ep_ring->cycle_state : !start_cycle); | |
3664 | ||
2f6d3b65 MN |
3665 | /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ |
3666 | if (!xep->use_extended_tbc) | |
3667 | field |= TRB_TBC(burst_count); | |
3668 | ||
09c352ed | 3669 | /* fill the rest of the TRB fields, and remaining normal TRBs */ |
04e51901 AX |
3670 | for (j = 0; j < trbs_per_td; j++) { |
3671 | u32 remainder = 0; | |
09c352ed MN |
3672 | |
3673 | /* only first TRB is isoc, overwrite otherwise */ | |
3674 | if (!first_trb) | |
3675 | field = TRB_TYPE(TRB_NORMAL) | | |
3676 | ep_ring->cycle_state; | |
04e51901 | 3677 | |
af8b9e63 SS |
3678 | /* Only set interrupt on short packet for IN EPs */ |
3679 | if (usb_urb_dir_in(urb)) | |
3680 | field |= TRB_ISP; | |
3681 | ||
09c352ed | 3682 | /* Set the chain bit for all except the last TRB */ |
04e51901 | 3683 | if (j < trbs_per_td - 1) { |
47cbf692 | 3684 | more_trbs_coming = true; |
09c352ed | 3685 | field |= TRB_CHAIN; |
04e51901 | 3686 | } else { |
09c352ed | 3687 | more_trbs_coming = false; |
04e51901 AX |
3688 | td->last_trb = ep_ring->enqueue; |
3689 | field |= TRB_IOC; | |
09c352ed MN |
3690 | /* set BEI, except for the last TD */ |
3691 | if (xhci->hci_version >= 0x100 && | |
3692 | !(xhci->quirks & XHCI_AVOID_BEI) && | |
3693 | i < num_tds - 1) | |
3694 | field |= TRB_BEI; | |
04e51901 | 3695 | } |
04e51901 | 3696 | /* Calculate TRB length */ |
d2510342 | 3697 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); |
04e51901 AX |
3698 | if (trb_buff_len > td_remain_len) |
3699 | trb_buff_len = td_remain_len; | |
3700 | ||
4da6e6f2 | 3701 | /* Set the TRB length, TD size, & interrupter fields. */ |
c840d6ce MN |
3702 | remainder = xhci_td_remainder(xhci, running_total, |
3703 | trb_buff_len, td_len, | |
124c3937 | 3704 | urb, more_trbs_coming); |
c840d6ce | 3705 | |
04e51901 | 3706 | length_field = TRB_LEN(trb_buff_len) | |
04e51901 | 3707 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3708 | |
2f6d3b65 MN |
3709 | /* xhci 1.1 with ETE uses TD Size field for TBC */ |
3710 | if (first_trb && xep->use_extended_tbc) | |
3711 | length_field |= TRB_TD_SIZE_TBC(burst_count); | |
3712 | else | |
3713 | length_field |= TRB_TD_SIZE(remainder); | |
3714 | first_trb = false; | |
3715 | ||
3b72fca0 | 3716 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
3717 | lower_32_bits(addr), |
3718 | upper_32_bits(addr), | |
3719 | length_field, | |
af8b9e63 | 3720 | field); |
04e51901 AX |
3721 | running_total += trb_buff_len; |
3722 | ||
3723 | addr += trb_buff_len; | |
3724 | td_remain_len -= trb_buff_len; | |
3725 | } | |
3726 | ||
3727 | /* Check TD length */ | |
3728 | if (running_total != td_len) { | |
3729 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
3730 | ret = -EINVAL; |
3731 | goto cleanup; | |
04e51901 AX |
3732 | } |
3733 | } | |
3734 | ||
79b8094f LB |
3735 | /* store the next frame id */ |
3736 | if (HCC_CFC(xhci->hcc_params)) | |
3737 | xep->next_frame_id = urb->start_frame + num_tds * urb->interval; | |
3738 | ||
c41136b0 AX |
3739 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
3740 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
3741 | usb_amd_quirk_pll_disable(); | |
3742 | } | |
3743 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
3744 | ||
e1eab2e0 AX |
3745 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
3746 | start_cycle, start_trb); | |
04e51901 | 3747 | return 0; |
522989a2 SS |
3748 | cleanup: |
3749 | /* Clean up a partially enqueued isoc transfer. */ | |
3750 | ||
3751 | for (i--; i >= 0; i--) | |
7e64b037 | 3752 | list_del_init(&urb_priv->td[i].td_list); |
522989a2 SS |
3753 | |
3754 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
3755 | * into No-ops with a software-owned cycle bit. That way the hardware | |
3756 | * won't accidentally start executing bogus TDs when we partially | |
3757 | * overwrite them. td->first_trb and td->start_seg are already set. | |
3758 | */ | |
7e64b037 | 3759 | urb_priv->td[0].last_trb = ep_ring->enqueue; |
522989a2 | 3760 | /* Every TRB except the first & last will have its cycle bit flipped. */ |
7e64b037 | 3761 | td_to_noop(xhci, ep_ring, &urb_priv->td[0], true); |
522989a2 SS |
3762 | |
3763 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
7e64b037 MN |
3764 | ep_ring->enqueue = urb_priv->td[0].first_trb; |
3765 | ep_ring->enq_seg = urb_priv->td[0].start_seg; | |
522989a2 | 3766 | ep_ring->cycle_state = start_cycle; |
b008df60 | 3767 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
3768 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
3769 | return ret; | |
04e51901 AX |
3770 | } |
3771 | ||
3772 | /* | |
3773 | * Check transfer ring to guarantee there is enough room for the urb. | |
3774 | * Update ISO URB start_frame and interval. | |
79b8094f LB |
3775 | * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to |
3776 | * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or | |
3777 | * Contiguous Frame ID is not supported by HC. | |
04e51901 AX |
3778 | */ |
3779 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3780 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3781 | { | |
3782 | struct xhci_virt_device *xdev; | |
3783 | struct xhci_ring *ep_ring; | |
3784 | struct xhci_ep_ctx *ep_ctx; | |
3785 | int start_frame; | |
04e51901 AX |
3786 | int num_tds, num_trbs, i; |
3787 | int ret; | |
79b8094f LB |
3788 | struct xhci_virt_ep *xep; |
3789 | int ist; | |
04e51901 AX |
3790 | |
3791 | xdev = xhci->devs[slot_id]; | |
79b8094f | 3792 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
3793 | ep_ring = xdev->eps[ep_index].ring; |
3794 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
3795 | ||
3796 | num_trbs = 0; | |
3797 | num_tds = urb->number_of_packets; | |
3798 | for (i = 0; i < num_tds; i++) | |
d2510342 | 3799 | num_trbs += count_isoc_trbs_needed(urb, i); |
04e51901 AX |
3800 | |
3801 | /* Check the ring to guarantee there is enough room for the whole urb. | |
3802 | * Do not insert any td of the urb to the ring if the check failed. | |
3803 | */ | |
5071e6b2 | 3804 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 3805 | num_trbs, mem_flags); |
04e51901 AX |
3806 | if (ret) |
3807 | return ret; | |
3808 | ||
79b8094f LB |
3809 | /* |
3810 | * Check interval value. This should be done before we start to | |
3811 | * calculate the start frame value. | |
3812 | */ | |
78140156 | 3813 | check_interval(xhci, urb, ep_ctx); |
79b8094f LB |
3814 | |
3815 | /* Calculate the start frame and put it in urb->start_frame. */ | |
42df7215 | 3816 | if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { |
5071e6b2 | 3817 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) { |
42df7215 LB |
3818 | urb->start_frame = xep->next_frame_id; |
3819 | goto skip_start_over; | |
3820 | } | |
79b8094f LB |
3821 | } |
3822 | ||
3823 | start_frame = readl(&xhci->run_regs->microframe_index); | |
3824 | start_frame &= 0x3fff; | |
3825 | /* | |
3826 | * Round up to the next frame and consider the time before trb really | |
3827 | * gets scheduled by hardare. | |
3828 | */ | |
3829 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3830 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3831 | ist <<= 3; | |
3832 | start_frame += ist + XHCI_CFC_DELAY; | |
3833 | start_frame = roundup(start_frame, 8); | |
3834 | ||
3835 | /* | |
3836 | * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT | |
3837 | * is greate than 8 microframes. | |
3838 | */ | |
3839 | if (urb->dev->speed == USB_SPEED_LOW || | |
3840 | urb->dev->speed == USB_SPEED_FULL) { | |
3841 | start_frame = roundup(start_frame, urb->interval << 3); | |
3842 | urb->start_frame = start_frame >> 3; | |
3843 | } else { | |
3844 | start_frame = roundup(start_frame, urb->interval); | |
3845 | urb->start_frame = start_frame; | |
3846 | } | |
3847 | ||
3848 | skip_start_over: | |
b008df60 AX |
3849 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
3850 | ||
3fc8206d | 3851 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
3852 | } |
3853 | ||
d0e96f5a SS |
3854 | /**** Command Ring Operations ****/ |
3855 | ||
913a8a34 SS |
3856 | /* Generic function for queueing a command TRB on the command ring. |
3857 | * Check to make sure there's room on the command ring for one command TRB. | |
3858 | * Also check that there's room reserved for commands that must not fail. | |
3859 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
3860 | * then only check for the number of reserved spots. | |
3861 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
3862 | * because the command event handler may want to resubmit a failed command. | |
3863 | */ | |
ddba5cd0 MN |
3864 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3865 | u32 field1, u32 field2, | |
3866 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 3867 | { |
913a8a34 | 3868 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a | 3869 | int ret; |
ad6b1d91 | 3870 | |
98d74f9c MN |
3871 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
3872 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
ad6b1d91 | 3873 | xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); |
c9aa1a2d | 3874 | return -ESHUTDOWN; |
ad6b1d91 | 3875 | } |
d1dc908a | 3876 | |
913a8a34 SS |
3877 | if (!command_must_succeed) |
3878 | reserved_trbs++; | |
3879 | ||
d1dc908a | 3880 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 3881 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
3882 | if (ret < 0) { |
3883 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
3884 | if (command_must_succeed) |
3885 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
3886 | "unfailable commands failed.\n"); | |
d1dc908a | 3887 | return ret; |
7f84eef0 | 3888 | } |
c9aa1a2d MN |
3889 | |
3890 | cmd->command_trb = xhci->cmd_ring->enqueue; | |
ddba5cd0 | 3891 | |
c311e391 | 3892 | /* if there are no other commands queued we start the timeout timer */ |
daa47f21 | 3893 | if (list_empty(&xhci->cmd_list)) { |
c311e391 | 3894 | xhci->current_cmd = cmd; |
cb4d5ce5 | 3895 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
c311e391 MN |
3896 | } |
3897 | ||
daa47f21 LB |
3898 | list_add_tail(&cmd->cmd_list, &xhci->cmd_list); |
3899 | ||
3b72fca0 AX |
3900 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
3901 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
3902 | return 0; |
3903 | } | |
3904 | ||
3ffbba95 | 3905 | /* Queue a slot enable or disable request on the command ring */ |
ddba5cd0 MN |
3906 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3907 | u32 trb_type, u32 slot_id) | |
3ffbba95 | 3908 | { |
ddba5cd0 | 3909 | return queue_command(xhci, cmd, 0, 0, 0, |
913a8a34 | 3910 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
3911 | } |
3912 | ||
3913 | /* Queue an address device command TRB */ | |
ddba5cd0 MN |
3914 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3915 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) | |
3ffbba95 | 3916 | { |
ddba5cd0 | 3917 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3918 | upper_32_bits(in_ctx_ptr), 0, |
48fc7dbd DW |
3919 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
3920 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); | |
2a8f82c4 SS |
3921 | } |
3922 | ||
ddba5cd0 | 3923 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
0238634d SS |
3924 | u32 field1, u32 field2, u32 field3, u32 field4) |
3925 | { | |
ddba5cd0 | 3926 | return queue_command(xhci, cmd, field1, field2, field3, field4, false); |
0238634d SS |
3927 | } |
3928 | ||
2a8f82c4 | 3929 | /* Queue a reset device command TRB */ |
ddba5cd0 MN |
3930 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3931 | u32 slot_id) | |
2a8f82c4 | 3932 | { |
ddba5cd0 | 3933 | return queue_command(xhci, cmd, 0, 0, 0, |
2a8f82c4 | 3934 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
913a8a34 | 3935 | false); |
3ffbba95 | 3936 | } |
f94e0186 SS |
3937 | |
3938 | /* Queue a configure endpoint command TRB */ | |
ddba5cd0 MN |
3939 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
3940 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, | |
913a8a34 | 3941 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 3942 | { |
ddba5cd0 | 3943 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 3944 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 SS |
3945 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
3946 | command_must_succeed); | |
f94e0186 | 3947 | } |
ae636747 | 3948 | |
f2217e8e | 3949 | /* Queue an evaluate context command TRB */ |
ddba5cd0 MN |
3950 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3951 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) | |
f2217e8e | 3952 | { |
ddba5cd0 | 3953 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
f2217e8e | 3954 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 | 3955 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 3956 | command_must_succeed); |
f2217e8e SS |
3957 | } |
3958 | ||
be88fe4f AX |
3959 | /* |
3960 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
3961 | * activity on an endpoint that is about to be suspended. | |
3962 | */ | |
ddba5cd0 MN |
3963 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
3964 | int slot_id, unsigned int ep_index, int suspend) | |
ae636747 SS |
3965 | { |
3966 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3967 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
3968 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 3969 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 | 3970 | |
ddba5cd0 | 3971 | return queue_command(xhci, cmd, 0, 0, 0, |
be88fe4f | 3972 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
3973 | } |
3974 | ||
d3a43e66 HG |
3975 | /* Set Transfer Ring Dequeue Pointer command */ |
3976 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, | |
3977 | unsigned int slot_id, unsigned int ep_index, | |
3978 | unsigned int stream_id, | |
3979 | struct xhci_dequeue_state *deq_state) | |
ae636747 SS |
3980 | { |
3981 | dma_addr_t addr; | |
3982 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
3983 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
e9df17eb | 3984 | u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id); |
95241dbd | 3985 | u32 trb_sct = 0; |
ae636747 | 3986 | u32 type = TRB_TYPE(TRB_SET_DEQ); |
bf161e85 | 3987 | struct xhci_virt_ep *ep; |
1e3452e3 HG |
3988 | struct xhci_command *cmd; |
3989 | int ret; | |
ae636747 | 3990 | |
d3a43e66 HG |
3991 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
3992 | "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u", | |
3993 | deq_state->new_deq_seg, | |
3994 | (unsigned long long)deq_state->new_deq_seg->dma, | |
3995 | deq_state->new_deq_ptr, | |
3996 | (unsigned long long)xhci_trb_virt_to_dma( | |
3997 | deq_state->new_deq_seg, deq_state->new_deq_ptr), | |
3998 | deq_state->new_cycle_state); | |
3999 | ||
4000 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
4001 | deq_state->new_deq_ptr); | |
c92bcfa7 | 4002 | if (addr == 0) { |
ae636747 | 4003 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); |
700e2052 | 4004 | xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n", |
d3a43e66 HG |
4005 | deq_state->new_deq_seg, deq_state->new_deq_ptr); |
4006 | return; | |
c92bcfa7 | 4007 | } |
bf161e85 SS |
4008 | ep = &xhci->devs[slot_id]->eps[ep_index]; |
4009 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
4010 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n"); | |
4011 | xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n"); | |
d3a43e66 | 4012 | return; |
bf161e85 | 4013 | } |
1e3452e3 HG |
4014 | |
4015 | /* This function gets called from contexts where it cannot sleep */ | |
4016 | cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); | |
4017 | if (!cmd) { | |
4018 | xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n"); | |
d3a43e66 | 4019 | return; |
1e3452e3 HG |
4020 | } |
4021 | ||
d3a43e66 HG |
4022 | ep->queued_deq_seg = deq_state->new_deq_seg; |
4023 | ep->queued_deq_ptr = deq_state->new_deq_ptr; | |
95241dbd HG |
4024 | if (stream_id) |
4025 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); | |
1e3452e3 | 4026 | ret = queue_command(xhci, cmd, |
d3a43e66 HG |
4027 | lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state, |
4028 | upper_32_bits(addr), trb_stream_id, | |
4029 | trb_slot_id | trb_ep_index | type, false); | |
1e3452e3 HG |
4030 | if (ret < 0) { |
4031 | xhci_free_command(xhci, cmd); | |
d3a43e66 | 4032 | return; |
1e3452e3 HG |
4033 | } |
4034 | ||
d3a43e66 HG |
4035 | /* Stop the TD queueing code from ringing the doorbell until |
4036 | * this command completes. The HC won't set the dequeue pointer | |
4037 | * if the ring is running, and ringing the doorbell starts the | |
4038 | * ring running. | |
4039 | */ | |
4040 | ep->ep_state |= SET_DEQ_PENDING; | |
ae636747 | 4041 | } |
a1587d97 | 4042 | |
ddba5cd0 MN |
4043 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4044 | int slot_id, unsigned int ep_index) | |
a1587d97 SS |
4045 | { |
4046 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4047 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4048 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
4049 | ||
ddba5cd0 MN |
4050 | return queue_command(xhci, cmd, 0, 0, 0, |
4051 | trb_slot_id | trb_ep_index | type, false); | |
a1587d97 | 4052 | } |