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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
7f84eef0 SS |
2 | /* |
3 | * xHCI host controller driver | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
7f84eef0 SS |
9 | */ |
10 | ||
11 | /* | |
12 | * Ring initialization rules: | |
13 | * 1. Each segment is initialized to zero, except for link TRBs. | |
14 | * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or | |
15 | * Consumer Cycle State (CCS), depending on ring function. | |
16 | * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment. | |
17 | * | |
18 | * Ring behavior rules: | |
19 | * 1. A ring is empty if enqueue == dequeue. This means there will always be at | |
20 | * least one free TRB in the ring. This is useful if you want to turn that | |
21 | * into a link TRB and expand the ring. | |
22 | * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a | |
23 | * link TRB, then load the pointer with the address in the link TRB. If the | |
24 | * link TRB had its toggle bit set, you may need to update the ring cycle | |
25 | * state (see cycle bit rules). You may have to do this multiple times | |
26 | * until you reach a non-link TRB. | |
27 | * 3. A ring is full if enqueue++ (for the definition of increment above) | |
28 | * equals the dequeue pointer. | |
29 | * | |
30 | * Cycle bit rules: | |
31 | * 1. When a consumer increments a dequeue pointer and encounters a toggle bit | |
32 | * in a link TRB, it must toggle the ring cycle state. | |
33 | * 2. When a producer increments an enqueue pointer and encounters a toggle bit | |
34 | * in a link TRB, it must toggle the ring cycle state. | |
35 | * | |
36 | * Producer rules: | |
37 | * 1. Check if ring is full before you enqueue. | |
38 | * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing. | |
39 | * Update enqueue pointer between each write (which may update the ring | |
40 | * cycle state). | |
41 | * 3. Notify consumer. If SW is producer, it rings the doorbell for command | |
42 | * and endpoint rings. If HC is the producer for the event ring, | |
43 | * and it generates an interrupt according to interrupt modulation rules. | |
44 | * | |
45 | * Consumer rules: | |
46 | * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state, | |
47 | * the TRB is owned by the consumer. | |
48 | * 2. Update dequeue pointer (which may update the ring cycle state) and | |
49 | * continue processing TRBs until you reach a TRB which is not owned by you. | |
50 | * 3. Notify the producer. SW is the consumer for the event ring, and it | |
51 | * updates event ring dequeue pointer. HC is the consumer for the command and | |
52 | * endpoint rings; it generates events on the event ring for these. | |
53 | */ | |
54 | ||
8a96c052 | 55 | #include <linux/scatterlist.h> |
5a0e3ad6 | 56 | #include <linux/slab.h> |
f9c589e1 | 57 | #include <linux/dma-mapping.h> |
7f84eef0 | 58 | #include "xhci.h" |
3a7fa5be | 59 | #include "xhci-trace.h" |
7f84eef0 | 60 | |
d1dbfb94 MN |
61 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
62 | u32 field1, u32 field2, | |
63 | u32 field3, u32 field4, bool command_must_succeed); | |
64 | ||
7f84eef0 SS |
65 | /* |
66 | * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA | |
67 | * address of the TRB. | |
68 | */ | |
23e3be11 | 69 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, |
7f84eef0 SS |
70 | union xhci_trb *trb) |
71 | { | |
6071d836 | 72 | unsigned long segment_offset; |
7f84eef0 | 73 | |
6071d836 | 74 | if (!seg || !trb || trb < seg->trbs) |
7f84eef0 | 75 | return 0; |
6071d836 SS |
76 | /* offset in TRBs */ |
77 | segment_offset = trb - seg->trbs; | |
7895086a | 78 | if (segment_offset >= TRBS_PER_SEGMENT) |
7f84eef0 | 79 | return 0; |
6071d836 | 80 | return seg->dma + (segment_offset * sizeof(*trb)); |
7f84eef0 SS |
81 | } |
82 | ||
0ce57499 MN |
83 | static bool trb_is_noop(union xhci_trb *trb) |
84 | { | |
85 | return TRB_TYPE_NOOP_LE32(trb->generic.field[3]); | |
86 | } | |
87 | ||
2d98ef40 MN |
88 | static bool trb_is_link(union xhci_trb *trb) |
89 | { | |
90 | return TRB_TYPE_LINK_LE32(trb->link.control); | |
91 | } | |
92 | ||
bd5e67f5 MN |
93 | static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb) |
94 | { | |
95 | return trb == &seg->trbs[TRBS_PER_SEGMENT - 1]; | |
96 | } | |
97 | ||
98 | static bool last_trb_on_ring(struct xhci_ring *ring, | |
99 | struct xhci_segment *seg, union xhci_trb *trb) | |
100 | { | |
101 | return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg); | |
102 | } | |
103 | ||
d0c77d84 MN |
104 | static bool link_trb_toggles_cycle(union xhci_trb *trb) |
105 | { | |
106 | return le32_to_cpu(trb->link.control) & LINK_TOGGLE; | |
107 | } | |
108 | ||
2a72126d MN |
109 | static bool last_td_in_urb(struct xhci_td *td) |
110 | { | |
111 | struct urb_priv *urb_priv = td->urb->hcpriv; | |
112 | ||
9ef7fbbb | 113 | return urb_priv->num_tds_done == urb_priv->num_tds; |
2a72126d MN |
114 | } |
115 | ||
116 | static void inc_td_cnt(struct urb *urb) | |
117 | { | |
118 | struct urb_priv *urb_priv = urb->hcpriv; | |
119 | ||
9ef7fbbb | 120 | urb_priv->num_tds_done++; |
2a72126d MN |
121 | } |
122 | ||
ae1e3f07 MN |
123 | static void trb_to_noop(union xhci_trb *trb, u32 noop_type) |
124 | { | |
125 | if (trb_is_link(trb)) { | |
126 | /* unchain chained link TRBs */ | |
127 | trb->link.control &= cpu_to_le32(~TRB_CHAIN); | |
128 | } else { | |
129 | trb->generic.field[0] = 0; | |
130 | trb->generic.field[1] = 0; | |
131 | trb->generic.field[2] = 0; | |
132 | /* Preserve only the cycle bit of this TRB */ | |
133 | trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE); | |
134 | trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type)); | |
135 | } | |
136 | } | |
137 | ||
ae636747 SS |
138 | /* Updates trb to point to the next TRB in the ring, and updates seg if the next |
139 | * TRB is in a new segment. This does not skip over link TRBs, and it does not | |
140 | * effect the ring dequeue or enqueue pointers. | |
141 | */ | |
142 | static void next_trb(struct xhci_hcd *xhci, | |
143 | struct xhci_ring *ring, | |
144 | struct xhci_segment **seg, | |
145 | union xhci_trb **trb) | |
146 | { | |
2d98ef40 | 147 | if (trb_is_link(*trb)) { |
ae636747 SS |
148 | *seg = (*seg)->next; |
149 | *trb = ((*seg)->trbs); | |
150 | } else { | |
a1669b2c | 151 | (*trb)++; |
ae636747 SS |
152 | } |
153 | } | |
154 | ||
7f84eef0 SS |
155 | /* |
156 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
7f84eef0 | 157 | */ |
67d2ea9f | 158 | void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring) |
7f84eef0 | 159 | { |
c716e8a5 MN |
160 | unsigned int link_trb_count = 0; |
161 | ||
bd5e67f5 MN |
162 | /* event ring doesn't have link trbs, check for last trb */ |
163 | if (ring->type == TYPE_EVENT) { | |
164 | if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) { | |
50d0206f | 165 | ring->dequeue++; |
49d5b05e | 166 | goto out; |
7f84eef0 | 167 | } |
bd5e67f5 MN |
168 | if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue)) |
169 | ring->cycle_state ^= 1; | |
170 | ring->deq_seg = ring->deq_seg->next; | |
171 | ring->dequeue = ring->deq_seg->trbs; | |
49d5b05e | 172 | goto out; |
bd5e67f5 MN |
173 | } |
174 | ||
175 | /* All other rings have link trbs */ | |
176 | if (!trb_is_link(ring->dequeue)) { | |
c716e8a5 MN |
177 | if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) { |
178 | xhci_warn(xhci, "Missing link TRB at end of segment\n"); | |
179 | } else { | |
180 | ring->dequeue++; | |
181 | ring->num_trbs_free++; | |
182 | } | |
bd5e67f5 | 183 | } |
c716e8a5 | 184 | |
bd5e67f5 MN |
185 | while (trb_is_link(ring->dequeue)) { |
186 | ring->deq_seg = ring->deq_seg->next; | |
187 | ring->dequeue = ring->deq_seg->trbs; | |
b2d6edbb | 188 | |
c716e8a5 MN |
189 | if (link_trb_count++ > ring->num_segs) { |
190 | xhci_warn(xhci, "Ring is an endless link TRB loop\n"); | |
191 | break; | |
192 | } | |
193 | } | |
49d5b05e | 194 | out: |
b2d6edbb LB |
195 | trace_xhci_inc_deq(ring); |
196 | ||
bd5e67f5 | 197 | return; |
7f84eef0 SS |
198 | } |
199 | ||
200 | /* | |
201 | * See Cycle bit rules. SW is the consumer for the event ring only. | |
7f84eef0 SS |
202 | * |
203 | * If we've just enqueued a TRB that is in the middle of a TD (meaning the | |
204 | * chain bit is set), then set the chain bit in all the following link TRBs. | |
205 | * If we've enqueued the last TRB in a TD, make sure the following link TRBs | |
206 | * have their chain bit cleared (so that each Link TRB is a separate TD). | |
207 | * | |
208 | * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit | |
b0567b3f SS |
209 | * set, but other sections talk about dealing with the chain bit set. This was |
210 | * fixed in the 0.96 specification errata, but we have to assume that all 0.95 | |
211 | * xHCI hardware can't handle the chain bit being cleared on a link TRB. | |
6cc30d85 SS |
212 | * |
213 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
214 | * prepare_transfer()? | |
7f84eef0 | 215 | */ |
6cc30d85 | 216 | static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, |
3b72fca0 | 217 | bool more_trbs_coming) |
7f84eef0 SS |
218 | { |
219 | u32 chain; | |
220 | union xhci_trb *next; | |
c716e8a5 | 221 | unsigned int link_trb_count = 0; |
7f84eef0 | 222 | |
28ccd296 | 223 | chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN; |
b008df60 | 224 | /* If this is not event ring, there is one less usable TRB */ |
2d98ef40 | 225 | if (!trb_is_link(ring->enqueue)) |
b008df60 | 226 | ring->num_trbs_free--; |
c716e8a5 MN |
227 | |
228 | if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) { | |
229 | xhci_err(xhci, "Tried to move enqueue past ring segment\n"); | |
230 | return; | |
231 | } | |
232 | ||
7f84eef0 SS |
233 | next = ++(ring->enqueue); |
234 | ||
2251198b | 235 | /* Update the dequeue pointer further if that was a link TRB */ |
2d98ef40 | 236 | while (trb_is_link(next)) { |
6cc30d85 | 237 | |
2251198b MN |
238 | /* |
239 | * If the caller doesn't plan on enqueueing more TDs before | |
240 | * ringing the doorbell, then we don't want to give the link TRB | |
241 | * to the hardware just yet. We'll give the link TRB back in | |
242 | * prepare_ring() just before we enqueue the TD at the top of | |
243 | * the ring. | |
244 | */ | |
245 | if (!chain && !more_trbs_coming) | |
246 | break; | |
3b72fca0 | 247 | |
2251198b MN |
248 | /* If we're not dealing with 0.95 hardware or isoc rings on |
249 | * AMD 0.96 host, carry over the chain bit of the previous TRB | |
250 | * (which may mean the chain bit is cleared). | |
251 | */ | |
252 | if (!(ring->type == TYPE_ISOC && | |
253 | (xhci->quirks & XHCI_AMD_0x96_HOST)) && | |
254 | !xhci_link_trb_quirk(xhci)) { | |
255 | next->link.control &= cpu_to_le32(~TRB_CHAIN); | |
256 | next->link.control |= cpu_to_le32(chain); | |
7f84eef0 | 257 | } |
2251198b MN |
258 | /* Give this link TRB to the hardware */ |
259 | wmb(); | |
260 | next->link.control ^= cpu_to_le32(TRB_CYCLE); | |
261 | ||
262 | /* Toggle the cycle bit after the last ring segment. */ | |
d0c77d84 | 263 | if (link_trb_toggles_cycle(next)) |
2251198b MN |
264 | ring->cycle_state ^= 1; |
265 | ||
7f84eef0 SS |
266 | ring->enq_seg = ring->enq_seg->next; |
267 | ring->enqueue = ring->enq_seg->trbs; | |
268 | next = ring->enqueue; | |
c716e8a5 MN |
269 | |
270 | if (link_trb_count++ > ring->num_segs) { | |
271 | xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__); | |
272 | break; | |
273 | } | |
7f84eef0 | 274 | } |
b2d6edbb LB |
275 | |
276 | trace_xhci_inc_enq(ring); | |
7f84eef0 SS |
277 | } |
278 | ||
279 | /* | |
085deb16 AX |
280 | * Check to see if there's room to enqueue num_trbs on the ring and make sure |
281 | * enqueue pointer will not advance into dequeue segment. See rules above. | |
7f84eef0 | 282 | */ |
b008df60 | 283 | static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring, |
7f84eef0 SS |
284 | unsigned int num_trbs) |
285 | { | |
085deb16 | 286 | int num_trbs_in_deq_seg; |
b008df60 | 287 | |
085deb16 AX |
288 | if (ring->num_trbs_free < num_trbs) |
289 | return 0; | |
290 | ||
291 | if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) { | |
292 | num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs; | |
293 | if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg) | |
294 | return 0; | |
295 | } | |
296 | ||
297 | return 1; | |
7f84eef0 SS |
298 | } |
299 | ||
7f84eef0 | 300 | /* Ring the host controller doorbell after placing a command on the ring */ |
23e3be11 | 301 | void xhci_ring_cmd_db(struct xhci_hcd *xhci) |
7f84eef0 | 302 | { |
c181bc5b EF |
303 | if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) |
304 | return; | |
305 | ||
7f84eef0 | 306 | xhci_dbg(xhci, "// Ding dong!\n"); |
58b9d71a MN |
307 | |
308 | trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST); | |
309 | ||
204b7793 | 310 | writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]); |
7f84eef0 | 311 | /* Flush PCI posted writes */ |
b0ba9720 | 312 | readl(&xhci->dba->doorbell[0]); |
7f84eef0 SS |
313 | } |
314 | ||
cb4d5ce5 OH |
315 | static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay) |
316 | { | |
317 | return mod_delayed_work(system_wq, &xhci->cmd_timer, delay); | |
318 | } | |
319 | ||
1c111b6c OH |
320 | static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci) |
321 | { | |
322 | return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command, | |
323 | cmd_list); | |
324 | } | |
325 | ||
326 | /* | |
327 | * Turn all commands on command ring with status set to "aborted" to no-op trbs. | |
328 | * If there are other commands waiting then restart the ring and kick the timer. | |
329 | * This must be called with command ring stopped and xhci->lock held. | |
330 | */ | |
331 | static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci, | |
332 | struct xhci_command *cur_cmd) | |
333 | { | |
334 | struct xhci_command *i_cmd; | |
1c111b6c OH |
335 | |
336 | /* Turn all aborted commands in list to no-ops, then restart */ | |
337 | list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) { | |
338 | ||
0b7c105a | 339 | if (i_cmd->status != COMP_COMMAND_ABORTED) |
1c111b6c OH |
340 | continue; |
341 | ||
604d02a2 | 342 | i_cmd->status = COMP_COMMAND_RING_STOPPED; |
1c111b6c OH |
343 | |
344 | xhci_dbg(xhci, "Turn aborted command %p to no-op\n", | |
345 | i_cmd->command_trb); | |
5278204c MN |
346 | |
347 | trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP); | |
1c111b6c OH |
348 | |
349 | /* | |
350 | * caller waiting for completion is called when command | |
351 | * completion event is received for these no-op commands | |
352 | */ | |
353 | } | |
354 | ||
355 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; | |
356 | ||
357 | /* ring command ring doorbell to restart the command ring */ | |
358 | if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) && | |
359 | !(xhci->xhc_state & XHCI_STATE_DYING)) { | |
360 | xhci->current_cmd = cur_cmd; | |
361 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); | |
362 | xhci_ring_cmd_db(xhci); | |
363 | } | |
364 | } | |
365 | ||
366 | /* Must be called with xhci->lock held, releases and aquires lock back */ | |
367 | static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags) | |
b92cc66c | 368 | { |
50125632 MN |
369 | struct xhci_segment *new_seg = xhci->cmd_ring->deq_seg; |
370 | union xhci_trb *new_deq = xhci->cmd_ring->dequeue; | |
371 | u64 crcr; | |
b92cc66c EF |
372 | int ret; |
373 | ||
374 | xhci_dbg(xhci, "Abort command ring\n"); | |
375 | ||
1c111b6c | 376 | reinit_completion(&xhci->cmd_ring_stop_completion); |
3425aa03 | 377 | |
ff0e50d3 PK |
378 | /* |
379 | * The control bits like command stop, abort are located in lower | |
50125632 MN |
380 | * dword of the command ring control register. |
381 | * Some controllers require all 64 bits to be written to abort the ring. | |
382 | * Make sure the upper dword is valid, pointing to the next command, | |
383 | * avoiding corrupting the command ring pointer in case the command ring | |
384 | * is stopped by the time the upper dword is written. | |
ff0e50d3 | 385 | */ |
50125632 MN |
386 | next_trb(xhci, NULL, &new_seg, &new_deq); |
387 | if (trb_is_link(new_deq)) | |
388 | next_trb(xhci, NULL, &new_seg, &new_deq); | |
389 | ||
390 | crcr = xhci_trb_virt_to_dma(new_seg, new_deq); | |
391 | xhci_write_64(xhci, crcr | CMD_RING_ABORT, &xhci->op_regs->cmd_ring); | |
b92cc66c | 392 | |
d9f11ba9 MN |
393 | /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the |
394 | * completion of the Command Abort operation. If CRR is not negated in 5 | |
395 | * seconds then driver handles it as if host died (-ENODEV). | |
396 | * In the future we should distinguish between -ENODEV and -ETIMEDOUT | |
397 | * and try to recover a -ETIMEDOUT with a host controller reset. | |
b92cc66c | 398 | */ |
dc0b177c | 399 | ret = xhci_handshake(&xhci->op_regs->cmd_ring, |
b92cc66c EF |
400 | CMD_RING_RUNNING, 0, 5 * 1000 * 1000); |
401 | if (ret < 0) { | |
d9f11ba9 | 402 | xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret); |
1cc6d861 | 403 | xhci_halt(xhci); |
d9f11ba9 MN |
404 | xhci_hc_died(xhci); |
405 | return ret; | |
1c111b6c OH |
406 | } |
407 | /* | |
408 | * Writing the CMD_RING_ABORT bit should cause a cmd completion event, | |
409 | * however on some host hw the CMD_RING_RUNNING bit is correctly cleared | |
410 | * but the completion event in never sent. Wait 2 secs (arbitrary | |
411 | * number) to handle those cases after negation of CMD_RING_RUNNING. | |
412 | */ | |
413 | spin_unlock_irqrestore(&xhci->lock, flags); | |
414 | ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion, | |
415 | msecs_to_jiffies(2000)); | |
416 | spin_lock_irqsave(&xhci->lock, flags); | |
417 | if (!ret) { | |
418 | xhci_dbg(xhci, "No stop event for abort, ring start fail?\n"); | |
419 | xhci_cleanup_command_queue(xhci); | |
420 | } else { | |
421 | xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci)); | |
b92cc66c | 422 | } |
b92cc66c EF |
423 | return 0; |
424 | } | |
425 | ||
be88fe4f | 426 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, |
ae636747 | 427 | unsigned int slot_id, |
e9df17eb SS |
428 | unsigned int ep_index, |
429 | unsigned int stream_id) | |
ae636747 | 430 | { |
28ccd296 | 431 | __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id]; |
50d64676 MW |
432 | struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index]; |
433 | unsigned int ep_state = ep->ep_state; | |
ae636747 | 434 | |
ae636747 | 435 | /* Don't ring the doorbell for this endpoint if there are pending |
50d64676 | 436 | * cancellations because we don't want to interrupt processing. |
8df75f42 SS |
437 | * We don't want to restart any stream rings if there's a set dequeue |
438 | * pointer command pending because the device can choose to start any | |
439 | * stream once the endpoint is on the HW schedule. | |
ae636747 | 440 | */ |
9983a5fc | 441 | if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) || |
ef513be0 | 442 | (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT)) |
50d64676 | 443 | return; |
58b9d71a MN |
444 | |
445 | trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id)); | |
446 | ||
204b7793 | 447 | writel(DB_VALUE(ep_index, stream_id), db_addr); |
b05dadb2 MN |
448 | /* flush the write */ |
449 | readl(db_addr); | |
ae636747 SS |
450 | } |
451 | ||
e9df17eb SS |
452 | /* Ring the doorbell for any rings with pending URBs */ |
453 | static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci, | |
454 | unsigned int slot_id, | |
455 | unsigned int ep_index) | |
456 | { | |
457 | unsigned int stream_id; | |
458 | struct xhci_virt_ep *ep; | |
459 | ||
460 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
461 | ||
462 | /* A ring has pending URBs if its TD list is not empty */ | |
463 | if (!(ep->ep_state & EP_HAS_STREAMS)) { | |
d66eaf9f | 464 | if (ep->ring && !(list_empty(&ep->ring->td_list))) |
be88fe4f | 465 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0); |
e9df17eb SS |
466 | return; |
467 | } | |
468 | ||
469 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; | |
470 | stream_id++) { | |
471 | struct xhci_stream_info *stream_info = ep->stream_info; | |
472 | if (!list_empty(&stream_info->stream_rings[stream_id]->td_list)) | |
be88fe4f AX |
473 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, |
474 | stream_id); | |
e9df17eb SS |
475 | } |
476 | } | |
477 | ||
ef513be0 JL |
478 | void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci, |
479 | unsigned int slot_id, | |
480 | unsigned int ep_index) | |
481 | { | |
482 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
483 | } | |
484 | ||
b1adc42d MN |
485 | static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci, |
486 | unsigned int slot_id, | |
487 | unsigned int ep_index) | |
488 | { | |
489 | if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) { | |
490 | xhci_warn(xhci, "Invalid slot_id %u\n", slot_id); | |
491 | return NULL; | |
492 | } | |
493 | if (ep_index >= EP_CTX_PER_DEV) { | |
494 | xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index); | |
495 | return NULL; | |
496 | } | |
497 | if (!xhci->devs[slot_id]) { | |
498 | xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id); | |
499 | return NULL; | |
500 | } | |
501 | ||
502 | return &xhci->devs[slot_id]->eps[ep_index]; | |
503 | } | |
504 | ||
42f2890a MN |
505 | static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci, |
506 | struct xhci_virt_ep *ep, | |
507 | unsigned int stream_id) | |
508 | { | |
509 | /* common case, no streams */ | |
510 | if (!(ep->ep_state & EP_HAS_STREAMS)) | |
511 | return ep->ring; | |
512 | ||
513 | if (!ep->stream_info) | |
514 | return NULL; | |
515 | ||
516 | if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) { | |
517 | xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n", | |
518 | stream_id, ep->vdev->slot_id, ep->ep_index); | |
519 | return NULL; | |
520 | } | |
521 | ||
522 | return ep->stream_info->stream_rings[stream_id]; | |
523 | } | |
524 | ||
75b040ec AI |
525 | /* Get the right ring for the given slot_id, ep_index and stream_id. |
526 | * If the endpoint supports streams, boundary check the URB's stream ID. | |
527 | * If the endpoint doesn't support streams, return the singular endpoint ring. | |
528 | */ | |
529 | struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, | |
021bff91 SS |
530 | unsigned int slot_id, unsigned int ep_index, |
531 | unsigned int stream_id) | |
532 | { | |
533 | struct xhci_virt_ep *ep; | |
534 | ||
b1adc42d MN |
535 | ep = xhci_get_virt_ep(xhci, slot_id, ep_index); |
536 | if (!ep) | |
537 | return NULL; | |
538 | ||
42f2890a | 539 | return xhci_virt_ep_to_ring(xhci, ep, stream_id); |
021bff91 SS |
540 | } |
541 | ||
e6b20121 MN |
542 | |
543 | /* | |
544 | * Get the hw dequeue pointer xHC stopped on, either directly from the | |
545 | * endpoint context, or if streams are in use from the stream context. | |
546 | * The returned hw_dequeue contains the lowest four bits with cycle state | |
547 | * and possbile stream context type. | |
548 | */ | |
549 | static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev, | |
550 | unsigned int ep_index, unsigned int stream_id) | |
551 | { | |
552 | struct xhci_ep_ctx *ep_ctx; | |
553 | struct xhci_stream_ctx *st_ctx; | |
554 | struct xhci_virt_ep *ep; | |
555 | ||
556 | ep = &vdev->eps[ep_index]; | |
557 | ||
558 | if (ep->ep_state & EP_HAS_STREAMS) { | |
559 | st_ctx = &ep->stream_info->stream_ctx_array[stream_id]; | |
560 | return le64_to_cpu(st_ctx->stream_ring); | |
561 | } | |
562 | ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index); | |
563 | return le64_to_cpu(ep_ctx->deq); | |
564 | } | |
565 | ||
d1dbfb94 MN |
566 | static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci, |
567 | unsigned int slot_id, unsigned int ep_index, | |
568 | unsigned int stream_id, struct xhci_td *td) | |
569 | { | |
570 | struct xhci_virt_device *dev = xhci->devs[slot_id]; | |
571 | struct xhci_virt_ep *ep = &dev->eps[ep_index]; | |
572 | struct xhci_ring *ep_ring; | |
573 | struct xhci_command *cmd; | |
574 | struct xhci_segment *new_seg; | |
5255660b | 575 | struct xhci_segment *halted_seg = NULL; |
d1dbfb94 MN |
576 | union xhci_trb *new_deq; |
577 | int new_cycle; | |
5255660b JB |
578 | union xhci_trb *halted_trb; |
579 | int index = 0; | |
d1dbfb94 MN |
580 | dma_addr_t addr; |
581 | u64 hw_dequeue; | |
582 | bool cycle_found = false; | |
583 | bool td_last_trb_found = false; | |
584 | u32 trb_sct = 0; | |
585 | int ret; | |
586 | ||
587 | ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id, | |
588 | ep_index, stream_id); | |
589 | if (!ep_ring) { | |
590 | xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n", | |
591 | stream_id); | |
592 | return -ENODEV; | |
593 | } | |
594 | /* | |
595 | * A cancelled TD can complete with a stall if HW cached the trb. | |
596 | * In this case driver can't find td, but if the ring is empty we | |
597 | * can move the dequeue pointer to the current enqueue position. | |
598 | * We shouldn't hit this anymore as cached cancelled TRBs are given back | |
599 | * after clearing the cache, but be on the safe side and keep it anyway | |
600 | */ | |
601 | if (!td) { | |
602 | if (list_empty(&ep_ring->td_list)) { | |
603 | new_seg = ep_ring->enq_seg; | |
604 | new_deq = ep_ring->enqueue; | |
605 | new_cycle = ep_ring->cycle_state; | |
606 | xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue"); | |
607 | goto deq_found; | |
608 | } else { | |
609 | xhci_warn(xhci, "Can't find new dequeue state, missing td\n"); | |
610 | return -EINVAL; | |
611 | } | |
612 | } | |
613 | ||
614 | hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id); | |
615 | new_seg = ep_ring->deq_seg; | |
616 | new_deq = ep_ring->dequeue; | |
5255660b JB |
617 | |
618 | /* | |
619 | * Quirk: xHC write-back of the DCS field in the hardware dequeue | |
620 | * pointer is wrong - use the cycle state of the TRB pointed to by | |
621 | * the dequeue pointer. | |
622 | */ | |
623 | if (xhci->quirks & XHCI_EP_CTX_BROKEN_DCS && | |
624 | !(ep->ep_state & EP_HAS_STREAMS)) | |
625 | halted_seg = trb_in_td(xhci, td->start_seg, | |
626 | td->first_trb, td->last_trb, | |
627 | hw_dequeue & ~0xf, false); | |
628 | if (halted_seg) { | |
629 | index = ((dma_addr_t)(hw_dequeue & ~0xf) - halted_seg->dma) / | |
630 | sizeof(*halted_trb); | |
631 | halted_trb = &halted_seg->trbs[index]; | |
632 | new_cycle = halted_trb->generic.field[3] & 0x1; | |
633 | xhci_dbg(xhci, "Endpoint DCS = %d TRB index = %d cycle = %d\n", | |
634 | (u8)(hw_dequeue & 0x1), index, new_cycle); | |
635 | } else { | |
636 | new_cycle = hw_dequeue & 0x1; | |
637 | } | |
d1dbfb94 MN |
638 | |
639 | /* | |
640 | * We want to find the pointer, segment and cycle state of the new trb | |
641 | * (the one after current TD's last_trb). We know the cycle state at | |
642 | * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are | |
643 | * found. | |
644 | */ | |
645 | do { | |
646 | if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq) | |
647 | == (dma_addr_t)(hw_dequeue & ~0xf)) { | |
648 | cycle_found = true; | |
649 | if (td_last_trb_found) | |
650 | break; | |
651 | } | |
652 | if (new_deq == td->last_trb) | |
653 | td_last_trb_found = true; | |
654 | ||
655 | if (cycle_found && trb_is_link(new_deq) && | |
656 | link_trb_toggles_cycle(new_deq)) | |
657 | new_cycle ^= 0x1; | |
658 | ||
659 | next_trb(xhci, ep_ring, &new_seg, &new_deq); | |
660 | ||
661 | /* Search wrapped around, bail out */ | |
662 | if (new_deq == ep->ring->dequeue) { | |
663 | xhci_err(xhci, "Error: Failed finding new dequeue state\n"); | |
664 | return -EINVAL; | |
665 | } | |
666 | ||
667 | } while (!cycle_found || !td_last_trb_found); | |
668 | ||
669 | deq_found: | |
670 | ||
671 | /* Don't update the ring cycle state for the producer (us). */ | |
672 | addr = xhci_trb_virt_to_dma(new_seg, new_deq); | |
673 | if (addr == 0) { | |
674 | xhci_warn(xhci, "Can't find dma of new dequeue ptr\n"); | |
675 | xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq); | |
676 | return -EINVAL; | |
677 | } | |
678 | ||
679 | if ((ep->ep_state & SET_DEQ_PENDING)) { | |
680 | xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n", | |
681 | &addr); | |
682 | return -EBUSY; | |
683 | } | |
684 | ||
685 | /* This function gets called from contexts where it cannot sleep */ | |
686 | cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC); | |
687 | if (!cmd) { | |
688 | xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr); | |
689 | return -ENOMEM; | |
690 | } | |
691 | ||
692 | if (stream_id) | |
693 | trb_sct = SCT_FOR_TRB(SCT_PRI_TR); | |
694 | ret = queue_command(xhci, cmd, | |
695 | lower_32_bits(addr) | trb_sct | new_cycle, | |
696 | upper_32_bits(addr), | |
697 | STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) | | |
698 | EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false); | |
699 | if (ret < 0) { | |
700 | xhci_free_command(xhci, cmd); | |
701 | return ret; | |
702 | } | |
703 | ep->queued_deq_seg = new_seg; | |
704 | ep->queued_deq_ptr = new_deq; | |
705 | ||
706 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
707 | "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle); | |
708 | ||
709 | /* Stop the TD queueing code from ringing the doorbell until | |
710 | * this command completes. The HC won't set the dequeue pointer | |
711 | * if the ring is running, and ringing the doorbell starts the | |
712 | * ring running. | |
713 | */ | |
714 | ep->ep_state |= SET_DEQ_PENDING; | |
715 | xhci_ring_cmd_db(xhci); | |
716 | return 0; | |
717 | } | |
718 | ||
522989a2 SS |
719 | /* flip_cycle means flip the cycle bit of all but the first and last TRB. |
720 | * (The last TRB actually points to the ring enqueue pointer, which is not part | |
721 | * of this TD.) This is used to remove partially enqueued isoc TDs from a ring. | |
722 | */ | |
23e3be11 | 723 | static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, |
0d58a1a0 | 724 | struct xhci_td *td, bool flip_cycle) |
ae636747 | 725 | { |
0d58a1a0 MN |
726 | struct xhci_segment *seg = td->start_seg; |
727 | union xhci_trb *trb = td->first_trb; | |
728 | ||
729 | while (1) { | |
ae1e3f07 MN |
730 | trb_to_noop(trb, TRB_TR_NOOP); |
731 | ||
0d58a1a0 MN |
732 | /* flip cycle if asked to */ |
733 | if (flip_cycle && trb != td->first_trb && trb != td->last_trb) | |
734 | trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE); | |
735 | ||
736 | if (trb == td->last_trb) | |
ae636747 | 737 | break; |
0d58a1a0 MN |
738 | |
739 | next_trb(xhci, ep_ring, &seg, &trb); | |
ae636747 SS |
740 | } |
741 | } | |
742 | ||
575688e1 | 743 | static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci, |
6f5165cf SS |
744 | struct xhci_virt_ep *ep) |
745 | { | |
9983a5fc | 746 | ep->ep_state &= ~EP_STOP_CMD_PENDING; |
f9926596 MN |
747 | /* Can't del_timer_sync in interrupt */ |
748 | del_timer(&ep->stop_cmd_timer); | |
6f5165cf SS |
749 | } |
750 | ||
2a72126d MN |
751 | /* |
752 | * Must be called with xhci->lock held in interrupt context, | |
753 | * releases and re-acquires xhci->lock | |
754 | */ | |
6f5165cf | 755 | static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, |
2a72126d | 756 | struct xhci_td *cur_td, int status) |
6f5165cf | 757 | { |
2a72126d MN |
758 | struct urb *urb = cur_td->urb; |
759 | struct urb_priv *urb_priv = urb->hcpriv; | |
760 | struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus); | |
761 | ||
762 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { | |
763 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--; | |
764 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { | |
765 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
766 | usb_amd_quirk_pll_enable(); | |
c41136b0 | 767 | } |
8e51adcc | 768 | } |
446b3141 | 769 | xhci_urb_free_priv(urb_priv); |
2a72126d | 770 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
5abdc2e6 | 771 | trace_xhci_urb_giveback(urb); |
7bc5d5af | 772 | usb_hcd_giveback_urb(hcd, urb, status); |
446b3141 MN |
773 | } |
774 | ||
2d6d5769 WY |
775 | static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, |
776 | struct xhci_ring *ring, struct xhci_td *td) | |
f9c589e1 MN |
777 | { |
778 | struct device *dev = xhci_to_hcd(xhci)->self.controller; | |
779 | struct xhci_segment *seg = td->bounce_seg; | |
780 | struct urb *urb = td->urb; | |
597c56e3 | 781 | size_t len; |
f9c589e1 | 782 | |
f45e2a02 | 783 | if (!ring || !seg || !urb) |
f9c589e1 MN |
784 | return; |
785 | ||
786 | if (usb_urb_dir_out(urb)) { | |
787 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, | |
788 | DMA_TO_DEVICE); | |
789 | return; | |
790 | } | |
791 | ||
f9c589e1 MN |
792 | dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len, |
793 | DMA_FROM_DEVICE); | |
597c56e3 | 794 | /* for in tranfers we need to copy the data from bounce to sg */ |
d4a61063 MN |
795 | if (urb->num_sgs) { |
796 | len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf, | |
797 | seg->bounce_len, seg->bounce_offs); | |
798 | if (len != seg->bounce_len) | |
799 | xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n", | |
800 | len, seg->bounce_len); | |
801 | } else { | |
802 | memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf, | |
803 | seg->bounce_len); | |
804 | } | |
f9c589e1 MN |
805 | seg->bounce_len = 0; |
806 | seg->bounce_offs = 0; | |
807 | } | |
808 | ||
69eaf9e7 | 809 | static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td, |
a6ccd1fd | 810 | struct xhci_ring *ep_ring, int status) |
69eaf9e7 MN |
811 | { |
812 | struct urb *urb = NULL; | |
813 | ||
814 | /* Clean up the endpoint's TD list */ | |
815 | urb = td->urb; | |
816 | ||
817 | /* if a bounce buffer was used to align this td then unmap it */ | |
818 | xhci_unmap_td_bounce_buffer(xhci, ep_ring, td); | |
819 | ||
820 | /* Do one last check of the actual transfer length. | |
821 | * If the host controller said we transferred more data than the buffer | |
822 | * length, urb->actual_length will be a very big number (since it's | |
823 | * unsigned). Play it safe and say we didn't transfer anything. | |
824 | */ | |
825 | if (urb->actual_length > urb->transfer_buffer_length) { | |
826 | xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n", | |
827 | urb->transfer_buffer_length, urb->actual_length); | |
828 | urb->actual_length = 0; | |
a6ccd1fd | 829 | status = 0; |
69eaf9e7 | 830 | } |
e1a29839 MN |
831 | /* TD might be removed from td_list if we are giving back a cancelled URB */ |
832 | if (!list_empty(&td->td_list)) | |
833 | list_del_init(&td->td_list); | |
834 | /* Giving back a cancelled URB, or if a slated TD completed anyway */ | |
69eaf9e7 MN |
835 | if (!list_empty(&td->cancelled_td_list)) |
836 | list_del_init(&td->cancelled_td_list); | |
837 | ||
838 | inc_td_cnt(urb); | |
839 | /* Giveback the urb when all the tds are completed */ | |
840 | if (last_td_in_urb(td)) { | |
841 | if ((urb->actual_length != urb->transfer_buffer_length && | |
842 | (urb->transfer_flags & URB_SHORT_NOT_OK)) || | |
a6ccd1fd | 843 | (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc))) |
69eaf9e7 MN |
844 | xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n", |
845 | urb, urb->actual_length, | |
a6ccd1fd | 846 | urb->transfer_buffer_length, status); |
69eaf9e7 MN |
847 | |
848 | /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */ | |
849 | if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) | |
a6ccd1fd MN |
850 | status = 0; |
851 | xhci_giveback_urb_in_irq(xhci, td, status); | |
69eaf9e7 MN |
852 | } |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
674f8438 MN |
857 | |
858 | /* Complete the cancelled URBs we unlinked from td_list. */ | |
859 | static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep) | |
860 | { | |
861 | struct xhci_ring *ring; | |
862 | struct xhci_td *td, *tmp_td; | |
863 | ||
864 | list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, | |
865 | cancelled_td_list) { | |
866 | ||
674f8438 MN |
867 | ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb); |
868 | ||
0d9b9f53 MN |
869 | if (td->cancel_status == TD_CLEARED) { |
870 | xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n", | |
871 | __func__, td->urb); | |
a80c203c | 872 | xhci_td_cleanup(ep->xhci, td, ring, td->status); |
0d9b9f53 MN |
873 | } else { |
874 | xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n", | |
875 | __func__, td->urb, td->cancel_status); | |
876 | } | |
674f8438 MN |
877 | if (ep->xhci->xhc_state & XHCI_STATE_DYING) |
878 | return; | |
879 | } | |
880 | } | |
881 | ||
d8ac9500 MN |
882 | static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id, |
883 | unsigned int ep_index, enum xhci_ep_reset_type reset_type) | |
884 | { | |
885 | struct xhci_command *command; | |
886 | int ret = 0; | |
887 | ||
888 | command = xhci_alloc_command(xhci, false, GFP_ATOMIC); | |
889 | if (!command) { | |
890 | ret = -ENOMEM; | |
891 | goto done; | |
892 | } | |
893 | ||
0d9b9f53 MN |
894 | xhci_dbg(xhci, "%s-reset ep %u, slot %u\n", |
895 | (reset_type == EP_HARD_RESET) ? "Hard" : "Soft", | |
896 | ep_index, slot_id); | |
897 | ||
d8ac9500 MN |
898 | ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type); |
899 | done: | |
900 | if (ret) | |
901 | xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n", | |
902 | slot_id, ep_index, ret); | |
903 | return ret; | |
904 | } | |
905 | ||
9b6a126a | 906 | static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci, |
7c6c334e MN |
907 | struct xhci_virt_ep *ep, unsigned int stream_id, |
908 | struct xhci_td *td, | |
909 | enum xhci_ep_reset_type reset_type) | |
910 | { | |
911 | unsigned int slot_id = ep->vdev->slot_id; | |
912 | int err; | |
913 | ||
914 | /* | |
915 | * Avoid resetting endpoint if link is inactive. Can cause host hang. | |
916 | * Device will be reset soon to recover the link so don't do anything | |
917 | */ | |
918 | if (ep->vdev->flags & VDEV_PORT_ERROR) | |
9b6a126a | 919 | return -ENODEV; |
7c6c334e | 920 | |
674f8438 MN |
921 | /* add td to cancelled list and let reset ep handler take care of it */ |
922 | if (reset_type == EP_HARD_RESET) { | |
923 | ep->ep_state |= EP_HARD_CLEAR_TOGGLE; | |
924 | if (td && list_empty(&td->cancelled_td_list)) { | |
925 | list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); | |
926 | td->cancel_status = TD_HALTED; | |
927 | } | |
928 | } | |
929 | ||
51ee4a84 | 930 | if (ep->ep_state & EP_HALTED) { |
0d9b9f53 MN |
931 | xhci_dbg(xhci, "Reset ep command for ep_index %d already pending\n", |
932 | ep->ep_index); | |
9b6a126a | 933 | return 0; |
51ee4a84 MN |
934 | } |
935 | ||
7c6c334e MN |
936 | err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type); |
937 | if (err) | |
9b6a126a | 938 | return err; |
7c6c334e | 939 | |
51ee4a84 MN |
940 | ep->ep_state |= EP_HALTED; |
941 | ||
7c6c334e | 942 | xhci_ring_cmd_db(xhci); |
9b6a126a MN |
943 | |
944 | return 0; | |
7c6c334e MN |
945 | } |
946 | ||
4db35692 MN |
947 | /* |
948 | * Fix up the ep ring first, so HW stops executing cancelled TDs. | |
949 | * We have the xHCI lock, so nothing can modify this list until we drop it. | |
950 | * We're also in the event handler, so we can't get re-interrupted if another | |
951 | * Stop Endpoint command completes. | |
674f8438 MN |
952 | * |
953 | * only call this when ring is not in a running state | |
4db35692 MN |
954 | */ |
955 | ||
674f8438 | 956 | static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep) |
4db35692 MN |
957 | { |
958 | struct xhci_hcd *xhci; | |
959 | struct xhci_td *td = NULL; | |
960 | struct xhci_td *tmp_td = NULL; | |
674f8438 | 961 | struct xhci_td *cached_td = NULL; |
4db35692 MN |
962 | struct xhci_ring *ring; |
963 | u64 hw_deq; | |
674f8438 | 964 | unsigned int slot_id = ep->vdev->slot_id; |
d1dbfb94 | 965 | int err; |
4db35692 MN |
966 | |
967 | xhci = ep->xhci; | |
968 | ||
969 | list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) { | |
970 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
0d9b9f53 MN |
971 | "Removing canceled TD starting at 0x%llx (dma) in stream %u URB %p", |
972 | (unsigned long long)xhci_trb_virt_to_dma( | |
973 | td->start_seg, td->first_trb), | |
974 | td->urb->stream_id, td->urb); | |
4db35692 MN |
975 | list_del_init(&td->td_list); |
976 | ring = xhci_urb_to_transfer_ring(xhci, td->urb); | |
977 | if (!ring) { | |
978 | xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n", | |
979 | td->urb, td->urb->stream_id); | |
980 | continue; | |
981 | } | |
982 | /* | |
a7f2e927 | 983 | * If a ring stopped on the TD we need to cancel then we have to |
4db35692 | 984 | * move the xHC endpoint ring dequeue pointer past this TD. |
a7f2e927 MN |
985 | * Rings halted due to STALL may show hw_deq is past the stalled |
986 | * TD, but still require a set TR Deq command to flush xHC cache. | |
4db35692 MN |
987 | */ |
988 | hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index, | |
989 | td->urb->stream_id); | |
990 | hw_deq &= ~0xf; | |
991 | ||
94f33914 MN |
992 | if (td->cancel_status == TD_HALTED || |
993 | trb_in_td(xhci, td->start_seg, td->first_trb, td->last_trb, hw_deq, false)) { | |
674f8438 MN |
994 | switch (td->cancel_status) { |
995 | case TD_CLEARED: /* TD is already no-op */ | |
996 | case TD_CLEARING_CACHE: /* set TR deq command already queued */ | |
997 | break; | |
998 | case TD_DIRTY: /* TD is cached, clear it */ | |
999 | case TD_HALTED: | |
94f33914 MN |
1000 | td->cancel_status = TD_CLEARING_CACHE; |
1001 | if (cached_td) | |
1002 | /* FIXME stream case, several stopped rings */ | |
1003 | xhci_dbg(xhci, | |
1004 | "Move dq past stream %u URB %p instead of stream %u URB %p\n", | |
1005 | td->urb->stream_id, td->urb, | |
1006 | cached_td->urb->stream_id, cached_td->urb); | |
674f8438 MN |
1007 | cached_td = td; |
1008 | break; | |
1009 | } | |
4db35692 MN |
1010 | } else { |
1011 | td_to_noop(xhci, ring, td, false); | |
674f8438 | 1012 | td->cancel_status = TD_CLEARED; |
4db35692 | 1013 | } |
674f8438 | 1014 | } |
d1dbfb94 | 1015 | |
94f33914 MN |
1016 | /* If there's no need to move the dequeue pointer then we're done */ |
1017 | if (!cached_td) | |
1018 | return 0; | |
1019 | ||
1020 | err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index, | |
1021 | cached_td->urb->stream_id, | |
1022 | cached_td); | |
1023 | if (err) { | |
1024 | /* Failed to move past cached td, just set cached TDs to no-op */ | |
1025 | list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) { | |
1026 | if (td->cancel_status != TD_CLEARING_CACHE) | |
1027 | continue; | |
1028 | xhci_dbg(xhci, "Failed to clear cancelled cached URB %p, mark clear anyway\n", | |
1029 | td->urb); | |
1030 | td_to_noop(xhci, ring, td, false); | |
1031 | td->cancel_status = TD_CLEARED; | |
d1dbfb94 | 1032 | } |
4db35692 MN |
1033 | } |
1034 | return 0; | |
1035 | } | |
1036 | ||
9ebf3000 MN |
1037 | /* |
1038 | * Returns the TD the endpoint ring halted on. | |
1039 | * Only call for non-running rings without streams. | |
1040 | */ | |
1041 | static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep) | |
1042 | { | |
1043 | struct xhci_td *td; | |
1044 | u64 hw_deq; | |
1045 | ||
1046 | if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */ | |
1047 | hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0); | |
1048 | hw_deq &= ~0xf; | |
1049 | td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list); | |
1050 | if (trb_in_td(ep->xhci, td->start_seg, td->first_trb, | |
1051 | td->last_trb, hw_deq, false)) | |
1052 | return td; | |
1053 | } | |
1054 | return NULL; | |
1055 | } | |
1056 | ||
ae636747 SS |
1057 | /* |
1058 | * When we get a command completion for a Stop Endpoint Command, we need to | |
1059 | * unlink any cancelled TDs from the ring. There are two ways to do that: | |
1060 | * | |
1061 | * 1. If the HW was in the middle of processing the TD that needs to be | |
1062 | * cancelled, then we must move the ring's dequeue pointer past the last TRB | |
1063 | * in the TD with a Set Dequeue Pointer Command. | |
1064 | * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain | |
1065 | * bit cleared) so that the HW will skip over them. | |
1066 | */ | |
b8200c94 | 1067 | static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id, |
9ebf3000 | 1068 | union xhci_trb *trb, u32 comp_code) |
ae636747 | 1069 | { |
ae636747 | 1070 | unsigned int ep_index; |
63a0d9ab | 1071 | struct xhci_virt_ep *ep; |
19a7d0d6 | 1072 | struct xhci_ep_ctx *ep_ctx; |
9ebf3000 MN |
1073 | struct xhci_td *td = NULL; |
1074 | enum xhci_ep_reset_type reset_type; | |
1174d449 | 1075 | struct xhci_command *command; |
9b6a126a | 1076 | int err; |
ae636747 | 1077 | |
bc752bde | 1078 | if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) { |
9ea1833e | 1079 | if (!xhci->devs[slot_id]) |
674f8438 MN |
1080 | xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n", |
1081 | slot_id); | |
be88fe4f AX |
1082 | return; |
1083 | } | |
1084 | ||
28ccd296 | 1085 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
b1adc42d MN |
1086 | ep = xhci_get_virt_ep(xhci, slot_id, ep_index); |
1087 | if (!ep) | |
1088 | return; | |
1089 | ||
674f8438 | 1090 | ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); |
ae636747 | 1091 | |
674f8438 | 1092 | trace_xhci_handle_cmd_stop_ep(ep_ctx); |
04861f83 | 1093 | |
9ebf3000 MN |
1094 | if (comp_code == COMP_CONTEXT_STATE_ERROR) { |
1095 | /* | |
1096 | * If stop endpoint command raced with a halting endpoint we need to | |
1097 | * reset the host side endpoint first. | |
1098 | * If the TD we halted on isn't cancelled the TD should be given back | |
1099 | * with a proper error code, and the ring dequeue moved past the TD. | |
1100 | * If streams case we can't find hw_deq, or the TD we halted on so do a | |
1101 | * soft reset. | |
1102 | * | |
1103 | * Proper error code is unknown here, it would be -EPIPE if device side | |
1104 | * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error) | |
1105 | * We use -EPROTO, if device is stalled it should return a stall error on | |
1106 | * next transfer, which then will return -EPIPE, and device side stall is | |
1107 | * noted and cleared by class driver. | |
1108 | */ | |
1109 | switch (GET_EP_CTX_STATE(ep_ctx)) { | |
1110 | case EP_STATE_HALTED: | |
1111 | xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n"); | |
1112 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1113 | reset_type = EP_SOFT_RESET; | |
1114 | } else { | |
1115 | reset_type = EP_HARD_RESET; | |
1116 | td = find_halted_td(ep); | |
1117 | if (td) | |
1118 | td->status = -EPROTO; | |
1119 | } | |
1120 | /* reset ep, reset handler cleans up cancelled tds */ | |
9b6a126a MN |
1121 | err = xhci_handle_halted_endpoint(xhci, ep, 0, td, |
1122 | reset_type); | |
1123 | if (err) | |
1124 | break; | |
9ebf3000 | 1125 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
1174d449 MN |
1126 | return; |
1127 | case EP_STATE_RUNNING: | |
1128 | /* Race, HW handled stop ep cmd before ep was running */ | |
0d9b9f53 MN |
1129 | xhci_dbg(xhci, "Stop ep completion ctx error, ep is running\n"); |
1130 | ||
1174d449 MN |
1131 | command = xhci_alloc_command(xhci, false, GFP_ATOMIC); |
1132 | if (!command) | |
1133 | xhci_stop_watchdog_timer_in_irq(xhci, ep); | |
1134 | ||
1135 | mod_timer(&ep->stop_cmd_timer, | |
1136 | jiffies + XHCI_STOP_EP_CMD_TIMEOUT * HZ); | |
1137 | xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0); | |
1138 | xhci_ring_cmd_db(xhci); | |
1139 | ||
9ebf3000 MN |
1140 | return; |
1141 | default: | |
1142 | break; | |
1143 | } | |
1144 | } | |
674f8438 MN |
1145 | /* will queue a set TR deq if stopped on a cancelled, uncleared TD */ |
1146 | xhci_invalidate_cancelled_tds(ep); | |
6f5165cf | 1147 | xhci_stop_watchdog_timer_in_irq(xhci, ep); |
ae636747 | 1148 | |
674f8438 MN |
1149 | /* Otherwise ring the doorbell(s) to restart queued transfers */ |
1150 | xhci_giveback_invalidated_tds(ep); | |
1151 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1152 | } |
1153 | ||
50e8725e SS |
1154 | static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
1155 | { | |
1156 | struct xhci_td *cur_td; | |
a54cfae3 | 1157 | struct xhci_td *tmp; |
50e8725e | 1158 | |
a54cfae3 | 1159 | list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) { |
50e8725e | 1160 | list_del_init(&cur_td->td_list); |
a54cfae3 | 1161 | |
50e8725e SS |
1162 | if (!list_empty(&cur_td->cancelled_td_list)) |
1163 | list_del_init(&cur_td->cancelled_td_list); | |
f9c589e1 | 1164 | |
a60f2f2f | 1165 | xhci_unmap_td_bounce_buffer(xhci, ring, cur_td); |
2a72126d MN |
1166 | |
1167 | inc_td_cnt(cur_td->urb); | |
1168 | if (last_td_in_urb(cur_td)) | |
1169 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
1170 | } |
1171 | } | |
1172 | ||
1173 | static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci, | |
1174 | int slot_id, int ep_index) | |
1175 | { | |
1176 | struct xhci_td *cur_td; | |
a54cfae3 | 1177 | struct xhci_td *tmp; |
50e8725e SS |
1178 | struct xhci_virt_ep *ep; |
1179 | struct xhci_ring *ring; | |
1180 | ||
1181 | ep = &xhci->devs[slot_id]->eps[ep_index]; | |
21d0e51b SS |
1182 | if ((ep->ep_state & EP_HAS_STREAMS) || |
1183 | (ep->ep_state & EP_GETTING_NO_STREAMS)) { | |
1184 | int stream_id; | |
1185 | ||
4b895868 | 1186 | for (stream_id = 1; stream_id < ep->stream_info->num_streams; |
21d0e51b | 1187 | stream_id++) { |
4b895868 MN |
1188 | ring = ep->stream_info->stream_rings[stream_id]; |
1189 | if (!ring) | |
1190 | continue; | |
1191 | ||
21d0e51b SS |
1192 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1193 | "Killing URBs for slot ID %u, ep index %u, stream %u", | |
4b895868 MN |
1194 | slot_id, ep_index, stream_id); |
1195 | xhci_kill_ring_urbs(xhci, ring); | |
21d0e51b SS |
1196 | } |
1197 | } else { | |
1198 | ring = ep->ring; | |
1199 | if (!ring) | |
1200 | return; | |
1201 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, | |
1202 | "Killing URBs for slot ID %u, ep index %u", | |
1203 | slot_id, ep_index); | |
1204 | xhci_kill_ring_urbs(xhci, ring); | |
1205 | } | |
2a72126d | 1206 | |
a54cfae3 FB |
1207 | list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list, |
1208 | cancelled_td_list) { | |
1209 | list_del_init(&cur_td->cancelled_td_list); | |
2a72126d | 1210 | inc_td_cnt(cur_td->urb); |
a54cfae3 | 1211 | |
2a72126d MN |
1212 | if (last_td_in_urb(cur_td)) |
1213 | xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN); | |
50e8725e SS |
1214 | } |
1215 | } | |
1216 | ||
d9f11ba9 MN |
1217 | /* |
1218 | * host controller died, register read returns 0xffffffff | |
1219 | * Complete pending commands, mark them ABORTED. | |
1220 | * URBs need to be given back as usb core might be waiting with device locks | |
1221 | * held for the URBs to finish during device disconnect, blocking host remove. | |
1222 | * | |
1223 | * Call with xhci->lock held. | |
1224 | * lock is relased and re-acquired while giving back urb. | |
1225 | */ | |
1226 | void xhci_hc_died(struct xhci_hcd *xhci) | |
1227 | { | |
1228 | int i, j; | |
1229 | ||
1230 | if (xhci->xhc_state & XHCI_STATE_DYING) | |
1231 | return; | |
1232 | ||
1233 | xhci_err(xhci, "xHCI host controller not responding, assume dead\n"); | |
1234 | xhci->xhc_state |= XHCI_STATE_DYING; | |
1235 | ||
1236 | xhci_cleanup_command_queue(xhci); | |
1237 | ||
1238 | /* return any pending urbs, remove may be waiting for them */ | |
1239 | for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) { | |
1240 | if (!xhci->devs[i]) | |
1241 | continue; | |
1242 | for (j = 0; j < 31; j++) | |
1243 | xhci_kill_endpoint_urbs(xhci, i, j); | |
1244 | } | |
1245 | ||
1246 | /* inform usb core hc died if PCI remove isn't already handling it */ | |
1247 | if (!(xhci->xhc_state & XHCI_STATE_REMOVING)) | |
1248 | usb_hc_died(xhci_to_hcd(xhci)); | |
1249 | } | |
1250 | ||
6f5165cf SS |
1251 | /* Watchdog timer function for when a stop endpoint command fails to complete. |
1252 | * In this case, we assume the host controller is broken or dying or dead. The | |
1253 | * host may still be completing some other events, so we have to be careful to | |
1254 | * let the event ring handler and the URB dequeueing/enqueueing functions know | |
1255 | * through xhci->state. | |
1256 | * | |
1257 | * The timer may also fire if the host takes a very long time to respond to the | |
1258 | * command, and the stop endpoint command completion handler cannot delete the | |
1259 | * timer before the timer function is called. Another endpoint cancellation may | |
1260 | * sneak in before the timer function can grab the lock, and that may queue | |
1261 | * another stop endpoint command and add the timer back. So we cannot use a | |
1262 | * simple flag to say whether there is a pending stop endpoint command for a | |
1263 | * particular endpoint. | |
1264 | * | |
f9926596 MN |
1265 | * Instead we use a combination of that flag and checking if a new timer is |
1266 | * pending. | |
6f5165cf | 1267 | */ |
66a45503 | 1268 | void xhci_stop_endpoint_command_watchdog(struct timer_list *t) |
6f5165cf | 1269 | { |
66a45503 KC |
1270 | struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer); |
1271 | struct xhci_hcd *xhci = ep->xhci; | |
f43d6231 | 1272 | unsigned long flags; |
9c1aa36e | 1273 | u32 usbsts; |
4843b4b5 | 1274 | char str[XHCI_MSG_MAX]; |
6f5165cf | 1275 | |
f43d6231 | 1276 | spin_lock_irqsave(&xhci->lock, flags); |
6f5165cf | 1277 | |
f9926596 MN |
1278 | /* bail out if cmd completed but raced with stop ep watchdog timer.*/ |
1279 | if (!(ep->ep_state & EP_STOP_CMD_PENDING) || | |
1280 | timer_pending(&ep->stop_cmd_timer)) { | |
f43d6231 | 1281 | spin_unlock_irqrestore(&xhci->lock, flags); |
f9926596 | 1282 | xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit"); |
6f5165cf SS |
1283 | return; |
1284 | } | |
9c1aa36e | 1285 | usbsts = readl(&xhci->op_regs->status); |
6f5165cf SS |
1286 | |
1287 | xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n"); | |
4843b4b5 | 1288 | xhci_warn(xhci, "USBSTS:%s\n", xhci_decode_usbsts(str, usbsts)); |
9c1aa36e | 1289 | |
f9926596 MN |
1290 | ep->ep_state &= ~EP_STOP_CMD_PENDING; |
1291 | ||
d9f11ba9 | 1292 | xhci_halt(xhci); |
6f5165cf | 1293 | |
d9f11ba9 MN |
1294 | /* |
1295 | * handle a stop endpoint cmd timeout as if host died (-ENODEV). | |
1296 | * In the future we could distinguish between -ENODEV and -ETIMEDOUT | |
1297 | * and try to recover a -ETIMEDOUT with a host controller reset | |
1298 | */ | |
1299 | xhci_hc_died(xhci); | |
6f5165cf | 1300 | |
f43d6231 | 1301 | spin_unlock_irqrestore(&xhci->lock, flags); |
aa50b290 XR |
1302 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1303 | "xHCI host controller is dead."); | |
6f5165cf SS |
1304 | } |
1305 | ||
b008df60 AX |
1306 | static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci, |
1307 | struct xhci_virt_device *dev, | |
1308 | struct xhci_ring *ep_ring, | |
1309 | unsigned int ep_index) | |
1310 | { | |
1311 | union xhci_trb *dequeue_temp; | |
1312 | int num_trbs_free_temp; | |
1313 | bool revert = false; | |
1314 | ||
1315 | num_trbs_free_temp = ep_ring->num_trbs_free; | |
1316 | dequeue_temp = ep_ring->dequeue; | |
1317 | ||
0d9f78a9 SS |
1318 | /* If we get two back-to-back stalls, and the first stalled transfer |
1319 | * ends just before a link TRB, the dequeue pointer will be left on | |
1320 | * the link TRB by the code in the while loop. So we have to update | |
1321 | * the dequeue pointer one segment further, or we'll jump off | |
1322 | * the segment into la-la-land. | |
1323 | */ | |
2d98ef40 | 1324 | if (trb_is_link(ep_ring->dequeue)) { |
0d9f78a9 SS |
1325 | ep_ring->deq_seg = ep_ring->deq_seg->next; |
1326 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
1327 | } | |
1328 | ||
b008df60 AX |
1329 | while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) { |
1330 | /* We have more usable TRBs */ | |
1331 | ep_ring->num_trbs_free++; | |
1332 | ep_ring->dequeue++; | |
2d98ef40 | 1333 | if (trb_is_link(ep_ring->dequeue)) { |
b008df60 AX |
1334 | if (ep_ring->dequeue == |
1335 | dev->eps[ep_index].queued_deq_ptr) | |
1336 | break; | |
1337 | ep_ring->deq_seg = ep_ring->deq_seg->next; | |
1338 | ep_ring->dequeue = ep_ring->deq_seg->trbs; | |
1339 | } | |
1340 | if (ep_ring->dequeue == dequeue_temp) { | |
1341 | revert = true; | |
1342 | break; | |
1343 | } | |
1344 | } | |
1345 | ||
1346 | if (revert) { | |
1347 | xhci_dbg(xhci, "Unable to find new dequeue pointer\n"); | |
1348 | ep_ring->num_trbs_free = num_trbs_free_temp; | |
1349 | } | |
1350 | } | |
1351 | ||
ae636747 SS |
1352 | /* |
1353 | * When we get a completion for a Set Transfer Ring Dequeue Pointer command, | |
1354 | * we need to clear the set deq pending flag in the endpoint ring state, so that | |
1355 | * the TD queueing code can ring the doorbell again. We also need to ring the | |
1356 | * endpoint doorbell to restart the ring, but only if there aren't more | |
1357 | * cancellations pending. | |
1358 | */ | |
b8200c94 | 1359 | static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1360 | union xhci_trb *trb, u32 cmd_comp_code) |
ae636747 | 1361 | { |
ae636747 | 1362 | unsigned int ep_index; |
e9df17eb | 1363 | unsigned int stream_id; |
ae636747 | 1364 | struct xhci_ring *ep_ring; |
9aad95e2 | 1365 | struct xhci_virt_ep *ep; |
d115b048 JY |
1366 | struct xhci_ep_ctx *ep_ctx; |
1367 | struct xhci_slot_ctx *slot_ctx; | |
674f8438 | 1368 | struct xhci_td *td, *tmp_td; |
ae636747 | 1369 | |
28ccd296 ME |
1370 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
1371 | stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2])); | |
b1adc42d MN |
1372 | ep = xhci_get_virt_ep(xhci, slot_id, ep_index); |
1373 | if (!ep) | |
1374 | return; | |
e9df17eb | 1375 | |
42f2890a | 1376 | ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id); |
e9df17eb | 1377 | if (!ep_ring) { |
e587b8b2 | 1378 | xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n", |
e9df17eb SS |
1379 | stream_id); |
1380 | /* XXX: Harmless??? */ | |
0d4976ec | 1381 | goto cleanup; |
e9df17eb SS |
1382 | } |
1383 | ||
b1adc42d MN |
1384 | ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); |
1385 | slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx); | |
19a7d0d6 FB |
1386 | trace_xhci_handle_cmd_set_deq(slot_ctx); |
1387 | trace_xhci_handle_cmd_set_deq_ep(ep_ctx); | |
ae636747 | 1388 | |
c69a0597 | 1389 | if (cmd_comp_code != COMP_SUCCESS) { |
ae636747 SS |
1390 | unsigned int ep_state; |
1391 | unsigned int slot_state; | |
1392 | ||
c69a0597 | 1393 | switch (cmd_comp_code) { |
0b7c105a | 1394 | case COMP_TRB_ERROR: |
e587b8b2 | 1395 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n"); |
ae636747 | 1396 | break; |
0b7c105a | 1397 | case COMP_CONTEXT_STATE_ERROR: |
e587b8b2 | 1398 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n"); |
5071e6b2 | 1399 | ep_state = GET_EP_CTX_STATE(ep_ctx); |
28ccd296 | 1400 | slot_state = le32_to_cpu(slot_ctx->dev_state); |
ae636747 | 1401 | slot_state = GET_SLOT_STATE(slot_state); |
aa50b290 XR |
1402 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1403 | "Slot state = %u, EP state = %u", | |
ae636747 SS |
1404 | slot_state, ep_state); |
1405 | break; | |
0b7c105a | 1406 | case COMP_SLOT_NOT_ENABLED_ERROR: |
e587b8b2 ON |
1407 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n", |
1408 | slot_id); | |
ae636747 SS |
1409 | break; |
1410 | default: | |
e587b8b2 ON |
1411 | xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n", |
1412 | cmd_comp_code); | |
ae636747 SS |
1413 | break; |
1414 | } | |
1415 | /* OK what do we do now? The endpoint state is hosed, and we | |
1416 | * should never get to this point if the synchronization between | |
1417 | * queueing, and endpoint state are correct. This might happen | |
1418 | * if the device gets disconnected after we've finished | |
1419 | * cancelling URBs, which might not be an error... | |
1420 | */ | |
1421 | } else { | |
9aad95e2 HG |
1422 | u64 deq; |
1423 | /* 4.6.10 deq ptr is written to the stream ctx for streams */ | |
1424 | if (ep->ep_state & EP_HAS_STREAMS) { | |
1425 | struct xhci_stream_ctx *ctx = | |
1426 | &ep->stream_info->stream_ctx_array[stream_id]; | |
1427 | deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK; | |
1428 | } else { | |
1429 | deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK; | |
1430 | } | |
aa50b290 | 1431 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
9aad95e2 HG |
1432 | "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq); |
1433 | if (xhci_trb_virt_to_dma(ep->queued_deq_seg, | |
1434 | ep->queued_deq_ptr) == deq) { | |
bf161e85 SS |
1435 | /* Update the ring's dequeue segment and dequeue pointer |
1436 | * to reflect the new position. | |
1437 | */ | |
b1adc42d | 1438 | update_ring_for_set_deq_completion(xhci, ep->vdev, |
b008df60 | 1439 | ep_ring, ep_index); |
bf161e85 | 1440 | } else { |
e587b8b2 | 1441 | xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n"); |
bf161e85 | 1442 | xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n", |
9aad95e2 | 1443 | ep->queued_deq_seg, ep->queued_deq_ptr); |
bf161e85 | 1444 | } |
ae636747 | 1445 | } |
674f8438 MN |
1446 | /* HW cached TDs cleared from cache, give them back */ |
1447 | list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, | |
1448 | cancelled_td_list) { | |
1449 | ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb); | |
1450 | if (td->cancel_status == TD_CLEARING_CACHE) { | |
1451 | td->cancel_status = TD_CLEARED; | |
0d9b9f53 MN |
1452 | xhci_dbg(ep->xhci, "%s: Giveback cancelled URB %p TD\n", |
1453 | __func__, td->urb); | |
674f8438 | 1454 | xhci_td_cleanup(ep->xhci, td, ep_ring, td->status); |
0d9b9f53 MN |
1455 | } else { |
1456 | xhci_dbg(ep->xhci, "%s: Keep cancelled URB %p TD as cancel_status is %d\n", | |
1457 | __func__, td->urb, td->cancel_status); | |
674f8438 MN |
1458 | } |
1459 | } | |
0d4976ec | 1460 | cleanup: |
b1adc42d MN |
1461 | ep->ep_state &= ~SET_DEQ_PENDING; |
1462 | ep->queued_deq_seg = NULL; | |
1463 | ep->queued_deq_ptr = NULL; | |
e9df17eb SS |
1464 | /* Restart any rings with pending URBs */ |
1465 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
ae636747 SS |
1466 | } |
1467 | ||
b8200c94 | 1468 | static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id, |
c69a0597 | 1469 | union xhci_trb *trb, u32 cmd_comp_code) |
a1587d97 | 1470 | { |
b1adc42d | 1471 | struct xhci_virt_ep *ep; |
19a7d0d6 | 1472 | struct xhci_ep_ctx *ep_ctx; |
a1587d97 SS |
1473 | unsigned int ep_index; |
1474 | ||
28ccd296 | 1475 | ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3])); |
b1adc42d MN |
1476 | ep = xhci_get_virt_ep(xhci, slot_id, ep_index); |
1477 | if (!ep) | |
1478 | return; | |
1479 | ||
1480 | ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); | |
19a7d0d6 FB |
1481 | trace_xhci_handle_cmd_reset_ep(ep_ctx); |
1482 | ||
a1587d97 SS |
1483 | /* This command will only fail if the endpoint wasn't halted, |
1484 | * but we don't care. | |
1485 | */ | |
a0254324 | 1486 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
c69a0597 | 1487 | "Ignoring reset ep completion code of %u", cmd_comp_code); |
a1587d97 | 1488 | |
674f8438 MN |
1489 | /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */ |
1490 | xhci_invalidate_cancelled_tds(ep); | |
74e0b564 | 1491 | |
674f8438 MN |
1492 | if (xhci->quirks & XHCI_RESET_EP_QUIRK) |
1493 | xhci_dbg(xhci, "Note: Removed workaround to queue config ep for this hw"); | |
1494 | /* Clear our internal halted state */ | |
1495 | ep->ep_state &= ~EP_HALTED; | |
74e0b564 | 1496 | |
674f8438 | 1497 | xhci_giveback_invalidated_tds(ep); |
f8f80be5 MN |
1498 | |
1499 | /* if this was a soft reset, then restart */ | |
1500 | if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP) | |
1501 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
a1587d97 | 1502 | } |
ae636747 | 1503 | |
b244b431 | 1504 | static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id, |
c2d3d49b | 1505 | struct xhci_command *command, u32 cmd_comp_code) |
b244b431 XR |
1506 | { |
1507 | if (cmd_comp_code == COMP_SUCCESS) | |
c2d3d49b | 1508 | command->slot_id = slot_id; |
b244b431 | 1509 | else |
c2d3d49b | 1510 | command->slot_id = 0; |
b244b431 XR |
1511 | } |
1512 | ||
6c02dd14 XR |
1513 | static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id) |
1514 | { | |
1515 | struct xhci_virt_device *virt_dev; | |
19a7d0d6 | 1516 | struct xhci_slot_ctx *slot_ctx; |
6c02dd14 XR |
1517 | |
1518 | virt_dev = xhci->devs[slot_id]; | |
1519 | if (!virt_dev) | |
1520 | return; | |
19a7d0d6 FB |
1521 | |
1522 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
1523 | trace_xhci_handle_cmd_disable_slot(slot_ctx); | |
1524 | ||
6c02dd14 XR |
1525 | if (xhci->quirks & XHCI_EP_LIMIT_QUIRK) |
1526 | /* Delete default control endpoint resources */ | |
1527 | xhci_free_device_endpoint_resources(xhci, virt_dev, true); | |
6c02dd14 XR |
1528 | } |
1529 | ||
6ed46d33 | 1530 | static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id, |
a1810307 | 1531 | u32 cmd_comp_code) |
6ed46d33 XR |
1532 | { |
1533 | struct xhci_virt_device *virt_dev; | |
1534 | struct xhci_input_control_ctx *ctrl_ctx; | |
19a7d0d6 | 1535 | struct xhci_ep_ctx *ep_ctx; |
6ed46d33 XR |
1536 | unsigned int ep_index; |
1537 | unsigned int ep_state; | |
1538 | u32 add_flags, drop_flags; | |
1539 | ||
6ed46d33 XR |
1540 | /* |
1541 | * Configure endpoint commands can come from the USB core | |
1542 | * configuration or alt setting changes, or because the HW | |
1543 | * needed an extra configure endpoint command after a reset | |
1544 | * endpoint command or streams were being configured. | |
1545 | * If the command was for a halted endpoint, the xHCI driver | |
1546 | * is not waiting on the configure endpoint command. | |
1547 | */ | |
9ea1833e | 1548 | virt_dev = xhci->devs[slot_id]; |
03ed579d MN |
1549 | if (!virt_dev) |
1550 | return; | |
4daf9df5 | 1551 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
6ed46d33 XR |
1552 | if (!ctrl_ctx) { |
1553 | xhci_warn(xhci, "Could not get input context, bad type.\n"); | |
1554 | return; | |
1555 | } | |
1556 | ||
1557 | add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
1558 | drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
1559 | /* Input ctx add_flags are the endpoint index plus one */ | |
1560 | ep_index = xhci_last_valid_endpoint(add_flags) - 1; | |
1561 | ||
19a7d0d6 FB |
1562 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index); |
1563 | trace_xhci_handle_cmd_config_ep(ep_ctx); | |
1564 | ||
6ed46d33 XR |
1565 | /* A usb_set_interface() call directly after clearing a halted |
1566 | * condition may race on this quirky hardware. Not worth | |
1567 | * worrying about, since this is prototype hardware. Not sure | |
1568 | * if this will work for streams, but streams support was | |
1569 | * untested on this prototype. | |
1570 | */ | |
1571 | if (xhci->quirks & XHCI_RESET_EP_QUIRK && | |
1572 | ep_index != (unsigned int) -1 && | |
1573 | add_flags - SLOT_FLAG == drop_flags) { | |
1574 | ep_state = virt_dev->eps[ep_index].ep_state; | |
1575 | if (!(ep_state & EP_HALTED)) | |
ddba5cd0 | 1576 | return; |
6ed46d33 XR |
1577 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1578 | "Completed config ep cmd - " | |
1579 | "last ep index = %d, state = %d", | |
1580 | ep_index, ep_state); | |
1581 | /* Clear internal halted state and restart ring(s) */ | |
1582 | virt_dev->eps[ep_index].ep_state &= ~EP_HALTED; | |
1583 | ring_doorbell_for_active_rings(xhci, slot_id, ep_index); | |
1584 | return; | |
1585 | } | |
6ed46d33 XR |
1586 | return; |
1587 | } | |
1588 | ||
19a7d0d6 FB |
1589 | static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id) |
1590 | { | |
1591 | struct xhci_virt_device *vdev; | |
1592 | struct xhci_slot_ctx *slot_ctx; | |
1593 | ||
1594 | vdev = xhci->devs[slot_id]; | |
03ed579d MN |
1595 | if (!vdev) |
1596 | return; | |
19a7d0d6 FB |
1597 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); |
1598 | trace_xhci_handle_cmd_addr_dev(slot_ctx); | |
1599 | } | |
1600 | ||
a1810307 | 1601 | static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id) |
f681321b | 1602 | { |
19a7d0d6 FB |
1603 | struct xhci_virt_device *vdev; |
1604 | struct xhci_slot_ctx *slot_ctx; | |
1605 | ||
1606 | vdev = xhci->devs[slot_id]; | |
03ed579d MN |
1607 | if (!vdev) { |
1608 | xhci_warn(xhci, "Reset device command completion for disabled slot %u\n", | |
1609 | slot_id); | |
1610 | return; | |
1611 | } | |
19a7d0d6 FB |
1612 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); |
1613 | trace_xhci_handle_cmd_reset_dev(slot_ctx); | |
1614 | ||
f681321b | 1615 | xhci_dbg(xhci, "Completed reset device command.\n"); |
f681321b XR |
1616 | } |
1617 | ||
2c070821 XR |
1618 | static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci, |
1619 | struct xhci_event_cmd *event) | |
1620 | { | |
1621 | if (!(xhci->quirks & XHCI_NEC_HOST)) { | |
f4c8f03c | 1622 | xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n"); |
2c070821 XR |
1623 | return; |
1624 | } | |
1625 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, | |
1626 | "NEC firmware version %2x.%02x", | |
1627 | NEC_FW_MAJOR(le32_to_cpu(event->status)), | |
1628 | NEC_FW_MINOR(le32_to_cpu(event->status))); | |
1629 | } | |
1630 | ||
9ea1833e | 1631 | static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status) |
c9aa1a2d MN |
1632 | { |
1633 | list_del(&cmd->cmd_list); | |
9ea1833e MN |
1634 | |
1635 | if (cmd->completion) { | |
1636 | cmd->status = status; | |
1637 | complete(cmd->completion); | |
1638 | } else { | |
c9aa1a2d | 1639 | kfree(cmd); |
9ea1833e | 1640 | } |
c9aa1a2d MN |
1641 | } |
1642 | ||
1643 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci) | |
1644 | { | |
1645 | struct xhci_command *cur_cmd, *tmp_cmd; | |
d1aad52c | 1646 | xhci->current_cmd = NULL; |
c9aa1a2d | 1647 | list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list) |
0b7c105a | 1648 | xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED); |
c9aa1a2d MN |
1649 | } |
1650 | ||
cb4d5ce5 | 1651 | void xhci_handle_command_timeout(struct work_struct *work) |
c311e391 MN |
1652 | { |
1653 | struct xhci_hcd *xhci; | |
c311e391 MN |
1654 | unsigned long flags; |
1655 | u64 hw_ring_state; | |
cb4d5ce5 OH |
1656 | |
1657 | xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer); | |
c311e391 | 1658 | |
c311e391 | 1659 | spin_lock_irqsave(&xhci->lock, flags); |
2b985467 | 1660 | |
a5a1b951 MN |
1661 | /* |
1662 | * If timeout work is pending, or current_cmd is NULL, it means we | |
1663 | * raced with command completion. Command is handled so just return. | |
1664 | */ | |
cb4d5ce5 | 1665 | if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) { |
2b985467 LB |
1666 | spin_unlock_irqrestore(&xhci->lock, flags); |
1667 | return; | |
c311e391 | 1668 | } |
2b985467 | 1669 | /* mark this command to be cancelled */ |
0b7c105a | 1670 | xhci->current_cmd->status = COMP_COMMAND_ABORTED; |
2b985467 | 1671 | |
c311e391 MN |
1672 | /* Make sure command ring is running before aborting it */ |
1673 | hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); | |
d9f11ba9 MN |
1674 | if (hw_ring_state == ~(u64)0) { |
1675 | xhci_hc_died(xhci); | |
1676 | goto time_out_completed; | |
1677 | } | |
1678 | ||
c311e391 MN |
1679 | if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) && |
1680 | (hw_ring_state & CMD_RING_RUNNING)) { | |
1c111b6c OH |
1681 | /* Prevent new doorbell, and start command abort */ |
1682 | xhci->cmd_ring_state = CMD_RING_STATE_ABORTED; | |
c311e391 | 1683 | xhci_dbg(xhci, "Command timeout\n"); |
d9f11ba9 | 1684 | xhci_abort_cmd_ring(xhci, flags); |
4dea7077 | 1685 | goto time_out_completed; |
c311e391 | 1686 | } |
3425aa03 | 1687 | |
1c111b6c OH |
1688 | /* host removed. Bail out */ |
1689 | if (xhci->xhc_state & XHCI_STATE_REMOVING) { | |
1690 | xhci_dbg(xhci, "host removed, ring start fail?\n"); | |
3425aa03 | 1691 | xhci_cleanup_command_queue(xhci); |
4dea7077 LB |
1692 | |
1693 | goto time_out_completed; | |
3425aa03 MN |
1694 | } |
1695 | ||
c311e391 MN |
1696 | /* command timeout on stopped ring, ring can't be aborted */ |
1697 | xhci_dbg(xhci, "Command timeout on stopped ring\n"); | |
1698 | xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd); | |
4dea7077 LB |
1699 | |
1700 | time_out_completed: | |
c311e391 MN |
1701 | spin_unlock_irqrestore(&xhci->lock, flags); |
1702 | return; | |
1703 | } | |
1704 | ||
7f84eef0 SS |
1705 | static void handle_cmd_completion(struct xhci_hcd *xhci, |
1706 | struct xhci_event_cmd *event) | |
1707 | { | |
296fcdab | 1708 | unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
7f84eef0 SS |
1709 | u64 cmd_dma; |
1710 | dma_addr_t cmd_dequeue_dma; | |
e7a79a1d | 1711 | u32 cmd_comp_code; |
9124b121 | 1712 | union xhci_trb *cmd_trb; |
c9aa1a2d | 1713 | struct xhci_command *cmd; |
b54fc46d | 1714 | u32 cmd_type; |
7f84eef0 | 1715 | |
296fcdab LKK |
1716 | if (slot_id >= MAX_HC_SLOTS) { |
1717 | xhci_warn(xhci, "Invalid slot_id %u\n", slot_id); | |
1718 | return; | |
1719 | } | |
1720 | ||
28ccd296 | 1721 | cmd_dma = le64_to_cpu(event->cmd_trb); |
9124b121 | 1722 | cmd_trb = xhci->cmd_ring->dequeue; |
a37c3f76 FB |
1723 | |
1724 | trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic); | |
1725 | ||
23e3be11 | 1726 | cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, |
9124b121 | 1727 | cmd_trb); |
f4c8f03c LB |
1728 | /* |
1729 | * Check whether the completion event is for our internal kept | |
1730 | * command. | |
1731 | */ | |
1732 | if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) { | |
1733 | xhci_warn(xhci, | |
1734 | "ERROR mismatched command completion event\n"); | |
7f84eef0 SS |
1735 | return; |
1736 | } | |
b63f4053 | 1737 | |
04861f83 | 1738 | cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list); |
c9aa1a2d | 1739 | |
cb4d5ce5 | 1740 | cancel_delayed_work(&xhci->cmd_timer); |
c311e391 | 1741 | |
e7a79a1d | 1742 | cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status)); |
c311e391 MN |
1743 | |
1744 | /* If CMD ring stopped we own the trbs between enqueue and dequeue */ | |
604d02a2 | 1745 | if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) { |
1c111b6c | 1746 | complete_all(&xhci->cmd_ring_stop_completion); |
c311e391 MN |
1747 | return; |
1748 | } | |
33be1265 MN |
1749 | |
1750 | if (cmd->command_trb != xhci->cmd_ring->dequeue) { | |
1751 | xhci_err(xhci, | |
1752 | "Command completion event does not match command\n"); | |
1753 | return; | |
1754 | } | |
1755 | ||
c311e391 MN |
1756 | /* |
1757 | * Host aborted the command ring, check if the current command was | |
1758 | * supposed to be aborted, otherwise continue normally. | |
1759 | * The command ring is stopped now, but the xHC will issue a Command | |
1760 | * Ring Stopped event which will cause us to restart it. | |
1761 | */ | |
0b7c105a | 1762 | if (cmd_comp_code == COMP_COMMAND_ABORTED) { |
c311e391 | 1763 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; |
0b7c105a | 1764 | if (cmd->status == COMP_COMMAND_ABORTED) { |
2a7cfdf3 BW |
1765 | if (xhci->current_cmd == cmd) |
1766 | xhci->current_cmd = NULL; | |
c311e391 | 1767 | goto event_handled; |
2a7cfdf3 | 1768 | } |
b63f4053 EF |
1769 | } |
1770 | ||
b54fc46d XR |
1771 | cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3])); |
1772 | switch (cmd_type) { | |
1773 | case TRB_ENABLE_SLOT: | |
c2d3d49b | 1774 | xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code); |
3ffbba95 | 1775 | break; |
b54fc46d | 1776 | case TRB_DISABLE_SLOT: |
6c02dd14 | 1777 | xhci_handle_cmd_disable_slot(xhci, slot_id); |
3ffbba95 | 1778 | break; |
b54fc46d | 1779 | case TRB_CONFIG_EP: |
9ea1833e | 1780 | if (!cmd->completion) |
a1810307 | 1781 | xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code); |
f94e0186 | 1782 | break; |
b54fc46d | 1783 | case TRB_EVAL_CONTEXT: |
2d3f1fac | 1784 | break; |
b54fc46d | 1785 | case TRB_ADDR_DEV: |
19a7d0d6 | 1786 | xhci_handle_cmd_addr_dev(xhci, slot_id); |
3ffbba95 | 1787 | break; |
b54fc46d | 1788 | case TRB_STOP_RING: |
b8200c94 XR |
1789 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1790 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
a38fe338 | 1791 | if (!cmd->completion) |
9ebf3000 MN |
1792 | xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, |
1793 | cmd_comp_code); | |
ae636747 | 1794 | break; |
b54fc46d | 1795 | case TRB_SET_DEQ: |
b8200c94 XR |
1796 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1797 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1798 | xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code); |
ae636747 | 1799 | break; |
b54fc46d | 1800 | case TRB_CMD_NOOP: |
c311e391 | 1801 | /* Is this an aborted command turned to NO-OP? */ |
604d02a2 MN |
1802 | if (cmd->status == COMP_COMMAND_RING_STOPPED) |
1803 | cmd_comp_code = COMP_COMMAND_RING_STOPPED; | |
7f84eef0 | 1804 | break; |
b54fc46d | 1805 | case TRB_RESET_EP: |
b8200c94 XR |
1806 | WARN_ON(slot_id != TRB_TO_SLOT_ID( |
1807 | le32_to_cpu(cmd_trb->generic.field[3]))); | |
c69a0597 | 1808 | xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code); |
a1587d97 | 1809 | break; |
b54fc46d | 1810 | case TRB_RESET_DEV: |
6fcfb0d6 MN |
1811 | /* SLOT_ID field in reset device cmd completion event TRB is 0. |
1812 | * Use the SLOT_ID from the command TRB instead (xhci 4.6.11) | |
1813 | */ | |
1814 | slot_id = TRB_TO_SLOT_ID( | |
1815 | le32_to_cpu(cmd_trb->generic.field[3])); | |
a1810307 | 1816 | xhci_handle_cmd_reset_dev(xhci, slot_id); |
2a8f82c4 | 1817 | break; |
b54fc46d | 1818 | case TRB_NEC_GET_FW: |
2c070821 | 1819 | xhci_handle_cmd_nec_get_fw(xhci, event); |
0238634d | 1820 | break; |
7f84eef0 SS |
1821 | default: |
1822 | /* Skip over unknown commands on the event ring */ | |
f4c8f03c | 1823 | xhci_info(xhci, "INFO unknown command type %d\n", cmd_type); |
7f84eef0 SS |
1824 | break; |
1825 | } | |
c9aa1a2d | 1826 | |
c311e391 | 1827 | /* restart timer if this wasn't the last command */ |
daa47f21 | 1828 | if (!list_is_singular(&xhci->cmd_list)) { |
04861f83 FB |
1829 | xhci->current_cmd = list_first_entry(&cmd->cmd_list, |
1830 | struct xhci_command, cmd_list); | |
cb4d5ce5 | 1831 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
2b985467 LB |
1832 | } else if (xhci->current_cmd == cmd) { |
1833 | xhci->current_cmd = NULL; | |
c311e391 MN |
1834 | } |
1835 | ||
1836 | event_handled: | |
9ea1833e | 1837 | xhci_complete_del_and_free_cmd(cmd, cmd_comp_code); |
c9aa1a2d | 1838 | |
3b72fca0 | 1839 | inc_deq(xhci, xhci->cmd_ring); |
7f84eef0 SS |
1840 | } |
1841 | ||
0238634d | 1842 | static void handle_vendor_event(struct xhci_hcd *xhci, |
0353810a | 1843 | union xhci_trb *event, u32 trb_type) |
0238634d | 1844 | { |
0238634d SS |
1845 | xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type); |
1846 | if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST)) | |
1847 | handle_cmd_completion(xhci, &event->event_cmd); | |
1848 | } | |
1849 | ||
623bef9e SS |
1850 | static void handle_device_notification(struct xhci_hcd *xhci, |
1851 | union xhci_trb *event) | |
1852 | { | |
1853 | u32 slot_id; | |
4ee823b8 | 1854 | struct usb_device *udev; |
623bef9e | 1855 | |
7e76ad43 | 1856 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3])); |
4ee823b8 | 1857 | if (!xhci->devs[slot_id]) { |
623bef9e SS |
1858 | xhci_warn(xhci, "Device Notification event for " |
1859 | "unused slot %u\n", slot_id); | |
4ee823b8 SS |
1860 | return; |
1861 | } | |
1862 | ||
1863 | xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n", | |
1864 | slot_id); | |
1865 | udev = xhci->devs[slot_id]->udev; | |
1866 | if (udev && udev->parent) | |
1867 | usb_wakeup_notification(udev->parent, udev->portnum); | |
623bef9e SS |
1868 | } |
1869 | ||
11644a76 CG |
1870 | /* |
1871 | * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI | |
1872 | * Controller. | |
1873 | * As per ThunderX2errata-129 USB 2 device may come up as USB 1 | |
1874 | * If a connection to a USB 1 device is followed by another connection | |
1875 | * to a USB 2 device. | |
1876 | * | |
1877 | * Reset the PHY after the USB device is disconnected if device speed | |
1878 | * is less than HCD_USB3. | |
1879 | * Retry the reset sequence max of 4 times checking the PLL lock status. | |
1880 | * | |
1881 | */ | |
1882 | static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci) | |
1883 | { | |
1884 | struct usb_hcd *hcd = xhci_to_hcd(xhci); | |
1885 | u32 pll_lock_check; | |
1886 | u32 retry_count = 4; | |
1887 | ||
1888 | do { | |
1889 | /* Assert PHY reset */ | |
1890 | writel(0x6F, hcd->regs + 0x1048); | |
1891 | udelay(10); | |
1892 | /* De-assert the PHY reset */ | |
1893 | writel(0x7F, hcd->regs + 0x1048); | |
1894 | udelay(200); | |
1895 | pll_lock_check = readl(hcd->regs + 0x1070); | |
1896 | } while (!(pll_lock_check & 0x1) && --retry_count); | |
1897 | } | |
1898 | ||
0f2a7930 SS |
1899 | static void handle_port_status(struct xhci_hcd *xhci, |
1900 | union xhci_trb *event) | |
1901 | { | |
f6ff0ac8 | 1902 | struct usb_hcd *hcd; |
0f2a7930 | 1903 | u32 port_id; |
76a0f32b | 1904 | u32 portsc, cmd_reg; |
518e848e | 1905 | int max_ports; |
56192531 | 1906 | int slot_id; |
74e6ad58 | 1907 | unsigned int hcd_portnum; |
20b67cf5 | 1908 | struct xhci_bus_state *bus_state; |
386139d7 | 1909 | bool bogus_port_status = false; |
52c7755b | 1910 | struct xhci_port *port; |
0f2a7930 SS |
1911 | |
1912 | /* Port status change events always have a successful completion code */ | |
f4c8f03c LB |
1913 | if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) |
1914 | xhci_warn(xhci, | |
1915 | "WARN: xHC returned failed port status event\n"); | |
1916 | ||
28ccd296 | 1917 | port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0])); |
518e848e | 1918 | max_ports = HCS_MAX_PORTS(xhci->hcs_params1); |
d70d5a84 | 1919 | |
518e848e | 1920 | if ((port_id <= 0) || (port_id > max_ports)) { |
d70d5a84 MN |
1921 | xhci_warn(xhci, "Port change event with invalid port ID %d\n", |
1922 | port_id); | |
09ce0c0c PC |
1923 | inc_deq(xhci, xhci->event_ring); |
1924 | return; | |
56192531 AX |
1925 | } |
1926 | ||
52c7755b MN |
1927 | port = &xhci->hw_ports[port_id - 1]; |
1928 | if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) { | |
d70d5a84 MN |
1929 | xhci_warn(xhci, "Port change event, no port for port ID %u\n", |
1930 | port_id); | |
386139d7 | 1931 | bogus_port_status = true; |
f6ff0ac8 SS |
1932 | goto cleanup; |
1933 | } | |
1934 | ||
1245374e MN |
1935 | /* We might get interrupts after shared_hcd is removed */ |
1936 | if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) { | |
1937 | xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n"); | |
1938 | bogus_port_status = true; | |
1939 | goto cleanup; | |
1940 | } | |
1941 | ||
52c7755b | 1942 | hcd = port->rhub->hcd; |
f6187f42 | 1943 | bus_state = &port->rhub->bus_state; |
74e6ad58 | 1944 | hcd_portnum = port->hcd_portnum; |
52c7755b | 1945 | portsc = readl(port->addr); |
5308a91b | 1946 | |
d70d5a84 MN |
1947 | xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n", |
1948 | hcd->self.busnum, hcd_portnum + 1, port_id, portsc); | |
1949 | ||
74e6ad58 | 1950 | trace_xhci_handle_port_status(hcd_portnum, portsc); |
8ca1358b | 1951 | |
7111ebc9 | 1952 | if (hcd->state == HC_STATE_SUSPENDED) { |
56192531 AX |
1953 | xhci_dbg(xhci, "resume root hub\n"); |
1954 | usb_hcd_resume_root_hub(hcd); | |
1955 | } | |
1956 | ||
b8c3b718 MN |
1957 | if (hcd->speed >= HCD_USB3 && |
1958 | (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) { | |
1959 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1); | |
1960 | if (slot_id && xhci->devs[slot_id]) | |
1961 | xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR; | |
b8c3b718 | 1962 | } |
fac4271d | 1963 | |
76a0f32b | 1964 | if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) { |
56192531 AX |
1965 | xhci_dbg(xhci, "port resume event for port %d\n", port_id); |
1966 | ||
76a0f32b MN |
1967 | cmd_reg = readl(&xhci->op_regs->command); |
1968 | if (!(cmd_reg & CMD_RUN)) { | |
56192531 AX |
1969 | xhci_warn(xhci, "xHC is not running.\n"); |
1970 | goto cleanup; | |
1971 | } | |
1972 | ||
76a0f32b | 1973 | if (DEV_SUPERSPEED_ANY(portsc)) { |
d93814cf | 1974 | xhci_dbg(xhci, "remote wake SS port %d\n", port_id); |
4ee823b8 SS |
1975 | /* Set a flag to say the port signaled remote wakeup, |
1976 | * so we can tell the difference between the end of | |
1977 | * device and host initiated resume. | |
1978 | */ | |
74e6ad58 | 1979 | bus_state->port_remote_wakeup |= 1 << hcd_portnum; |
eaefcf24 | 1980 | xhci_test_and_clear_bit(xhci, port, PORT_PLC); |
057d476f | 1981 | usb_hcd_start_port_resume(&hcd->self, hcd_portnum); |
6b7f40f7 | 1982 | xhci_set_link_state(xhci, port, XDEV_U0); |
d93814cf SS |
1983 | /* Need to wait until the next link state change |
1984 | * indicates the device is actually in U0. | |
1985 | */ | |
1986 | bogus_port_status = true; | |
1987 | goto cleanup; | |
74e6ad58 | 1988 | } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) { |
56192531 | 1989 | xhci_dbg(xhci, "resume HS port %d\n", port_id); |
74e6ad58 | 1990 | bus_state->resume_done[hcd_portnum] = jiffies + |
b9e45188 | 1991 | msecs_to_jiffies(USB_RESUME_TIMEOUT); |
74e6ad58 | 1992 | set_bit(hcd_portnum, &bus_state->resuming_ports); |
0914ea66 AG |
1993 | /* Do the rest in GetPortStatus after resume time delay. |
1994 | * Avoid polling roothub status before that so that a | |
1995 | * usb device auto-resume latency around ~40ms. | |
1996 | */ | |
1997 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
56192531 | 1998 | mod_timer(&hcd->rh_timer, |
74e6ad58 | 1999 | bus_state->resume_done[hcd_portnum]); |
330e2d61 | 2000 | usb_hcd_start_port_resume(&hcd->self, hcd_portnum); |
0914ea66 | 2001 | bogus_port_status = true; |
56192531 AX |
2002 | } |
2003 | } | |
d93814cf | 2004 | |
6cbcf596 MN |
2005 | if ((portsc & PORT_PLC) && |
2006 | DEV_SUPERSPEED_ANY(portsc) && | |
2007 | ((portsc & PORT_PLS_MASK) == XDEV_U0 || | |
2008 | (portsc & PORT_PLS_MASK) == XDEV_U1 || | |
2009 | (portsc & PORT_PLS_MASK) == XDEV_U2)) { | |
d93814cf | 2010 | xhci_dbg(xhci, "resume SS port %d finished\n", port_id); |
0200b9f7 | 2011 | complete(&bus_state->u3exit_done[hcd_portnum]); |
6cbcf596 | 2012 | /* We've just brought the device into U0/1/2 through either the |
4ee823b8 SS |
2013 | * Resume state after a device remote wakeup, or through the |
2014 | * U3Exit state after a host-initiated resume. If it's a device | |
2015 | * initiated remote wake, don't pass up the link state change, | |
2016 | * so the roothub behavior is consistent with external | |
2017 | * USB 3.0 hub behavior. | |
2018 | */ | |
74e6ad58 | 2019 | slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1); |
d93814cf SS |
2020 | if (slot_id && xhci->devs[slot_id]) |
2021 | xhci_ring_device(xhci, slot_id); | |
74e6ad58 | 2022 | if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) { |
eaefcf24 | 2023 | xhci_test_and_clear_bit(xhci, port, PORT_PLC); |
4ee823b8 | 2024 | usb_wakeup_notification(hcd->self.root_hub, |
74e6ad58 | 2025 | hcd_portnum + 1); |
4ee823b8 SS |
2026 | bogus_port_status = true; |
2027 | goto cleanup; | |
2028 | } | |
d93814cf | 2029 | } |
56192531 | 2030 | |
8b3d4570 SS |
2031 | /* |
2032 | * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or | |
2033 | * RExit to a disconnect state). If so, let the the driver know it's | |
2034 | * out of the RExit state. | |
2035 | */ | |
958c0bd8 | 2036 | if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 && |
74e6ad58 | 2037 | test_and_clear_bit(hcd_portnum, |
8b3d4570 | 2038 | &bus_state->rexit_ports)) { |
74e6ad58 | 2039 | complete(&bus_state->rexit_done[hcd_portnum]); |
8b3d4570 SS |
2040 | bogus_port_status = true; |
2041 | goto cleanup; | |
2042 | } | |
2043 | ||
11644a76 | 2044 | if (hcd->speed < HCD_USB3) { |
eaefcf24 | 2045 | xhci_test_and_clear_bit(xhci, port, PORT_PLC); |
11644a76 CG |
2046 | if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) && |
2047 | (portsc & PORT_CSC) && !(portsc & PORT_CONNECT)) | |
2048 | xhci_cavium_reset_phy_quirk(xhci); | |
2049 | } | |
6fd45621 | 2050 | |
56192531 | 2051 | cleanup: |
0f2a7930 | 2052 | /* Update event ring dequeue pointer before dropping the lock */ |
3b72fca0 | 2053 | inc_deq(xhci, xhci->event_ring); |
0f2a7930 | 2054 | |
386139d7 SS |
2055 | /* Don't make the USB core poll the roothub if we got a bad port status |
2056 | * change event. Besides, at that point we can't tell which roothub | |
2057 | * (USB 2.0 or USB 3.0) to kick. | |
2058 | */ | |
2059 | if (bogus_port_status) | |
2060 | return; | |
2061 | ||
c52804a4 SS |
2062 | /* |
2063 | * xHCI port-status-change events occur when the "or" of all the | |
2064 | * status-change bits in the portsc register changes from 0 to 1. | |
2065 | * New status changes won't cause an event if any other change | |
2066 | * bits are still set. When an event occurs, switch over to | |
2067 | * polling to avoid losing status changes. | |
2068 | */ | |
669bc5a1 MN |
2069 | xhci_dbg(xhci, "%s: starting usb%d port polling.\n", |
2070 | __func__, hcd->self.busnum); | |
c52804a4 | 2071 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
0f2a7930 SS |
2072 | spin_unlock(&xhci->lock); |
2073 | /* Pass this up to the core */ | |
f6ff0ac8 | 2074 | usb_hcd_poll_rh_status(hcd); |
0f2a7930 SS |
2075 | spin_lock(&xhci->lock); |
2076 | } | |
2077 | ||
d0e96f5a SS |
2078 | /* |
2079 | * This TD is defined by the TRBs starting at start_trb in start_seg and ending | |
2080 | * at end_trb, which may be in another segment. If the suspect DMA address is a | |
2081 | * TRB in this TD, this function returns that TRB's segment. Otherwise it | |
2082 | * returns 0. | |
2083 | */ | |
cffb9be8 HG |
2084 | struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, |
2085 | struct xhci_segment *start_seg, | |
d0e96f5a SS |
2086 | union xhci_trb *start_trb, |
2087 | union xhci_trb *end_trb, | |
cffb9be8 HG |
2088 | dma_addr_t suspect_dma, |
2089 | bool debug) | |
d0e96f5a SS |
2090 | { |
2091 | dma_addr_t start_dma; | |
2092 | dma_addr_t end_seg_dma; | |
2093 | dma_addr_t end_trb_dma; | |
2094 | struct xhci_segment *cur_seg; | |
2095 | ||
23e3be11 | 2096 | start_dma = xhci_trb_virt_to_dma(start_seg, start_trb); |
d0e96f5a SS |
2097 | cur_seg = start_seg; |
2098 | ||
2099 | do { | |
2fa88daa | 2100 | if (start_dma == 0) |
326b4810 | 2101 | return NULL; |
ae636747 | 2102 | /* We may get an event for a Link TRB in the middle of a TD */ |
23e3be11 | 2103 | end_seg_dma = xhci_trb_virt_to_dma(cur_seg, |
2fa88daa | 2104 | &cur_seg->trbs[TRBS_PER_SEGMENT - 1]); |
d0e96f5a | 2105 | /* If the end TRB isn't in this segment, this is set to 0 */ |
23e3be11 | 2106 | end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb); |
d0e96f5a | 2107 | |
cffb9be8 HG |
2108 | if (debug) |
2109 | xhci_warn(xhci, | |
2110 | "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n", | |
2111 | (unsigned long long)suspect_dma, | |
2112 | (unsigned long long)start_dma, | |
2113 | (unsigned long long)end_trb_dma, | |
2114 | (unsigned long long)cur_seg->dma, | |
2115 | (unsigned long long)end_seg_dma); | |
2116 | ||
d0e96f5a SS |
2117 | if (end_trb_dma > 0) { |
2118 | /* The end TRB is in this segment, so suspect should be here */ | |
2119 | if (start_dma <= end_trb_dma) { | |
2120 | if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma) | |
2121 | return cur_seg; | |
2122 | } else { | |
2123 | /* Case for one segment with | |
2124 | * a TD wrapped around to the top | |
2125 | */ | |
2126 | if ((suspect_dma >= start_dma && | |
2127 | suspect_dma <= end_seg_dma) || | |
2128 | (suspect_dma >= cur_seg->dma && | |
2129 | suspect_dma <= end_trb_dma)) | |
2130 | return cur_seg; | |
2131 | } | |
326b4810 | 2132 | return NULL; |
d0e96f5a SS |
2133 | } else { |
2134 | /* Might still be somewhere in this segment */ | |
2135 | if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma) | |
2136 | return cur_seg; | |
2137 | } | |
2138 | cur_seg = cur_seg->next; | |
23e3be11 | 2139 | start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]); |
2fa88daa | 2140 | } while (cur_seg != start_seg); |
d0e96f5a | 2141 | |
326b4810 | 2142 | return NULL; |
d0e96f5a SS |
2143 | } |
2144 | ||
ef513be0 JL |
2145 | static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td, |
2146 | struct xhci_virt_ep *ep) | |
2147 | { | |
2148 | /* | |
2149 | * As part of low/full-speed endpoint-halt processing | |
2150 | * we must clear the TT buffer (USB 2.0 specification 11.17.5). | |
2151 | */ | |
2152 | if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) && | |
2153 | (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) && | |
2154 | !(ep->ep_state & EP_CLEARING_TT)) { | |
2155 | ep->ep_state |= EP_CLEARING_TT; | |
2156 | td->urb->ep->hcpriv = td->urb->dev; | |
2157 | if (usb_hub_clear_tt_buffer(td->urb)) | |
2158 | ep->ep_state &= ~EP_CLEARING_TT; | |
2159 | } | |
2160 | } | |
2161 | ||
bcef3fd5 SS |
2162 | /* Check if an error has halted the endpoint ring. The class driver will |
2163 | * cleanup the halt for a non-default control endpoint if we indicate a stall. | |
2164 | * However, a babble and other errors also halt the endpoint ring, and the class | |
2165 | * driver won't clear the halt in that case, so we need to issue a Set Transfer | |
2166 | * Ring Dequeue Pointer command manually. | |
2167 | */ | |
2168 | static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci, | |
2169 | struct xhci_ep_ctx *ep_ctx, | |
2170 | unsigned int trb_comp_code) | |
2171 | { | |
2172 | /* TRB completion codes that may require a manual halt cleanup */ | |
0b7c105a FB |
2173 | if (trb_comp_code == COMP_USB_TRANSACTION_ERROR || |
2174 | trb_comp_code == COMP_BABBLE_DETECTED_ERROR || | |
2175 | trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR) | |
d4fc8bf5 | 2176 | /* The 0.95 spec says a babbling control endpoint |
bcef3fd5 SS |
2177 | * is not halted. The 0.96 spec says it is. Some HW |
2178 | * claims to be 0.95 compliant, but it halts the control | |
2179 | * endpoint anyway. Check if a babble halted the | |
2180 | * endpoint. | |
2181 | */ | |
5071e6b2 | 2182 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED) |
bcef3fd5 SS |
2183 | return 1; |
2184 | ||
2185 | return 0; | |
2186 | } | |
2187 | ||
b45b5069 SS |
2188 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code) |
2189 | { | |
2190 | if (trb_comp_code >= 224 && trb_comp_code <= 255) { | |
2191 | /* Vendor defined "informational" completion code, | |
2192 | * treat as not-an-error. | |
2193 | */ | |
2194 | xhci_dbg(xhci, "Vendor defined info completion code %u\n", | |
2195 | trb_comp_code); | |
2196 | xhci_dbg(xhci, "Treating code as success.\n"); | |
2197 | return 1; | |
2198 | } | |
2199 | return 0; | |
2200 | } | |
2201 | ||
e9fcb077 MN |
2202 | static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, |
2203 | struct xhci_ring *ep_ring, struct xhci_td *td, | |
2204 | u32 trb_comp_code) | |
4422da61 | 2205 | { |
4422da61 | 2206 | struct xhci_ep_ctx *ep_ctx; |
4422da61 | 2207 | |
ab58f3bb | 2208 | ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index); |
4422da61 | 2209 | |
3c648d3d MN |
2210 | switch (trb_comp_code) { |
2211 | case COMP_STOPPED_LENGTH_INVALID: | |
2212 | case COMP_STOPPED_SHORT_PACKET: | |
2213 | case COMP_STOPPED: | |
2214 | /* | |
2215 | * The "Stop Endpoint" completion will take care of any | |
2216 | * stopped TDs. A stopped TD may be restarted, so don't update | |
4422da61 AX |
2217 | * the ring dequeue pointer or take this TD off any lists yet. |
2218 | */ | |
4422da61 | 2219 | return 0; |
3c648d3d MN |
2220 | case COMP_USB_TRANSACTION_ERROR: |
2221 | case COMP_BABBLE_DETECTED_ERROR: | |
2222 | case COMP_SPLIT_TRANSACTION_ERROR: | |
2223 | /* | |
2224 | * If endpoint context state is not halted we might be | |
2225 | * racing with a reset endpoint command issued by a unsuccessful | |
2226 | * stop endpoint completion (context error). In that case the | |
2227 | * td should be on the cancelled list, and EP_HALTED flag set. | |
2228 | * | |
2229 | * Or then it's not halted due to the 0.95 spec stating that a | |
2230 | * babbling control endpoint should not halt. The 0.96 spec | |
2231 | * again says it should. Some HW claims to be 0.95 compliant, | |
2232 | * but it halts the control endpoint anyway. | |
2233 | */ | |
2234 | if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) { | |
2235 | /* | |
2236 | * If EP_HALTED is set and TD is on the cancelled list | |
2237 | * the TD and dequeue pointer will be handled by reset | |
2238 | * ep command completion | |
2239 | */ | |
2240 | if ((ep->ep_state & EP_HALTED) && | |
2241 | !list_empty(&td->cancelled_td_list)) { | |
2242 | xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n", | |
2243 | (unsigned long long)xhci_trb_virt_to_dma( | |
2244 | td->start_seg, td->first_trb)); | |
2245 | return 0; | |
2246 | } | |
2247 | /* endpoint not halted, don't reset it */ | |
2248 | break; | |
2249 | } | |
2250 | /* Almost same procedure as for STALL_ERROR below */ | |
2251 | xhci_clear_hub_tt_buffer(xhci, td, ep); | |
2252 | xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td, | |
2253 | EP_HARD_RESET); | |
2254 | return 0; | |
2255 | case COMP_STALL_ERROR: | |
8f97250c MN |
2256 | /* |
2257 | * xhci internal endpoint state will go to a "halt" state for | |
2258 | * any stall, including default control pipe protocol stall. | |
2259 | * To clear the host side halt we need to issue a reset endpoint | |
2260 | * command, followed by a set dequeue command to move past the | |
2261 | * TD. | |
2262 | * Class drivers clear the device side halt from a functional | |
2263 | * stall later. Hub TT buffer should only be cleared for FS/LS | |
2264 | * devices behind HS hubs for functional stalls. | |
69defe04 | 2265 | */ |
3c648d3d | 2266 | if (ep->ep_index != 0) |
8f97250c | 2267 | xhci_clear_hub_tt_buffer(xhci, td, ep); |
7c6c334e MN |
2268 | |
2269 | xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td, | |
674f8438 MN |
2270 | EP_HARD_RESET); |
2271 | ||
2272 | return 0; /* xhci_handle_halted_endpoint marked td cancelled */ | |
3c648d3d MN |
2273 | default: |
2274 | break; | |
69defe04 | 2275 | } |
4422da61 | 2276 | |
3c648d3d MN |
2277 | /* Update ring dequeue pointer */ |
2278 | ep_ring->dequeue = td->last_trb; | |
2279 | ep_ring->deq_seg = td->last_trb_seg; | |
2280 | ep_ring->num_trbs_free += td->num_trbs - 1; | |
2281 | inc_deq(xhci, ep_ring); | |
2282 | ||
a6ccd1fd | 2283 | return xhci_td_cleanup(xhci, td, ep_ring, td->status); |
4422da61 AX |
2284 | } |
2285 | ||
30a65b45 MN |
2286 | /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */ |
2287 | static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
2288 | union xhci_trb *stop_trb) | |
2289 | { | |
2290 | u32 sum; | |
2291 | union xhci_trb *trb = ring->dequeue; | |
2292 | struct xhci_segment *seg = ring->deq_seg; | |
2293 | ||
2294 | for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) { | |
2295 | if (!trb_is_noop(trb) && !trb_is_link(trb)) | |
2296 | sum += TRB_LEN(le32_to_cpu(trb->generic.field[2])); | |
2297 | } | |
2298 | return sum; | |
2299 | } | |
2300 | ||
8af56be1 AX |
2301 | /* |
2302 | * Process control tds, update urb status and actual_length. | |
2303 | */ | |
e9fcb077 MN |
2304 | static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, |
2305 | struct xhci_ring *ep_ring, struct xhci_td *td, | |
2306 | union xhci_trb *ep_trb, struct xhci_transfer_event *event) | |
8af56be1 | 2307 | { |
8af56be1 AX |
2308 | struct xhci_ep_ctx *ep_ctx; |
2309 | u32 trb_comp_code; | |
0b6c324c | 2310 | u32 remaining, requested; |
29fc1aa4 | 2311 | u32 trb_type; |
8af56be1 | 2312 | |
29fc1aa4 | 2313 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3])); |
ab58f3bb | 2314 | ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index); |
28ccd296 | 2315 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
0b6c324c MN |
2316 | requested = td->urb->transfer_buffer_length; |
2317 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2318 | ||
8af56be1 AX |
2319 | switch (trb_comp_code) { |
2320 | case COMP_SUCCESS: | |
29fc1aa4 | 2321 | if (trb_type != TRB_STATUS) { |
0b6c324c | 2322 | xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n", |
29fc1aa4 | 2323 | (trb_type == TRB_DATA) ? "data" : "setup"); |
a6ccd1fd | 2324 | td->status = -ESHUTDOWN; |
0b6c324c | 2325 | break; |
8af56be1 | 2326 | } |
a6ccd1fd | 2327 | td->status = 0; |
8af56be1 | 2328 | break; |
0b7c105a | 2329 | case COMP_SHORT_PACKET: |
a6ccd1fd | 2330 | td->status = 0; |
8af56be1 | 2331 | break; |
0b7c105a | 2332 | case COMP_STOPPED_SHORT_PACKET: |
29fc1aa4 | 2333 | if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) |
0b6c324c | 2334 | td->urb->actual_length = remaining; |
40a3b775 | 2335 | else |
0b6c324c MN |
2336 | xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n"); |
2337 | goto finish_td; | |
0b7c105a | 2338 | case COMP_STOPPED: |
29fc1aa4 FB |
2339 | switch (trb_type) { |
2340 | case TRB_SETUP: | |
2341 | td->urb->actual_length = 0; | |
2342 | goto finish_td; | |
2343 | case TRB_DATA: | |
2344 | case TRB_NORMAL: | |
0b6c324c | 2345 | td->urb->actual_length = requested - remaining; |
29fc1aa4 | 2346 | goto finish_td; |
0ab2881a MN |
2347 | case TRB_STATUS: |
2348 | td->urb->actual_length = requested; | |
2349 | goto finish_td; | |
29fc1aa4 FB |
2350 | default: |
2351 | xhci_warn(xhci, "WARN: unexpected TRB Type %d\n", | |
2352 | trb_type); | |
2353 | goto finish_td; | |
2354 | } | |
0b7c105a | 2355 | case COMP_STOPPED_LENGTH_INVALID: |
0b6c324c | 2356 | goto finish_td; |
8af56be1 AX |
2357 | default: |
2358 | if (!xhci_requires_manual_halt_cleanup(xhci, | |
0b6c324c | 2359 | ep_ctx, trb_comp_code)) |
8af56be1 | 2360 | break; |
0b6c324c | 2361 | xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n", |
ab58f3bb | 2362 | trb_comp_code, ep->ep_index); |
df561f66 | 2363 | fallthrough; |
0b7c105a | 2364 | case COMP_STALL_ERROR: |
8af56be1 | 2365 | /* Did we transfer part of the data (middle) phase? */ |
29fc1aa4 | 2366 | if (trb_type == TRB_DATA || trb_type == TRB_NORMAL) |
0b6c324c | 2367 | td->urb->actual_length = requested - remaining; |
22ae47e6 | 2368 | else if (!td->urb_length_set) |
8af56be1 | 2369 | td->urb->actual_length = 0; |
0b6c324c | 2370 | goto finish_td; |
8af56be1 | 2371 | } |
0b6c324c MN |
2372 | |
2373 | /* stopped at setup stage, no data transferred */ | |
29fc1aa4 | 2374 | if (trb_type == TRB_SETUP) |
0b6c324c MN |
2375 | goto finish_td; |
2376 | ||
8af56be1 | 2377 | /* |
0b6c324c MN |
2378 | * if on data stage then update the actual_length of the URB and flag it |
2379 | * as set, so it won't be overwritten in the event for the last TRB. | |
8af56be1 | 2380 | */ |
29fc1aa4 FB |
2381 | if (trb_type == TRB_DATA || |
2382 | trb_type == TRB_NORMAL) { | |
0b6c324c MN |
2383 | td->urb_length_set = true; |
2384 | td->urb->actual_length = requested - remaining; | |
2385 | xhci_dbg(xhci, "Waiting for status stage event\n"); | |
2386 | return 0; | |
8af56be1 AX |
2387 | } |
2388 | ||
0b6c324c MN |
2389 | /* at status stage */ |
2390 | if (!td->urb_length_set) | |
2391 | td->urb->actual_length = requested; | |
2392 | ||
2393 | finish_td: | |
e9fcb077 | 2394 | return finish_td(xhci, ep, ep_ring, td, trb_comp_code); |
8af56be1 AX |
2395 | } |
2396 | ||
04e51901 AX |
2397 | /* |
2398 | * Process isochronous tds, update urb packet status and actual_length. | |
2399 | */ | |
e9fcb077 MN |
2400 | static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, |
2401 | struct xhci_ring *ep_ring, struct xhci_td *td, | |
2402 | union xhci_trb *ep_trb, struct xhci_transfer_event *event) | |
04e51901 | 2403 | { |
04e51901 AX |
2404 | struct urb_priv *urb_priv; |
2405 | int idx; | |
926008c9 | 2406 | struct usb_iso_packet_descriptor *frame; |
04e51901 | 2407 | u32 trb_comp_code; |
36da3a1d MN |
2408 | bool sum_trbs_for_length = false; |
2409 | u32 remaining, requested, ep_trb_len; | |
2410 | int short_framestatus; | |
04e51901 | 2411 | |
28ccd296 | 2412 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
04e51901 | 2413 | urb_priv = td->urb->hcpriv; |
9ef7fbbb | 2414 | idx = urb_priv->num_tds_done; |
926008c9 | 2415 | frame = &td->urb->iso_frame_desc[idx]; |
36da3a1d MN |
2416 | requested = frame->length; |
2417 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); | |
2418 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); | |
2419 | short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ? | |
2420 | -EREMOTEIO : 0; | |
04e51901 | 2421 | |
926008c9 DT |
2422 | /* handle completion code */ |
2423 | switch (trb_comp_code) { | |
2424 | case COMP_SUCCESS: | |
36da3a1d MN |
2425 | if (remaining) { |
2426 | frame->status = short_framestatus; | |
2427 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH) | |
2428 | sum_trbs_for_length = true; | |
1530bbc6 SS |
2429 | break; |
2430 | } | |
36da3a1d MN |
2431 | frame->status = 0; |
2432 | break; | |
0b7c105a | 2433 | case COMP_SHORT_PACKET: |
36da3a1d MN |
2434 | frame->status = short_framestatus; |
2435 | sum_trbs_for_length = true; | |
926008c9 | 2436 | break; |
0b7c105a | 2437 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
926008c9 | 2438 | frame->status = -ECOMM; |
926008c9 | 2439 | break; |
0b7c105a FB |
2440 | case COMP_ISOCH_BUFFER_OVERRUN: |
2441 | case COMP_BABBLE_DETECTED_ERROR: | |
926008c9 | 2442 | frame->status = -EOVERFLOW; |
926008c9 | 2443 | break; |
0b7c105a FB |
2444 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
2445 | case COMP_STALL_ERROR: | |
d104d015 | 2446 | frame->status = -EPROTO; |
d104d015 | 2447 | break; |
0b7c105a | 2448 | case COMP_USB_TRANSACTION_ERROR: |
926008c9 | 2449 | frame->status = -EPROTO; |
f97c08ae | 2450 | if (ep_trb != td->last_trb) |
d104d015 | 2451 | return 0; |
926008c9 | 2452 | break; |
0b7c105a | 2453 | case COMP_STOPPED: |
36da3a1d MN |
2454 | sum_trbs_for_length = true; |
2455 | break; | |
0b7c105a | 2456 | case COMP_STOPPED_SHORT_PACKET: |
36da3a1d MN |
2457 | /* field normally containing residue now contains tranferred */ |
2458 | frame->status = short_framestatus; | |
2459 | requested = remaining; | |
2460 | break; | |
0b7c105a | 2461 | case COMP_STOPPED_LENGTH_INVALID: |
36da3a1d MN |
2462 | requested = 0; |
2463 | remaining = 0; | |
926008c9 DT |
2464 | break; |
2465 | default: | |
36da3a1d | 2466 | sum_trbs_for_length = true; |
926008c9 DT |
2467 | frame->status = -1; |
2468 | break; | |
04e51901 AX |
2469 | } |
2470 | ||
36da3a1d | 2471 | if (sum_trbs_for_length) |
d4dff804 | 2472 | frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) + |
36da3a1d MN |
2473 | ep_trb_len - remaining; |
2474 | else | |
2475 | frame->actual_length = requested; | |
04e51901 | 2476 | |
36da3a1d | 2477 | td->urb->actual_length += frame->actual_length; |
04e51901 | 2478 | |
e9fcb077 | 2479 | return finish_td(xhci, ep, ep_ring, td, trb_comp_code); |
04e51901 AX |
2480 | } |
2481 | ||
926008c9 | 2482 | static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td, |
a6ccd1fd | 2483 | struct xhci_virt_ep *ep, int status) |
926008c9 | 2484 | { |
926008c9 DT |
2485 | struct urb_priv *urb_priv; |
2486 | struct usb_iso_packet_descriptor *frame; | |
2487 | int idx; | |
2488 | ||
926008c9 | 2489 | urb_priv = td->urb->hcpriv; |
9ef7fbbb | 2490 | idx = urb_priv->num_tds_done; |
926008c9 DT |
2491 | frame = &td->urb->iso_frame_desc[idx]; |
2492 | ||
b3df3f9c | 2493 | /* The transfer is partly done. */ |
926008c9 DT |
2494 | frame->status = -EXDEV; |
2495 | ||
2496 | /* calc actual length */ | |
2497 | frame->actual_length = 0; | |
2498 | ||
2499 | /* Update ring dequeue pointer */ | |
55f6153d MN |
2500 | ep->ring->dequeue = td->last_trb; |
2501 | ep->ring->deq_seg = td->last_trb_seg; | |
2502 | ep->ring->num_trbs_free += td->num_trbs - 1; | |
d4dff804 | 2503 | inc_deq(xhci, ep->ring); |
926008c9 | 2504 | |
d4dff804 | 2505 | return xhci_td_cleanup(xhci, td, ep->ring, status); |
926008c9 DT |
2506 | } |
2507 | ||
22405ed2 AX |
2508 | /* |
2509 | * Process bulk and interrupt tds, update urb status and actual_length. | |
2510 | */ | |
e9fcb077 MN |
2511 | static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep, |
2512 | struct xhci_ring *ep_ring, struct xhci_td *td, | |
2513 | union xhci_trb *ep_trb, struct xhci_transfer_event *event) | |
22405ed2 | 2514 | { |
f8f80be5 | 2515 | struct xhci_slot_ctx *slot_ctx; |
22405ed2 | 2516 | u32 trb_comp_code; |
f97c08ae | 2517 | u32 remaining, requested, ep_trb_len; |
22405ed2 | 2518 | |
ab58f3bb | 2519 | slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx); |
28ccd296 | 2520 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); |
30a65b45 | 2521 | remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)); |
f97c08ae | 2522 | ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2])); |
30a65b45 | 2523 | requested = td->urb->transfer_buffer_length; |
22405ed2 AX |
2524 | |
2525 | switch (trb_comp_code) { | |
2526 | case COMP_SUCCESS: | |
f8f80be5 | 2527 | ep_ring->err_count = 0; |
30a65b45 | 2528 | /* handle success with untransferred data as short packet */ |
f97c08ae | 2529 | if (ep_trb != td->last_trb || remaining) { |
52ab8685 | 2530 | xhci_warn(xhci, "WARN Successful completion on short TX\n"); |
30a65b45 MN |
2531 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2532 | td->urb->ep->desc.bEndpointAddress, | |
2533 | requested, remaining); | |
22405ed2 | 2534 | } |
a6ccd1fd | 2535 | td->status = 0; |
22405ed2 | 2536 | break; |
0b7c105a | 2537 | case COMP_SHORT_PACKET: |
30a65b45 MN |
2538 | xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n", |
2539 | td->urb->ep->desc.bEndpointAddress, | |
2540 | requested, remaining); | |
a6ccd1fd | 2541 | td->status = 0; |
22405ed2 | 2542 | break; |
0b7c105a | 2543 | case COMP_STOPPED_SHORT_PACKET: |
30a65b45 MN |
2544 | td->urb->actual_length = remaining; |
2545 | goto finish_td; | |
0b7c105a | 2546 | case COMP_STOPPED_LENGTH_INVALID: |
30a65b45 | 2547 | /* stopped on ep trb with invalid length, exclude it */ |
f97c08ae | 2548 | ep_trb_len = 0; |
30a65b45 MN |
2549 | remaining = 0; |
2550 | break; | |
f8f80be5 | 2551 | case COMP_USB_TRANSACTION_ERROR: |
a4a251f8 SG |
2552 | if (xhci->quirks & XHCI_NO_SOFT_RETRY || |
2553 | (ep_ring->err_count++ > MAX_SOFT_RETRY) || | |
f8f80be5 MN |
2554 | le32_to_cpu(slot_ctx->tt_info) & TT_SLOT) |
2555 | break; | |
a6ccd1fd MN |
2556 | |
2557 | td->status = 0; | |
7c6c334e MN |
2558 | |
2559 | xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td, | |
2560 | EP_SOFT_RESET); | |
f8f80be5 | 2561 | return 0; |
22405ed2 | 2562 | default: |
30a65b45 | 2563 | /* do nothing */ |
22405ed2 AX |
2564 | break; |
2565 | } | |
40a3b775 | 2566 | |
f97c08ae | 2567 | if (ep_trb == td->last_trb) |
30a65b45 MN |
2568 | td->urb->actual_length = requested - remaining; |
2569 | else | |
2570 | td->urb->actual_length = | |
f97c08ae MN |
2571 | sum_trb_lengths(xhci, ep_ring, ep_trb) + |
2572 | ep_trb_len - remaining; | |
30a65b45 MN |
2573 | finish_td: |
2574 | if (remaining > requested) { | |
2575 | xhci_warn(xhci, "bad transfer trb length %d in event trb\n", | |
2576 | remaining); | |
22405ed2 | 2577 | td->urb->actual_length = 0; |
22405ed2 | 2578 | } |
e9fcb077 MN |
2579 | |
2580 | return finish_td(xhci, ep, ep_ring, td, trb_comp_code); | |
22405ed2 AX |
2581 | } |
2582 | ||
d0e96f5a SS |
2583 | /* |
2584 | * If this function returns an error condition, it means it got a Transfer | |
2585 | * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address. | |
2586 | * At this point, the host controller is probably hosed and should be reset. | |
2587 | */ | |
2588 | static int handle_tx_event(struct xhci_hcd *xhci, | |
2589 | struct xhci_transfer_event *event) | |
2590 | { | |
63a0d9ab | 2591 | struct xhci_virt_ep *ep; |
d0e96f5a | 2592 | struct xhci_ring *ep_ring; |
82d1009f | 2593 | unsigned int slot_id; |
d0e96f5a | 2594 | int ep_index; |
326b4810 | 2595 | struct xhci_td *td = NULL; |
f97c08ae MN |
2596 | dma_addr_t ep_trb_dma; |
2597 | struct xhci_segment *ep_seg; | |
2598 | union xhci_trb *ep_trb; | |
d0e96f5a | 2599 | int status = -EINPROGRESS; |
d115b048 | 2600 | struct xhci_ep_ctx *ep_ctx; |
c2d7b49f | 2601 | struct list_head *tmp; |
66d1eebc | 2602 | u32 trb_comp_code; |
c2d7b49f | 2603 | int td_num = 0; |
3b4739b8 | 2604 | bool handling_skipped_tds = false; |
d0e96f5a | 2605 | |
28ccd296 | 2606 | slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags)); |
b3368382 MN |
2607 | ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1; |
2608 | trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len)); | |
2609 | ep_trb_dma = le64_to_cpu(event->buffer); | |
2610 | ||
b1adc42d MN |
2611 | ep = xhci_get_virt_ep(xhci, slot_id, ep_index); |
2612 | if (!ep) { | |
2613 | xhci_err(xhci, "ERROR Invalid Transfer event\n"); | |
b3368382 MN |
2614 | goto err_out; |
2615 | } | |
2616 | ||
b3368382 | 2617 | ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma); |
b1adc42d | 2618 | ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index); |
b3368382 | 2619 | |
ade2e3a1 | 2620 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) { |
b7f769ae | 2621 | xhci_err(xhci, |
ade2e3a1 | 2622 | "ERROR Transfer event for disabled endpoint slot %u ep %u\n", |
b7f769ae | 2623 | slot_id, ep_index); |
b3368382 | 2624 | goto err_out; |
d0e96f5a SS |
2625 | } |
2626 | ||
ade2e3a1 MN |
2627 | /* Some transfer events don't always point to a trb, see xhci 4.17.4 */ |
2628 | if (!ep_ring) { | |
2629 | switch (trb_comp_code) { | |
2630 | case COMP_STALL_ERROR: | |
2631 | case COMP_USB_TRANSACTION_ERROR: | |
2632 | case COMP_INVALID_STREAM_TYPE_ERROR: | |
2633 | case COMP_INVALID_STREAM_ID_ERROR: | |
7c6c334e MN |
2634 | xhci_handle_halted_endpoint(xhci, ep, 0, NULL, |
2635 | EP_SOFT_RESET); | |
ade2e3a1 MN |
2636 | goto cleanup; |
2637 | case COMP_RING_UNDERRUN: | |
2638 | case COMP_RING_OVERRUN: | |
d9193efb | 2639 | case COMP_STOPPED_LENGTH_INVALID: |
ade2e3a1 MN |
2640 | goto cleanup; |
2641 | default: | |
2642 | xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n", | |
2643 | slot_id, ep_index); | |
2644 | goto err_out; | |
2645 | } | |
2646 | } | |
2647 | ||
c2d7b49f AX |
2648 | /* Count current td numbers if ep->skip is set */ |
2649 | if (ep->skip) { | |
2650 | list_for_each(tmp, &ep_ring->td_list) | |
2651 | td_num++; | |
2652 | } | |
2653 | ||
986a92d4 | 2654 | /* Look for common error cases */ |
66d1eebc | 2655 | switch (trb_comp_code) { |
b10de142 SS |
2656 | /* Skip codes that require special handling depending on |
2657 | * transfer type | |
2658 | */ | |
2659 | case COMP_SUCCESS: | |
1c11a172 | 2660 | if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) |
1530bbc6 | 2661 | break; |
7ff11162 MN |
2662 | if (xhci->quirks & XHCI_TRUST_TX_LENGTH || |
2663 | ep_ring->last_td_was_short) | |
0b7c105a | 2664 | trb_comp_code = COMP_SHORT_PACKET; |
1530bbc6 | 2665 | else |
8202ce2e | 2666 | xhci_warn_ratelimited(xhci, |
b7f769ae ZX |
2667 | "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n", |
2668 | slot_id, ep_index); | |
1d6903a6 | 2669 | break; |
0b7c105a | 2670 | case COMP_SHORT_PACKET: |
b10de142 | 2671 | break; |
b3368382 | 2672 | /* Completion codes for endpoint stopped state */ |
0b7c105a | 2673 | case COMP_STOPPED: |
b7f769ae ZX |
2674 | xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n", |
2675 | slot_id, ep_index); | |
ae636747 | 2676 | break; |
0b7c105a | 2677 | case COMP_STOPPED_LENGTH_INVALID: |
b7f769ae ZX |
2678 | xhci_dbg(xhci, |
2679 | "Stopped on No-op or Link TRB for slot %u ep %u\n", | |
2680 | slot_id, ep_index); | |
ae636747 | 2681 | break; |
0b7c105a | 2682 | case COMP_STOPPED_SHORT_PACKET: |
b7f769ae ZX |
2683 | xhci_dbg(xhci, |
2684 | "Stopped with short packet transfer detected for slot %u ep %u\n", | |
2685 | slot_id, ep_index); | |
40a3b775 | 2686 | break; |
b3368382 | 2687 | /* Completion codes for endpoint halted state */ |
0b7c105a | 2688 | case COMP_STALL_ERROR: |
b7f769ae ZX |
2689 | xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id, |
2690 | ep_index); | |
b10de142 SS |
2691 | status = -EPIPE; |
2692 | break; | |
0b7c105a | 2693 | case COMP_SPLIT_TRANSACTION_ERROR: |
76eac5d2 MN |
2694 | xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n", |
2695 | slot_id, ep_index); | |
2696 | status = -EPROTO; | |
2697 | break; | |
0b7c105a | 2698 | case COMP_USB_TRANSACTION_ERROR: |
b7f769ae ZX |
2699 | xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n", |
2700 | slot_id, ep_index); | |
b10de142 SS |
2701 | status = -EPROTO; |
2702 | break; | |
0b7c105a | 2703 | case COMP_BABBLE_DETECTED_ERROR: |
b7f769ae ZX |
2704 | xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n", |
2705 | slot_id, ep_index); | |
4a73143c SS |
2706 | status = -EOVERFLOW; |
2707 | break; | |
b3368382 MN |
2708 | /* Completion codes for endpoint error state */ |
2709 | case COMP_TRB_ERROR: | |
2710 | xhci_warn(xhci, | |
2711 | "WARN: TRB error for slot %u ep %u on endpoint\n", | |
2712 | slot_id, ep_index); | |
2713 | status = -EILSEQ; | |
2714 | break; | |
2715 | /* completion codes not indicating endpoint state change */ | |
0b7c105a | 2716 | case COMP_DATA_BUFFER_ERROR: |
b7f769ae ZX |
2717 | xhci_warn(xhci, |
2718 | "WARN: HC couldn't access mem fast enough for slot %u ep %u\n", | |
2719 | slot_id, ep_index); | |
b10de142 SS |
2720 | status = -ENOSR; |
2721 | break; | |
0b7c105a | 2722 | case COMP_BANDWIDTH_OVERRUN_ERROR: |
b7f769ae ZX |
2723 | xhci_warn(xhci, |
2724 | "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n", | |
2725 | slot_id, ep_index); | |
986a92d4 | 2726 | break; |
0b7c105a | 2727 | case COMP_ISOCH_BUFFER_OVERRUN: |
b7f769ae ZX |
2728 | xhci_warn(xhci, |
2729 | "WARN: buffer overrun event for slot %u ep %u on endpoint", | |
2730 | slot_id, ep_index); | |
986a92d4 | 2731 | break; |
0b7c105a | 2732 | case COMP_RING_UNDERRUN: |
986a92d4 AX |
2733 | /* |
2734 | * When the Isoch ring is empty, the xHC will generate | |
2735 | * a Ring Overrun Event for IN Isoch endpoint or Ring | |
2736 | * Underrun Event for OUT Isoch endpoint. | |
2737 | */ | |
2738 | xhci_dbg(xhci, "underrun event on endpoint\n"); | |
2739 | if (!list_empty(&ep_ring->td_list)) | |
2740 | xhci_dbg(xhci, "Underrun Event for slot %d ep %d " | |
2741 | "still with TDs queued?\n", | |
28ccd296 ME |
2742 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2743 | ep_index); | |
986a92d4 | 2744 | goto cleanup; |
0b7c105a | 2745 | case COMP_RING_OVERRUN: |
986a92d4 AX |
2746 | xhci_dbg(xhci, "overrun event on endpoint\n"); |
2747 | if (!list_empty(&ep_ring->td_list)) | |
2748 | xhci_dbg(xhci, "Overrun Event for slot %d ep %d " | |
2749 | "still with TDs queued?\n", | |
28ccd296 ME |
2750 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), |
2751 | ep_index); | |
986a92d4 | 2752 | goto cleanup; |
0b7c105a | 2753 | case COMP_MISSED_SERVICE_ERROR: |
d18240db AX |
2754 | /* |
2755 | * When encounter missed service error, one or more isoc tds | |
2756 | * may be missed by xHC. | |
2757 | * Set skip flag of the ep_ring; Complete the missed tds as | |
2758 | * short transfer when process the ep_ring next time. | |
2759 | */ | |
2760 | ep->skip = true; | |
b7f769ae ZX |
2761 | xhci_dbg(xhci, |
2762 | "Miss service interval error for slot %u ep %u, set skip flag\n", | |
2763 | slot_id, ep_index); | |
d18240db | 2764 | goto cleanup; |
0b7c105a | 2765 | case COMP_NO_PING_RESPONSE_ERROR: |
3b4739b8 | 2766 | ep->skip = true; |
b7f769ae ZX |
2767 | xhci_dbg(xhci, |
2768 | "No Ping response error for slot %u ep %u, Skip one Isoc TD\n", | |
2769 | slot_id, ep_index); | |
3b4739b8 | 2770 | goto cleanup; |
b3368382 MN |
2771 | |
2772 | case COMP_INCOMPATIBLE_DEVICE_ERROR: | |
2773 | /* needs disable slot command to recover */ | |
2774 | xhci_warn(xhci, | |
2775 | "WARN: detect an incompatible device for slot %u ep %u", | |
2776 | slot_id, ep_index); | |
2777 | status = -EPROTO; | |
2778 | break; | |
b10de142 | 2779 | default: |
b45b5069 | 2780 | if (xhci_is_vendor_info_code(xhci, trb_comp_code)) { |
5ad6a529 SS |
2781 | status = 0; |
2782 | break; | |
2783 | } | |
b7f769ae ZX |
2784 | xhci_warn(xhci, |
2785 | "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n", | |
2786 | trb_comp_code, slot_id, ep_index); | |
986a92d4 AX |
2787 | goto cleanup; |
2788 | } | |
2789 | ||
d18240db AX |
2790 | do { |
2791 | /* This TRB should be in the TD at the head of this ring's | |
2792 | * TD list. | |
2793 | */ | |
2794 | if (list_empty(&ep_ring->td_list)) { | |
a83d6755 | 2795 | /* |
e4ec40ec MN |
2796 | * Don't print wanings if it's due to a stopped endpoint |
2797 | * generating an extra completion event if the device | |
2798 | * was suspended. Or, a event for the last TRB of a | |
2799 | * short TD we already got a short event for. | |
2800 | * The short TD is already removed from the TD list. | |
a83d6755 | 2801 | */ |
e4ec40ec | 2802 | |
0b7c105a | 2803 | if (!(trb_comp_code == COMP_STOPPED || |
e4ec40ec MN |
2804 | trb_comp_code == COMP_STOPPED_LENGTH_INVALID || |
2805 | ep_ring->last_td_was_short)) { | |
a83d6755 SS |
2806 | xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n", |
2807 | TRB_TO_SLOT_ID(le32_to_cpu(event->flags)), | |
2808 | ep_index); | |
a83d6755 | 2809 | } |
d18240db AX |
2810 | if (ep->skip) { |
2811 | ep->skip = false; | |
b7f769ae ZX |
2812 | xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n", |
2813 | slot_id, ep_index); | |
d18240db | 2814 | } |
93ceaa80 MN |
2815 | if (trb_comp_code == COMP_STALL_ERROR || |
2816 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, | |
2817 | trb_comp_code)) { | |
7c6c334e MN |
2818 | xhci_handle_halted_endpoint(xhci, ep, |
2819 | ep_ring->stream_id, | |
2820 | NULL, | |
2821 | EP_HARD_RESET); | |
93ceaa80 | 2822 | } |
d18240db AX |
2823 | goto cleanup; |
2824 | } | |
986a92d4 | 2825 | |
c2d7b49f AX |
2826 | /* We've skipped all the TDs on the ep ring when ep->skip set */ |
2827 | if (ep->skip && td_num == 0) { | |
2828 | ep->skip = false; | |
b7f769ae ZX |
2829 | xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n", |
2830 | slot_id, ep_index); | |
c2d7b49f AX |
2831 | goto cleanup; |
2832 | } | |
2833 | ||
04861f83 FB |
2834 | td = list_first_entry(&ep_ring->td_list, struct xhci_td, |
2835 | td_list); | |
c2d7b49f AX |
2836 | if (ep->skip) |
2837 | td_num--; | |
926008c9 | 2838 | |
d18240db | 2839 | /* Is this a TRB in the currently executing TD? */ |
f97c08ae MN |
2840 | ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue, |
2841 | td->last_trb, ep_trb_dma, false); | |
e1cf486d AH |
2842 | |
2843 | /* | |
2844 | * Skip the Force Stopped Event. The event_trb(event_dma) of FSE | |
2845 | * is not in the current TD pointed by ep_ring->dequeue because | |
2846 | * that the hardware dequeue pointer still at the previous TRB | |
2847 | * of the current TD. The previous TRB maybe a Link TD or the | |
2848 | * last TRB of the previous TD. The command completion handle | |
2849 | * will take care the rest. | |
2850 | */ | |
0b7c105a FB |
2851 | if (!ep_seg && (trb_comp_code == COMP_STOPPED || |
2852 | trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) { | |
e1cf486d AH |
2853 | goto cleanup; |
2854 | } | |
2855 | ||
f97c08ae | 2856 | if (!ep_seg) { |
926008c9 DT |
2857 | if (!ep->skip || |
2858 | !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) { | |
ad808333 SS |
2859 | /* Some host controllers give a spurious |
2860 | * successful event after a short transfer. | |
2861 | * Ignore it. | |
2862 | */ | |
ddba5cd0 | 2863 | if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && |
ad808333 SS |
2864 | ep_ring->last_td_was_short) { |
2865 | ep_ring->last_td_was_short = false; | |
ad808333 SS |
2866 | goto cleanup; |
2867 | } | |
926008c9 DT |
2868 | /* HC is busted, give up! */ |
2869 | xhci_err(xhci, | |
2870 | "ERROR Transfer event TRB DMA ptr not " | |
cffb9be8 HG |
2871 | "part of current TD ep_index %d " |
2872 | "comp_code %u\n", ep_index, | |
2873 | trb_comp_code); | |
2874 | trb_in_td(xhci, ep_ring->deq_seg, | |
2875 | ep_ring->dequeue, td->last_trb, | |
f97c08ae | 2876 | ep_trb_dma, true); |
926008c9 DT |
2877 | return -ESHUTDOWN; |
2878 | } | |
2879 | ||
a6ccd1fd | 2880 | skip_isoc_td(xhci, td, ep, status); |
926008c9 DT |
2881 | goto cleanup; |
2882 | } | |
0b7c105a | 2883 | if (trb_comp_code == COMP_SHORT_PACKET) |
ad808333 SS |
2884 | ep_ring->last_td_was_short = true; |
2885 | else | |
2886 | ep_ring->last_td_was_short = false; | |
926008c9 DT |
2887 | |
2888 | if (ep->skip) { | |
b7f769ae ZX |
2889 | xhci_dbg(xhci, |
2890 | "Found td. Clear skip flag for slot %u ep %u.\n", | |
2891 | slot_id, ep_index); | |
d18240db AX |
2892 | ep->skip = false; |
2893 | } | |
678539cf | 2894 | |
f97c08ae MN |
2895 | ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) / |
2896 | sizeof(*ep_trb)]; | |
a37c3f76 FB |
2897 | |
2898 | trace_xhci_handle_transfer(ep_ring, | |
2899 | (struct xhci_generic_trb *) ep_trb); | |
2900 | ||
926008c9 | 2901 | /* |
810a624b LB |
2902 | * No-op TRB could trigger interrupts in a case where |
2903 | * a URB was killed and a STALL_ERROR happens right | |
2904 | * after the endpoint ring stopped. Reset the halted | |
2905 | * endpoint. Otherwise, the endpoint remains stalled | |
2906 | * indefinitely. | |
926008c9 | 2907 | */ |
a6ccd1fd | 2908 | |
f97c08ae | 2909 | if (trb_is_noop(ep_trb)) { |
810a624b LB |
2910 | if (trb_comp_code == COMP_STALL_ERROR || |
2911 | xhci_requires_manual_halt_cleanup(xhci, ep_ctx, | |
2912 | trb_comp_code)) | |
7c6c334e MN |
2913 | xhci_handle_halted_endpoint(xhci, ep, |
2914 | ep_ring->stream_id, | |
2915 | td, EP_HARD_RESET); | |
926008c9 | 2916 | goto cleanup; |
d18240db | 2917 | } |
4422da61 | 2918 | |
a6ccd1fd MN |
2919 | td->status = status; |
2920 | ||
0c03d89d | 2921 | /* update the urb's actual_length and give back to the core */ |
d18240db | 2922 | if (usb_endpoint_xfer_control(&td->urb->ep->desc)) |
e9fcb077 | 2923 | process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event); |
04e51901 | 2924 | else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc)) |
e9fcb077 | 2925 | process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event); |
d18240db | 2926 | else |
e9fcb077 | 2927 | process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event); |
d18240db | 2928 | cleanup: |
3b4739b8 | 2929 | handling_skipped_tds = ep->skip && |
0b7c105a FB |
2930 | trb_comp_code != COMP_MISSED_SERVICE_ERROR && |
2931 | trb_comp_code != COMP_NO_PING_RESPONSE_ERROR; | |
3b4739b8 | 2932 | |
d18240db | 2933 | /* |
3b4739b8 MN |
2934 | * Do not update event ring dequeue pointer if we're in a loop |
2935 | * processing missed tds. | |
d18240db | 2936 | */ |
3b4739b8 | 2937 | if (!handling_skipped_tds) |
3b72fca0 | 2938 | inc_deq(xhci, xhci->event_ring); |
d18240db | 2939 | |
d18240db AX |
2940 | /* |
2941 | * If ep->skip is set, it means there are missed tds on the | |
2942 | * endpoint ring need to take care of. | |
2943 | * Process them as short transfer until reach the td pointed by | |
2944 | * the event. | |
2945 | */ | |
3b4739b8 | 2946 | } while (handling_skipped_tds); |
d18240db | 2947 | |
d0e96f5a | 2948 | return 0; |
b3368382 MN |
2949 | |
2950 | err_out: | |
2951 | xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n", | |
2952 | (unsigned long long) xhci_trb_virt_to_dma( | |
2953 | xhci->event_ring->deq_seg, | |
2954 | xhci->event_ring->dequeue), | |
2955 | lower_32_bits(le64_to_cpu(event->buffer)), | |
2956 | upper_32_bits(le64_to_cpu(event->buffer)), | |
2957 | le32_to_cpu(event->transfer_len), | |
2958 | le32_to_cpu(event->flags)); | |
2959 | return -ENODEV; | |
d0e96f5a SS |
2960 | } |
2961 | ||
0f2a7930 SS |
2962 | /* |
2963 | * This function handles all OS-owned events on the event ring. It may drop | |
2964 | * xhci->lock between event processing (e.g. to pass up port status changes). | |
9dee9a21 ME |
2965 | * Returns >0 for "possibly more events to process" (caller should call again), |
2966 | * otherwise 0 if done. In future, <0 returns should indicate error code. | |
0f2a7930 | 2967 | */ |
9dee9a21 | 2968 | static int xhci_handle_event(struct xhci_hcd *xhci) |
7f84eef0 SS |
2969 | { |
2970 | union xhci_trb *event; | |
0f2a7930 | 2971 | int update_ptrs = 1; |
0353810a | 2972 | u32 trb_type; |
d0e96f5a | 2973 | int ret; |
7f84eef0 | 2974 | |
f4c8f03c | 2975 | /* Event ring hasn't been allocated yet. */ |
7f84eef0 | 2976 | if (!xhci->event_ring || !xhci->event_ring->dequeue) { |
f4c8f03c LB |
2977 | xhci_err(xhci, "ERROR event ring not ready\n"); |
2978 | return -ENOMEM; | |
7f84eef0 SS |
2979 | } |
2980 | ||
2981 | event = xhci->event_ring->dequeue; | |
2982 | /* Does the HC or OS own the TRB? */ | |
28ccd296 | 2983 | if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) != |
f4c8f03c | 2984 | xhci->event_ring->cycle_state) |
9dee9a21 | 2985 | return 0; |
7f84eef0 | 2986 | |
a37c3f76 FB |
2987 | trace_xhci_handle_event(xhci->event_ring, &event->generic); |
2988 | ||
92a3da41 ME |
2989 | /* |
2990 | * Barrier between reading the TRB_CYCLE (valid) flag above and any | |
2991 | * speculative reads of the event's flags/data below. | |
2992 | */ | |
2993 | rmb(); | |
0353810a | 2994 | trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags)); |
0f2a7930 | 2995 | /* FIXME: Handle more event types. */ |
0353810a MN |
2996 | |
2997 | switch (trb_type) { | |
2998 | case TRB_COMPLETION: | |
7f84eef0 SS |
2999 | handle_cmd_completion(xhci, &event->event_cmd); |
3000 | break; | |
0353810a | 3001 | case TRB_PORT_STATUS: |
0f2a7930 SS |
3002 | handle_port_status(xhci, event); |
3003 | update_ptrs = 0; | |
3004 | break; | |
0353810a | 3005 | case TRB_TRANSFER: |
d0e96f5a | 3006 | ret = handle_tx_event(xhci, &event->trans_event); |
f4c8f03c | 3007 | if (ret >= 0) |
d0e96f5a SS |
3008 | update_ptrs = 0; |
3009 | break; | |
0353810a | 3010 | case TRB_DEV_NOTE: |
623bef9e SS |
3011 | handle_device_notification(xhci, event); |
3012 | break; | |
7f84eef0 | 3013 | default: |
0353810a MN |
3014 | if (trb_type >= TRB_VENDOR_DEFINED_LOW) |
3015 | handle_vendor_event(xhci, event, trb_type); | |
0238634d | 3016 | else |
0353810a | 3017 | xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type); |
7f84eef0 | 3018 | } |
6f5165cf SS |
3019 | /* Any of the above functions may drop and re-acquire the lock, so check |
3020 | * to make sure a watchdog timer didn't mark the host as non-responsive. | |
3021 | */ | |
3022 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
3023 | xhci_dbg(xhci, "xHCI host dying, returning from " | |
3024 | "event handler.\n"); | |
9dee9a21 | 3025 | return 0; |
6f5165cf | 3026 | } |
7f84eef0 | 3027 | |
c06d68b8 SS |
3028 | if (update_ptrs) |
3029 | /* Update SW event ring dequeue pointer */ | |
3b72fca0 | 3030 | inc_deq(xhci, xhci->event_ring); |
c06d68b8 | 3031 | |
9dee9a21 ME |
3032 | /* Are there more items on the event ring? Caller will call us again to |
3033 | * check. | |
3034 | */ | |
3035 | return 1; | |
7f84eef0 | 3036 | } |
9032cd52 | 3037 | |
dc0ffbea PC |
3038 | /* |
3039 | * Update Event Ring Dequeue Pointer: | |
3040 | * - When all events have finished | |
3041 | * - To avoid "Event Ring Full Error" condition | |
3042 | */ | |
3043 | static void xhci_update_erst_dequeue(struct xhci_hcd *xhci, | |
3044 | union xhci_trb *event_ring_deq) | |
3045 | { | |
3046 | u64 temp_64; | |
3047 | dma_addr_t deq; | |
3048 | ||
3049 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | |
3050 | /* If necessary, update the HW's version of the event ring deq ptr. */ | |
3051 | if (event_ring_deq != xhci->event_ring->dequeue) { | |
3052 | deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, | |
3053 | xhci->event_ring->dequeue); | |
3054 | if (deq == 0) | |
3055 | xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n"); | |
3056 | /* | |
3057 | * Per 4.9.4, Software writes to the ERDP register shall | |
3058 | * always advance the Event Ring Dequeue Pointer value. | |
3059 | */ | |
3060 | if ((temp_64 & (u64) ~ERST_PTR_MASK) == | |
3061 | ((u64) deq & (u64) ~ERST_PTR_MASK)) | |
3062 | return; | |
3063 | ||
3064 | /* Update HC event ring dequeue pointer */ | |
3065 | temp_64 &= ERST_PTR_MASK; | |
3066 | temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK); | |
3067 | } | |
3068 | ||
3069 | /* Clear the event handler busy flag (RW1C) */ | |
3070 | temp_64 |= ERST_EHB; | |
3071 | xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue); | |
3072 | } | |
3073 | ||
9032cd52 SS |
3074 | /* |
3075 | * xHCI spec says we can get an interrupt, and if the HC has an error condition, | |
3076 | * we might get bad data out of the event ring. Section 4.10.2.7 has a list of | |
3077 | * indicators of an event TRB error, but we check the status *first* to be safe. | |
3078 | */ | |
3079 | irqreturn_t xhci_irq(struct usb_hcd *hcd) | |
3080 | { | |
3081 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
c06d68b8 | 3082 | union xhci_trb *event_ring_deq; |
76a35293 | 3083 | irqreturn_t ret = IRQ_NONE; |
76a35293 FB |
3084 | u64 temp_64; |
3085 | u32 status; | |
dc0ffbea | 3086 | int event_loop = 0; |
9032cd52 | 3087 | |
5e712172 | 3088 | spin_lock(&xhci->lock); |
9032cd52 | 3089 | /* Check if the xHC generated the interrupt, or the irq is shared */ |
b0ba9720 | 3090 | status = readl(&xhci->op_regs->status); |
d9f11ba9 MN |
3091 | if (status == ~(u32)0) { |
3092 | xhci_hc_died(xhci); | |
76a35293 FB |
3093 | ret = IRQ_HANDLED; |
3094 | goto out; | |
9032cd52 | 3095 | } |
76a35293 FB |
3096 | |
3097 | if (!(status & STS_EINT)) | |
3098 | goto out; | |
3099 | ||
27e0dd4d | 3100 | if (status & STS_FATAL) { |
9032cd52 SS |
3101 | xhci_warn(xhci, "WARNING: Host System Error\n"); |
3102 | xhci_halt(xhci); | |
76a35293 FB |
3103 | ret = IRQ_HANDLED; |
3104 | goto out; | |
9032cd52 SS |
3105 | } |
3106 | ||
bda53145 SS |
3107 | /* |
3108 | * Clear the op reg interrupt status first, | |
3109 | * so we can receive interrupts from other MSI-X interrupters. | |
3110 | * Write 1 to clear the interrupt status. | |
3111 | */ | |
27e0dd4d | 3112 | status |= STS_EINT; |
204b7793 | 3113 | writel(status, &xhci->op_regs->status); |
bda53145 | 3114 | |
6a29beef | 3115 | if (!hcd->msi_enabled) { |
c21599a3 | 3116 | u32 irq_pending; |
b0ba9720 | 3117 | irq_pending = readl(&xhci->ir_set->irq_pending); |
4e833c0b | 3118 | irq_pending |= IMAN_IP; |
204b7793 | 3119 | writel(irq_pending, &xhci->ir_set->irq_pending); |
c21599a3 | 3120 | } |
bda53145 | 3121 | |
27a41a83 GKB |
3122 | if (xhci->xhc_state & XHCI_STATE_DYING || |
3123 | xhci->xhc_state & XHCI_STATE_HALTED) { | |
bda53145 SS |
3124 | xhci_dbg(xhci, "xHCI dying, ignoring interrupt. " |
3125 | "Shouldn't IRQs be disabled?\n"); | |
c06d68b8 SS |
3126 | /* Clear the event handler busy flag (RW1C); |
3127 | * the event ring should be empty. | |
bda53145 | 3128 | */ |
f7b2e403 | 3129 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
477632df SS |
3130 | xhci_write_64(xhci, temp_64 | ERST_EHB, |
3131 | &xhci->ir_set->erst_dequeue); | |
76a35293 FB |
3132 | ret = IRQ_HANDLED; |
3133 | goto out; | |
c06d68b8 SS |
3134 | } |
3135 | ||
3136 | event_ring_deq = xhci->event_ring->dequeue; | |
3137 | /* FIXME this should be a delayed service routine | |
3138 | * that clears the EHB. | |
3139 | */ | |
dc0ffbea PC |
3140 | while (xhci_handle_event(xhci) > 0) { |
3141 | if (event_loop++ < TRBS_PER_SEGMENT / 2) | |
3142 | continue; | |
3143 | xhci_update_erst_dequeue(xhci, event_ring_deq); | |
90d551a5 MN |
3144 | |
3145 | /* ring is half-full, force isoc trbs to interrupt more often */ | |
3146 | if (xhci->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN) | |
3147 | xhci->isoc_bei_interval = xhci->isoc_bei_interval / 2; | |
3148 | ||
dc0ffbea | 3149 | event_loop = 0; |
c06d68b8 SS |
3150 | } |
3151 | ||
dc0ffbea | 3152 | xhci_update_erst_dequeue(xhci, event_ring_deq); |
76a35293 | 3153 | ret = IRQ_HANDLED; |
c06d68b8 | 3154 | |
76a35293 | 3155 | out: |
5e712172 | 3156 | spin_unlock(&xhci->lock); |
9032cd52 | 3157 | |
76a35293 | 3158 | return ret; |
9032cd52 SS |
3159 | } |
3160 | ||
851ec164 | 3161 | irqreturn_t xhci_msi_irq(int irq, void *hcd) |
9032cd52 | 3162 | { |
968b822c | 3163 | return xhci_irq(hcd); |
9032cd52 | 3164 | } |
7f84eef0 | 3165 | |
d0e96f5a SS |
3166 | /**** Endpoint Ring Operations ****/ |
3167 | ||
7f84eef0 SS |
3168 | /* |
3169 | * Generic function for queueing a TRB on a ring. | |
3170 | * The caller must have checked to make sure there's room on the ring. | |
6cc30d85 SS |
3171 | * |
3172 | * @more_trbs_coming: Will you enqueue more TRBs before calling | |
3173 | * prepare_transfer()? | |
7f84eef0 SS |
3174 | */ |
3175 | static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring, | |
3b72fca0 | 3176 | bool more_trbs_coming, |
7f84eef0 SS |
3177 | u32 field1, u32 field2, u32 field3, u32 field4) |
3178 | { | |
3179 | struct xhci_generic_trb *trb; | |
3180 | ||
3181 | trb = &ring->enqueue->generic; | |
28ccd296 ME |
3182 | trb->field[0] = cpu_to_le32(field1); |
3183 | trb->field[1] = cpu_to_le32(field2); | |
3184 | trb->field[2] = cpu_to_le32(field3); | |
576667ba MN |
3185 | /* make sure TRB is fully written before giving it to the controller */ |
3186 | wmb(); | |
28ccd296 | 3187 | trb->field[3] = cpu_to_le32(field4); |
a37c3f76 FB |
3188 | |
3189 | trace_xhci_queue_trb(ring, trb); | |
3190 | ||
3b72fca0 | 3191 | inc_enq(xhci, ring, more_trbs_coming); |
7f84eef0 SS |
3192 | } |
3193 | ||
d0e96f5a SS |
3194 | /* |
3195 | * Does various checks on the endpoint ring, and makes it ready to queue num_trbs. | |
3196 | * FIXME allocate segments if the ring is full. | |
3197 | */ | |
3198 | static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring, | |
3b72fca0 | 3199 | u32 ep_state, unsigned int num_trbs, gfp_t mem_flags) |
d0e96f5a | 3200 | { |
8dfec614 | 3201 | unsigned int num_trbs_needed; |
04d21f72 | 3202 | unsigned int link_trb_count = 0; |
8dfec614 | 3203 | |
d0e96f5a | 3204 | /* Make sure the endpoint has been added to xHC schedule */ |
d0e96f5a SS |
3205 | switch (ep_state) { |
3206 | case EP_STATE_DISABLED: | |
3207 | /* | |
3208 | * USB core changed config/interfaces without notifying us, | |
3209 | * or hardware is reporting the wrong state. | |
3210 | */ | |
3211 | xhci_warn(xhci, "WARN urb submitted to disabled ep\n"); | |
3212 | return -ENOENT; | |
d0e96f5a | 3213 | case EP_STATE_ERROR: |
c92bcfa7 | 3214 | xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n"); |
d0e96f5a SS |
3215 | /* FIXME event handling code for error needs to clear it */ |
3216 | /* XXX not sure if this should be -ENOENT or not */ | |
3217 | return -EINVAL; | |
c92bcfa7 SS |
3218 | case EP_STATE_HALTED: |
3219 | xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n"); | |
1d6903a6 | 3220 | break; |
d0e96f5a SS |
3221 | case EP_STATE_STOPPED: |
3222 | case EP_STATE_RUNNING: | |
3223 | break; | |
3224 | default: | |
3225 | xhci_err(xhci, "ERROR unknown endpoint state for ep\n"); | |
3226 | /* | |
3227 | * FIXME issue Configure Endpoint command to try to get the HC | |
3228 | * back into a known state. | |
3229 | */ | |
3230 | return -EINVAL; | |
3231 | } | |
8dfec614 AX |
3232 | |
3233 | while (1) { | |
3d4b81ed SS |
3234 | if (room_on_ring(xhci, ep_ring, num_trbs)) |
3235 | break; | |
8dfec614 AX |
3236 | |
3237 | if (ep_ring == xhci->cmd_ring) { | |
3238 | xhci_err(xhci, "Do not support expand command ring\n"); | |
3239 | return -ENOMEM; | |
3240 | } | |
3241 | ||
68ffb011 XR |
3242 | xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion, |
3243 | "ERROR no room on ep ring, try ring expansion"); | |
8dfec614 AX |
3244 | num_trbs_needed = num_trbs - ep_ring->num_trbs_free; |
3245 | if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed, | |
3246 | mem_flags)) { | |
3247 | xhci_err(xhci, "Ring expansion failed\n"); | |
3248 | return -ENOMEM; | |
3249 | } | |
261fa12b | 3250 | } |
6c12db90 | 3251 | |
d0c77d84 MN |
3252 | while (trb_is_link(ep_ring->enqueue)) { |
3253 | /* If we're not dealing with 0.95 hardware or isoc rings | |
3254 | * on AMD 0.96 host, clear the chain bit. | |
3255 | */ | |
3256 | if (!xhci_link_trb_quirk(xhci) && | |
3257 | !(ep_ring->type == TYPE_ISOC && | |
3258 | (xhci->quirks & XHCI_AMD_0x96_HOST))) | |
3259 | ep_ring->enqueue->link.control &= | |
3260 | cpu_to_le32(~TRB_CHAIN); | |
3261 | else | |
3262 | ep_ring->enqueue->link.control |= | |
3263 | cpu_to_le32(TRB_CHAIN); | |
6c12db90 | 3264 | |
d0c77d84 MN |
3265 | wmb(); |
3266 | ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE); | |
6c12db90 | 3267 | |
d0c77d84 MN |
3268 | /* Toggle the cycle bit after the last ring segment. */ |
3269 | if (link_trb_toggles_cycle(ep_ring->enqueue)) | |
3270 | ep_ring->cycle_state ^= 1; | |
6c12db90 | 3271 | |
d0c77d84 MN |
3272 | ep_ring->enq_seg = ep_ring->enq_seg->next; |
3273 | ep_ring->enqueue = ep_ring->enq_seg->trbs; | |
04d21f72 MN |
3274 | |
3275 | /* prevent infinite loop if all first trbs are link trbs */ | |
3276 | if (link_trb_count++ > ep_ring->num_segs) { | |
3277 | xhci_warn(xhci, "Ring is an endless link TRB loop\n"); | |
3278 | return -EINVAL; | |
3279 | } | |
6c12db90 | 3280 | } |
c716e8a5 MN |
3281 | |
3282 | if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) { | |
3283 | xhci_warn(xhci, "Missing link TRB at end of ring segment\n"); | |
3284 | return -EINVAL; | |
3285 | } | |
3286 | ||
d0e96f5a SS |
3287 | return 0; |
3288 | } | |
3289 | ||
23e3be11 | 3290 | static int prepare_transfer(struct xhci_hcd *xhci, |
d0e96f5a SS |
3291 | struct xhci_virt_device *xdev, |
3292 | unsigned int ep_index, | |
e9df17eb | 3293 | unsigned int stream_id, |
d0e96f5a SS |
3294 | unsigned int num_trbs, |
3295 | struct urb *urb, | |
8e51adcc | 3296 | unsigned int td_index, |
d0e96f5a SS |
3297 | gfp_t mem_flags) |
3298 | { | |
3299 | int ret; | |
8e51adcc AX |
3300 | struct urb_priv *urb_priv; |
3301 | struct xhci_td *td; | |
e9df17eb | 3302 | struct xhci_ring *ep_ring; |
d115b048 | 3303 | struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); |
e9df17eb | 3304 | |
c089cada MN |
3305 | ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index, |
3306 | stream_id); | |
e9df17eb SS |
3307 | if (!ep_ring) { |
3308 | xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n", | |
3309 | stream_id); | |
3310 | return -EINVAL; | |
3311 | } | |
3312 | ||
5071e6b2 | 3313 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 3314 | num_trbs, mem_flags); |
d0e96f5a SS |
3315 | if (ret) |
3316 | return ret; | |
d0e96f5a | 3317 | |
8e51adcc | 3318 | urb_priv = urb->hcpriv; |
7e64b037 | 3319 | td = &urb_priv->td[td_index]; |
8e51adcc AX |
3320 | |
3321 | INIT_LIST_HEAD(&td->td_list); | |
3322 | INIT_LIST_HEAD(&td->cancelled_td_list); | |
3323 | ||
3324 | if (td_index == 0) { | |
214f76f7 | 3325 | ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb); |
d13565c1 | 3326 | if (unlikely(ret)) |
8e51adcc | 3327 | return ret; |
d0e96f5a SS |
3328 | } |
3329 | ||
8e51adcc | 3330 | td->urb = urb; |
d0e96f5a | 3331 | /* Add this TD to the tail of the endpoint ring's TD list */ |
8e51adcc AX |
3332 | list_add_tail(&td->td_list, &ep_ring->td_list); |
3333 | td->start_seg = ep_ring->enq_seg; | |
3334 | td->first_trb = ep_ring->enqueue; | |
3335 | ||
d0e96f5a SS |
3336 | return 0; |
3337 | } | |
3338 | ||
67d2ea9f | 3339 | unsigned int count_trbs(u64 addr, u64 len) |
d2510342 AI |
3340 | { |
3341 | unsigned int num_trbs; | |
3342 | ||
3343 | num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)), | |
3344 | TRB_MAX_BUFF_SIZE); | |
3345 | if (num_trbs == 0) | |
3346 | num_trbs++; | |
3347 | ||
3348 | return num_trbs; | |
3349 | } | |
3350 | ||
3351 | static inline unsigned int count_trbs_needed(struct urb *urb) | |
3352 | { | |
3353 | return count_trbs(urb->transfer_dma, urb->transfer_buffer_length); | |
3354 | } | |
3355 | ||
3356 | static unsigned int count_sg_trbs_needed(struct urb *urb) | |
8a96c052 | 3357 | { |
8a96c052 | 3358 | struct scatterlist *sg; |
d2510342 | 3359 | unsigned int i, len, full_len, num_trbs = 0; |
8a96c052 | 3360 | |
d2510342 | 3361 | full_len = urb->transfer_buffer_length; |
8a96c052 | 3362 | |
d2510342 AI |
3363 | for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) { |
3364 | len = sg_dma_len(sg); | |
3365 | num_trbs += count_trbs(sg_dma_address(sg), len); | |
3366 | len = min_t(unsigned int, len, full_len); | |
3367 | full_len -= len; | |
3368 | if (full_len == 0) | |
8a96c052 SS |
3369 | break; |
3370 | } | |
d2510342 | 3371 | |
8a96c052 SS |
3372 | return num_trbs; |
3373 | } | |
3374 | ||
d2510342 AI |
3375 | static unsigned int count_isoc_trbs_needed(struct urb *urb, int i) |
3376 | { | |
3377 | u64 addr, len; | |
3378 | ||
3379 | addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset); | |
3380 | len = urb->iso_frame_desc[i].length; | |
3381 | ||
3382 | return count_trbs(addr, len); | |
3383 | } | |
3384 | ||
3385 | static void check_trb_math(struct urb *urb, int running_total) | |
8a96c052 | 3386 | { |
d2510342 | 3387 | if (unlikely(running_total != urb->transfer_buffer_length)) |
a2490187 | 3388 | dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, " |
8a96c052 SS |
3389 | "queued %#x (%d), asked for %#x (%d)\n", |
3390 | __func__, | |
3391 | urb->ep->desc.bEndpointAddress, | |
3392 | running_total, running_total, | |
3393 | urb->transfer_buffer_length, | |
3394 | urb->transfer_buffer_length); | |
3395 | } | |
3396 | ||
23e3be11 | 3397 | static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id, |
e9df17eb | 3398 | unsigned int ep_index, unsigned int stream_id, int start_cycle, |
e1eab2e0 | 3399 | struct xhci_generic_trb *start_trb) |
8a96c052 | 3400 | { |
8a96c052 SS |
3401 | /* |
3402 | * Pass all the TRBs to the hardware at once and make sure this write | |
3403 | * isn't reordered. | |
3404 | */ | |
3405 | wmb(); | |
50f7b52a | 3406 | if (start_cycle) |
28ccd296 | 3407 | start_trb->field[3] |= cpu_to_le32(start_cycle); |
50f7b52a | 3408 | else |
28ccd296 | 3409 | start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); |
be88fe4f | 3410 | xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id); |
8a96c052 SS |
3411 | } |
3412 | ||
78140156 AI |
3413 | static void check_interval(struct xhci_hcd *xhci, struct urb *urb, |
3414 | struct xhci_ep_ctx *ep_ctx) | |
624defa1 | 3415 | { |
624defa1 SS |
3416 | int xhci_interval; |
3417 | int ep_interval; | |
3418 | ||
28ccd296 | 3419 | xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info)); |
624defa1 | 3420 | ep_interval = urb->interval; |
78140156 | 3421 | |
624defa1 SS |
3422 | /* Convert to microframes */ |
3423 | if (urb->dev->speed == USB_SPEED_LOW || | |
3424 | urb->dev->speed == USB_SPEED_FULL) | |
3425 | ep_interval *= 8; | |
78140156 | 3426 | |
624defa1 SS |
3427 | /* FIXME change this to a warning and a suggestion to use the new API |
3428 | * to set the polling interval (once the API is added). | |
3429 | */ | |
3430 | if (xhci_interval != ep_interval) { | |
0730d52a DK |
3431 | dev_dbg_ratelimited(&urb->dev->dev, |
3432 | "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n", | |
3433 | ep_interval, ep_interval == 1 ? "" : "s", | |
3434 | xhci_interval, xhci_interval == 1 ? "" : "s"); | |
624defa1 SS |
3435 | urb->interval = xhci_interval; |
3436 | /* Convert back to frames for LS/FS devices */ | |
3437 | if (urb->dev->speed == USB_SPEED_LOW || | |
3438 | urb->dev->speed == USB_SPEED_FULL) | |
3439 | urb->interval /= 8; | |
3440 | } | |
78140156 AI |
3441 | } |
3442 | ||
3443 | /* | |
3444 | * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt | |
3445 | * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD | |
3446 | * (comprised of sg list entries) can take several service intervals to | |
3447 | * transmit. | |
3448 | */ | |
3449 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
3450 | struct urb *urb, int slot_id, unsigned int ep_index) | |
3451 | { | |
3452 | struct xhci_ep_ctx *ep_ctx; | |
3453 | ||
3454 | ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index); | |
3455 | check_interval(xhci, urb, ep_ctx); | |
3456 | ||
3fc8206d | 3457 | return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index); |
624defa1 SS |
3458 | } |
3459 | ||
4da6e6f2 | 3460 | /* |
4525c0a1 SS |
3461 | * For xHCI 1.0 host controllers, TD size is the number of max packet sized |
3462 | * packets remaining in the TD (*not* including this TRB). | |
4da6e6f2 SS |
3463 | * |
3464 | * Total TD packet count = total_packet_count = | |
4525c0a1 | 3465 | * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) |
4da6e6f2 SS |
3466 | * |
3467 | * Packets transferred up to and including this TRB = packets_transferred = | |
3468 | * rounddown(total bytes transferred including this TRB / wMaxPacketSize) | |
3469 | * | |
3470 | * TD size = total_packet_count - packets_transferred | |
3471 | * | |
c840d6ce MN |
3472 | * For xHCI 0.96 and older, TD size field should be the remaining bytes |
3473 | * including this TRB, right shifted by 10 | |
3474 | * | |
3475 | * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. | |
3476 | * This is taken care of in the TRB_TD_SIZE() macro | |
3477 | * | |
4525c0a1 | 3478 | * The last TRB in a TD must have the TD size set to zero. |
4da6e6f2 | 3479 | */ |
c840d6ce MN |
3480 | static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, |
3481 | int trb_buff_len, unsigned int td_total_len, | |
124c3937 | 3482 | struct urb *urb, bool more_trbs_coming) |
4da6e6f2 | 3483 | { |
c840d6ce MN |
3484 | u32 maxp, total_packet_count; |
3485 | ||
72b663a9 | 3486 | /* MTK xHCI 0.96 contains some features from 1.0 */ |
0cbd4b34 | 3487 | if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST)) |
c840d6ce MN |
3488 | return ((td_total_len - transferred) >> 10); |
3489 | ||
48df4a6f | 3490 | /* One TRB with a zero-length data packet. */ |
124c3937 | 3491 | if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || |
c840d6ce | 3492 | trb_buff_len == td_total_len) |
48df4a6f SS |
3493 | return 0; |
3494 | ||
72b663a9 CY |
3495 | /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */ |
3496 | if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100)) | |
0cbd4b34 CY |
3497 | trb_buff_len = 0; |
3498 | ||
734d3ddd | 3499 | maxp = usb_endpoint_maxp(&urb->ep->desc); |
0cbd4b34 CY |
3500 | total_packet_count = DIV_ROUND_UP(td_total_len, maxp); |
3501 | ||
c840d6ce MN |
3502 | /* Queueing functions don't count the current TRB into transferred */ |
3503 | return (total_packet_count - ((transferred + trb_buff_len) / maxp)); | |
4da6e6f2 SS |
3504 | } |
3505 | ||
f9c589e1 | 3506 | |
474ed23a | 3507 | static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, |
f9c589e1 | 3508 | u32 *trb_buff_len, struct xhci_segment *seg) |
474ed23a | 3509 | { |
f9c589e1 | 3510 | struct device *dev = xhci_to_hcd(xhci)->self.controller; |
474ed23a MN |
3511 | unsigned int unalign; |
3512 | unsigned int max_pkt; | |
f9c589e1 | 3513 | u32 new_buff_len; |
597c56e3 | 3514 | size_t len; |
474ed23a | 3515 | |
734d3ddd | 3516 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
474ed23a MN |
3517 | unalign = (enqd_len + *trb_buff_len) % max_pkt; |
3518 | ||
3519 | /* we got lucky, last normal TRB data on segment is packet aligned */ | |
3520 | if (unalign == 0) | |
3521 | return 0; | |
3522 | ||
f9c589e1 MN |
3523 | xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n", |
3524 | unalign, *trb_buff_len); | |
3525 | ||
474ed23a MN |
3526 | /* is the last nornal TRB alignable by splitting it */ |
3527 | if (*trb_buff_len > unalign) { | |
3528 | *trb_buff_len -= unalign; | |
f9c589e1 | 3529 | xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len); |
474ed23a MN |
3530 | return 0; |
3531 | } | |
f9c589e1 MN |
3532 | |
3533 | /* | |
3534 | * We want enqd_len + trb_buff_len to sum up to a number aligned to | |
3535 | * number which is divisible by the endpoint's wMaxPacketSize. IOW: | |
3536 | * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0. | |
3537 | */ | |
3538 | new_buff_len = max_pkt - (enqd_len % max_pkt); | |
3539 | ||
3540 | if (new_buff_len > (urb->transfer_buffer_length - enqd_len)) | |
3541 | new_buff_len = (urb->transfer_buffer_length - enqd_len); | |
3542 | ||
3543 | /* create a max max_pkt sized bounce buffer pointed to by last trb */ | |
3544 | if (usb_urb_dir_out(urb)) { | |
d4a61063 MN |
3545 | if (urb->num_sgs) { |
3546 | len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs, | |
3547 | seg->bounce_buf, new_buff_len, enqd_len); | |
3548 | if (len != new_buff_len) | |
3549 | xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n", | |
3550 | len, new_buff_len); | |
3551 | } else { | |
3552 | memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len); | |
3553 | } | |
3554 | ||
f9c589e1 MN |
3555 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, |
3556 | max_pkt, DMA_TO_DEVICE); | |
3557 | } else { | |
3558 | seg->bounce_dma = dma_map_single(dev, seg->bounce_buf, | |
3559 | max_pkt, DMA_FROM_DEVICE); | |
3560 | } | |
3561 | ||
3562 | if (dma_mapping_error(dev, seg->bounce_dma)) { | |
3563 | /* try without aligning. Some host controllers survive */ | |
3564 | xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n"); | |
3565 | return 0; | |
3566 | } | |
3567 | *trb_buff_len = new_buff_len; | |
3568 | seg->bounce_len = new_buff_len; | |
3569 | seg->bounce_offs = enqd_len; | |
3570 | ||
3571 | xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len); | |
3572 | ||
474ed23a MN |
3573 | return 1; |
3574 | } | |
3575 | ||
d2510342 AI |
3576 | /* This is very similar to what ehci-q.c qtd_fill() does */ |
3577 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
8a96c052 SS |
3578 | struct urb *urb, int slot_id, unsigned int ep_index) |
3579 | { | |
5a5a0b1a | 3580 | struct xhci_ring *ring; |
8e51adcc | 3581 | struct urb_priv *urb_priv; |
8a96c052 | 3582 | struct xhci_td *td; |
d2510342 AI |
3583 | struct xhci_generic_trb *start_trb; |
3584 | struct scatterlist *sg = NULL; | |
5a83f04a MN |
3585 | bool more_trbs_coming = true; |
3586 | bool need_zero_pkt = false; | |
86065c27 MN |
3587 | bool first_trb = true; |
3588 | unsigned int num_trbs; | |
d2510342 | 3589 | unsigned int start_cycle, num_sgs = 0; |
86065c27 | 3590 | unsigned int enqd_len, block_len, trb_buff_len, full_len; |
f9c589e1 | 3591 | int sent_len, ret; |
d2510342 | 3592 | u32 field, length_field, remainder; |
f9c589e1 | 3593 | u64 addr, send_addr; |
8a96c052 | 3594 | |
5a5a0b1a MN |
3595 | ring = xhci_urb_to_transfer_ring(xhci, urb); |
3596 | if (!ring) | |
e9df17eb SS |
3597 | return -EINVAL; |
3598 | ||
86065c27 | 3599 | full_len = urb->transfer_buffer_length; |
d2510342 | 3600 | /* If we have scatter/gather list, we use it. */ |
2017a1e5 | 3601 | if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) { |
d2510342 AI |
3602 | num_sgs = urb->num_mapped_sgs; |
3603 | sg = urb->sg; | |
86065c27 MN |
3604 | addr = (u64) sg_dma_address(sg); |
3605 | block_len = sg_dma_len(sg); | |
d2510342 | 3606 | num_trbs = count_sg_trbs_needed(urb); |
86065c27 | 3607 | } else { |
d2510342 | 3608 | num_trbs = count_trbs_needed(urb); |
86065c27 MN |
3609 | addr = (u64) urb->transfer_dma; |
3610 | block_len = full_len; | |
3611 | } | |
4758dcd1 | 3612 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
e9df17eb | 3613 | ep_index, urb->stream_id, |
3b72fca0 | 3614 | num_trbs, urb, 0, mem_flags); |
d2510342 | 3615 | if (unlikely(ret < 0)) |
4758dcd1 | 3616 | return ret; |
8e51adcc AX |
3617 | |
3618 | urb_priv = urb->hcpriv; | |
4758dcd1 RA |
3619 | |
3620 | /* Deal with URB_ZERO_PACKET - need one more td/trb */ | |
9ef7fbbb | 3621 | if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1) |
5a83f04a | 3622 | need_zero_pkt = true; |
4758dcd1 | 3623 | |
7e64b037 | 3624 | td = &urb_priv->td[0]; |
8e51adcc | 3625 | |
8a96c052 SS |
3626 | /* |
3627 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3628 | * until we've finished creating all the other TRBs. The ring's cycle | |
3629 | * state may change as we enqueue the other TRBs, so save it too. | |
3630 | */ | |
5a5a0b1a MN |
3631 | start_trb = &ring->enqueue->generic; |
3632 | start_cycle = ring->cycle_state; | |
f9c589e1 | 3633 | send_addr = addr; |
8a96c052 | 3634 | |
d2510342 | 3635 | /* Queue the TRBs, even if they are zero-length */ |
0d2daade AB |
3636 | for (enqd_len = 0; first_trb || enqd_len < full_len; |
3637 | enqd_len += trb_buff_len) { | |
d2510342 | 3638 | field = TRB_TYPE(TRB_NORMAL); |
af8b9e63 | 3639 | |
86065c27 MN |
3640 | /* TRB buffer should not cross 64KB boundaries */ |
3641 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); | |
3642 | trb_buff_len = min_t(unsigned int, trb_buff_len, block_len); | |
8a96c052 | 3643 | |
86065c27 MN |
3644 | if (enqd_len + trb_buff_len > full_len) |
3645 | trb_buff_len = full_len - enqd_len; | |
b10de142 SS |
3646 | |
3647 | /* Don't change the cycle bit of the first TRB until later */ | |
86065c27 MN |
3648 | if (first_trb) { |
3649 | first_trb = false; | |
50f7b52a | 3650 | if (start_cycle == 0) |
d2510342 | 3651 | field |= TRB_CYCLE; |
50f7b52a | 3652 | } else |
5a5a0b1a | 3653 | field |= ring->cycle_state; |
b10de142 SS |
3654 | |
3655 | /* Chain all the TRBs together; clear the chain bit in the last | |
3656 | * TRB to indicate it's the last TRB in the chain. | |
3657 | */ | |
86065c27 | 3658 | if (enqd_len + trb_buff_len < full_len) { |
b10de142 | 3659 | field |= TRB_CHAIN; |
2d98ef40 | 3660 | if (trb_is_link(ring->enqueue + 1)) { |
474ed23a | 3661 | if (xhci_align_td(xhci, urb, enqd_len, |
f9c589e1 MN |
3662 | &trb_buff_len, |
3663 | ring->enq_seg)) { | |
3664 | send_addr = ring->enq_seg->bounce_dma; | |
3665 | /* assuming TD won't span 2 segs */ | |
3666 | td->bounce_seg = ring->enq_seg; | |
3667 | } | |
474ed23a | 3668 | } |
f9c589e1 MN |
3669 | } |
3670 | if (enqd_len + trb_buff_len >= full_len) { | |
3671 | field &= ~TRB_CHAIN; | |
4758dcd1 | 3672 | field |= TRB_IOC; |
124c3937 | 3673 | more_trbs_coming = false; |
5a83f04a | 3674 | td->last_trb = ring->enqueue; |
55f6153d | 3675 | td->last_trb_seg = ring->enq_seg; |
33e39350 NSJ |
3676 | if (xhci_urb_suitable_for_idt(urb)) { |
3677 | memcpy(&send_addr, urb->transfer_buffer, | |
3678 | trb_buff_len); | |
bfa3dbb3 | 3679 | le64_to_cpus(&send_addr); |
33e39350 NSJ |
3680 | field |= TRB_IDT; |
3681 | } | |
b10de142 | 3682 | } |
af8b9e63 SS |
3683 | |
3684 | /* Only set interrupt on short packet for IN endpoints */ | |
3685 | if (usb_urb_dir_in(urb)) | |
3686 | field |= TRB_ISP; | |
3687 | ||
4da6e6f2 | 3688 | /* Set the TRB length, TD size, and interrupter fields. */ |
86065c27 MN |
3689 | remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len, |
3690 | full_len, urb, more_trbs_coming); | |
3691 | ||
f9dc68fe | 3692 | length_field = TRB_LEN(trb_buff_len) | |
c840d6ce | 3693 | TRB_TD_SIZE(remainder) | |
f9dc68fe | 3694 | TRB_INTR_TARGET(0); |
4da6e6f2 | 3695 | |
124c3937 | 3696 | queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt, |
f9c589e1 MN |
3697 | lower_32_bits(send_addr), |
3698 | upper_32_bits(send_addr), | |
f9dc68fe | 3699 | length_field, |
d2510342 | 3700 | field); |
55f6153d | 3701 | td->num_trbs++; |
b10de142 | 3702 | addr += trb_buff_len; |
f9c589e1 | 3703 | sent_len = trb_buff_len; |
d2510342 | 3704 | |
f9c589e1 | 3705 | while (sg && sent_len >= block_len) { |
86065c27 MN |
3706 | /* New sg entry */ |
3707 | --num_sgs; | |
f9c589e1 | 3708 | sent_len -= block_len; |
3c6f8cb9 SA |
3709 | sg = sg_next(sg); |
3710 | if (num_sgs != 0 && sg) { | |
86065c27 MN |
3711 | block_len = sg_dma_len(sg); |
3712 | addr = (u64) sg_dma_address(sg); | |
f9c589e1 | 3713 | addr += sent_len; |
d2510342 AI |
3714 | } |
3715 | } | |
f9c589e1 MN |
3716 | block_len -= sent_len; |
3717 | send_addr = addr; | |
d2510342 | 3718 | } |
b10de142 | 3719 | |
5a83f04a MN |
3720 | if (need_zero_pkt) { |
3721 | ret = prepare_transfer(xhci, xhci->devs[slot_id], | |
3722 | ep_index, urb->stream_id, | |
3723 | 1, urb, 1, mem_flags); | |
7e64b037 | 3724 | urb_priv->td[1].last_trb = ring->enqueue; |
55f6153d | 3725 | urb_priv->td[1].last_trb_seg = ring->enq_seg; |
5a83f04a MN |
3726 | field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC; |
3727 | queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field); | |
55f6153d | 3728 | urb_priv->td[1].num_trbs++; |
5a83f04a MN |
3729 | } |
3730 | ||
86065c27 | 3731 | check_trb_math(urb, enqd_len); |
e9df17eb | 3732 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
e1eab2e0 | 3733 | start_cycle, start_trb); |
b10de142 SS |
3734 | return 0; |
3735 | } | |
3736 | ||
d0e96f5a | 3737 | /* Caller must have locked xhci->lock */ |
23e3be11 | 3738 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, |
d0e96f5a SS |
3739 | struct urb *urb, int slot_id, unsigned int ep_index) |
3740 | { | |
3741 | struct xhci_ring *ep_ring; | |
3742 | int num_trbs; | |
3743 | int ret; | |
3744 | struct usb_ctrlrequest *setup; | |
3745 | struct xhci_generic_trb *start_trb; | |
3746 | int start_cycle; | |
fb79a6da | 3747 | u32 field; |
8e51adcc | 3748 | struct urb_priv *urb_priv; |
d0e96f5a SS |
3749 | struct xhci_td *td; |
3750 | ||
e9df17eb SS |
3751 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); |
3752 | if (!ep_ring) | |
3753 | return -EINVAL; | |
d0e96f5a SS |
3754 | |
3755 | /* | |
3756 | * Need to copy setup packet into setup TRB, so we can't use the setup | |
3757 | * DMA address. | |
3758 | */ | |
3759 | if (!urb->setup_packet) | |
3760 | return -EINVAL; | |
3761 | ||
d0e96f5a SS |
3762 | /* 1 TRB for setup, 1 for status */ |
3763 | num_trbs = 2; | |
3764 | /* | |
3765 | * Don't need to check if we need additional event data and normal TRBs, | |
3766 | * since data in control transfers will never get bigger than 16MB | |
3767 | * XXX: can we get a buffer that crosses 64KB boundaries? | |
3768 | */ | |
3769 | if (urb->transfer_buffer_length > 0) | |
3770 | num_trbs++; | |
e9df17eb SS |
3771 | ret = prepare_transfer(xhci, xhci->devs[slot_id], |
3772 | ep_index, urb->stream_id, | |
3b72fca0 | 3773 | num_trbs, urb, 0, mem_flags); |
d0e96f5a SS |
3774 | if (ret < 0) |
3775 | return ret; | |
3776 | ||
8e51adcc | 3777 | urb_priv = urb->hcpriv; |
7e64b037 | 3778 | td = &urb_priv->td[0]; |
55f6153d | 3779 | td->num_trbs = num_trbs; |
8e51adcc | 3780 | |
d0e96f5a SS |
3781 | /* |
3782 | * Don't give the first TRB to the hardware (by toggling the cycle bit) | |
3783 | * until we've finished creating all the other TRBs. The ring's cycle | |
3784 | * state may change as we enqueue the other TRBs, so save it too. | |
3785 | */ | |
3786 | start_trb = &ep_ring->enqueue->generic; | |
3787 | start_cycle = ep_ring->cycle_state; | |
3788 | ||
3789 | /* Queue setup TRB - see section 6.4.1.2.1 */ | |
3790 | /* FIXME better way to translate setup_packet into two u32 fields? */ | |
3791 | setup = (struct usb_ctrlrequest *) urb->setup_packet; | |
50f7b52a AX |
3792 | field = 0; |
3793 | field |= TRB_IDT | TRB_TYPE(TRB_SETUP); | |
3794 | if (start_cycle == 0) | |
3795 | field |= 0x1; | |
b83cdc8f | 3796 | |
dca77945 | 3797 | /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */ |
0cbd4b34 | 3798 | if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) { |
b83cdc8f AX |
3799 | if (urb->transfer_buffer_length > 0) { |
3800 | if (setup->bRequestType & USB_DIR_IN) | |
3801 | field |= TRB_TX_TYPE(TRB_DATA_IN); | |
3802 | else | |
3803 | field |= TRB_TX_TYPE(TRB_DATA_OUT); | |
3804 | } | |
3805 | } | |
3806 | ||
3b72fca0 | 3807 | queue_trb(xhci, ep_ring, true, |
28ccd296 ME |
3808 | setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16, |
3809 | le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16, | |
3810 | TRB_LEN(8) | TRB_INTR_TARGET(0), | |
3811 | /* Immediate data in pointer */ | |
3812 | field); | |
d0e96f5a SS |
3813 | |
3814 | /* If there's data, queue data TRBs */ | |
af8b9e63 SS |
3815 | /* Only set interrupt on short packet for IN endpoints */ |
3816 | if (usb_urb_dir_in(urb)) | |
3817 | field = TRB_ISP | TRB_TYPE(TRB_DATA); | |
3818 | else | |
3819 | field = TRB_TYPE(TRB_DATA); | |
3820 | ||
d0e96f5a | 3821 | if (urb->transfer_buffer_length > 0) { |
fb79a6da | 3822 | u32 length_field, remainder; |
13b82b74 | 3823 | u64 addr; |
fb79a6da | 3824 | |
33e39350 | 3825 | if (xhci_urb_suitable_for_idt(urb)) { |
13b82b74 | 3826 | memcpy(&addr, urb->transfer_buffer, |
33e39350 | 3827 | urb->transfer_buffer_length); |
bfa3dbb3 | 3828 | le64_to_cpus(&addr); |
33e39350 | 3829 | field |= TRB_IDT; |
13b82b74 MN |
3830 | } else { |
3831 | addr = (u64) urb->transfer_dma; | |
33e39350 NSJ |
3832 | } |
3833 | ||
fb79a6da LB |
3834 | remainder = xhci_td_remainder(xhci, 0, |
3835 | urb->transfer_buffer_length, | |
3836 | urb->transfer_buffer_length, | |
3837 | urb, 1); | |
3838 | length_field = TRB_LEN(urb->transfer_buffer_length) | | |
3839 | TRB_TD_SIZE(remainder) | | |
3840 | TRB_INTR_TARGET(0); | |
d0e96f5a SS |
3841 | if (setup->bRequestType & USB_DIR_IN) |
3842 | field |= TRB_DIR_IN; | |
3b72fca0 | 3843 | queue_trb(xhci, ep_ring, true, |
13b82b74 MN |
3844 | lower_32_bits(addr), |
3845 | upper_32_bits(addr), | |
f9dc68fe | 3846 | length_field, |
af8b9e63 | 3847 | field | ep_ring->cycle_state); |
d0e96f5a SS |
3848 | } |
3849 | ||
3850 | /* Save the DMA address of the last TRB in the TD */ | |
3851 | td->last_trb = ep_ring->enqueue; | |
55f6153d | 3852 | td->last_trb_seg = ep_ring->enq_seg; |
d0e96f5a SS |
3853 | |
3854 | /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ | |
3855 | /* If the device sent data, the status stage is an OUT transfer */ | |
3856 | if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN) | |
3857 | field = 0; | |
3858 | else | |
3859 | field = TRB_DIR_IN; | |
3b72fca0 | 3860 | queue_trb(xhci, ep_ring, false, |
d0e96f5a SS |
3861 | 0, |
3862 | 0, | |
3863 | TRB_INTR_TARGET(0), | |
3864 | /* Event on completion */ | |
3865 | field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state); | |
3866 | ||
e9df17eb | 3867 | giveback_first_trb(xhci, slot_id, ep_index, 0, |
e1eab2e0 | 3868 | start_cycle, start_trb); |
d0e96f5a SS |
3869 | return 0; |
3870 | } | |
3871 | ||
5cd43e33 SS |
3872 | /* |
3873 | * The transfer burst count field of the isochronous TRB defines the number of | |
3874 | * bursts that are required to move all packets in this TD. Only SuperSpeed | |
3875 | * devices can burst up to bMaxBurst number of packets per service interval. | |
3876 | * This field is zero based, meaning a value of zero in the field means one | |
3877 | * burst. Basically, for everything but SuperSpeed devices, this field will be | |
3878 | * zero. Only xHCI 1.0 host controllers support this field. | |
3879 | */ | |
3880 | static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci, | |
5cd43e33 SS |
3881 | struct urb *urb, unsigned int total_packet_count) |
3882 | { | |
3883 | unsigned int max_burst; | |
3884 | ||
09c352ed | 3885 | if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER) |
5cd43e33 SS |
3886 | return 0; |
3887 | ||
3888 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3213b151 | 3889 | return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1; |
5cd43e33 SS |
3890 | } |
3891 | ||
b61d378f SS |
3892 | /* |
3893 | * Returns the number of packets in the last "burst" of packets. This field is | |
3894 | * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so | |
3895 | * the last burst packet count is equal to the total number of packets in the | |
3896 | * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst | |
3897 | * must contain (bMaxBurst + 1) number of packets, but the last burst can | |
3898 | * contain 1 to (bMaxBurst + 1) packets. | |
3899 | */ | |
3900 | static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci, | |
b61d378f SS |
3901 | struct urb *urb, unsigned int total_packet_count) |
3902 | { | |
3903 | unsigned int max_burst; | |
3904 | unsigned int residue; | |
3905 | ||
3906 | if (xhci->hci_version < 0x100) | |
3907 | return 0; | |
3908 | ||
09c352ed | 3909 | if (urb->dev->speed >= USB_SPEED_SUPER) { |
b61d378f SS |
3910 | /* bMaxBurst is zero based: 0 means 1 packet per burst */ |
3911 | max_burst = urb->ep->ss_ep_comp.bMaxBurst; | |
3912 | residue = total_packet_count % (max_burst + 1); | |
3913 | /* If residue is zero, the last burst contains (max_burst + 1) | |
3914 | * number of packets, but the TLBPC field is zero-based. | |
3915 | */ | |
3916 | if (residue == 0) | |
3917 | return max_burst; | |
3918 | return residue - 1; | |
b61d378f | 3919 | } |
09c352ed MN |
3920 | if (total_packet_count == 0) |
3921 | return 0; | |
3922 | return total_packet_count - 1; | |
b61d378f SS |
3923 | } |
3924 | ||
79b8094f LB |
3925 | /* |
3926 | * Calculates Frame ID field of the isochronous TRB identifies the | |
3927 | * target frame that the Interval associated with this Isochronous | |
3928 | * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec. | |
3929 | * | |
3930 | * Returns actual frame id on success, negative value on error. | |
3931 | */ | |
3932 | static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci, | |
3933 | struct urb *urb, int index) | |
3934 | { | |
3935 | int start_frame, ist, ret = 0; | |
3936 | int start_frame_id, end_frame_id, current_frame_id; | |
3937 | ||
3938 | if (urb->dev->speed == USB_SPEED_LOW || | |
3939 | urb->dev->speed == USB_SPEED_FULL) | |
3940 | start_frame = urb->start_frame + index * urb->interval; | |
3941 | else | |
3942 | start_frame = (urb->start_frame + index * urb->interval) >> 3; | |
3943 | ||
3944 | /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2): | |
3945 | * | |
3946 | * If bit [3] of IST is cleared to '0', software can add a TRB no | |
3947 | * later than IST[2:0] Microframes before that TRB is scheduled to | |
3948 | * be executed. | |
3949 | * If bit [3] of IST is set to '1', software can add a TRB no later | |
3950 | * than IST[2:0] Frames before that TRB is scheduled to be executed. | |
3951 | */ | |
3952 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
3953 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
3954 | ist <<= 3; | |
3955 | ||
3956 | /* Software shall not schedule an Isoch TD with a Frame ID value that | |
3957 | * is less than the Start Frame ID or greater than the End Frame ID, | |
3958 | * where: | |
3959 | * | |
3960 | * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048 | |
3961 | * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048 | |
3962 | * | |
3963 | * Both the End Frame ID and Start Frame ID values are calculated | |
3964 | * in microframes. When software determines the valid Frame ID value; | |
3965 | * The End Frame ID value should be rounded down to the nearest Frame | |
3966 | * boundary, and the Start Frame ID value should be rounded up to the | |
3967 | * nearest Frame boundary. | |
3968 | */ | |
3969 | current_frame_id = readl(&xhci->run_regs->microframe_index); | |
3970 | start_frame_id = roundup(current_frame_id + ist + 1, 8); | |
3971 | end_frame_id = rounddown(current_frame_id + 895 * 8, 8); | |
3972 | ||
3973 | start_frame &= 0x7ff; | |
3974 | start_frame_id = (start_frame_id >> 3) & 0x7ff; | |
3975 | end_frame_id = (end_frame_id >> 3) & 0x7ff; | |
3976 | ||
3977 | xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n", | |
3978 | __func__, index, readl(&xhci->run_regs->microframe_index), | |
3979 | start_frame_id, end_frame_id, start_frame); | |
3980 | ||
3981 | if (start_frame_id < end_frame_id) { | |
3982 | if (start_frame > end_frame_id || | |
3983 | start_frame < start_frame_id) | |
3984 | ret = -EINVAL; | |
3985 | } else if (start_frame_id > end_frame_id) { | |
3986 | if ((start_frame > end_frame_id && | |
3987 | start_frame < start_frame_id)) | |
3988 | ret = -EINVAL; | |
3989 | } else { | |
3990 | ret = -EINVAL; | |
3991 | } | |
3992 | ||
3993 | if (index == 0) { | |
3994 | if (ret == -EINVAL || start_frame == start_frame_id) { | |
3995 | start_frame = start_frame_id + 1; | |
3996 | if (urb->dev->speed == USB_SPEED_LOW || | |
3997 | urb->dev->speed == USB_SPEED_FULL) | |
3998 | urb->start_frame = start_frame; | |
3999 | else | |
4000 | urb->start_frame = start_frame << 3; | |
4001 | ret = 0; | |
4002 | } | |
4003 | } | |
4004 | ||
4005 | if (ret) { | |
4006 | xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n", | |
4007 | start_frame, current_frame_id, index, | |
4008 | start_frame_id, end_frame_id); | |
4009 | xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n"); | |
4010 | return ret; | |
4011 | } | |
4012 | ||
4013 | return start_frame; | |
4014 | } | |
4015 | ||
edc649a8 MN |
4016 | /* Check if we should generate event interrupt for a TD in an isoc URB */ |
4017 | static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i) | |
4018 | { | |
4019 | if (xhci->hci_version < 0x100) | |
4020 | return false; | |
4021 | /* always generate an event interrupt for the last TD */ | |
4022 | if (i == num_tds - 1) | |
4023 | return false; | |
4024 | /* | |
4025 | * If AVOID_BEI is set the host handles full event rings poorly, | |
4026 | * generate an event at least every 8th TD to clear the event ring | |
4027 | */ | |
4028 | if (i && xhci->quirks & XHCI_AVOID_BEI) | |
90d551a5 | 4029 | return !!(i % xhci->isoc_bei_interval); |
edc649a8 MN |
4030 | |
4031 | return true; | |
4032 | } | |
4033 | ||
04e51901 AX |
4034 | /* This is for isoc transfer */ |
4035 | static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags, | |
4036 | struct urb *urb, int slot_id, unsigned int ep_index) | |
4037 | { | |
4038 | struct xhci_ring *ep_ring; | |
4039 | struct urb_priv *urb_priv; | |
4040 | struct xhci_td *td; | |
4041 | int num_tds, trbs_per_td; | |
4042 | struct xhci_generic_trb *start_trb; | |
4043 | bool first_trb; | |
4044 | int start_cycle; | |
4045 | u32 field, length_field; | |
4046 | int running_total, trb_buff_len, td_len, td_remain_len, ret; | |
4047 | u64 start_addr, addr; | |
4048 | int i, j; | |
47cbf692 | 4049 | bool more_trbs_coming; |
79b8094f | 4050 | struct xhci_virt_ep *xep; |
09c352ed | 4051 | int frame_id; |
04e51901 | 4052 | |
79b8094f | 4053 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
4054 | ep_ring = xhci->devs[slot_id]->eps[ep_index].ring; |
4055 | ||
4056 | num_tds = urb->number_of_packets; | |
4057 | if (num_tds < 1) { | |
4058 | xhci_dbg(xhci, "Isoc URB with zero packets?\n"); | |
4059 | return -EINVAL; | |
4060 | } | |
04e51901 AX |
4061 | start_addr = (u64) urb->transfer_dma; |
4062 | start_trb = &ep_ring->enqueue->generic; | |
4063 | start_cycle = ep_ring->cycle_state; | |
4064 | ||
522989a2 | 4065 | urb_priv = urb->hcpriv; |
09c352ed | 4066 | /* Queue the TRBs for each TD, even if they are zero-length */ |
04e51901 | 4067 | for (i = 0; i < num_tds; i++) { |
09c352ed MN |
4068 | unsigned int total_pkt_count, max_pkt; |
4069 | unsigned int burst_count, last_burst_pkt_count; | |
4070 | u32 sia_frame_id; | |
04e51901 | 4071 | |
4da6e6f2 | 4072 | first_trb = true; |
04e51901 AX |
4073 | running_total = 0; |
4074 | addr = start_addr + urb->iso_frame_desc[i].offset; | |
4075 | td_len = urb->iso_frame_desc[i].length; | |
4076 | td_remain_len = td_len; | |
734d3ddd | 4077 | max_pkt = usb_endpoint_maxp(&urb->ep->desc); |
09c352ed MN |
4078 | total_pkt_count = DIV_ROUND_UP(td_len, max_pkt); |
4079 | ||
48df4a6f | 4080 | /* A zero-length transfer still involves at least one packet. */ |
09c352ed MN |
4081 | if (total_pkt_count == 0) |
4082 | total_pkt_count++; | |
4083 | burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count); | |
4084 | last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci, | |
4085 | urb, total_pkt_count); | |
04e51901 | 4086 | |
d2510342 | 4087 | trbs_per_td = count_isoc_trbs_needed(urb, i); |
04e51901 AX |
4088 | |
4089 | ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, | |
3b72fca0 | 4090 | urb->stream_id, trbs_per_td, urb, i, mem_flags); |
522989a2 SS |
4091 | if (ret < 0) { |
4092 | if (i == 0) | |
4093 | return ret; | |
4094 | goto cleanup; | |
4095 | } | |
7e64b037 | 4096 | td = &urb_priv->td[i]; |
55f6153d | 4097 | td->num_trbs = trbs_per_td; |
09c352ed MN |
4098 | /* use SIA as default, if frame id is used overwrite it */ |
4099 | sia_frame_id = TRB_SIA; | |
4100 | if (!(urb->transfer_flags & URB_ISO_ASAP) && | |
4101 | HCC_CFC(xhci->hcc_params)) { | |
4102 | frame_id = xhci_get_isoc_frame_id(xhci, urb, i); | |
4103 | if (frame_id >= 0) | |
4104 | sia_frame_id = TRB_FRAME_ID(frame_id); | |
4105 | } | |
4106 | /* | |
4107 | * Set isoc specific data for the first TRB in a TD. | |
4108 | * Prevent HW from getting the TRBs by keeping the cycle state | |
4109 | * inverted in the first TDs isoc TRB. | |
4110 | */ | |
2f6d3b65 | 4111 | field = TRB_TYPE(TRB_ISOC) | |
09c352ed MN |
4112 | TRB_TLBPC(last_burst_pkt_count) | |
4113 | sia_frame_id | | |
4114 | (i ? ep_ring->cycle_state : !start_cycle); | |
4115 | ||
2f6d3b65 MN |
4116 | /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */ |
4117 | if (!xep->use_extended_tbc) | |
4118 | field |= TRB_TBC(burst_count); | |
4119 | ||
09c352ed | 4120 | /* fill the rest of the TRB fields, and remaining normal TRBs */ |
04e51901 AX |
4121 | for (j = 0; j < trbs_per_td; j++) { |
4122 | u32 remainder = 0; | |
09c352ed MN |
4123 | |
4124 | /* only first TRB is isoc, overwrite otherwise */ | |
4125 | if (!first_trb) | |
4126 | field = TRB_TYPE(TRB_NORMAL) | | |
4127 | ep_ring->cycle_state; | |
04e51901 | 4128 | |
af8b9e63 SS |
4129 | /* Only set interrupt on short packet for IN EPs */ |
4130 | if (usb_urb_dir_in(urb)) | |
4131 | field |= TRB_ISP; | |
4132 | ||
09c352ed | 4133 | /* Set the chain bit for all except the last TRB */ |
04e51901 | 4134 | if (j < trbs_per_td - 1) { |
47cbf692 | 4135 | more_trbs_coming = true; |
09c352ed | 4136 | field |= TRB_CHAIN; |
04e51901 | 4137 | } else { |
09c352ed | 4138 | more_trbs_coming = false; |
04e51901 | 4139 | td->last_trb = ep_ring->enqueue; |
55f6153d | 4140 | td->last_trb_seg = ep_ring->enq_seg; |
04e51901 | 4141 | field |= TRB_IOC; |
edc649a8 | 4142 | if (trb_block_event_intr(xhci, num_tds, i)) |
09c352ed | 4143 | field |= TRB_BEI; |
04e51901 | 4144 | } |
04e51901 | 4145 | /* Calculate TRB length */ |
d2510342 | 4146 | trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr); |
04e51901 AX |
4147 | if (trb_buff_len > td_remain_len) |
4148 | trb_buff_len = td_remain_len; | |
4149 | ||
4da6e6f2 | 4150 | /* Set the TRB length, TD size, & interrupter fields. */ |
c840d6ce MN |
4151 | remainder = xhci_td_remainder(xhci, running_total, |
4152 | trb_buff_len, td_len, | |
124c3937 | 4153 | urb, more_trbs_coming); |
c840d6ce | 4154 | |
04e51901 | 4155 | length_field = TRB_LEN(trb_buff_len) | |
04e51901 | 4156 | TRB_INTR_TARGET(0); |
4da6e6f2 | 4157 | |
2f6d3b65 MN |
4158 | /* xhci 1.1 with ETE uses TD Size field for TBC */ |
4159 | if (first_trb && xep->use_extended_tbc) | |
4160 | length_field |= TRB_TD_SIZE_TBC(burst_count); | |
4161 | else | |
4162 | length_field |= TRB_TD_SIZE(remainder); | |
4163 | first_trb = false; | |
4164 | ||
3b72fca0 | 4165 | queue_trb(xhci, ep_ring, more_trbs_coming, |
04e51901 AX |
4166 | lower_32_bits(addr), |
4167 | upper_32_bits(addr), | |
4168 | length_field, | |
af8b9e63 | 4169 | field); |
04e51901 AX |
4170 | running_total += trb_buff_len; |
4171 | ||
4172 | addr += trb_buff_len; | |
4173 | td_remain_len -= trb_buff_len; | |
4174 | } | |
4175 | ||
4176 | /* Check TD length */ | |
4177 | if (running_total != td_len) { | |
4178 | xhci_err(xhci, "ISOC TD length unmatch\n"); | |
cf840551 AX |
4179 | ret = -EINVAL; |
4180 | goto cleanup; | |
04e51901 AX |
4181 | } |
4182 | } | |
4183 | ||
79b8094f LB |
4184 | /* store the next frame id */ |
4185 | if (HCC_CFC(xhci->hcc_params)) | |
4186 | xep->next_frame_id = urb->start_frame + num_tds * urb->interval; | |
4187 | ||
c41136b0 AX |
4188 | if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) { |
4189 | if (xhci->quirks & XHCI_AMD_PLL_FIX) | |
4190 | usb_amd_quirk_pll_disable(); | |
4191 | } | |
4192 | xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++; | |
4193 | ||
e1eab2e0 AX |
4194 | giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id, |
4195 | start_cycle, start_trb); | |
04e51901 | 4196 | return 0; |
522989a2 SS |
4197 | cleanup: |
4198 | /* Clean up a partially enqueued isoc transfer. */ | |
4199 | ||
4200 | for (i--; i >= 0; i--) | |
7e64b037 | 4201 | list_del_init(&urb_priv->td[i].td_list); |
522989a2 SS |
4202 | |
4203 | /* Use the first TD as a temporary variable to turn the TDs we've queued | |
4204 | * into No-ops with a software-owned cycle bit. That way the hardware | |
4205 | * won't accidentally start executing bogus TDs when we partially | |
4206 | * overwrite them. td->first_trb and td->start_seg are already set. | |
4207 | */ | |
7e64b037 | 4208 | urb_priv->td[0].last_trb = ep_ring->enqueue; |
522989a2 | 4209 | /* Every TRB except the first & last will have its cycle bit flipped. */ |
7e64b037 | 4210 | td_to_noop(xhci, ep_ring, &urb_priv->td[0], true); |
522989a2 SS |
4211 | |
4212 | /* Reset the ring enqueue back to the first TRB and its cycle bit. */ | |
7e64b037 MN |
4213 | ep_ring->enqueue = urb_priv->td[0].first_trb; |
4214 | ep_ring->enq_seg = urb_priv->td[0].start_seg; | |
522989a2 | 4215 | ep_ring->cycle_state = start_cycle; |
b008df60 | 4216 | ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp; |
522989a2 SS |
4217 | usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb); |
4218 | return ret; | |
04e51901 AX |
4219 | } |
4220 | ||
4221 | /* | |
4222 | * Check transfer ring to guarantee there is enough room for the urb. | |
4223 | * Update ISO URB start_frame and interval. | |
79b8094f LB |
4224 | * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to |
4225 | * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or | |
4226 | * Contiguous Frame ID is not supported by HC. | |
04e51901 AX |
4227 | */ |
4228 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, | |
4229 | struct urb *urb, int slot_id, unsigned int ep_index) | |
4230 | { | |
4231 | struct xhci_virt_device *xdev; | |
4232 | struct xhci_ring *ep_ring; | |
4233 | struct xhci_ep_ctx *ep_ctx; | |
4234 | int start_frame; | |
04e51901 AX |
4235 | int num_tds, num_trbs, i; |
4236 | int ret; | |
79b8094f LB |
4237 | struct xhci_virt_ep *xep; |
4238 | int ist; | |
04e51901 AX |
4239 | |
4240 | xdev = xhci->devs[slot_id]; | |
79b8094f | 4241 | xep = &xhci->devs[slot_id]->eps[ep_index]; |
04e51901 AX |
4242 | ep_ring = xdev->eps[ep_index].ring; |
4243 | ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index); | |
4244 | ||
4245 | num_trbs = 0; | |
4246 | num_tds = urb->number_of_packets; | |
4247 | for (i = 0; i < num_tds; i++) | |
d2510342 | 4248 | num_trbs += count_isoc_trbs_needed(urb, i); |
04e51901 AX |
4249 | |
4250 | /* Check the ring to guarantee there is enough room for the whole urb. | |
4251 | * Do not insert any td of the urb to the ring if the check failed. | |
4252 | */ | |
5071e6b2 | 4253 | ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx), |
3b72fca0 | 4254 | num_trbs, mem_flags); |
04e51901 AX |
4255 | if (ret) |
4256 | return ret; | |
4257 | ||
79b8094f LB |
4258 | /* |
4259 | * Check interval value. This should be done before we start to | |
4260 | * calculate the start frame value. | |
4261 | */ | |
78140156 | 4262 | check_interval(xhci, urb, ep_ctx); |
79b8094f LB |
4263 | |
4264 | /* Calculate the start frame and put it in urb->start_frame. */ | |
42df7215 | 4265 | if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) { |
5071e6b2 | 4266 | if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) { |
42df7215 LB |
4267 | urb->start_frame = xep->next_frame_id; |
4268 | goto skip_start_over; | |
4269 | } | |
79b8094f LB |
4270 | } |
4271 | ||
4272 | start_frame = readl(&xhci->run_regs->microframe_index); | |
4273 | start_frame &= 0x3fff; | |
4274 | /* | |
4275 | * Round up to the next frame and consider the time before trb really | |
4276 | * gets scheduled by hardare. | |
4277 | */ | |
4278 | ist = HCS_IST(xhci->hcs_params2) & 0x7; | |
4279 | if (HCS_IST(xhci->hcs_params2) & (1 << 3)) | |
4280 | ist <<= 3; | |
4281 | start_frame += ist + XHCI_CFC_DELAY; | |
4282 | start_frame = roundup(start_frame, 8); | |
4283 | ||
4284 | /* | |
4285 | * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT | |
4286 | * is greate than 8 microframes. | |
4287 | */ | |
4288 | if (urb->dev->speed == USB_SPEED_LOW || | |
4289 | urb->dev->speed == USB_SPEED_FULL) { | |
4290 | start_frame = roundup(start_frame, urb->interval << 3); | |
4291 | urb->start_frame = start_frame >> 3; | |
4292 | } else { | |
4293 | start_frame = roundup(start_frame, urb->interval); | |
4294 | urb->start_frame = start_frame; | |
4295 | } | |
4296 | ||
4297 | skip_start_over: | |
b008df60 AX |
4298 | ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free; |
4299 | ||
3fc8206d | 4300 | return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index); |
04e51901 AX |
4301 | } |
4302 | ||
d0e96f5a SS |
4303 | /**** Command Ring Operations ****/ |
4304 | ||
913a8a34 SS |
4305 | /* Generic function for queueing a command TRB on the command ring. |
4306 | * Check to make sure there's room on the command ring for one command TRB. | |
4307 | * Also check that there's room reserved for commands that must not fail. | |
4308 | * If this is a command that must not fail, meaning command_must_succeed = TRUE, | |
4309 | * then only check for the number of reserved spots. | |
4310 | * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB | |
4311 | * because the command event handler may want to resubmit a failed command. | |
4312 | */ | |
ddba5cd0 MN |
4313 | static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4314 | u32 field1, u32 field2, | |
4315 | u32 field3, u32 field4, bool command_must_succeed) | |
7f84eef0 | 4316 | { |
913a8a34 | 4317 | int reserved_trbs = xhci->cmd_ring_reserved_trbs; |
d1dc908a | 4318 | int ret; |
ad6b1d91 | 4319 | |
98d74f9c MN |
4320 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
4321 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
ad6b1d91 | 4322 | xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n"); |
c9aa1a2d | 4323 | return -ESHUTDOWN; |
ad6b1d91 | 4324 | } |
d1dc908a | 4325 | |
913a8a34 SS |
4326 | if (!command_must_succeed) |
4327 | reserved_trbs++; | |
4328 | ||
d1dc908a | 4329 | ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING, |
3b72fca0 | 4330 | reserved_trbs, GFP_ATOMIC); |
d1dc908a SS |
4331 | if (ret < 0) { |
4332 | xhci_err(xhci, "ERR: No room for command on command ring\n"); | |
913a8a34 SS |
4333 | if (command_must_succeed) |
4334 | xhci_err(xhci, "ERR: Reserved TRB counting for " | |
4335 | "unfailable commands failed.\n"); | |
d1dc908a | 4336 | return ret; |
7f84eef0 | 4337 | } |
c9aa1a2d MN |
4338 | |
4339 | cmd->command_trb = xhci->cmd_ring->enqueue; | |
ddba5cd0 | 4340 | |
c311e391 | 4341 | /* if there are no other commands queued we start the timeout timer */ |
daa47f21 | 4342 | if (list_empty(&xhci->cmd_list)) { |
c311e391 | 4343 | xhci->current_cmd = cmd; |
cb4d5ce5 | 4344 | xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT); |
c311e391 MN |
4345 | } |
4346 | ||
daa47f21 LB |
4347 | list_add_tail(&cmd->cmd_list, &xhci->cmd_list); |
4348 | ||
3b72fca0 AX |
4349 | queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3, |
4350 | field4 | xhci->cmd_ring->cycle_state); | |
7f84eef0 SS |
4351 | return 0; |
4352 | } | |
4353 | ||
3ffbba95 | 4354 | /* Queue a slot enable or disable request on the command ring */ |
ddba5cd0 MN |
4355 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4356 | u32 trb_type, u32 slot_id) | |
3ffbba95 | 4357 | { |
ddba5cd0 | 4358 | return queue_command(xhci, cmd, 0, 0, 0, |
913a8a34 | 4359 | TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false); |
3ffbba95 SS |
4360 | } |
4361 | ||
4362 | /* Queue an address device command TRB */ | |
ddba5cd0 MN |
4363 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4364 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup) | |
3ffbba95 | 4365 | { |
ddba5cd0 | 4366 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 4367 | upper_32_bits(in_ctx_ptr), 0, |
48fc7dbd DW |
4368 | TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id) |
4369 | | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false); | |
2a8f82c4 SS |
4370 | } |
4371 | ||
ddba5cd0 | 4372 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, |
0238634d SS |
4373 | u32 field1, u32 field2, u32 field3, u32 field4) |
4374 | { | |
ddba5cd0 | 4375 | return queue_command(xhci, cmd, field1, field2, field3, field4, false); |
0238634d SS |
4376 | } |
4377 | ||
2a8f82c4 | 4378 | /* Queue a reset device command TRB */ |
ddba5cd0 MN |
4379 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4380 | u32 slot_id) | |
2a8f82c4 | 4381 | { |
ddba5cd0 | 4382 | return queue_command(xhci, cmd, 0, 0, 0, |
2a8f82c4 | 4383 | TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id), |
913a8a34 | 4384 | false); |
3ffbba95 | 4385 | } |
f94e0186 SS |
4386 | |
4387 | /* Queue a configure endpoint command TRB */ | |
ddba5cd0 MN |
4388 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
4389 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, | |
913a8a34 | 4390 | u32 slot_id, bool command_must_succeed) |
f94e0186 | 4391 | { |
ddba5cd0 | 4392 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
8e595a5d | 4393 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 SS |
4394 | TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id), |
4395 | command_must_succeed); | |
f94e0186 | 4396 | } |
ae636747 | 4397 | |
f2217e8e | 4398 | /* Queue an evaluate context command TRB */ |
ddba5cd0 MN |
4399 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4400 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed) | |
f2217e8e | 4401 | { |
ddba5cd0 | 4402 | return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr), |
f2217e8e | 4403 | upper_32_bits(in_ctx_ptr), 0, |
913a8a34 | 4404 | TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id), |
4b266541 | 4405 | command_must_succeed); |
f2217e8e SS |
4406 | } |
4407 | ||
be88fe4f AX |
4408 | /* |
4409 | * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop | |
4410 | * activity on an endpoint that is about to be suspended. | |
4411 | */ | |
ddba5cd0 MN |
4412 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
4413 | int slot_id, unsigned int ep_index, int suspend) | |
ae636747 SS |
4414 | { |
4415 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4416 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4417 | u32 type = TRB_TYPE(TRB_STOP_RING); | |
be88fe4f | 4418 | u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend); |
ae636747 | 4419 | |
ddba5cd0 | 4420 | return queue_command(xhci, cmd, 0, 0, 0, |
be88fe4f | 4421 | trb_slot_id | trb_ep_index | type | trb_suspend, false); |
ae636747 SS |
4422 | } |
4423 | ||
ddba5cd0 | 4424 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, |
21749148 MN |
4425 | int slot_id, unsigned int ep_index, |
4426 | enum xhci_ep_reset_type reset_type) | |
a1587d97 SS |
4427 | { |
4428 | u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id); | |
4429 | u32 trb_ep_index = EP_ID_FOR_TRB(ep_index); | |
4430 | u32 type = TRB_TYPE(TRB_RESET_EP); | |
4431 | ||
21749148 MN |
4432 | if (reset_type == EP_SOFT_RESET) |
4433 | type |= TRB_TSP; | |
4434 | ||
ddba5cd0 MN |
4435 | return queue_command(xhci, cmd, 0, 0, 0, |
4436 | trb_slot_id | trb_ep_index | type, false); | |
a1587d97 | 4437 | } |