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USB: add SPDX identifiers to all remaining files in drivers/usb/
[mirror_ubuntu-jammy-kernel.git] / drivers / usb / host / xhci-tegra.c
CommitLineData
5fd54ace 1// SPDX-License-Identifier: GPL-2.0
e84fce0f
TR		 2/*
3 * NVIDIA Tegra xHCI host controller driver
4 *
5 * Copyright (C) 2014 NVIDIA Corporation
6 * Copyright (C) 2014 Google, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/firmware.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of_device.h>
21#include <linux/phy/phy.h>
22#include <linux/phy/tegra/xusb.h>
23#include <linux/platform_device.h>
24#include <linux/pm.h>
25#include <linux/regulator/consumer.h>
26#include <linux/reset.h>
27#include <linux/slab.h>
28
29#include "xhci.h"
30
31#define TEGRA_XHCI_SS_HIGH_SPEED 120000000
32#define TEGRA_XHCI_SS_LOW_SPEED 12000000
33
34/* FPCI CFG registers */
35#define XUSB_CFG_1 0x004
36#define XUSB_IO_SPACE_EN BIT(0)
37#define XUSB_MEM_SPACE_EN BIT(1)
38#define XUSB_BUS_MASTER_EN BIT(2)
39#define XUSB_CFG_4 0x010
40#define XUSB_BASE_ADDR_SHIFT 15
41#define XUSB_BASE_ADDR_MASK 0x1ffff
42#define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
43#define XUSB_CFG_CSB_BASE_ADDR 0x800
44
45/* FPCI mailbox registers */
46#define XUSB_CFG_ARU_MBOX_CMD 0x0e4
47#define MBOX_DEST_FALC BIT(27)
48#define MBOX_DEST_PME BIT(28)
49#define MBOX_DEST_SMI BIT(29)
50#define MBOX_DEST_XHCI BIT(30)
51#define MBOX_INT_EN BIT(31)
52#define XUSB_CFG_ARU_MBOX_DATA_IN 0x0e8
53#define CMD_DATA_SHIFT 0
54#define CMD_DATA_MASK 0xffffff
55#define CMD_TYPE_SHIFT 24
56#define CMD_TYPE_MASK 0xff
57#define XUSB_CFG_ARU_MBOX_DATA_OUT 0x0ec
58#define XUSB_CFG_ARU_MBOX_OWNER 0x0f0
59#define MBOX_OWNER_NONE 0
60#define MBOX_OWNER_FW 1
61#define MBOX_OWNER_SW 2
62#define XUSB_CFG_ARU_SMI_INTR 0x428
63#define MBOX_SMI_INTR_FW_HANG BIT(1)
64#define MBOX_SMI_INTR_EN BIT(3)
65
66/* IPFS registers */
67#define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
68#define IPFS_EN_FPCI BIT(0)
69#define IPFS_XUSB_HOST_INTR_MASK_0 0x188
70#define IPFS_IP_INT_MASK BIT(16)
71#define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
72
73#define CSB_PAGE_SELECT_MASK 0x7fffff
74#define CSB_PAGE_SELECT_SHIFT 9
75#define CSB_PAGE_OFFSET_MASK 0x1ff
76#define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
77 CSB_PAGE_SELECT_MASK)
78#define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
79
80/* Falcon CSB registers */
81#define XUSB_FALC_CPUCTL 0x100
82#define CPUCTL_STARTCPU BIT(1)
83#define CPUCTL_STATE_HALTED BIT(4)
84#define CPUCTL_STATE_STOPPED BIT(5)
85#define XUSB_FALC_BOOTVEC 0x104
86#define XUSB_FALC_DMACTL 0x10c
87#define XUSB_FALC_IMFILLRNG1 0x154
88#define IMFILLRNG1_TAG_MASK 0xffff
89#define IMFILLRNG1_TAG_LO_SHIFT 0
90#define IMFILLRNG1_TAG_HI_SHIFT 16
91#define XUSB_FALC_IMFILLCTL 0x158
92
93/* MP CSB registers */
94#define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
95#define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
96#define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
97#define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
98#define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
99#define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
100#define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
101#define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
102#define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
103#define L2IMEMOP_ACTION_SHIFT 24
104#define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
105#define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
106#define XUSB_CSB_MP_APMAP 0x10181c
107#define APMAP_BOOTPATH BIT(31)
108
109#define IMEM_BLOCK_SIZE 256
110
111struct tegra_xusb_fw_header {
112 u32 boot_loadaddr_in_imem;
113 u32 boot_codedfi_offset;
114 u32 boot_codetag;
115 u32 boot_codesize;
116 u32 phys_memaddr;
117 u16 reqphys_memsize;
118 u16 alloc_phys_memsize;
119 u32 rodata_img_offset;
120 u32 rodata_section_start;
121 u32 rodata_section_end;
122 u32 main_fnaddr;
123 u32 fwimg_cksum;
124 u32 fwimg_created_time;
125 u32 imem_resident_start;
126 u32 imem_resident_end;
127 u32 idirect_start;
128 u32 idirect_end;
129 u32 l2_imem_start;
130 u32 l2_imem_end;
131 u32 version_id;
132 u8 init_ddirect;
133 u8 reserved[3];
134 u32 phys_addr_log_buffer;
135 u32 total_log_entries;
136 u32 dequeue_ptr;
137 u32 dummy_var[2];
138 u32 fwimg_len;
139 u8 magic[8];
140 u32 ss_low_power_entry_timeout;
141 u8 num_hsic_port;
142 u8 padding[139]; /* Pad to 256 bytes */
143};
144
145struct tegra_xusb_phy_type {
146 const char *name;
147 unsigned int num;
148};
149
150struct tegra_xusb_soc {
151 const char *firmware;
152 const char * const *supply_names;
153 unsigned int num_supplies;
154 const struct tegra_xusb_phy_type *phy_types;
155 unsigned int num_types;
156
157 struct {
158 struct {
159 unsigned int offset;
160 unsigned int count;
161 } usb2, ulpi, hsic, usb3;
162 } ports;
ab065e96
TR		 163
164 bool scale_ss_clock;
e84fce0f
TR		 165};
166
167struct tegra_xusb {
168 struct device *dev;
169 void __iomem *regs;
170 struct usb_hcd *hcd;
171
172 struct mutex lock;
173
174 int xhci_irq;
175 int mbox_irq;
176
177 void __iomem *ipfs_base;
178 void __iomem *fpci_base;
179
180 const struct tegra_xusb_soc *soc;
181
182 struct regulator_bulk_data *supplies;
183
184 struct tegra_xusb_padctl *padctl;
185
186 struct clk *host_clk;
187 struct clk *falcon_clk;
188 struct clk *ss_clk;
189 struct clk *ss_src_clk;
190 struct clk *hs_src_clk;
191 struct clk *fs_src_clk;
192 struct clk *pll_u_480m;
193 struct clk *clk_m;
194 struct clk *pll_e;
195
196 struct reset_control *host_rst;
197 struct reset_control *ss_rst;
198
199 struct phy **phys;
200 unsigned int num_phys;
201
202 /* Firmware loading related */
203 struct {
204 size_t size;
205 void *virt;
206 dma_addr_t phys;
207 } fw;
208};
209
210static struct hc_driver __read_mostly tegra_xhci_hc_driver;
211
212static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
213{
214 return readl(tegra->fpci_base + offset);
215}
216
217static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
218 unsigned int offset)
219{
220 writel(value, tegra->fpci_base + offset);
221}
222
223static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
224{
225 return readl(tegra->ipfs_base + offset);
226}
227
228static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
229 unsigned int offset)
230{
231 writel(value, tegra->ipfs_base + offset);
232}
233
234static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
235{
236 u32 page = CSB_PAGE_SELECT(offset);
237 u32 ofs = CSB_PAGE_OFFSET(offset);
238
239 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
240
241 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
242}
243
244static void csb_writel(struct tegra_xusb *tegra, u32 value,
245 unsigned int offset)
246{
247 u32 page = CSB_PAGE_SELECT(offset);
248 u32 ofs = CSB_PAGE_OFFSET(offset);
249
250 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
251 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
252}
253
254static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
255 unsigned long rate)
256{
257 unsigned long new_parent_rate, old_parent_rate;
258 struct clk *clk = tegra->ss_src_clk;
259 unsigned int div;
260 int err;
261
262 if (clk_get_rate(clk) == rate)
263 return 0;
264
265 switch (rate) {
266 case TEGRA_XHCI_SS_HIGH_SPEED:
267 /*
268 * Reparent to PLLU_480M. Set divider first to avoid
269 * overclocking.
270 */
271 old_parent_rate = clk_get_rate(clk_get_parent(clk));
272 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
273 div = new_parent_rate / rate;
274
275 err = clk_set_rate(clk, old_parent_rate / div);
276 if (err)
277 return err;
278
279 err = clk_set_parent(clk, tegra->pll_u_480m);
280 if (err)
281 return err;
282
283 /*
284 * The rate should already be correct, but set it again just
285 * to be sure.
286 */
287 err = clk_set_rate(clk, rate);
288 if (err)
289 return err;
290
291 break;
292
293 case TEGRA_XHCI_SS_LOW_SPEED:
294 /* Reparent to CLK_M */
295 err = clk_set_parent(clk, tegra->clk_m);
296 if (err)
297 return err;
298
299 err = clk_set_rate(clk, rate);
300 if (err)
301 return err;
302
303 break;
304
305 default:
306 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
307 return -EINVAL;
308 }
309
310 if (clk_get_rate(clk) != rate) {
311 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
312 return -EINVAL;
313 }
314
315 return 0;
316}
317
318static unsigned long extract_field(u32 value, unsigned int start,
319 unsigned int count)
320{
321 return (value >> start) & ((1 << count) - 1);
322}
323
324/* Command requests from the firmware */
325enum tegra_xusb_mbox_cmd {
326 MBOX_CMD_MSG_ENABLED = 1,
327 MBOX_CMD_INC_FALC_CLOCK,
328 MBOX_CMD_DEC_FALC_CLOCK,
329 MBOX_CMD_INC_SSPI_CLOCK,
330 MBOX_CMD_DEC_SSPI_CLOCK,
331 MBOX_CMD_SET_BW, /* no ACK/NAK required */
332 MBOX_CMD_SET_SS_PWR_GATING,
333 MBOX_CMD_SET_SS_PWR_UNGATING,
334 MBOX_CMD_SAVE_DFE_CTLE_CTX,
335 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
336 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
337 MBOX_CMD_START_HSIC_IDLE,
338 MBOX_CMD_STOP_HSIC_IDLE,
339 MBOX_CMD_DBC_WAKE_STACK, /* unused */
340 MBOX_CMD_HSIC_PRETEND_CONNECT,
341 MBOX_CMD_RESET_SSPI,
342 MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
343 MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
344
345 MBOX_CMD_MAX,
346
347 /* Response message to above commands */
348 MBOX_CMD_ACK = 128,
349 MBOX_CMD_NAK
350};
351
352static const char * const mbox_cmd_name[] = {
353 [ 1] = "MSG_ENABLE",
354 [ 2] = "INC_FALCON_CLOCK",
355 [ 3] = "DEC_FALCON_CLOCK",
356 [ 4] = "INC_SSPI_CLOCK",
357 [ 5] = "DEC_SSPI_CLOCK",
358 [ 6] = "SET_BW",
359 [ 7] = "SET_SS_PWR_GATING",
360 [ 8] = "SET_SS_PWR_UNGATING",
361 [ 9] = "SAVE_DFE_CTLE_CTX",
362 [ 10] = "AIRPLANE_MODE_ENABLED",
363 [ 11] = "AIRPLANE_MODE_DISABLED",
364 [ 12] = "START_HSIC_IDLE",
365 [ 13] = "STOP_HSIC_IDLE",
366 [ 14] = "DBC_WAKE_STACK",
367 [ 15] = "HSIC_PRETEND_CONNECT",
368 [ 16] = "RESET_SSPI",
369 [ 17] = "DISABLE_SS_LFPS_DETECTION",
370 [ 18] = "ENABLE_SS_LFPS_DETECTION",
371 [128] = "ACK",
372 [129] = "NAK",
373};
374
375struct tegra_xusb_mbox_msg {
376 u32 cmd;
377 u32 data;
378};
379
380static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
381{
382 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
383 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
384}
385static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
386 u32 value)
387{
388 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
389 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
390}
391
392static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
393{
394 switch (cmd) {
395 case MBOX_CMD_SET_BW:
396 case MBOX_CMD_ACK:
397 case MBOX_CMD_NAK:
398 return false;
399
400 default:
401 return true;
402 }
403}
404
405static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
406 const struct tegra_xusb_mbox_msg *msg)
407{
408 bool wait_for_idle = false;
409 u32 value;
410
411 /*
412 * Acquire the mailbox. The firmware still owns the mailbox for
413 * ACK/NAK messages.
414 */
415 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
416 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
417 if (value != MBOX_OWNER_NONE) {
418 dev_err(tegra->dev, "mailbox is busy\n");
419 return -EBUSY;
420 }
421
422 fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER);
423
424 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
425 if (value != MBOX_OWNER_SW) {
426 dev_err(tegra->dev, "failed to acquire mailbox\n");
427 return -EBUSY;
428 }
429
430 wait_for_idle = true;
431 }
432
433 value = tegra_xusb_mbox_pack(msg);
434 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN);
435
436 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
437 value |= MBOX_INT_EN | MBOX_DEST_FALC;
438 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
439
440 if (wait_for_idle) {
441 unsigned long timeout = jiffies + msecs_to_jiffies(250);
442
443 while (time_before(jiffies, timeout)) {
444 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
445 if (value == MBOX_OWNER_NONE)
446 break;
447
448 usleep_range(10, 20);
449 }
450
451 if (time_after(jiffies, timeout))
452 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
453
454 if (value != MBOX_OWNER_NONE)
455 return -ETIMEDOUT;
456 }
457
458 return 0;
459}
460
461static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
462{
463 struct tegra_xusb *tegra = data;
464 u32 value;
465
466 /* clear mailbox interrupts */
467 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
468 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
469
470 if (value & MBOX_SMI_INTR_FW_HANG)
471 dev_err(tegra->dev, "controller firmware hang\n");
472
473 return IRQ_WAKE_THREAD;
474}
475
476static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
477 const struct tegra_xusb_mbox_msg *msg)
478{
479 struct tegra_xusb_padctl *padctl = tegra->padctl;
480 const struct tegra_xusb_soc *soc = tegra->soc;
481 struct device *dev = tegra->dev;
482 struct tegra_xusb_mbox_msg rsp;
483 unsigned long mask;
484 unsigned int port;
485 bool idle, enable;
486 int err;
487
488 memset(&rsp, 0, sizeof(rsp));
489
490 switch (msg->cmd) {
491 case MBOX_CMD_INC_FALC_CLOCK:
492 case MBOX_CMD_DEC_FALC_CLOCK:
493 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
494 if (rsp.data != msg->data)
495 rsp.cmd = MBOX_CMD_NAK;
496 else
497 rsp.cmd = MBOX_CMD_ACK;
498
499 break;
500
501 case MBOX_CMD_INC_SSPI_CLOCK:
502 case MBOX_CMD_DEC_SSPI_CLOCK:
ab065e96
TR		 503 if (tegra->soc->scale_ss_clock) {
504 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
505 if (err < 0)
506 rsp.cmd = MBOX_CMD_NAK;
507 else
508 rsp.cmd = MBOX_CMD_ACK;
509
510 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
511 } else {
e84fce0f 512 rsp.cmd = MBOX_CMD_ACK;
ab065e96
TR		 513 rsp.data = msg->data;
514 }
e84fce0f 515
e84fce0f
TR		 516 break;
517
518 case MBOX_CMD_SET_BW:
519 /*
520 * TODO: Request bandwidth once EMC scaling is supported.
521 * Ignore for now since ACK/NAK is not required for SET_BW
522 * messages.
523 */
524 break;
525
526 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
527 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
528 if (err < 0) {
529 dev_err(dev, "failed to save context for USB3#%u: %d\n",
530 msg->data, err);
531 rsp.cmd = MBOX_CMD_NAK;
532 } else {
533 rsp.cmd = MBOX_CMD_ACK;
534 }
535
536 rsp.data = msg->data;
537 break;
538
539 case MBOX_CMD_START_HSIC_IDLE:
540 case MBOX_CMD_STOP_HSIC_IDLE:
541 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
542 idle = false;
543 else
544 idle = true;
545
546 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
547 soc->ports.hsic.count);
548
549 for_each_set_bit(port, &mask, 32) {
550 err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
551 idle);
552 if (err < 0)
553 break;
554 }
555
556 if (err < 0) {
557 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
558 idle ? "idle" : "busy", err);
559 rsp.cmd = MBOX_CMD_NAK;
560 } else {
561 rsp.cmd = MBOX_CMD_ACK;
562 }
563
564 rsp.data = msg->data;
565 break;
566
567 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
568 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
569 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
570 enable = false;
571 else
572 enable = true;
573
574 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
575 soc->ports.usb3.count);
576
577 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
578 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
579 port,
580 enable);
581 if (err < 0)
582 break;
583 }
584
585 if (err < 0) {
586 dev_err(dev,
587 "failed to %s LFPS detection on USB3#%u: %d\n",
588 enable ? "enable" : "disable", port, err);
589 rsp.cmd = MBOX_CMD_NAK;
590 } else {
591 rsp.cmd = MBOX_CMD_ACK;
592 }
593
594 rsp.data = msg->data;
595 break;
596
597 default:
598 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
599 break;
600 }
601
602 if (rsp.cmd) {
603 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
604
605 err = tegra_xusb_mbox_send(tegra, &rsp);
606 if (err < 0)
607 dev_err(dev, "failed to send %s: %d\n", cmd, err);
608 }
609}
610
611static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
612{
613 struct tegra_xusb *tegra = data;
614 struct tegra_xusb_mbox_msg msg;
615 u32 value;
616
617 mutex_lock(&tegra->lock);
618
619 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT);
620 tegra_xusb_mbox_unpack(&msg, value);
621
622 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
623 value &= ~MBOX_DEST_SMI;
624 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
625
626 /* clear mailbox owner if no ACK/NAK is required */
627 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
628 fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER);
629
630 tegra_xusb_mbox_handle(tegra, &msg);
631
632 mutex_unlock(&tegra->lock);
633 return IRQ_HANDLED;
634}
635
636static void tegra_xusb_ipfs_config(struct tegra_xusb *tegra,
637 struct resource *regs)
638{
639 u32 value;
640
641 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
642 value |= IPFS_EN_FPCI;
643 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
644
645 usleep_range(10, 20);
646
647 /* Program BAR0 space */
648 value = fpci_readl(tegra, XUSB_CFG_4);
649 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
650 value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
651 fpci_writel(tegra, value, XUSB_CFG_4);
652
653 usleep_range(100, 200);
654
655 /* Enable bus master */
656 value = fpci_readl(tegra, XUSB_CFG_1);
657 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
658 fpci_writel(tegra, value, XUSB_CFG_1);
659
660 /* Enable interrupt assertion */
661 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
662 value |= IPFS_IP_INT_MASK;
663 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
664
665 /* Set hysteresis */
666 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
667}
668
669static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
670{
671 int err;
672
673 err = clk_prepare_enable(tegra->pll_e);
674 if (err < 0)
675 return err;
676
677 err = clk_prepare_enable(tegra->host_clk);
678 if (err < 0)
679 goto disable_plle;
680
681 err = clk_prepare_enable(tegra->ss_clk);
682 if (err < 0)
683 goto disable_host;
684
685 err = clk_prepare_enable(tegra->falcon_clk);
686 if (err < 0)
687 goto disable_ss;
688
689 err = clk_prepare_enable(tegra->fs_src_clk);
690 if (err < 0)
691 goto disable_falc;
692
693 err = clk_prepare_enable(tegra->hs_src_clk);
694 if (err < 0)
695 goto disable_fs_src;
696
ab065e96
TR		 697 if (tegra->soc->scale_ss_clock) {
698 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
699 if (err < 0)
700 goto disable_hs_src;
701 }
e84fce0f
TR		 702
703 return 0;
704
705disable_hs_src:
706 clk_disable_unprepare(tegra->hs_src_clk);
707disable_fs_src:
708 clk_disable_unprepare(tegra->fs_src_clk);
709disable_falc:
710 clk_disable_unprepare(tegra->falcon_clk);
711disable_ss:
712 clk_disable_unprepare(tegra->ss_clk);
713disable_host:
714 clk_disable_unprepare(tegra->host_clk);
715disable_plle:
716 clk_disable_unprepare(tegra->pll_e);
717 return err;
718}
719
720static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
721{
722 clk_disable_unprepare(tegra->pll_e);
723 clk_disable_unprepare(tegra->host_clk);
724 clk_disable_unprepare(tegra->ss_clk);
725 clk_disable_unprepare(tegra->falcon_clk);
726 clk_disable_unprepare(tegra->fs_src_clk);
727 clk_disable_unprepare(tegra->hs_src_clk);
728}
729
730static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
731{
732 unsigned int i;
733 int err;
734
735 for (i = 0; i < tegra->num_phys; i++) {
736 err = phy_init(tegra->phys[i]);
737 if (err)
738 goto disable_phy;
739
740 err = phy_power_on(tegra->phys[i]);
741 if (err) {
742 phy_exit(tegra->phys[i]);
743 goto disable_phy;
744 }
745 }
746
747 return 0;
748
749disable_phy:
750 while (i--) {
751 phy_power_off(tegra->phys[i]);
752 phy_exit(tegra->phys[i]);
753 }
754
755 return err;
756}
757
758static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
759{
760 unsigned int i;
761
762 for (i = 0; i < tegra->num_phys; i++) {
763 phy_power_off(tegra->phys[i]);
764 phy_exit(tegra->phys[i]);
765 }
766}
767
768static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
769{
770 unsigned int code_tag_blocks, code_size_blocks, code_blocks;
771 struct tegra_xusb_fw_header *header;
772 struct device *dev = tegra->dev;
773 const struct firmware *fw;
774 unsigned long timeout;
9506b146 775 time64_t timestamp;
e84fce0f
TR		 776 struct tm time;
777 u64 address;
778 u32 value;
779 int err;
780
781 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
782 if (err < 0) {
783 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
784 return err;
785 }
786
787 /* Load Falcon controller with its firmware. */
788 header = (struct tegra_xusb_fw_header *)fw->data;
789 tegra->fw.size = le32_to_cpu(header->fwimg_len);
790
791 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
792 &tegra->fw.phys, GFP_KERNEL);
793 if (!tegra->fw.virt) {
794 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
795 release_firmware(fw);
796 return -ENOMEM;
797 }
798
799 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
800 memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
801 release_firmware(fw);
802
803 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
804 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
805 csb_readl(tegra, XUSB_FALC_CPUCTL));
806 return 0;
807 }
808
809 /* Program the size of DFI into ILOAD_ATTR. */
810 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
811
812 /*
813 * Boot code of the firmware reads the ILOAD_BASE registers
814 * to get to the start of the DFI in system memory.
815 */
816 address = tegra->fw.phys + sizeof(*header);
817 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
818 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
819
820 /* Set BOOTPATH to 1 in APMAP. */
821 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
822
823 /* Invalidate L2IMEM. */
824 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
825
826 /*
827 * Initiate fetch of bootcode from system memory into L2IMEM.
828 * Program bootcode location and size in system memory.
829 */
830 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
831 IMEM_BLOCK_SIZE);
832 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
833 IMEM_BLOCK_SIZE);
834 code_blocks = code_tag_blocks + code_size_blocks;
835
836 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
837 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
838 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
839 L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
840 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
841
842 /* Trigger L2IMEM load operation. */
843 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
844 XUSB_CSB_MP_L2IMEMOP_TRIG);
845
846 /* Setup Falcon auto-fill. */
847 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
848
849 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
850 IMFILLRNG1_TAG_LO_SHIFT) |
851 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
852 IMFILLRNG1_TAG_HI_SHIFT);
853 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
854
855 csb_writel(tegra, 0, XUSB_FALC_DMACTL);
856
857 msleep(50);
858
859 csb_writel(tegra, le32_to_cpu(header->boot_codetag),
860 XUSB_FALC_BOOTVEC);
861
862 /* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */
863 timeout = jiffies + msecs_to_jiffies(5);
864
865 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
866
867 while (time_before(jiffies, timeout)) {
868 if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED)
869 break;
870
871 usleep_range(100, 200);
872 }
873
874 if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) {
875 dev_err(dev, "Falcon failed to start, state: %#x\n",
876 csb_readl(tegra, XUSB_FALC_CPUCTL));
877 return -EIO;
878 }
879
880 timestamp = le32_to_cpu(header->fwimg_created_time);
9506b146 881 time64_to_tm(timestamp, 0, &time);
e84fce0f
TR		 882
883 dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
884 time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
885 time.tm_hour, time.tm_min, time.tm_sec);
886
887 return 0;
888}
889
890static int tegra_xusb_probe(struct platform_device *pdev)
891{
892 struct tegra_xusb_mbox_msg msg;
893 struct resource *res, *regs;
894 struct tegra_xusb *tegra;
895 struct xhci_hcd *xhci;
896 unsigned int i, j, k;
897 struct phy *phy;
898 int err;
899
900 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
901
902 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
903 if (!tegra)
904 return -ENOMEM;
905
906 tegra->soc = of_device_get_match_data(&pdev->dev);
907 mutex_init(&tegra->lock);
908 tegra->dev = &pdev->dev;
909
910 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
911 tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
912 if (IS_ERR(tegra->regs))
913 return PTR_ERR(tegra->regs);
914
915 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
916 tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res);
917 if (IS_ERR(tegra->fpci_base))
918 return PTR_ERR(tegra->fpci_base);
919
920 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
921 tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res);
922 if (IS_ERR(tegra->ipfs_base))
923 return PTR_ERR(tegra->ipfs_base);
924
925 tegra->xhci_irq = platform_get_irq(pdev, 0);
926 if (tegra->xhci_irq < 0)
927 return tegra->xhci_irq;
928
929 tegra->mbox_irq = platform_get_irq(pdev, 1);
930 if (tegra->mbox_irq < 0)
931 return tegra->mbox_irq;
932
933 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
934 if (IS_ERR(tegra->padctl))
935 return PTR_ERR(tegra->padctl);
936
937 tegra->host_rst = devm_reset_control_get(&pdev->dev, "xusb_host");
938 if (IS_ERR(tegra->host_rst)) {
939 err = PTR_ERR(tegra->host_rst);
940 dev_err(&pdev->dev, "failed to get xusb_host reset: %d\n", err);
941 goto put_padctl;
942 }
943
944 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
945 if (IS_ERR(tegra->ss_rst)) {
946 err = PTR_ERR(tegra->ss_rst);
947 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", err);
948 goto put_padctl;
949 }
950
951 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
952 if (IS_ERR(tegra->host_clk)) {
953 err = PTR_ERR(tegra->host_clk);
954 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
955 goto put_padctl;
956 }
957
958 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
959 if (IS_ERR(tegra->falcon_clk)) {
960 err = PTR_ERR(tegra->falcon_clk);
961 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
962 goto put_padctl;
963 }
964
965 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
966 if (IS_ERR(tegra->ss_clk)) {
967 err = PTR_ERR(tegra->ss_clk);
968 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
969 goto put_padctl;
970 }
971
972 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
973 if (IS_ERR(tegra->ss_src_clk)) {
974 err = PTR_ERR(tegra->ss_src_clk);
975 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
976 goto put_padctl;
977 }
978
979 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
980 if (IS_ERR(tegra->hs_src_clk)) {
981 err = PTR_ERR(tegra->hs_src_clk);
982 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
983 goto put_padctl;
984 }
985
986 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
987 if (IS_ERR(tegra->fs_src_clk)) {
988 err = PTR_ERR(tegra->fs_src_clk);
989 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
990 goto put_padctl;
991 }
992
993 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
994 if (IS_ERR(tegra->pll_u_480m)) {
995 err = PTR_ERR(tegra->pll_u_480m);
996 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
997 goto put_padctl;
998 }
999
1000 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1001 if (IS_ERR(tegra->clk_m)) {
1002 err = PTR_ERR(tegra->clk_m);
1003 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1004 goto put_padctl;
1005 }
1006
1007 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1008 if (IS_ERR(tegra->pll_e)) {
1009 err = PTR_ERR(tegra->pll_e);
1010 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1011 goto put_padctl;
1012 }
1013
1014 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1015 sizeof(*tegra->supplies), GFP_KERNEL);
1016 if (!tegra->supplies) {
1017 err = -ENOMEM;
1018 goto put_padctl;
1019 }
1020
1021 for (i = 0; i < tegra->soc->num_supplies; i++)
1022 tegra->supplies[i].supply = tegra->soc->supply_names[i];
1023
1024 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1025 tegra->supplies);
1026 if (err) {
1027 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1028 goto put_padctl;
1029 }
1030
1031 for (i = 0; i < tegra->soc->num_types; i++)
1032 tegra->num_phys += tegra->soc->phy_types[i].num;
1033
1034 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1035 sizeof(*tegra->phys), GFP_KERNEL);
1036 if (!tegra->phys) {
e84fce0f
TR		 1037 err = -ENOMEM;
1038 goto put_padctl;
1039 }
1040
1041 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1042 char prop[8];
1043
1044 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1045 snprintf(prop, sizeof(prop), "%s-%d",
1046 tegra->soc->phy_types[i].name, j);
1047
1048 phy = devm_phy_optional_get(&pdev->dev, prop);
1049 if (IS_ERR(phy)) {
1050 dev_err(&pdev->dev,
1051 "failed to get PHY %s: %ld\n", prop,
1052 PTR_ERR(phy));
1053 err = PTR_ERR(phy);
1054 goto put_padctl;
1055 }
1056
1057 tegra->phys[k++] = phy;
1058 }
1059 }
1060
1061 err = tegra_xusb_clk_enable(tegra);
1062 if (err) {
1063 dev_err(&pdev->dev, "failed to enable clocks: %d\n", err);
1064 goto put_padctl;
1065 }
1066
1067 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
1068 if (err) {
1069 dev_err(&pdev->dev, "failed to enable regulators: %d\n", err);
1070 goto disable_clk;
1071 }
1072
1073 err = tegra_xusb_phy_enable(tegra);
1074 if (err < 0) {
1075 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1076 goto disable_regulator;
1077 }
1078
1079 tegra_xusb_ipfs_config(tegra, regs);
1080
1081 err = tegra_xusb_load_firmware(tegra);
1082 if (err < 0) {
1083 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1084 goto disable_phy;
1085 }
1086
1087 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1088 dev_name(&pdev->dev));
1089 if (!tegra->hcd) {
1090 err = -ENOMEM;
1091 goto disable_phy;
1092 }
1093
1094 /*
1095 * This must happen after usb_create_hcd(), because usb_create_hcd()
1096 * will overwrite the drvdata of the device with the hcd it creates.
1097 */
1098 platform_set_drvdata(pdev, tegra);
1099
1100 tegra->hcd->regs = tegra->regs;
1101 tegra->hcd->rsrc_start = regs->start;
1102 tegra->hcd->rsrc_len = resource_size(regs);
1103
1104 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1105 if (err < 0) {
1106 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1107 goto put_usb2;
1108 }
1109
1110 device_wakeup_enable(tegra->hcd->self.controller);
1111
1112 xhci = hcd_to_xhci(tegra->hcd);
1113
1114 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1115 &pdev->dev,
1116 dev_name(&pdev->dev),
1117 tegra->hcd);
1118 if (!xhci->shared_hcd) {
1119 dev_err(&pdev->dev, "failed to create shared HCD\n");
b175b38a 1120 err = -ENOMEM;
e84fce0f
TR		 1121 goto remove_usb2;
1122 }
1123
1124 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1125 if (err < 0) {
1126 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1127 goto put_usb3;
1128 }
1129
1130 mutex_lock(&tegra->lock);
1131
1132 /* Enable firmware messages from controller. */
1133 msg.cmd = MBOX_CMD_MSG_ENABLED;
1134 msg.data = 0;
1135
1136 err = tegra_xusb_mbox_send(tegra, &msg);
1137 if (err < 0) {
1138 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1139 mutex_unlock(&tegra->lock);
1140 goto remove_usb3;
1141 }
1142
1143 mutex_unlock(&tegra->lock);
1144
1145 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1146 tegra_xusb_mbox_irq,
1147 tegra_xusb_mbox_thread, 0,
1148 dev_name(&pdev->dev), tegra);
1149 if (err < 0) {
1150 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1151 goto remove_usb3;
1152 }
1153
1154 return 0;
1155
1156remove_usb3:
1157 usb_remove_hcd(xhci->shared_hcd);
1158put_usb3:
1159 usb_put_hcd(xhci->shared_hcd);
1160remove_usb2:
1161 usb_remove_hcd(tegra->hcd);
1162put_usb2:
1163 usb_put_hcd(tegra->hcd);
1164disable_phy:
1165 tegra_xusb_phy_disable(tegra);
1166disable_regulator:
1167 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1168disable_clk:
1169 tegra_xusb_clk_disable(tegra);
1170put_padctl:
1171 tegra_xusb_padctl_put(tegra->padctl);
1172 return err;
1173}
1174
1175static int tegra_xusb_remove(struct platform_device *pdev)
1176{
1177 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1178 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1179
1180 usb_remove_hcd(xhci->shared_hcd);
1181 usb_put_hcd(xhci->shared_hcd);
1182 usb_remove_hcd(tegra->hcd);
1183 usb_put_hcd(tegra->hcd);
1184
1185 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1186 tegra->fw.phys);
1187
1188 tegra_xusb_phy_disable(tegra);
1189 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1190 tegra_xusb_clk_disable(tegra);
1191
1192 tegra_xusb_padctl_put(tegra->padctl);
1193
1194 return 0;
1195}
1196
1197#ifdef CONFIG_PM_SLEEP
1198static int tegra_xusb_suspend(struct device *dev)
1199{
1200 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1201 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1202 bool wakeup = device_may_wakeup(dev);
1203
1204 /* TODO: Powergate controller across suspend/resume. */
1205 return xhci_suspend(xhci, wakeup);
1206}
1207
1208static int tegra_xusb_resume(struct device *dev)
1209{
1210 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1211 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1212
1213 return xhci_resume(xhci, 0);
1214}
1215#endif
1216
1217static const struct dev_pm_ops tegra_xusb_pm_ops = {
1218 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
1219};
1220
1221static const char * const tegra124_supply_names[] = {
1222 "avddio-pex",
1223 "dvddio-pex",
1224 "avdd-usb",
1225 "avdd-pll-utmip",
1226 "avdd-pll-erefe",
1227 "avdd-usb-ss-pll",
1228 "hvdd-usb-ss",
1229 "hvdd-usb-ss-pll-e",
1230};
1231
1232static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
1233 { .name = "usb3", .num = 2, },
1234 { .name = "usb2", .num = 3, },
1235 { .name = "hsic", .num = 2, },
1236};
1237
1238static const struct tegra_xusb_soc tegra124_soc = {
1239 .firmware = "nvidia/tegra124/xusb.bin",
1240 .supply_names = tegra124_supply_names,
1241 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
1242 .phy_types = tegra124_phy_types,
1243 .num_types = ARRAY_SIZE(tegra124_phy_types),
1244 .ports = {
1245 .usb2 = { .offset = 4, .count = 4, },
1246 .hsic = { .offset = 6, .count = 2, },
1247 .usb3 = { .offset = 0, .count = 2, },
1248 },
ab065e96 1249 .scale_ss_clock = true,
e84fce0f
TR		 1250};
1251MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
1252
ab065e96
TR		 1253static const char * const tegra210_supply_names[] = {
1254 "dvddio-pex",
1255 "hvddio-pex",
1256 "avdd-usb",
1257 "avdd-pll-utmip",
1258 "avdd-pll-uerefe",
1259 "dvdd-pex-pll",
1260 "hvdd-pex-pll-e",
1261};
1262
1263static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
1264 { .name = "usb3", .num = 4, },
1265 { .name = "usb2", .num = 4, },
1266 { .name = "hsic", .num = 1, },
1267};
1268
1269static const struct tegra_xusb_soc tegra210_soc = {
1270 .firmware = "nvidia/tegra210/xusb.bin",
1271 .supply_names = tegra210_supply_names,
1272 .num_supplies = ARRAY_SIZE(tegra210_supply_names),
1273 .phy_types = tegra210_phy_types,
1274 .num_types = ARRAY_SIZE(tegra210_phy_types),
1275 .ports = {
1276 .usb2 = { .offset = 4, .count = 4, },
1277 .hsic = { .offset = 8, .count = 1, },
1278 .usb3 = { .offset = 0, .count = 4, },
1279 },
1280 .scale_ss_clock = false,
1281};
1282MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
1283
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TR		 1284static const struct of_device_id tegra_xusb_of_match[] = {
1285 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
ab065e96 1286 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
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TR		 1287 { },
1288};
1289MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
1290
1291static struct platform_driver tegra_xusb_driver = {
1292 .probe = tegra_xusb_probe,
1293 .remove = tegra_xusb_remove,
1294 .driver = {
1295 .name = "tegra-xusb",
1296 .pm = &tegra_xusb_pm_ops,
1297 .of_match_table = tegra_xusb_of_match,
1298 },
1299};
1300
1301static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
1302{
1303 xhci->quirks |= XHCI_PLAT;
1304}
1305
1306static int tegra_xhci_setup(struct usb_hcd *hcd)
1307{
1308 return xhci_gen_setup(hcd, tegra_xhci_quirks);
1309}
1310
1311static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
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TR		 1312 .reset = tegra_xhci_setup,
1313};
1314
1315static int __init tegra_xusb_init(void)
1316{
1317 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
1318
1319 return platform_driver_register(&tegra_xusb_driver);
1320}
1321module_init(tegra_xusb_init);
1322
1323static void __exit tegra_xusb_exit(void)
1324{
1325 platform_driver_unregister(&tegra_xusb_driver);
1326}
1327module_exit(tegra_xusb_exit);
1328
1329MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
1330MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
1331MODULE_LICENSE("GPL v2");
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