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Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
66d4eadd SS |
2 | /* |
3 | * xHCI host controller driver | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
66d4eadd SS |
9 | */ |
10 | ||
43b86af8 | 11 | #include <linux/pci.h> |
66d4eadd | 12 | #include <linux/irq.h> |
8df75f42 | 13 | #include <linux/log2.h> |
66d4eadd | 14 | #include <linux/module.h> |
b0567b3f | 15 | #include <linux/moduleparam.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
71c731a2 | 17 | #include <linux/dmi.h> |
008eb957 | 18 | #include <linux/dma-mapping.h> |
66d4eadd SS |
19 | |
20 | #include "xhci.h" | |
84a99f6f | 21 | #include "xhci-trace.h" |
0cbd4b34 | 22 | #include "xhci-mtk.h" |
02b6fdc2 | 23 | #include "xhci-debugfs.h" |
b6c33de0 | 24 | #include "xhci-dbgcap.h" |
66d4eadd SS |
25 | |
26 | #define DRIVER_AUTHOR "Sarah Sharp" | |
27 | #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver" | |
28 | ||
a1377e53 LB |
29 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
30 | ||
b0567b3f SS |
31 | /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */ |
32 | static int link_quirk; | |
33 | module_param(link_quirk, int, S_IRUGO | S_IWUSR); | |
34 | MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB"); | |
35 | ||
45d29576 MZ |
36 | static unsigned long long quirks; |
37 | module_param(quirks, ullong, S_IRUGO); | |
4e6a1ee7 TI |
38 | MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default"); |
39 | ||
66d4eadd SS |
40 | /* TODO: copied from ehci-hcd.c - can this be refactored? */ |
41 | /* | |
2611bd18 | 42 | * xhci_handshake - spin reading hc until handshake completes or fails |
66d4eadd SS |
43 | * @ptr: address of hc register to be read |
44 | * @mask: bits to look at in result of read | |
45 | * @done: value of those bits when handshake succeeds | |
46 | * @usec: timeout in microseconds | |
47 | * | |
48 | * Returns negative errno, or zero on success | |
49 | * | |
50 | * Success happens when the "mask" bits have the specified value (hardware | |
51 | * handshake done). There are two failure modes: "usec" have passed (major | |
52 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
53 | */ | |
dc0b177c | 54 | int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec) |
66d4eadd SS |
55 | { |
56 | u32 result; | |
57 | ||
58 | do { | |
b0ba9720 | 59 | result = readl(ptr); |
66d4eadd SS |
60 | if (result == ~(u32)0) /* card removed */ |
61 | return -ENODEV; | |
62 | result &= mask; | |
63 | if (result == done) | |
64 | return 0; | |
65 | udelay(1); | |
66 | usec--; | |
67 | } while (usec > 0); | |
68 | return -ETIMEDOUT; | |
69 | } | |
70 | ||
71 | /* | |
4f0f0bae | 72 | * Disable interrupts and begin the xHCI halting process. |
66d4eadd | 73 | */ |
4f0f0bae | 74 | void xhci_quiesce(struct xhci_hcd *xhci) |
66d4eadd SS |
75 | { |
76 | u32 halted; | |
77 | u32 cmd; | |
78 | u32 mask; | |
79 | ||
66d4eadd | 80 | mask = ~(XHCI_IRQS); |
b0ba9720 | 81 | halted = readl(&xhci->op_regs->status) & STS_HALT; |
66d4eadd SS |
82 | if (!halted) |
83 | mask &= ~CMD_RUN; | |
84 | ||
b0ba9720 | 85 | cmd = readl(&xhci->op_regs->command); |
66d4eadd | 86 | cmd &= mask; |
204b7793 | 87 | writel(cmd, &xhci->op_regs->command); |
4f0f0bae SS |
88 | } |
89 | ||
90 | /* | |
91 | * Force HC into halt state. | |
92 | * | |
93 | * Disable any IRQs and clear the run/stop bit. | |
94 | * HC will complete any current and actively pipelined transactions, and | |
bdfca502 | 95 | * should halt within 16 ms of the run/stop bit being cleared. |
4f0f0bae | 96 | * Read HC Halted bit in the status register to see when the HC is finished. |
4f0f0bae SS |
97 | */ |
98 | int xhci_halt(struct xhci_hcd *xhci) | |
99 | { | |
c6cc27c7 | 100 | int ret; |
d195fcff | 101 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC"); |
4f0f0bae | 102 | xhci_quiesce(xhci); |
66d4eadd | 103 | |
dc0b177c | 104 | ret = xhci_handshake(&xhci->op_regs->status, |
66d4eadd | 105 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); |
99154fd3 MN |
106 | if (ret) { |
107 | xhci_warn(xhci, "Host halt failed, %d\n", ret); | |
108 | return ret; | |
109 | } | |
110 | xhci->xhc_state |= XHCI_STATE_HALTED; | |
111 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
c6cc27c7 | 112 | return ret; |
66d4eadd SS |
113 | } |
114 | ||
ed07453f SS |
115 | /* |
116 | * Set the run bit and wait for the host to be running. | |
117 | */ | |
26bba5c7 | 118 | int xhci_start(struct xhci_hcd *xhci) |
ed07453f SS |
119 | { |
120 | u32 temp; | |
121 | int ret; | |
122 | ||
b0ba9720 | 123 | temp = readl(&xhci->op_regs->command); |
ed07453f | 124 | temp |= (CMD_RUN); |
d195fcff | 125 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.", |
ed07453f | 126 | temp); |
204b7793 | 127 | writel(temp, &xhci->op_regs->command); |
ed07453f SS |
128 | |
129 | /* | |
130 | * Wait for the HCHalted Status bit to be 0 to indicate the host is | |
131 | * running. | |
132 | */ | |
dc0b177c | 133 | ret = xhci_handshake(&xhci->op_regs->status, |
ed07453f SS |
134 | STS_HALT, 0, XHCI_MAX_HALT_USEC); |
135 | if (ret == -ETIMEDOUT) | |
136 | xhci_err(xhci, "Host took too long to start, " | |
137 | "waited %u microseconds.\n", | |
138 | XHCI_MAX_HALT_USEC); | |
c6cc27c7 | 139 | if (!ret) |
98d74f9c MN |
140 | /* clear state flags. Including dying, halted or removing */ |
141 | xhci->xhc_state = 0; | |
e5bfeab0 | 142 | |
ed07453f SS |
143 | return ret; |
144 | } | |
145 | ||
66d4eadd | 146 | /* |
ac04e6ff | 147 | * Reset a halted HC. |
66d4eadd SS |
148 | * |
149 | * This resets pipelines, timers, counters, state machines, etc. | |
150 | * Transactions will be terminated immediately, and operational registers | |
151 | * will be set to their defaults. | |
152 | */ | |
153 | int xhci_reset(struct xhci_hcd *xhci) | |
154 | { | |
155 | u32 command; | |
156 | u32 state; | |
f370b996 | 157 | int ret, i; |
66d4eadd | 158 | |
b0ba9720 | 159 | state = readl(&xhci->op_regs->status); |
c11ae038 MN |
160 | |
161 | if (state == ~(u32)0) { | |
162 | xhci_warn(xhci, "Host not accessible, reset failed.\n"); | |
163 | return -ENODEV; | |
164 | } | |
165 | ||
d3512f63 SS |
166 | if ((state & STS_HALT) == 0) { |
167 | xhci_warn(xhci, "Host controller not halted, aborting reset.\n"); | |
168 | return 0; | |
169 | } | |
66d4eadd | 170 | |
d195fcff | 171 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC"); |
b0ba9720 | 172 | command = readl(&xhci->op_regs->command); |
66d4eadd | 173 | command |= CMD_RESET; |
204b7793 | 174 | writel(command, &xhci->op_regs->command); |
66d4eadd | 175 | |
a5964396 RM |
176 | /* Existing Intel xHCI controllers require a delay of 1 mS, |
177 | * after setting the CMD_RESET bit, and before accessing any | |
178 | * HC registers. This allows the HC to complete the | |
179 | * reset operation and be ready for HC register access. | |
180 | * Without this delay, the subsequent HC register access, | |
181 | * may result in a system hang very rarely. | |
182 | */ | |
183 | if (xhci->quirks & XHCI_INTEL_HOST) | |
184 | udelay(1000); | |
185 | ||
dc0b177c | 186 | ret = xhci_handshake(&xhci->op_regs->command, |
22ceac19 | 187 | CMD_RESET, 0, 10 * 1000 * 1000); |
2d62f3ee SS |
188 | if (ret) |
189 | return ret; | |
190 | ||
9da5a109 JC |
191 | if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL) |
192 | usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller)); | |
193 | ||
d195fcff XR |
194 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
195 | "Wait for controller to be ready for doorbell rings"); | |
2d62f3ee SS |
196 | /* |
197 | * xHCI cannot write to any doorbells or operational registers other | |
198 | * than status until the "Controller Not Ready" flag is cleared. | |
199 | */ | |
dc0b177c | 200 | ret = xhci_handshake(&xhci->op_regs->status, |
22ceac19 | 201 | STS_CNR, 0, 10 * 1000 * 1000); |
f370b996 | 202 | |
98871e94 | 203 | for (i = 0; i < 2; i++) { |
f370b996 AX |
204 | xhci->bus_state[i].port_c_suspend = 0; |
205 | xhci->bus_state[i].suspended_ports = 0; | |
206 | xhci->bus_state[i].resuming_ports = 0; | |
207 | } | |
208 | ||
209 | return ret; | |
66d4eadd SS |
210 | } |
211 | ||
43b86af8 | 212 | |
77d45b45 | 213 | #ifdef CONFIG_USB_PCI |
43b86af8 DN |
214 | /* |
215 | * Set up MSI | |
216 | */ | |
217 | static int xhci_setup_msi(struct xhci_hcd *xhci) | |
66d4eadd SS |
218 | { |
219 | int ret; | |
4c39d4b9 AB |
220 | /* |
221 | * TODO:Check with MSI Soc for sysdev | |
222 | */ | |
43b86af8 DN |
223 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
224 | ||
77d45b45 CH |
225 | ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); |
226 | if (ret < 0) { | |
d195fcff XR |
227 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
228 | "failed to allocate MSI entry"); | |
43b86af8 DN |
229 | return ret; |
230 | } | |
231 | ||
851ec164 | 232 | ret = request_irq(pdev->irq, xhci_msi_irq, |
43b86af8 DN |
233 | 0, "xhci_hcd", xhci_to_hcd(xhci)); |
234 | if (ret) { | |
d195fcff XR |
235 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
236 | "disable MSI interrupt"); | |
77d45b45 | 237 | pci_free_irq_vectors(pdev); |
43b86af8 DN |
238 | } |
239 | ||
240 | return ret; | |
241 | } | |
242 | ||
243 | /* | |
244 | * Set up MSI-X | |
245 | */ | |
246 | static int xhci_setup_msix(struct xhci_hcd *xhci) | |
247 | { | |
248 | int i, ret = 0; | |
0029227f AX |
249 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
250 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 251 | |
43b86af8 DN |
252 | /* |
253 | * calculate number of msi-x vectors supported. | |
254 | * - HCS_MAX_INTRS: the max number of interrupts the host can handle, | |
255 | * with max number of interrupters based on the xhci HCSPARAMS1. | |
256 | * - num_online_cpus: maximum msi-x vectors per CPUs core. | |
257 | * Add additional 1 vector to ensure always available interrupt. | |
258 | */ | |
259 | xhci->msix_count = min(num_online_cpus() + 1, | |
260 | HCS_MAX_INTRS(xhci->hcs_params1)); | |
261 | ||
77d45b45 CH |
262 | ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count, |
263 | PCI_IRQ_MSIX); | |
264 | if (ret < 0) { | |
d195fcff XR |
265 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
266 | "Failed to enable MSI-X"); | |
77d45b45 | 267 | return ret; |
66d4eadd SS |
268 | } |
269 | ||
43b86af8 | 270 | for (i = 0; i < xhci->msix_count; i++) { |
77d45b45 CH |
271 | ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0, |
272 | "xhci_hcd", xhci_to_hcd(xhci)); | |
43b86af8 DN |
273 | if (ret) |
274 | goto disable_msix; | |
66d4eadd | 275 | } |
43b86af8 | 276 | |
0029227f | 277 | hcd->msix_enabled = 1; |
43b86af8 | 278 | return ret; |
66d4eadd SS |
279 | |
280 | disable_msix: | |
d195fcff | 281 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); |
77d45b45 CH |
282 | while (--i >= 0) |
283 | free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); | |
284 | pci_free_irq_vectors(pdev); | |
66d4eadd SS |
285 | return ret; |
286 | } | |
287 | ||
66d4eadd SS |
288 | /* Free any IRQs and disable MSI-X */ |
289 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) | |
290 | { | |
0029227f AX |
291 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
292 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 293 | |
9005355a JP |
294 | if (xhci->quirks & XHCI_PLAT) |
295 | return; | |
296 | ||
77d45b45 CH |
297 | /* return if using legacy interrupt */ |
298 | if (hcd->irq > 0) | |
299 | return; | |
300 | ||
301 | if (hcd->msix_enabled) { | |
302 | int i; | |
43b86af8 | 303 | |
77d45b45 CH |
304 | for (i = 0; i < xhci->msix_count; i++) |
305 | free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); | |
43b86af8 | 306 | } else { |
77d45b45 | 307 | free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); |
43b86af8 DN |
308 | } |
309 | ||
77d45b45 | 310 | pci_free_irq_vectors(pdev); |
0029227f | 311 | hcd->msix_enabled = 0; |
66d4eadd | 312 | } |
66d4eadd | 313 | |
d5c82feb | 314 | static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
421aa841 | 315 | { |
77d45b45 CH |
316 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
317 | ||
318 | if (hcd->msix_enabled) { | |
319 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
320 | int i; | |
421aa841 | 321 | |
421aa841 | 322 | for (i = 0; i < xhci->msix_count; i++) |
77d45b45 | 323 | synchronize_irq(pci_irq_vector(pdev, i)); |
421aa841 SAS |
324 | } |
325 | } | |
326 | ||
327 | static int xhci_try_enable_msi(struct usb_hcd *hcd) | |
328 | { | |
329 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
52fb6125 | 330 | struct pci_dev *pdev; |
421aa841 SAS |
331 | int ret; |
332 | ||
52fb6125 SS |
333 | /* The xhci platform device has set up IRQs through usb_add_hcd. */ |
334 | if (xhci->quirks & XHCI_PLAT) | |
335 | return 0; | |
336 | ||
337 | pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
421aa841 SAS |
338 | /* |
339 | * Some Fresco Logic host controllers advertise MSI, but fail to | |
340 | * generate interrupts. Don't even try to enable MSI. | |
341 | */ | |
342 | if (xhci->quirks & XHCI_BROKEN_MSI) | |
00eed9c8 | 343 | goto legacy_irq; |
421aa841 SAS |
344 | |
345 | /* unregister the legacy interrupt */ | |
346 | if (hcd->irq) | |
347 | free_irq(hcd->irq, hcd); | |
cd70469d | 348 | hcd->irq = 0; |
421aa841 SAS |
349 | |
350 | ret = xhci_setup_msix(xhci); | |
351 | if (ret) | |
352 | /* fall back to msi*/ | |
353 | ret = xhci_setup_msi(xhci); | |
354 | ||
6a29beef PC |
355 | if (!ret) { |
356 | hcd->msi_enabled = 1; | |
421aa841 | 357 | return 0; |
6a29beef | 358 | } |
421aa841 | 359 | |
68d07f64 SS |
360 | if (!pdev->irq) { |
361 | xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); | |
362 | return -EINVAL; | |
363 | } | |
364 | ||
00eed9c8 | 365 | legacy_irq: |
79699437 AH |
366 | if (!strlen(hcd->irq_descr)) |
367 | snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", | |
368 | hcd->driver->description, hcd->self.busnum); | |
369 | ||
421aa841 SAS |
370 | /* fall back to legacy interrupt*/ |
371 | ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, | |
372 | hcd->irq_descr, hcd); | |
373 | if (ret) { | |
374 | xhci_err(xhci, "request interrupt %d failed\n", | |
375 | pdev->irq); | |
376 | return ret; | |
377 | } | |
378 | hcd->irq = pdev->irq; | |
379 | return 0; | |
380 | } | |
381 | ||
382 | #else | |
383 | ||
01bb59eb | 384 | static inline int xhci_try_enable_msi(struct usb_hcd *hcd) |
421aa841 SAS |
385 | { |
386 | return 0; | |
387 | } | |
388 | ||
01bb59eb | 389 | static inline void xhci_cleanup_msix(struct xhci_hcd *xhci) |
421aa841 SAS |
390 | { |
391 | } | |
392 | ||
01bb59eb | 393 | static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
421aa841 SAS |
394 | { |
395 | } | |
396 | ||
397 | #endif | |
398 | ||
e99e88a9 | 399 | static void compliance_mode_recovery(struct timer_list *t) |
71c731a2 AC |
400 | { |
401 | struct xhci_hcd *xhci; | |
402 | struct usb_hcd *hcd; | |
403 | u32 temp; | |
404 | int i; | |
405 | ||
e99e88a9 | 406 | xhci = from_timer(xhci, t, comp_mode_recovery_timer); |
71c731a2 AC |
407 | |
408 | for (i = 0; i < xhci->num_usb3_ports; i++) { | |
b0ba9720 | 409 | temp = readl(xhci->usb3_ports[i]); |
71c731a2 AC |
410 | if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) { |
411 | /* | |
412 | * Compliance Mode Detected. Letting USB Core | |
413 | * handle the Warm Reset | |
414 | */ | |
4bdfe4c3 XR |
415 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
416 | "Compliance mode detected->port %d", | |
71c731a2 | 417 | i + 1); |
4bdfe4c3 XR |
418 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
419 | "Attempting compliance mode recovery"); | |
71c731a2 AC |
420 | hcd = xhci->shared_hcd; |
421 | ||
422 | if (hcd->state == HC_STATE_SUSPENDED) | |
423 | usb_hcd_resume_root_hub(hcd); | |
424 | ||
425 | usb_hcd_poll_rh_status(hcd); | |
426 | } | |
427 | } | |
428 | ||
429 | if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1)) | |
430 | mod_timer(&xhci->comp_mode_recovery_timer, | |
431 | jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS)); | |
432 | } | |
433 | ||
434 | /* | |
435 | * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver | |
436 | * that causes ports behind that hardware to enter compliance mode sometimes. | |
437 | * The quirk creates a timer that polls every 2 seconds the link state of | |
438 | * each host controller's port and recovers it by issuing a Warm reset | |
439 | * if Compliance mode is detected, otherwise the port will become "dead" (no | |
440 | * device connections or disconnections will be detected anymore). Becasue no | |
441 | * status event is generated when entering compliance mode (per xhci spec), | |
442 | * this quirk is needed on systems that have the failing hardware installed. | |
443 | */ | |
444 | static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci) | |
445 | { | |
446 | xhci->port_status_u0 = 0; | |
e99e88a9 KC |
447 | timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery, |
448 | 0); | |
71c731a2 AC |
449 | xhci->comp_mode_recovery_timer.expires = jiffies + |
450 | msecs_to_jiffies(COMP_MODE_RCVRY_MSECS); | |
451 | ||
71c731a2 | 452 | add_timer(&xhci->comp_mode_recovery_timer); |
4bdfe4c3 XR |
453 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
454 | "Compliance mode recovery timer initialized"); | |
71c731a2 AC |
455 | } |
456 | ||
457 | /* | |
458 | * This function identifies the systems that have installed the SN65LVPE502CP | |
459 | * USB3.0 re-driver and that need the Compliance Mode Quirk. | |
460 | * Systems: | |
461 | * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820 | |
462 | */ | |
e1cd9727 | 463 | static bool xhci_compliance_mode_recovery_timer_quirk_check(void) |
71c731a2 AC |
464 | { |
465 | const char *dmi_product_name, *dmi_sys_vendor; | |
466 | ||
467 | dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); | |
468 | dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR); | |
457a73d3 VG |
469 | if (!dmi_product_name || !dmi_sys_vendor) |
470 | return false; | |
71c731a2 AC |
471 | |
472 | if (!(strstr(dmi_sys_vendor, "Hewlett-Packard"))) | |
473 | return false; | |
474 | ||
475 | if (strstr(dmi_product_name, "Z420") || | |
476 | strstr(dmi_product_name, "Z620") || | |
47080974 | 477 | strstr(dmi_product_name, "Z820") || |
b0e4e606 | 478 | strstr(dmi_product_name, "Z1 Workstation")) |
71c731a2 AC |
479 | return true; |
480 | ||
481 | return false; | |
482 | } | |
483 | ||
484 | static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci) | |
485 | { | |
486 | return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1)); | |
487 | } | |
488 | ||
489 | ||
66d4eadd SS |
490 | /* |
491 | * Initialize memory for HCD and xHC (one-time init). | |
492 | * | |
493 | * Program the PAGESIZE register, initialize the device context array, create | |
494 | * device contexts (?), set up a command ring segment (or two?), create event | |
495 | * ring (one for now). | |
496 | */ | |
3969384c | 497 | static int xhci_init(struct usb_hcd *hcd) |
66d4eadd SS |
498 | { |
499 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
500 | int retval = 0; | |
501 | ||
d195fcff | 502 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init"); |
66d4eadd | 503 | spin_lock_init(&xhci->lock); |
d7826599 | 504 | if (xhci->hci_version == 0x95 && link_quirk) { |
4bdfe4c3 XR |
505 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
506 | "QUIRK: Not clearing Link TRB chain bits."); | |
b0567b3f SS |
507 | xhci->quirks |= XHCI_LINK_TRB_QUIRK; |
508 | } else { | |
d195fcff XR |
509 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
510 | "xHCI doesn't need link TRB QUIRK"); | |
b0567b3f | 511 | } |
66d4eadd | 512 | retval = xhci_mem_init(xhci, GFP_KERNEL); |
d195fcff | 513 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init"); |
66d4eadd | 514 | |
71c731a2 | 515 | /* Initializing Compliance Mode Recovery Data If Needed */ |
c3897aa5 | 516 | if (xhci_compliance_mode_recovery_timer_quirk_check()) { |
71c731a2 AC |
517 | xhci->quirks |= XHCI_COMP_MODE_QUIRK; |
518 | compliance_mode_recovery_timer_init(xhci); | |
519 | } | |
520 | ||
66d4eadd SS |
521 | return retval; |
522 | } | |
523 | ||
7f84eef0 SS |
524 | /*-------------------------------------------------------------------------*/ |
525 | ||
7f84eef0 | 526 | |
f6ff0ac8 SS |
527 | static int xhci_run_finished(struct xhci_hcd *xhci) |
528 | { | |
529 | if (xhci_start(xhci)) { | |
530 | xhci_halt(xhci); | |
531 | return -ENODEV; | |
532 | } | |
533 | xhci->shared_hcd->state = HC_STATE_RUNNING; | |
c181bc5b | 534 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; |
f6ff0ac8 SS |
535 | |
536 | if (xhci->quirks & XHCI_NEC_HOST) | |
537 | xhci_ring_cmd_db(xhci); | |
538 | ||
d195fcff XR |
539 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
540 | "Finished xhci_run for USB3 roothub"); | |
f6ff0ac8 SS |
541 | return 0; |
542 | } | |
543 | ||
66d4eadd SS |
544 | /* |
545 | * Start the HC after it was halted. | |
546 | * | |
547 | * This function is called by the USB core when the HC driver is added. | |
548 | * Its opposite is xhci_stop(). | |
549 | * | |
550 | * xhci_init() must be called once before this function can be called. | |
551 | * Reset the HC, enable device slot contexts, program DCBAAP, and | |
552 | * set command ring pointer and event ring pointer. | |
553 | * | |
554 | * Setup MSI-X vectors and enable interrupts. | |
555 | */ | |
556 | int xhci_run(struct usb_hcd *hcd) | |
557 | { | |
558 | u32 temp; | |
8e595a5d | 559 | u64 temp_64; |
3fd1ec58 | 560 | int ret; |
66d4eadd | 561 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
66d4eadd | 562 | |
f6ff0ac8 SS |
563 | /* Start the xHCI host controller running only after the USB 2.0 roothub |
564 | * is setup. | |
565 | */ | |
66d4eadd | 566 | |
0f2a7930 | 567 | hcd->uses_new_polling = 1; |
f6ff0ac8 SS |
568 | if (!usb_hcd_is_primary_hcd(hcd)) |
569 | return xhci_run_finished(xhci); | |
0f2a7930 | 570 | |
d195fcff | 571 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run"); |
43b86af8 | 572 | |
3fd1ec58 | 573 | ret = xhci_try_enable_msi(hcd); |
43b86af8 | 574 | if (ret) |
3fd1ec58 | 575 | return ret; |
66d4eadd | 576 | |
66e49d87 SS |
577 | xhci_dbg_cmd_ptrs(xhci); |
578 | ||
579 | xhci_dbg(xhci, "ERST memory map follows:\n"); | |
580 | xhci_dbg_erst(xhci, &xhci->erst); | |
f7b2e403 | 581 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
66e49d87 | 582 | temp_64 &= ~ERST_PTR_MASK; |
d195fcff XR |
583 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
584 | "ERST deq = 64'h%0lx", (long unsigned int) temp_64); | |
66e49d87 | 585 | |
d195fcff XR |
586 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
587 | "// Set the interrupt modulation register"); | |
b0ba9720 | 588 | temp = readl(&xhci->ir_set->irq_control); |
a4d88302 | 589 | temp &= ~ER_IRQ_INTERVAL_MASK; |
0cbd4b34 CY |
590 | /* |
591 | * the increment interval is 8 times as much as that defined | |
592 | * in xHCI spec on MTK's controller | |
593 | */ | |
594 | temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160); | |
204b7793 | 595 | writel(temp, &xhci->ir_set->irq_control); |
66d4eadd SS |
596 | |
597 | /* Set the HCD state before we enable the irqs */ | |
b0ba9720 | 598 | temp = readl(&xhci->op_regs->command); |
66d4eadd | 599 | temp |= (CMD_EIE); |
d195fcff XR |
600 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
601 | "// Enable interrupts, cmd = 0x%x.", temp); | |
204b7793 | 602 | writel(temp, &xhci->op_regs->command); |
66d4eadd | 603 | |
b0ba9720 | 604 | temp = readl(&xhci->ir_set->irq_pending); |
d195fcff XR |
605 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
606 | "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", | |
700e2052 | 607 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); |
204b7793 | 608 | writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 609 | xhci_print_ir_set(xhci, 0); |
66d4eadd | 610 | |
ddba5cd0 MN |
611 | if (xhci->quirks & XHCI_NEC_HOST) { |
612 | struct xhci_command *command; | |
74e0b564 | 613 | |
ddba5cd0 MN |
614 | command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); |
615 | if (!command) | |
616 | return -ENOMEM; | |
74e0b564 | 617 | |
d6f5f071 | 618 | ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0, |
0238634d | 619 | TRB_TYPE(TRB_NEC_GET_FW)); |
d6f5f071 SW |
620 | if (ret) |
621 | xhci_free_command(xhci, command); | |
ddba5cd0 | 622 | } |
d195fcff XR |
623 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
624 | "Finished xhci_run for USB2 roothub"); | |
02b6fdc2 | 625 | |
b6c33de0 LB |
626 | xhci_dbc_init(xhci); |
627 | ||
02b6fdc2 LB |
628 | xhci_debugfs_init(xhci); |
629 | ||
f6ff0ac8 SS |
630 | return 0; |
631 | } | |
436e8c7d | 632 | EXPORT_SYMBOL_GPL(xhci_run); |
ed07453f | 633 | |
66d4eadd SS |
634 | /* |
635 | * Stop xHCI driver. | |
636 | * | |
637 | * This function is called by the USB core when the HC driver is removed. | |
638 | * Its opposite is xhci_run(). | |
639 | * | |
640 | * Disable device contexts, disable IRQs, and quiesce the HC. | |
641 | * Reset the HC, finish any completed transactions, and cleanup memory. | |
642 | */ | |
3969384c | 643 | static void xhci_stop(struct usb_hcd *hcd) |
66d4eadd SS |
644 | { |
645 | u32 temp; | |
646 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
647 | ||
8c24d6d7 | 648 | mutex_lock(&xhci->mutex); |
8c24d6d7 | 649 | |
fe190ed0 | 650 | /* Only halt host and free memory after both hcds are removed */ |
27a41a83 | 651 | if (!usb_hcd_is_primary_hcd(hcd)) { |
fe190ed0 JS |
652 | /* usb core will free this hcd shortly, unset pointer */ |
653 | xhci->shared_hcd = NULL; | |
27a41a83 GKB |
654 | mutex_unlock(&xhci->mutex); |
655 | return; | |
656 | } | |
66d4eadd | 657 | |
b6c33de0 LB |
658 | xhci_dbc_exit(xhci); |
659 | ||
fe190ed0 JS |
660 | spin_lock_irq(&xhci->lock); |
661 | xhci->xhc_state |= XHCI_STATE_HALTED; | |
662 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
663 | xhci_halt(xhci); | |
664 | xhci_reset(xhci); | |
665 | spin_unlock_irq(&xhci->lock); | |
666 | ||
40a9fb17 ZR |
667 | xhci_cleanup_msix(xhci); |
668 | ||
71c731a2 AC |
669 | /* Deleting Compliance Mode Recovery Timer */ |
670 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
58b1d799 | 671 | (!(xhci_all_ports_seen_u0(xhci)))) { |
71c731a2 | 672 | del_timer_sync(&xhci->comp_mode_recovery_timer); |
4bdfe4c3 XR |
673 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
674 | "%s: compliance mode recovery timer deleted", | |
58b1d799 TC |
675 | __func__); |
676 | } | |
71c731a2 | 677 | |
c41136b0 AX |
678 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
679 | usb_amd_dev_put(); | |
680 | ||
d195fcff XR |
681 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
682 | "// Disabling event ring interrupts"); | |
b0ba9720 | 683 | temp = readl(&xhci->op_regs->status); |
d1001ab4 | 684 | writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status); |
b0ba9720 | 685 | temp = readl(&xhci->ir_set->irq_pending); |
204b7793 | 686 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 687 | xhci_print_ir_set(xhci, 0); |
66d4eadd | 688 | |
d195fcff | 689 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory"); |
66d4eadd | 690 | xhci_mem_cleanup(xhci); |
0467ba5f | 691 | xhci_debugfs_exit(xhci); |
d195fcff XR |
692 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
693 | "xhci_stop completed - status = %x", | |
b0ba9720 | 694 | readl(&xhci->op_regs->status)); |
85ac90f8 | 695 | mutex_unlock(&xhci->mutex); |
66d4eadd SS |
696 | } |
697 | ||
698 | /* | |
699 | * Shutdown HC (not bus-specific) | |
700 | * | |
701 | * This is called when the machine is rebooting or halting. We assume that the | |
702 | * machine will be powered off, and the HC's internal state will be reset. | |
703 | * Don't bother to free memory. | |
f6ff0ac8 SS |
704 | * |
705 | * This will only ever be called with the main usb_hcd (the USB3 roothub). | |
66d4eadd | 706 | */ |
3969384c | 707 | static void xhci_shutdown(struct usb_hcd *hcd) |
66d4eadd SS |
708 | { |
709 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
710 | ||
052c7f9f | 711 | if (xhci->quirks & XHCI_SPURIOUS_REBOOT) |
4c39d4b9 | 712 | usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev)); |
e95829f4 | 713 | |
66d4eadd SS |
714 | spin_lock_irq(&xhci->lock); |
715 | xhci_halt(xhci); | |
638298dc TI |
716 | /* Workaround for spurious wakeups at shutdown with HSW */ |
717 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
718 | xhci_reset(xhci); | |
43b86af8 | 719 | spin_unlock_irq(&xhci->lock); |
66d4eadd | 720 | |
40a9fb17 ZR |
721 | xhci_cleanup_msix(xhci); |
722 | ||
d195fcff XR |
723 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
724 | "xhci_shutdown completed - status = %x", | |
b0ba9720 | 725 | readl(&xhci->op_regs->status)); |
638298dc TI |
726 | |
727 | /* Yet another workaround for spurious wakeups at shutdown with HSW */ | |
728 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
4c39d4b9 | 729 | pci_set_power_state(to_pci_dev(hcd->self.sysdev), PCI_D3hot); |
66d4eadd SS |
730 | } |
731 | ||
b5b5c3ac | 732 | #ifdef CONFIG_PM |
5535b1d5 AX |
733 | static void xhci_save_registers(struct xhci_hcd *xhci) |
734 | { | |
b0ba9720 XR |
735 | xhci->s3.command = readl(&xhci->op_regs->command); |
736 | xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification); | |
f7b2e403 | 737 | xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
b0ba9720 XR |
738 | xhci->s3.config_reg = readl(&xhci->op_regs->config_reg); |
739 | xhci->s3.erst_size = readl(&xhci->ir_set->erst_size); | |
f7b2e403 SS |
740 | xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
741 | xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | |
b0ba9720 XR |
742 | xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending); |
743 | xhci->s3.irq_control = readl(&xhci->ir_set->irq_control); | |
5535b1d5 AX |
744 | } |
745 | ||
746 | static void xhci_restore_registers(struct xhci_hcd *xhci) | |
747 | { | |
204b7793 XR |
748 | writel(xhci->s3.command, &xhci->op_regs->command); |
749 | writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification); | |
477632df | 750 | xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); |
204b7793 XR |
751 | writel(xhci->s3.config_reg, &xhci->op_regs->config_reg); |
752 | writel(xhci->s3.erst_size, &xhci->ir_set->erst_size); | |
477632df SS |
753 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); |
754 | xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue); | |
204b7793 XR |
755 | writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending); |
756 | writel(xhci->s3.irq_control, &xhci->ir_set->irq_control); | |
5535b1d5 AX |
757 | } |
758 | ||
89821320 SS |
759 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) |
760 | { | |
761 | u64 val_64; | |
762 | ||
763 | /* step 2: initialize command ring buffer */ | |
f7b2e403 | 764 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
89821320 SS |
765 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | |
766 | (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | |
767 | xhci->cmd_ring->dequeue) & | |
768 | (u64) ~CMD_RING_RSVD_BITS) | | |
769 | xhci->cmd_ring->cycle_state; | |
d195fcff XR |
770 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
771 | "// Setting command ring address to 0x%llx", | |
89821320 | 772 | (long unsigned long) val_64); |
477632df | 773 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); |
89821320 SS |
774 | } |
775 | ||
776 | /* | |
777 | * The whole command ring must be cleared to zero when we suspend the host. | |
778 | * | |
779 | * The host doesn't save the command ring pointer in the suspend well, so we | |
780 | * need to re-program it on resume. Unfortunately, the pointer must be 64-byte | |
781 | * aligned, because of the reserved bits in the command ring dequeue pointer | |
782 | * register. Therefore, we can't just set the dequeue pointer back in the | |
783 | * middle of the ring (TRBs are 16-byte aligned). | |
784 | */ | |
785 | static void xhci_clear_command_ring(struct xhci_hcd *xhci) | |
786 | { | |
787 | struct xhci_ring *ring; | |
788 | struct xhci_segment *seg; | |
789 | ||
790 | ring = xhci->cmd_ring; | |
791 | seg = ring->deq_seg; | |
792 | do { | |
158886cd AX |
793 | memset(seg->trbs, 0, |
794 | sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1)); | |
795 | seg->trbs[TRBS_PER_SEGMENT - 1].link.control &= | |
796 | cpu_to_le32(~TRB_CYCLE); | |
89821320 SS |
797 | seg = seg->next; |
798 | } while (seg != ring->deq_seg); | |
799 | ||
800 | /* Reset the software enqueue and dequeue pointers */ | |
801 | ring->deq_seg = ring->first_seg; | |
802 | ring->dequeue = ring->first_seg->trbs; | |
803 | ring->enq_seg = ring->deq_seg; | |
804 | ring->enqueue = ring->dequeue; | |
805 | ||
b008df60 | 806 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; |
89821320 SS |
807 | /* |
808 | * Ring is now zeroed, so the HW should look for change of ownership | |
809 | * when the cycle bit is set to 1. | |
810 | */ | |
811 | ring->cycle_state = 1; | |
812 | ||
813 | /* | |
814 | * Reset the hardware dequeue pointer. | |
815 | * Yes, this will need to be re-written after resume, but we're paranoid | |
816 | * and want to make sure the hardware doesn't access bogus memory | |
817 | * because, say, the BIOS or an SMI started the host without changing | |
818 | * the command ring pointers. | |
819 | */ | |
820 | xhci_set_cmd_ring_deq(xhci); | |
821 | } | |
822 | ||
a1377e53 LB |
823 | static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci) |
824 | { | |
825 | int port_index; | |
826 | __le32 __iomem **port_array; | |
827 | unsigned long flags; | |
828 | u32 t1, t2; | |
829 | ||
830 | spin_lock_irqsave(&xhci->lock, flags); | |
831 | ||
8a1115ff | 832 | /* disable usb3 ports Wake bits */ |
a1377e53 LB |
833 | port_index = xhci->num_usb3_ports; |
834 | port_array = xhci->usb3_ports; | |
835 | while (port_index--) { | |
836 | t1 = readl(port_array[port_index]); | |
837 | t1 = xhci_port_state_to_neutral(t1); | |
838 | t2 = t1 & ~PORT_WAKE_BITS; | |
839 | if (t1 != t2) | |
840 | writel(t2, port_array[port_index]); | |
841 | } | |
842 | ||
8a1115ff | 843 | /* disable usb2 ports Wake bits */ |
a1377e53 LB |
844 | port_index = xhci->num_usb2_ports; |
845 | port_array = xhci->usb2_ports; | |
846 | while (port_index--) { | |
847 | t1 = readl(port_array[port_index]); | |
848 | t1 = xhci_port_state_to_neutral(t1); | |
849 | t2 = t1 & ~PORT_WAKE_BITS; | |
850 | if (t1 != t2) | |
851 | writel(t2, port_array[port_index]); | |
852 | } | |
853 | ||
854 | spin_unlock_irqrestore(&xhci->lock, flags); | |
855 | } | |
856 | ||
006f19b2 MN |
857 | static bool xhci_pending_portevent(struct xhci_hcd *xhci) |
858 | { | |
859 | __le32 __iomem **port_array; | |
860 | int port_index; | |
861 | u32 status; | |
862 | u32 portsc; | |
863 | ||
864 | status = readl(&xhci->op_regs->status); | |
865 | if (status & STS_EINT) | |
866 | return true; | |
867 | /* | |
868 | * Checking STS_EINT is not enough as there is a lag between a change | |
869 | * bit being set and the Port Status Change Event that it generated | |
870 | * being written to the Event Ring. See note in xhci 1.1 section 4.19.2. | |
871 | */ | |
872 | ||
873 | port_index = xhci->num_usb2_ports; | |
874 | port_array = xhci->usb2_ports; | |
875 | while (port_index--) { | |
876 | portsc = readl(port_array[port_index]); | |
877 | if (portsc & PORT_CHANGE_MASK || | |
878 | (portsc & PORT_PLS_MASK) == XDEV_RESUME) | |
879 | return true; | |
880 | } | |
881 | port_index = xhci->num_usb3_ports; | |
882 | port_array = xhci->usb3_ports; | |
883 | while (port_index--) { | |
884 | portsc = readl(port_array[port_index]); | |
885 | if (portsc & PORT_CHANGE_MASK || | |
886 | (portsc & PORT_PLS_MASK) == XDEV_RESUME) | |
887 | return true; | |
888 | } | |
889 | return false; | |
890 | } | |
891 | ||
5535b1d5 AX |
892 | /* |
893 | * Stop HC (not bus-specific) | |
894 | * | |
895 | * This is called when the machine transition into S3/S4 mode. | |
896 | * | |
897 | */ | |
a1377e53 | 898 | int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup) |
5535b1d5 AX |
899 | { |
900 | int rc = 0; | |
455f5892 | 901 | unsigned int delay = XHCI_MAX_HALT_USEC; |
5535b1d5 AX |
902 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
903 | u32 command; | |
6a089ef9 | 904 | u32 res; |
5535b1d5 | 905 | |
9fa733f2 RQ |
906 | if (!hcd->state) |
907 | return 0; | |
908 | ||
77b84767 FB |
909 | if (hcd->state != HC_STATE_SUSPENDED || |
910 | xhci->shared_hcd->state != HC_STATE_SUSPENDED) | |
911 | return -EINVAL; | |
912 | ||
b6c33de0 LB |
913 | xhci_dbc_suspend(xhci); |
914 | ||
a1377e53 LB |
915 | /* Clear root port wake on bits if wakeup not allowed. */ |
916 | if (!do_wakeup) | |
917 | xhci_disable_port_wake_on_bits(xhci); | |
918 | ||
c52804a4 SS |
919 | /* Don't poll the roothubs on bus suspend. */ |
920 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
921 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
922 | del_timer_sync(&hcd->rh_timer); | |
14e61a1b AC |
923 | clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); |
924 | del_timer_sync(&xhci->shared_hcd->rh_timer); | |
c52804a4 | 925 | |
7c267cb7 KHF |
926 | if (xhci->quirks & XHCI_SUSPEND_DELAY) |
927 | usleep_range(1000, 1500); | |
928 | ||
5535b1d5 AX |
929 | spin_lock_irq(&xhci->lock); |
930 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
b3209379 | 931 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); |
5535b1d5 AX |
932 | /* step 1: stop endpoint */ |
933 | /* skipped assuming that port suspend has done */ | |
934 | ||
935 | /* step 2: clear Run/Stop bit */ | |
b0ba9720 | 936 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 937 | command &= ~CMD_RUN; |
204b7793 | 938 | writel(command, &xhci->op_regs->command); |
455f5892 ON |
939 | |
940 | /* Some chips from Fresco Logic need an extraordinary delay */ | |
941 | delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1; | |
942 | ||
dc0b177c | 943 | if (xhci_handshake(&xhci->op_regs->status, |
455f5892 | 944 | STS_HALT, STS_HALT, delay)) { |
5535b1d5 AX |
945 | xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n"); |
946 | spin_unlock_irq(&xhci->lock); | |
947 | return -ETIMEDOUT; | |
948 | } | |
89821320 | 949 | xhci_clear_command_ring(xhci); |
5535b1d5 AX |
950 | |
951 | /* step 3: save registers */ | |
952 | xhci_save_registers(xhci); | |
953 | ||
954 | /* step 4: set CSS flag */ | |
b0ba9720 | 955 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 956 | command |= CMD_CSS; |
204b7793 | 957 | writel(command, &xhci->op_regs->command); |
6a089ef9 | 958 | xhci->broken_suspend = 0; |
dc0b177c | 959 | if (xhci_handshake(&xhci->op_regs->status, |
2611bd18 | 960 | STS_SAVE, 0, 10 * 1000)) { |
6a089ef9 SS |
961 | /* |
962 | * AMD SNPS xHC 3.0 occasionally does not clear the | |
963 | * SSS bit of USBSTS and when driver tries to poll | |
964 | * to see if the xHC clears BIT(8) which never happens | |
965 | * and driver assumes that controller is not responding | |
966 | * and times out. To workaround this, its good to check | |
967 | * if SRE and HCE bits are not set (as per xhci | |
968 | * Section 5.4.2) and bypass the timeout. | |
969 | */ | |
970 | res = readl(&xhci->op_regs->status); | |
971 | if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) && | |
972 | (((res & STS_SRE) == 0) && | |
973 | ((res & STS_HCE) == 0))) { | |
974 | xhci->broken_suspend = 1; | |
975 | } else { | |
976 | xhci_warn(xhci, "WARN: xHC save state timeout\n"); | |
977 | spin_unlock_irq(&xhci->lock); | |
978 | return -ETIMEDOUT; | |
979 | } | |
5535b1d5 | 980 | } |
5535b1d5 AX |
981 | spin_unlock_irq(&xhci->lock); |
982 | ||
71c731a2 AC |
983 | /* |
984 | * Deleting Compliance Mode Recovery Timer because the xHCI Host | |
985 | * is about to be suspended. | |
986 | */ | |
987 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
988 | (!(xhci_all_ports_seen_u0(xhci)))) { | |
989 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
990 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
991 | "%s: compliance mode recovery timer deleted", | |
58b1d799 | 992 | __func__); |
71c731a2 AC |
993 | } |
994 | ||
0029227f AX |
995 | /* step 5: remove core well power */ |
996 | /* synchronize irq when using MSI-X */ | |
421aa841 | 997 | xhci_msix_sync_irqs(xhci); |
0029227f | 998 | |
5535b1d5 AX |
999 | return rc; |
1000 | } | |
436e8c7d | 1001 | EXPORT_SYMBOL_GPL(xhci_suspend); |
5535b1d5 AX |
1002 | |
1003 | /* | |
1004 | * start xHC (not bus-specific) | |
1005 | * | |
1006 | * This is called when the machine transition from S3/S4 mode. | |
1007 | * | |
1008 | */ | |
1009 | int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |
1010 | { | |
006f19b2 | 1011 | u32 command, temp = 0; |
5535b1d5 | 1012 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
65b22f93 | 1013 | struct usb_hcd *secondary_hcd; |
f69e3120 | 1014 | int retval = 0; |
77df9e0b | 1015 | bool comp_timer_running = false; |
5535b1d5 | 1016 | |
9fa733f2 RQ |
1017 | if (!hcd->state) |
1018 | return 0; | |
1019 | ||
f6ff0ac8 | 1020 | /* Wait a bit if either of the roothubs need to settle from the |
25985edc | 1021 | * transition into bus suspend. |
20b67cf5 | 1022 | */ |
f6ff0ac8 SS |
1023 | if (time_before(jiffies, xhci->bus_state[0].next_statechange) || |
1024 | time_before(jiffies, | |
1025 | xhci->bus_state[1].next_statechange)) | |
5535b1d5 AX |
1026 | msleep(100); |
1027 | ||
f69e3120 AS |
1028 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
1029 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); | |
1030 | ||
5535b1d5 | 1031 | spin_lock_irq(&xhci->lock); |
6a089ef9 | 1032 | if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend) |
c877b3b2 | 1033 | hibernated = true; |
5535b1d5 AX |
1034 | |
1035 | if (!hibernated) { | |
1036 | /* step 1: restore register */ | |
1037 | xhci_restore_registers(xhci); | |
1038 | /* step 2: initialize command ring buffer */ | |
89821320 | 1039 | xhci_set_cmd_ring_deq(xhci); |
5535b1d5 AX |
1040 | /* step 3: restore state and start state*/ |
1041 | /* step 3: set CRS flag */ | |
b0ba9720 | 1042 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 1043 | command |= CMD_CRS; |
204b7793 | 1044 | writel(command, &xhci->op_regs->command); |
dc0b177c | 1045 | if (xhci_handshake(&xhci->op_regs->status, |
622eb783 AX |
1046 | STS_RESTORE, 0, 10 * 1000)) { |
1047 | xhci_warn(xhci, "WARN: xHC restore state timeout\n"); | |
5535b1d5 AX |
1048 | spin_unlock_irq(&xhci->lock); |
1049 | return -ETIMEDOUT; | |
1050 | } | |
b0ba9720 | 1051 | temp = readl(&xhci->op_regs->status); |
5535b1d5 AX |
1052 | } |
1053 | ||
1054 | /* If restore operation fails, re-initialize the HC during resume */ | |
1055 | if ((temp & STS_SRE) || hibernated) { | |
77df9e0b TC |
1056 | |
1057 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
1058 | !(xhci_all_ports_seen_u0(xhci))) { | |
1059 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
1060 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1061 | "Compliance Mode Recovery Timer deleted!"); | |
77df9e0b TC |
1062 | } |
1063 | ||
fedd383e SS |
1064 | /* Let the USB core know _both_ roothubs lost power. */ |
1065 | usb_root_hub_lost_power(xhci->main_hcd->self.root_hub); | |
1066 | usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub); | |
5535b1d5 AX |
1067 | |
1068 | xhci_dbg(xhci, "Stop HCD\n"); | |
1069 | xhci_halt(xhci); | |
1070 | xhci_reset(xhci); | |
5535b1d5 | 1071 | spin_unlock_irq(&xhci->lock); |
0029227f | 1072 | xhci_cleanup_msix(xhci); |
5535b1d5 | 1073 | |
5535b1d5 | 1074 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); |
b0ba9720 | 1075 | temp = readl(&xhci->op_regs->status); |
d1001ab4 | 1076 | writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status); |
b0ba9720 | 1077 | temp = readl(&xhci->ir_set->irq_pending); |
204b7793 | 1078 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 1079 | xhci_print_ir_set(xhci, 0); |
5535b1d5 AX |
1080 | |
1081 | xhci_dbg(xhci, "cleaning up memory\n"); | |
1082 | xhci_mem_cleanup(xhci); | |
96cb3baf | 1083 | xhci_debugfs_exit(xhci); |
5535b1d5 | 1084 | xhci_dbg(xhci, "xhci_stop completed - status = %x\n", |
b0ba9720 | 1085 | readl(&xhci->op_regs->status)); |
5535b1d5 | 1086 | |
65b22f93 SS |
1087 | /* USB core calls the PCI reinit and start functions twice: |
1088 | * first with the primary HCD, and then with the secondary HCD. | |
1089 | * If we don't do the same, the host will never be started. | |
1090 | */ | |
1091 | if (!usb_hcd_is_primary_hcd(hcd)) | |
1092 | secondary_hcd = hcd; | |
1093 | else | |
1094 | secondary_hcd = xhci->shared_hcd; | |
1095 | ||
1096 | xhci_dbg(xhci, "Initialize the xhci_hcd\n"); | |
1097 | retval = xhci_init(hcd->primary_hcd); | |
5535b1d5 AX |
1098 | if (retval) |
1099 | return retval; | |
77df9e0b TC |
1100 | comp_timer_running = true; |
1101 | ||
65b22f93 SS |
1102 | xhci_dbg(xhci, "Start the primary HCD\n"); |
1103 | retval = xhci_run(hcd->primary_hcd); | |
b3209379 | 1104 | if (!retval) { |
f69e3120 AS |
1105 | xhci_dbg(xhci, "Start the secondary HCD\n"); |
1106 | retval = xhci_run(secondary_hcd); | |
b3209379 | 1107 | } |
5535b1d5 | 1108 | hcd->state = HC_STATE_SUSPENDED; |
b3209379 | 1109 | xhci->shared_hcd->state = HC_STATE_SUSPENDED; |
f69e3120 | 1110 | goto done; |
5535b1d5 AX |
1111 | } |
1112 | ||
5535b1d5 | 1113 | /* step 4: set Run/Stop bit */ |
b0ba9720 | 1114 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 1115 | command |= CMD_RUN; |
204b7793 | 1116 | writel(command, &xhci->op_regs->command); |
dc0b177c | 1117 | xhci_handshake(&xhci->op_regs->status, STS_HALT, |
5535b1d5 AX |
1118 | 0, 250 * 1000); |
1119 | ||
1120 | /* step 5: walk topology and initialize portsc, | |
1121 | * portpmsc and portli | |
1122 | */ | |
1123 | /* this is done in bus_resume */ | |
1124 | ||
1125 | /* step 6: restart each of the previously | |
1126 | * Running endpoints by ringing their doorbells | |
1127 | */ | |
1128 | ||
5535b1d5 | 1129 | spin_unlock_irq(&xhci->lock); |
f69e3120 | 1130 | |
b6c33de0 LB |
1131 | xhci_dbc_resume(xhci); |
1132 | ||
f69e3120 AS |
1133 | done: |
1134 | if (retval == 0) { | |
d6236f6d | 1135 | /* Resume root hubs only when have pending events. */ |
006f19b2 | 1136 | if (xhci_pending_portevent(xhci)) { |
d6236f6d | 1137 | usb_hcd_resume_root_hub(xhci->shared_hcd); |
671ffdff | 1138 | usb_hcd_resume_root_hub(hcd); |
d6236f6d | 1139 | } |
f69e3120 | 1140 | } |
71c731a2 AC |
1141 | |
1142 | /* | |
1143 | * If system is subject to the Quirk, Compliance Mode Timer needs to | |
1144 | * be re-initialized Always after a system resume. Ports are subject | |
1145 | * to suffer the Compliance Mode issue again. It doesn't matter if | |
1146 | * ports have entered previously to U0 before system's suspension. | |
1147 | */ | |
77df9e0b | 1148 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running) |
71c731a2 AC |
1149 | compliance_mode_recovery_timer_init(xhci); |
1150 | ||
9da5a109 JC |
1151 | if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL) |
1152 | usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller)); | |
1153 | ||
c52804a4 SS |
1154 | /* Re-enable port polling. */ |
1155 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
14e61a1b AC |
1156 | set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); |
1157 | usb_hcd_poll_rh_status(xhci->shared_hcd); | |
671ffdff MN |
1158 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
1159 | usb_hcd_poll_rh_status(hcd); | |
c52804a4 | 1160 | |
f69e3120 | 1161 | return retval; |
5535b1d5 | 1162 | } |
436e8c7d | 1163 | EXPORT_SYMBOL_GPL(xhci_resume); |
b5b5c3ac SS |
1164 | #endif /* CONFIG_PM */ |
1165 | ||
7f84eef0 SS |
1166 | /*-------------------------------------------------------------------------*/ |
1167 | ||
d0e96f5a SS |
1168 | /** |
1169 | * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and | |
1170 | * HCDs. Find the index for an endpoint given its descriptor. Use the return | |
1171 | * value to right shift 1 for the bitmask. | |
1172 | * | |
1173 | * Index = (epnum * 2) + direction - 1, | |
1174 | * where direction = 0 for OUT, 1 for IN. | |
1175 | * For control endpoints, the IN index is used (OUT index is unused), so | |
1176 | * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) | |
1177 | */ | |
1178 | unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc) | |
1179 | { | |
1180 | unsigned int index; | |
1181 | if (usb_endpoint_xfer_control(desc)) | |
1182 | index = (unsigned int) (usb_endpoint_num(desc)*2); | |
1183 | else | |
1184 | index = (unsigned int) (usb_endpoint_num(desc)*2) + | |
1185 | (usb_endpoint_dir_in(desc) ? 1 : 0) - 1; | |
1186 | return index; | |
1187 | } | |
1188 | ||
01c5f447 JW |
1189 | /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint |
1190 | * address from the XHCI endpoint index. | |
1191 | */ | |
1192 | unsigned int xhci_get_endpoint_address(unsigned int ep_index) | |
1193 | { | |
1194 | unsigned int number = DIV_ROUND_UP(ep_index, 2); | |
1195 | unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN; | |
1196 | return direction | number; | |
1197 | } | |
1198 | ||
f94e0186 SS |
1199 | /* Find the flag for this endpoint (for use in the control context). Use the |
1200 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1201 | * bit 1, etc. | |
1202 | */ | |
3969384c | 1203 | static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc) |
f94e0186 SS |
1204 | { |
1205 | return 1 << (xhci_get_endpoint_index(desc) + 1); | |
1206 | } | |
1207 | ||
ac9d8fe7 SS |
1208 | /* Find the flag for this endpoint (for use in the control context). Use the |
1209 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1210 | * bit 1, etc. | |
1211 | */ | |
3969384c | 1212 | static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index) |
ac9d8fe7 SS |
1213 | { |
1214 | return 1 << (ep_index + 1); | |
1215 | } | |
1216 | ||
f94e0186 SS |
1217 | /* Compute the last valid endpoint context index. Basically, this is the |
1218 | * endpoint index plus one. For slot contexts with more than valid endpoint, | |
1219 | * we find the most significant bit set in the added contexts flags. | |
1220 | * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000 | |
1221 | * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one. | |
1222 | */ | |
ac9d8fe7 | 1223 | unsigned int xhci_last_valid_endpoint(u32 added_ctxs) |
f94e0186 SS |
1224 | { |
1225 | return fls(added_ctxs) - 1; | |
1226 | } | |
1227 | ||
d0e96f5a SS |
1228 | /* Returns 1 if the arguments are OK; |
1229 | * returns 0 this is a root hub; returns -EINVAL for NULL pointers. | |
1230 | */ | |
8212a49d | 1231 | static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev, |
64927730 AX |
1232 | struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev, |
1233 | const char *func) { | |
1234 | struct xhci_hcd *xhci; | |
1235 | struct xhci_virt_device *virt_dev; | |
1236 | ||
d0e96f5a | 1237 | if (!hcd || (check_ep && !ep) || !udev) { |
5c1127d3 | 1238 | pr_debug("xHCI %s called with invalid args\n", func); |
d0e96f5a SS |
1239 | return -EINVAL; |
1240 | } | |
1241 | if (!udev->parent) { | |
5c1127d3 | 1242 | pr_debug("xHCI %s called for root hub\n", func); |
d0e96f5a SS |
1243 | return 0; |
1244 | } | |
64927730 | 1245 | |
7bd89b40 | 1246 | xhci = hcd_to_xhci(hcd); |
64927730 | 1247 | if (check_virt_dev) { |
73ddc247 | 1248 | if (!udev->slot_id || !xhci->devs[udev->slot_id]) { |
5c1127d3 XR |
1249 | xhci_dbg(xhci, "xHCI %s called with unaddressed device\n", |
1250 | func); | |
64927730 AX |
1251 | return -EINVAL; |
1252 | } | |
1253 | ||
1254 | virt_dev = xhci->devs[udev->slot_id]; | |
1255 | if (virt_dev->udev != udev) { | |
5c1127d3 | 1256 | xhci_dbg(xhci, "xHCI %s called with udev and " |
64927730 AX |
1257 | "virt_dev does not match\n", func); |
1258 | return -EINVAL; | |
1259 | } | |
d0e96f5a | 1260 | } |
64927730 | 1261 | |
203a8661 SS |
1262 | if (xhci->xhc_state & XHCI_STATE_HALTED) |
1263 | return -ENODEV; | |
1264 | ||
d0e96f5a SS |
1265 | return 1; |
1266 | } | |
1267 | ||
2d3f1fac | 1268 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, |
913a8a34 SS |
1269 | struct usb_device *udev, struct xhci_command *command, |
1270 | bool ctx_change, bool must_succeed); | |
2d3f1fac SS |
1271 | |
1272 | /* | |
1273 | * Full speed devices may have a max packet size greater than 8 bytes, but the | |
1274 | * USB core doesn't know that until it reads the first 8 bytes of the | |
1275 | * descriptor. If the usb_device's max packet size changes after that point, | |
1276 | * we need to issue an evaluate context command and wait on it. | |
1277 | */ | |
1278 | static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id, | |
1279 | unsigned int ep_index, struct urb *urb) | |
1280 | { | |
2d3f1fac SS |
1281 | struct xhci_container_ctx *out_ctx; |
1282 | struct xhci_input_control_ctx *ctrl_ctx; | |
1283 | struct xhci_ep_ctx *ep_ctx; | |
ddba5cd0 | 1284 | struct xhci_command *command; |
2d3f1fac SS |
1285 | int max_packet_size; |
1286 | int hw_max_packet_size; | |
1287 | int ret = 0; | |
1288 | ||
1289 | out_ctx = xhci->devs[slot_id]->out_ctx; | |
1290 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); | |
28ccd296 | 1291 | hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); |
29cc8897 | 1292 | max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc); |
2d3f1fac | 1293 | if (hw_max_packet_size != max_packet_size) { |
3a7fa5be XR |
1294 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1295 | "Max Packet Size for ep 0 changed."); | |
1296 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, | |
1297 | "Max packet size in usb_device = %d", | |
2d3f1fac | 1298 | max_packet_size); |
3a7fa5be XR |
1299 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1300 | "Max packet size in xHCI HW = %d", | |
2d3f1fac | 1301 | hw_max_packet_size); |
3a7fa5be XR |
1302 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1303 | "Issuing evaluate context command."); | |
2d3f1fac | 1304 | |
92f8e767 SS |
1305 | /* Set up the input context flags for the command */ |
1306 | /* FIXME: This won't work if a non-default control endpoint | |
1307 | * changes max packet sizes. | |
1308 | */ | |
ddba5cd0 MN |
1309 | |
1310 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); | |
1311 | if (!command) | |
1312 | return -ENOMEM; | |
1313 | ||
1314 | command->in_ctx = xhci->devs[slot_id]->in_ctx; | |
4daf9df5 | 1315 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 SS |
1316 | if (!ctrl_ctx) { |
1317 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1318 | __func__); | |
ddba5cd0 MN |
1319 | ret = -ENOMEM; |
1320 | goto command_cleanup; | |
92f8e767 | 1321 | } |
2d3f1fac | 1322 | /* Set up the modified control endpoint 0 */ |
913a8a34 SS |
1323 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
1324 | xhci->devs[slot_id]->out_ctx, ep_index); | |
92f8e767 | 1325 | |
ddba5cd0 | 1326 | ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index); |
28ccd296 ME |
1327 | ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK); |
1328 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); | |
2d3f1fac | 1329 | |
28ccd296 | 1330 | ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); |
2d3f1fac SS |
1331 | ctrl_ctx->drop_flags = 0; |
1332 | ||
ddba5cd0 | 1333 | ret = xhci_configure_endpoint(xhci, urb->dev, command, |
913a8a34 | 1334 | true, false); |
2d3f1fac SS |
1335 | |
1336 | /* Clean up the input context for later use by bandwidth | |
1337 | * functions. | |
1338 | */ | |
28ccd296 | 1339 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); |
ddba5cd0 MN |
1340 | command_cleanup: |
1341 | kfree(command->completion); | |
1342 | kfree(command); | |
2d3f1fac SS |
1343 | } |
1344 | return ret; | |
1345 | } | |
1346 | ||
d0e96f5a SS |
1347 | /* |
1348 | * non-error returns are a promise to giveback() the urb later | |
1349 | * we drop ownership so next owner (or urb unlink) can get it | |
1350 | */ | |
3969384c | 1351 | static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) |
d0e96f5a SS |
1352 | { |
1353 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
1354 | unsigned long flags; | |
1355 | int ret = 0; | |
6969408d | 1356 | unsigned int slot_id, ep_index, ep_state; |
8e51adcc | 1357 | struct urb_priv *urb_priv; |
7e64b037 | 1358 | int num_tds; |
2d3f1fac | 1359 | |
64927730 AX |
1360 | if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, |
1361 | true, true, __func__) <= 0) | |
d0e96f5a SS |
1362 | return -EINVAL; |
1363 | ||
1364 | slot_id = urb->dev->slot_id; | |
1365 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
d0e96f5a | 1366 | |
541c7d43 | 1367 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
d0e96f5a SS |
1368 | if (!in_interrupt()) |
1369 | xhci_dbg(xhci, "urb submitted during PCI suspend\n"); | |
6969408d | 1370 | return -ESHUTDOWN; |
d0e96f5a | 1371 | } |
8e51adcc AX |
1372 | |
1373 | if (usb_endpoint_xfer_isoc(&urb->ep->desc)) | |
e6f7caa3 | 1374 | num_tds = urb->number_of_packets; |
4758dcd1 RA |
1375 | else if (usb_endpoint_is_bulk_out(&urb->ep->desc) && |
1376 | urb->transfer_buffer_length > 0 && | |
1377 | urb->transfer_flags & URB_ZERO_PACKET && | |
1378 | !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc))) | |
e6f7caa3 | 1379 | num_tds = 2; |
8e51adcc | 1380 | else |
e6f7caa3 | 1381 | num_tds = 1; |
8e51adcc AX |
1382 | |
1383 | urb_priv = kzalloc(sizeof(struct urb_priv) + | |
7e64b037 | 1384 | num_tds * sizeof(struct xhci_td), mem_flags); |
8e51adcc AX |
1385 | if (!urb_priv) |
1386 | return -ENOMEM; | |
1387 | ||
9ef7fbbb MN |
1388 | urb_priv->num_tds = num_tds; |
1389 | urb_priv->num_tds_done = 0; | |
8e51adcc AX |
1390 | urb->hcpriv = urb_priv; |
1391 | ||
5abdc2e6 FB |
1392 | trace_xhci_urb_enqueue(urb); |
1393 | ||
2d3f1fac SS |
1394 | if (usb_endpoint_xfer_control(&urb->ep->desc)) { |
1395 | /* Check to see if the max packet size for the default control | |
1396 | * endpoint changed during FS device enumeration | |
1397 | */ | |
1398 | if (urb->dev->speed == USB_SPEED_FULL) { | |
1399 | ret = xhci_check_maxpacket(xhci, slot_id, | |
1400 | ep_index, urb); | |
d13565c1 | 1401 | if (ret < 0) { |
4daf9df5 | 1402 | xhci_urb_free_priv(urb_priv); |
d13565c1 | 1403 | urb->hcpriv = NULL; |
2d3f1fac | 1404 | return ret; |
d13565c1 | 1405 | } |
2d3f1fac | 1406 | } |
6969408d | 1407 | } |
2d3f1fac | 1408 | |
6969408d MN |
1409 | spin_lock_irqsave(&xhci->lock, flags); |
1410 | ||
1411 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
1412 | xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n", | |
1413 | urb->ep->desc.bEndpointAddress, urb); | |
1414 | ret = -ESHUTDOWN; | |
1415 | goto free_priv; | |
1416 | } | |
1417 | ||
1418 | switch (usb_endpoint_type(&urb->ep->desc)) { | |
1419 | ||
1420 | case USB_ENDPOINT_XFER_CONTROL: | |
b11069f5 | 1421 | ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb, |
6969408d MN |
1422 | slot_id, ep_index); |
1423 | break; | |
1424 | case USB_ENDPOINT_XFER_BULK: | |
1425 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
1426 | if (ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) { | |
1427 | xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n", | |
1428 | ep_state); | |
8df75f42 | 1429 | ret = -EINVAL; |
6969408d | 1430 | break; |
8df75f42 | 1431 | } |
6969408d MN |
1432 | ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, |
1433 | slot_id, ep_index); | |
1434 | break; | |
1435 | ||
1436 | ||
1437 | case USB_ENDPOINT_XFER_INT: | |
624defa1 SS |
1438 | ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb, |
1439 | slot_id, ep_index); | |
6969408d MN |
1440 | break; |
1441 | ||
1442 | case USB_ENDPOINT_XFER_ISOC: | |
787f4e5a AX |
1443 | ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb, |
1444 | slot_id, ep_index); | |
2d3f1fac | 1445 | } |
6969408d MN |
1446 | |
1447 | if (ret) { | |
d13565c1 | 1448 | free_priv: |
6969408d MN |
1449 | xhci_urb_free_priv(urb_priv); |
1450 | urb->hcpriv = NULL; | |
1451 | } | |
6f5165cf | 1452 | spin_unlock_irqrestore(&xhci->lock, flags); |
d13565c1 | 1453 | return ret; |
d0e96f5a SS |
1454 | } |
1455 | ||
ae636747 SS |
1456 | /* |
1457 | * Remove the URB's TD from the endpoint ring. This may cause the HC to stop | |
1458 | * USB transfers, potentially stopping in the middle of a TRB buffer. The HC | |
1459 | * should pick up where it left off in the TD, unless a Set Transfer Ring | |
1460 | * Dequeue Pointer is issued. | |
1461 | * | |
1462 | * The TRBs that make up the buffers for the canceled URB will be "removed" from | |
1463 | * the ring. Since the ring is a contiguous structure, they can't be physically | |
1464 | * removed. Instead, there are two options: | |
1465 | * | |
1466 | * 1) If the HC is in the middle of processing the URB to be canceled, we | |
1467 | * simply move the ring's dequeue pointer past those TRBs using the Set | |
1468 | * Transfer Ring Dequeue Pointer command. This will be the common case, | |
1469 | * when drivers timeout on the last submitted URB and attempt to cancel. | |
1470 | * | |
1471 | * 2) If the HC is in the middle of a different TD, we turn the TRBs into a | |
1472 | * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The | |
1473 | * HC will need to invalidate the any TRBs it has cached after the stop | |
1474 | * endpoint command, as noted in the xHCI 0.95 errata. | |
1475 | * | |
1476 | * 3) The TD may have completed by the time the Stop Endpoint Command | |
1477 | * completes, so software needs to handle that case too. | |
1478 | * | |
1479 | * This function should protect against the TD enqueueing code ringing the | |
1480 | * doorbell while this code is waiting for a Stop Endpoint command to complete. | |
1481 | * It also needs to account for multiple cancellations on happening at the same | |
1482 | * time for the same endpoint. | |
1483 | * | |
1484 | * Note that this function can be called in any context, or so says | |
1485 | * usb_hcd_unlink_urb() | |
d0e96f5a | 1486 | */ |
3969384c | 1487 | static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
d0e96f5a | 1488 | { |
ae636747 | 1489 | unsigned long flags; |
8e51adcc | 1490 | int ret, i; |
e34b2fbf | 1491 | u32 temp; |
ae636747 | 1492 | struct xhci_hcd *xhci; |
8e51adcc | 1493 | struct urb_priv *urb_priv; |
ae636747 SS |
1494 | struct xhci_td *td; |
1495 | unsigned int ep_index; | |
1496 | struct xhci_ring *ep_ring; | |
63a0d9ab | 1497 | struct xhci_virt_ep *ep; |
ddba5cd0 | 1498 | struct xhci_command *command; |
d3519b9d | 1499 | struct xhci_virt_device *vdev; |
ae636747 SS |
1500 | |
1501 | xhci = hcd_to_xhci(hcd); | |
1502 | spin_lock_irqsave(&xhci->lock, flags); | |
5abdc2e6 FB |
1503 | |
1504 | trace_xhci_urb_dequeue(urb); | |
1505 | ||
ae636747 SS |
1506 | /* Make sure the URB hasn't completed or been unlinked already */ |
1507 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); | |
d3519b9d | 1508 | if (ret) |
ae636747 | 1509 | goto done; |
d3519b9d MN |
1510 | |
1511 | /* give back URB now if we can't queue it for cancel */ | |
1512 | vdev = xhci->devs[urb->dev->slot_id]; | |
1513 | urb_priv = urb->hcpriv; | |
1514 | if (!vdev || !urb_priv) | |
1515 | goto err_giveback; | |
1516 | ||
1517 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
1518 | ep = &vdev->eps[ep_index]; | |
1519 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); | |
1520 | if (!ep || !ep_ring) | |
1521 | goto err_giveback; | |
1522 | ||
d9f11ba9 | 1523 | /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */ |
b0ba9720 | 1524 | temp = readl(&xhci->op_regs->status); |
d9f11ba9 MN |
1525 | if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) { |
1526 | xhci_hc_died(xhci); | |
1527 | goto done; | |
1528 | } | |
1529 | ||
1530 | if (xhci->xhc_state & XHCI_STATE_HALTED) { | |
aa50b290 | 1531 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
d9f11ba9 | 1532 | "HC halted, freeing TD manually."); |
9ef7fbbb | 1533 | for (i = urb_priv->num_tds_done; |
d3519b9d | 1534 | i < urb_priv->num_tds; |
5c821711 | 1535 | i++) { |
7e64b037 | 1536 | td = &urb_priv->td[i]; |
585df1d9 SS |
1537 | if (!list_empty(&td->td_list)) |
1538 | list_del_init(&td->td_list); | |
1539 | if (!list_empty(&td->cancelled_td_list)) | |
1540 | list_del_init(&td->cancelled_td_list); | |
1541 | } | |
d3519b9d | 1542 | goto err_giveback; |
e34b2fbf | 1543 | } |
ae636747 | 1544 | |
9ef7fbbb MN |
1545 | i = urb_priv->num_tds_done; |
1546 | if (i < urb_priv->num_tds) | |
aa50b290 XR |
1547 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1548 | "Cancel URB %p, dev %s, ep 0x%x, " | |
1549 | "starting at offset 0x%llx", | |
79688acf SS |
1550 | urb, urb->dev->devpath, |
1551 | urb->ep->desc.bEndpointAddress, | |
1552 | (unsigned long long) xhci_trb_virt_to_dma( | |
7e64b037 MN |
1553 | urb_priv->td[i].start_seg, |
1554 | urb_priv->td[i].first_trb)); | |
79688acf | 1555 | |
9ef7fbbb | 1556 | for (; i < urb_priv->num_tds; i++) { |
7e64b037 | 1557 | td = &urb_priv->td[i]; |
8e51adcc AX |
1558 | list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); |
1559 | } | |
1560 | ||
ae636747 SS |
1561 | /* Queue a stop endpoint command, but only if this is |
1562 | * the first cancellation to be handled. | |
1563 | */ | |
9983a5fc | 1564 | if (!(ep->ep_state & EP_STOP_CMD_PENDING)) { |
ddba5cd0 | 1565 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); |
a0ee619f HG |
1566 | if (!command) { |
1567 | ret = -ENOMEM; | |
1568 | goto done; | |
1569 | } | |
9983a5fc | 1570 | ep->ep_state |= EP_STOP_CMD_PENDING; |
6f5165cf SS |
1571 | ep->stop_cmd_timer.expires = jiffies + |
1572 | XHCI_STOP_EP_CMD_TIMEOUT * HZ; | |
1573 | add_timer(&ep->stop_cmd_timer); | |
ddba5cd0 MN |
1574 | xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id, |
1575 | ep_index, 0); | |
23e3be11 | 1576 | xhci_ring_cmd_db(xhci); |
ae636747 SS |
1577 | } |
1578 | done: | |
1579 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1580 | return ret; | |
d3519b9d MN |
1581 | |
1582 | err_giveback: | |
1583 | if (urb_priv) | |
1584 | xhci_urb_free_priv(urb_priv); | |
1585 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
1586 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1587 | usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN); | |
1588 | return ret; | |
d0e96f5a SS |
1589 | } |
1590 | ||
f94e0186 SS |
1591 | /* Drop an endpoint from a new bandwidth configuration for this device. |
1592 | * Only one call to this function is allowed per endpoint before | |
1593 | * check_bandwidth() or reset_bandwidth() must be called. | |
1594 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1595 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1596 | * different endpoint descriptor in usb_host_endpoint. | |
1597 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1598 | * not allowed. | |
f88ba78d SS |
1599 | * |
1600 | * The USB core will not allow URBs to be queued to an endpoint that is being | |
1601 | * disabled, so there's no need for mutual exclusion to protect | |
1602 | * the xhci->devs[slot_id] structure. | |
f94e0186 | 1603 | */ |
3969384c | 1604 | static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, |
f94e0186 SS |
1605 | struct usb_host_endpoint *ep) |
1606 | { | |
f94e0186 | 1607 | struct xhci_hcd *xhci; |
d115b048 JY |
1608 | struct xhci_container_ctx *in_ctx, *out_ctx; |
1609 | struct xhci_input_control_ctx *ctrl_ctx; | |
f94e0186 SS |
1610 | unsigned int ep_index; |
1611 | struct xhci_ep_ctx *ep_ctx; | |
1612 | u32 drop_flag; | |
d6759133 | 1613 | u32 new_add_flags, new_drop_flags; |
f94e0186 SS |
1614 | int ret; |
1615 | ||
64927730 | 1616 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
f94e0186 SS |
1617 | if (ret <= 0) |
1618 | return ret; | |
1619 | xhci = hcd_to_xhci(hcd); | |
fe6c6c13 SS |
1620 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1621 | return -ENODEV; | |
f94e0186 | 1622 | |
fe6c6c13 | 1623 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
1624 | drop_flag = xhci_get_endpoint_flag(&ep->desc); |
1625 | if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) { | |
1626 | xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n", | |
1627 | __func__, drop_flag); | |
1628 | return 0; | |
1629 | } | |
1630 | ||
f94e0186 | 1631 | in_ctx = xhci->devs[udev->slot_id]->in_ctx; |
d115b048 | 1632 | out_ctx = xhci->devs[udev->slot_id]->out_ctx; |
4daf9df5 | 1633 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
1634 | if (!ctrl_ctx) { |
1635 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1636 | __func__); | |
1637 | return 0; | |
1638 | } | |
1639 | ||
f94e0186 | 1640 | ep_index = xhci_get_endpoint_index(&ep->desc); |
d115b048 | 1641 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
f94e0186 SS |
1642 | /* If the HC already knows the endpoint is disabled, |
1643 | * or the HCD has noted it is disabled, ignore this request | |
1644 | */ | |
5071e6b2 | 1645 | if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) || |
28ccd296 ME |
1646 | le32_to_cpu(ctrl_ctx->drop_flags) & |
1647 | xhci_get_endpoint_flag(&ep->desc)) { | |
a6134136 HG |
1648 | /* Do not warn when called after a usb_device_reset */ |
1649 | if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL) | |
1650 | xhci_warn(xhci, "xHCI %s called with disabled ep %p\n", | |
1651 | __func__, ep); | |
f94e0186 SS |
1652 | return 0; |
1653 | } | |
1654 | ||
28ccd296 ME |
1655 | ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag); |
1656 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
f94e0186 | 1657 | |
28ccd296 ME |
1658 | ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag); |
1659 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 | 1660 | |
02b6fdc2 LB |
1661 | xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index); |
1662 | ||
f94e0186 SS |
1663 | xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep); |
1664 | ||
0cbd4b34 CY |
1665 | if (xhci->quirks & XHCI_MTK_HOST) |
1666 | xhci_mtk_drop_ep_quirk(hcd, udev, ep); | |
1667 | ||
d6759133 | 1668 | xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n", |
f94e0186 SS |
1669 | (unsigned int) ep->desc.bEndpointAddress, |
1670 | udev->slot_id, | |
1671 | (unsigned int) new_drop_flags, | |
d6759133 | 1672 | (unsigned int) new_add_flags); |
f94e0186 SS |
1673 | return 0; |
1674 | } | |
1675 | ||
1676 | /* Add an endpoint to a new possible bandwidth configuration for this device. | |
1677 | * Only one call to this function is allowed per endpoint before | |
1678 | * check_bandwidth() or reset_bandwidth() must be called. | |
1679 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1680 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1681 | * different endpoint descriptor in usb_host_endpoint. | |
1682 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1683 | * not allowed. | |
f88ba78d SS |
1684 | * |
1685 | * The USB core will not allow URBs to be queued to an endpoint until the | |
1686 | * configuration or alt setting is installed in the device, so there's no need | |
1687 | * for mutual exclusion to protect the xhci->devs[slot_id] structure. | |
f94e0186 | 1688 | */ |
3969384c | 1689 | static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, |
f94e0186 SS |
1690 | struct usb_host_endpoint *ep) |
1691 | { | |
f94e0186 | 1692 | struct xhci_hcd *xhci; |
92c9691b | 1693 | struct xhci_container_ctx *in_ctx; |
f94e0186 | 1694 | unsigned int ep_index; |
d115b048 | 1695 | struct xhci_input_control_ctx *ctrl_ctx; |
f94e0186 | 1696 | u32 added_ctxs; |
d6759133 | 1697 | u32 new_add_flags, new_drop_flags; |
fa75ac37 | 1698 | struct xhci_virt_device *virt_dev; |
f94e0186 SS |
1699 | int ret = 0; |
1700 | ||
64927730 | 1701 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
a1587d97 SS |
1702 | if (ret <= 0) { |
1703 | /* So we won't queue a reset ep command for a root hub */ | |
1704 | ep->hcpriv = NULL; | |
f94e0186 | 1705 | return ret; |
a1587d97 | 1706 | } |
f94e0186 | 1707 | xhci = hcd_to_xhci(hcd); |
fe6c6c13 SS |
1708 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1709 | return -ENODEV; | |
f94e0186 SS |
1710 | |
1711 | added_ctxs = xhci_get_endpoint_flag(&ep->desc); | |
f94e0186 SS |
1712 | if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) { |
1713 | /* FIXME when we have to issue an evaluate endpoint command to | |
1714 | * deal with ep0 max packet size changing once we get the | |
1715 | * descriptors | |
1716 | */ | |
1717 | xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n", | |
1718 | __func__, added_ctxs); | |
1719 | return 0; | |
1720 | } | |
1721 | ||
fa75ac37 SS |
1722 | virt_dev = xhci->devs[udev->slot_id]; |
1723 | in_ctx = virt_dev->in_ctx; | |
4daf9df5 | 1724 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
1725 | if (!ctrl_ctx) { |
1726 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1727 | __func__); | |
1728 | return 0; | |
1729 | } | |
fa75ac37 | 1730 | |
92f8e767 | 1731 | ep_index = xhci_get_endpoint_index(&ep->desc); |
fa75ac37 SS |
1732 | /* If this endpoint is already in use, and the upper layers are trying |
1733 | * to add it again without dropping it, reject the addition. | |
1734 | */ | |
1735 | if (virt_dev->eps[ep_index].ring && | |
92c9691b | 1736 | !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) { |
fa75ac37 SS |
1737 | xhci_warn(xhci, "Trying to add endpoint 0x%x " |
1738 | "without dropping it.\n", | |
1739 | (unsigned int) ep->desc.bEndpointAddress); | |
1740 | return -EINVAL; | |
1741 | } | |
1742 | ||
f94e0186 SS |
1743 | /* If the HCD has already noted the endpoint is enabled, |
1744 | * ignore this request. | |
1745 | */ | |
92c9691b | 1746 | if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) { |
700e2052 GKH |
1747 | xhci_warn(xhci, "xHCI %s called with enabled ep %p\n", |
1748 | __func__, ep); | |
f94e0186 SS |
1749 | return 0; |
1750 | } | |
1751 | ||
f88ba78d SS |
1752 | /* |
1753 | * Configuration and alternate setting changes must be done in | |
1754 | * process context, not interrupt context (or so documenation | |
1755 | * for usb_set_interface() and usb_set_configuration() claim). | |
1756 | */ | |
fa75ac37 | 1757 | if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) { |
f94e0186 SS |
1758 | dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n", |
1759 | __func__, ep->desc.bEndpointAddress); | |
f94e0186 SS |
1760 | return -ENOMEM; |
1761 | } | |
1762 | ||
0cbd4b34 CY |
1763 | if (xhci->quirks & XHCI_MTK_HOST) { |
1764 | ret = xhci_mtk_add_ep_quirk(hcd, udev, ep); | |
1765 | if (ret < 0) { | |
9821786d LB |
1766 | xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring); |
1767 | virt_dev->eps[ep_index].new_ring = NULL; | |
0cbd4b34 CY |
1768 | return ret; |
1769 | } | |
1770 | } | |
1771 | ||
28ccd296 ME |
1772 | ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs); |
1773 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 SS |
1774 | |
1775 | /* If xhci_endpoint_disable() was called for this endpoint, but the | |
1776 | * xHC hasn't been notified yet through the check_bandwidth() call, | |
1777 | * this re-adds a new state for the endpoint from the new endpoint | |
1778 | * descriptors. We must drop and re-add this endpoint, so we leave the | |
1779 | * drop flags alone. | |
1780 | */ | |
28ccd296 | 1781 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); |
f94e0186 | 1782 | |
a1587d97 SS |
1783 | /* Store the usb_device pointer for later use */ |
1784 | ep->hcpriv = udev; | |
1785 | ||
02b6fdc2 LB |
1786 | xhci_debugfs_create_endpoint(xhci, virt_dev, ep_index); |
1787 | ||
d6759133 | 1788 | xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n", |
f94e0186 SS |
1789 | (unsigned int) ep->desc.bEndpointAddress, |
1790 | udev->slot_id, | |
1791 | (unsigned int) new_drop_flags, | |
d6759133 | 1792 | (unsigned int) new_add_flags); |
f94e0186 SS |
1793 | return 0; |
1794 | } | |
1795 | ||
d115b048 | 1796 | static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev) |
f94e0186 | 1797 | { |
d115b048 | 1798 | struct xhci_input_control_ctx *ctrl_ctx; |
f94e0186 | 1799 | struct xhci_ep_ctx *ep_ctx; |
d115b048 | 1800 | struct xhci_slot_ctx *slot_ctx; |
f94e0186 SS |
1801 | int i; |
1802 | ||
4daf9df5 | 1803 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
92f8e767 SS |
1804 | if (!ctrl_ctx) { |
1805 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1806 | __func__); | |
1807 | return; | |
1808 | } | |
1809 | ||
f94e0186 SS |
1810 | /* When a device's add flag and drop flag are zero, any subsequent |
1811 | * configure endpoint command will leave that endpoint's state | |
1812 | * untouched. Make sure we don't leave any old state in the input | |
1813 | * endpoint contexts. | |
1814 | */ | |
d115b048 JY |
1815 | ctrl_ctx->drop_flags = 0; |
1816 | ctrl_ctx->add_flags = 0; | |
1817 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); | |
28ccd296 | 1818 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); |
f94e0186 | 1819 | /* Endpoint 0 is always valid */ |
28ccd296 | 1820 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); |
98871e94 | 1821 | for (i = 1; i < 31; i++) { |
d115b048 | 1822 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i); |
f94e0186 SS |
1823 | ep_ctx->ep_info = 0; |
1824 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1825 | ep_ctx->deq = 0; |
f94e0186 SS |
1826 | ep_ctx->tx_info = 0; |
1827 | } | |
1828 | } | |
1829 | ||
f2217e8e | 1830 | static int xhci_configure_endpoint_result(struct xhci_hcd *xhci, |
00161f7d | 1831 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1832 | { |
1833 | int ret; | |
1834 | ||
913a8a34 | 1835 | switch (*cmd_status) { |
0b7c105a | 1836 | case COMP_COMMAND_ABORTED: |
604d02a2 | 1837 | case COMP_COMMAND_RING_STOPPED: |
c311e391 MN |
1838 | xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n"); |
1839 | ret = -ETIME; | |
1840 | break; | |
0b7c105a | 1841 | case COMP_RESOURCE_ERROR: |
288c0f44 ON |
1842 | dev_warn(&udev->dev, |
1843 | "Not enough host controller resources for new device state.\n"); | |
f2217e8e SS |
1844 | ret = -ENOMEM; |
1845 | /* FIXME: can we allocate more resources for the HC? */ | |
1846 | break; | |
0b7c105a FB |
1847 | case COMP_BANDWIDTH_ERROR: |
1848 | case COMP_SECONDARY_BANDWIDTH_ERROR: | |
288c0f44 ON |
1849 | dev_warn(&udev->dev, |
1850 | "Not enough bandwidth for new device state.\n"); | |
f2217e8e SS |
1851 | ret = -ENOSPC; |
1852 | /* FIXME: can we go back to the old state? */ | |
1853 | break; | |
0b7c105a | 1854 | case COMP_TRB_ERROR: |
f2217e8e SS |
1855 | /* the HCD set up something wrong */ |
1856 | dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, " | |
1857 | "add flag = 1, " | |
1858 | "and endpoint is not disabled.\n"); | |
1859 | ret = -EINVAL; | |
1860 | break; | |
0b7c105a | 1861 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
288c0f44 ON |
1862 | dev_warn(&udev->dev, |
1863 | "ERROR: Incompatible device for endpoint configure command.\n"); | |
f6ba6fe2 AH |
1864 | ret = -ENODEV; |
1865 | break; | |
f2217e8e | 1866 | case COMP_SUCCESS: |
3a7fa5be XR |
1867 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1868 | "Successful Endpoint Configure command"); | |
f2217e8e SS |
1869 | ret = 0; |
1870 | break; | |
1871 | default: | |
288c0f44 ON |
1872 | xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n", |
1873 | *cmd_status); | |
f2217e8e SS |
1874 | ret = -EINVAL; |
1875 | break; | |
1876 | } | |
1877 | return ret; | |
1878 | } | |
1879 | ||
1880 | static int xhci_evaluate_context_result(struct xhci_hcd *xhci, | |
00161f7d | 1881 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1882 | { |
1883 | int ret; | |
1884 | ||
913a8a34 | 1885 | switch (*cmd_status) { |
0b7c105a | 1886 | case COMP_COMMAND_ABORTED: |
604d02a2 | 1887 | case COMP_COMMAND_RING_STOPPED: |
c311e391 MN |
1888 | xhci_warn(xhci, "Timeout while waiting for evaluate context command\n"); |
1889 | ret = -ETIME; | |
1890 | break; | |
0b7c105a | 1891 | case COMP_PARAMETER_ERROR: |
288c0f44 ON |
1892 | dev_warn(&udev->dev, |
1893 | "WARN: xHCI driver setup invalid evaluate context command.\n"); | |
f2217e8e SS |
1894 | ret = -EINVAL; |
1895 | break; | |
0b7c105a | 1896 | case COMP_SLOT_NOT_ENABLED_ERROR: |
288c0f44 ON |
1897 | dev_warn(&udev->dev, |
1898 | "WARN: slot not enabled for evaluate context command.\n"); | |
b8031342 SS |
1899 | ret = -EINVAL; |
1900 | break; | |
0b7c105a | 1901 | case COMP_CONTEXT_STATE_ERROR: |
288c0f44 ON |
1902 | dev_warn(&udev->dev, |
1903 | "WARN: invalid context state for evaluate context command.\n"); | |
f2217e8e SS |
1904 | ret = -EINVAL; |
1905 | break; | |
0b7c105a | 1906 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
288c0f44 ON |
1907 | dev_warn(&udev->dev, |
1908 | "ERROR: Incompatible device for evaluate context command.\n"); | |
f6ba6fe2 AH |
1909 | ret = -ENODEV; |
1910 | break; | |
0b7c105a | 1911 | case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: |
1bb73a88 AH |
1912 | /* Max Exit Latency too large error */ |
1913 | dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n"); | |
1914 | ret = -EINVAL; | |
1915 | break; | |
f2217e8e | 1916 | case COMP_SUCCESS: |
3a7fa5be XR |
1917 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1918 | "Successful evaluate context command"); | |
f2217e8e SS |
1919 | ret = 0; |
1920 | break; | |
1921 | default: | |
288c0f44 ON |
1922 | xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n", |
1923 | *cmd_status); | |
f2217e8e SS |
1924 | ret = -EINVAL; |
1925 | break; | |
1926 | } | |
1927 | return ret; | |
1928 | } | |
1929 | ||
2cf95c18 | 1930 | static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci, |
92f8e767 | 1931 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 1932 | { |
2cf95c18 SS |
1933 | u32 valid_add_flags; |
1934 | u32 valid_drop_flags; | |
1935 | ||
2cf95c18 SS |
1936 | /* Ignore the slot flag (bit 0), and the default control endpoint flag |
1937 | * (bit 1). The default control endpoint is added during the Address | |
1938 | * Device command and is never removed until the slot is disabled. | |
1939 | */ | |
ef73400c XR |
1940 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
1941 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; | |
2cf95c18 SS |
1942 | |
1943 | /* Use hweight32 to count the number of ones in the add flags, or | |
1944 | * number of endpoints added. Don't count endpoints that are changed | |
1945 | * (both added and dropped). | |
1946 | */ | |
1947 | return hweight32(valid_add_flags) - | |
1948 | hweight32(valid_add_flags & valid_drop_flags); | |
1949 | } | |
1950 | ||
1951 | static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci, | |
92f8e767 | 1952 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 1953 | { |
2cf95c18 SS |
1954 | u32 valid_add_flags; |
1955 | u32 valid_drop_flags; | |
1956 | ||
78d1ff02 XR |
1957 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
1958 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; | |
2cf95c18 SS |
1959 | |
1960 | return hweight32(valid_drop_flags) - | |
1961 | hweight32(valid_add_flags & valid_drop_flags); | |
1962 | } | |
1963 | ||
1964 | /* | |
1965 | * We need to reserve the new number of endpoints before the configure endpoint | |
1966 | * command completes. We can't subtract the dropped endpoints from the number | |
1967 | * of active endpoints until the command completes because we can oversubscribe | |
1968 | * the host in this case: | |
1969 | * | |
1970 | * - the first configure endpoint command drops more endpoints than it adds | |
1971 | * - a second configure endpoint command that adds more endpoints is queued | |
1972 | * - the first configure endpoint command fails, so the config is unchanged | |
1973 | * - the second command may succeed, even though there isn't enough resources | |
1974 | * | |
1975 | * Must be called with xhci->lock held. | |
1976 | */ | |
1977 | static int xhci_reserve_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 1978 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1979 | { |
1980 | u32 added_eps; | |
1981 | ||
92f8e767 | 1982 | added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 1983 | if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) { |
4bdfe4c3 XR |
1984 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1985 | "Not enough ep ctxs: " | |
1986 | "%u active, need to add %u, limit is %u.", | |
2cf95c18 SS |
1987 | xhci->num_active_eps, added_eps, |
1988 | xhci->limit_active_eps); | |
1989 | return -ENOMEM; | |
1990 | } | |
1991 | xhci->num_active_eps += added_eps; | |
4bdfe4c3 XR |
1992 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1993 | "Adding %u ep ctxs, %u now active.", added_eps, | |
2cf95c18 SS |
1994 | xhci->num_active_eps); |
1995 | return 0; | |
1996 | } | |
1997 | ||
1998 | /* | |
1999 | * The configure endpoint was failed by the xHC for some other reason, so we | |
2000 | * need to revert the resources that failed configuration would have used. | |
2001 | * | |
2002 | * Must be called with xhci->lock held. | |
2003 | */ | |
2004 | static void xhci_free_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 2005 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
2006 | { |
2007 | u32 num_failed_eps; | |
2008 | ||
92f8e767 | 2009 | num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 2010 | xhci->num_active_eps -= num_failed_eps; |
4bdfe4c3 XR |
2011 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2012 | "Removing %u failed ep ctxs, %u now active.", | |
2cf95c18 SS |
2013 | num_failed_eps, |
2014 | xhci->num_active_eps); | |
2015 | } | |
2016 | ||
2017 | /* | |
2018 | * Now that the command has completed, clean up the active endpoint count by | |
2019 | * subtracting out the endpoints that were dropped (but not changed). | |
2020 | * | |
2021 | * Must be called with xhci->lock held. | |
2022 | */ | |
2023 | static void xhci_finish_resource_reservation(struct xhci_hcd *xhci, | |
92f8e767 | 2024 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
2025 | { |
2026 | u32 num_dropped_eps; | |
2027 | ||
92f8e767 | 2028 | num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx); |
2cf95c18 SS |
2029 | xhci->num_active_eps -= num_dropped_eps; |
2030 | if (num_dropped_eps) | |
4bdfe4c3 XR |
2031 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2032 | "Removing %u dropped ep ctxs, %u now active.", | |
2cf95c18 SS |
2033 | num_dropped_eps, |
2034 | xhci->num_active_eps); | |
2035 | } | |
2036 | ||
ed384bd3 | 2037 | static unsigned int xhci_get_block_size(struct usb_device *udev) |
c29eea62 SS |
2038 | { |
2039 | switch (udev->speed) { | |
2040 | case USB_SPEED_LOW: | |
2041 | case USB_SPEED_FULL: | |
2042 | return FS_BLOCK; | |
2043 | case USB_SPEED_HIGH: | |
2044 | return HS_BLOCK; | |
2045 | case USB_SPEED_SUPER: | |
0caf6b33 | 2046 | case USB_SPEED_SUPER_PLUS: |
c29eea62 SS |
2047 | return SS_BLOCK; |
2048 | case USB_SPEED_UNKNOWN: | |
2049 | case USB_SPEED_WIRELESS: | |
2050 | default: | |
2051 | /* Should never happen */ | |
2052 | return 1; | |
2053 | } | |
2054 | } | |
2055 | ||
ed384bd3 FB |
2056 | static unsigned int |
2057 | xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw) | |
c29eea62 SS |
2058 | { |
2059 | if (interval_bw->overhead[LS_OVERHEAD_TYPE]) | |
2060 | return LS_OVERHEAD; | |
2061 | if (interval_bw->overhead[FS_OVERHEAD_TYPE]) | |
2062 | return FS_OVERHEAD; | |
2063 | return HS_OVERHEAD; | |
2064 | } | |
2065 | ||
2066 | /* If we are changing a LS/FS device under a HS hub, | |
2067 | * make sure (if we are activating a new TT) that the HS bus has enough | |
2068 | * bandwidth for this new TT. | |
2069 | */ | |
2070 | static int xhci_check_tt_bw_table(struct xhci_hcd *xhci, | |
2071 | struct xhci_virt_device *virt_dev, | |
2072 | int old_active_eps) | |
2073 | { | |
2074 | struct xhci_interval_bw_table *bw_table; | |
2075 | struct xhci_tt_bw_info *tt_info; | |
2076 | ||
2077 | /* Find the bandwidth table for the root port this TT is attached to. */ | |
2078 | bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table; | |
2079 | tt_info = virt_dev->tt_info; | |
2080 | /* If this TT already had active endpoints, the bandwidth for this TT | |
2081 | * has already been added. Removing all periodic endpoints (and thus | |
2082 | * making the TT enactive) will only decrease the bandwidth used. | |
2083 | */ | |
2084 | if (old_active_eps) | |
2085 | return 0; | |
2086 | if (old_active_eps == 0 && tt_info->active_eps != 0) { | |
2087 | if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT) | |
2088 | return -ENOMEM; | |
2089 | return 0; | |
2090 | } | |
2091 | /* Not sure why we would have no new active endpoints... | |
2092 | * | |
2093 | * Maybe because of an Evaluate Context change for a hub update or a | |
2094 | * control endpoint 0 max packet size change? | |
2095 | * FIXME: skip the bandwidth calculation in that case. | |
2096 | */ | |
2097 | return 0; | |
2098 | } | |
2099 | ||
2b698999 SS |
2100 | static int xhci_check_ss_bw(struct xhci_hcd *xhci, |
2101 | struct xhci_virt_device *virt_dev) | |
2102 | { | |
2103 | unsigned int bw_reserved; | |
2104 | ||
2105 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100); | |
2106 | if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved)) | |
2107 | return -ENOMEM; | |
2108 | ||
2109 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100); | |
2110 | if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved)) | |
2111 | return -ENOMEM; | |
2112 | ||
2113 | return 0; | |
2114 | } | |
2115 | ||
c29eea62 SS |
2116 | /* |
2117 | * This algorithm is a very conservative estimate of the worst-case scheduling | |
2118 | * scenario for any one interval. The hardware dynamically schedules the | |
2119 | * packets, so we can't tell which microframe could be the limiting factor in | |
2120 | * the bandwidth scheduling. This only takes into account periodic endpoints. | |
2121 | * | |
2122 | * Obviously, we can't solve an NP complete problem to find the minimum worst | |
2123 | * case scenario. Instead, we come up with an estimate that is no less than | |
2124 | * the worst case bandwidth used for any one microframe, but may be an | |
2125 | * over-estimate. | |
2126 | * | |
2127 | * We walk the requirements for each endpoint by interval, starting with the | |
2128 | * smallest interval, and place packets in the schedule where there is only one | |
2129 | * possible way to schedule packets for that interval. In order to simplify | |
2130 | * this algorithm, we record the largest max packet size for each interval, and | |
2131 | * assume all packets will be that size. | |
2132 | * | |
2133 | * For interval 0, we obviously must schedule all packets for each interval. | |
2134 | * The bandwidth for interval 0 is just the amount of data to be transmitted | |
2135 | * (the sum of all max ESIT payload sizes, plus any overhead per packet times | |
2136 | * the number of packets). | |
2137 | * | |
2138 | * For interval 1, we have two possible microframes to schedule those packets | |
2139 | * in. For this algorithm, if we can schedule the same number of packets for | |
2140 | * each possible scheduling opportunity (each microframe), we will do so. The | |
2141 | * remaining number of packets will be saved to be transmitted in the gaps in | |
2142 | * the next interval's scheduling sequence. | |
2143 | * | |
2144 | * As we move those remaining packets to be scheduled with interval 2 packets, | |
2145 | * we have to double the number of remaining packets to transmit. This is | |
2146 | * because the intervals are actually powers of 2, and we would be transmitting | |
2147 | * the previous interval's packets twice in this interval. We also have to be | |
2148 | * sure that when we look at the largest max packet size for this interval, we | |
2149 | * also look at the largest max packet size for the remaining packets and take | |
2150 | * the greater of the two. | |
2151 | * | |
2152 | * The algorithm continues to evenly distribute packets in each scheduling | |
2153 | * opportunity, and push the remaining packets out, until we get to the last | |
2154 | * interval. Then those packets and their associated overhead are just added | |
2155 | * to the bandwidth used. | |
2e27980e SS |
2156 | */ |
2157 | static int xhci_check_bw_table(struct xhci_hcd *xhci, | |
2158 | struct xhci_virt_device *virt_dev, | |
2159 | int old_active_eps) | |
2160 | { | |
c29eea62 SS |
2161 | unsigned int bw_reserved; |
2162 | unsigned int max_bandwidth; | |
2163 | unsigned int bw_used; | |
2164 | unsigned int block_size; | |
2165 | struct xhci_interval_bw_table *bw_table; | |
2166 | unsigned int packet_size = 0; | |
2167 | unsigned int overhead = 0; | |
2168 | unsigned int packets_transmitted = 0; | |
2169 | unsigned int packets_remaining = 0; | |
2170 | unsigned int i; | |
2171 | ||
0caf6b33 | 2172 | if (virt_dev->udev->speed >= USB_SPEED_SUPER) |
2b698999 SS |
2173 | return xhci_check_ss_bw(xhci, virt_dev); |
2174 | ||
c29eea62 SS |
2175 | if (virt_dev->udev->speed == USB_SPEED_HIGH) { |
2176 | max_bandwidth = HS_BW_LIMIT; | |
2177 | /* Convert percent of bus BW reserved to blocks reserved */ | |
2178 | bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100); | |
2179 | } else { | |
2180 | max_bandwidth = FS_BW_LIMIT; | |
2181 | bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100); | |
2182 | } | |
2183 | ||
2184 | bw_table = virt_dev->bw_table; | |
2185 | /* We need to translate the max packet size and max ESIT payloads into | |
2186 | * the units the hardware uses. | |
2187 | */ | |
2188 | block_size = xhci_get_block_size(virt_dev->udev); | |
2189 | ||
2190 | /* If we are manipulating a LS/FS device under a HS hub, double check | |
2191 | * that the HS bus has enough bandwidth if we are activing a new TT. | |
2192 | */ | |
2193 | if (virt_dev->tt_info) { | |
4bdfe4c3 XR |
2194 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2195 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2196 | virt_dev->real_port); |
2197 | if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) { | |
2198 | xhci_warn(xhci, "Not enough bandwidth on HS bus for " | |
2199 | "newly activated TT.\n"); | |
2200 | return -ENOMEM; | |
2201 | } | |
4bdfe4c3 XR |
2202 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2203 | "Recalculating BW for TT slot %u port %u", | |
c29eea62 SS |
2204 | virt_dev->tt_info->slot_id, |
2205 | virt_dev->tt_info->ttport); | |
2206 | } else { | |
4bdfe4c3 XR |
2207 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2208 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2209 | virt_dev->real_port); |
2210 | } | |
2211 | ||
2212 | /* Add in how much bandwidth will be used for interval zero, or the | |
2213 | * rounded max ESIT payload + number of packets * largest overhead. | |
2214 | */ | |
2215 | bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) + | |
2216 | bw_table->interval_bw[0].num_packets * | |
2217 | xhci_get_largest_overhead(&bw_table->interval_bw[0]); | |
2218 | ||
2219 | for (i = 1; i < XHCI_MAX_INTERVAL; i++) { | |
2220 | unsigned int bw_added; | |
2221 | unsigned int largest_mps; | |
2222 | unsigned int interval_overhead; | |
2223 | ||
2224 | /* | |
2225 | * How many packets could we transmit in this interval? | |
2226 | * If packets didn't fit in the previous interval, we will need | |
2227 | * to transmit that many packets twice within this interval. | |
2228 | */ | |
2229 | packets_remaining = 2 * packets_remaining + | |
2230 | bw_table->interval_bw[i].num_packets; | |
2231 | ||
2232 | /* Find the largest max packet size of this or the previous | |
2233 | * interval. | |
2234 | */ | |
2235 | if (list_empty(&bw_table->interval_bw[i].endpoints)) | |
2236 | largest_mps = 0; | |
2237 | else { | |
2238 | struct xhci_virt_ep *virt_ep; | |
2239 | struct list_head *ep_entry; | |
2240 | ||
2241 | ep_entry = bw_table->interval_bw[i].endpoints.next; | |
2242 | virt_ep = list_entry(ep_entry, | |
2243 | struct xhci_virt_ep, bw_endpoint_list); | |
2244 | /* Convert to blocks, rounding up */ | |
2245 | largest_mps = DIV_ROUND_UP( | |
2246 | virt_ep->bw_info.max_packet_size, | |
2247 | block_size); | |
2248 | } | |
2249 | if (largest_mps > packet_size) | |
2250 | packet_size = largest_mps; | |
2251 | ||
2252 | /* Use the larger overhead of this or the previous interval. */ | |
2253 | interval_overhead = xhci_get_largest_overhead( | |
2254 | &bw_table->interval_bw[i]); | |
2255 | if (interval_overhead > overhead) | |
2256 | overhead = interval_overhead; | |
2257 | ||
2258 | /* How many packets can we evenly distribute across | |
2259 | * (1 << (i + 1)) possible scheduling opportunities? | |
2260 | */ | |
2261 | packets_transmitted = packets_remaining >> (i + 1); | |
2262 | ||
2263 | /* Add in the bandwidth used for those scheduled packets */ | |
2264 | bw_added = packets_transmitted * (overhead + packet_size); | |
2265 | ||
2266 | /* How many packets do we have remaining to transmit? */ | |
2267 | packets_remaining = packets_remaining % (1 << (i + 1)); | |
2268 | ||
2269 | /* What largest max packet size should those packets have? */ | |
2270 | /* If we've transmitted all packets, don't carry over the | |
2271 | * largest packet size. | |
2272 | */ | |
2273 | if (packets_remaining == 0) { | |
2274 | packet_size = 0; | |
2275 | overhead = 0; | |
2276 | } else if (packets_transmitted > 0) { | |
2277 | /* Otherwise if we do have remaining packets, and we've | |
2278 | * scheduled some packets in this interval, take the | |
2279 | * largest max packet size from endpoints with this | |
2280 | * interval. | |
2281 | */ | |
2282 | packet_size = largest_mps; | |
2283 | overhead = interval_overhead; | |
2284 | } | |
2285 | /* Otherwise carry over packet_size and overhead from the last | |
2286 | * time we had a remainder. | |
2287 | */ | |
2288 | bw_used += bw_added; | |
2289 | if (bw_used > max_bandwidth) { | |
2290 | xhci_warn(xhci, "Not enough bandwidth. " | |
2291 | "Proposed: %u, Max: %u\n", | |
2292 | bw_used, max_bandwidth); | |
2293 | return -ENOMEM; | |
2294 | } | |
2295 | } | |
2296 | /* | |
2297 | * Ok, we know we have some packets left over after even-handedly | |
2298 | * scheduling interval 15. We don't know which microframes they will | |
2299 | * fit into, so we over-schedule and say they will be scheduled every | |
2300 | * microframe. | |
2301 | */ | |
2302 | if (packets_remaining > 0) | |
2303 | bw_used += overhead + packet_size; | |
2304 | ||
2305 | if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) { | |
2306 | unsigned int port_index = virt_dev->real_port - 1; | |
2307 | ||
2308 | /* OK, we're manipulating a HS device attached to a | |
2309 | * root port bandwidth domain. Include the number of active TTs | |
2310 | * in the bandwidth used. | |
2311 | */ | |
2312 | bw_used += TT_HS_OVERHEAD * | |
2313 | xhci->rh_bw[port_index].num_active_tts; | |
2314 | } | |
2315 | ||
4bdfe4c3 XR |
2316 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2317 | "Final bandwidth: %u, Limit: %u, Reserved: %u, " | |
2318 | "Available: %u " "percent", | |
c29eea62 SS |
2319 | bw_used, max_bandwidth, bw_reserved, |
2320 | (max_bandwidth - bw_used - bw_reserved) * 100 / | |
2321 | max_bandwidth); | |
2322 | ||
2323 | bw_used += bw_reserved; | |
2324 | if (bw_used > max_bandwidth) { | |
2325 | xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n", | |
2326 | bw_used, max_bandwidth); | |
2327 | return -ENOMEM; | |
2328 | } | |
2329 | ||
2330 | bw_table->bw_used = bw_used; | |
2e27980e SS |
2331 | return 0; |
2332 | } | |
2333 | ||
2334 | static bool xhci_is_async_ep(unsigned int ep_type) | |
2335 | { | |
2336 | return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
2337 | ep_type != ISOC_IN_EP && | |
2338 | ep_type != INT_IN_EP); | |
2339 | } | |
2340 | ||
2b698999 SS |
2341 | static bool xhci_is_sync_in_ep(unsigned int ep_type) |
2342 | { | |
392a07ae | 2343 | return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP); |
2b698999 SS |
2344 | } |
2345 | ||
2346 | static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw) | |
2347 | { | |
2348 | unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK); | |
2349 | ||
2350 | if (ep_bw->ep_interval == 0) | |
2351 | return SS_OVERHEAD_BURST + | |
2352 | (ep_bw->mult * ep_bw->num_packets * | |
2353 | (SS_OVERHEAD + mps)); | |
2354 | return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets * | |
2355 | (SS_OVERHEAD + mps + SS_OVERHEAD_BURST), | |
2356 | 1 << ep_bw->ep_interval); | |
2357 | ||
2358 | } | |
2359 | ||
3969384c | 2360 | static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, |
2e27980e SS |
2361 | struct xhci_bw_info *ep_bw, |
2362 | struct xhci_interval_bw_table *bw_table, | |
2363 | struct usb_device *udev, | |
2364 | struct xhci_virt_ep *virt_ep, | |
2365 | struct xhci_tt_bw_info *tt_info) | |
2366 | { | |
2367 | struct xhci_interval_bw *interval_bw; | |
2368 | int normalized_interval; | |
2369 | ||
2b698999 | 2370 | if (xhci_is_async_ep(ep_bw->type)) |
2e27980e SS |
2371 | return; |
2372 | ||
0caf6b33 | 2373 | if (udev->speed >= USB_SPEED_SUPER) { |
2b698999 SS |
2374 | if (xhci_is_sync_in_ep(ep_bw->type)) |
2375 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in -= | |
2376 | xhci_get_ss_bw_consumed(ep_bw); | |
2377 | else | |
2378 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out -= | |
2379 | xhci_get_ss_bw_consumed(ep_bw); | |
2380 | return; | |
2381 | } | |
2382 | ||
2383 | /* SuperSpeed endpoints never get added to intervals in the table, so | |
2384 | * this check is only valid for HS/FS/LS devices. | |
2385 | */ | |
2386 | if (list_empty(&virt_ep->bw_endpoint_list)) | |
2387 | return; | |
2e27980e SS |
2388 | /* For LS/FS devices, we need to translate the interval expressed in |
2389 | * microframes to frames. | |
2390 | */ | |
2391 | if (udev->speed == USB_SPEED_HIGH) | |
2392 | normalized_interval = ep_bw->ep_interval; | |
2393 | else | |
2394 | normalized_interval = ep_bw->ep_interval - 3; | |
2395 | ||
2396 | if (normalized_interval == 0) | |
2397 | bw_table->interval0_esit_payload -= ep_bw->max_esit_payload; | |
2398 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2399 | interval_bw->num_packets -= ep_bw->num_packets; | |
2400 | switch (udev->speed) { | |
2401 | case USB_SPEED_LOW: | |
2402 | interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1; | |
2403 | break; | |
2404 | case USB_SPEED_FULL: | |
2405 | interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1; | |
2406 | break; | |
2407 | case USB_SPEED_HIGH: | |
2408 | interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1; | |
2409 | break; | |
2410 | case USB_SPEED_SUPER: | |
0caf6b33 | 2411 | case USB_SPEED_SUPER_PLUS: |
2e27980e SS |
2412 | case USB_SPEED_UNKNOWN: |
2413 | case USB_SPEED_WIRELESS: | |
2414 | /* Should never happen because only LS/FS/HS endpoints will get | |
2415 | * added to the endpoint list. | |
2416 | */ | |
2417 | return; | |
2418 | } | |
2419 | if (tt_info) | |
2420 | tt_info->active_eps -= 1; | |
2421 | list_del_init(&virt_ep->bw_endpoint_list); | |
2422 | } | |
2423 | ||
2424 | static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci, | |
2425 | struct xhci_bw_info *ep_bw, | |
2426 | struct xhci_interval_bw_table *bw_table, | |
2427 | struct usb_device *udev, | |
2428 | struct xhci_virt_ep *virt_ep, | |
2429 | struct xhci_tt_bw_info *tt_info) | |
2430 | { | |
2431 | struct xhci_interval_bw *interval_bw; | |
2432 | struct xhci_virt_ep *smaller_ep; | |
2433 | int normalized_interval; | |
2434 | ||
2435 | if (xhci_is_async_ep(ep_bw->type)) | |
2436 | return; | |
2437 | ||
2b698999 SS |
2438 | if (udev->speed == USB_SPEED_SUPER) { |
2439 | if (xhci_is_sync_in_ep(ep_bw->type)) | |
2440 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in += | |
2441 | xhci_get_ss_bw_consumed(ep_bw); | |
2442 | else | |
2443 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out += | |
2444 | xhci_get_ss_bw_consumed(ep_bw); | |
2445 | return; | |
2446 | } | |
2447 | ||
2e27980e SS |
2448 | /* For LS/FS devices, we need to translate the interval expressed in |
2449 | * microframes to frames. | |
2450 | */ | |
2451 | if (udev->speed == USB_SPEED_HIGH) | |
2452 | normalized_interval = ep_bw->ep_interval; | |
2453 | else | |
2454 | normalized_interval = ep_bw->ep_interval - 3; | |
2455 | ||
2456 | if (normalized_interval == 0) | |
2457 | bw_table->interval0_esit_payload += ep_bw->max_esit_payload; | |
2458 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2459 | interval_bw->num_packets += ep_bw->num_packets; | |
2460 | switch (udev->speed) { | |
2461 | case USB_SPEED_LOW: | |
2462 | interval_bw->overhead[LS_OVERHEAD_TYPE] += 1; | |
2463 | break; | |
2464 | case USB_SPEED_FULL: | |
2465 | interval_bw->overhead[FS_OVERHEAD_TYPE] += 1; | |
2466 | break; | |
2467 | case USB_SPEED_HIGH: | |
2468 | interval_bw->overhead[HS_OVERHEAD_TYPE] += 1; | |
2469 | break; | |
2470 | case USB_SPEED_SUPER: | |
0caf6b33 | 2471 | case USB_SPEED_SUPER_PLUS: |
2e27980e SS |
2472 | case USB_SPEED_UNKNOWN: |
2473 | case USB_SPEED_WIRELESS: | |
2474 | /* Should never happen because only LS/FS/HS endpoints will get | |
2475 | * added to the endpoint list. | |
2476 | */ | |
2477 | return; | |
2478 | } | |
2479 | ||
2480 | if (tt_info) | |
2481 | tt_info->active_eps += 1; | |
2482 | /* Insert the endpoint into the list, largest max packet size first. */ | |
2483 | list_for_each_entry(smaller_ep, &interval_bw->endpoints, | |
2484 | bw_endpoint_list) { | |
2485 | if (ep_bw->max_packet_size >= | |
2486 | smaller_ep->bw_info.max_packet_size) { | |
2487 | /* Add the new ep before the smaller endpoint */ | |
2488 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2489 | &smaller_ep->bw_endpoint_list); | |
2490 | return; | |
2491 | } | |
2492 | } | |
2493 | /* Add the new endpoint at the end of the list. */ | |
2494 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2495 | &interval_bw->endpoints); | |
2496 | } | |
2497 | ||
2498 | void xhci_update_tt_active_eps(struct xhci_hcd *xhci, | |
2499 | struct xhci_virt_device *virt_dev, | |
2500 | int old_active_eps) | |
2501 | { | |
2502 | struct xhci_root_port_bw_info *rh_bw_info; | |
2503 | if (!virt_dev->tt_info) | |
2504 | return; | |
2505 | ||
2506 | rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1]; | |
2507 | if (old_active_eps == 0 && | |
2508 | virt_dev->tt_info->active_eps != 0) { | |
2509 | rh_bw_info->num_active_tts += 1; | |
c29eea62 | 2510 | rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD; |
2e27980e SS |
2511 | } else if (old_active_eps != 0 && |
2512 | virt_dev->tt_info->active_eps == 0) { | |
2513 | rh_bw_info->num_active_tts -= 1; | |
c29eea62 | 2514 | rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD; |
2e27980e SS |
2515 | } |
2516 | } | |
2517 | ||
2518 | static int xhci_reserve_bandwidth(struct xhci_hcd *xhci, | |
2519 | struct xhci_virt_device *virt_dev, | |
2520 | struct xhci_container_ctx *in_ctx) | |
2521 | { | |
2522 | struct xhci_bw_info ep_bw_info[31]; | |
2523 | int i; | |
2524 | struct xhci_input_control_ctx *ctrl_ctx; | |
2525 | int old_active_eps = 0; | |
2526 | ||
2e27980e SS |
2527 | if (virt_dev->tt_info) |
2528 | old_active_eps = virt_dev->tt_info->active_eps; | |
2529 | ||
4daf9df5 | 2530 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
2531 | if (!ctrl_ctx) { |
2532 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2533 | __func__); | |
2534 | return -ENOMEM; | |
2535 | } | |
2e27980e SS |
2536 | |
2537 | for (i = 0; i < 31; i++) { | |
2538 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2539 | continue; | |
2540 | ||
2541 | /* Make a copy of the BW info in case we need to revert this */ | |
2542 | memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info, | |
2543 | sizeof(ep_bw_info[i])); | |
2544 | /* Drop the endpoint from the interval table if the endpoint is | |
2545 | * being dropped or changed. | |
2546 | */ | |
2547 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2548 | xhci_drop_ep_from_interval_table(xhci, | |
2549 | &virt_dev->eps[i].bw_info, | |
2550 | virt_dev->bw_table, | |
2551 | virt_dev->udev, | |
2552 | &virt_dev->eps[i], | |
2553 | virt_dev->tt_info); | |
2554 | } | |
2555 | /* Overwrite the information stored in the endpoints' bw_info */ | |
2556 | xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev); | |
2557 | for (i = 0; i < 31; i++) { | |
2558 | /* Add any changed or added endpoints to the interval table */ | |
2559 | if (EP_IS_ADDED(ctrl_ctx, i)) | |
2560 | xhci_add_ep_to_interval_table(xhci, | |
2561 | &virt_dev->eps[i].bw_info, | |
2562 | virt_dev->bw_table, | |
2563 | virt_dev->udev, | |
2564 | &virt_dev->eps[i], | |
2565 | virt_dev->tt_info); | |
2566 | } | |
2567 | ||
2568 | if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) { | |
2569 | /* Ok, this fits in the bandwidth we have. | |
2570 | * Update the number of active TTs. | |
2571 | */ | |
2572 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
2573 | return 0; | |
2574 | } | |
2575 | ||
2576 | /* We don't have enough bandwidth for this, revert the stored info. */ | |
2577 | for (i = 0; i < 31; i++) { | |
2578 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2579 | continue; | |
2580 | ||
2581 | /* Drop the new copies of any added or changed endpoints from | |
2582 | * the interval table. | |
2583 | */ | |
2584 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
2585 | xhci_drop_ep_from_interval_table(xhci, | |
2586 | &virt_dev->eps[i].bw_info, | |
2587 | virt_dev->bw_table, | |
2588 | virt_dev->udev, | |
2589 | &virt_dev->eps[i], | |
2590 | virt_dev->tt_info); | |
2591 | } | |
2592 | /* Revert the endpoint back to its old information */ | |
2593 | memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i], | |
2594 | sizeof(ep_bw_info[i])); | |
2595 | /* Add any changed or dropped endpoints back into the table */ | |
2596 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2597 | xhci_add_ep_to_interval_table(xhci, | |
2598 | &virt_dev->eps[i].bw_info, | |
2599 | virt_dev->bw_table, | |
2600 | virt_dev->udev, | |
2601 | &virt_dev->eps[i], | |
2602 | virt_dev->tt_info); | |
2603 | } | |
2604 | return -ENOMEM; | |
2605 | } | |
2606 | ||
2607 | ||
f2217e8e SS |
2608 | /* Issue a configure endpoint command or evaluate context command |
2609 | * and wait for it to finish. | |
2610 | */ | |
2611 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, | |
913a8a34 SS |
2612 | struct usb_device *udev, |
2613 | struct xhci_command *command, | |
2614 | bool ctx_change, bool must_succeed) | |
f2217e8e SS |
2615 | { |
2616 | int ret; | |
f2217e8e | 2617 | unsigned long flags; |
92f8e767 | 2618 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 2619 | struct xhci_virt_device *virt_dev; |
e3a78ff0 | 2620 | struct xhci_slot_ctx *slot_ctx; |
ddba5cd0 MN |
2621 | |
2622 | if (!command) | |
2623 | return -EINVAL; | |
f2217e8e SS |
2624 | |
2625 | spin_lock_irqsave(&xhci->lock, flags); | |
d9f11ba9 MN |
2626 | |
2627 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2628 | spin_unlock_irqrestore(&xhci->lock, flags); | |
2629 | return -ESHUTDOWN; | |
2630 | } | |
2631 | ||
913a8a34 | 2632 | virt_dev = xhci->devs[udev->slot_id]; |
750645f8 | 2633 | |
4daf9df5 | 2634 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 | 2635 | if (!ctrl_ctx) { |
1f21569c | 2636 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
2637 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
2638 | __func__); | |
2639 | return -ENOMEM; | |
2640 | } | |
2cf95c18 | 2641 | |
750645f8 | 2642 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) && |
92f8e767 | 2643 | xhci_reserve_host_resources(xhci, ctrl_ctx)) { |
750645f8 SS |
2644 | spin_unlock_irqrestore(&xhci->lock, flags); |
2645 | xhci_warn(xhci, "Not enough host resources, " | |
2646 | "active endpoint contexts = %u\n", | |
2647 | xhci->num_active_eps); | |
2648 | return -ENOMEM; | |
2649 | } | |
2e27980e | 2650 | if ((xhci->quirks & XHCI_SW_BW_CHECKING) && |
ddba5cd0 | 2651 | xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) { |
2e27980e | 2652 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) |
92f8e767 | 2653 | xhci_free_host_resources(xhci, ctrl_ctx); |
2e27980e SS |
2654 | spin_unlock_irqrestore(&xhci->lock, flags); |
2655 | xhci_warn(xhci, "Not enough bandwidth\n"); | |
2656 | return -ENOMEM; | |
2657 | } | |
750645f8 | 2658 | |
e3a78ff0 MN |
2659 | slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx); |
2660 | trace_xhci_configure_endpoint(slot_ctx); | |
2661 | ||
f2217e8e | 2662 | if (!ctx_change) |
ddba5cd0 MN |
2663 | ret = xhci_queue_configure_endpoint(xhci, command, |
2664 | command->in_ctx->dma, | |
913a8a34 | 2665 | udev->slot_id, must_succeed); |
f2217e8e | 2666 | else |
ddba5cd0 MN |
2667 | ret = xhci_queue_evaluate_context(xhci, command, |
2668 | command->in_ctx->dma, | |
4b266541 | 2669 | udev->slot_id, must_succeed); |
f2217e8e | 2670 | if (ret < 0) { |
2cf95c18 | 2671 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) |
92f8e767 | 2672 | xhci_free_host_resources(xhci, ctrl_ctx); |
f2217e8e | 2673 | spin_unlock_irqrestore(&xhci->lock, flags); |
3a7fa5be XR |
2674 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
2675 | "FIXME allocate a new ring segment"); | |
f2217e8e SS |
2676 | return -ENOMEM; |
2677 | } | |
2678 | xhci_ring_cmd_db(xhci); | |
2679 | spin_unlock_irqrestore(&xhci->lock, flags); | |
2680 | ||
2681 | /* Wait for the configure endpoint command to complete */ | |
c311e391 | 2682 | wait_for_completion(command->completion); |
f2217e8e SS |
2683 | |
2684 | if (!ctx_change) | |
ddba5cd0 MN |
2685 | ret = xhci_configure_endpoint_result(xhci, udev, |
2686 | &command->status); | |
2cf95c18 | 2687 | else |
ddba5cd0 MN |
2688 | ret = xhci_evaluate_context_result(xhci, udev, |
2689 | &command->status); | |
2cf95c18 SS |
2690 | |
2691 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
2692 | spin_lock_irqsave(&xhci->lock, flags); | |
2693 | /* If the command failed, remove the reserved resources. | |
2694 | * Otherwise, clean up the estimate to include dropped eps. | |
2695 | */ | |
2696 | if (ret) | |
92f8e767 | 2697 | xhci_free_host_resources(xhci, ctrl_ctx); |
2cf95c18 | 2698 | else |
92f8e767 | 2699 | xhci_finish_resource_reservation(xhci, ctrl_ctx); |
2cf95c18 SS |
2700 | spin_unlock_irqrestore(&xhci->lock, flags); |
2701 | } | |
2702 | return ret; | |
f2217e8e SS |
2703 | } |
2704 | ||
df613834 HG |
2705 | static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci, |
2706 | struct xhci_virt_device *vdev, int i) | |
2707 | { | |
2708 | struct xhci_virt_ep *ep = &vdev->eps[i]; | |
2709 | ||
2710 | if (ep->ep_state & EP_HAS_STREAMS) { | |
2711 | xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n", | |
2712 | xhci_get_endpoint_address(i)); | |
2713 | xhci_free_stream_info(xhci, ep->stream_info); | |
2714 | ep->stream_info = NULL; | |
2715 | ep->ep_state &= ~EP_HAS_STREAMS; | |
2716 | } | |
2717 | } | |
2718 | ||
f88ba78d SS |
2719 | /* Called after one or more calls to xhci_add_endpoint() or |
2720 | * xhci_drop_endpoint(). If this call fails, the USB core is expected | |
2721 | * to call xhci_reset_bandwidth(). | |
2722 | * | |
2723 | * Since we are in the middle of changing either configuration or | |
2724 | * installing a new alt setting, the USB core won't allow URBs to be | |
2725 | * enqueued for any endpoint on the old config or interface. Nothing | |
2726 | * else should be touching the xhci->devs[slot_id] structure, so we | |
2727 | * don't need to take the xhci->lock for manipulating that. | |
2728 | */ | |
3969384c | 2729 | static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) |
f94e0186 SS |
2730 | { |
2731 | int i; | |
2732 | int ret = 0; | |
f94e0186 SS |
2733 | struct xhci_hcd *xhci; |
2734 | struct xhci_virt_device *virt_dev; | |
d115b048 JY |
2735 | struct xhci_input_control_ctx *ctrl_ctx; |
2736 | struct xhci_slot_ctx *slot_ctx; | |
ddba5cd0 | 2737 | struct xhci_command *command; |
f94e0186 | 2738 | |
64927730 | 2739 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2740 | if (ret <= 0) |
2741 | return ret; | |
2742 | xhci = hcd_to_xhci(hcd); | |
98d74f9c MN |
2743 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
2744 | (xhci->xhc_state & XHCI_STATE_REMOVING)) | |
fe6c6c13 | 2745 | return -ENODEV; |
f94e0186 | 2746 | |
700e2052 | 2747 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2748 | virt_dev = xhci->devs[udev->slot_id]; |
2749 | ||
ddba5cd0 MN |
2750 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); |
2751 | if (!command) | |
2752 | return -ENOMEM; | |
2753 | ||
2754 | command->in_ctx = virt_dev->in_ctx; | |
2755 | ||
f94e0186 | 2756 | /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */ |
4daf9df5 | 2757 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 SS |
2758 | if (!ctrl_ctx) { |
2759 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2760 | __func__); | |
ddba5cd0 MN |
2761 | ret = -ENOMEM; |
2762 | goto command_cleanup; | |
92f8e767 | 2763 | } |
28ccd296 ME |
2764 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
2765 | ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG); | |
2766 | ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG)); | |
2dc37539 SS |
2767 | |
2768 | /* Don't issue the command if there's no endpoints to update. */ | |
2769 | if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) && | |
ddba5cd0 MN |
2770 | ctrl_ctx->drop_flags == 0) { |
2771 | ret = 0; | |
2772 | goto command_cleanup; | |
2773 | } | |
d6759133 | 2774 | /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */ |
d115b048 | 2775 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
d6759133 JW |
2776 | for (i = 31; i >= 1; i--) { |
2777 | __le32 le32 = cpu_to_le32(BIT(i)); | |
2778 | ||
2779 | if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32)) | |
2780 | || (ctrl_ctx->add_flags & le32) || i == 1) { | |
2781 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); | |
2782 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i)); | |
2783 | break; | |
2784 | } | |
2785 | } | |
f94e0186 | 2786 | |
ddba5cd0 | 2787 | ret = xhci_configure_endpoint(xhci, udev, command, |
913a8a34 | 2788 | false, false); |
ddba5cd0 | 2789 | if (ret) |
f94e0186 | 2790 | /* Callee should call reset_bandwidth() */ |
ddba5cd0 | 2791 | goto command_cleanup; |
f94e0186 | 2792 | |
834cb0fc | 2793 | /* Free any rings that were dropped, but not changed. */ |
98871e94 | 2794 | for (i = 1; i < 31; i++) { |
4819fef5 | 2795 | if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) && |
df613834 | 2796 | !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) { |
c5628a2a | 2797 | xhci_free_endpoint_ring(xhci, virt_dev, i); |
df613834 HG |
2798 | xhci_check_bw_drop_ep_streams(xhci, virt_dev, i); |
2799 | } | |
834cb0fc | 2800 | } |
d115b048 | 2801 | xhci_zero_in_ctx(xhci, virt_dev); |
834cb0fc SS |
2802 | /* |
2803 | * Install any rings for completely new endpoints or changed endpoints, | |
c5628a2a | 2804 | * and free any old rings from changed endpoints. |
834cb0fc | 2805 | */ |
98871e94 | 2806 | for (i = 1; i < 31; i++) { |
74f9fe21 SS |
2807 | if (!virt_dev->eps[i].new_ring) |
2808 | continue; | |
c5628a2a | 2809 | /* Only free the old ring if it exists. |
74f9fe21 SS |
2810 | * It may not if this is the first add of an endpoint. |
2811 | */ | |
2812 | if (virt_dev->eps[i].ring) { | |
c5628a2a | 2813 | xhci_free_endpoint_ring(xhci, virt_dev, i); |
f94e0186 | 2814 | } |
df613834 | 2815 | xhci_check_bw_drop_ep_streams(xhci, virt_dev, i); |
74f9fe21 SS |
2816 | virt_dev->eps[i].ring = virt_dev->eps[i].new_ring; |
2817 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 | 2818 | } |
ddba5cd0 MN |
2819 | command_cleanup: |
2820 | kfree(command->completion); | |
2821 | kfree(command); | |
f94e0186 | 2822 | |
f94e0186 SS |
2823 | return ret; |
2824 | } | |
2825 | ||
3969384c | 2826 | static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) |
f94e0186 | 2827 | { |
f94e0186 SS |
2828 | struct xhci_hcd *xhci; |
2829 | struct xhci_virt_device *virt_dev; | |
2830 | int i, ret; | |
2831 | ||
64927730 | 2832 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2833 | if (ret <= 0) |
2834 | return; | |
2835 | xhci = hcd_to_xhci(hcd); | |
2836 | ||
700e2052 | 2837 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2838 | virt_dev = xhci->devs[udev->slot_id]; |
2839 | /* Free any rings allocated for added endpoints */ | |
98871e94 | 2840 | for (i = 0; i < 31; i++) { |
63a0d9ab | 2841 | if (virt_dev->eps[i].new_ring) { |
02b6fdc2 | 2842 | xhci_debugfs_remove_endpoint(xhci, virt_dev, i); |
63a0d9ab SS |
2843 | xhci_ring_free(xhci, virt_dev->eps[i].new_ring); |
2844 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 SS |
2845 | } |
2846 | } | |
d115b048 | 2847 | xhci_zero_in_ctx(xhci, virt_dev); |
f94e0186 SS |
2848 | } |
2849 | ||
5270b951 | 2850 | static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci, |
913a8a34 SS |
2851 | struct xhci_container_ctx *in_ctx, |
2852 | struct xhci_container_ctx *out_ctx, | |
92f8e767 | 2853 | struct xhci_input_control_ctx *ctrl_ctx, |
913a8a34 | 2854 | u32 add_flags, u32 drop_flags) |
5270b951 | 2855 | { |
28ccd296 ME |
2856 | ctrl_ctx->add_flags = cpu_to_le32(add_flags); |
2857 | ctrl_ctx->drop_flags = cpu_to_le32(drop_flags); | |
913a8a34 | 2858 | xhci_slot_copy(xhci, in_ctx, out_ctx); |
28ccd296 | 2859 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
5270b951 SS |
2860 | } |
2861 | ||
8212a49d | 2862 | static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci, |
ac9d8fe7 SS |
2863 | unsigned int slot_id, unsigned int ep_index, |
2864 | struct xhci_dequeue_state *deq_state) | |
2865 | { | |
92f8e767 | 2866 | struct xhci_input_control_ctx *ctrl_ctx; |
ac9d8fe7 | 2867 | struct xhci_container_ctx *in_ctx; |
ac9d8fe7 SS |
2868 | struct xhci_ep_ctx *ep_ctx; |
2869 | u32 added_ctxs; | |
2870 | dma_addr_t addr; | |
2871 | ||
92f8e767 | 2872 | in_ctx = xhci->devs[slot_id]->in_ctx; |
4daf9df5 | 2873 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
2874 | if (!ctrl_ctx) { |
2875 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2876 | __func__); | |
2877 | return; | |
2878 | } | |
2879 | ||
913a8a34 SS |
2880 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
2881 | xhci->devs[slot_id]->out_ctx, ep_index); | |
ac9d8fe7 SS |
2882 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); |
2883 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
2884 | deq_state->new_deq_ptr); | |
2885 | if (addr == 0) { | |
2886 | xhci_warn(xhci, "WARN Cannot submit config ep after " | |
2887 | "reset ep command\n"); | |
2888 | xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n", | |
2889 | deq_state->new_deq_seg, | |
2890 | deq_state->new_deq_ptr); | |
2891 | return; | |
2892 | } | |
28ccd296 | 2893 | ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state); |
ac9d8fe7 | 2894 | |
ac9d8fe7 | 2895 | added_ctxs = xhci_get_endpoint_flag_from_index(ep_index); |
913a8a34 | 2896 | xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx, |
92f8e767 SS |
2897 | xhci->devs[slot_id]->out_ctx, ctrl_ctx, |
2898 | added_ctxs, added_ctxs); | |
ac9d8fe7 SS |
2899 | } |
2900 | ||
d36374fd MN |
2901 | void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index, |
2902 | unsigned int stream_id, struct xhci_td *td) | |
82d1009f SS |
2903 | { |
2904 | struct xhci_dequeue_state deq_state; | |
63a0d9ab | 2905 | struct xhci_virt_ep *ep; |
d97b4f8d | 2906 | struct usb_device *udev = td->urb->dev; |
82d1009f | 2907 | |
a0254324 XR |
2908 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2909 | "Cleaning up stalled endpoint ring"); | |
63a0d9ab | 2910 | ep = &xhci->devs[udev->slot_id]->eps[ep_index]; |
82d1009f SS |
2911 | /* We need to move the HW's dequeue pointer past this TD, |
2912 | * or it will attempt to resend it on the next doorbell ring. | |
2913 | */ | |
2914 | xhci_find_new_dequeue_state(xhci, udev->slot_id, | |
d36374fd | 2915 | ep_index, stream_id, td, &deq_state); |
82d1009f | 2916 | |
365038d8 MN |
2917 | if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg) |
2918 | return; | |
2919 | ||
ac9d8fe7 SS |
2920 | /* HW with the reset endpoint quirk will use the saved dequeue state to |
2921 | * issue a configure endpoint command later. | |
2922 | */ | |
2923 | if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) { | |
a0254324 XR |
2924 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2925 | "Queueing new dequeue state"); | |
1e3452e3 | 2926 | xhci_queue_new_dequeue_state(xhci, udev->slot_id, |
8790736d | 2927 | ep_index, &deq_state); |
ac9d8fe7 SS |
2928 | } else { |
2929 | /* Better hope no one uses the input context between now and the | |
2930 | * reset endpoint completion! | |
e9df17eb SS |
2931 | * XXX: No idea how this hardware will react when stream rings |
2932 | * are enabled. | |
ac9d8fe7 | 2933 | */ |
4bdfe4c3 XR |
2934 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2935 | "Setting up input context for " | |
2936 | "configure endpoint command"); | |
ac9d8fe7 SS |
2937 | xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id, |
2938 | ep_index, &deq_state); | |
2939 | } | |
82d1009f SS |
2940 | } |
2941 | ||
d0167ad2 | 2942 | /* Called when clearing halted device. The core should have sent the control |
8e71a322 | 2943 | * message to clear the device halt condition. The host side of the halt should |
d0167ad2 MN |
2944 | * already be cleared with a reset endpoint command issued when the STALL tx |
2945 | * event was received. | |
2946 | * | |
2947 | * Context: in_interrupt | |
a1587d97 | 2948 | */ |
8e71a322 | 2949 | |
3969384c | 2950 | static void xhci_endpoint_reset(struct usb_hcd *hcd, |
a1587d97 SS |
2951 | struct usb_host_endpoint *ep) |
2952 | { | |
2953 | struct xhci_hcd *xhci; | |
a1587d97 SS |
2954 | |
2955 | xhci = hcd_to_xhci(hcd); | |
ddba5cd0 | 2956 | |
c92bcfa7 | 2957 | /* |
d0167ad2 | 2958 | * We might need to implement the config ep cmd in xhci 4.8.1 note: |
8e71a322 MN |
2959 | * The Reset Endpoint Command may only be issued to endpoints in the |
2960 | * Halted state. If software wishes reset the Data Toggle or Sequence | |
2961 | * Number of an endpoint that isn't in the Halted state, then software | |
2962 | * may issue a Configure Endpoint Command with the Drop and Add bits set | |
2963 | * for the target endpoint. that is in the Stopped state. | |
c92bcfa7 | 2964 | */ |
a1587d97 | 2965 | |
d0167ad2 MN |
2966 | /* For now just print debug to follow the situation */ |
2967 | xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n", | |
2968 | ep->desc.bEndpointAddress); | |
a1587d97 SS |
2969 | } |
2970 | ||
8df75f42 SS |
2971 | static int xhci_check_streams_endpoint(struct xhci_hcd *xhci, |
2972 | struct usb_device *udev, struct usb_host_endpoint *ep, | |
2973 | unsigned int slot_id) | |
2974 | { | |
2975 | int ret; | |
2976 | unsigned int ep_index; | |
2977 | unsigned int ep_state; | |
2978 | ||
2979 | if (!ep) | |
2980 | return -EINVAL; | |
64927730 | 2981 | ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__); |
8df75f42 SS |
2982 | if (ret <= 0) |
2983 | return -EINVAL; | |
a3901538 | 2984 | if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) { |
8df75f42 SS |
2985 | xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion" |
2986 | " descriptor for ep 0x%x does not support streams\n", | |
2987 | ep->desc.bEndpointAddress); | |
2988 | return -EINVAL; | |
2989 | } | |
2990 | ||
2991 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
2992 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
2993 | if (ep_state & EP_HAS_STREAMS || | |
2994 | ep_state & EP_GETTING_STREAMS) { | |
2995 | xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x " | |
2996 | "already has streams set up.\n", | |
2997 | ep->desc.bEndpointAddress); | |
2998 | xhci_warn(xhci, "Send email to xHCI maintainer and ask for " | |
2999 | "dynamic stream context array reallocation.\n"); | |
3000 | return -EINVAL; | |
3001 | } | |
3002 | if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) { | |
3003 | xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk " | |
3004 | "endpoint 0x%x; URBs are pending.\n", | |
3005 | ep->desc.bEndpointAddress); | |
3006 | return -EINVAL; | |
3007 | } | |
3008 | return 0; | |
3009 | } | |
3010 | ||
3011 | static void xhci_calculate_streams_entries(struct xhci_hcd *xhci, | |
3012 | unsigned int *num_streams, unsigned int *num_stream_ctxs) | |
3013 | { | |
3014 | unsigned int max_streams; | |
3015 | ||
3016 | /* The stream context array size must be a power of two */ | |
3017 | *num_stream_ctxs = roundup_pow_of_two(*num_streams); | |
3018 | /* | |
3019 | * Find out how many primary stream array entries the host controller | |
3020 | * supports. Later we may use secondary stream arrays (similar to 2nd | |
3021 | * level page entries), but that's an optional feature for xHCI host | |
3022 | * controllers. xHCs must support at least 4 stream IDs. | |
3023 | */ | |
3024 | max_streams = HCC_MAX_PSA(xhci->hcc_params); | |
3025 | if (*num_stream_ctxs > max_streams) { | |
3026 | xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n", | |
3027 | max_streams); | |
3028 | *num_stream_ctxs = max_streams; | |
3029 | *num_streams = max_streams; | |
3030 | } | |
3031 | } | |
3032 | ||
3033 | /* Returns an error code if one of the endpoint already has streams. | |
3034 | * This does not change any data structures, it only checks and gathers | |
3035 | * information. | |
3036 | */ | |
3037 | static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci, | |
3038 | struct usb_device *udev, | |
3039 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
3040 | unsigned int *num_streams, u32 *changed_ep_bitmask) | |
3041 | { | |
8df75f42 SS |
3042 | unsigned int max_streams; |
3043 | unsigned int endpoint_flag; | |
3044 | int i; | |
3045 | int ret; | |
3046 | ||
3047 | for (i = 0; i < num_eps; i++) { | |
3048 | ret = xhci_check_streams_endpoint(xhci, udev, | |
3049 | eps[i], udev->slot_id); | |
3050 | if (ret < 0) | |
3051 | return ret; | |
3052 | ||
18b7ede5 | 3053 | max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp); |
8df75f42 SS |
3054 | if (max_streams < (*num_streams - 1)) { |
3055 | xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n", | |
3056 | eps[i]->desc.bEndpointAddress, | |
3057 | max_streams); | |
3058 | *num_streams = max_streams+1; | |
3059 | } | |
3060 | ||
3061 | endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc); | |
3062 | if (*changed_ep_bitmask & endpoint_flag) | |
3063 | return -EINVAL; | |
3064 | *changed_ep_bitmask |= endpoint_flag; | |
3065 | } | |
3066 | return 0; | |
3067 | } | |
3068 | ||
3069 | static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci, | |
3070 | struct usb_device *udev, | |
3071 | struct usb_host_endpoint **eps, unsigned int num_eps) | |
3072 | { | |
3073 | u32 changed_ep_bitmask = 0; | |
3074 | unsigned int slot_id; | |
3075 | unsigned int ep_index; | |
3076 | unsigned int ep_state; | |
3077 | int i; | |
3078 | ||
3079 | slot_id = udev->slot_id; | |
3080 | if (!xhci->devs[slot_id]) | |
3081 | return 0; | |
3082 | ||
3083 | for (i = 0; i < num_eps; i++) { | |
3084 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3085 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
3086 | /* Are streams already being freed for the endpoint? */ | |
3087 | if (ep_state & EP_GETTING_NO_STREAMS) { | |
3088 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3089 | "endpoint 0x%x, " |
3090 | "streams are being disabled already\n", | |
8df75f42 SS |
3091 | eps[i]->desc.bEndpointAddress); |
3092 | return 0; | |
3093 | } | |
3094 | /* Are there actually any streams to free? */ | |
3095 | if (!(ep_state & EP_HAS_STREAMS) && | |
3096 | !(ep_state & EP_GETTING_STREAMS)) { | |
3097 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3098 | "endpoint 0x%x, " |
3099 | "streams are already disabled!\n", | |
8df75f42 SS |
3100 | eps[i]->desc.bEndpointAddress); |
3101 | xhci_warn(xhci, "WARN xhci_free_streams() called " | |
3102 | "with non-streams endpoint\n"); | |
3103 | return 0; | |
3104 | } | |
3105 | changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc); | |
3106 | } | |
3107 | return changed_ep_bitmask; | |
3108 | } | |
3109 | ||
3110 | /* | |
c2a298d9 | 3111 | * The USB device drivers use this function (through the HCD interface in USB |
8df75f42 SS |
3112 | * core) to prepare a set of bulk endpoints to use streams. Streams are used to |
3113 | * coordinate mass storage command queueing across multiple endpoints (basically | |
3114 | * a stream ID == a task ID). | |
3115 | * | |
3116 | * Setting up streams involves allocating the same size stream context array | |
3117 | * for each endpoint and issuing a configure endpoint command for all endpoints. | |
3118 | * | |
3119 | * Don't allow the call to succeed if one endpoint only supports one stream | |
3120 | * (which means it doesn't support streams at all). | |
3121 | * | |
3122 | * Drivers may get less stream IDs than they asked for, if the host controller | |
3123 | * hardware or endpoints claim they can't support the number of requested | |
3124 | * stream IDs. | |
3125 | */ | |
3969384c | 3126 | static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, |
8df75f42 SS |
3127 | struct usb_host_endpoint **eps, unsigned int num_eps, |
3128 | unsigned int num_streams, gfp_t mem_flags) | |
3129 | { | |
3130 | int i, ret; | |
3131 | struct xhci_hcd *xhci; | |
3132 | struct xhci_virt_device *vdev; | |
3133 | struct xhci_command *config_cmd; | |
92f8e767 | 3134 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3135 | unsigned int ep_index; |
3136 | unsigned int num_stream_ctxs; | |
f9c589e1 | 3137 | unsigned int max_packet; |
8df75f42 SS |
3138 | unsigned long flags; |
3139 | u32 changed_ep_bitmask = 0; | |
3140 | ||
3141 | if (!eps) | |
3142 | return -EINVAL; | |
3143 | ||
3144 | /* Add one to the number of streams requested to account for | |
3145 | * stream 0 that is reserved for xHCI usage. | |
3146 | */ | |
3147 | num_streams += 1; | |
3148 | xhci = hcd_to_xhci(hcd); | |
3149 | xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n", | |
3150 | num_streams); | |
3151 | ||
f7920884 | 3152 | /* MaxPSASize value 0 (2 streams) means streams are not supported */ |
8f873c1f HG |
3153 | if ((xhci->quirks & XHCI_BROKEN_STREAMS) || |
3154 | HCC_MAX_PSA(xhci->hcc_params) < 4) { | |
f7920884 HG |
3155 | xhci_dbg(xhci, "xHCI controller does not support streams.\n"); |
3156 | return -ENOSYS; | |
3157 | } | |
3158 | ||
8df75f42 | 3159 | config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); |
74e0b564 | 3160 | if (!config_cmd) |
8df75f42 | 3161 | return -ENOMEM; |
74e0b564 | 3162 | |
4daf9df5 | 3163 | ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx); |
92f8e767 SS |
3164 | if (!ctrl_ctx) { |
3165 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3166 | __func__); | |
3167 | xhci_free_command(xhci, config_cmd); | |
3168 | return -ENOMEM; | |
3169 | } | |
8df75f42 SS |
3170 | |
3171 | /* Check to make sure all endpoints are not already configured for | |
3172 | * streams. While we're at it, find the maximum number of streams that | |
3173 | * all the endpoints will support and check for duplicate endpoints. | |
3174 | */ | |
3175 | spin_lock_irqsave(&xhci->lock, flags); | |
3176 | ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps, | |
3177 | num_eps, &num_streams, &changed_ep_bitmask); | |
3178 | if (ret < 0) { | |
3179 | xhci_free_command(xhci, config_cmd); | |
3180 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3181 | return ret; | |
3182 | } | |
3183 | if (num_streams <= 1) { | |
3184 | xhci_warn(xhci, "WARN: endpoints can't handle " | |
3185 | "more than one stream.\n"); | |
3186 | xhci_free_command(xhci, config_cmd); | |
3187 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3188 | return -EINVAL; | |
3189 | } | |
3190 | vdev = xhci->devs[udev->slot_id]; | |
25985edc | 3191 | /* Mark each endpoint as being in transition, so |
8df75f42 SS |
3192 | * xhci_urb_enqueue() will reject all URBs. |
3193 | */ | |
3194 | for (i = 0; i < num_eps; i++) { | |
3195 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3196 | vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS; | |
3197 | } | |
3198 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3199 | ||
3200 | /* Setup internal data structures and allocate HW data structures for | |
3201 | * streams (but don't install the HW structures in the input context | |
3202 | * until we're sure all memory allocation succeeded). | |
3203 | */ | |
3204 | xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs); | |
3205 | xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n", | |
3206 | num_stream_ctxs, num_streams); | |
3207 | ||
3208 | for (i = 0; i < num_eps; i++) { | |
3209 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
734d3ddd | 3210 | max_packet = usb_endpoint_maxp(&eps[i]->desc); |
8df75f42 SS |
3211 | vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci, |
3212 | num_stream_ctxs, | |
f9c589e1 MN |
3213 | num_streams, |
3214 | max_packet, mem_flags); | |
8df75f42 SS |
3215 | if (!vdev->eps[ep_index].stream_info) |
3216 | goto cleanup; | |
3217 | /* Set maxPstreams in endpoint context and update deq ptr to | |
3218 | * point to stream context array. FIXME | |
3219 | */ | |
3220 | } | |
3221 | ||
3222 | /* Set up the input context for a configure endpoint command. */ | |
3223 | for (i = 0; i < num_eps; i++) { | |
3224 | struct xhci_ep_ctx *ep_ctx; | |
3225 | ||
3226 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3227 | ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index); | |
3228 | ||
3229 | xhci_endpoint_copy(xhci, config_cmd->in_ctx, | |
3230 | vdev->out_ctx, ep_index); | |
3231 | xhci_setup_streams_ep_input_ctx(xhci, ep_ctx, | |
3232 | vdev->eps[ep_index].stream_info); | |
3233 | } | |
3234 | /* Tell the HW to drop its old copy of the endpoint context info | |
3235 | * and add the updated copy from the input context. | |
3236 | */ | |
3237 | xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx, | |
92f8e767 SS |
3238 | vdev->out_ctx, ctrl_ctx, |
3239 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3240 | |
3241 | /* Issue and wait for the configure endpoint command */ | |
3242 | ret = xhci_configure_endpoint(xhci, udev, config_cmd, | |
3243 | false, false); | |
3244 | ||
3245 | /* xHC rejected the configure endpoint command for some reason, so we | |
3246 | * leave the old ring intact and free our internal streams data | |
3247 | * structure. | |
3248 | */ | |
3249 | if (ret < 0) | |
3250 | goto cleanup; | |
3251 | ||
3252 | spin_lock_irqsave(&xhci->lock, flags); | |
3253 | for (i = 0; i < num_eps; i++) { | |
3254 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3255 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3256 | xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n", | |
3257 | udev->slot_id, ep_index); | |
3258 | vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS; | |
3259 | } | |
3260 | xhci_free_command(xhci, config_cmd); | |
3261 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3262 | ||
3263 | /* Subtract 1 for stream 0, which drivers can't use */ | |
3264 | return num_streams - 1; | |
3265 | ||
3266 | cleanup: | |
3267 | /* If it didn't work, free the streams! */ | |
3268 | for (i = 0; i < num_eps; i++) { | |
3269 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3270 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3271 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3272 | /* FIXME Unset maxPstreams in endpoint context and |
3273 | * update deq ptr to point to normal string ring. | |
3274 | */ | |
3275 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3276 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3277 | xhci_endpoint_zero(xhci, vdev, eps[i]); | |
3278 | } | |
3279 | xhci_free_command(xhci, config_cmd); | |
3280 | return -ENOMEM; | |
3281 | } | |
3282 | ||
3283 | /* Transition the endpoint from using streams to being a "normal" endpoint | |
3284 | * without streams. | |
3285 | * | |
3286 | * Modify the endpoint context state, submit a configure endpoint command, | |
3287 | * and free all endpoint rings for streams if that completes successfully. | |
3288 | */ | |
3969384c | 3289 | static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, |
8df75f42 SS |
3290 | struct usb_host_endpoint **eps, unsigned int num_eps, |
3291 | gfp_t mem_flags) | |
3292 | { | |
3293 | int i, ret; | |
3294 | struct xhci_hcd *xhci; | |
3295 | struct xhci_virt_device *vdev; | |
3296 | struct xhci_command *command; | |
92f8e767 | 3297 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3298 | unsigned int ep_index; |
3299 | unsigned long flags; | |
3300 | u32 changed_ep_bitmask; | |
3301 | ||
3302 | xhci = hcd_to_xhci(hcd); | |
3303 | vdev = xhci->devs[udev->slot_id]; | |
3304 | ||
3305 | /* Set up a configure endpoint command to remove the streams rings */ | |
3306 | spin_lock_irqsave(&xhci->lock, flags); | |
3307 | changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci, | |
3308 | udev, eps, num_eps); | |
3309 | if (changed_ep_bitmask == 0) { | |
3310 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3311 | return -EINVAL; | |
3312 | } | |
3313 | ||
3314 | /* Use the xhci_command structure from the first endpoint. We may have | |
3315 | * allocated too many, but the driver may call xhci_free_streams() for | |
3316 | * each endpoint it grouped into one call to xhci_alloc_streams(). | |
3317 | */ | |
3318 | ep_index = xhci_get_endpoint_index(&eps[0]->desc); | |
3319 | command = vdev->eps[ep_index].stream_info->free_streams_command; | |
4daf9df5 | 3320 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 | 3321 | if (!ctrl_ctx) { |
1f21569c | 3322 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
3323 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
3324 | __func__); | |
3325 | return -EINVAL; | |
3326 | } | |
3327 | ||
8df75f42 SS |
3328 | for (i = 0; i < num_eps; i++) { |
3329 | struct xhci_ep_ctx *ep_ctx; | |
3330 | ||
3331 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3332 | ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index); | |
3333 | xhci->devs[udev->slot_id]->eps[ep_index].ep_state |= | |
3334 | EP_GETTING_NO_STREAMS; | |
3335 | ||
3336 | xhci_endpoint_copy(xhci, command->in_ctx, | |
3337 | vdev->out_ctx, ep_index); | |
4daf9df5 | 3338 | xhci_setup_no_streams_ep_input_ctx(ep_ctx, |
8df75f42 SS |
3339 | &vdev->eps[ep_index]); |
3340 | } | |
3341 | xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx, | |
92f8e767 SS |
3342 | vdev->out_ctx, ctrl_ctx, |
3343 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3344 | spin_unlock_irqrestore(&xhci->lock, flags); |
3345 | ||
3346 | /* Issue and wait for the configure endpoint command, | |
3347 | * which must succeed. | |
3348 | */ | |
3349 | ret = xhci_configure_endpoint(xhci, udev, command, | |
3350 | false, true); | |
3351 | ||
3352 | /* xHC rejected the configure endpoint command for some reason, so we | |
3353 | * leave the streams rings intact. | |
3354 | */ | |
3355 | if (ret < 0) | |
3356 | return ret; | |
3357 | ||
3358 | spin_lock_irqsave(&xhci->lock, flags); | |
3359 | for (i = 0; i < num_eps; i++) { | |
3360 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3361 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3362 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3363 | /* FIXME Unset maxPstreams in endpoint context and |
3364 | * update deq ptr to point to normal string ring. | |
3365 | */ | |
3366 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS; | |
3367 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3368 | } | |
3369 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3370 | ||
3371 | return 0; | |
3372 | } | |
3373 | ||
2cf95c18 SS |
3374 | /* |
3375 | * Deletes endpoint resources for endpoints that were active before a Reset | |
3376 | * Device command, or a Disable Slot command. The Reset Device command leaves | |
3377 | * the control endpoint intact, whereas the Disable Slot command deletes it. | |
3378 | * | |
3379 | * Must be called with xhci->lock held. | |
3380 | */ | |
3381 | void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, | |
3382 | struct xhci_virt_device *virt_dev, bool drop_control_ep) | |
3383 | { | |
3384 | int i; | |
3385 | unsigned int num_dropped_eps = 0; | |
3386 | unsigned int drop_flags = 0; | |
3387 | ||
3388 | for (i = (drop_control_ep ? 0 : 1); i < 31; i++) { | |
3389 | if (virt_dev->eps[i].ring) { | |
3390 | drop_flags |= 1 << i; | |
3391 | num_dropped_eps++; | |
3392 | } | |
3393 | } | |
3394 | xhci->num_active_eps -= num_dropped_eps; | |
3395 | if (num_dropped_eps) | |
4bdfe4c3 XR |
3396 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3397 | "Dropped %u ep ctxs, flags = 0x%x, " | |
3398 | "%u now active.", | |
2cf95c18 SS |
3399 | num_dropped_eps, drop_flags, |
3400 | xhci->num_active_eps); | |
3401 | } | |
3402 | ||
2a8f82c4 SS |
3403 | /* |
3404 | * This submits a Reset Device Command, which will set the device state to 0, | |
3405 | * set the device address to 0, and disable all the endpoints except the default | |
3406 | * control endpoint. The USB core should come back and call | |
3407 | * xhci_address_device(), and then re-set up the configuration. If this is | |
3408 | * called because of a usb_reset_and_verify_device(), then the old alternate | |
3409 | * settings will be re-installed through the normal bandwidth allocation | |
3410 | * functions. | |
3411 | * | |
3412 | * Wait for the Reset Device command to finish. Remove all structures | |
3413 | * associated with the endpoints that were disabled. Clear the input device | |
c5628a2a | 3414 | * structure? Reset the control endpoint 0 max packet size? |
f0615c45 AX |
3415 | * |
3416 | * If the virt_dev to be reset does not exist or does not match the udev, | |
3417 | * it means the device is lost, possibly due to the xHC restore error and | |
3418 | * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to | |
3419 | * re-allocate the device. | |
2a8f82c4 | 3420 | */ |
3969384c LB |
3421 | static int xhci_discover_or_reset_device(struct usb_hcd *hcd, |
3422 | struct usb_device *udev) | |
2a8f82c4 SS |
3423 | { |
3424 | int ret, i; | |
3425 | unsigned long flags; | |
3426 | struct xhci_hcd *xhci; | |
3427 | unsigned int slot_id; | |
3428 | struct xhci_virt_device *virt_dev; | |
3429 | struct xhci_command *reset_device_cmd; | |
2a8f82c4 | 3430 | int last_freed_endpoint; |
001fd382 | 3431 | struct xhci_slot_ctx *slot_ctx; |
2e27980e | 3432 | int old_active_eps = 0; |
2a8f82c4 | 3433 | |
f0615c45 | 3434 | ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__); |
2a8f82c4 SS |
3435 | if (ret <= 0) |
3436 | return ret; | |
3437 | xhci = hcd_to_xhci(hcd); | |
3438 | slot_id = udev->slot_id; | |
3439 | virt_dev = xhci->devs[slot_id]; | |
f0615c45 AX |
3440 | if (!virt_dev) { |
3441 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3442 | "not exist. Re-allocate the device\n", slot_id); | |
3443 | ret = xhci_alloc_dev(hcd, udev); | |
3444 | if (ret == 1) | |
3445 | return 0; | |
3446 | else | |
3447 | return -EINVAL; | |
3448 | } | |
3449 | ||
326124a0 BC |
3450 | if (virt_dev->tt_info) |
3451 | old_active_eps = virt_dev->tt_info->active_eps; | |
3452 | ||
f0615c45 AX |
3453 | if (virt_dev->udev != udev) { |
3454 | /* If the virt_dev and the udev does not match, this virt_dev | |
3455 | * may belong to another udev. | |
3456 | * Re-allocate the device. | |
3457 | */ | |
3458 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3459 | "not match the udev. Re-allocate the device\n", | |
3460 | slot_id); | |
3461 | ret = xhci_alloc_dev(hcd, udev); | |
3462 | if (ret == 1) | |
3463 | return 0; | |
3464 | else | |
3465 | return -EINVAL; | |
3466 | } | |
2a8f82c4 | 3467 | |
001fd382 ML |
3468 | /* If device is not setup, there is no point in resetting it */ |
3469 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
3470 | if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == | |
3471 | SLOT_STATE_DISABLED) | |
3472 | return 0; | |
3473 | ||
19a7d0d6 FB |
3474 | trace_xhci_discover_or_reset_device(slot_ctx); |
3475 | ||
2a8f82c4 SS |
3476 | xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id); |
3477 | /* Allocate the command structure that holds the struct completion. | |
3478 | * Assume we're in process context, since the normal device reset | |
3479 | * process has to wait for the device anyway. Storage devices are | |
3480 | * reset as part of error handling, so use GFP_NOIO instead of | |
3481 | * GFP_KERNEL. | |
3482 | */ | |
3483 | reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); | |
3484 | if (!reset_device_cmd) { | |
3485 | xhci_dbg(xhci, "Couldn't allocate command structure.\n"); | |
3486 | return -ENOMEM; | |
3487 | } | |
3488 | ||
3489 | /* Attempt to submit the Reset Device command to the command ring */ | |
3490 | spin_lock_irqsave(&xhci->lock, flags); | |
7a3783ef | 3491 | |
ddba5cd0 | 3492 | ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id); |
2a8f82c4 SS |
3493 | if (ret) { |
3494 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
2a8f82c4 SS |
3495 | spin_unlock_irqrestore(&xhci->lock, flags); |
3496 | goto command_cleanup; | |
3497 | } | |
3498 | xhci_ring_cmd_db(xhci); | |
3499 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3500 | ||
3501 | /* Wait for the Reset Device command to finish */ | |
c311e391 | 3502 | wait_for_completion(reset_device_cmd->completion); |
2a8f82c4 SS |
3503 | |
3504 | /* The Reset Device command can't fail, according to the 0.95/0.96 spec, | |
3505 | * unless we tried to reset a slot ID that wasn't enabled, | |
3506 | * or the device wasn't in the addressed or configured state. | |
3507 | */ | |
3508 | ret = reset_device_cmd->status; | |
3509 | switch (ret) { | |
0b7c105a | 3510 | case COMP_COMMAND_ABORTED: |
604d02a2 | 3511 | case COMP_COMMAND_RING_STOPPED: |
c311e391 MN |
3512 | xhci_warn(xhci, "Timeout waiting for reset device command\n"); |
3513 | ret = -ETIME; | |
3514 | goto command_cleanup; | |
0b7c105a FB |
3515 | case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */ |
3516 | case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */ | |
38a532a6 | 3517 | xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n", |
2a8f82c4 SS |
3518 | slot_id, |
3519 | xhci_get_slot_state(xhci, virt_dev->out_ctx)); | |
38a532a6 | 3520 | xhci_dbg(xhci, "Not freeing device rings.\n"); |
2a8f82c4 SS |
3521 | /* Don't treat this as an error. May change my mind later. */ |
3522 | ret = 0; | |
3523 | goto command_cleanup; | |
3524 | case COMP_SUCCESS: | |
3525 | xhci_dbg(xhci, "Successful reset device command.\n"); | |
3526 | break; | |
3527 | default: | |
3528 | if (xhci_is_vendor_info_code(xhci, ret)) | |
3529 | break; | |
3530 | xhci_warn(xhci, "Unknown completion code %u for " | |
3531 | "reset device command.\n", ret); | |
3532 | ret = -EINVAL; | |
3533 | goto command_cleanup; | |
3534 | } | |
3535 | ||
2cf95c18 SS |
3536 | /* Free up host controller endpoint resources */ |
3537 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
3538 | spin_lock_irqsave(&xhci->lock, flags); | |
3539 | /* Don't delete the default control endpoint resources */ | |
3540 | xhci_free_device_endpoint_resources(xhci, virt_dev, false); | |
3541 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3542 | } | |
3543 | ||
c5628a2a | 3544 | /* Everything but endpoint 0 is disabled, so free the rings. */ |
2a8f82c4 | 3545 | last_freed_endpoint = 1; |
98871e94 | 3546 | for (i = 1; i < 31; i++) { |
2dea75d9 DT |
3547 | struct xhci_virt_ep *ep = &virt_dev->eps[i]; |
3548 | ||
3549 | if (ep->ep_state & EP_HAS_STREAMS) { | |
df613834 HG |
3550 | xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n", |
3551 | xhci_get_endpoint_address(i)); | |
2dea75d9 DT |
3552 | xhci_free_stream_info(xhci, ep->stream_info); |
3553 | ep->stream_info = NULL; | |
3554 | ep->ep_state &= ~EP_HAS_STREAMS; | |
3555 | } | |
3556 | ||
3557 | if (ep->ring) { | |
02b6fdc2 | 3558 | xhci_debugfs_remove_endpoint(xhci, virt_dev, i); |
c5628a2a | 3559 | xhci_free_endpoint_ring(xhci, virt_dev, i); |
2dea75d9 DT |
3560 | last_freed_endpoint = i; |
3561 | } | |
2e27980e SS |
3562 | if (!list_empty(&virt_dev->eps[i].bw_endpoint_list)) |
3563 | xhci_drop_ep_from_interval_table(xhci, | |
3564 | &virt_dev->eps[i].bw_info, | |
3565 | virt_dev->bw_table, | |
3566 | udev, | |
3567 | &virt_dev->eps[i], | |
3568 | virt_dev->tt_info); | |
9af5d71d | 3569 | xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info); |
2a8f82c4 | 3570 | } |
2e27980e SS |
3571 | /* If necessary, update the number of active TTs on this root port */ |
3572 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
2a8f82c4 SS |
3573 | ret = 0; |
3574 | ||
3575 | command_cleanup: | |
3576 | xhci_free_command(xhci, reset_device_cmd); | |
3577 | return ret; | |
3578 | } | |
3579 | ||
3ffbba95 SS |
3580 | /* |
3581 | * At this point, the struct usb_device is about to go away, the device has | |
3582 | * disconnected, and all traffic has been stopped and the endpoints have been | |
3583 | * disabled. Free any HC data structures associated with that device. | |
3584 | */ | |
3969384c | 3585 | static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) |
3ffbba95 SS |
3586 | { |
3587 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
6f5165cf | 3588 | struct xhci_virt_device *virt_dev; |
19a7d0d6 | 3589 | struct xhci_slot_ctx *slot_ctx; |
64927730 | 3590 | int i, ret; |
ddba5cd0 | 3591 | |
c8476fb8 SN |
3592 | #ifndef CONFIG_USB_DEFAULT_PERSIST |
3593 | /* | |
3594 | * We called pm_runtime_get_noresume when the device was attached. | |
3595 | * Decrement the counter here to allow controller to runtime suspend | |
3596 | * if no devices remain. | |
3597 | */ | |
3598 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | |
e7ecf069 | 3599 | pm_runtime_put_noidle(hcd->self.controller); |
c8476fb8 SN |
3600 | #endif |
3601 | ||
64927730 | 3602 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
7bd89b40 SS |
3603 | /* If the host is halted due to driver unload, we still need to free the |
3604 | * device. | |
3605 | */ | |
cd3f1790 | 3606 | if (ret <= 0 && ret != -ENODEV) |
3ffbba95 | 3607 | return; |
64927730 | 3608 | |
6f5165cf | 3609 | virt_dev = xhci->devs[udev->slot_id]; |
19a7d0d6 FB |
3610 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
3611 | trace_xhci_free_dev(slot_ctx); | |
6f5165cf SS |
3612 | |
3613 | /* Stop any wayward timer functions (which may grab the lock) */ | |
98871e94 | 3614 | for (i = 0; i < 31; i++) { |
9983a5fc | 3615 | virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING; |
6f5165cf SS |
3616 | del_timer_sync(&virt_dev->eps[i].stop_cmd_timer); |
3617 | } | |
92953db5 | 3618 | xhci_debugfs_remove_slot(xhci, udev->slot_id); |
a4b035a6 | 3619 | virt_dev->udev = NULL; |
11ec7588 | 3620 | ret = xhci_disable_slot(xhci, udev->slot_id); |
92953db5 | 3621 | if (ret) |
11ec7588 | 3622 | xhci_free_virt_device(xhci, udev->slot_id); |
f9e609b8 GZ |
3623 | } |
3624 | ||
cd3f1790 | 3625 | int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id) |
f9e609b8 | 3626 | { |
cd3f1790 | 3627 | struct xhci_command *command; |
f9e609b8 GZ |
3628 | unsigned long flags; |
3629 | u32 state; | |
3630 | int ret = 0; | |
f9e609b8 | 3631 | |
cd3f1790 | 3632 | command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); |
f9e609b8 GZ |
3633 | if (!command) |
3634 | return -ENOMEM; | |
3635 | ||
3ffbba95 | 3636 | spin_lock_irqsave(&xhci->lock, flags); |
c526d0d4 | 3637 | /* Don't disable the slot if the host controller is dead. */ |
b0ba9720 | 3638 | state = readl(&xhci->op_regs->status); |
7bd89b40 SS |
3639 | if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) || |
3640 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
c526d0d4 | 3641 | spin_unlock_irqrestore(&xhci->lock, flags); |
ddba5cd0 | 3642 | kfree(command); |
dcabc76f | 3643 | return -ENODEV; |
c526d0d4 SS |
3644 | } |
3645 | ||
f9e609b8 GZ |
3646 | ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT, |
3647 | slot_id); | |
3648 | if (ret) { | |
3ffbba95 | 3649 | spin_unlock_irqrestore(&xhci->lock, flags); |
cd3f1790 | 3650 | kfree(command); |
f9e609b8 | 3651 | return ret; |
3ffbba95 | 3652 | } |
23e3be11 | 3653 | xhci_ring_cmd_db(xhci); |
3ffbba95 | 3654 | spin_unlock_irqrestore(&xhci->lock, flags); |
f9e609b8 | 3655 | return ret; |
3ffbba95 SS |
3656 | } |
3657 | ||
2cf95c18 SS |
3658 | /* |
3659 | * Checks if we have enough host controller resources for the default control | |
3660 | * endpoint. | |
3661 | * | |
3662 | * Must be called with xhci->lock held. | |
3663 | */ | |
3664 | static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci) | |
3665 | { | |
3666 | if (xhci->num_active_eps + 1 > xhci->limit_active_eps) { | |
4bdfe4c3 XR |
3667 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3668 | "Not enough ep ctxs: " | |
3669 | "%u active, need to add 1, limit is %u.", | |
2cf95c18 SS |
3670 | xhci->num_active_eps, xhci->limit_active_eps); |
3671 | return -ENOMEM; | |
3672 | } | |
3673 | xhci->num_active_eps += 1; | |
4bdfe4c3 XR |
3674 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3675 | "Adding 1 ep ctx, %u now active.", | |
2cf95c18 SS |
3676 | xhci->num_active_eps); |
3677 | return 0; | |
3678 | } | |
3679 | ||
3680 | ||
3ffbba95 SS |
3681 | /* |
3682 | * Returns 0 if the xHC ran out of device slots, the Enable Slot command | |
3683 | * timed out, or allocating memory failed. Returns 1 on success. | |
3684 | */ | |
3685 | int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
3686 | { | |
3687 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
19a7d0d6 FB |
3688 | struct xhci_virt_device *vdev; |
3689 | struct xhci_slot_ctx *slot_ctx; | |
3ffbba95 | 3690 | unsigned long flags; |
a00918d0 | 3691 | int ret, slot_id; |
ddba5cd0 MN |
3692 | struct xhci_command *command; |
3693 | ||
87e44f2a | 3694 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); |
ddba5cd0 MN |
3695 | if (!command) |
3696 | return 0; | |
3ffbba95 SS |
3697 | |
3698 | spin_lock_irqsave(&xhci->lock, flags); | |
ddba5cd0 | 3699 | ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0); |
3ffbba95 SS |
3700 | if (ret) { |
3701 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3702 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
87e44f2a | 3703 | xhci_free_command(xhci, command); |
3ffbba95 SS |
3704 | return 0; |
3705 | } | |
23e3be11 | 3706 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3707 | spin_unlock_irqrestore(&xhci->lock, flags); |
3708 | ||
c311e391 | 3709 | wait_for_completion(command->completion); |
c2d3d49b | 3710 | slot_id = command->slot_id; |
3ffbba95 | 3711 | |
a00918d0 | 3712 | if (!slot_id || command->status != COMP_SUCCESS) { |
3ffbba95 | 3713 | xhci_err(xhci, "Error while assigning device slot ID\n"); |
be982038 SS |
3714 | xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n", |
3715 | HCS_MAX_SLOTS( | |
3716 | readl(&xhci->cap_regs->hcs_params1))); | |
87e44f2a | 3717 | xhci_free_command(xhci, command); |
3ffbba95 SS |
3718 | return 0; |
3719 | } | |
2cf95c18 | 3720 | |
cd3f1790 LB |
3721 | xhci_free_command(xhci, command); |
3722 | ||
2cf95c18 SS |
3723 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { |
3724 | spin_lock_irqsave(&xhci->lock, flags); | |
3725 | ret = xhci_reserve_host_control_ep_resources(xhci); | |
3726 | if (ret) { | |
3727 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3728 | xhci_warn(xhci, "Not enough host resources, " | |
3729 | "active endpoint contexts = %u\n", | |
3730 | xhci->num_active_eps); | |
3731 | goto disable_slot; | |
3732 | } | |
3733 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3734 | } | |
3735 | /* Use GFP_NOIO, since this function can be called from | |
a6d940dd SS |
3736 | * xhci_discover_or_reset_device(), which may be called as part of |
3737 | * mass storage driver error handling. | |
3738 | */ | |
a00918d0 | 3739 | if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) { |
3ffbba95 | 3740 | xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); |
2cf95c18 | 3741 | goto disable_slot; |
3ffbba95 | 3742 | } |
19a7d0d6 FB |
3743 | vdev = xhci->devs[slot_id]; |
3744 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); | |
3745 | trace_xhci_alloc_dev(slot_ctx); | |
3746 | ||
a00918d0 | 3747 | udev->slot_id = slot_id; |
c8476fb8 | 3748 | |
02b6fdc2 LB |
3749 | xhci_debugfs_create_slot(xhci, slot_id); |
3750 | ||
c8476fb8 SN |
3751 | #ifndef CONFIG_USB_DEFAULT_PERSIST |
3752 | /* | |
3753 | * If resetting upon resume, we can't put the controller into runtime | |
3754 | * suspend if there is a device attached. | |
3755 | */ | |
3756 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | |
e7ecf069 | 3757 | pm_runtime_get_noresume(hcd->self.controller); |
c8476fb8 SN |
3758 | #endif |
3759 | ||
3ffbba95 SS |
3760 | /* Is this a LS or FS device under a HS hub? */ |
3761 | /* Hub or peripherial? */ | |
3ffbba95 | 3762 | return 1; |
2cf95c18 SS |
3763 | |
3764 | disable_slot: | |
11ec7588 LB |
3765 | ret = xhci_disable_slot(xhci, udev->slot_id); |
3766 | if (ret) | |
3767 | xhci_free_virt_device(xhci, udev->slot_id); | |
3768 | ||
3769 | return 0; | |
3ffbba95 SS |
3770 | } |
3771 | ||
3772 | /* | |
48fc7dbd DW |
3773 | * Issue an Address Device command and optionally send a corresponding |
3774 | * SetAddress request to the device. | |
3ffbba95 | 3775 | */ |
48fc7dbd DW |
3776 | static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, |
3777 | enum xhci_setup_dev setup) | |
3ffbba95 | 3778 | { |
6f8ffc0b | 3779 | const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address"; |
3ffbba95 | 3780 | unsigned long flags; |
3ffbba95 SS |
3781 | struct xhci_virt_device *virt_dev; |
3782 | int ret = 0; | |
3783 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
d115b048 JY |
3784 | struct xhci_slot_ctx *slot_ctx; |
3785 | struct xhci_input_control_ctx *ctrl_ctx; | |
8e595a5d | 3786 | u64 temp_64; |
a00918d0 CB |
3787 | struct xhci_command *command = NULL; |
3788 | ||
3789 | mutex_lock(&xhci->mutex); | |
3ffbba95 | 3790 | |
90797aee LB |
3791 | if (xhci->xhc_state) { /* dying, removing or halted */ |
3792 | ret = -ESHUTDOWN; | |
448116bf | 3793 | goto out; |
90797aee | 3794 | } |
448116bf | 3795 | |
3ffbba95 | 3796 | if (!udev->slot_id) { |
84a99f6f XR |
3797 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3798 | "Bad Slot ID %d", udev->slot_id); | |
a00918d0 CB |
3799 | ret = -EINVAL; |
3800 | goto out; | |
3ffbba95 SS |
3801 | } |
3802 | ||
3ffbba95 SS |
3803 | virt_dev = xhci->devs[udev->slot_id]; |
3804 | ||
7ed603ec ME |
3805 | if (WARN_ON(!virt_dev)) { |
3806 | /* | |
3807 | * In plug/unplug torture test with an NEC controller, | |
3808 | * a zero-dereference was observed once due to virt_dev = 0. | |
3809 | * Print useful debug rather than crash if it is observed again! | |
3810 | */ | |
3811 | xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n", | |
3812 | udev->slot_id); | |
a00918d0 CB |
3813 | ret = -EINVAL; |
3814 | goto out; | |
7ed603ec | 3815 | } |
19a7d0d6 FB |
3816 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
3817 | trace_xhci_setup_device_slot(slot_ctx); | |
7ed603ec | 3818 | |
f161ead7 | 3819 | if (setup == SETUP_CONTEXT_ONLY) { |
f161ead7 MN |
3820 | if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == |
3821 | SLOT_STATE_DEFAULT) { | |
3822 | xhci_dbg(xhci, "Slot already in default state\n"); | |
a00918d0 | 3823 | goto out; |
f161ead7 MN |
3824 | } |
3825 | } | |
3826 | ||
87e44f2a | 3827 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); |
a00918d0 CB |
3828 | if (!command) { |
3829 | ret = -ENOMEM; | |
3830 | goto out; | |
3831 | } | |
ddba5cd0 MN |
3832 | |
3833 | command->in_ctx = virt_dev->in_ctx; | |
ddba5cd0 | 3834 | |
f0615c45 | 3835 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
4daf9df5 | 3836 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
92f8e767 SS |
3837 | if (!ctrl_ctx) { |
3838 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3839 | __func__); | |
a00918d0 CB |
3840 | ret = -EINVAL; |
3841 | goto out; | |
92f8e767 | 3842 | } |
f0615c45 AX |
3843 | /* |
3844 | * If this is the first Set Address since device plug-in or | |
3845 | * virt_device realloaction after a resume with an xHCI power loss, | |
3846 | * then set up the slot context. | |
3847 | */ | |
3848 | if (!slot_ctx->dev_info) | |
3ffbba95 | 3849 | xhci_setup_addressable_virt_dev(xhci, udev); |
f0615c45 | 3850 | /* Otherwise, update the control endpoint ring enqueue pointer. */ |
2d1ee590 SS |
3851 | else |
3852 | xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev); | |
d31c285b SS |
3853 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); |
3854 | ctrl_ctx->drop_flags = 0; | |
3855 | ||
1d27fabe | 3856 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
0c052aab | 3857 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3ffbba95 | 3858 | |
f88ba78d | 3859 | spin_lock_irqsave(&xhci->lock, flags); |
a711edee | 3860 | trace_xhci_setup_device(virt_dev); |
ddba5cd0 | 3861 | ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma, |
48fc7dbd | 3862 | udev->slot_id, setup); |
3ffbba95 SS |
3863 | if (ret) { |
3864 | spin_unlock_irqrestore(&xhci->lock, flags); | |
84a99f6f XR |
3865 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3866 | "FIXME: allocate a command ring segment"); | |
a00918d0 | 3867 | goto out; |
3ffbba95 | 3868 | } |
23e3be11 | 3869 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3870 | spin_unlock_irqrestore(&xhci->lock, flags); |
3871 | ||
3872 | /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */ | |
c311e391 MN |
3873 | wait_for_completion(command->completion); |
3874 | ||
3ffbba95 SS |
3875 | /* FIXME: From section 4.3.4: "Software shall be responsible for timing |
3876 | * the SetAddress() "recovery interval" required by USB and aborting the | |
3877 | * command on a timeout. | |
3878 | */ | |
9ea1833e | 3879 | switch (command->status) { |
0b7c105a | 3880 | case COMP_COMMAND_ABORTED: |
604d02a2 | 3881 | case COMP_COMMAND_RING_STOPPED: |
c311e391 MN |
3882 | xhci_warn(xhci, "Timeout while waiting for setup device command\n"); |
3883 | ret = -ETIME; | |
3884 | break; | |
0b7c105a FB |
3885 | case COMP_CONTEXT_STATE_ERROR: |
3886 | case COMP_SLOT_NOT_ENABLED_ERROR: | |
6f8ffc0b DW |
3887 | xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n", |
3888 | act, udev->slot_id); | |
3ffbba95 SS |
3889 | ret = -EINVAL; |
3890 | break; | |
0b7c105a | 3891 | case COMP_USB_TRANSACTION_ERROR: |
6f8ffc0b | 3892 | dev_warn(&udev->dev, "Device not responding to setup %s.\n", act); |
651aaf36 LB |
3893 | |
3894 | mutex_unlock(&xhci->mutex); | |
3895 | ret = xhci_disable_slot(xhci, udev->slot_id); | |
3896 | if (!ret) | |
3897 | xhci_alloc_dev(hcd, udev); | |
3898 | kfree(command->completion); | |
3899 | kfree(command); | |
3900 | return -EPROTO; | |
0b7c105a | 3901 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
6f8ffc0b DW |
3902 | dev_warn(&udev->dev, |
3903 | "ERROR: Incompatible device for setup %s command\n", act); | |
f6ba6fe2 AH |
3904 | ret = -ENODEV; |
3905 | break; | |
3ffbba95 | 3906 | case COMP_SUCCESS: |
84a99f6f | 3907 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
6f8ffc0b | 3908 | "Successful setup %s command", act); |
3ffbba95 SS |
3909 | break; |
3910 | default: | |
6f8ffc0b DW |
3911 | xhci_err(xhci, |
3912 | "ERROR: unexpected setup %s command completion code 0x%x.\n", | |
9ea1833e | 3913 | act, command->status); |
1d27fabe | 3914 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1); |
3ffbba95 SS |
3915 | ret = -EINVAL; |
3916 | break; | |
3917 | } | |
a00918d0 CB |
3918 | if (ret) |
3919 | goto out; | |
f7b2e403 | 3920 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
84a99f6f XR |
3921 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3922 | "Op regs DCBAA ptr = %#016llx", temp_64); | |
3923 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
3924 | "Slot ID %d dcbaa entry @%p = %#016llx", | |
3925 | udev->slot_id, | |
3926 | &xhci->dcbaa->dev_context_ptrs[udev->slot_id], | |
3927 | (unsigned long long) | |
3928 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id])); | |
3929 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
3930 | "Output Context DMA address = %#08llx", | |
d115b048 | 3931 | (unsigned long long)virt_dev->out_ctx->dma); |
1d27fabe | 3932 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
0c052aab | 3933 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3ffbba95 SS |
3934 | /* |
3935 | * USB core uses address 1 for the roothubs, so we add one to the | |
3936 | * address given back to us by the HC. | |
3937 | */ | |
1d27fabe | 3938 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, |
0c052aab | 3939 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
f94e0186 | 3940 | /* Zero the input context control for later use */ |
d115b048 JY |
3941 | ctrl_ctx->add_flags = 0; |
3942 | ctrl_ctx->drop_flags = 0; | |
3ffbba95 | 3943 | |
84a99f6f | 3944 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
a2cdc343 DW |
3945 | "Internal device address = %d", |
3946 | le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK); | |
a00918d0 CB |
3947 | out: |
3948 | mutex_unlock(&xhci->mutex); | |
87e44f2a LB |
3949 | if (command) { |
3950 | kfree(command->completion); | |
3951 | kfree(command); | |
3952 | } | |
a00918d0 | 3953 | return ret; |
3ffbba95 SS |
3954 | } |
3955 | ||
3969384c | 3956 | static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) |
48fc7dbd DW |
3957 | { |
3958 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS); | |
3959 | } | |
3960 | ||
3969384c | 3961 | static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev) |
48fc7dbd DW |
3962 | { |
3963 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY); | |
3964 | } | |
3965 | ||
3f5eb141 LT |
3966 | /* |
3967 | * Transfer the port index into real index in the HW port status | |
3968 | * registers. Caculate offset between the port's PORTSC register | |
3969 | * and port status base. Divide the number of per port register | |
3970 | * to get the real index. The raw port number bases 1. | |
3971 | */ | |
3972 | int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1) | |
3973 | { | |
3974 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
3975 | __le32 __iomem *base_addr = &xhci->op_regs->port_status_base; | |
3976 | __le32 __iomem *addr; | |
3977 | int raw_port; | |
3978 | ||
b50107bb | 3979 | if (hcd->speed < HCD_USB3) |
3f5eb141 LT |
3980 | addr = xhci->usb2_ports[port1 - 1]; |
3981 | else | |
3982 | addr = xhci->usb3_ports[port1 - 1]; | |
3983 | ||
3984 | raw_port = (addr - base_addr)/NUM_PORT_REGS + 1; | |
3985 | return raw_port; | |
3986 | } | |
3987 | ||
a558ccdc MN |
3988 | /* |
3989 | * Issue an Evaluate Context command to change the Maximum Exit Latency in the | |
3990 | * slot context. If that succeeds, store the new MEL in the xhci_virt_device. | |
3991 | */ | |
d5c82feb | 3992 | static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci, |
a558ccdc MN |
3993 | struct usb_device *udev, u16 max_exit_latency) |
3994 | { | |
3995 | struct xhci_virt_device *virt_dev; | |
3996 | struct xhci_command *command; | |
3997 | struct xhci_input_control_ctx *ctrl_ctx; | |
3998 | struct xhci_slot_ctx *slot_ctx; | |
3999 | unsigned long flags; | |
4000 | int ret; | |
4001 | ||
4002 | spin_lock_irqsave(&xhci->lock, flags); | |
96044694 MN |
4003 | |
4004 | virt_dev = xhci->devs[udev->slot_id]; | |
4005 | ||
4006 | /* | |
4007 | * virt_dev might not exists yet if xHC resumed from hibernate (S4) and | |
4008 | * xHC was re-initialized. Exit latency will be set later after | |
4009 | * hub_port_finish_reset() is done and xhci->devs[] are re-allocated | |
4010 | */ | |
4011 | ||
4012 | if (!virt_dev || max_exit_latency == virt_dev->current_mel) { | |
a558ccdc MN |
4013 | spin_unlock_irqrestore(&xhci->lock, flags); |
4014 | return 0; | |
4015 | } | |
4016 | ||
4017 | /* Attempt to issue an Evaluate Context command to change the MEL. */ | |
a558ccdc | 4018 | command = xhci->lpm_command; |
4daf9df5 | 4019 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 SS |
4020 | if (!ctrl_ctx) { |
4021 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4022 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
4023 | __func__); | |
4024 | return -ENOMEM; | |
4025 | } | |
4026 | ||
a558ccdc MN |
4027 | xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx); |
4028 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4029 | ||
a558ccdc MN |
4030 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
4031 | slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx); | |
4032 | slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT)); | |
4033 | slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency); | |
4801d4ea | 4034 | slot_ctx->dev_state = 0; |
a558ccdc | 4035 | |
3a7fa5be XR |
4036 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
4037 | "Set up evaluate context for LPM MEL change."); | |
a558ccdc MN |
4038 | |
4039 | /* Issue and wait for the evaluate context command. */ | |
4040 | ret = xhci_configure_endpoint(xhci, udev, command, | |
4041 | true, true); | |
a558ccdc MN |
4042 | |
4043 | if (!ret) { | |
4044 | spin_lock_irqsave(&xhci->lock, flags); | |
4045 | virt_dev->current_mel = max_exit_latency; | |
4046 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4047 | } | |
4048 | return ret; | |
4049 | } | |
4050 | ||
ceb6c9c8 | 4051 | #ifdef CONFIG_PM |
9574323c AX |
4052 | |
4053 | /* BESL to HIRD Encoding array for USB2 LPM */ | |
4054 | static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000, | |
4055 | 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000}; | |
4056 | ||
4057 | /* Calculate HIRD/BESL for USB2 PORTPMSC*/ | |
f99298bf AX |
4058 | static int xhci_calculate_hird_besl(struct xhci_hcd *xhci, |
4059 | struct usb_device *udev) | |
9574323c | 4060 | { |
f99298bf AX |
4061 | int u2del, besl, besl_host; |
4062 | int besl_device = 0; | |
4063 | u32 field; | |
4064 | ||
4065 | u2del = HCS_U2_LATENCY(xhci->hcs_params3); | |
4066 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
9574323c | 4067 | |
f99298bf AX |
4068 | if (field & USB_BESL_SUPPORT) { |
4069 | for (besl_host = 0; besl_host < 16; besl_host++) { | |
4070 | if (xhci_besl_encoding[besl_host] >= u2del) | |
9574323c AX |
4071 | break; |
4072 | } | |
f99298bf AX |
4073 | /* Use baseline BESL value as default */ |
4074 | if (field & USB_BESL_BASELINE_VALID) | |
4075 | besl_device = USB_GET_BESL_BASELINE(field); | |
4076 | else if (field & USB_BESL_DEEP_VALID) | |
4077 | besl_device = USB_GET_BESL_DEEP(field); | |
9574323c AX |
4078 | } else { |
4079 | if (u2del <= 50) | |
f99298bf | 4080 | besl_host = 0; |
9574323c | 4081 | else |
f99298bf | 4082 | besl_host = (u2del - 51) / 75 + 1; |
9574323c AX |
4083 | } |
4084 | ||
f99298bf AX |
4085 | besl = besl_host + besl_device; |
4086 | if (besl > 15) | |
4087 | besl = 15; | |
4088 | ||
4089 | return besl; | |
9574323c AX |
4090 | } |
4091 | ||
a558ccdc MN |
4092 | /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */ |
4093 | static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev) | |
4094 | { | |
4095 | u32 field; | |
4096 | int l1; | |
4097 | int besld = 0; | |
4098 | int hirdm = 0; | |
4099 | ||
4100 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
4101 | ||
4102 | /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */ | |
17f34867 | 4103 | l1 = udev->l1_params.timeout / 256; |
a558ccdc MN |
4104 | |
4105 | /* device has preferred BESLD */ | |
4106 | if (field & USB_BESL_DEEP_VALID) { | |
4107 | besld = USB_GET_BESL_DEEP(field); | |
4108 | hirdm = 1; | |
4109 | } | |
4110 | ||
4111 | return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm); | |
4112 | } | |
4113 | ||
3969384c | 4114 | static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, |
65580b43 AX |
4115 | struct usb_device *udev, int enable) |
4116 | { | |
4117 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4118 | __le32 __iomem **port_array; | |
a558ccdc MN |
4119 | __le32 __iomem *pm_addr, *hlpm_addr; |
4120 | u32 pm_val, hlpm_val, field; | |
65580b43 AX |
4121 | unsigned int port_num; |
4122 | unsigned long flags; | |
a558ccdc MN |
4123 | int hird, exit_latency; |
4124 | int ret; | |
65580b43 | 4125 | |
b50107bb | 4126 | if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support || |
65580b43 AX |
4127 | !udev->lpm_capable) |
4128 | return -EPERM; | |
4129 | ||
4130 | if (!udev->parent || udev->parent->parent || | |
4131 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4132 | return -EPERM; | |
4133 | ||
4134 | if (udev->usb2_hw_lpm_capable != 1) | |
4135 | return -EPERM; | |
4136 | ||
4137 | spin_lock_irqsave(&xhci->lock, flags); | |
4138 | ||
4139 | port_array = xhci->usb2_ports; | |
4140 | port_num = udev->portnum - 1; | |
b6e76371 | 4141 | pm_addr = port_array[port_num] + PORTPMSC; |
b0ba9720 | 4142 | pm_val = readl(pm_addr); |
a558ccdc MN |
4143 | hlpm_addr = port_array[port_num] + PORTHLPMC; |
4144 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
65580b43 AX |
4145 | |
4146 | xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n", | |
654a55d3 | 4147 | enable ? "enable" : "disable", port_num + 1); |
65580b43 | 4148 | |
4750bc78 | 4149 | if (enable && !(xhci->quirks & XHCI_HW_LPM_DISABLE)) { |
a558ccdc MN |
4150 | /* Host supports BESL timeout instead of HIRD */ |
4151 | if (udev->usb2_hw_lpm_besl_capable) { | |
4152 | /* if device doesn't have a preferred BESL value use a | |
4153 | * default one which works with mixed HIRD and BESL | |
4154 | * systems. See XHCI_DEFAULT_BESL definition in xhci.h | |
4155 | */ | |
4156 | if ((field & USB_BESL_SUPPORT) && | |
4157 | (field & USB_BESL_BASELINE_VALID)) | |
4158 | hird = USB_GET_BESL_BASELINE(field); | |
4159 | else | |
17f34867 | 4160 | hird = udev->l1_params.besl; |
a558ccdc MN |
4161 | |
4162 | exit_latency = xhci_besl_encoding[hird]; | |
4163 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4164 | ||
4165 | /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx | |
4166 | * input context for link powermanagement evaluate | |
4167 | * context commands. It is protected by hcd->bandwidth | |
4168 | * mutex and is shared by all devices. We need to set | |
4169 | * the max ext latency in USB 2 BESL LPM as well, so | |
4170 | * use the same mutex and xhci_change_max_exit_latency() | |
4171 | */ | |
4172 | mutex_lock(hcd->bandwidth_mutex); | |
4173 | ret = xhci_change_max_exit_latency(xhci, udev, | |
4174 | exit_latency); | |
4175 | mutex_unlock(hcd->bandwidth_mutex); | |
4176 | ||
4177 | if (ret < 0) | |
4178 | return ret; | |
4179 | spin_lock_irqsave(&xhci->lock, flags); | |
4180 | ||
4181 | hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev); | |
204b7793 | 4182 | writel(hlpm_val, hlpm_addr); |
a558ccdc | 4183 | /* flush write */ |
b0ba9720 | 4184 | readl(hlpm_addr); |
a558ccdc MN |
4185 | } else { |
4186 | hird = xhci_calculate_hird_besl(xhci, udev); | |
4187 | } | |
4188 | ||
4189 | pm_val &= ~PORT_HIRD_MASK; | |
58e21f73 | 4190 | pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id); |
204b7793 | 4191 | writel(pm_val, pm_addr); |
b0ba9720 | 4192 | pm_val = readl(pm_addr); |
a558ccdc | 4193 | pm_val |= PORT_HLE; |
204b7793 | 4194 | writel(pm_val, pm_addr); |
a558ccdc | 4195 | /* flush write */ |
b0ba9720 | 4196 | readl(pm_addr); |
65580b43 | 4197 | } else { |
58e21f73 | 4198 | pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK); |
204b7793 | 4199 | writel(pm_val, pm_addr); |
a558ccdc | 4200 | /* flush write */ |
b0ba9720 | 4201 | readl(pm_addr); |
a558ccdc MN |
4202 | if (udev->usb2_hw_lpm_besl_capable) { |
4203 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4204 | mutex_lock(hcd->bandwidth_mutex); | |
4205 | xhci_change_max_exit_latency(xhci, udev, 0); | |
4206 | mutex_unlock(hcd->bandwidth_mutex); | |
4207 | return 0; | |
4208 | } | |
65580b43 AX |
4209 | } |
4210 | ||
4211 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4212 | return 0; | |
4213 | } | |
4214 | ||
b630d4b9 MN |
4215 | /* check if a usb2 port supports a given extened capability protocol |
4216 | * only USB2 ports extended protocol capability values are cached. | |
4217 | * Return 1 if capability is supported | |
4218 | */ | |
4219 | static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port, | |
4220 | unsigned capability) | |
4221 | { | |
4222 | u32 port_offset, port_count; | |
4223 | int i; | |
4224 | ||
4225 | for (i = 0; i < xhci->num_ext_caps; i++) { | |
4226 | if (xhci->ext_caps[i] & capability) { | |
4227 | /* port offsets starts at 1 */ | |
4228 | port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1; | |
4229 | port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]); | |
4230 | if (port >= port_offset && | |
4231 | port < port_offset + port_count) | |
4232 | return 1; | |
4233 | } | |
4234 | } | |
4235 | return 0; | |
4236 | } | |
4237 | ||
3969384c | 4238 | static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
b01bcbf7 SS |
4239 | { |
4240 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
b630d4b9 | 4241 | int portnum = udev->portnum - 1; |
b01bcbf7 | 4242 | |
b50107bb | 4243 | if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support || |
de68bab4 SS |
4244 | !udev->lpm_capable) |
4245 | return 0; | |
4246 | ||
4247 | /* we only support lpm for non-hub device connected to root hub yet */ | |
4248 | if (!udev->parent || udev->parent->parent || | |
4249 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4250 | return 0; | |
4251 | ||
4252 | if (xhci->hw_lpm_support == 1 && | |
4253 | xhci_check_usb2_port_capability( | |
4254 | xhci, portnum, XHCI_HLC)) { | |
4255 | udev->usb2_hw_lpm_capable = 1; | |
4256 | udev->l1_params.timeout = XHCI_L1_TIMEOUT; | |
4257 | udev->l1_params.besl = XHCI_DEFAULT_BESL; | |
4258 | if (xhci_check_usb2_port_capability(xhci, portnum, | |
4259 | XHCI_BLC)) | |
4260 | udev->usb2_hw_lpm_besl_capable = 1; | |
b01bcbf7 SS |
4261 | } |
4262 | ||
4263 | return 0; | |
4264 | } | |
4265 | ||
3b3db026 SS |
4266 | /*---------------------- USB 3.0 Link PM functions ------------------------*/ |
4267 | ||
e3567d2c SS |
4268 | /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */ |
4269 | static unsigned long long xhci_service_interval_to_ns( | |
4270 | struct usb_endpoint_descriptor *desc) | |
4271 | { | |
16b45fdf | 4272 | return (1ULL << (desc->bInterval - 1)) * 125 * 1000; |
e3567d2c SS |
4273 | } |
4274 | ||
3b3db026 SS |
4275 | static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev, |
4276 | enum usb3_link_state state) | |
4277 | { | |
4278 | unsigned long long sel; | |
4279 | unsigned long long pel; | |
4280 | unsigned int max_sel_pel; | |
4281 | char *state_name; | |
4282 | ||
4283 | switch (state) { | |
4284 | case USB3_LPM_U1: | |
4285 | /* Convert SEL and PEL stored in nanoseconds to microseconds */ | |
4286 | sel = DIV_ROUND_UP(udev->u1_params.sel, 1000); | |
4287 | pel = DIV_ROUND_UP(udev->u1_params.pel, 1000); | |
4288 | max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL; | |
4289 | state_name = "U1"; | |
4290 | break; | |
4291 | case USB3_LPM_U2: | |
4292 | sel = DIV_ROUND_UP(udev->u2_params.sel, 1000); | |
4293 | pel = DIV_ROUND_UP(udev->u2_params.pel, 1000); | |
4294 | max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL; | |
4295 | state_name = "U2"; | |
4296 | break; | |
4297 | default: | |
4298 | dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n", | |
4299 | __func__); | |
e25e62ae | 4300 | return USB3_LPM_DISABLED; |
3b3db026 SS |
4301 | } |
4302 | ||
4303 | if (sel <= max_sel_pel && pel <= max_sel_pel) | |
4304 | return USB3_LPM_DEVICE_INITIATED; | |
4305 | ||
4306 | if (sel > max_sel_pel) | |
4307 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
4308 | "due to long SEL %llu ms\n", | |
4309 | state_name, sel); | |
4310 | else | |
4311 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
03e64e96 | 4312 | "due to long PEL %llu ms\n", |
3b3db026 SS |
4313 | state_name, pel); |
4314 | return USB3_LPM_DISABLED; | |
4315 | } | |
4316 | ||
9502c46c | 4317 | /* The U1 timeout should be the maximum of the following values: |
e3567d2c SS |
4318 | * - For control endpoints, U1 system exit latency (SEL) * 3 |
4319 | * - For bulk endpoints, U1 SEL * 5 | |
4320 | * - For interrupt endpoints: | |
4321 | * - Notification EPs, U1 SEL * 3 | |
4322 | * - Periodic EPs, max(105% of bInterval, U1 SEL * 2) | |
4323 | * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2) | |
4324 | */ | |
9502c46c PA |
4325 | static unsigned long long xhci_calculate_intel_u1_timeout( |
4326 | struct usb_device *udev, | |
e3567d2c SS |
4327 | struct usb_endpoint_descriptor *desc) |
4328 | { | |
4329 | unsigned long long timeout_ns; | |
4330 | int ep_type; | |
4331 | int intr_type; | |
4332 | ||
4333 | ep_type = usb_endpoint_type(desc); | |
4334 | switch (ep_type) { | |
4335 | case USB_ENDPOINT_XFER_CONTROL: | |
4336 | timeout_ns = udev->u1_params.sel * 3; | |
4337 | break; | |
4338 | case USB_ENDPOINT_XFER_BULK: | |
4339 | timeout_ns = udev->u1_params.sel * 5; | |
4340 | break; | |
4341 | case USB_ENDPOINT_XFER_INT: | |
4342 | intr_type = usb_endpoint_interrupt_type(desc); | |
4343 | if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) { | |
4344 | timeout_ns = udev->u1_params.sel * 3; | |
4345 | break; | |
4346 | } | |
4347 | /* Otherwise the calculation is the same as isoc eps */ | |
7d864999 | 4348 | /* fall through */ |
e3567d2c SS |
4349 | case USB_ENDPOINT_XFER_ISOC: |
4350 | timeout_ns = xhci_service_interval_to_ns(desc); | |
c88db160 | 4351 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100); |
e3567d2c SS |
4352 | if (timeout_ns < udev->u1_params.sel * 2) |
4353 | timeout_ns = udev->u1_params.sel * 2; | |
4354 | break; | |
4355 | default: | |
4356 | return 0; | |
4357 | } | |
4358 | ||
9502c46c PA |
4359 | return timeout_ns; |
4360 | } | |
4361 | ||
4362 | /* Returns the hub-encoded U1 timeout value. */ | |
4363 | static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci, | |
4364 | struct usb_device *udev, | |
4365 | struct usb_endpoint_descriptor *desc) | |
4366 | { | |
4367 | unsigned long long timeout_ns; | |
4368 | ||
4369 | if (xhci->quirks & XHCI_INTEL_HOST) | |
4370 | timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc); | |
4371 | else | |
4372 | timeout_ns = udev->u1_params.sel; | |
4373 | ||
4374 | /* The U1 timeout is encoded in 1us intervals. | |
4375 | * Don't return a timeout of zero, because that's USB3_LPM_DISABLED. | |
4376 | */ | |
e3567d2c | 4377 | if (timeout_ns == USB3_LPM_DISABLED) |
9502c46c PA |
4378 | timeout_ns = 1; |
4379 | else | |
4380 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000); | |
e3567d2c SS |
4381 | |
4382 | /* If the necessary timeout value is bigger than what we can set in the | |
4383 | * USB 3.0 hub, we have to disable hub-initiated U1. | |
4384 | */ | |
4385 | if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT) | |
4386 | return timeout_ns; | |
4387 | dev_dbg(&udev->dev, "Hub-initiated U1 disabled " | |
4388 | "due to long timeout %llu ms\n", timeout_ns); | |
4389 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1); | |
4390 | } | |
4391 | ||
9502c46c | 4392 | /* The U2 timeout should be the maximum of: |
e3567d2c SS |
4393 | * - 10 ms (to avoid the bandwidth impact on the scheduler) |
4394 | * - largest bInterval of any active periodic endpoint (to avoid going | |
4395 | * into lower power link states between intervals). | |
4396 | * - the U2 Exit Latency of the device | |
4397 | */ | |
9502c46c PA |
4398 | static unsigned long long xhci_calculate_intel_u2_timeout( |
4399 | struct usb_device *udev, | |
e3567d2c SS |
4400 | struct usb_endpoint_descriptor *desc) |
4401 | { | |
4402 | unsigned long long timeout_ns; | |
4403 | unsigned long long u2_del_ns; | |
4404 | ||
4405 | timeout_ns = 10 * 1000 * 1000; | |
4406 | ||
4407 | if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) && | |
4408 | (xhci_service_interval_to_ns(desc) > timeout_ns)) | |
4409 | timeout_ns = xhci_service_interval_to_ns(desc); | |
4410 | ||
966e7a85 | 4411 | u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL; |
e3567d2c SS |
4412 | if (u2_del_ns > timeout_ns) |
4413 | timeout_ns = u2_del_ns; | |
4414 | ||
9502c46c PA |
4415 | return timeout_ns; |
4416 | } | |
4417 | ||
4418 | /* Returns the hub-encoded U2 timeout value. */ | |
4419 | static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci, | |
4420 | struct usb_device *udev, | |
4421 | struct usb_endpoint_descriptor *desc) | |
4422 | { | |
4423 | unsigned long long timeout_ns; | |
4424 | ||
4425 | if (xhci->quirks & XHCI_INTEL_HOST) | |
4426 | timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc); | |
4427 | else | |
4428 | timeout_ns = udev->u2_params.sel; | |
4429 | ||
e3567d2c | 4430 | /* The U2 timeout is encoded in 256us intervals */ |
c88db160 | 4431 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000); |
e3567d2c SS |
4432 | /* If the necessary timeout value is bigger than what we can set in the |
4433 | * USB 3.0 hub, we have to disable hub-initiated U2. | |
4434 | */ | |
4435 | if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT) | |
4436 | return timeout_ns; | |
4437 | dev_dbg(&udev->dev, "Hub-initiated U2 disabled " | |
4438 | "due to long timeout %llu ms\n", timeout_ns); | |
4439 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2); | |
4440 | } | |
4441 | ||
3b3db026 SS |
4442 | static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci, |
4443 | struct usb_device *udev, | |
4444 | struct usb_endpoint_descriptor *desc, | |
4445 | enum usb3_link_state state, | |
4446 | u16 *timeout) | |
4447 | { | |
9502c46c PA |
4448 | if (state == USB3_LPM_U1) |
4449 | return xhci_calculate_u1_timeout(xhci, udev, desc); | |
4450 | else if (state == USB3_LPM_U2) | |
4451 | return xhci_calculate_u2_timeout(xhci, udev, desc); | |
e3567d2c | 4452 | |
3b3db026 SS |
4453 | return USB3_LPM_DISABLED; |
4454 | } | |
4455 | ||
4456 | static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci, | |
4457 | struct usb_device *udev, | |
4458 | struct usb_endpoint_descriptor *desc, | |
4459 | enum usb3_link_state state, | |
4460 | u16 *timeout) | |
4461 | { | |
4462 | u16 alt_timeout; | |
4463 | ||
4464 | alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev, | |
4465 | desc, state, timeout); | |
4466 | ||
4467 | /* If we found we can't enable hub-initiated LPM, or | |
4468 | * the U1 or U2 exit latency was too high to allow | |
4469 | * device-initiated LPM as well, just stop searching. | |
4470 | */ | |
4471 | if (alt_timeout == USB3_LPM_DISABLED || | |
4472 | alt_timeout == USB3_LPM_DEVICE_INITIATED) { | |
4473 | *timeout = alt_timeout; | |
4474 | return -E2BIG; | |
4475 | } | |
4476 | if (alt_timeout > *timeout) | |
4477 | *timeout = alt_timeout; | |
4478 | return 0; | |
4479 | } | |
4480 | ||
4481 | static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci, | |
4482 | struct usb_device *udev, | |
4483 | struct usb_host_interface *alt, | |
4484 | enum usb3_link_state state, | |
4485 | u16 *timeout) | |
4486 | { | |
4487 | int j; | |
4488 | ||
4489 | for (j = 0; j < alt->desc.bNumEndpoints; j++) { | |
4490 | if (xhci_update_timeout_for_endpoint(xhci, udev, | |
4491 | &alt->endpoint[j].desc, state, timeout)) | |
4492 | return -E2BIG; | |
4493 | continue; | |
4494 | } | |
4495 | return 0; | |
4496 | } | |
4497 | ||
e3567d2c SS |
4498 | static int xhci_check_intel_tier_policy(struct usb_device *udev, |
4499 | enum usb3_link_state state) | |
4500 | { | |
4501 | struct usb_device *parent; | |
4502 | unsigned int num_hubs; | |
4503 | ||
4504 | if (state == USB3_LPM_U2) | |
4505 | return 0; | |
4506 | ||
4507 | /* Don't enable U1 if the device is on a 2nd tier hub or lower. */ | |
4508 | for (parent = udev->parent, num_hubs = 0; parent->parent; | |
4509 | parent = parent->parent) | |
4510 | num_hubs++; | |
4511 | ||
4512 | if (num_hubs < 2) | |
4513 | return 0; | |
4514 | ||
4515 | dev_dbg(&udev->dev, "Disabling U1 link state for device" | |
4516 | " below second-tier hub.\n"); | |
4517 | dev_dbg(&udev->dev, "Plug device into first-tier hub " | |
4518 | "to decrease power consumption.\n"); | |
4519 | return -E2BIG; | |
4520 | } | |
4521 | ||
3b3db026 SS |
4522 | static int xhci_check_tier_policy(struct xhci_hcd *xhci, |
4523 | struct usb_device *udev, | |
4524 | enum usb3_link_state state) | |
4525 | { | |
e3567d2c SS |
4526 | if (xhci->quirks & XHCI_INTEL_HOST) |
4527 | return xhci_check_intel_tier_policy(udev, state); | |
9502c46c PA |
4528 | else |
4529 | return 0; | |
3b3db026 SS |
4530 | } |
4531 | ||
4532 | /* Returns the U1 or U2 timeout that should be enabled. | |
4533 | * If the tier check or timeout setting functions return with a non-zero exit | |
4534 | * code, that means the timeout value has been finalized and we shouldn't look | |
4535 | * at any more endpoints. | |
4536 | */ | |
4537 | static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd, | |
4538 | struct usb_device *udev, enum usb3_link_state state) | |
4539 | { | |
4540 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4541 | struct usb_host_config *config; | |
4542 | char *state_name; | |
4543 | int i; | |
4544 | u16 timeout = USB3_LPM_DISABLED; | |
4545 | ||
4546 | if (state == USB3_LPM_U1) | |
4547 | state_name = "U1"; | |
4548 | else if (state == USB3_LPM_U2) | |
4549 | state_name = "U2"; | |
4550 | else { | |
4551 | dev_warn(&udev->dev, "Can't enable unknown link state %i\n", | |
4552 | state); | |
4553 | return timeout; | |
4554 | } | |
4555 | ||
4556 | if (xhci_check_tier_policy(xhci, udev, state) < 0) | |
4557 | return timeout; | |
4558 | ||
4559 | /* Gather some information about the currently installed configuration | |
4560 | * and alternate interface settings. | |
4561 | */ | |
4562 | if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc, | |
4563 | state, &timeout)) | |
4564 | return timeout; | |
4565 | ||
4566 | config = udev->actconfig; | |
4567 | if (!config) | |
4568 | return timeout; | |
4569 | ||
64ba419b | 4570 | for (i = 0; i < config->desc.bNumInterfaces; i++) { |
3b3db026 SS |
4571 | struct usb_driver *driver; |
4572 | struct usb_interface *intf = config->interface[i]; | |
4573 | ||
4574 | if (!intf) | |
4575 | continue; | |
4576 | ||
4577 | /* Check if any currently bound drivers want hub-initiated LPM | |
4578 | * disabled. | |
4579 | */ | |
4580 | if (intf->dev.driver) { | |
4581 | driver = to_usb_driver(intf->dev.driver); | |
4582 | if (driver && driver->disable_hub_initiated_lpm) { | |
4583 | dev_dbg(&udev->dev, "Hub-initiated %s disabled " | |
4584 | "at request of driver %s\n", | |
4585 | state_name, driver->name); | |
4586 | return xhci_get_timeout_no_hub_lpm(udev, state); | |
4587 | } | |
4588 | } | |
4589 | ||
4590 | /* Not sure how this could happen... */ | |
4591 | if (!intf->cur_altsetting) | |
4592 | continue; | |
4593 | ||
4594 | if (xhci_update_timeout_for_interface(xhci, udev, | |
4595 | intf->cur_altsetting, | |
4596 | state, &timeout)) | |
4597 | return timeout; | |
4598 | } | |
4599 | return timeout; | |
4600 | } | |
4601 | ||
3b3db026 SS |
4602 | static int calculate_max_exit_latency(struct usb_device *udev, |
4603 | enum usb3_link_state state_changed, | |
4604 | u16 hub_encoded_timeout) | |
4605 | { | |
4606 | unsigned long long u1_mel_us = 0; | |
4607 | unsigned long long u2_mel_us = 0; | |
4608 | unsigned long long mel_us = 0; | |
4609 | bool disabling_u1; | |
4610 | bool disabling_u2; | |
4611 | bool enabling_u1; | |
4612 | bool enabling_u2; | |
4613 | ||
4614 | disabling_u1 = (state_changed == USB3_LPM_U1 && | |
4615 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4616 | disabling_u2 = (state_changed == USB3_LPM_U2 && | |
4617 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4618 | ||
4619 | enabling_u1 = (state_changed == USB3_LPM_U1 && | |
4620 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4621 | enabling_u2 = (state_changed == USB3_LPM_U2 && | |
4622 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4623 | ||
4624 | /* If U1 was already enabled and we're not disabling it, | |
4625 | * or we're going to enable U1, account for the U1 max exit latency. | |
4626 | */ | |
4627 | if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) || | |
4628 | enabling_u1) | |
4629 | u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000); | |
4630 | if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) || | |
4631 | enabling_u2) | |
4632 | u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000); | |
4633 | ||
4634 | if (u1_mel_us > u2_mel_us) | |
4635 | mel_us = u1_mel_us; | |
4636 | else | |
4637 | mel_us = u2_mel_us; | |
4638 | /* xHCI host controller max exit latency field is only 16 bits wide. */ | |
4639 | if (mel_us > MAX_EXIT) { | |
4640 | dev_warn(&udev->dev, "Link PM max exit latency of %lluus " | |
4641 | "is too big.\n", mel_us); | |
4642 | return -E2BIG; | |
4643 | } | |
4644 | return mel_us; | |
4645 | } | |
4646 | ||
4647 | /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */ | |
3969384c | 4648 | static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, |
3b3db026 SS |
4649 | struct usb_device *udev, enum usb3_link_state state) |
4650 | { | |
4651 | struct xhci_hcd *xhci; | |
4652 | u16 hub_encoded_timeout; | |
4653 | int mel; | |
4654 | int ret; | |
4655 | ||
4656 | xhci = hcd_to_xhci(hcd); | |
4657 | /* The LPM timeout values are pretty host-controller specific, so don't | |
4658 | * enable hub-initiated timeouts unless the vendor has provided | |
4659 | * information about their timeout algorithm. | |
4660 | */ | |
4661 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4662 | !xhci->devs[udev->slot_id]) | |
4663 | return USB3_LPM_DISABLED; | |
4664 | ||
4665 | hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state); | |
4666 | mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout); | |
4667 | if (mel < 0) { | |
4668 | /* Max Exit Latency is too big, disable LPM. */ | |
4669 | hub_encoded_timeout = USB3_LPM_DISABLED; | |
4670 | mel = 0; | |
4671 | } | |
4672 | ||
4673 | ret = xhci_change_max_exit_latency(xhci, udev, mel); | |
4674 | if (ret) | |
4675 | return ret; | |
4676 | return hub_encoded_timeout; | |
4677 | } | |
4678 | ||
3969384c | 4679 | static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, |
3b3db026 SS |
4680 | struct usb_device *udev, enum usb3_link_state state) |
4681 | { | |
4682 | struct xhci_hcd *xhci; | |
4683 | u16 mel; | |
3b3db026 SS |
4684 | |
4685 | xhci = hcd_to_xhci(hcd); | |
4686 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4687 | !xhci->devs[udev->slot_id]) | |
4688 | return 0; | |
4689 | ||
4690 | mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED); | |
f1cda54c | 4691 | return xhci_change_max_exit_latency(xhci, udev, mel); |
3b3db026 | 4692 | } |
b01bcbf7 | 4693 | #else /* CONFIG_PM */ |
9574323c | 4694 | |
3969384c | 4695 | static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, |
ceb6c9c8 RW |
4696 | struct usb_device *udev, int enable) |
4697 | { | |
4698 | return 0; | |
4699 | } | |
4700 | ||
3969384c | 4701 | static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
ceb6c9c8 RW |
4702 | { |
4703 | return 0; | |
4704 | } | |
4705 | ||
3969384c | 4706 | static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, |
b01bcbf7 | 4707 | struct usb_device *udev, enum usb3_link_state state) |
65580b43 | 4708 | { |
b01bcbf7 | 4709 | return USB3_LPM_DISABLED; |
65580b43 AX |
4710 | } |
4711 | ||
3969384c | 4712 | static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, |
b01bcbf7 | 4713 | struct usb_device *udev, enum usb3_link_state state) |
9574323c AX |
4714 | { |
4715 | return 0; | |
4716 | } | |
b01bcbf7 | 4717 | #endif /* CONFIG_PM */ |
9574323c | 4718 | |
b01bcbf7 | 4719 | /*-------------------------------------------------------------------------*/ |
9574323c | 4720 | |
ac1c1b7f SS |
4721 | /* Once a hub descriptor is fetched for a device, we need to update the xHC's |
4722 | * internal data structures for the device. | |
4723 | */ | |
3969384c | 4724 | static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, |
ac1c1b7f SS |
4725 | struct usb_tt *tt, gfp_t mem_flags) |
4726 | { | |
4727 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4728 | struct xhci_virt_device *vdev; | |
4729 | struct xhci_command *config_cmd; | |
4730 | struct xhci_input_control_ctx *ctrl_ctx; | |
4731 | struct xhci_slot_ctx *slot_ctx; | |
4732 | unsigned long flags; | |
4733 | unsigned think_time; | |
4734 | int ret; | |
4735 | ||
4736 | /* Ignore root hubs */ | |
4737 | if (!hdev->parent) | |
4738 | return 0; | |
4739 | ||
4740 | vdev = xhci->devs[hdev->slot_id]; | |
4741 | if (!vdev) { | |
4742 | xhci_warn(xhci, "Cannot update hub desc for unknown device.\n"); | |
4743 | return -EINVAL; | |
4744 | } | |
74e0b564 | 4745 | |
a1d78c16 | 4746 | config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); |
74e0b564 | 4747 | if (!config_cmd) |
ac1c1b7f | 4748 | return -ENOMEM; |
74e0b564 | 4749 | |
4daf9df5 | 4750 | ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx); |
92f8e767 SS |
4751 | if (!ctrl_ctx) { |
4752 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
4753 | __func__); | |
4754 | xhci_free_command(xhci, config_cmd); | |
4755 | return -ENOMEM; | |
4756 | } | |
ac1c1b7f SS |
4757 | |
4758 | spin_lock_irqsave(&xhci->lock, flags); | |
839c817c SS |
4759 | if (hdev->speed == USB_SPEED_HIGH && |
4760 | xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) { | |
4761 | xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n"); | |
4762 | xhci_free_command(xhci, config_cmd); | |
4763 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4764 | return -ENOMEM; | |
4765 | } | |
4766 | ||
ac1c1b7f | 4767 | xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx); |
28ccd296 | 4768 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
ac1c1b7f | 4769 | slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx); |
28ccd296 | 4770 | slot_ctx->dev_info |= cpu_to_le32(DEV_HUB); |
096b110a CY |
4771 | /* |
4772 | * refer to section 6.2.2: MTT should be 0 for full speed hub, | |
4773 | * but it may be already set to 1 when setup an xHCI virtual | |
4774 | * device, so clear it anyway. | |
4775 | */ | |
ac1c1b7f | 4776 | if (tt->multi) |
28ccd296 | 4777 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
096b110a CY |
4778 | else if (hdev->speed == USB_SPEED_FULL) |
4779 | slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT); | |
4780 | ||
ac1c1b7f SS |
4781 | if (xhci->hci_version > 0x95) { |
4782 | xhci_dbg(xhci, "xHCI version %x needs hub " | |
4783 | "TT think time and number of ports\n", | |
4784 | (unsigned int) xhci->hci_version); | |
28ccd296 | 4785 | slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild)); |
ac1c1b7f SS |
4786 | /* Set TT think time - convert from ns to FS bit times. |
4787 | * 0 = 8 FS bit times, 1 = 16 FS bit times, | |
4788 | * 2 = 24 FS bit times, 3 = 32 FS bit times. | |
700b4173 AX |
4789 | * |
4790 | * xHCI 1.0: this field shall be 0 if the device is not a | |
4791 | * High-spped hub. | |
ac1c1b7f SS |
4792 | */ |
4793 | think_time = tt->think_time; | |
4794 | if (think_time != 0) | |
4795 | think_time = (think_time / 666) - 1; | |
700b4173 AX |
4796 | if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH) |
4797 | slot_ctx->tt_info |= | |
4798 | cpu_to_le32(TT_THINK_TIME(think_time)); | |
ac1c1b7f SS |
4799 | } else { |
4800 | xhci_dbg(xhci, "xHCI version %x doesn't need hub " | |
4801 | "TT think time or number of ports\n", | |
4802 | (unsigned int) xhci->hci_version); | |
4803 | } | |
4804 | slot_ctx->dev_state = 0; | |
4805 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4806 | ||
4807 | xhci_dbg(xhci, "Set up %s for hub device.\n", | |
4808 | (xhci->hci_version > 0x95) ? | |
4809 | "configure endpoint" : "evaluate context"); | |
ac1c1b7f SS |
4810 | |
4811 | /* Issue and wait for the configure endpoint or | |
4812 | * evaluate context command. | |
4813 | */ | |
4814 | if (xhci->hci_version > 0x95) | |
4815 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
4816 | false, false); | |
4817 | else | |
4818 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
4819 | true, false); | |
4820 | ||
ac1c1b7f SS |
4821 | xhci_free_command(xhci, config_cmd); |
4822 | return ret; | |
4823 | } | |
4824 | ||
3969384c | 4825 | static int xhci_get_frame(struct usb_hcd *hcd) |
66d4eadd SS |
4826 | { |
4827 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4828 | /* EHCI mods by the periodic size. Why? */ | |
b0ba9720 | 4829 | return readl(&xhci->run_regs->microframe_index) >> 3; |
66d4eadd SS |
4830 | } |
4831 | ||
552e0c4f SAS |
4832 | int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) |
4833 | { | |
4834 | struct xhci_hcd *xhci; | |
4c39d4b9 AB |
4835 | /* |
4836 | * TODO: Check with DWC3 clients for sysdev according to | |
4837 | * quirks | |
4838 | */ | |
4839 | struct device *dev = hcd->self.sysdev; | |
c279f4b1 | 4840 | unsigned int minor_rev; |
552e0c4f | 4841 | int retval; |
552e0c4f | 4842 | |
1386ff75 SS |
4843 | /* Accept arbitrarily long scatter-gather lists */ |
4844 | hcd->self.sg_tablesize = ~0; | |
fc76051c | 4845 | |
e2ed5114 MN |
4846 | /* support to build packet from discontinuous buffers */ |
4847 | hcd->self.no_sg_constraint = 1; | |
4848 | ||
19181bc5 HG |
4849 | /* XHCI controllers don't stop the ep queue on short packets :| */ |
4850 | hcd->self.no_stop_on_short = 1; | |
552e0c4f | 4851 | |
b50107bb MN |
4852 | xhci = hcd_to_xhci(hcd); |
4853 | ||
552e0c4f | 4854 | if (usb_hcd_is_primary_hcd(hcd)) { |
552e0c4f SAS |
4855 | xhci->main_hcd = hcd; |
4856 | /* Mark the first roothub as being USB 2.0. | |
4857 | * The xHCI driver will register the USB 3.0 roothub. | |
4858 | */ | |
4859 | hcd->speed = HCD_USB2; | |
4860 | hcd->self.root_hub->speed = USB_SPEED_HIGH; | |
4861 | /* | |
4862 | * USB 2.0 roothub under xHCI has an integrated TT, | |
4863 | * (rate matching hub) as opposed to having an OHCI/UHCI | |
4864 | * companion controller. | |
4865 | */ | |
4866 | hcd->has_tt = 1; | |
4867 | } else { | |
c279f4b1 MN |
4868 | /* |
4869 | * Some 3.1 hosts return sbrn 0x30, use xhci supported protocol | |
4870 | * minor revision instead of sbrn | |
4871 | */ | |
4872 | minor_rev = xhci->usb3_rhub.min_rev; | |
4873 | if (minor_rev) { | |
b50107bb | 4874 | hcd->speed = HCD_USB31; |
2c0e06f8 | 4875 | hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS; |
b50107bb | 4876 | } |
c279f4b1 MN |
4877 | xhci_info(xhci, "Host supports USB 3.%x %s SuperSpeed\n", |
4878 | minor_rev, | |
4879 | minor_rev ? "Enhanced" : ""); | |
4880 | ||
552e0c4f SAS |
4881 | /* xHCI private pointer was set in xhci_pci_probe for the second |
4882 | * registered roothub. | |
4883 | */ | |
552e0c4f SAS |
4884 | return 0; |
4885 | } | |
4886 | ||
a00918d0 | 4887 | mutex_init(&xhci->mutex); |
552e0c4f SAS |
4888 | xhci->cap_regs = hcd->regs; |
4889 | xhci->op_regs = hcd->regs + | |
b0ba9720 | 4890 | HC_LENGTH(readl(&xhci->cap_regs->hc_capbase)); |
552e0c4f | 4891 | xhci->run_regs = hcd->regs + |
b0ba9720 | 4892 | (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK); |
552e0c4f | 4893 | /* Cache read-only capability registers */ |
b0ba9720 XR |
4894 | xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1); |
4895 | xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2); | |
4896 | xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3); | |
4897 | xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase); | |
552e0c4f | 4898 | xhci->hci_version = HC_VERSION(xhci->hcc_params); |
b0ba9720 | 4899 | xhci->hcc_params = readl(&xhci->cap_regs->hcc_params); |
04abb6de LB |
4900 | if (xhci->hci_version > 0x100) |
4901 | xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2); | |
552e0c4f SAS |
4902 | xhci_print_registers(xhci); |
4903 | ||
757de492 | 4904 | xhci->quirks |= quirks; |
4e6a1ee7 | 4905 | |
552e0c4f SAS |
4906 | get_quirks(dev, xhci); |
4907 | ||
07f3cb7c GC |
4908 | /* In xhci controllers which follow xhci 1.0 spec gives a spurious |
4909 | * success event after a short transfer. This quirk will ignore such | |
4910 | * spurious event. | |
4911 | */ | |
4912 | if (xhci->hci_version > 0x96) | |
4913 | xhci->quirks |= XHCI_SPURIOUS_SUCCESS; | |
4914 | ||
552e0c4f SAS |
4915 | /* Make sure the HC is halted. */ |
4916 | retval = xhci_halt(xhci); | |
4917 | if (retval) | |
cd33a321 | 4918 | return retval; |
552e0c4f SAS |
4919 | |
4920 | xhci_dbg(xhci, "Resetting HCD\n"); | |
4921 | /* Reset the internal HC memory state and registers. */ | |
4922 | retval = xhci_reset(xhci); | |
4923 | if (retval) | |
cd33a321 | 4924 | return retval; |
552e0c4f SAS |
4925 | xhci_dbg(xhci, "Reset complete\n"); |
4926 | ||
0a380be8 YS |
4927 | /* |
4928 | * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0) | |
4929 | * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit | |
4930 | * address memory pointers actually. So, this driver clears the AC64 | |
4931 | * bit of xhci->hcc_params to call dma_set_coherent_mask(dev, | |
4932 | * DMA_BIT_MASK(32)) in this xhci_gen_setup(). | |
4933 | */ | |
4934 | if (xhci->quirks & XHCI_NO_64BIT_SUPPORT) | |
4935 | xhci->hcc_params &= ~BIT(0); | |
4936 | ||
c10cf118 XR |
4937 | /* Set dma_mask and coherent_dma_mask to 64-bits, |
4938 | * if xHC supports 64-bit addressing */ | |
4939 | if (HCC_64BIT_ADDR(xhci->hcc_params) && | |
4940 | !dma_set_mask(dev, DMA_BIT_MASK(64))) { | |
552e0c4f | 4941 | xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n"); |
c10cf118 | 4942 | dma_set_coherent_mask(dev, DMA_BIT_MASK(64)); |
fda182d8 DD |
4943 | } else { |
4944 | /* | |
4945 | * This is to avoid error in cases where a 32-bit USB | |
4946 | * controller is used on a 64-bit capable system. | |
4947 | */ | |
4948 | retval = dma_set_mask(dev, DMA_BIT_MASK(32)); | |
4949 | if (retval) | |
4950 | return retval; | |
4951 | xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n"); | |
4952 | dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); | |
552e0c4f SAS |
4953 | } |
4954 | ||
4955 | xhci_dbg(xhci, "Calling HCD init\n"); | |
4956 | /* Initialize HCD and host controller data structures. */ | |
4957 | retval = xhci_init(hcd); | |
4958 | if (retval) | |
cd33a321 | 4959 | return retval; |
552e0c4f | 4960 | xhci_dbg(xhci, "Called HCD init\n"); |
99705092 | 4961 | |
45d29576 | 4962 | xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n", |
99705092 HG |
4963 | xhci->hcc_params, xhci->hci_version, xhci->quirks); |
4964 | ||
552e0c4f | 4965 | return 0; |
552e0c4f | 4966 | } |
436e8c7d | 4967 | EXPORT_SYMBOL_GPL(xhci_gen_setup); |
552e0c4f | 4968 | |
1885d9a3 AB |
4969 | static const struct hc_driver xhci_hc_driver = { |
4970 | .description = "xhci-hcd", | |
4971 | .product_desc = "xHCI Host Controller", | |
32479d4b | 4972 | .hcd_priv_size = sizeof(struct xhci_hcd), |
1885d9a3 AB |
4973 | |
4974 | /* | |
4975 | * generic hardware linkage | |
4976 | */ | |
4977 | .irq = xhci_irq, | |
4978 | .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, | |
4979 | ||
4980 | /* | |
4981 | * basic lifecycle operations | |
4982 | */ | |
4983 | .reset = NULL, /* set in xhci_init_driver() */ | |
4984 | .start = xhci_run, | |
4985 | .stop = xhci_stop, | |
4986 | .shutdown = xhci_shutdown, | |
4987 | ||
4988 | /* | |
4989 | * managing i/o requests and associated device resources | |
4990 | */ | |
4991 | .urb_enqueue = xhci_urb_enqueue, | |
4992 | .urb_dequeue = xhci_urb_dequeue, | |
4993 | .alloc_dev = xhci_alloc_dev, | |
4994 | .free_dev = xhci_free_dev, | |
4995 | .alloc_streams = xhci_alloc_streams, | |
4996 | .free_streams = xhci_free_streams, | |
4997 | .add_endpoint = xhci_add_endpoint, | |
4998 | .drop_endpoint = xhci_drop_endpoint, | |
4999 | .endpoint_reset = xhci_endpoint_reset, | |
5000 | .check_bandwidth = xhci_check_bandwidth, | |
5001 | .reset_bandwidth = xhci_reset_bandwidth, | |
5002 | .address_device = xhci_address_device, | |
5003 | .enable_device = xhci_enable_device, | |
5004 | .update_hub_device = xhci_update_hub_device, | |
5005 | .reset_device = xhci_discover_or_reset_device, | |
5006 | ||
5007 | /* | |
5008 | * scheduling support | |
5009 | */ | |
5010 | .get_frame_number = xhci_get_frame, | |
5011 | ||
5012 | /* | |
5013 | * root hub support | |
5014 | */ | |
5015 | .hub_control = xhci_hub_control, | |
5016 | .hub_status_data = xhci_hub_status_data, | |
5017 | .bus_suspend = xhci_bus_suspend, | |
5018 | .bus_resume = xhci_bus_resume, | |
5019 | ||
5020 | /* | |
5021 | * call back when device connected and addressed | |
5022 | */ | |
5023 | .update_device = xhci_update_device, | |
5024 | .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, | |
5025 | .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, | |
5026 | .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, | |
5027 | .find_raw_port_number = xhci_find_raw_port_number, | |
5028 | }; | |
5029 | ||
cd33a321 RQ |
5030 | void xhci_init_driver(struct hc_driver *drv, |
5031 | const struct xhci_driver_overrides *over) | |
1885d9a3 | 5032 | { |
cd33a321 RQ |
5033 | BUG_ON(!over); |
5034 | ||
5035 | /* Copy the generic table to drv then apply the overrides */ | |
1885d9a3 | 5036 | *drv = xhci_hc_driver; |
cd33a321 RQ |
5037 | |
5038 | if (over) { | |
5039 | drv->hcd_priv_size += over->extra_priv_size; | |
5040 | if (over->reset) | |
5041 | drv->reset = over->reset; | |
5042 | if (over->start) | |
5043 | drv->start = over->start; | |
5044 | } | |
1885d9a3 AB |
5045 | } |
5046 | EXPORT_SYMBOL_GPL(xhci_init_driver); | |
5047 | ||
66d4eadd SS |
5048 | MODULE_DESCRIPTION(DRIVER_DESC); |
5049 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
5050 | MODULE_LICENSE("GPL"); | |
5051 | ||
5052 | static int __init xhci_hcd_init(void) | |
5053 | { | |
98441973 SS |
5054 | /* |
5055 | * Check the compiler generated sizes of structures that must be laid | |
5056 | * out in specific ways for hardware access. | |
5057 | */ | |
5058 | BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8); | |
5059 | BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8); | |
5060 | BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8); | |
5061 | /* xhci_device_control has eight fields, and also | |
5062 | * embeds one xhci_slot_ctx and 31 xhci_ep_ctx | |
5063 | */ | |
98441973 SS |
5064 | BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8); |
5065 | BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8); | |
5066 | BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8); | |
04abb6de | 5067 | BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8); |
98441973 SS |
5068 | BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8); |
5069 | /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */ | |
5070 | BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8); | |
1eaf35e4 ON |
5071 | |
5072 | if (usb_disabled()) | |
5073 | return -ENODEV; | |
5074 | ||
02b6fdc2 LB |
5075 | xhci_debugfs_create_root(); |
5076 | ||
66d4eadd SS |
5077 | return 0; |
5078 | } | |
b04c846c AD |
5079 | |
5080 | /* | |
5081 | * If an init function is provided, an exit function must also be provided | |
5082 | * to allow module unload. | |
5083 | */ | |
02b6fdc2 LB |
5084 | static void __exit xhci_hcd_fini(void) |
5085 | { | |
5086 | xhci_debugfs_remove_root(); | |
5087 | } | |
b04c846c | 5088 | |
66d4eadd | 5089 | module_init(xhci_hcd_init); |
b04c846c | 5090 | module_exit(xhci_hcd_fini); |