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Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
66d4eadd SS |
2 | /* |
3 | * xHCI host controller driver | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
66d4eadd SS |
9 | */ |
10 | ||
43b86af8 | 11 | #include <linux/pci.h> |
66d4eadd | 12 | #include <linux/irq.h> |
8df75f42 | 13 | #include <linux/log2.h> |
66d4eadd | 14 | #include <linux/module.h> |
b0567b3f | 15 | #include <linux/moduleparam.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
71c731a2 | 17 | #include <linux/dmi.h> |
008eb957 | 18 | #include <linux/dma-mapping.h> |
66d4eadd SS |
19 | |
20 | #include "xhci.h" | |
84a99f6f | 21 | #include "xhci-trace.h" |
0cbd4b34 | 22 | #include "xhci-mtk.h" |
02b6fdc2 | 23 | #include "xhci-debugfs.h" |
b6c33de0 | 24 | #include "xhci-dbgcap.h" |
66d4eadd SS |
25 | |
26 | #define DRIVER_AUTHOR "Sarah Sharp" | |
27 | #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver" | |
28 | ||
a1377e53 LB |
29 | #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) |
30 | ||
b0567b3f SS |
31 | /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */ |
32 | static int link_quirk; | |
33 | module_param(link_quirk, int, S_IRUGO | S_IWUSR); | |
34 | MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB"); | |
35 | ||
4e6a1ee7 TI |
36 | static unsigned int quirks; |
37 | module_param(quirks, uint, S_IRUGO); | |
38 | MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default"); | |
39 | ||
66d4eadd SS |
40 | /* TODO: copied from ehci-hcd.c - can this be refactored? */ |
41 | /* | |
2611bd18 | 42 | * xhci_handshake - spin reading hc until handshake completes or fails |
66d4eadd SS |
43 | * @ptr: address of hc register to be read |
44 | * @mask: bits to look at in result of read | |
45 | * @done: value of those bits when handshake succeeds | |
46 | * @usec: timeout in microseconds | |
47 | * | |
48 | * Returns negative errno, or zero on success | |
49 | * | |
50 | * Success happens when the "mask" bits have the specified value (hardware | |
51 | * handshake done). There are two failure modes: "usec" have passed (major | |
52 | * hardware flakeout), or the register reads as all-ones (hardware removed). | |
53 | */ | |
dc0b177c | 54 | int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec) |
66d4eadd SS |
55 | { |
56 | u32 result; | |
57 | ||
58 | do { | |
b0ba9720 | 59 | result = readl(ptr); |
66d4eadd SS |
60 | if (result == ~(u32)0) /* card removed */ |
61 | return -ENODEV; | |
62 | result &= mask; | |
63 | if (result == done) | |
64 | return 0; | |
65 | udelay(1); | |
66 | usec--; | |
67 | } while (usec > 0); | |
68 | return -ETIMEDOUT; | |
69 | } | |
70 | ||
71 | /* | |
4f0f0bae | 72 | * Disable interrupts and begin the xHCI halting process. |
66d4eadd | 73 | */ |
4f0f0bae | 74 | void xhci_quiesce(struct xhci_hcd *xhci) |
66d4eadd SS |
75 | { |
76 | u32 halted; | |
77 | u32 cmd; | |
78 | u32 mask; | |
79 | ||
66d4eadd | 80 | mask = ~(XHCI_IRQS); |
b0ba9720 | 81 | halted = readl(&xhci->op_regs->status) & STS_HALT; |
66d4eadd SS |
82 | if (!halted) |
83 | mask &= ~CMD_RUN; | |
84 | ||
b0ba9720 | 85 | cmd = readl(&xhci->op_regs->command); |
66d4eadd | 86 | cmd &= mask; |
204b7793 | 87 | writel(cmd, &xhci->op_regs->command); |
4f0f0bae SS |
88 | } |
89 | ||
90 | /* | |
91 | * Force HC into halt state. | |
92 | * | |
93 | * Disable any IRQs and clear the run/stop bit. | |
94 | * HC will complete any current and actively pipelined transactions, and | |
bdfca502 | 95 | * should halt within 16 ms of the run/stop bit being cleared. |
4f0f0bae | 96 | * Read HC Halted bit in the status register to see when the HC is finished. |
4f0f0bae SS |
97 | */ |
98 | int xhci_halt(struct xhci_hcd *xhci) | |
99 | { | |
c6cc27c7 | 100 | int ret; |
d195fcff | 101 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC"); |
4f0f0bae | 102 | xhci_quiesce(xhci); |
66d4eadd | 103 | |
dc0b177c | 104 | ret = xhci_handshake(&xhci->op_regs->status, |
66d4eadd | 105 | STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); |
99154fd3 MN |
106 | if (ret) { |
107 | xhci_warn(xhci, "Host halt failed, %d\n", ret); | |
108 | return ret; | |
109 | } | |
110 | xhci->xhc_state |= XHCI_STATE_HALTED; | |
111 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
c6cc27c7 | 112 | return ret; |
66d4eadd SS |
113 | } |
114 | ||
ed07453f SS |
115 | /* |
116 | * Set the run bit and wait for the host to be running. | |
117 | */ | |
26bba5c7 | 118 | int xhci_start(struct xhci_hcd *xhci) |
ed07453f SS |
119 | { |
120 | u32 temp; | |
121 | int ret; | |
122 | ||
b0ba9720 | 123 | temp = readl(&xhci->op_regs->command); |
ed07453f | 124 | temp |= (CMD_RUN); |
d195fcff | 125 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.", |
ed07453f | 126 | temp); |
204b7793 | 127 | writel(temp, &xhci->op_regs->command); |
ed07453f SS |
128 | |
129 | /* | |
130 | * Wait for the HCHalted Status bit to be 0 to indicate the host is | |
131 | * running. | |
132 | */ | |
dc0b177c | 133 | ret = xhci_handshake(&xhci->op_regs->status, |
ed07453f SS |
134 | STS_HALT, 0, XHCI_MAX_HALT_USEC); |
135 | if (ret == -ETIMEDOUT) | |
136 | xhci_err(xhci, "Host took too long to start, " | |
137 | "waited %u microseconds.\n", | |
138 | XHCI_MAX_HALT_USEC); | |
c6cc27c7 | 139 | if (!ret) |
98d74f9c MN |
140 | /* clear state flags. Including dying, halted or removing */ |
141 | xhci->xhc_state = 0; | |
e5bfeab0 | 142 | |
ed07453f SS |
143 | return ret; |
144 | } | |
145 | ||
66d4eadd | 146 | /* |
ac04e6ff | 147 | * Reset a halted HC. |
66d4eadd SS |
148 | * |
149 | * This resets pipelines, timers, counters, state machines, etc. | |
150 | * Transactions will be terminated immediately, and operational registers | |
151 | * will be set to their defaults. | |
152 | */ | |
153 | int xhci_reset(struct xhci_hcd *xhci) | |
154 | { | |
155 | u32 command; | |
156 | u32 state; | |
f370b996 | 157 | int ret, i; |
66d4eadd | 158 | |
b0ba9720 | 159 | state = readl(&xhci->op_regs->status); |
c11ae038 MN |
160 | |
161 | if (state == ~(u32)0) { | |
162 | xhci_warn(xhci, "Host not accessible, reset failed.\n"); | |
163 | return -ENODEV; | |
164 | } | |
165 | ||
d3512f63 SS |
166 | if ((state & STS_HALT) == 0) { |
167 | xhci_warn(xhci, "Host controller not halted, aborting reset.\n"); | |
168 | return 0; | |
169 | } | |
66d4eadd | 170 | |
d195fcff | 171 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC"); |
b0ba9720 | 172 | command = readl(&xhci->op_regs->command); |
66d4eadd | 173 | command |= CMD_RESET; |
204b7793 | 174 | writel(command, &xhci->op_regs->command); |
66d4eadd | 175 | |
a5964396 RM |
176 | /* Existing Intel xHCI controllers require a delay of 1 mS, |
177 | * after setting the CMD_RESET bit, and before accessing any | |
178 | * HC registers. This allows the HC to complete the | |
179 | * reset operation and be ready for HC register access. | |
180 | * Without this delay, the subsequent HC register access, | |
181 | * may result in a system hang very rarely. | |
182 | */ | |
183 | if (xhci->quirks & XHCI_INTEL_HOST) | |
184 | udelay(1000); | |
185 | ||
dc0b177c | 186 | ret = xhci_handshake(&xhci->op_regs->command, |
22ceac19 | 187 | CMD_RESET, 0, 10 * 1000 * 1000); |
2d62f3ee SS |
188 | if (ret) |
189 | return ret; | |
190 | ||
9da5a109 JC |
191 | if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL) |
192 | usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller)); | |
193 | ||
d195fcff XR |
194 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
195 | "Wait for controller to be ready for doorbell rings"); | |
2d62f3ee SS |
196 | /* |
197 | * xHCI cannot write to any doorbells or operational registers other | |
198 | * than status until the "Controller Not Ready" flag is cleared. | |
199 | */ | |
dc0b177c | 200 | ret = xhci_handshake(&xhci->op_regs->status, |
22ceac19 | 201 | STS_CNR, 0, 10 * 1000 * 1000); |
f370b996 | 202 | |
98871e94 | 203 | for (i = 0; i < 2; i++) { |
f370b996 AX |
204 | xhci->bus_state[i].port_c_suspend = 0; |
205 | xhci->bus_state[i].suspended_ports = 0; | |
206 | xhci->bus_state[i].resuming_ports = 0; | |
207 | } | |
208 | ||
209 | return ret; | |
66d4eadd SS |
210 | } |
211 | ||
43b86af8 | 212 | |
77d45b45 | 213 | #ifdef CONFIG_USB_PCI |
43b86af8 DN |
214 | /* |
215 | * Set up MSI | |
216 | */ | |
217 | static int xhci_setup_msi(struct xhci_hcd *xhci) | |
66d4eadd SS |
218 | { |
219 | int ret; | |
4c39d4b9 AB |
220 | /* |
221 | * TODO:Check with MSI Soc for sysdev | |
222 | */ | |
43b86af8 DN |
223 | struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); |
224 | ||
77d45b45 CH |
225 | ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); |
226 | if (ret < 0) { | |
d195fcff XR |
227 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
228 | "failed to allocate MSI entry"); | |
43b86af8 DN |
229 | return ret; |
230 | } | |
231 | ||
851ec164 | 232 | ret = request_irq(pdev->irq, xhci_msi_irq, |
43b86af8 DN |
233 | 0, "xhci_hcd", xhci_to_hcd(xhci)); |
234 | if (ret) { | |
d195fcff XR |
235 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
236 | "disable MSI interrupt"); | |
77d45b45 | 237 | pci_free_irq_vectors(pdev); |
43b86af8 DN |
238 | } |
239 | ||
240 | return ret; | |
241 | } | |
242 | ||
243 | /* | |
244 | * Set up MSI-X | |
245 | */ | |
246 | static int xhci_setup_msix(struct xhci_hcd *xhci) | |
247 | { | |
248 | int i, ret = 0; | |
0029227f AX |
249 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
250 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 251 | |
43b86af8 DN |
252 | /* |
253 | * calculate number of msi-x vectors supported. | |
254 | * - HCS_MAX_INTRS: the max number of interrupts the host can handle, | |
255 | * with max number of interrupters based on the xhci HCSPARAMS1. | |
256 | * - num_online_cpus: maximum msi-x vectors per CPUs core. | |
257 | * Add additional 1 vector to ensure always available interrupt. | |
258 | */ | |
259 | xhci->msix_count = min(num_online_cpus() + 1, | |
260 | HCS_MAX_INTRS(xhci->hcs_params1)); | |
261 | ||
77d45b45 CH |
262 | ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count, |
263 | PCI_IRQ_MSIX); | |
264 | if (ret < 0) { | |
d195fcff XR |
265 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
266 | "Failed to enable MSI-X"); | |
77d45b45 | 267 | return ret; |
66d4eadd SS |
268 | } |
269 | ||
43b86af8 | 270 | for (i = 0; i < xhci->msix_count; i++) { |
77d45b45 CH |
271 | ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0, |
272 | "xhci_hcd", xhci_to_hcd(xhci)); | |
43b86af8 DN |
273 | if (ret) |
274 | goto disable_msix; | |
66d4eadd | 275 | } |
43b86af8 | 276 | |
0029227f | 277 | hcd->msix_enabled = 1; |
43b86af8 | 278 | return ret; |
66d4eadd SS |
279 | |
280 | disable_msix: | |
d195fcff | 281 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt"); |
77d45b45 CH |
282 | while (--i >= 0) |
283 | free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); | |
284 | pci_free_irq_vectors(pdev); | |
66d4eadd SS |
285 | return ret; |
286 | } | |
287 | ||
66d4eadd SS |
288 | /* Free any IRQs and disable MSI-X */ |
289 | static void xhci_cleanup_msix(struct xhci_hcd *xhci) | |
290 | { | |
0029227f AX |
291 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
292 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
66d4eadd | 293 | |
9005355a JP |
294 | if (xhci->quirks & XHCI_PLAT) |
295 | return; | |
296 | ||
77d45b45 CH |
297 | /* return if using legacy interrupt */ |
298 | if (hcd->irq > 0) | |
299 | return; | |
300 | ||
301 | if (hcd->msix_enabled) { | |
302 | int i; | |
43b86af8 | 303 | |
77d45b45 CH |
304 | for (i = 0; i < xhci->msix_count; i++) |
305 | free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci)); | |
43b86af8 | 306 | } else { |
77d45b45 | 307 | free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci)); |
43b86af8 DN |
308 | } |
309 | ||
77d45b45 | 310 | pci_free_irq_vectors(pdev); |
0029227f | 311 | hcd->msix_enabled = 0; |
66d4eadd | 312 | } |
66d4eadd | 313 | |
d5c82feb | 314 | static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
421aa841 | 315 | { |
77d45b45 CH |
316 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
317 | ||
318 | if (hcd->msix_enabled) { | |
319 | struct pci_dev *pdev = to_pci_dev(hcd->self.controller); | |
320 | int i; | |
421aa841 | 321 | |
421aa841 | 322 | for (i = 0; i < xhci->msix_count; i++) |
77d45b45 | 323 | synchronize_irq(pci_irq_vector(pdev, i)); |
421aa841 SAS |
324 | } |
325 | } | |
326 | ||
327 | static int xhci_try_enable_msi(struct usb_hcd *hcd) | |
328 | { | |
329 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
52fb6125 | 330 | struct pci_dev *pdev; |
421aa841 SAS |
331 | int ret; |
332 | ||
52fb6125 SS |
333 | /* The xhci platform device has set up IRQs through usb_add_hcd. */ |
334 | if (xhci->quirks & XHCI_PLAT) | |
335 | return 0; | |
336 | ||
337 | pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller); | |
421aa841 SAS |
338 | /* |
339 | * Some Fresco Logic host controllers advertise MSI, but fail to | |
340 | * generate interrupts. Don't even try to enable MSI. | |
341 | */ | |
342 | if (xhci->quirks & XHCI_BROKEN_MSI) | |
00eed9c8 | 343 | goto legacy_irq; |
421aa841 SAS |
344 | |
345 | /* unregister the legacy interrupt */ | |
346 | if (hcd->irq) | |
347 | free_irq(hcd->irq, hcd); | |
cd70469d | 348 | hcd->irq = 0; |
421aa841 SAS |
349 | |
350 | ret = xhci_setup_msix(xhci); | |
351 | if (ret) | |
352 | /* fall back to msi*/ | |
353 | ret = xhci_setup_msi(xhci); | |
354 | ||
6a29beef PC |
355 | if (!ret) { |
356 | hcd->msi_enabled = 1; | |
421aa841 | 357 | return 0; |
6a29beef | 358 | } |
421aa841 | 359 | |
68d07f64 SS |
360 | if (!pdev->irq) { |
361 | xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n"); | |
362 | return -EINVAL; | |
363 | } | |
364 | ||
00eed9c8 | 365 | legacy_irq: |
79699437 AH |
366 | if (!strlen(hcd->irq_descr)) |
367 | snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d", | |
368 | hcd->driver->description, hcd->self.busnum); | |
369 | ||
421aa841 SAS |
370 | /* fall back to legacy interrupt*/ |
371 | ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED, | |
372 | hcd->irq_descr, hcd); | |
373 | if (ret) { | |
374 | xhci_err(xhci, "request interrupt %d failed\n", | |
375 | pdev->irq); | |
376 | return ret; | |
377 | } | |
378 | hcd->irq = pdev->irq; | |
379 | return 0; | |
380 | } | |
381 | ||
382 | #else | |
383 | ||
01bb59eb | 384 | static inline int xhci_try_enable_msi(struct usb_hcd *hcd) |
421aa841 SAS |
385 | { |
386 | return 0; | |
387 | } | |
388 | ||
01bb59eb | 389 | static inline void xhci_cleanup_msix(struct xhci_hcd *xhci) |
421aa841 SAS |
390 | { |
391 | } | |
392 | ||
01bb59eb | 393 | static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci) |
421aa841 SAS |
394 | { |
395 | } | |
396 | ||
397 | #endif | |
398 | ||
e99e88a9 | 399 | static void compliance_mode_recovery(struct timer_list *t) |
71c731a2 AC |
400 | { |
401 | struct xhci_hcd *xhci; | |
402 | struct usb_hcd *hcd; | |
403 | u32 temp; | |
404 | int i; | |
405 | ||
e99e88a9 | 406 | xhci = from_timer(xhci, t, comp_mode_recovery_timer); |
71c731a2 AC |
407 | |
408 | for (i = 0; i < xhci->num_usb3_ports; i++) { | |
b0ba9720 | 409 | temp = readl(xhci->usb3_ports[i]); |
71c731a2 AC |
410 | if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) { |
411 | /* | |
412 | * Compliance Mode Detected. Letting USB Core | |
413 | * handle the Warm Reset | |
414 | */ | |
4bdfe4c3 XR |
415 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
416 | "Compliance mode detected->port %d", | |
71c731a2 | 417 | i + 1); |
4bdfe4c3 XR |
418 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
419 | "Attempting compliance mode recovery"); | |
71c731a2 AC |
420 | hcd = xhci->shared_hcd; |
421 | ||
422 | if (hcd->state == HC_STATE_SUSPENDED) | |
423 | usb_hcd_resume_root_hub(hcd); | |
424 | ||
425 | usb_hcd_poll_rh_status(hcd); | |
426 | } | |
427 | } | |
428 | ||
429 | if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1)) | |
430 | mod_timer(&xhci->comp_mode_recovery_timer, | |
431 | jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS)); | |
432 | } | |
433 | ||
434 | /* | |
435 | * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver | |
436 | * that causes ports behind that hardware to enter compliance mode sometimes. | |
437 | * The quirk creates a timer that polls every 2 seconds the link state of | |
438 | * each host controller's port and recovers it by issuing a Warm reset | |
439 | * if Compliance mode is detected, otherwise the port will become "dead" (no | |
440 | * device connections or disconnections will be detected anymore). Becasue no | |
441 | * status event is generated when entering compliance mode (per xhci spec), | |
442 | * this quirk is needed on systems that have the failing hardware installed. | |
443 | */ | |
444 | static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci) | |
445 | { | |
446 | xhci->port_status_u0 = 0; | |
e99e88a9 KC |
447 | timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery, |
448 | 0); | |
71c731a2 AC |
449 | xhci->comp_mode_recovery_timer.expires = jiffies + |
450 | msecs_to_jiffies(COMP_MODE_RCVRY_MSECS); | |
451 | ||
71c731a2 | 452 | add_timer(&xhci->comp_mode_recovery_timer); |
4bdfe4c3 XR |
453 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
454 | "Compliance mode recovery timer initialized"); | |
71c731a2 AC |
455 | } |
456 | ||
457 | /* | |
458 | * This function identifies the systems that have installed the SN65LVPE502CP | |
459 | * USB3.0 re-driver and that need the Compliance Mode Quirk. | |
460 | * Systems: | |
461 | * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820 | |
462 | */ | |
e1cd9727 | 463 | static bool xhci_compliance_mode_recovery_timer_quirk_check(void) |
71c731a2 AC |
464 | { |
465 | const char *dmi_product_name, *dmi_sys_vendor; | |
466 | ||
467 | dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); | |
468 | dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR); | |
457a73d3 VG |
469 | if (!dmi_product_name || !dmi_sys_vendor) |
470 | return false; | |
71c731a2 AC |
471 | |
472 | if (!(strstr(dmi_sys_vendor, "Hewlett-Packard"))) | |
473 | return false; | |
474 | ||
475 | if (strstr(dmi_product_name, "Z420") || | |
476 | strstr(dmi_product_name, "Z620") || | |
47080974 | 477 | strstr(dmi_product_name, "Z820") || |
b0e4e606 | 478 | strstr(dmi_product_name, "Z1 Workstation")) |
71c731a2 AC |
479 | return true; |
480 | ||
481 | return false; | |
482 | } | |
483 | ||
484 | static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci) | |
485 | { | |
486 | return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1)); | |
487 | } | |
488 | ||
489 | ||
66d4eadd SS |
490 | /* |
491 | * Initialize memory for HCD and xHC (one-time init). | |
492 | * | |
493 | * Program the PAGESIZE register, initialize the device context array, create | |
494 | * device contexts (?), set up a command ring segment (or two?), create event | |
495 | * ring (one for now). | |
496 | */ | |
3969384c | 497 | static int xhci_init(struct usb_hcd *hcd) |
66d4eadd SS |
498 | { |
499 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
500 | int retval = 0; | |
501 | ||
d195fcff | 502 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init"); |
66d4eadd | 503 | spin_lock_init(&xhci->lock); |
d7826599 | 504 | if (xhci->hci_version == 0x95 && link_quirk) { |
4bdfe4c3 XR |
505 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
506 | "QUIRK: Not clearing Link TRB chain bits."); | |
b0567b3f SS |
507 | xhci->quirks |= XHCI_LINK_TRB_QUIRK; |
508 | } else { | |
d195fcff XR |
509 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
510 | "xHCI doesn't need link TRB QUIRK"); | |
b0567b3f | 511 | } |
66d4eadd | 512 | retval = xhci_mem_init(xhci, GFP_KERNEL); |
d195fcff | 513 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init"); |
66d4eadd | 514 | |
71c731a2 | 515 | /* Initializing Compliance Mode Recovery Data If Needed */ |
c3897aa5 | 516 | if (xhci_compliance_mode_recovery_timer_quirk_check()) { |
71c731a2 AC |
517 | xhci->quirks |= XHCI_COMP_MODE_QUIRK; |
518 | compliance_mode_recovery_timer_init(xhci); | |
519 | } | |
520 | ||
66d4eadd SS |
521 | return retval; |
522 | } | |
523 | ||
7f84eef0 SS |
524 | /*-------------------------------------------------------------------------*/ |
525 | ||
7f84eef0 | 526 | |
f6ff0ac8 SS |
527 | static int xhci_run_finished(struct xhci_hcd *xhci) |
528 | { | |
529 | if (xhci_start(xhci)) { | |
530 | xhci_halt(xhci); | |
531 | return -ENODEV; | |
532 | } | |
533 | xhci->shared_hcd->state = HC_STATE_RUNNING; | |
c181bc5b | 534 | xhci->cmd_ring_state = CMD_RING_STATE_RUNNING; |
f6ff0ac8 SS |
535 | |
536 | if (xhci->quirks & XHCI_NEC_HOST) | |
537 | xhci_ring_cmd_db(xhci); | |
538 | ||
d195fcff XR |
539 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
540 | "Finished xhci_run for USB3 roothub"); | |
f6ff0ac8 SS |
541 | return 0; |
542 | } | |
543 | ||
66d4eadd SS |
544 | /* |
545 | * Start the HC after it was halted. | |
546 | * | |
547 | * This function is called by the USB core when the HC driver is added. | |
548 | * Its opposite is xhci_stop(). | |
549 | * | |
550 | * xhci_init() must be called once before this function can be called. | |
551 | * Reset the HC, enable device slot contexts, program DCBAAP, and | |
552 | * set command ring pointer and event ring pointer. | |
553 | * | |
554 | * Setup MSI-X vectors and enable interrupts. | |
555 | */ | |
556 | int xhci_run(struct usb_hcd *hcd) | |
557 | { | |
558 | u32 temp; | |
8e595a5d | 559 | u64 temp_64; |
3fd1ec58 | 560 | int ret; |
66d4eadd | 561 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); |
66d4eadd | 562 | |
f6ff0ac8 SS |
563 | /* Start the xHCI host controller running only after the USB 2.0 roothub |
564 | * is setup. | |
565 | */ | |
66d4eadd | 566 | |
0f2a7930 | 567 | hcd->uses_new_polling = 1; |
f6ff0ac8 SS |
568 | if (!usb_hcd_is_primary_hcd(hcd)) |
569 | return xhci_run_finished(xhci); | |
0f2a7930 | 570 | |
d195fcff | 571 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run"); |
43b86af8 | 572 | |
3fd1ec58 | 573 | ret = xhci_try_enable_msi(hcd); |
43b86af8 | 574 | if (ret) |
3fd1ec58 | 575 | return ret; |
66d4eadd | 576 | |
66e49d87 SS |
577 | xhci_dbg_cmd_ptrs(xhci); |
578 | ||
579 | xhci_dbg(xhci, "ERST memory map follows:\n"); | |
580 | xhci_dbg_erst(xhci, &xhci->erst); | |
f7b2e403 | 581 | temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); |
66e49d87 | 582 | temp_64 &= ~ERST_PTR_MASK; |
d195fcff XR |
583 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
584 | "ERST deq = 64'h%0lx", (long unsigned int) temp_64); | |
66e49d87 | 585 | |
d195fcff XR |
586 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
587 | "// Set the interrupt modulation register"); | |
b0ba9720 | 588 | temp = readl(&xhci->ir_set->irq_control); |
a4d88302 | 589 | temp &= ~ER_IRQ_INTERVAL_MASK; |
0cbd4b34 CY |
590 | /* |
591 | * the increment interval is 8 times as much as that defined | |
592 | * in xHCI spec on MTK's controller | |
593 | */ | |
594 | temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160); | |
204b7793 | 595 | writel(temp, &xhci->ir_set->irq_control); |
66d4eadd SS |
596 | |
597 | /* Set the HCD state before we enable the irqs */ | |
b0ba9720 | 598 | temp = readl(&xhci->op_regs->command); |
66d4eadd | 599 | temp |= (CMD_EIE); |
d195fcff XR |
600 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
601 | "// Enable interrupts, cmd = 0x%x.", temp); | |
204b7793 | 602 | writel(temp, &xhci->op_regs->command); |
66d4eadd | 603 | |
b0ba9720 | 604 | temp = readl(&xhci->ir_set->irq_pending); |
d195fcff XR |
605 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
606 | "// Enabling event ring interrupter %p by writing 0x%x to irq_pending", | |
700e2052 | 607 | xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp)); |
204b7793 | 608 | writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 609 | xhci_print_ir_set(xhci, 0); |
66d4eadd | 610 | |
ddba5cd0 MN |
611 | if (xhci->quirks & XHCI_NEC_HOST) { |
612 | struct xhci_command *command; | |
74e0b564 | 613 | |
ddba5cd0 MN |
614 | command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); |
615 | if (!command) | |
616 | return -ENOMEM; | |
74e0b564 | 617 | |
d6f5f071 | 618 | ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0, |
0238634d | 619 | TRB_TYPE(TRB_NEC_GET_FW)); |
d6f5f071 SW |
620 | if (ret) |
621 | xhci_free_command(xhci, command); | |
ddba5cd0 | 622 | } |
d195fcff XR |
623 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
624 | "Finished xhci_run for USB2 roothub"); | |
02b6fdc2 | 625 | |
b6c33de0 LB |
626 | xhci_dbc_init(xhci); |
627 | ||
02b6fdc2 LB |
628 | xhci_debugfs_init(xhci); |
629 | ||
f6ff0ac8 SS |
630 | return 0; |
631 | } | |
436e8c7d | 632 | EXPORT_SYMBOL_GPL(xhci_run); |
ed07453f | 633 | |
66d4eadd SS |
634 | /* |
635 | * Stop xHCI driver. | |
636 | * | |
637 | * This function is called by the USB core when the HC driver is removed. | |
638 | * Its opposite is xhci_run(). | |
639 | * | |
640 | * Disable device contexts, disable IRQs, and quiesce the HC. | |
641 | * Reset the HC, finish any completed transactions, and cleanup memory. | |
642 | */ | |
3969384c | 643 | static void xhci_stop(struct usb_hcd *hcd) |
66d4eadd SS |
644 | { |
645 | u32 temp; | |
646 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
647 | ||
8c24d6d7 | 648 | mutex_lock(&xhci->mutex); |
8c24d6d7 | 649 | |
fe190ed0 | 650 | /* Only halt host and free memory after both hcds are removed */ |
27a41a83 | 651 | if (!usb_hcd_is_primary_hcd(hcd)) { |
fe190ed0 JS |
652 | /* usb core will free this hcd shortly, unset pointer */ |
653 | xhci->shared_hcd = NULL; | |
27a41a83 GKB |
654 | mutex_unlock(&xhci->mutex); |
655 | return; | |
656 | } | |
66d4eadd | 657 | |
b6c33de0 LB |
658 | xhci_dbc_exit(xhci); |
659 | ||
fe190ed0 JS |
660 | spin_lock_irq(&xhci->lock); |
661 | xhci->xhc_state |= XHCI_STATE_HALTED; | |
662 | xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; | |
663 | xhci_halt(xhci); | |
664 | xhci_reset(xhci); | |
665 | spin_unlock_irq(&xhci->lock); | |
666 | ||
40a9fb17 ZR |
667 | xhci_cleanup_msix(xhci); |
668 | ||
71c731a2 AC |
669 | /* Deleting Compliance Mode Recovery Timer */ |
670 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
58b1d799 | 671 | (!(xhci_all_ports_seen_u0(xhci)))) { |
71c731a2 | 672 | del_timer_sync(&xhci->comp_mode_recovery_timer); |
4bdfe4c3 XR |
673 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
674 | "%s: compliance mode recovery timer deleted", | |
58b1d799 TC |
675 | __func__); |
676 | } | |
71c731a2 | 677 | |
c41136b0 AX |
678 | if (xhci->quirks & XHCI_AMD_PLL_FIX) |
679 | usb_amd_dev_put(); | |
680 | ||
d195fcff XR |
681 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
682 | "// Disabling event ring interrupts"); | |
b0ba9720 | 683 | temp = readl(&xhci->op_regs->status); |
d1001ab4 | 684 | writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status); |
b0ba9720 | 685 | temp = readl(&xhci->ir_set->irq_pending); |
204b7793 | 686 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 687 | xhci_print_ir_set(xhci, 0); |
66d4eadd | 688 | |
d195fcff | 689 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory"); |
66d4eadd | 690 | xhci_mem_cleanup(xhci); |
0467ba5f | 691 | xhci_debugfs_exit(xhci); |
d195fcff XR |
692 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
693 | "xhci_stop completed - status = %x", | |
b0ba9720 | 694 | readl(&xhci->op_regs->status)); |
85ac90f8 | 695 | mutex_unlock(&xhci->mutex); |
66d4eadd SS |
696 | } |
697 | ||
698 | /* | |
699 | * Shutdown HC (not bus-specific) | |
700 | * | |
701 | * This is called when the machine is rebooting or halting. We assume that the | |
702 | * machine will be powered off, and the HC's internal state will be reset. | |
703 | * Don't bother to free memory. | |
f6ff0ac8 SS |
704 | * |
705 | * This will only ever be called with the main usb_hcd (the USB3 roothub). | |
66d4eadd | 706 | */ |
3969384c | 707 | static void xhci_shutdown(struct usb_hcd *hcd) |
66d4eadd SS |
708 | { |
709 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
710 | ||
052c7f9f | 711 | if (xhci->quirks & XHCI_SPURIOUS_REBOOT) |
4c39d4b9 | 712 | usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev)); |
e95829f4 | 713 | |
66d4eadd SS |
714 | spin_lock_irq(&xhci->lock); |
715 | xhci_halt(xhci); | |
638298dc TI |
716 | /* Workaround for spurious wakeups at shutdown with HSW */ |
717 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
718 | xhci_reset(xhci); | |
43b86af8 | 719 | spin_unlock_irq(&xhci->lock); |
66d4eadd | 720 | |
40a9fb17 ZR |
721 | xhci_cleanup_msix(xhci); |
722 | ||
d195fcff XR |
723 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
724 | "xhci_shutdown completed - status = %x", | |
b0ba9720 | 725 | readl(&xhci->op_regs->status)); |
638298dc TI |
726 | |
727 | /* Yet another workaround for spurious wakeups at shutdown with HSW */ | |
728 | if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) | |
4c39d4b9 | 729 | pci_set_power_state(to_pci_dev(hcd->self.sysdev), PCI_D3hot); |
66d4eadd SS |
730 | } |
731 | ||
b5b5c3ac | 732 | #ifdef CONFIG_PM |
5535b1d5 AX |
733 | static void xhci_save_registers(struct xhci_hcd *xhci) |
734 | { | |
b0ba9720 XR |
735 | xhci->s3.command = readl(&xhci->op_regs->command); |
736 | xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification); | |
f7b2e403 | 737 | xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
b0ba9720 XR |
738 | xhci->s3.config_reg = readl(&xhci->op_regs->config_reg); |
739 | xhci->s3.erst_size = readl(&xhci->ir_set->erst_size); | |
f7b2e403 SS |
740 | xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base); |
741 | xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue); | |
b0ba9720 XR |
742 | xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending); |
743 | xhci->s3.irq_control = readl(&xhci->ir_set->irq_control); | |
5535b1d5 AX |
744 | } |
745 | ||
746 | static void xhci_restore_registers(struct xhci_hcd *xhci) | |
747 | { | |
204b7793 XR |
748 | writel(xhci->s3.command, &xhci->op_regs->command); |
749 | writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification); | |
477632df | 750 | xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr); |
204b7793 XR |
751 | writel(xhci->s3.config_reg, &xhci->op_regs->config_reg); |
752 | writel(xhci->s3.erst_size, &xhci->ir_set->erst_size); | |
477632df SS |
753 | xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base); |
754 | xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue); | |
204b7793 XR |
755 | writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending); |
756 | writel(xhci->s3.irq_control, &xhci->ir_set->irq_control); | |
5535b1d5 AX |
757 | } |
758 | ||
89821320 SS |
759 | static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci) |
760 | { | |
761 | u64 val_64; | |
762 | ||
763 | /* step 2: initialize command ring buffer */ | |
f7b2e403 | 764 | val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); |
89821320 SS |
765 | val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) | |
766 | (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg, | |
767 | xhci->cmd_ring->dequeue) & | |
768 | (u64) ~CMD_RING_RSVD_BITS) | | |
769 | xhci->cmd_ring->cycle_state; | |
d195fcff XR |
770 | xhci_dbg_trace(xhci, trace_xhci_dbg_init, |
771 | "// Setting command ring address to 0x%llx", | |
89821320 | 772 | (long unsigned long) val_64); |
477632df | 773 | xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); |
89821320 SS |
774 | } |
775 | ||
776 | /* | |
777 | * The whole command ring must be cleared to zero when we suspend the host. | |
778 | * | |
779 | * The host doesn't save the command ring pointer in the suspend well, so we | |
780 | * need to re-program it on resume. Unfortunately, the pointer must be 64-byte | |
781 | * aligned, because of the reserved bits in the command ring dequeue pointer | |
782 | * register. Therefore, we can't just set the dequeue pointer back in the | |
783 | * middle of the ring (TRBs are 16-byte aligned). | |
784 | */ | |
785 | static void xhci_clear_command_ring(struct xhci_hcd *xhci) | |
786 | { | |
787 | struct xhci_ring *ring; | |
788 | struct xhci_segment *seg; | |
789 | ||
790 | ring = xhci->cmd_ring; | |
791 | seg = ring->deq_seg; | |
792 | do { | |
158886cd AX |
793 | memset(seg->trbs, 0, |
794 | sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1)); | |
795 | seg->trbs[TRBS_PER_SEGMENT - 1].link.control &= | |
796 | cpu_to_le32(~TRB_CYCLE); | |
89821320 SS |
797 | seg = seg->next; |
798 | } while (seg != ring->deq_seg); | |
799 | ||
800 | /* Reset the software enqueue and dequeue pointers */ | |
801 | ring->deq_seg = ring->first_seg; | |
802 | ring->dequeue = ring->first_seg->trbs; | |
803 | ring->enq_seg = ring->deq_seg; | |
804 | ring->enqueue = ring->dequeue; | |
805 | ||
b008df60 | 806 | ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1; |
89821320 SS |
807 | /* |
808 | * Ring is now zeroed, so the HW should look for change of ownership | |
809 | * when the cycle bit is set to 1. | |
810 | */ | |
811 | ring->cycle_state = 1; | |
812 | ||
813 | /* | |
814 | * Reset the hardware dequeue pointer. | |
815 | * Yes, this will need to be re-written after resume, but we're paranoid | |
816 | * and want to make sure the hardware doesn't access bogus memory | |
817 | * because, say, the BIOS or an SMI started the host without changing | |
818 | * the command ring pointers. | |
819 | */ | |
820 | xhci_set_cmd_ring_deq(xhci); | |
821 | } | |
822 | ||
a1377e53 LB |
823 | static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci) |
824 | { | |
825 | int port_index; | |
826 | __le32 __iomem **port_array; | |
827 | unsigned long flags; | |
828 | u32 t1, t2; | |
829 | ||
830 | spin_lock_irqsave(&xhci->lock, flags); | |
831 | ||
8a1115ff | 832 | /* disable usb3 ports Wake bits */ |
a1377e53 LB |
833 | port_index = xhci->num_usb3_ports; |
834 | port_array = xhci->usb3_ports; | |
835 | while (port_index--) { | |
836 | t1 = readl(port_array[port_index]); | |
837 | t1 = xhci_port_state_to_neutral(t1); | |
838 | t2 = t1 & ~PORT_WAKE_BITS; | |
839 | if (t1 != t2) | |
840 | writel(t2, port_array[port_index]); | |
841 | } | |
842 | ||
8a1115ff | 843 | /* disable usb2 ports Wake bits */ |
a1377e53 LB |
844 | port_index = xhci->num_usb2_ports; |
845 | port_array = xhci->usb2_ports; | |
846 | while (port_index--) { | |
847 | t1 = readl(port_array[port_index]); | |
848 | t1 = xhci_port_state_to_neutral(t1); | |
849 | t2 = t1 & ~PORT_WAKE_BITS; | |
850 | if (t1 != t2) | |
851 | writel(t2, port_array[port_index]); | |
852 | } | |
853 | ||
854 | spin_unlock_irqrestore(&xhci->lock, flags); | |
855 | } | |
856 | ||
5535b1d5 AX |
857 | /* |
858 | * Stop HC (not bus-specific) | |
859 | * | |
860 | * This is called when the machine transition into S3/S4 mode. | |
861 | * | |
862 | */ | |
a1377e53 | 863 | int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup) |
5535b1d5 AX |
864 | { |
865 | int rc = 0; | |
455f5892 | 866 | unsigned int delay = XHCI_MAX_HALT_USEC; |
5535b1d5 AX |
867 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
868 | u32 command; | |
869 | ||
9fa733f2 RQ |
870 | if (!hcd->state) |
871 | return 0; | |
872 | ||
77b84767 FB |
873 | if (hcd->state != HC_STATE_SUSPENDED || |
874 | xhci->shared_hcd->state != HC_STATE_SUSPENDED) | |
875 | return -EINVAL; | |
876 | ||
b6c33de0 LB |
877 | xhci_dbc_suspend(xhci); |
878 | ||
a1377e53 LB |
879 | /* Clear root port wake on bits if wakeup not allowed. */ |
880 | if (!do_wakeup) | |
881 | xhci_disable_port_wake_on_bits(xhci); | |
882 | ||
c52804a4 SS |
883 | /* Don't poll the roothubs on bus suspend. */ |
884 | xhci_dbg(xhci, "%s: stopping port polling.\n", __func__); | |
885 | clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); | |
886 | del_timer_sync(&hcd->rh_timer); | |
14e61a1b AC |
887 | clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); |
888 | del_timer_sync(&xhci->shared_hcd->rh_timer); | |
c52804a4 | 889 | |
5535b1d5 AX |
890 | spin_lock_irq(&xhci->lock); |
891 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); | |
b3209379 | 892 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); |
5535b1d5 AX |
893 | /* step 1: stop endpoint */ |
894 | /* skipped assuming that port suspend has done */ | |
895 | ||
896 | /* step 2: clear Run/Stop bit */ | |
b0ba9720 | 897 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 898 | command &= ~CMD_RUN; |
204b7793 | 899 | writel(command, &xhci->op_regs->command); |
455f5892 ON |
900 | |
901 | /* Some chips from Fresco Logic need an extraordinary delay */ | |
902 | delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1; | |
903 | ||
dc0b177c | 904 | if (xhci_handshake(&xhci->op_regs->status, |
455f5892 | 905 | STS_HALT, STS_HALT, delay)) { |
5535b1d5 AX |
906 | xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n"); |
907 | spin_unlock_irq(&xhci->lock); | |
908 | return -ETIMEDOUT; | |
909 | } | |
89821320 | 910 | xhci_clear_command_ring(xhci); |
5535b1d5 AX |
911 | |
912 | /* step 3: save registers */ | |
913 | xhci_save_registers(xhci); | |
914 | ||
915 | /* step 4: set CSS flag */ | |
b0ba9720 | 916 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 917 | command |= CMD_CSS; |
204b7793 | 918 | writel(command, &xhci->op_regs->command); |
dc0b177c | 919 | if (xhci_handshake(&xhci->op_regs->status, |
2611bd18 | 920 | STS_SAVE, 0, 10 * 1000)) { |
622eb783 | 921 | xhci_warn(xhci, "WARN: xHC save state timeout\n"); |
5535b1d5 AX |
922 | spin_unlock_irq(&xhci->lock); |
923 | return -ETIMEDOUT; | |
924 | } | |
5535b1d5 AX |
925 | spin_unlock_irq(&xhci->lock); |
926 | ||
71c731a2 AC |
927 | /* |
928 | * Deleting Compliance Mode Recovery Timer because the xHCI Host | |
929 | * is about to be suspended. | |
930 | */ | |
931 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
932 | (!(xhci_all_ports_seen_u0(xhci)))) { | |
933 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
934 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
935 | "%s: compliance mode recovery timer deleted", | |
58b1d799 | 936 | __func__); |
71c731a2 AC |
937 | } |
938 | ||
0029227f AX |
939 | /* step 5: remove core well power */ |
940 | /* synchronize irq when using MSI-X */ | |
421aa841 | 941 | xhci_msix_sync_irqs(xhci); |
0029227f | 942 | |
5535b1d5 AX |
943 | return rc; |
944 | } | |
436e8c7d | 945 | EXPORT_SYMBOL_GPL(xhci_suspend); |
5535b1d5 AX |
946 | |
947 | /* | |
948 | * start xHC (not bus-specific) | |
949 | * | |
950 | * This is called when the machine transition from S3/S4 mode. | |
951 | * | |
952 | */ | |
953 | int xhci_resume(struct xhci_hcd *xhci, bool hibernated) | |
954 | { | |
d6236f6d | 955 | u32 command, temp = 0, status; |
5535b1d5 | 956 | struct usb_hcd *hcd = xhci_to_hcd(xhci); |
65b22f93 | 957 | struct usb_hcd *secondary_hcd; |
f69e3120 | 958 | int retval = 0; |
77df9e0b | 959 | bool comp_timer_running = false; |
5535b1d5 | 960 | |
9fa733f2 RQ |
961 | if (!hcd->state) |
962 | return 0; | |
963 | ||
f6ff0ac8 | 964 | /* Wait a bit if either of the roothubs need to settle from the |
25985edc | 965 | * transition into bus suspend. |
20b67cf5 | 966 | */ |
f6ff0ac8 SS |
967 | if (time_before(jiffies, xhci->bus_state[0].next_statechange) || |
968 | time_before(jiffies, | |
969 | xhci->bus_state[1].next_statechange)) | |
5535b1d5 AX |
970 | msleep(100); |
971 | ||
f69e3120 AS |
972 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); |
973 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); | |
974 | ||
5535b1d5 | 975 | spin_lock_irq(&xhci->lock); |
c877b3b2 ML |
976 | if (xhci->quirks & XHCI_RESET_ON_RESUME) |
977 | hibernated = true; | |
5535b1d5 AX |
978 | |
979 | if (!hibernated) { | |
980 | /* step 1: restore register */ | |
981 | xhci_restore_registers(xhci); | |
982 | /* step 2: initialize command ring buffer */ | |
89821320 | 983 | xhci_set_cmd_ring_deq(xhci); |
5535b1d5 AX |
984 | /* step 3: restore state and start state*/ |
985 | /* step 3: set CRS flag */ | |
b0ba9720 | 986 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 987 | command |= CMD_CRS; |
204b7793 | 988 | writel(command, &xhci->op_regs->command); |
dc0b177c | 989 | if (xhci_handshake(&xhci->op_regs->status, |
622eb783 AX |
990 | STS_RESTORE, 0, 10 * 1000)) { |
991 | xhci_warn(xhci, "WARN: xHC restore state timeout\n"); | |
5535b1d5 AX |
992 | spin_unlock_irq(&xhci->lock); |
993 | return -ETIMEDOUT; | |
994 | } | |
b0ba9720 | 995 | temp = readl(&xhci->op_regs->status); |
5535b1d5 AX |
996 | } |
997 | ||
998 | /* If restore operation fails, re-initialize the HC during resume */ | |
999 | if ((temp & STS_SRE) || hibernated) { | |
77df9e0b TC |
1000 | |
1001 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && | |
1002 | !(xhci_all_ports_seen_u0(xhci))) { | |
1003 | del_timer_sync(&xhci->comp_mode_recovery_timer); | |
4bdfe4c3 XR |
1004 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1005 | "Compliance Mode Recovery Timer deleted!"); | |
77df9e0b TC |
1006 | } |
1007 | ||
fedd383e SS |
1008 | /* Let the USB core know _both_ roothubs lost power. */ |
1009 | usb_root_hub_lost_power(xhci->main_hcd->self.root_hub); | |
1010 | usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub); | |
5535b1d5 AX |
1011 | |
1012 | xhci_dbg(xhci, "Stop HCD\n"); | |
1013 | xhci_halt(xhci); | |
1014 | xhci_reset(xhci); | |
5535b1d5 | 1015 | spin_unlock_irq(&xhci->lock); |
0029227f | 1016 | xhci_cleanup_msix(xhci); |
5535b1d5 | 1017 | |
5535b1d5 | 1018 | xhci_dbg(xhci, "// Disabling event ring interrupts\n"); |
b0ba9720 | 1019 | temp = readl(&xhci->op_regs->status); |
d1001ab4 | 1020 | writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status); |
b0ba9720 | 1021 | temp = readl(&xhci->ir_set->irq_pending); |
204b7793 | 1022 | writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending); |
09ece30e | 1023 | xhci_print_ir_set(xhci, 0); |
5535b1d5 AX |
1024 | |
1025 | xhci_dbg(xhci, "cleaning up memory\n"); | |
1026 | xhci_mem_cleanup(xhci); | |
96cb3baf | 1027 | xhci_debugfs_exit(xhci); |
5535b1d5 | 1028 | xhci_dbg(xhci, "xhci_stop completed - status = %x\n", |
b0ba9720 | 1029 | readl(&xhci->op_regs->status)); |
5535b1d5 | 1030 | |
65b22f93 SS |
1031 | /* USB core calls the PCI reinit and start functions twice: |
1032 | * first with the primary HCD, and then with the secondary HCD. | |
1033 | * If we don't do the same, the host will never be started. | |
1034 | */ | |
1035 | if (!usb_hcd_is_primary_hcd(hcd)) | |
1036 | secondary_hcd = hcd; | |
1037 | else | |
1038 | secondary_hcd = xhci->shared_hcd; | |
1039 | ||
1040 | xhci_dbg(xhci, "Initialize the xhci_hcd\n"); | |
1041 | retval = xhci_init(hcd->primary_hcd); | |
5535b1d5 AX |
1042 | if (retval) |
1043 | return retval; | |
77df9e0b TC |
1044 | comp_timer_running = true; |
1045 | ||
65b22f93 SS |
1046 | xhci_dbg(xhci, "Start the primary HCD\n"); |
1047 | retval = xhci_run(hcd->primary_hcd); | |
b3209379 | 1048 | if (!retval) { |
f69e3120 AS |
1049 | xhci_dbg(xhci, "Start the secondary HCD\n"); |
1050 | retval = xhci_run(secondary_hcd); | |
b3209379 | 1051 | } |
5535b1d5 | 1052 | hcd->state = HC_STATE_SUSPENDED; |
b3209379 | 1053 | xhci->shared_hcd->state = HC_STATE_SUSPENDED; |
f69e3120 | 1054 | goto done; |
5535b1d5 AX |
1055 | } |
1056 | ||
5535b1d5 | 1057 | /* step 4: set Run/Stop bit */ |
b0ba9720 | 1058 | command = readl(&xhci->op_regs->command); |
5535b1d5 | 1059 | command |= CMD_RUN; |
204b7793 | 1060 | writel(command, &xhci->op_regs->command); |
dc0b177c | 1061 | xhci_handshake(&xhci->op_regs->status, STS_HALT, |
5535b1d5 AX |
1062 | 0, 250 * 1000); |
1063 | ||
1064 | /* step 5: walk topology and initialize portsc, | |
1065 | * portpmsc and portli | |
1066 | */ | |
1067 | /* this is done in bus_resume */ | |
1068 | ||
1069 | /* step 6: restart each of the previously | |
1070 | * Running endpoints by ringing their doorbells | |
1071 | */ | |
1072 | ||
5535b1d5 | 1073 | spin_unlock_irq(&xhci->lock); |
f69e3120 | 1074 | |
b6c33de0 LB |
1075 | xhci_dbc_resume(xhci); |
1076 | ||
f69e3120 AS |
1077 | done: |
1078 | if (retval == 0) { | |
d6236f6d WY |
1079 | /* Resume root hubs only when have pending events. */ |
1080 | status = readl(&xhci->op_regs->status); | |
1081 | if (status & STS_EINT) { | |
d6236f6d | 1082 | usb_hcd_resume_root_hub(xhci->shared_hcd); |
671ffdff | 1083 | usb_hcd_resume_root_hub(hcd); |
d6236f6d | 1084 | } |
f69e3120 | 1085 | } |
71c731a2 AC |
1086 | |
1087 | /* | |
1088 | * If system is subject to the Quirk, Compliance Mode Timer needs to | |
1089 | * be re-initialized Always after a system resume. Ports are subject | |
1090 | * to suffer the Compliance Mode issue again. It doesn't matter if | |
1091 | * ports have entered previously to U0 before system's suspension. | |
1092 | */ | |
77df9e0b | 1093 | if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running) |
71c731a2 AC |
1094 | compliance_mode_recovery_timer_init(xhci); |
1095 | ||
9da5a109 JC |
1096 | if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL) |
1097 | usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller)); | |
1098 | ||
c52804a4 SS |
1099 | /* Re-enable port polling. */ |
1100 | xhci_dbg(xhci, "%s: starting port polling.\n", __func__); | |
14e61a1b AC |
1101 | set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); |
1102 | usb_hcd_poll_rh_status(xhci->shared_hcd); | |
671ffdff MN |
1103 | set_bit(HCD_FLAG_POLL_RH, &hcd->flags); |
1104 | usb_hcd_poll_rh_status(hcd); | |
c52804a4 | 1105 | |
f69e3120 | 1106 | return retval; |
5535b1d5 | 1107 | } |
436e8c7d | 1108 | EXPORT_SYMBOL_GPL(xhci_resume); |
b5b5c3ac SS |
1109 | #endif /* CONFIG_PM */ |
1110 | ||
7f84eef0 SS |
1111 | /*-------------------------------------------------------------------------*/ |
1112 | ||
d0e96f5a SS |
1113 | /** |
1114 | * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and | |
1115 | * HCDs. Find the index for an endpoint given its descriptor. Use the return | |
1116 | * value to right shift 1 for the bitmask. | |
1117 | * | |
1118 | * Index = (epnum * 2) + direction - 1, | |
1119 | * where direction = 0 for OUT, 1 for IN. | |
1120 | * For control endpoints, the IN index is used (OUT index is unused), so | |
1121 | * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2) | |
1122 | */ | |
1123 | unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc) | |
1124 | { | |
1125 | unsigned int index; | |
1126 | if (usb_endpoint_xfer_control(desc)) | |
1127 | index = (unsigned int) (usb_endpoint_num(desc)*2); | |
1128 | else | |
1129 | index = (unsigned int) (usb_endpoint_num(desc)*2) + | |
1130 | (usb_endpoint_dir_in(desc) ? 1 : 0) - 1; | |
1131 | return index; | |
1132 | } | |
1133 | ||
01c5f447 JW |
1134 | /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint |
1135 | * address from the XHCI endpoint index. | |
1136 | */ | |
1137 | unsigned int xhci_get_endpoint_address(unsigned int ep_index) | |
1138 | { | |
1139 | unsigned int number = DIV_ROUND_UP(ep_index, 2); | |
1140 | unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN; | |
1141 | return direction | number; | |
1142 | } | |
1143 | ||
f94e0186 SS |
1144 | /* Find the flag for this endpoint (for use in the control context). Use the |
1145 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1146 | * bit 1, etc. | |
1147 | */ | |
3969384c | 1148 | static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc) |
f94e0186 SS |
1149 | { |
1150 | return 1 << (xhci_get_endpoint_index(desc) + 1); | |
1151 | } | |
1152 | ||
ac9d8fe7 SS |
1153 | /* Find the flag for this endpoint (for use in the control context). Use the |
1154 | * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is | |
1155 | * bit 1, etc. | |
1156 | */ | |
3969384c | 1157 | static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index) |
ac9d8fe7 SS |
1158 | { |
1159 | return 1 << (ep_index + 1); | |
1160 | } | |
1161 | ||
f94e0186 SS |
1162 | /* Compute the last valid endpoint context index. Basically, this is the |
1163 | * endpoint index plus one. For slot contexts with more than valid endpoint, | |
1164 | * we find the most significant bit set in the added contexts flags. | |
1165 | * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000 | |
1166 | * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one. | |
1167 | */ | |
ac9d8fe7 | 1168 | unsigned int xhci_last_valid_endpoint(u32 added_ctxs) |
f94e0186 SS |
1169 | { |
1170 | return fls(added_ctxs) - 1; | |
1171 | } | |
1172 | ||
d0e96f5a SS |
1173 | /* Returns 1 if the arguments are OK; |
1174 | * returns 0 this is a root hub; returns -EINVAL for NULL pointers. | |
1175 | */ | |
8212a49d | 1176 | static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev, |
64927730 AX |
1177 | struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev, |
1178 | const char *func) { | |
1179 | struct xhci_hcd *xhci; | |
1180 | struct xhci_virt_device *virt_dev; | |
1181 | ||
d0e96f5a | 1182 | if (!hcd || (check_ep && !ep) || !udev) { |
5c1127d3 | 1183 | pr_debug("xHCI %s called with invalid args\n", func); |
d0e96f5a SS |
1184 | return -EINVAL; |
1185 | } | |
1186 | if (!udev->parent) { | |
5c1127d3 | 1187 | pr_debug("xHCI %s called for root hub\n", func); |
d0e96f5a SS |
1188 | return 0; |
1189 | } | |
64927730 | 1190 | |
7bd89b40 | 1191 | xhci = hcd_to_xhci(hcd); |
64927730 | 1192 | if (check_virt_dev) { |
73ddc247 | 1193 | if (!udev->slot_id || !xhci->devs[udev->slot_id]) { |
5c1127d3 XR |
1194 | xhci_dbg(xhci, "xHCI %s called with unaddressed device\n", |
1195 | func); | |
64927730 AX |
1196 | return -EINVAL; |
1197 | } | |
1198 | ||
1199 | virt_dev = xhci->devs[udev->slot_id]; | |
1200 | if (virt_dev->udev != udev) { | |
5c1127d3 | 1201 | xhci_dbg(xhci, "xHCI %s called with udev and " |
64927730 AX |
1202 | "virt_dev does not match\n", func); |
1203 | return -EINVAL; | |
1204 | } | |
d0e96f5a | 1205 | } |
64927730 | 1206 | |
203a8661 SS |
1207 | if (xhci->xhc_state & XHCI_STATE_HALTED) |
1208 | return -ENODEV; | |
1209 | ||
d0e96f5a SS |
1210 | return 1; |
1211 | } | |
1212 | ||
2d3f1fac | 1213 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, |
913a8a34 SS |
1214 | struct usb_device *udev, struct xhci_command *command, |
1215 | bool ctx_change, bool must_succeed); | |
2d3f1fac SS |
1216 | |
1217 | /* | |
1218 | * Full speed devices may have a max packet size greater than 8 bytes, but the | |
1219 | * USB core doesn't know that until it reads the first 8 bytes of the | |
1220 | * descriptor. If the usb_device's max packet size changes after that point, | |
1221 | * we need to issue an evaluate context command and wait on it. | |
1222 | */ | |
1223 | static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id, | |
1224 | unsigned int ep_index, struct urb *urb) | |
1225 | { | |
2d3f1fac SS |
1226 | struct xhci_container_ctx *out_ctx; |
1227 | struct xhci_input_control_ctx *ctrl_ctx; | |
1228 | struct xhci_ep_ctx *ep_ctx; | |
ddba5cd0 | 1229 | struct xhci_command *command; |
2d3f1fac SS |
1230 | int max_packet_size; |
1231 | int hw_max_packet_size; | |
1232 | int ret = 0; | |
1233 | ||
1234 | out_ctx = xhci->devs[slot_id]->out_ctx; | |
1235 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); | |
28ccd296 | 1236 | hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2)); |
29cc8897 | 1237 | max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc); |
2d3f1fac | 1238 | if (hw_max_packet_size != max_packet_size) { |
3a7fa5be XR |
1239 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1240 | "Max Packet Size for ep 0 changed."); | |
1241 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, | |
1242 | "Max packet size in usb_device = %d", | |
2d3f1fac | 1243 | max_packet_size); |
3a7fa5be XR |
1244 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1245 | "Max packet size in xHCI HW = %d", | |
2d3f1fac | 1246 | hw_max_packet_size); |
3a7fa5be XR |
1247 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1248 | "Issuing evaluate context command."); | |
2d3f1fac | 1249 | |
92f8e767 SS |
1250 | /* Set up the input context flags for the command */ |
1251 | /* FIXME: This won't work if a non-default control endpoint | |
1252 | * changes max packet sizes. | |
1253 | */ | |
ddba5cd0 MN |
1254 | |
1255 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); | |
1256 | if (!command) | |
1257 | return -ENOMEM; | |
1258 | ||
1259 | command->in_ctx = xhci->devs[slot_id]->in_ctx; | |
4daf9df5 | 1260 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 SS |
1261 | if (!ctrl_ctx) { |
1262 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1263 | __func__); | |
ddba5cd0 MN |
1264 | ret = -ENOMEM; |
1265 | goto command_cleanup; | |
92f8e767 | 1266 | } |
2d3f1fac | 1267 | /* Set up the modified control endpoint 0 */ |
913a8a34 SS |
1268 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
1269 | xhci->devs[slot_id]->out_ctx, ep_index); | |
92f8e767 | 1270 | |
ddba5cd0 | 1271 | ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index); |
28ccd296 ME |
1272 | ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK); |
1273 | ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); | |
2d3f1fac | 1274 | |
28ccd296 | 1275 | ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG); |
2d3f1fac SS |
1276 | ctrl_ctx->drop_flags = 0; |
1277 | ||
ddba5cd0 | 1278 | ret = xhci_configure_endpoint(xhci, urb->dev, command, |
913a8a34 | 1279 | true, false); |
2d3f1fac SS |
1280 | |
1281 | /* Clean up the input context for later use by bandwidth | |
1282 | * functions. | |
1283 | */ | |
28ccd296 | 1284 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); |
ddba5cd0 MN |
1285 | command_cleanup: |
1286 | kfree(command->completion); | |
1287 | kfree(command); | |
2d3f1fac SS |
1288 | } |
1289 | return ret; | |
1290 | } | |
1291 | ||
d0e96f5a SS |
1292 | /* |
1293 | * non-error returns are a promise to giveback() the urb later | |
1294 | * we drop ownership so next owner (or urb unlink) can get it | |
1295 | */ | |
3969384c | 1296 | static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags) |
d0e96f5a SS |
1297 | { |
1298 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
1299 | unsigned long flags; | |
1300 | int ret = 0; | |
6969408d | 1301 | unsigned int slot_id, ep_index, ep_state; |
8e51adcc | 1302 | struct urb_priv *urb_priv; |
7e64b037 | 1303 | int num_tds; |
2d3f1fac | 1304 | |
64927730 AX |
1305 | if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, |
1306 | true, true, __func__) <= 0) | |
d0e96f5a SS |
1307 | return -EINVAL; |
1308 | ||
1309 | slot_id = urb->dev->slot_id; | |
1310 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
d0e96f5a | 1311 | |
541c7d43 | 1312 | if (!HCD_HW_ACCESSIBLE(hcd)) { |
d0e96f5a SS |
1313 | if (!in_interrupt()) |
1314 | xhci_dbg(xhci, "urb submitted during PCI suspend\n"); | |
6969408d | 1315 | return -ESHUTDOWN; |
d0e96f5a | 1316 | } |
8e51adcc AX |
1317 | |
1318 | if (usb_endpoint_xfer_isoc(&urb->ep->desc)) | |
e6f7caa3 | 1319 | num_tds = urb->number_of_packets; |
4758dcd1 RA |
1320 | else if (usb_endpoint_is_bulk_out(&urb->ep->desc) && |
1321 | urb->transfer_buffer_length > 0 && | |
1322 | urb->transfer_flags & URB_ZERO_PACKET && | |
1323 | !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc))) | |
e6f7caa3 | 1324 | num_tds = 2; |
8e51adcc | 1325 | else |
e6f7caa3 | 1326 | num_tds = 1; |
8e51adcc AX |
1327 | |
1328 | urb_priv = kzalloc(sizeof(struct urb_priv) + | |
7e64b037 | 1329 | num_tds * sizeof(struct xhci_td), mem_flags); |
8e51adcc AX |
1330 | if (!urb_priv) |
1331 | return -ENOMEM; | |
1332 | ||
9ef7fbbb MN |
1333 | urb_priv->num_tds = num_tds; |
1334 | urb_priv->num_tds_done = 0; | |
8e51adcc AX |
1335 | urb->hcpriv = urb_priv; |
1336 | ||
5abdc2e6 FB |
1337 | trace_xhci_urb_enqueue(urb); |
1338 | ||
2d3f1fac SS |
1339 | if (usb_endpoint_xfer_control(&urb->ep->desc)) { |
1340 | /* Check to see if the max packet size for the default control | |
1341 | * endpoint changed during FS device enumeration | |
1342 | */ | |
1343 | if (urb->dev->speed == USB_SPEED_FULL) { | |
1344 | ret = xhci_check_maxpacket(xhci, slot_id, | |
1345 | ep_index, urb); | |
d13565c1 | 1346 | if (ret < 0) { |
4daf9df5 | 1347 | xhci_urb_free_priv(urb_priv); |
d13565c1 | 1348 | urb->hcpriv = NULL; |
2d3f1fac | 1349 | return ret; |
d13565c1 | 1350 | } |
2d3f1fac | 1351 | } |
6969408d | 1352 | } |
2d3f1fac | 1353 | |
6969408d MN |
1354 | spin_lock_irqsave(&xhci->lock, flags); |
1355 | ||
1356 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
1357 | xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n", | |
1358 | urb->ep->desc.bEndpointAddress, urb); | |
1359 | ret = -ESHUTDOWN; | |
1360 | goto free_priv; | |
1361 | } | |
1362 | ||
1363 | switch (usb_endpoint_type(&urb->ep->desc)) { | |
1364 | ||
1365 | case USB_ENDPOINT_XFER_CONTROL: | |
b11069f5 | 1366 | ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb, |
6969408d MN |
1367 | slot_id, ep_index); |
1368 | break; | |
1369 | case USB_ENDPOINT_XFER_BULK: | |
1370 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
1371 | if (ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) { | |
1372 | xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n", | |
1373 | ep_state); | |
8df75f42 | 1374 | ret = -EINVAL; |
6969408d | 1375 | break; |
8df75f42 | 1376 | } |
6969408d MN |
1377 | ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, |
1378 | slot_id, ep_index); | |
1379 | break; | |
1380 | ||
1381 | ||
1382 | case USB_ENDPOINT_XFER_INT: | |
624defa1 SS |
1383 | ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb, |
1384 | slot_id, ep_index); | |
6969408d MN |
1385 | break; |
1386 | ||
1387 | case USB_ENDPOINT_XFER_ISOC: | |
787f4e5a AX |
1388 | ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb, |
1389 | slot_id, ep_index); | |
2d3f1fac | 1390 | } |
6969408d MN |
1391 | |
1392 | if (ret) { | |
d13565c1 | 1393 | free_priv: |
6969408d MN |
1394 | xhci_urb_free_priv(urb_priv); |
1395 | urb->hcpriv = NULL; | |
1396 | } | |
6f5165cf | 1397 | spin_unlock_irqrestore(&xhci->lock, flags); |
d13565c1 | 1398 | return ret; |
d0e96f5a SS |
1399 | } |
1400 | ||
ae636747 SS |
1401 | /* |
1402 | * Remove the URB's TD from the endpoint ring. This may cause the HC to stop | |
1403 | * USB transfers, potentially stopping in the middle of a TRB buffer. The HC | |
1404 | * should pick up where it left off in the TD, unless a Set Transfer Ring | |
1405 | * Dequeue Pointer is issued. | |
1406 | * | |
1407 | * The TRBs that make up the buffers for the canceled URB will be "removed" from | |
1408 | * the ring. Since the ring is a contiguous structure, they can't be physically | |
1409 | * removed. Instead, there are two options: | |
1410 | * | |
1411 | * 1) If the HC is in the middle of processing the URB to be canceled, we | |
1412 | * simply move the ring's dequeue pointer past those TRBs using the Set | |
1413 | * Transfer Ring Dequeue Pointer command. This will be the common case, | |
1414 | * when drivers timeout on the last submitted URB and attempt to cancel. | |
1415 | * | |
1416 | * 2) If the HC is in the middle of a different TD, we turn the TRBs into a | |
1417 | * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The | |
1418 | * HC will need to invalidate the any TRBs it has cached after the stop | |
1419 | * endpoint command, as noted in the xHCI 0.95 errata. | |
1420 | * | |
1421 | * 3) The TD may have completed by the time the Stop Endpoint Command | |
1422 | * completes, so software needs to handle that case too. | |
1423 | * | |
1424 | * This function should protect against the TD enqueueing code ringing the | |
1425 | * doorbell while this code is waiting for a Stop Endpoint command to complete. | |
1426 | * It also needs to account for multiple cancellations on happening at the same | |
1427 | * time for the same endpoint. | |
1428 | * | |
1429 | * Note that this function can be called in any context, or so says | |
1430 | * usb_hcd_unlink_urb() | |
d0e96f5a | 1431 | */ |
3969384c | 1432 | static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) |
d0e96f5a | 1433 | { |
ae636747 | 1434 | unsigned long flags; |
8e51adcc | 1435 | int ret, i; |
e34b2fbf | 1436 | u32 temp; |
ae636747 | 1437 | struct xhci_hcd *xhci; |
8e51adcc | 1438 | struct urb_priv *urb_priv; |
ae636747 SS |
1439 | struct xhci_td *td; |
1440 | unsigned int ep_index; | |
1441 | struct xhci_ring *ep_ring; | |
63a0d9ab | 1442 | struct xhci_virt_ep *ep; |
ddba5cd0 | 1443 | struct xhci_command *command; |
d3519b9d | 1444 | struct xhci_virt_device *vdev; |
ae636747 SS |
1445 | |
1446 | xhci = hcd_to_xhci(hcd); | |
1447 | spin_lock_irqsave(&xhci->lock, flags); | |
5abdc2e6 FB |
1448 | |
1449 | trace_xhci_urb_dequeue(urb); | |
1450 | ||
ae636747 SS |
1451 | /* Make sure the URB hasn't completed or been unlinked already */ |
1452 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); | |
d3519b9d | 1453 | if (ret) |
ae636747 | 1454 | goto done; |
d3519b9d MN |
1455 | |
1456 | /* give back URB now if we can't queue it for cancel */ | |
1457 | vdev = xhci->devs[urb->dev->slot_id]; | |
1458 | urb_priv = urb->hcpriv; | |
1459 | if (!vdev || !urb_priv) | |
1460 | goto err_giveback; | |
1461 | ||
1462 | ep_index = xhci_get_endpoint_index(&urb->ep->desc); | |
1463 | ep = &vdev->eps[ep_index]; | |
1464 | ep_ring = xhci_urb_to_transfer_ring(xhci, urb); | |
1465 | if (!ep || !ep_ring) | |
1466 | goto err_giveback; | |
1467 | ||
d9f11ba9 | 1468 | /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */ |
b0ba9720 | 1469 | temp = readl(&xhci->op_regs->status); |
d9f11ba9 MN |
1470 | if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) { |
1471 | xhci_hc_died(xhci); | |
1472 | goto done; | |
1473 | } | |
1474 | ||
1475 | if (xhci->xhc_state & XHCI_STATE_HALTED) { | |
aa50b290 | 1476 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
d9f11ba9 | 1477 | "HC halted, freeing TD manually."); |
9ef7fbbb | 1478 | for (i = urb_priv->num_tds_done; |
d3519b9d | 1479 | i < urb_priv->num_tds; |
5c821711 | 1480 | i++) { |
7e64b037 | 1481 | td = &urb_priv->td[i]; |
585df1d9 SS |
1482 | if (!list_empty(&td->td_list)) |
1483 | list_del_init(&td->td_list); | |
1484 | if (!list_empty(&td->cancelled_td_list)) | |
1485 | list_del_init(&td->cancelled_td_list); | |
1486 | } | |
d3519b9d | 1487 | goto err_giveback; |
e34b2fbf | 1488 | } |
ae636747 | 1489 | |
9ef7fbbb MN |
1490 | i = urb_priv->num_tds_done; |
1491 | if (i < urb_priv->num_tds) | |
aa50b290 XR |
1492 | xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, |
1493 | "Cancel URB %p, dev %s, ep 0x%x, " | |
1494 | "starting at offset 0x%llx", | |
79688acf SS |
1495 | urb, urb->dev->devpath, |
1496 | urb->ep->desc.bEndpointAddress, | |
1497 | (unsigned long long) xhci_trb_virt_to_dma( | |
7e64b037 MN |
1498 | urb_priv->td[i].start_seg, |
1499 | urb_priv->td[i].first_trb)); | |
79688acf | 1500 | |
9ef7fbbb | 1501 | for (; i < urb_priv->num_tds; i++) { |
7e64b037 | 1502 | td = &urb_priv->td[i]; |
8e51adcc AX |
1503 | list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list); |
1504 | } | |
1505 | ||
ae636747 SS |
1506 | /* Queue a stop endpoint command, but only if this is |
1507 | * the first cancellation to be handled. | |
1508 | */ | |
9983a5fc | 1509 | if (!(ep->ep_state & EP_STOP_CMD_PENDING)) { |
ddba5cd0 | 1510 | command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC); |
a0ee619f HG |
1511 | if (!command) { |
1512 | ret = -ENOMEM; | |
1513 | goto done; | |
1514 | } | |
9983a5fc | 1515 | ep->ep_state |= EP_STOP_CMD_PENDING; |
6f5165cf SS |
1516 | ep->stop_cmd_timer.expires = jiffies + |
1517 | XHCI_STOP_EP_CMD_TIMEOUT * HZ; | |
1518 | add_timer(&ep->stop_cmd_timer); | |
ddba5cd0 MN |
1519 | xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id, |
1520 | ep_index, 0); | |
23e3be11 | 1521 | xhci_ring_cmd_db(xhci); |
ae636747 SS |
1522 | } |
1523 | done: | |
1524 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1525 | return ret; | |
d3519b9d MN |
1526 | |
1527 | err_giveback: | |
1528 | if (urb_priv) | |
1529 | xhci_urb_free_priv(urb_priv); | |
1530 | usb_hcd_unlink_urb_from_ep(hcd, urb); | |
1531 | spin_unlock_irqrestore(&xhci->lock, flags); | |
1532 | usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN); | |
1533 | return ret; | |
d0e96f5a SS |
1534 | } |
1535 | ||
f94e0186 SS |
1536 | /* Drop an endpoint from a new bandwidth configuration for this device. |
1537 | * Only one call to this function is allowed per endpoint before | |
1538 | * check_bandwidth() or reset_bandwidth() must be called. | |
1539 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1540 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1541 | * different endpoint descriptor in usb_host_endpoint. | |
1542 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1543 | * not allowed. | |
f88ba78d SS |
1544 | * |
1545 | * The USB core will not allow URBs to be queued to an endpoint that is being | |
1546 | * disabled, so there's no need for mutual exclusion to protect | |
1547 | * the xhci->devs[slot_id] structure. | |
f94e0186 | 1548 | */ |
3969384c | 1549 | static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, |
f94e0186 SS |
1550 | struct usb_host_endpoint *ep) |
1551 | { | |
f94e0186 | 1552 | struct xhci_hcd *xhci; |
d115b048 JY |
1553 | struct xhci_container_ctx *in_ctx, *out_ctx; |
1554 | struct xhci_input_control_ctx *ctrl_ctx; | |
f94e0186 SS |
1555 | unsigned int ep_index; |
1556 | struct xhci_ep_ctx *ep_ctx; | |
1557 | u32 drop_flag; | |
d6759133 | 1558 | u32 new_add_flags, new_drop_flags; |
f94e0186 SS |
1559 | int ret; |
1560 | ||
64927730 | 1561 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
f94e0186 SS |
1562 | if (ret <= 0) |
1563 | return ret; | |
1564 | xhci = hcd_to_xhci(hcd); | |
fe6c6c13 SS |
1565 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1566 | return -ENODEV; | |
f94e0186 | 1567 | |
fe6c6c13 | 1568 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
1569 | drop_flag = xhci_get_endpoint_flag(&ep->desc); |
1570 | if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) { | |
1571 | xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n", | |
1572 | __func__, drop_flag); | |
1573 | return 0; | |
1574 | } | |
1575 | ||
f94e0186 | 1576 | in_ctx = xhci->devs[udev->slot_id]->in_ctx; |
d115b048 | 1577 | out_ctx = xhci->devs[udev->slot_id]->out_ctx; |
4daf9df5 | 1578 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
1579 | if (!ctrl_ctx) { |
1580 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1581 | __func__); | |
1582 | return 0; | |
1583 | } | |
1584 | ||
f94e0186 | 1585 | ep_index = xhci_get_endpoint_index(&ep->desc); |
d115b048 | 1586 | ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); |
f94e0186 SS |
1587 | /* If the HC already knows the endpoint is disabled, |
1588 | * or the HCD has noted it is disabled, ignore this request | |
1589 | */ | |
5071e6b2 | 1590 | if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) || |
28ccd296 ME |
1591 | le32_to_cpu(ctrl_ctx->drop_flags) & |
1592 | xhci_get_endpoint_flag(&ep->desc)) { | |
a6134136 HG |
1593 | /* Do not warn when called after a usb_device_reset */ |
1594 | if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL) | |
1595 | xhci_warn(xhci, "xHCI %s called with disabled ep %p\n", | |
1596 | __func__, ep); | |
f94e0186 SS |
1597 | return 0; |
1598 | } | |
1599 | ||
28ccd296 ME |
1600 | ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag); |
1601 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); | |
f94e0186 | 1602 | |
28ccd296 ME |
1603 | ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag); |
1604 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 | 1605 | |
02b6fdc2 LB |
1606 | xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index); |
1607 | ||
f94e0186 SS |
1608 | xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep); |
1609 | ||
0cbd4b34 CY |
1610 | if (xhci->quirks & XHCI_MTK_HOST) |
1611 | xhci_mtk_drop_ep_quirk(hcd, udev, ep); | |
1612 | ||
d6759133 | 1613 | xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n", |
f94e0186 SS |
1614 | (unsigned int) ep->desc.bEndpointAddress, |
1615 | udev->slot_id, | |
1616 | (unsigned int) new_drop_flags, | |
d6759133 | 1617 | (unsigned int) new_add_flags); |
f94e0186 SS |
1618 | return 0; |
1619 | } | |
1620 | ||
1621 | /* Add an endpoint to a new possible bandwidth configuration for this device. | |
1622 | * Only one call to this function is allowed per endpoint before | |
1623 | * check_bandwidth() or reset_bandwidth() must be called. | |
1624 | * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will | |
1625 | * add the endpoint to the schedule with possibly new parameters denoted by a | |
1626 | * different endpoint descriptor in usb_host_endpoint. | |
1627 | * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is | |
1628 | * not allowed. | |
f88ba78d SS |
1629 | * |
1630 | * The USB core will not allow URBs to be queued to an endpoint until the | |
1631 | * configuration or alt setting is installed in the device, so there's no need | |
1632 | * for mutual exclusion to protect the xhci->devs[slot_id] structure. | |
f94e0186 | 1633 | */ |
3969384c | 1634 | static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, |
f94e0186 SS |
1635 | struct usb_host_endpoint *ep) |
1636 | { | |
f94e0186 | 1637 | struct xhci_hcd *xhci; |
92c9691b | 1638 | struct xhci_container_ctx *in_ctx; |
f94e0186 | 1639 | unsigned int ep_index; |
d115b048 | 1640 | struct xhci_input_control_ctx *ctrl_ctx; |
f94e0186 | 1641 | u32 added_ctxs; |
d6759133 | 1642 | u32 new_add_flags, new_drop_flags; |
fa75ac37 | 1643 | struct xhci_virt_device *virt_dev; |
f94e0186 SS |
1644 | int ret = 0; |
1645 | ||
64927730 | 1646 | ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); |
a1587d97 SS |
1647 | if (ret <= 0) { |
1648 | /* So we won't queue a reset ep command for a root hub */ | |
1649 | ep->hcpriv = NULL; | |
f94e0186 | 1650 | return ret; |
a1587d97 | 1651 | } |
f94e0186 | 1652 | xhci = hcd_to_xhci(hcd); |
fe6c6c13 SS |
1653 | if (xhci->xhc_state & XHCI_STATE_DYING) |
1654 | return -ENODEV; | |
f94e0186 SS |
1655 | |
1656 | added_ctxs = xhci_get_endpoint_flag(&ep->desc); | |
f94e0186 SS |
1657 | if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) { |
1658 | /* FIXME when we have to issue an evaluate endpoint command to | |
1659 | * deal with ep0 max packet size changing once we get the | |
1660 | * descriptors | |
1661 | */ | |
1662 | xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n", | |
1663 | __func__, added_ctxs); | |
1664 | return 0; | |
1665 | } | |
1666 | ||
fa75ac37 SS |
1667 | virt_dev = xhci->devs[udev->slot_id]; |
1668 | in_ctx = virt_dev->in_ctx; | |
4daf9df5 | 1669 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
1670 | if (!ctrl_ctx) { |
1671 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1672 | __func__); | |
1673 | return 0; | |
1674 | } | |
fa75ac37 | 1675 | |
92f8e767 | 1676 | ep_index = xhci_get_endpoint_index(&ep->desc); |
fa75ac37 SS |
1677 | /* If this endpoint is already in use, and the upper layers are trying |
1678 | * to add it again without dropping it, reject the addition. | |
1679 | */ | |
1680 | if (virt_dev->eps[ep_index].ring && | |
92c9691b | 1681 | !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) { |
fa75ac37 SS |
1682 | xhci_warn(xhci, "Trying to add endpoint 0x%x " |
1683 | "without dropping it.\n", | |
1684 | (unsigned int) ep->desc.bEndpointAddress); | |
1685 | return -EINVAL; | |
1686 | } | |
1687 | ||
f94e0186 SS |
1688 | /* If the HCD has already noted the endpoint is enabled, |
1689 | * ignore this request. | |
1690 | */ | |
92c9691b | 1691 | if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) { |
700e2052 GKH |
1692 | xhci_warn(xhci, "xHCI %s called with enabled ep %p\n", |
1693 | __func__, ep); | |
f94e0186 SS |
1694 | return 0; |
1695 | } | |
1696 | ||
f88ba78d SS |
1697 | /* |
1698 | * Configuration and alternate setting changes must be done in | |
1699 | * process context, not interrupt context (or so documenation | |
1700 | * for usb_set_interface() and usb_set_configuration() claim). | |
1701 | */ | |
fa75ac37 | 1702 | if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) { |
f94e0186 SS |
1703 | dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n", |
1704 | __func__, ep->desc.bEndpointAddress); | |
f94e0186 SS |
1705 | return -ENOMEM; |
1706 | } | |
1707 | ||
0cbd4b34 CY |
1708 | if (xhci->quirks & XHCI_MTK_HOST) { |
1709 | ret = xhci_mtk_add_ep_quirk(hcd, udev, ep); | |
1710 | if (ret < 0) { | |
9821786d LB |
1711 | xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring); |
1712 | virt_dev->eps[ep_index].new_ring = NULL; | |
0cbd4b34 CY |
1713 | return ret; |
1714 | } | |
1715 | } | |
1716 | ||
28ccd296 ME |
1717 | ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs); |
1718 | new_add_flags = le32_to_cpu(ctrl_ctx->add_flags); | |
f94e0186 SS |
1719 | |
1720 | /* If xhci_endpoint_disable() was called for this endpoint, but the | |
1721 | * xHC hasn't been notified yet through the check_bandwidth() call, | |
1722 | * this re-adds a new state for the endpoint from the new endpoint | |
1723 | * descriptors. We must drop and re-add this endpoint, so we leave the | |
1724 | * drop flags alone. | |
1725 | */ | |
28ccd296 | 1726 | new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags); |
f94e0186 | 1727 | |
a1587d97 SS |
1728 | /* Store the usb_device pointer for later use */ |
1729 | ep->hcpriv = udev; | |
1730 | ||
02b6fdc2 LB |
1731 | xhci_debugfs_create_endpoint(xhci, virt_dev, ep_index); |
1732 | ||
d6759133 | 1733 | xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n", |
f94e0186 SS |
1734 | (unsigned int) ep->desc.bEndpointAddress, |
1735 | udev->slot_id, | |
1736 | (unsigned int) new_drop_flags, | |
d6759133 | 1737 | (unsigned int) new_add_flags); |
f94e0186 SS |
1738 | return 0; |
1739 | } | |
1740 | ||
d115b048 | 1741 | static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev) |
f94e0186 | 1742 | { |
d115b048 | 1743 | struct xhci_input_control_ctx *ctrl_ctx; |
f94e0186 | 1744 | struct xhci_ep_ctx *ep_ctx; |
d115b048 | 1745 | struct xhci_slot_ctx *slot_ctx; |
f94e0186 SS |
1746 | int i; |
1747 | ||
4daf9df5 | 1748 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
92f8e767 SS |
1749 | if (!ctrl_ctx) { |
1750 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
1751 | __func__); | |
1752 | return; | |
1753 | } | |
1754 | ||
f94e0186 SS |
1755 | /* When a device's add flag and drop flag are zero, any subsequent |
1756 | * configure endpoint command will leave that endpoint's state | |
1757 | * untouched. Make sure we don't leave any old state in the input | |
1758 | * endpoint contexts. | |
1759 | */ | |
d115b048 JY |
1760 | ctrl_ctx->drop_flags = 0; |
1761 | ctrl_ctx->add_flags = 0; | |
1762 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); | |
28ccd296 | 1763 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); |
f94e0186 | 1764 | /* Endpoint 0 is always valid */ |
28ccd296 | 1765 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); |
98871e94 | 1766 | for (i = 1; i < 31; i++) { |
d115b048 | 1767 | ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i); |
f94e0186 SS |
1768 | ep_ctx->ep_info = 0; |
1769 | ep_ctx->ep_info2 = 0; | |
8e595a5d | 1770 | ep_ctx->deq = 0; |
f94e0186 SS |
1771 | ep_ctx->tx_info = 0; |
1772 | } | |
1773 | } | |
1774 | ||
f2217e8e | 1775 | static int xhci_configure_endpoint_result(struct xhci_hcd *xhci, |
00161f7d | 1776 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1777 | { |
1778 | int ret; | |
1779 | ||
913a8a34 | 1780 | switch (*cmd_status) { |
0b7c105a | 1781 | case COMP_COMMAND_ABORTED: |
604d02a2 | 1782 | case COMP_COMMAND_RING_STOPPED: |
c311e391 MN |
1783 | xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n"); |
1784 | ret = -ETIME; | |
1785 | break; | |
0b7c105a | 1786 | case COMP_RESOURCE_ERROR: |
288c0f44 ON |
1787 | dev_warn(&udev->dev, |
1788 | "Not enough host controller resources for new device state.\n"); | |
f2217e8e SS |
1789 | ret = -ENOMEM; |
1790 | /* FIXME: can we allocate more resources for the HC? */ | |
1791 | break; | |
0b7c105a FB |
1792 | case COMP_BANDWIDTH_ERROR: |
1793 | case COMP_SECONDARY_BANDWIDTH_ERROR: | |
288c0f44 ON |
1794 | dev_warn(&udev->dev, |
1795 | "Not enough bandwidth for new device state.\n"); | |
f2217e8e SS |
1796 | ret = -ENOSPC; |
1797 | /* FIXME: can we go back to the old state? */ | |
1798 | break; | |
0b7c105a | 1799 | case COMP_TRB_ERROR: |
f2217e8e SS |
1800 | /* the HCD set up something wrong */ |
1801 | dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, " | |
1802 | "add flag = 1, " | |
1803 | "and endpoint is not disabled.\n"); | |
1804 | ret = -EINVAL; | |
1805 | break; | |
0b7c105a | 1806 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
288c0f44 ON |
1807 | dev_warn(&udev->dev, |
1808 | "ERROR: Incompatible device for endpoint configure command.\n"); | |
f6ba6fe2 AH |
1809 | ret = -ENODEV; |
1810 | break; | |
f2217e8e | 1811 | case COMP_SUCCESS: |
3a7fa5be XR |
1812 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1813 | "Successful Endpoint Configure command"); | |
f2217e8e SS |
1814 | ret = 0; |
1815 | break; | |
1816 | default: | |
288c0f44 ON |
1817 | xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n", |
1818 | *cmd_status); | |
f2217e8e SS |
1819 | ret = -EINVAL; |
1820 | break; | |
1821 | } | |
1822 | return ret; | |
1823 | } | |
1824 | ||
1825 | static int xhci_evaluate_context_result(struct xhci_hcd *xhci, | |
00161f7d | 1826 | struct usb_device *udev, u32 *cmd_status) |
f2217e8e SS |
1827 | { |
1828 | int ret; | |
1829 | ||
913a8a34 | 1830 | switch (*cmd_status) { |
0b7c105a | 1831 | case COMP_COMMAND_ABORTED: |
604d02a2 | 1832 | case COMP_COMMAND_RING_STOPPED: |
c311e391 MN |
1833 | xhci_warn(xhci, "Timeout while waiting for evaluate context command\n"); |
1834 | ret = -ETIME; | |
1835 | break; | |
0b7c105a | 1836 | case COMP_PARAMETER_ERROR: |
288c0f44 ON |
1837 | dev_warn(&udev->dev, |
1838 | "WARN: xHCI driver setup invalid evaluate context command.\n"); | |
f2217e8e SS |
1839 | ret = -EINVAL; |
1840 | break; | |
0b7c105a | 1841 | case COMP_SLOT_NOT_ENABLED_ERROR: |
288c0f44 ON |
1842 | dev_warn(&udev->dev, |
1843 | "WARN: slot not enabled for evaluate context command.\n"); | |
b8031342 SS |
1844 | ret = -EINVAL; |
1845 | break; | |
0b7c105a | 1846 | case COMP_CONTEXT_STATE_ERROR: |
288c0f44 ON |
1847 | dev_warn(&udev->dev, |
1848 | "WARN: invalid context state for evaluate context command.\n"); | |
f2217e8e SS |
1849 | ret = -EINVAL; |
1850 | break; | |
0b7c105a | 1851 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
288c0f44 ON |
1852 | dev_warn(&udev->dev, |
1853 | "ERROR: Incompatible device for evaluate context command.\n"); | |
f6ba6fe2 AH |
1854 | ret = -ENODEV; |
1855 | break; | |
0b7c105a | 1856 | case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: |
1bb73a88 AH |
1857 | /* Max Exit Latency too large error */ |
1858 | dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n"); | |
1859 | ret = -EINVAL; | |
1860 | break; | |
f2217e8e | 1861 | case COMP_SUCCESS: |
3a7fa5be XR |
1862 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
1863 | "Successful evaluate context command"); | |
f2217e8e SS |
1864 | ret = 0; |
1865 | break; | |
1866 | default: | |
288c0f44 ON |
1867 | xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n", |
1868 | *cmd_status); | |
f2217e8e SS |
1869 | ret = -EINVAL; |
1870 | break; | |
1871 | } | |
1872 | return ret; | |
1873 | } | |
1874 | ||
2cf95c18 | 1875 | static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci, |
92f8e767 | 1876 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 1877 | { |
2cf95c18 SS |
1878 | u32 valid_add_flags; |
1879 | u32 valid_drop_flags; | |
1880 | ||
2cf95c18 SS |
1881 | /* Ignore the slot flag (bit 0), and the default control endpoint flag |
1882 | * (bit 1). The default control endpoint is added during the Address | |
1883 | * Device command and is never removed until the slot is disabled. | |
1884 | */ | |
ef73400c XR |
1885 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
1886 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; | |
2cf95c18 SS |
1887 | |
1888 | /* Use hweight32 to count the number of ones in the add flags, or | |
1889 | * number of endpoints added. Don't count endpoints that are changed | |
1890 | * (both added and dropped). | |
1891 | */ | |
1892 | return hweight32(valid_add_flags) - | |
1893 | hweight32(valid_add_flags & valid_drop_flags); | |
1894 | } | |
1895 | ||
1896 | static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci, | |
92f8e767 | 1897 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 | 1898 | { |
2cf95c18 SS |
1899 | u32 valid_add_flags; |
1900 | u32 valid_drop_flags; | |
1901 | ||
78d1ff02 XR |
1902 | valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2; |
1903 | valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2; | |
2cf95c18 SS |
1904 | |
1905 | return hweight32(valid_drop_flags) - | |
1906 | hweight32(valid_add_flags & valid_drop_flags); | |
1907 | } | |
1908 | ||
1909 | /* | |
1910 | * We need to reserve the new number of endpoints before the configure endpoint | |
1911 | * command completes. We can't subtract the dropped endpoints from the number | |
1912 | * of active endpoints until the command completes because we can oversubscribe | |
1913 | * the host in this case: | |
1914 | * | |
1915 | * - the first configure endpoint command drops more endpoints than it adds | |
1916 | * - a second configure endpoint command that adds more endpoints is queued | |
1917 | * - the first configure endpoint command fails, so the config is unchanged | |
1918 | * - the second command may succeed, even though there isn't enough resources | |
1919 | * | |
1920 | * Must be called with xhci->lock held. | |
1921 | */ | |
1922 | static int xhci_reserve_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 1923 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1924 | { |
1925 | u32 added_eps; | |
1926 | ||
92f8e767 | 1927 | added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 1928 | if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) { |
4bdfe4c3 XR |
1929 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1930 | "Not enough ep ctxs: " | |
1931 | "%u active, need to add %u, limit is %u.", | |
2cf95c18 SS |
1932 | xhci->num_active_eps, added_eps, |
1933 | xhci->limit_active_eps); | |
1934 | return -ENOMEM; | |
1935 | } | |
1936 | xhci->num_active_eps += added_eps; | |
4bdfe4c3 XR |
1937 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1938 | "Adding %u ep ctxs, %u now active.", added_eps, | |
2cf95c18 SS |
1939 | xhci->num_active_eps); |
1940 | return 0; | |
1941 | } | |
1942 | ||
1943 | /* | |
1944 | * The configure endpoint was failed by the xHC for some other reason, so we | |
1945 | * need to revert the resources that failed configuration would have used. | |
1946 | * | |
1947 | * Must be called with xhci->lock held. | |
1948 | */ | |
1949 | static void xhci_free_host_resources(struct xhci_hcd *xhci, | |
92f8e767 | 1950 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1951 | { |
1952 | u32 num_failed_eps; | |
1953 | ||
92f8e767 | 1954 | num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx); |
2cf95c18 | 1955 | xhci->num_active_eps -= num_failed_eps; |
4bdfe4c3 XR |
1956 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1957 | "Removing %u failed ep ctxs, %u now active.", | |
2cf95c18 SS |
1958 | num_failed_eps, |
1959 | xhci->num_active_eps); | |
1960 | } | |
1961 | ||
1962 | /* | |
1963 | * Now that the command has completed, clean up the active endpoint count by | |
1964 | * subtracting out the endpoints that were dropped (but not changed). | |
1965 | * | |
1966 | * Must be called with xhci->lock held. | |
1967 | */ | |
1968 | static void xhci_finish_resource_reservation(struct xhci_hcd *xhci, | |
92f8e767 | 1969 | struct xhci_input_control_ctx *ctrl_ctx) |
2cf95c18 SS |
1970 | { |
1971 | u32 num_dropped_eps; | |
1972 | ||
92f8e767 | 1973 | num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx); |
2cf95c18 SS |
1974 | xhci->num_active_eps -= num_dropped_eps; |
1975 | if (num_dropped_eps) | |
4bdfe4c3 XR |
1976 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
1977 | "Removing %u dropped ep ctxs, %u now active.", | |
2cf95c18 SS |
1978 | num_dropped_eps, |
1979 | xhci->num_active_eps); | |
1980 | } | |
1981 | ||
ed384bd3 | 1982 | static unsigned int xhci_get_block_size(struct usb_device *udev) |
c29eea62 SS |
1983 | { |
1984 | switch (udev->speed) { | |
1985 | case USB_SPEED_LOW: | |
1986 | case USB_SPEED_FULL: | |
1987 | return FS_BLOCK; | |
1988 | case USB_SPEED_HIGH: | |
1989 | return HS_BLOCK; | |
1990 | case USB_SPEED_SUPER: | |
0caf6b33 | 1991 | case USB_SPEED_SUPER_PLUS: |
c29eea62 SS |
1992 | return SS_BLOCK; |
1993 | case USB_SPEED_UNKNOWN: | |
1994 | case USB_SPEED_WIRELESS: | |
1995 | default: | |
1996 | /* Should never happen */ | |
1997 | return 1; | |
1998 | } | |
1999 | } | |
2000 | ||
ed384bd3 FB |
2001 | static unsigned int |
2002 | xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw) | |
c29eea62 SS |
2003 | { |
2004 | if (interval_bw->overhead[LS_OVERHEAD_TYPE]) | |
2005 | return LS_OVERHEAD; | |
2006 | if (interval_bw->overhead[FS_OVERHEAD_TYPE]) | |
2007 | return FS_OVERHEAD; | |
2008 | return HS_OVERHEAD; | |
2009 | } | |
2010 | ||
2011 | /* If we are changing a LS/FS device under a HS hub, | |
2012 | * make sure (if we are activating a new TT) that the HS bus has enough | |
2013 | * bandwidth for this new TT. | |
2014 | */ | |
2015 | static int xhci_check_tt_bw_table(struct xhci_hcd *xhci, | |
2016 | struct xhci_virt_device *virt_dev, | |
2017 | int old_active_eps) | |
2018 | { | |
2019 | struct xhci_interval_bw_table *bw_table; | |
2020 | struct xhci_tt_bw_info *tt_info; | |
2021 | ||
2022 | /* Find the bandwidth table for the root port this TT is attached to. */ | |
2023 | bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table; | |
2024 | tt_info = virt_dev->tt_info; | |
2025 | /* If this TT already had active endpoints, the bandwidth for this TT | |
2026 | * has already been added. Removing all periodic endpoints (and thus | |
2027 | * making the TT enactive) will only decrease the bandwidth used. | |
2028 | */ | |
2029 | if (old_active_eps) | |
2030 | return 0; | |
2031 | if (old_active_eps == 0 && tt_info->active_eps != 0) { | |
2032 | if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT) | |
2033 | return -ENOMEM; | |
2034 | return 0; | |
2035 | } | |
2036 | /* Not sure why we would have no new active endpoints... | |
2037 | * | |
2038 | * Maybe because of an Evaluate Context change for a hub update or a | |
2039 | * control endpoint 0 max packet size change? | |
2040 | * FIXME: skip the bandwidth calculation in that case. | |
2041 | */ | |
2042 | return 0; | |
2043 | } | |
2044 | ||
2b698999 SS |
2045 | static int xhci_check_ss_bw(struct xhci_hcd *xhci, |
2046 | struct xhci_virt_device *virt_dev) | |
2047 | { | |
2048 | unsigned int bw_reserved; | |
2049 | ||
2050 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100); | |
2051 | if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved)) | |
2052 | return -ENOMEM; | |
2053 | ||
2054 | bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100); | |
2055 | if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved)) | |
2056 | return -ENOMEM; | |
2057 | ||
2058 | return 0; | |
2059 | } | |
2060 | ||
c29eea62 SS |
2061 | /* |
2062 | * This algorithm is a very conservative estimate of the worst-case scheduling | |
2063 | * scenario for any one interval. The hardware dynamically schedules the | |
2064 | * packets, so we can't tell which microframe could be the limiting factor in | |
2065 | * the bandwidth scheduling. This only takes into account periodic endpoints. | |
2066 | * | |
2067 | * Obviously, we can't solve an NP complete problem to find the minimum worst | |
2068 | * case scenario. Instead, we come up with an estimate that is no less than | |
2069 | * the worst case bandwidth used for any one microframe, but may be an | |
2070 | * over-estimate. | |
2071 | * | |
2072 | * We walk the requirements for each endpoint by interval, starting with the | |
2073 | * smallest interval, and place packets in the schedule where there is only one | |
2074 | * possible way to schedule packets for that interval. In order to simplify | |
2075 | * this algorithm, we record the largest max packet size for each interval, and | |
2076 | * assume all packets will be that size. | |
2077 | * | |
2078 | * For interval 0, we obviously must schedule all packets for each interval. | |
2079 | * The bandwidth for interval 0 is just the amount of data to be transmitted | |
2080 | * (the sum of all max ESIT payload sizes, plus any overhead per packet times | |
2081 | * the number of packets). | |
2082 | * | |
2083 | * For interval 1, we have two possible microframes to schedule those packets | |
2084 | * in. For this algorithm, if we can schedule the same number of packets for | |
2085 | * each possible scheduling opportunity (each microframe), we will do so. The | |
2086 | * remaining number of packets will be saved to be transmitted in the gaps in | |
2087 | * the next interval's scheduling sequence. | |
2088 | * | |
2089 | * As we move those remaining packets to be scheduled with interval 2 packets, | |
2090 | * we have to double the number of remaining packets to transmit. This is | |
2091 | * because the intervals are actually powers of 2, and we would be transmitting | |
2092 | * the previous interval's packets twice in this interval. We also have to be | |
2093 | * sure that when we look at the largest max packet size for this interval, we | |
2094 | * also look at the largest max packet size for the remaining packets and take | |
2095 | * the greater of the two. | |
2096 | * | |
2097 | * The algorithm continues to evenly distribute packets in each scheduling | |
2098 | * opportunity, and push the remaining packets out, until we get to the last | |
2099 | * interval. Then those packets and their associated overhead are just added | |
2100 | * to the bandwidth used. | |
2e27980e SS |
2101 | */ |
2102 | static int xhci_check_bw_table(struct xhci_hcd *xhci, | |
2103 | struct xhci_virt_device *virt_dev, | |
2104 | int old_active_eps) | |
2105 | { | |
c29eea62 SS |
2106 | unsigned int bw_reserved; |
2107 | unsigned int max_bandwidth; | |
2108 | unsigned int bw_used; | |
2109 | unsigned int block_size; | |
2110 | struct xhci_interval_bw_table *bw_table; | |
2111 | unsigned int packet_size = 0; | |
2112 | unsigned int overhead = 0; | |
2113 | unsigned int packets_transmitted = 0; | |
2114 | unsigned int packets_remaining = 0; | |
2115 | unsigned int i; | |
2116 | ||
0caf6b33 | 2117 | if (virt_dev->udev->speed >= USB_SPEED_SUPER) |
2b698999 SS |
2118 | return xhci_check_ss_bw(xhci, virt_dev); |
2119 | ||
c29eea62 SS |
2120 | if (virt_dev->udev->speed == USB_SPEED_HIGH) { |
2121 | max_bandwidth = HS_BW_LIMIT; | |
2122 | /* Convert percent of bus BW reserved to blocks reserved */ | |
2123 | bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100); | |
2124 | } else { | |
2125 | max_bandwidth = FS_BW_LIMIT; | |
2126 | bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100); | |
2127 | } | |
2128 | ||
2129 | bw_table = virt_dev->bw_table; | |
2130 | /* We need to translate the max packet size and max ESIT payloads into | |
2131 | * the units the hardware uses. | |
2132 | */ | |
2133 | block_size = xhci_get_block_size(virt_dev->udev); | |
2134 | ||
2135 | /* If we are manipulating a LS/FS device under a HS hub, double check | |
2136 | * that the HS bus has enough bandwidth if we are activing a new TT. | |
2137 | */ | |
2138 | if (virt_dev->tt_info) { | |
4bdfe4c3 XR |
2139 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2140 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2141 | virt_dev->real_port); |
2142 | if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) { | |
2143 | xhci_warn(xhci, "Not enough bandwidth on HS bus for " | |
2144 | "newly activated TT.\n"); | |
2145 | return -ENOMEM; | |
2146 | } | |
4bdfe4c3 XR |
2147 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2148 | "Recalculating BW for TT slot %u port %u", | |
c29eea62 SS |
2149 | virt_dev->tt_info->slot_id, |
2150 | virt_dev->tt_info->ttport); | |
2151 | } else { | |
4bdfe4c3 XR |
2152 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2153 | "Recalculating BW for rootport %u", | |
c29eea62 SS |
2154 | virt_dev->real_port); |
2155 | } | |
2156 | ||
2157 | /* Add in how much bandwidth will be used for interval zero, or the | |
2158 | * rounded max ESIT payload + number of packets * largest overhead. | |
2159 | */ | |
2160 | bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) + | |
2161 | bw_table->interval_bw[0].num_packets * | |
2162 | xhci_get_largest_overhead(&bw_table->interval_bw[0]); | |
2163 | ||
2164 | for (i = 1; i < XHCI_MAX_INTERVAL; i++) { | |
2165 | unsigned int bw_added; | |
2166 | unsigned int largest_mps; | |
2167 | unsigned int interval_overhead; | |
2168 | ||
2169 | /* | |
2170 | * How many packets could we transmit in this interval? | |
2171 | * If packets didn't fit in the previous interval, we will need | |
2172 | * to transmit that many packets twice within this interval. | |
2173 | */ | |
2174 | packets_remaining = 2 * packets_remaining + | |
2175 | bw_table->interval_bw[i].num_packets; | |
2176 | ||
2177 | /* Find the largest max packet size of this or the previous | |
2178 | * interval. | |
2179 | */ | |
2180 | if (list_empty(&bw_table->interval_bw[i].endpoints)) | |
2181 | largest_mps = 0; | |
2182 | else { | |
2183 | struct xhci_virt_ep *virt_ep; | |
2184 | struct list_head *ep_entry; | |
2185 | ||
2186 | ep_entry = bw_table->interval_bw[i].endpoints.next; | |
2187 | virt_ep = list_entry(ep_entry, | |
2188 | struct xhci_virt_ep, bw_endpoint_list); | |
2189 | /* Convert to blocks, rounding up */ | |
2190 | largest_mps = DIV_ROUND_UP( | |
2191 | virt_ep->bw_info.max_packet_size, | |
2192 | block_size); | |
2193 | } | |
2194 | if (largest_mps > packet_size) | |
2195 | packet_size = largest_mps; | |
2196 | ||
2197 | /* Use the larger overhead of this or the previous interval. */ | |
2198 | interval_overhead = xhci_get_largest_overhead( | |
2199 | &bw_table->interval_bw[i]); | |
2200 | if (interval_overhead > overhead) | |
2201 | overhead = interval_overhead; | |
2202 | ||
2203 | /* How many packets can we evenly distribute across | |
2204 | * (1 << (i + 1)) possible scheduling opportunities? | |
2205 | */ | |
2206 | packets_transmitted = packets_remaining >> (i + 1); | |
2207 | ||
2208 | /* Add in the bandwidth used for those scheduled packets */ | |
2209 | bw_added = packets_transmitted * (overhead + packet_size); | |
2210 | ||
2211 | /* How many packets do we have remaining to transmit? */ | |
2212 | packets_remaining = packets_remaining % (1 << (i + 1)); | |
2213 | ||
2214 | /* What largest max packet size should those packets have? */ | |
2215 | /* If we've transmitted all packets, don't carry over the | |
2216 | * largest packet size. | |
2217 | */ | |
2218 | if (packets_remaining == 0) { | |
2219 | packet_size = 0; | |
2220 | overhead = 0; | |
2221 | } else if (packets_transmitted > 0) { | |
2222 | /* Otherwise if we do have remaining packets, and we've | |
2223 | * scheduled some packets in this interval, take the | |
2224 | * largest max packet size from endpoints with this | |
2225 | * interval. | |
2226 | */ | |
2227 | packet_size = largest_mps; | |
2228 | overhead = interval_overhead; | |
2229 | } | |
2230 | /* Otherwise carry over packet_size and overhead from the last | |
2231 | * time we had a remainder. | |
2232 | */ | |
2233 | bw_used += bw_added; | |
2234 | if (bw_used > max_bandwidth) { | |
2235 | xhci_warn(xhci, "Not enough bandwidth. " | |
2236 | "Proposed: %u, Max: %u\n", | |
2237 | bw_used, max_bandwidth); | |
2238 | return -ENOMEM; | |
2239 | } | |
2240 | } | |
2241 | /* | |
2242 | * Ok, we know we have some packets left over after even-handedly | |
2243 | * scheduling interval 15. We don't know which microframes they will | |
2244 | * fit into, so we over-schedule and say they will be scheduled every | |
2245 | * microframe. | |
2246 | */ | |
2247 | if (packets_remaining > 0) | |
2248 | bw_used += overhead + packet_size; | |
2249 | ||
2250 | if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) { | |
2251 | unsigned int port_index = virt_dev->real_port - 1; | |
2252 | ||
2253 | /* OK, we're manipulating a HS device attached to a | |
2254 | * root port bandwidth domain. Include the number of active TTs | |
2255 | * in the bandwidth used. | |
2256 | */ | |
2257 | bw_used += TT_HS_OVERHEAD * | |
2258 | xhci->rh_bw[port_index].num_active_tts; | |
2259 | } | |
2260 | ||
4bdfe4c3 XR |
2261 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2262 | "Final bandwidth: %u, Limit: %u, Reserved: %u, " | |
2263 | "Available: %u " "percent", | |
c29eea62 SS |
2264 | bw_used, max_bandwidth, bw_reserved, |
2265 | (max_bandwidth - bw_used - bw_reserved) * 100 / | |
2266 | max_bandwidth); | |
2267 | ||
2268 | bw_used += bw_reserved; | |
2269 | if (bw_used > max_bandwidth) { | |
2270 | xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n", | |
2271 | bw_used, max_bandwidth); | |
2272 | return -ENOMEM; | |
2273 | } | |
2274 | ||
2275 | bw_table->bw_used = bw_used; | |
2e27980e SS |
2276 | return 0; |
2277 | } | |
2278 | ||
2279 | static bool xhci_is_async_ep(unsigned int ep_type) | |
2280 | { | |
2281 | return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP && | |
2282 | ep_type != ISOC_IN_EP && | |
2283 | ep_type != INT_IN_EP); | |
2284 | } | |
2285 | ||
2b698999 SS |
2286 | static bool xhci_is_sync_in_ep(unsigned int ep_type) |
2287 | { | |
392a07ae | 2288 | return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP); |
2b698999 SS |
2289 | } |
2290 | ||
2291 | static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw) | |
2292 | { | |
2293 | unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK); | |
2294 | ||
2295 | if (ep_bw->ep_interval == 0) | |
2296 | return SS_OVERHEAD_BURST + | |
2297 | (ep_bw->mult * ep_bw->num_packets * | |
2298 | (SS_OVERHEAD + mps)); | |
2299 | return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets * | |
2300 | (SS_OVERHEAD + mps + SS_OVERHEAD_BURST), | |
2301 | 1 << ep_bw->ep_interval); | |
2302 | ||
2303 | } | |
2304 | ||
3969384c | 2305 | static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, |
2e27980e SS |
2306 | struct xhci_bw_info *ep_bw, |
2307 | struct xhci_interval_bw_table *bw_table, | |
2308 | struct usb_device *udev, | |
2309 | struct xhci_virt_ep *virt_ep, | |
2310 | struct xhci_tt_bw_info *tt_info) | |
2311 | { | |
2312 | struct xhci_interval_bw *interval_bw; | |
2313 | int normalized_interval; | |
2314 | ||
2b698999 | 2315 | if (xhci_is_async_ep(ep_bw->type)) |
2e27980e SS |
2316 | return; |
2317 | ||
0caf6b33 | 2318 | if (udev->speed >= USB_SPEED_SUPER) { |
2b698999 SS |
2319 | if (xhci_is_sync_in_ep(ep_bw->type)) |
2320 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in -= | |
2321 | xhci_get_ss_bw_consumed(ep_bw); | |
2322 | else | |
2323 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out -= | |
2324 | xhci_get_ss_bw_consumed(ep_bw); | |
2325 | return; | |
2326 | } | |
2327 | ||
2328 | /* SuperSpeed endpoints never get added to intervals in the table, so | |
2329 | * this check is only valid for HS/FS/LS devices. | |
2330 | */ | |
2331 | if (list_empty(&virt_ep->bw_endpoint_list)) | |
2332 | return; | |
2e27980e SS |
2333 | /* For LS/FS devices, we need to translate the interval expressed in |
2334 | * microframes to frames. | |
2335 | */ | |
2336 | if (udev->speed == USB_SPEED_HIGH) | |
2337 | normalized_interval = ep_bw->ep_interval; | |
2338 | else | |
2339 | normalized_interval = ep_bw->ep_interval - 3; | |
2340 | ||
2341 | if (normalized_interval == 0) | |
2342 | bw_table->interval0_esit_payload -= ep_bw->max_esit_payload; | |
2343 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2344 | interval_bw->num_packets -= ep_bw->num_packets; | |
2345 | switch (udev->speed) { | |
2346 | case USB_SPEED_LOW: | |
2347 | interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1; | |
2348 | break; | |
2349 | case USB_SPEED_FULL: | |
2350 | interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1; | |
2351 | break; | |
2352 | case USB_SPEED_HIGH: | |
2353 | interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1; | |
2354 | break; | |
2355 | case USB_SPEED_SUPER: | |
0caf6b33 | 2356 | case USB_SPEED_SUPER_PLUS: |
2e27980e SS |
2357 | case USB_SPEED_UNKNOWN: |
2358 | case USB_SPEED_WIRELESS: | |
2359 | /* Should never happen because only LS/FS/HS endpoints will get | |
2360 | * added to the endpoint list. | |
2361 | */ | |
2362 | return; | |
2363 | } | |
2364 | if (tt_info) | |
2365 | tt_info->active_eps -= 1; | |
2366 | list_del_init(&virt_ep->bw_endpoint_list); | |
2367 | } | |
2368 | ||
2369 | static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci, | |
2370 | struct xhci_bw_info *ep_bw, | |
2371 | struct xhci_interval_bw_table *bw_table, | |
2372 | struct usb_device *udev, | |
2373 | struct xhci_virt_ep *virt_ep, | |
2374 | struct xhci_tt_bw_info *tt_info) | |
2375 | { | |
2376 | struct xhci_interval_bw *interval_bw; | |
2377 | struct xhci_virt_ep *smaller_ep; | |
2378 | int normalized_interval; | |
2379 | ||
2380 | if (xhci_is_async_ep(ep_bw->type)) | |
2381 | return; | |
2382 | ||
2b698999 SS |
2383 | if (udev->speed == USB_SPEED_SUPER) { |
2384 | if (xhci_is_sync_in_ep(ep_bw->type)) | |
2385 | xhci->devs[udev->slot_id]->bw_table->ss_bw_in += | |
2386 | xhci_get_ss_bw_consumed(ep_bw); | |
2387 | else | |
2388 | xhci->devs[udev->slot_id]->bw_table->ss_bw_out += | |
2389 | xhci_get_ss_bw_consumed(ep_bw); | |
2390 | return; | |
2391 | } | |
2392 | ||
2e27980e SS |
2393 | /* For LS/FS devices, we need to translate the interval expressed in |
2394 | * microframes to frames. | |
2395 | */ | |
2396 | if (udev->speed == USB_SPEED_HIGH) | |
2397 | normalized_interval = ep_bw->ep_interval; | |
2398 | else | |
2399 | normalized_interval = ep_bw->ep_interval - 3; | |
2400 | ||
2401 | if (normalized_interval == 0) | |
2402 | bw_table->interval0_esit_payload += ep_bw->max_esit_payload; | |
2403 | interval_bw = &bw_table->interval_bw[normalized_interval]; | |
2404 | interval_bw->num_packets += ep_bw->num_packets; | |
2405 | switch (udev->speed) { | |
2406 | case USB_SPEED_LOW: | |
2407 | interval_bw->overhead[LS_OVERHEAD_TYPE] += 1; | |
2408 | break; | |
2409 | case USB_SPEED_FULL: | |
2410 | interval_bw->overhead[FS_OVERHEAD_TYPE] += 1; | |
2411 | break; | |
2412 | case USB_SPEED_HIGH: | |
2413 | interval_bw->overhead[HS_OVERHEAD_TYPE] += 1; | |
2414 | break; | |
2415 | case USB_SPEED_SUPER: | |
0caf6b33 | 2416 | case USB_SPEED_SUPER_PLUS: |
2e27980e SS |
2417 | case USB_SPEED_UNKNOWN: |
2418 | case USB_SPEED_WIRELESS: | |
2419 | /* Should never happen because only LS/FS/HS endpoints will get | |
2420 | * added to the endpoint list. | |
2421 | */ | |
2422 | return; | |
2423 | } | |
2424 | ||
2425 | if (tt_info) | |
2426 | tt_info->active_eps += 1; | |
2427 | /* Insert the endpoint into the list, largest max packet size first. */ | |
2428 | list_for_each_entry(smaller_ep, &interval_bw->endpoints, | |
2429 | bw_endpoint_list) { | |
2430 | if (ep_bw->max_packet_size >= | |
2431 | smaller_ep->bw_info.max_packet_size) { | |
2432 | /* Add the new ep before the smaller endpoint */ | |
2433 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2434 | &smaller_ep->bw_endpoint_list); | |
2435 | return; | |
2436 | } | |
2437 | } | |
2438 | /* Add the new endpoint at the end of the list. */ | |
2439 | list_add_tail(&virt_ep->bw_endpoint_list, | |
2440 | &interval_bw->endpoints); | |
2441 | } | |
2442 | ||
2443 | void xhci_update_tt_active_eps(struct xhci_hcd *xhci, | |
2444 | struct xhci_virt_device *virt_dev, | |
2445 | int old_active_eps) | |
2446 | { | |
2447 | struct xhci_root_port_bw_info *rh_bw_info; | |
2448 | if (!virt_dev->tt_info) | |
2449 | return; | |
2450 | ||
2451 | rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1]; | |
2452 | if (old_active_eps == 0 && | |
2453 | virt_dev->tt_info->active_eps != 0) { | |
2454 | rh_bw_info->num_active_tts += 1; | |
c29eea62 | 2455 | rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD; |
2e27980e SS |
2456 | } else if (old_active_eps != 0 && |
2457 | virt_dev->tt_info->active_eps == 0) { | |
2458 | rh_bw_info->num_active_tts -= 1; | |
c29eea62 | 2459 | rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD; |
2e27980e SS |
2460 | } |
2461 | } | |
2462 | ||
2463 | static int xhci_reserve_bandwidth(struct xhci_hcd *xhci, | |
2464 | struct xhci_virt_device *virt_dev, | |
2465 | struct xhci_container_ctx *in_ctx) | |
2466 | { | |
2467 | struct xhci_bw_info ep_bw_info[31]; | |
2468 | int i; | |
2469 | struct xhci_input_control_ctx *ctrl_ctx; | |
2470 | int old_active_eps = 0; | |
2471 | ||
2e27980e SS |
2472 | if (virt_dev->tt_info) |
2473 | old_active_eps = virt_dev->tt_info->active_eps; | |
2474 | ||
4daf9df5 | 2475 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
2476 | if (!ctrl_ctx) { |
2477 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2478 | __func__); | |
2479 | return -ENOMEM; | |
2480 | } | |
2e27980e SS |
2481 | |
2482 | for (i = 0; i < 31; i++) { | |
2483 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2484 | continue; | |
2485 | ||
2486 | /* Make a copy of the BW info in case we need to revert this */ | |
2487 | memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info, | |
2488 | sizeof(ep_bw_info[i])); | |
2489 | /* Drop the endpoint from the interval table if the endpoint is | |
2490 | * being dropped or changed. | |
2491 | */ | |
2492 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2493 | xhci_drop_ep_from_interval_table(xhci, | |
2494 | &virt_dev->eps[i].bw_info, | |
2495 | virt_dev->bw_table, | |
2496 | virt_dev->udev, | |
2497 | &virt_dev->eps[i], | |
2498 | virt_dev->tt_info); | |
2499 | } | |
2500 | /* Overwrite the information stored in the endpoints' bw_info */ | |
2501 | xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev); | |
2502 | for (i = 0; i < 31; i++) { | |
2503 | /* Add any changed or added endpoints to the interval table */ | |
2504 | if (EP_IS_ADDED(ctrl_ctx, i)) | |
2505 | xhci_add_ep_to_interval_table(xhci, | |
2506 | &virt_dev->eps[i].bw_info, | |
2507 | virt_dev->bw_table, | |
2508 | virt_dev->udev, | |
2509 | &virt_dev->eps[i], | |
2510 | virt_dev->tt_info); | |
2511 | } | |
2512 | ||
2513 | if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) { | |
2514 | /* Ok, this fits in the bandwidth we have. | |
2515 | * Update the number of active TTs. | |
2516 | */ | |
2517 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
2518 | return 0; | |
2519 | } | |
2520 | ||
2521 | /* We don't have enough bandwidth for this, revert the stored info. */ | |
2522 | for (i = 0; i < 31; i++) { | |
2523 | if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i)) | |
2524 | continue; | |
2525 | ||
2526 | /* Drop the new copies of any added or changed endpoints from | |
2527 | * the interval table. | |
2528 | */ | |
2529 | if (EP_IS_ADDED(ctrl_ctx, i)) { | |
2530 | xhci_drop_ep_from_interval_table(xhci, | |
2531 | &virt_dev->eps[i].bw_info, | |
2532 | virt_dev->bw_table, | |
2533 | virt_dev->udev, | |
2534 | &virt_dev->eps[i], | |
2535 | virt_dev->tt_info); | |
2536 | } | |
2537 | /* Revert the endpoint back to its old information */ | |
2538 | memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i], | |
2539 | sizeof(ep_bw_info[i])); | |
2540 | /* Add any changed or dropped endpoints back into the table */ | |
2541 | if (EP_IS_DROPPED(ctrl_ctx, i)) | |
2542 | xhci_add_ep_to_interval_table(xhci, | |
2543 | &virt_dev->eps[i].bw_info, | |
2544 | virt_dev->bw_table, | |
2545 | virt_dev->udev, | |
2546 | &virt_dev->eps[i], | |
2547 | virt_dev->tt_info); | |
2548 | } | |
2549 | return -ENOMEM; | |
2550 | } | |
2551 | ||
2552 | ||
f2217e8e SS |
2553 | /* Issue a configure endpoint command or evaluate context command |
2554 | * and wait for it to finish. | |
2555 | */ | |
2556 | static int xhci_configure_endpoint(struct xhci_hcd *xhci, | |
913a8a34 SS |
2557 | struct usb_device *udev, |
2558 | struct xhci_command *command, | |
2559 | bool ctx_change, bool must_succeed) | |
f2217e8e SS |
2560 | { |
2561 | int ret; | |
f2217e8e | 2562 | unsigned long flags; |
92f8e767 | 2563 | struct xhci_input_control_ctx *ctrl_ctx; |
913a8a34 | 2564 | struct xhci_virt_device *virt_dev; |
e3a78ff0 | 2565 | struct xhci_slot_ctx *slot_ctx; |
ddba5cd0 MN |
2566 | |
2567 | if (!command) | |
2568 | return -EINVAL; | |
f2217e8e SS |
2569 | |
2570 | spin_lock_irqsave(&xhci->lock, flags); | |
d9f11ba9 MN |
2571 | |
2572 | if (xhci->xhc_state & XHCI_STATE_DYING) { | |
2573 | spin_unlock_irqrestore(&xhci->lock, flags); | |
2574 | return -ESHUTDOWN; | |
2575 | } | |
2576 | ||
913a8a34 | 2577 | virt_dev = xhci->devs[udev->slot_id]; |
750645f8 | 2578 | |
4daf9df5 | 2579 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 | 2580 | if (!ctrl_ctx) { |
1f21569c | 2581 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
2582 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
2583 | __func__); | |
2584 | return -ENOMEM; | |
2585 | } | |
2cf95c18 | 2586 | |
750645f8 | 2587 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) && |
92f8e767 | 2588 | xhci_reserve_host_resources(xhci, ctrl_ctx)) { |
750645f8 SS |
2589 | spin_unlock_irqrestore(&xhci->lock, flags); |
2590 | xhci_warn(xhci, "Not enough host resources, " | |
2591 | "active endpoint contexts = %u\n", | |
2592 | xhci->num_active_eps); | |
2593 | return -ENOMEM; | |
2594 | } | |
2e27980e | 2595 | if ((xhci->quirks & XHCI_SW_BW_CHECKING) && |
ddba5cd0 | 2596 | xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) { |
2e27980e | 2597 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) |
92f8e767 | 2598 | xhci_free_host_resources(xhci, ctrl_ctx); |
2e27980e SS |
2599 | spin_unlock_irqrestore(&xhci->lock, flags); |
2600 | xhci_warn(xhci, "Not enough bandwidth\n"); | |
2601 | return -ENOMEM; | |
2602 | } | |
750645f8 | 2603 | |
e3a78ff0 MN |
2604 | slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx); |
2605 | trace_xhci_configure_endpoint(slot_ctx); | |
2606 | ||
f2217e8e | 2607 | if (!ctx_change) |
ddba5cd0 MN |
2608 | ret = xhci_queue_configure_endpoint(xhci, command, |
2609 | command->in_ctx->dma, | |
913a8a34 | 2610 | udev->slot_id, must_succeed); |
f2217e8e | 2611 | else |
ddba5cd0 MN |
2612 | ret = xhci_queue_evaluate_context(xhci, command, |
2613 | command->in_ctx->dma, | |
4b266541 | 2614 | udev->slot_id, must_succeed); |
f2217e8e | 2615 | if (ret < 0) { |
2cf95c18 | 2616 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) |
92f8e767 | 2617 | xhci_free_host_resources(xhci, ctrl_ctx); |
f2217e8e | 2618 | spin_unlock_irqrestore(&xhci->lock, flags); |
3a7fa5be XR |
2619 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
2620 | "FIXME allocate a new ring segment"); | |
f2217e8e SS |
2621 | return -ENOMEM; |
2622 | } | |
2623 | xhci_ring_cmd_db(xhci); | |
2624 | spin_unlock_irqrestore(&xhci->lock, flags); | |
2625 | ||
2626 | /* Wait for the configure endpoint command to complete */ | |
c311e391 | 2627 | wait_for_completion(command->completion); |
f2217e8e SS |
2628 | |
2629 | if (!ctx_change) | |
ddba5cd0 MN |
2630 | ret = xhci_configure_endpoint_result(xhci, udev, |
2631 | &command->status); | |
2cf95c18 | 2632 | else |
ddba5cd0 MN |
2633 | ret = xhci_evaluate_context_result(xhci, udev, |
2634 | &command->status); | |
2cf95c18 SS |
2635 | |
2636 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
2637 | spin_lock_irqsave(&xhci->lock, flags); | |
2638 | /* If the command failed, remove the reserved resources. | |
2639 | * Otherwise, clean up the estimate to include dropped eps. | |
2640 | */ | |
2641 | if (ret) | |
92f8e767 | 2642 | xhci_free_host_resources(xhci, ctrl_ctx); |
2cf95c18 | 2643 | else |
92f8e767 | 2644 | xhci_finish_resource_reservation(xhci, ctrl_ctx); |
2cf95c18 SS |
2645 | spin_unlock_irqrestore(&xhci->lock, flags); |
2646 | } | |
2647 | return ret; | |
f2217e8e SS |
2648 | } |
2649 | ||
df613834 HG |
2650 | static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci, |
2651 | struct xhci_virt_device *vdev, int i) | |
2652 | { | |
2653 | struct xhci_virt_ep *ep = &vdev->eps[i]; | |
2654 | ||
2655 | if (ep->ep_state & EP_HAS_STREAMS) { | |
2656 | xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n", | |
2657 | xhci_get_endpoint_address(i)); | |
2658 | xhci_free_stream_info(xhci, ep->stream_info); | |
2659 | ep->stream_info = NULL; | |
2660 | ep->ep_state &= ~EP_HAS_STREAMS; | |
2661 | } | |
2662 | } | |
2663 | ||
f88ba78d SS |
2664 | /* Called after one or more calls to xhci_add_endpoint() or |
2665 | * xhci_drop_endpoint(). If this call fails, the USB core is expected | |
2666 | * to call xhci_reset_bandwidth(). | |
2667 | * | |
2668 | * Since we are in the middle of changing either configuration or | |
2669 | * installing a new alt setting, the USB core won't allow URBs to be | |
2670 | * enqueued for any endpoint on the old config or interface. Nothing | |
2671 | * else should be touching the xhci->devs[slot_id] structure, so we | |
2672 | * don't need to take the xhci->lock for manipulating that. | |
2673 | */ | |
3969384c | 2674 | static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) |
f94e0186 SS |
2675 | { |
2676 | int i; | |
2677 | int ret = 0; | |
f94e0186 SS |
2678 | struct xhci_hcd *xhci; |
2679 | struct xhci_virt_device *virt_dev; | |
d115b048 JY |
2680 | struct xhci_input_control_ctx *ctrl_ctx; |
2681 | struct xhci_slot_ctx *slot_ctx; | |
ddba5cd0 | 2682 | struct xhci_command *command; |
f94e0186 | 2683 | |
64927730 | 2684 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2685 | if (ret <= 0) |
2686 | return ret; | |
2687 | xhci = hcd_to_xhci(hcd); | |
98d74f9c MN |
2688 | if ((xhci->xhc_state & XHCI_STATE_DYING) || |
2689 | (xhci->xhc_state & XHCI_STATE_REMOVING)) | |
fe6c6c13 | 2690 | return -ENODEV; |
f94e0186 | 2691 | |
700e2052 | 2692 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2693 | virt_dev = xhci->devs[udev->slot_id]; |
2694 | ||
ddba5cd0 MN |
2695 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); |
2696 | if (!command) | |
2697 | return -ENOMEM; | |
2698 | ||
2699 | command->in_ctx = virt_dev->in_ctx; | |
2700 | ||
f94e0186 | 2701 | /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */ |
4daf9df5 | 2702 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 SS |
2703 | if (!ctrl_ctx) { |
2704 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2705 | __func__); | |
ddba5cd0 MN |
2706 | ret = -ENOMEM; |
2707 | goto command_cleanup; | |
92f8e767 | 2708 | } |
28ccd296 ME |
2709 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
2710 | ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG); | |
2711 | ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG)); | |
2dc37539 SS |
2712 | |
2713 | /* Don't issue the command if there's no endpoints to update. */ | |
2714 | if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) && | |
ddba5cd0 MN |
2715 | ctrl_ctx->drop_flags == 0) { |
2716 | ret = 0; | |
2717 | goto command_cleanup; | |
2718 | } | |
d6759133 | 2719 | /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */ |
d115b048 | 2720 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
d6759133 JW |
2721 | for (i = 31; i >= 1; i--) { |
2722 | __le32 le32 = cpu_to_le32(BIT(i)); | |
2723 | ||
2724 | if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32)) | |
2725 | || (ctrl_ctx->add_flags & le32) || i == 1) { | |
2726 | slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); | |
2727 | slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i)); | |
2728 | break; | |
2729 | } | |
2730 | } | |
f94e0186 | 2731 | |
ddba5cd0 | 2732 | ret = xhci_configure_endpoint(xhci, udev, command, |
913a8a34 | 2733 | false, false); |
ddba5cd0 | 2734 | if (ret) |
f94e0186 | 2735 | /* Callee should call reset_bandwidth() */ |
ddba5cd0 | 2736 | goto command_cleanup; |
f94e0186 | 2737 | |
834cb0fc | 2738 | /* Free any rings that were dropped, but not changed. */ |
98871e94 | 2739 | for (i = 1; i < 31; i++) { |
4819fef5 | 2740 | if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) && |
df613834 | 2741 | !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) { |
c5628a2a | 2742 | xhci_free_endpoint_ring(xhci, virt_dev, i); |
df613834 HG |
2743 | xhci_check_bw_drop_ep_streams(xhci, virt_dev, i); |
2744 | } | |
834cb0fc | 2745 | } |
d115b048 | 2746 | xhci_zero_in_ctx(xhci, virt_dev); |
834cb0fc SS |
2747 | /* |
2748 | * Install any rings for completely new endpoints or changed endpoints, | |
c5628a2a | 2749 | * and free any old rings from changed endpoints. |
834cb0fc | 2750 | */ |
98871e94 | 2751 | for (i = 1; i < 31; i++) { |
74f9fe21 SS |
2752 | if (!virt_dev->eps[i].new_ring) |
2753 | continue; | |
c5628a2a | 2754 | /* Only free the old ring if it exists. |
74f9fe21 SS |
2755 | * It may not if this is the first add of an endpoint. |
2756 | */ | |
2757 | if (virt_dev->eps[i].ring) { | |
c5628a2a | 2758 | xhci_free_endpoint_ring(xhci, virt_dev, i); |
f94e0186 | 2759 | } |
df613834 | 2760 | xhci_check_bw_drop_ep_streams(xhci, virt_dev, i); |
74f9fe21 SS |
2761 | virt_dev->eps[i].ring = virt_dev->eps[i].new_ring; |
2762 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 | 2763 | } |
ddba5cd0 MN |
2764 | command_cleanup: |
2765 | kfree(command->completion); | |
2766 | kfree(command); | |
f94e0186 | 2767 | |
f94e0186 SS |
2768 | return ret; |
2769 | } | |
2770 | ||
3969384c | 2771 | static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev) |
f94e0186 | 2772 | { |
f94e0186 SS |
2773 | struct xhci_hcd *xhci; |
2774 | struct xhci_virt_device *virt_dev; | |
2775 | int i, ret; | |
2776 | ||
64927730 | 2777 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
f94e0186 SS |
2778 | if (ret <= 0) |
2779 | return; | |
2780 | xhci = hcd_to_xhci(hcd); | |
2781 | ||
700e2052 | 2782 | xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev); |
f94e0186 SS |
2783 | virt_dev = xhci->devs[udev->slot_id]; |
2784 | /* Free any rings allocated for added endpoints */ | |
98871e94 | 2785 | for (i = 0; i < 31; i++) { |
63a0d9ab | 2786 | if (virt_dev->eps[i].new_ring) { |
02b6fdc2 | 2787 | xhci_debugfs_remove_endpoint(xhci, virt_dev, i); |
63a0d9ab SS |
2788 | xhci_ring_free(xhci, virt_dev->eps[i].new_ring); |
2789 | virt_dev->eps[i].new_ring = NULL; | |
f94e0186 SS |
2790 | } |
2791 | } | |
d115b048 | 2792 | xhci_zero_in_ctx(xhci, virt_dev); |
f94e0186 SS |
2793 | } |
2794 | ||
5270b951 | 2795 | static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci, |
913a8a34 SS |
2796 | struct xhci_container_ctx *in_ctx, |
2797 | struct xhci_container_ctx *out_ctx, | |
92f8e767 | 2798 | struct xhci_input_control_ctx *ctrl_ctx, |
913a8a34 | 2799 | u32 add_flags, u32 drop_flags) |
5270b951 | 2800 | { |
28ccd296 ME |
2801 | ctrl_ctx->add_flags = cpu_to_le32(add_flags); |
2802 | ctrl_ctx->drop_flags = cpu_to_le32(drop_flags); | |
913a8a34 | 2803 | xhci_slot_copy(xhci, in_ctx, out_ctx); |
28ccd296 | 2804 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
5270b951 SS |
2805 | } |
2806 | ||
8212a49d | 2807 | static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci, |
ac9d8fe7 SS |
2808 | unsigned int slot_id, unsigned int ep_index, |
2809 | struct xhci_dequeue_state *deq_state) | |
2810 | { | |
92f8e767 | 2811 | struct xhci_input_control_ctx *ctrl_ctx; |
ac9d8fe7 | 2812 | struct xhci_container_ctx *in_ctx; |
ac9d8fe7 SS |
2813 | struct xhci_ep_ctx *ep_ctx; |
2814 | u32 added_ctxs; | |
2815 | dma_addr_t addr; | |
2816 | ||
92f8e767 | 2817 | in_ctx = xhci->devs[slot_id]->in_ctx; |
4daf9df5 | 2818 | ctrl_ctx = xhci_get_input_control_ctx(in_ctx); |
92f8e767 SS |
2819 | if (!ctrl_ctx) { |
2820 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
2821 | __func__); | |
2822 | return; | |
2823 | } | |
2824 | ||
913a8a34 SS |
2825 | xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx, |
2826 | xhci->devs[slot_id]->out_ctx, ep_index); | |
ac9d8fe7 SS |
2827 | ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index); |
2828 | addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg, | |
2829 | deq_state->new_deq_ptr); | |
2830 | if (addr == 0) { | |
2831 | xhci_warn(xhci, "WARN Cannot submit config ep after " | |
2832 | "reset ep command\n"); | |
2833 | xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n", | |
2834 | deq_state->new_deq_seg, | |
2835 | deq_state->new_deq_ptr); | |
2836 | return; | |
2837 | } | |
28ccd296 | 2838 | ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state); |
ac9d8fe7 | 2839 | |
ac9d8fe7 | 2840 | added_ctxs = xhci_get_endpoint_flag_from_index(ep_index); |
913a8a34 | 2841 | xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx, |
92f8e767 SS |
2842 | xhci->devs[slot_id]->out_ctx, ctrl_ctx, |
2843 | added_ctxs, added_ctxs); | |
ac9d8fe7 SS |
2844 | } |
2845 | ||
d36374fd MN |
2846 | void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index, |
2847 | unsigned int stream_id, struct xhci_td *td) | |
82d1009f SS |
2848 | { |
2849 | struct xhci_dequeue_state deq_state; | |
63a0d9ab | 2850 | struct xhci_virt_ep *ep; |
d97b4f8d | 2851 | struct usb_device *udev = td->urb->dev; |
82d1009f | 2852 | |
a0254324 XR |
2853 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2854 | "Cleaning up stalled endpoint ring"); | |
63a0d9ab | 2855 | ep = &xhci->devs[udev->slot_id]->eps[ep_index]; |
82d1009f SS |
2856 | /* We need to move the HW's dequeue pointer past this TD, |
2857 | * or it will attempt to resend it on the next doorbell ring. | |
2858 | */ | |
2859 | xhci_find_new_dequeue_state(xhci, udev->slot_id, | |
d36374fd | 2860 | ep_index, stream_id, td, &deq_state); |
82d1009f | 2861 | |
365038d8 MN |
2862 | if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg) |
2863 | return; | |
2864 | ||
ac9d8fe7 SS |
2865 | /* HW with the reset endpoint quirk will use the saved dequeue state to |
2866 | * issue a configure endpoint command later. | |
2867 | */ | |
2868 | if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) { | |
a0254324 XR |
2869 | xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep, |
2870 | "Queueing new dequeue state"); | |
1e3452e3 | 2871 | xhci_queue_new_dequeue_state(xhci, udev->slot_id, |
8790736d | 2872 | ep_index, &deq_state); |
ac9d8fe7 SS |
2873 | } else { |
2874 | /* Better hope no one uses the input context between now and the | |
2875 | * reset endpoint completion! | |
e9df17eb SS |
2876 | * XXX: No idea how this hardware will react when stream rings |
2877 | * are enabled. | |
ac9d8fe7 | 2878 | */ |
4bdfe4c3 XR |
2879 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
2880 | "Setting up input context for " | |
2881 | "configure endpoint command"); | |
ac9d8fe7 SS |
2882 | xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id, |
2883 | ep_index, &deq_state); | |
2884 | } | |
82d1009f SS |
2885 | } |
2886 | ||
d0167ad2 | 2887 | /* Called when clearing halted device. The core should have sent the control |
8e71a322 | 2888 | * message to clear the device halt condition. The host side of the halt should |
d0167ad2 MN |
2889 | * already be cleared with a reset endpoint command issued when the STALL tx |
2890 | * event was received. | |
2891 | * | |
2892 | * Context: in_interrupt | |
a1587d97 | 2893 | */ |
8e71a322 | 2894 | |
3969384c | 2895 | static void xhci_endpoint_reset(struct usb_hcd *hcd, |
a1587d97 SS |
2896 | struct usb_host_endpoint *ep) |
2897 | { | |
2898 | struct xhci_hcd *xhci; | |
a1587d97 SS |
2899 | |
2900 | xhci = hcd_to_xhci(hcd); | |
ddba5cd0 | 2901 | |
c92bcfa7 | 2902 | /* |
d0167ad2 | 2903 | * We might need to implement the config ep cmd in xhci 4.8.1 note: |
8e71a322 MN |
2904 | * The Reset Endpoint Command may only be issued to endpoints in the |
2905 | * Halted state. If software wishes reset the Data Toggle or Sequence | |
2906 | * Number of an endpoint that isn't in the Halted state, then software | |
2907 | * may issue a Configure Endpoint Command with the Drop and Add bits set | |
2908 | * for the target endpoint. that is in the Stopped state. | |
c92bcfa7 | 2909 | */ |
a1587d97 | 2910 | |
d0167ad2 MN |
2911 | /* For now just print debug to follow the situation */ |
2912 | xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n", | |
2913 | ep->desc.bEndpointAddress); | |
a1587d97 SS |
2914 | } |
2915 | ||
8df75f42 SS |
2916 | static int xhci_check_streams_endpoint(struct xhci_hcd *xhci, |
2917 | struct usb_device *udev, struct usb_host_endpoint *ep, | |
2918 | unsigned int slot_id) | |
2919 | { | |
2920 | int ret; | |
2921 | unsigned int ep_index; | |
2922 | unsigned int ep_state; | |
2923 | ||
2924 | if (!ep) | |
2925 | return -EINVAL; | |
64927730 | 2926 | ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__); |
8df75f42 SS |
2927 | if (ret <= 0) |
2928 | return -EINVAL; | |
a3901538 | 2929 | if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) { |
8df75f42 SS |
2930 | xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion" |
2931 | " descriptor for ep 0x%x does not support streams\n", | |
2932 | ep->desc.bEndpointAddress); | |
2933 | return -EINVAL; | |
2934 | } | |
2935 | ||
2936 | ep_index = xhci_get_endpoint_index(&ep->desc); | |
2937 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
2938 | if (ep_state & EP_HAS_STREAMS || | |
2939 | ep_state & EP_GETTING_STREAMS) { | |
2940 | xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x " | |
2941 | "already has streams set up.\n", | |
2942 | ep->desc.bEndpointAddress); | |
2943 | xhci_warn(xhci, "Send email to xHCI maintainer and ask for " | |
2944 | "dynamic stream context array reallocation.\n"); | |
2945 | return -EINVAL; | |
2946 | } | |
2947 | if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) { | |
2948 | xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk " | |
2949 | "endpoint 0x%x; URBs are pending.\n", | |
2950 | ep->desc.bEndpointAddress); | |
2951 | return -EINVAL; | |
2952 | } | |
2953 | return 0; | |
2954 | } | |
2955 | ||
2956 | static void xhci_calculate_streams_entries(struct xhci_hcd *xhci, | |
2957 | unsigned int *num_streams, unsigned int *num_stream_ctxs) | |
2958 | { | |
2959 | unsigned int max_streams; | |
2960 | ||
2961 | /* The stream context array size must be a power of two */ | |
2962 | *num_stream_ctxs = roundup_pow_of_two(*num_streams); | |
2963 | /* | |
2964 | * Find out how many primary stream array entries the host controller | |
2965 | * supports. Later we may use secondary stream arrays (similar to 2nd | |
2966 | * level page entries), but that's an optional feature for xHCI host | |
2967 | * controllers. xHCs must support at least 4 stream IDs. | |
2968 | */ | |
2969 | max_streams = HCC_MAX_PSA(xhci->hcc_params); | |
2970 | if (*num_stream_ctxs > max_streams) { | |
2971 | xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n", | |
2972 | max_streams); | |
2973 | *num_stream_ctxs = max_streams; | |
2974 | *num_streams = max_streams; | |
2975 | } | |
2976 | } | |
2977 | ||
2978 | /* Returns an error code if one of the endpoint already has streams. | |
2979 | * This does not change any data structures, it only checks and gathers | |
2980 | * information. | |
2981 | */ | |
2982 | static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci, | |
2983 | struct usb_device *udev, | |
2984 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
2985 | unsigned int *num_streams, u32 *changed_ep_bitmask) | |
2986 | { | |
8df75f42 SS |
2987 | unsigned int max_streams; |
2988 | unsigned int endpoint_flag; | |
2989 | int i; | |
2990 | int ret; | |
2991 | ||
2992 | for (i = 0; i < num_eps; i++) { | |
2993 | ret = xhci_check_streams_endpoint(xhci, udev, | |
2994 | eps[i], udev->slot_id); | |
2995 | if (ret < 0) | |
2996 | return ret; | |
2997 | ||
18b7ede5 | 2998 | max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp); |
8df75f42 SS |
2999 | if (max_streams < (*num_streams - 1)) { |
3000 | xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n", | |
3001 | eps[i]->desc.bEndpointAddress, | |
3002 | max_streams); | |
3003 | *num_streams = max_streams+1; | |
3004 | } | |
3005 | ||
3006 | endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc); | |
3007 | if (*changed_ep_bitmask & endpoint_flag) | |
3008 | return -EINVAL; | |
3009 | *changed_ep_bitmask |= endpoint_flag; | |
3010 | } | |
3011 | return 0; | |
3012 | } | |
3013 | ||
3014 | static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci, | |
3015 | struct usb_device *udev, | |
3016 | struct usb_host_endpoint **eps, unsigned int num_eps) | |
3017 | { | |
3018 | u32 changed_ep_bitmask = 0; | |
3019 | unsigned int slot_id; | |
3020 | unsigned int ep_index; | |
3021 | unsigned int ep_state; | |
3022 | int i; | |
3023 | ||
3024 | slot_id = udev->slot_id; | |
3025 | if (!xhci->devs[slot_id]) | |
3026 | return 0; | |
3027 | ||
3028 | for (i = 0; i < num_eps; i++) { | |
3029 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3030 | ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state; | |
3031 | /* Are streams already being freed for the endpoint? */ | |
3032 | if (ep_state & EP_GETTING_NO_STREAMS) { | |
3033 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3034 | "endpoint 0x%x, " |
3035 | "streams are being disabled already\n", | |
8df75f42 SS |
3036 | eps[i]->desc.bEndpointAddress); |
3037 | return 0; | |
3038 | } | |
3039 | /* Are there actually any streams to free? */ | |
3040 | if (!(ep_state & EP_HAS_STREAMS) && | |
3041 | !(ep_state & EP_GETTING_STREAMS)) { | |
3042 | xhci_warn(xhci, "WARN Can't disable streams for " | |
03e64e96 JP |
3043 | "endpoint 0x%x, " |
3044 | "streams are already disabled!\n", | |
8df75f42 SS |
3045 | eps[i]->desc.bEndpointAddress); |
3046 | xhci_warn(xhci, "WARN xhci_free_streams() called " | |
3047 | "with non-streams endpoint\n"); | |
3048 | return 0; | |
3049 | } | |
3050 | changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc); | |
3051 | } | |
3052 | return changed_ep_bitmask; | |
3053 | } | |
3054 | ||
3055 | /* | |
c2a298d9 | 3056 | * The USB device drivers use this function (through the HCD interface in USB |
8df75f42 SS |
3057 | * core) to prepare a set of bulk endpoints to use streams. Streams are used to |
3058 | * coordinate mass storage command queueing across multiple endpoints (basically | |
3059 | * a stream ID == a task ID). | |
3060 | * | |
3061 | * Setting up streams involves allocating the same size stream context array | |
3062 | * for each endpoint and issuing a configure endpoint command for all endpoints. | |
3063 | * | |
3064 | * Don't allow the call to succeed if one endpoint only supports one stream | |
3065 | * (which means it doesn't support streams at all). | |
3066 | * | |
3067 | * Drivers may get less stream IDs than they asked for, if the host controller | |
3068 | * hardware or endpoints claim they can't support the number of requested | |
3069 | * stream IDs. | |
3070 | */ | |
3969384c | 3071 | static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, |
8df75f42 SS |
3072 | struct usb_host_endpoint **eps, unsigned int num_eps, |
3073 | unsigned int num_streams, gfp_t mem_flags) | |
3074 | { | |
3075 | int i, ret; | |
3076 | struct xhci_hcd *xhci; | |
3077 | struct xhci_virt_device *vdev; | |
3078 | struct xhci_command *config_cmd; | |
92f8e767 | 3079 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3080 | unsigned int ep_index; |
3081 | unsigned int num_stream_ctxs; | |
f9c589e1 | 3082 | unsigned int max_packet; |
8df75f42 SS |
3083 | unsigned long flags; |
3084 | u32 changed_ep_bitmask = 0; | |
3085 | ||
3086 | if (!eps) | |
3087 | return -EINVAL; | |
3088 | ||
3089 | /* Add one to the number of streams requested to account for | |
3090 | * stream 0 that is reserved for xHCI usage. | |
3091 | */ | |
3092 | num_streams += 1; | |
3093 | xhci = hcd_to_xhci(hcd); | |
3094 | xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n", | |
3095 | num_streams); | |
3096 | ||
f7920884 | 3097 | /* MaxPSASize value 0 (2 streams) means streams are not supported */ |
8f873c1f HG |
3098 | if ((xhci->quirks & XHCI_BROKEN_STREAMS) || |
3099 | HCC_MAX_PSA(xhci->hcc_params) < 4) { | |
f7920884 HG |
3100 | xhci_dbg(xhci, "xHCI controller does not support streams.\n"); |
3101 | return -ENOSYS; | |
3102 | } | |
3103 | ||
8df75f42 | 3104 | config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); |
74e0b564 | 3105 | if (!config_cmd) |
8df75f42 | 3106 | return -ENOMEM; |
74e0b564 | 3107 | |
4daf9df5 | 3108 | ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx); |
92f8e767 SS |
3109 | if (!ctrl_ctx) { |
3110 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3111 | __func__); | |
3112 | xhci_free_command(xhci, config_cmd); | |
3113 | return -ENOMEM; | |
3114 | } | |
8df75f42 SS |
3115 | |
3116 | /* Check to make sure all endpoints are not already configured for | |
3117 | * streams. While we're at it, find the maximum number of streams that | |
3118 | * all the endpoints will support and check for duplicate endpoints. | |
3119 | */ | |
3120 | spin_lock_irqsave(&xhci->lock, flags); | |
3121 | ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps, | |
3122 | num_eps, &num_streams, &changed_ep_bitmask); | |
3123 | if (ret < 0) { | |
3124 | xhci_free_command(xhci, config_cmd); | |
3125 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3126 | return ret; | |
3127 | } | |
3128 | if (num_streams <= 1) { | |
3129 | xhci_warn(xhci, "WARN: endpoints can't handle " | |
3130 | "more than one stream.\n"); | |
3131 | xhci_free_command(xhci, config_cmd); | |
3132 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3133 | return -EINVAL; | |
3134 | } | |
3135 | vdev = xhci->devs[udev->slot_id]; | |
25985edc | 3136 | /* Mark each endpoint as being in transition, so |
8df75f42 SS |
3137 | * xhci_urb_enqueue() will reject all URBs. |
3138 | */ | |
3139 | for (i = 0; i < num_eps; i++) { | |
3140 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3141 | vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS; | |
3142 | } | |
3143 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3144 | ||
3145 | /* Setup internal data structures and allocate HW data structures for | |
3146 | * streams (but don't install the HW structures in the input context | |
3147 | * until we're sure all memory allocation succeeded). | |
3148 | */ | |
3149 | xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs); | |
3150 | xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n", | |
3151 | num_stream_ctxs, num_streams); | |
3152 | ||
3153 | for (i = 0; i < num_eps; i++) { | |
3154 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
734d3ddd | 3155 | max_packet = usb_endpoint_maxp(&eps[i]->desc); |
8df75f42 SS |
3156 | vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci, |
3157 | num_stream_ctxs, | |
f9c589e1 MN |
3158 | num_streams, |
3159 | max_packet, mem_flags); | |
8df75f42 SS |
3160 | if (!vdev->eps[ep_index].stream_info) |
3161 | goto cleanup; | |
3162 | /* Set maxPstreams in endpoint context and update deq ptr to | |
3163 | * point to stream context array. FIXME | |
3164 | */ | |
3165 | } | |
3166 | ||
3167 | /* Set up the input context for a configure endpoint command. */ | |
3168 | for (i = 0; i < num_eps; i++) { | |
3169 | struct xhci_ep_ctx *ep_ctx; | |
3170 | ||
3171 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3172 | ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index); | |
3173 | ||
3174 | xhci_endpoint_copy(xhci, config_cmd->in_ctx, | |
3175 | vdev->out_ctx, ep_index); | |
3176 | xhci_setup_streams_ep_input_ctx(xhci, ep_ctx, | |
3177 | vdev->eps[ep_index].stream_info); | |
3178 | } | |
3179 | /* Tell the HW to drop its old copy of the endpoint context info | |
3180 | * and add the updated copy from the input context. | |
3181 | */ | |
3182 | xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx, | |
92f8e767 SS |
3183 | vdev->out_ctx, ctrl_ctx, |
3184 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3185 | |
3186 | /* Issue and wait for the configure endpoint command */ | |
3187 | ret = xhci_configure_endpoint(xhci, udev, config_cmd, | |
3188 | false, false); | |
3189 | ||
3190 | /* xHC rejected the configure endpoint command for some reason, so we | |
3191 | * leave the old ring intact and free our internal streams data | |
3192 | * structure. | |
3193 | */ | |
3194 | if (ret < 0) | |
3195 | goto cleanup; | |
3196 | ||
3197 | spin_lock_irqsave(&xhci->lock, flags); | |
3198 | for (i = 0; i < num_eps; i++) { | |
3199 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3200 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3201 | xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n", | |
3202 | udev->slot_id, ep_index); | |
3203 | vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS; | |
3204 | } | |
3205 | xhci_free_command(xhci, config_cmd); | |
3206 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3207 | ||
3208 | /* Subtract 1 for stream 0, which drivers can't use */ | |
3209 | return num_streams - 1; | |
3210 | ||
3211 | cleanup: | |
3212 | /* If it didn't work, free the streams! */ | |
3213 | for (i = 0; i < num_eps; i++) { | |
3214 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3215 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3216 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3217 | /* FIXME Unset maxPstreams in endpoint context and |
3218 | * update deq ptr to point to normal string ring. | |
3219 | */ | |
3220 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS; | |
3221 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3222 | xhci_endpoint_zero(xhci, vdev, eps[i]); | |
3223 | } | |
3224 | xhci_free_command(xhci, config_cmd); | |
3225 | return -ENOMEM; | |
3226 | } | |
3227 | ||
3228 | /* Transition the endpoint from using streams to being a "normal" endpoint | |
3229 | * without streams. | |
3230 | * | |
3231 | * Modify the endpoint context state, submit a configure endpoint command, | |
3232 | * and free all endpoint rings for streams if that completes successfully. | |
3233 | */ | |
3969384c | 3234 | static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, |
8df75f42 SS |
3235 | struct usb_host_endpoint **eps, unsigned int num_eps, |
3236 | gfp_t mem_flags) | |
3237 | { | |
3238 | int i, ret; | |
3239 | struct xhci_hcd *xhci; | |
3240 | struct xhci_virt_device *vdev; | |
3241 | struct xhci_command *command; | |
92f8e767 | 3242 | struct xhci_input_control_ctx *ctrl_ctx; |
8df75f42 SS |
3243 | unsigned int ep_index; |
3244 | unsigned long flags; | |
3245 | u32 changed_ep_bitmask; | |
3246 | ||
3247 | xhci = hcd_to_xhci(hcd); | |
3248 | vdev = xhci->devs[udev->slot_id]; | |
3249 | ||
3250 | /* Set up a configure endpoint command to remove the streams rings */ | |
3251 | spin_lock_irqsave(&xhci->lock, flags); | |
3252 | changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci, | |
3253 | udev, eps, num_eps); | |
3254 | if (changed_ep_bitmask == 0) { | |
3255 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3256 | return -EINVAL; | |
3257 | } | |
3258 | ||
3259 | /* Use the xhci_command structure from the first endpoint. We may have | |
3260 | * allocated too many, but the driver may call xhci_free_streams() for | |
3261 | * each endpoint it grouped into one call to xhci_alloc_streams(). | |
3262 | */ | |
3263 | ep_index = xhci_get_endpoint_index(&eps[0]->desc); | |
3264 | command = vdev->eps[ep_index].stream_info->free_streams_command; | |
4daf9df5 | 3265 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 | 3266 | if (!ctrl_ctx) { |
1f21569c | 3267 | spin_unlock_irqrestore(&xhci->lock, flags); |
92f8e767 SS |
3268 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", |
3269 | __func__); | |
3270 | return -EINVAL; | |
3271 | } | |
3272 | ||
8df75f42 SS |
3273 | for (i = 0; i < num_eps; i++) { |
3274 | struct xhci_ep_ctx *ep_ctx; | |
3275 | ||
3276 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3277 | ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index); | |
3278 | xhci->devs[udev->slot_id]->eps[ep_index].ep_state |= | |
3279 | EP_GETTING_NO_STREAMS; | |
3280 | ||
3281 | xhci_endpoint_copy(xhci, command->in_ctx, | |
3282 | vdev->out_ctx, ep_index); | |
4daf9df5 | 3283 | xhci_setup_no_streams_ep_input_ctx(ep_ctx, |
8df75f42 SS |
3284 | &vdev->eps[ep_index]); |
3285 | } | |
3286 | xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx, | |
92f8e767 SS |
3287 | vdev->out_ctx, ctrl_ctx, |
3288 | changed_ep_bitmask, changed_ep_bitmask); | |
8df75f42 SS |
3289 | spin_unlock_irqrestore(&xhci->lock, flags); |
3290 | ||
3291 | /* Issue and wait for the configure endpoint command, | |
3292 | * which must succeed. | |
3293 | */ | |
3294 | ret = xhci_configure_endpoint(xhci, udev, command, | |
3295 | false, true); | |
3296 | ||
3297 | /* xHC rejected the configure endpoint command for some reason, so we | |
3298 | * leave the streams rings intact. | |
3299 | */ | |
3300 | if (ret < 0) | |
3301 | return ret; | |
3302 | ||
3303 | spin_lock_irqsave(&xhci->lock, flags); | |
3304 | for (i = 0; i < num_eps; i++) { | |
3305 | ep_index = xhci_get_endpoint_index(&eps[i]->desc); | |
3306 | xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info); | |
8a007748 | 3307 | vdev->eps[ep_index].stream_info = NULL; |
8df75f42 SS |
3308 | /* FIXME Unset maxPstreams in endpoint context and |
3309 | * update deq ptr to point to normal string ring. | |
3310 | */ | |
3311 | vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS; | |
3312 | vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS; | |
3313 | } | |
3314 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3315 | ||
3316 | return 0; | |
3317 | } | |
3318 | ||
2cf95c18 SS |
3319 | /* |
3320 | * Deletes endpoint resources for endpoints that were active before a Reset | |
3321 | * Device command, or a Disable Slot command. The Reset Device command leaves | |
3322 | * the control endpoint intact, whereas the Disable Slot command deletes it. | |
3323 | * | |
3324 | * Must be called with xhci->lock held. | |
3325 | */ | |
3326 | void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, | |
3327 | struct xhci_virt_device *virt_dev, bool drop_control_ep) | |
3328 | { | |
3329 | int i; | |
3330 | unsigned int num_dropped_eps = 0; | |
3331 | unsigned int drop_flags = 0; | |
3332 | ||
3333 | for (i = (drop_control_ep ? 0 : 1); i < 31; i++) { | |
3334 | if (virt_dev->eps[i].ring) { | |
3335 | drop_flags |= 1 << i; | |
3336 | num_dropped_eps++; | |
3337 | } | |
3338 | } | |
3339 | xhci->num_active_eps -= num_dropped_eps; | |
3340 | if (num_dropped_eps) | |
4bdfe4c3 XR |
3341 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3342 | "Dropped %u ep ctxs, flags = 0x%x, " | |
3343 | "%u now active.", | |
2cf95c18 SS |
3344 | num_dropped_eps, drop_flags, |
3345 | xhci->num_active_eps); | |
3346 | } | |
3347 | ||
2a8f82c4 SS |
3348 | /* |
3349 | * This submits a Reset Device Command, which will set the device state to 0, | |
3350 | * set the device address to 0, and disable all the endpoints except the default | |
3351 | * control endpoint. The USB core should come back and call | |
3352 | * xhci_address_device(), and then re-set up the configuration. If this is | |
3353 | * called because of a usb_reset_and_verify_device(), then the old alternate | |
3354 | * settings will be re-installed through the normal bandwidth allocation | |
3355 | * functions. | |
3356 | * | |
3357 | * Wait for the Reset Device command to finish. Remove all structures | |
3358 | * associated with the endpoints that were disabled. Clear the input device | |
c5628a2a | 3359 | * structure? Reset the control endpoint 0 max packet size? |
f0615c45 AX |
3360 | * |
3361 | * If the virt_dev to be reset does not exist or does not match the udev, | |
3362 | * it means the device is lost, possibly due to the xHC restore error and | |
3363 | * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to | |
3364 | * re-allocate the device. | |
2a8f82c4 | 3365 | */ |
3969384c LB |
3366 | static int xhci_discover_or_reset_device(struct usb_hcd *hcd, |
3367 | struct usb_device *udev) | |
2a8f82c4 SS |
3368 | { |
3369 | int ret, i; | |
3370 | unsigned long flags; | |
3371 | struct xhci_hcd *xhci; | |
3372 | unsigned int slot_id; | |
3373 | struct xhci_virt_device *virt_dev; | |
3374 | struct xhci_command *reset_device_cmd; | |
2a8f82c4 | 3375 | int last_freed_endpoint; |
001fd382 | 3376 | struct xhci_slot_ctx *slot_ctx; |
2e27980e | 3377 | int old_active_eps = 0; |
2a8f82c4 | 3378 | |
f0615c45 | 3379 | ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__); |
2a8f82c4 SS |
3380 | if (ret <= 0) |
3381 | return ret; | |
3382 | xhci = hcd_to_xhci(hcd); | |
3383 | slot_id = udev->slot_id; | |
3384 | virt_dev = xhci->devs[slot_id]; | |
f0615c45 AX |
3385 | if (!virt_dev) { |
3386 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3387 | "not exist. Re-allocate the device\n", slot_id); | |
3388 | ret = xhci_alloc_dev(hcd, udev); | |
3389 | if (ret == 1) | |
3390 | return 0; | |
3391 | else | |
3392 | return -EINVAL; | |
3393 | } | |
3394 | ||
326124a0 BC |
3395 | if (virt_dev->tt_info) |
3396 | old_active_eps = virt_dev->tt_info->active_eps; | |
3397 | ||
f0615c45 AX |
3398 | if (virt_dev->udev != udev) { |
3399 | /* If the virt_dev and the udev does not match, this virt_dev | |
3400 | * may belong to another udev. | |
3401 | * Re-allocate the device. | |
3402 | */ | |
3403 | xhci_dbg(xhci, "The device to be reset with slot ID %u does " | |
3404 | "not match the udev. Re-allocate the device\n", | |
3405 | slot_id); | |
3406 | ret = xhci_alloc_dev(hcd, udev); | |
3407 | if (ret == 1) | |
3408 | return 0; | |
3409 | else | |
3410 | return -EINVAL; | |
3411 | } | |
2a8f82c4 | 3412 | |
001fd382 ML |
3413 | /* If device is not setup, there is no point in resetting it */ |
3414 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); | |
3415 | if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == | |
3416 | SLOT_STATE_DISABLED) | |
3417 | return 0; | |
3418 | ||
19a7d0d6 FB |
3419 | trace_xhci_discover_or_reset_device(slot_ctx); |
3420 | ||
2a8f82c4 SS |
3421 | xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id); |
3422 | /* Allocate the command structure that holds the struct completion. | |
3423 | * Assume we're in process context, since the normal device reset | |
3424 | * process has to wait for the device anyway. Storage devices are | |
3425 | * reset as part of error handling, so use GFP_NOIO instead of | |
3426 | * GFP_KERNEL. | |
3427 | */ | |
3428 | reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO); | |
3429 | if (!reset_device_cmd) { | |
3430 | xhci_dbg(xhci, "Couldn't allocate command structure.\n"); | |
3431 | return -ENOMEM; | |
3432 | } | |
3433 | ||
3434 | /* Attempt to submit the Reset Device command to the command ring */ | |
3435 | spin_lock_irqsave(&xhci->lock, flags); | |
7a3783ef | 3436 | |
ddba5cd0 | 3437 | ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id); |
2a8f82c4 SS |
3438 | if (ret) { |
3439 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
2a8f82c4 SS |
3440 | spin_unlock_irqrestore(&xhci->lock, flags); |
3441 | goto command_cleanup; | |
3442 | } | |
3443 | xhci_ring_cmd_db(xhci); | |
3444 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3445 | ||
3446 | /* Wait for the Reset Device command to finish */ | |
c311e391 | 3447 | wait_for_completion(reset_device_cmd->completion); |
2a8f82c4 SS |
3448 | |
3449 | /* The Reset Device command can't fail, according to the 0.95/0.96 spec, | |
3450 | * unless we tried to reset a slot ID that wasn't enabled, | |
3451 | * or the device wasn't in the addressed or configured state. | |
3452 | */ | |
3453 | ret = reset_device_cmd->status; | |
3454 | switch (ret) { | |
0b7c105a | 3455 | case COMP_COMMAND_ABORTED: |
604d02a2 | 3456 | case COMP_COMMAND_RING_STOPPED: |
c311e391 MN |
3457 | xhci_warn(xhci, "Timeout waiting for reset device command\n"); |
3458 | ret = -ETIME; | |
3459 | goto command_cleanup; | |
0b7c105a FB |
3460 | case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */ |
3461 | case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */ | |
38a532a6 | 3462 | xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n", |
2a8f82c4 SS |
3463 | slot_id, |
3464 | xhci_get_slot_state(xhci, virt_dev->out_ctx)); | |
38a532a6 | 3465 | xhci_dbg(xhci, "Not freeing device rings.\n"); |
2a8f82c4 SS |
3466 | /* Don't treat this as an error. May change my mind later. */ |
3467 | ret = 0; | |
3468 | goto command_cleanup; | |
3469 | case COMP_SUCCESS: | |
3470 | xhci_dbg(xhci, "Successful reset device command.\n"); | |
3471 | break; | |
3472 | default: | |
3473 | if (xhci_is_vendor_info_code(xhci, ret)) | |
3474 | break; | |
3475 | xhci_warn(xhci, "Unknown completion code %u for " | |
3476 | "reset device command.\n", ret); | |
3477 | ret = -EINVAL; | |
3478 | goto command_cleanup; | |
3479 | } | |
3480 | ||
2cf95c18 SS |
3481 | /* Free up host controller endpoint resources */ |
3482 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { | |
3483 | spin_lock_irqsave(&xhci->lock, flags); | |
3484 | /* Don't delete the default control endpoint resources */ | |
3485 | xhci_free_device_endpoint_resources(xhci, virt_dev, false); | |
3486 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3487 | } | |
3488 | ||
c5628a2a | 3489 | /* Everything but endpoint 0 is disabled, so free the rings. */ |
2a8f82c4 | 3490 | last_freed_endpoint = 1; |
98871e94 | 3491 | for (i = 1; i < 31; i++) { |
2dea75d9 DT |
3492 | struct xhci_virt_ep *ep = &virt_dev->eps[i]; |
3493 | ||
3494 | if (ep->ep_state & EP_HAS_STREAMS) { | |
df613834 HG |
3495 | xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n", |
3496 | xhci_get_endpoint_address(i)); | |
2dea75d9 DT |
3497 | xhci_free_stream_info(xhci, ep->stream_info); |
3498 | ep->stream_info = NULL; | |
3499 | ep->ep_state &= ~EP_HAS_STREAMS; | |
3500 | } | |
3501 | ||
3502 | if (ep->ring) { | |
02b6fdc2 | 3503 | xhci_debugfs_remove_endpoint(xhci, virt_dev, i); |
c5628a2a | 3504 | xhci_free_endpoint_ring(xhci, virt_dev, i); |
2dea75d9 DT |
3505 | last_freed_endpoint = i; |
3506 | } | |
2e27980e SS |
3507 | if (!list_empty(&virt_dev->eps[i].bw_endpoint_list)) |
3508 | xhci_drop_ep_from_interval_table(xhci, | |
3509 | &virt_dev->eps[i].bw_info, | |
3510 | virt_dev->bw_table, | |
3511 | udev, | |
3512 | &virt_dev->eps[i], | |
3513 | virt_dev->tt_info); | |
9af5d71d | 3514 | xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info); |
2a8f82c4 | 3515 | } |
2e27980e SS |
3516 | /* If necessary, update the number of active TTs on this root port */ |
3517 | xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps); | |
2a8f82c4 SS |
3518 | ret = 0; |
3519 | ||
3520 | command_cleanup: | |
3521 | xhci_free_command(xhci, reset_device_cmd); | |
3522 | return ret; | |
3523 | } | |
3524 | ||
3ffbba95 SS |
3525 | /* |
3526 | * At this point, the struct usb_device is about to go away, the device has | |
3527 | * disconnected, and all traffic has been stopped and the endpoints have been | |
3528 | * disabled. Free any HC data structures associated with that device. | |
3529 | */ | |
3969384c | 3530 | static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev) |
3ffbba95 SS |
3531 | { |
3532 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
6f5165cf | 3533 | struct xhci_virt_device *virt_dev; |
19a7d0d6 | 3534 | struct xhci_slot_ctx *slot_ctx; |
64927730 | 3535 | int i, ret; |
ddba5cd0 | 3536 | |
c8476fb8 SN |
3537 | #ifndef CONFIG_USB_DEFAULT_PERSIST |
3538 | /* | |
3539 | * We called pm_runtime_get_noresume when the device was attached. | |
3540 | * Decrement the counter here to allow controller to runtime suspend | |
3541 | * if no devices remain. | |
3542 | */ | |
3543 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | |
e7ecf069 | 3544 | pm_runtime_put_noidle(hcd->self.controller); |
c8476fb8 SN |
3545 | #endif |
3546 | ||
64927730 | 3547 | ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__); |
7bd89b40 SS |
3548 | /* If the host is halted due to driver unload, we still need to free the |
3549 | * device. | |
3550 | */ | |
cd3f1790 | 3551 | if (ret <= 0 && ret != -ENODEV) |
3ffbba95 | 3552 | return; |
64927730 | 3553 | |
6f5165cf | 3554 | virt_dev = xhci->devs[udev->slot_id]; |
19a7d0d6 FB |
3555 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
3556 | trace_xhci_free_dev(slot_ctx); | |
6f5165cf SS |
3557 | |
3558 | /* Stop any wayward timer functions (which may grab the lock) */ | |
98871e94 | 3559 | for (i = 0; i < 31; i++) { |
9983a5fc | 3560 | virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING; |
6f5165cf SS |
3561 | del_timer_sync(&virt_dev->eps[i].stop_cmd_timer); |
3562 | } | |
92953db5 | 3563 | xhci_debugfs_remove_slot(xhci, udev->slot_id); |
11ec7588 | 3564 | ret = xhci_disable_slot(xhci, udev->slot_id); |
92953db5 | 3565 | if (ret) |
11ec7588 | 3566 | xhci_free_virt_device(xhci, udev->slot_id); |
f9e609b8 GZ |
3567 | } |
3568 | ||
cd3f1790 | 3569 | int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id) |
f9e609b8 | 3570 | { |
cd3f1790 | 3571 | struct xhci_command *command; |
f9e609b8 GZ |
3572 | unsigned long flags; |
3573 | u32 state; | |
3574 | int ret = 0; | |
f9e609b8 | 3575 | |
cd3f1790 | 3576 | command = xhci_alloc_command(xhci, false, false, GFP_KERNEL); |
f9e609b8 GZ |
3577 | if (!command) |
3578 | return -ENOMEM; | |
3579 | ||
3ffbba95 | 3580 | spin_lock_irqsave(&xhci->lock, flags); |
c526d0d4 | 3581 | /* Don't disable the slot if the host controller is dead. */ |
b0ba9720 | 3582 | state = readl(&xhci->op_regs->status); |
7bd89b40 SS |
3583 | if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) || |
3584 | (xhci->xhc_state & XHCI_STATE_HALTED)) { | |
c526d0d4 | 3585 | spin_unlock_irqrestore(&xhci->lock, flags); |
ddba5cd0 | 3586 | kfree(command); |
dcabc76f | 3587 | return -ENODEV; |
c526d0d4 SS |
3588 | } |
3589 | ||
f9e609b8 GZ |
3590 | ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT, |
3591 | slot_id); | |
3592 | if (ret) { | |
3ffbba95 | 3593 | spin_unlock_irqrestore(&xhci->lock, flags); |
cd3f1790 | 3594 | kfree(command); |
f9e609b8 | 3595 | return ret; |
3ffbba95 | 3596 | } |
23e3be11 | 3597 | xhci_ring_cmd_db(xhci); |
3ffbba95 | 3598 | spin_unlock_irqrestore(&xhci->lock, flags); |
f9e609b8 | 3599 | return ret; |
3ffbba95 SS |
3600 | } |
3601 | ||
2cf95c18 SS |
3602 | /* |
3603 | * Checks if we have enough host controller resources for the default control | |
3604 | * endpoint. | |
3605 | * | |
3606 | * Must be called with xhci->lock held. | |
3607 | */ | |
3608 | static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci) | |
3609 | { | |
3610 | if (xhci->num_active_eps + 1 > xhci->limit_active_eps) { | |
4bdfe4c3 XR |
3611 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3612 | "Not enough ep ctxs: " | |
3613 | "%u active, need to add 1, limit is %u.", | |
2cf95c18 SS |
3614 | xhci->num_active_eps, xhci->limit_active_eps); |
3615 | return -ENOMEM; | |
3616 | } | |
3617 | xhci->num_active_eps += 1; | |
4bdfe4c3 XR |
3618 | xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, |
3619 | "Adding 1 ep ctx, %u now active.", | |
2cf95c18 SS |
3620 | xhci->num_active_eps); |
3621 | return 0; | |
3622 | } | |
3623 | ||
3624 | ||
3ffbba95 SS |
3625 | /* |
3626 | * Returns 0 if the xHC ran out of device slots, the Enable Slot command | |
3627 | * timed out, or allocating memory failed. Returns 1 on success. | |
3628 | */ | |
3629 | int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev) | |
3630 | { | |
3631 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
19a7d0d6 FB |
3632 | struct xhci_virt_device *vdev; |
3633 | struct xhci_slot_ctx *slot_ctx; | |
3ffbba95 | 3634 | unsigned long flags; |
a00918d0 | 3635 | int ret, slot_id; |
ddba5cd0 MN |
3636 | struct xhci_command *command; |
3637 | ||
87e44f2a | 3638 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); |
ddba5cd0 MN |
3639 | if (!command) |
3640 | return 0; | |
3ffbba95 SS |
3641 | |
3642 | spin_lock_irqsave(&xhci->lock, flags); | |
ddba5cd0 | 3643 | ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0); |
3ffbba95 SS |
3644 | if (ret) { |
3645 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3646 | xhci_dbg(xhci, "FIXME: allocate a command ring segment\n"); | |
87e44f2a | 3647 | xhci_free_command(xhci, command); |
3ffbba95 SS |
3648 | return 0; |
3649 | } | |
23e3be11 | 3650 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3651 | spin_unlock_irqrestore(&xhci->lock, flags); |
3652 | ||
c311e391 | 3653 | wait_for_completion(command->completion); |
c2d3d49b | 3654 | slot_id = command->slot_id; |
3ffbba95 | 3655 | |
a00918d0 | 3656 | if (!slot_id || command->status != COMP_SUCCESS) { |
3ffbba95 | 3657 | xhci_err(xhci, "Error while assigning device slot ID\n"); |
be982038 SS |
3658 | xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n", |
3659 | HCS_MAX_SLOTS( | |
3660 | readl(&xhci->cap_regs->hcs_params1))); | |
87e44f2a | 3661 | xhci_free_command(xhci, command); |
3ffbba95 SS |
3662 | return 0; |
3663 | } | |
2cf95c18 | 3664 | |
cd3f1790 LB |
3665 | xhci_free_command(xhci, command); |
3666 | ||
2cf95c18 SS |
3667 | if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) { |
3668 | spin_lock_irqsave(&xhci->lock, flags); | |
3669 | ret = xhci_reserve_host_control_ep_resources(xhci); | |
3670 | if (ret) { | |
3671 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3672 | xhci_warn(xhci, "Not enough host resources, " | |
3673 | "active endpoint contexts = %u\n", | |
3674 | xhci->num_active_eps); | |
3675 | goto disable_slot; | |
3676 | } | |
3677 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3678 | } | |
3679 | /* Use GFP_NOIO, since this function can be called from | |
a6d940dd SS |
3680 | * xhci_discover_or_reset_device(), which may be called as part of |
3681 | * mass storage driver error handling. | |
3682 | */ | |
a00918d0 | 3683 | if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) { |
3ffbba95 | 3684 | xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n"); |
2cf95c18 | 3685 | goto disable_slot; |
3ffbba95 | 3686 | } |
19a7d0d6 FB |
3687 | vdev = xhci->devs[slot_id]; |
3688 | slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx); | |
3689 | trace_xhci_alloc_dev(slot_ctx); | |
3690 | ||
a00918d0 | 3691 | udev->slot_id = slot_id; |
c8476fb8 | 3692 | |
02b6fdc2 LB |
3693 | xhci_debugfs_create_slot(xhci, slot_id); |
3694 | ||
c8476fb8 SN |
3695 | #ifndef CONFIG_USB_DEFAULT_PERSIST |
3696 | /* | |
3697 | * If resetting upon resume, we can't put the controller into runtime | |
3698 | * suspend if there is a device attached. | |
3699 | */ | |
3700 | if (xhci->quirks & XHCI_RESET_ON_RESUME) | |
e7ecf069 | 3701 | pm_runtime_get_noresume(hcd->self.controller); |
c8476fb8 SN |
3702 | #endif |
3703 | ||
3ffbba95 SS |
3704 | /* Is this a LS or FS device under a HS hub? */ |
3705 | /* Hub or peripherial? */ | |
3ffbba95 | 3706 | return 1; |
2cf95c18 SS |
3707 | |
3708 | disable_slot: | |
11ec7588 LB |
3709 | ret = xhci_disable_slot(xhci, udev->slot_id); |
3710 | if (ret) | |
3711 | xhci_free_virt_device(xhci, udev->slot_id); | |
3712 | ||
3713 | return 0; | |
3ffbba95 SS |
3714 | } |
3715 | ||
3716 | /* | |
48fc7dbd DW |
3717 | * Issue an Address Device command and optionally send a corresponding |
3718 | * SetAddress request to the device. | |
3ffbba95 | 3719 | */ |
48fc7dbd DW |
3720 | static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev, |
3721 | enum xhci_setup_dev setup) | |
3ffbba95 | 3722 | { |
6f8ffc0b | 3723 | const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address"; |
3ffbba95 | 3724 | unsigned long flags; |
3ffbba95 SS |
3725 | struct xhci_virt_device *virt_dev; |
3726 | int ret = 0; | |
3727 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
d115b048 JY |
3728 | struct xhci_slot_ctx *slot_ctx; |
3729 | struct xhci_input_control_ctx *ctrl_ctx; | |
8e595a5d | 3730 | u64 temp_64; |
a00918d0 CB |
3731 | struct xhci_command *command = NULL; |
3732 | ||
3733 | mutex_lock(&xhci->mutex); | |
3ffbba95 | 3734 | |
90797aee LB |
3735 | if (xhci->xhc_state) { /* dying, removing or halted */ |
3736 | ret = -ESHUTDOWN; | |
448116bf | 3737 | goto out; |
90797aee | 3738 | } |
448116bf | 3739 | |
3ffbba95 | 3740 | if (!udev->slot_id) { |
84a99f6f XR |
3741 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3742 | "Bad Slot ID %d", udev->slot_id); | |
a00918d0 CB |
3743 | ret = -EINVAL; |
3744 | goto out; | |
3ffbba95 SS |
3745 | } |
3746 | ||
3ffbba95 SS |
3747 | virt_dev = xhci->devs[udev->slot_id]; |
3748 | ||
7ed603ec ME |
3749 | if (WARN_ON(!virt_dev)) { |
3750 | /* | |
3751 | * In plug/unplug torture test with an NEC controller, | |
3752 | * a zero-dereference was observed once due to virt_dev = 0. | |
3753 | * Print useful debug rather than crash if it is observed again! | |
3754 | */ | |
3755 | xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n", | |
3756 | udev->slot_id); | |
a00918d0 CB |
3757 | ret = -EINVAL; |
3758 | goto out; | |
7ed603ec | 3759 | } |
19a7d0d6 FB |
3760 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx); |
3761 | trace_xhci_setup_device_slot(slot_ctx); | |
7ed603ec | 3762 | |
f161ead7 | 3763 | if (setup == SETUP_CONTEXT_ONLY) { |
f161ead7 MN |
3764 | if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) == |
3765 | SLOT_STATE_DEFAULT) { | |
3766 | xhci_dbg(xhci, "Slot already in default state\n"); | |
a00918d0 | 3767 | goto out; |
f161ead7 MN |
3768 | } |
3769 | } | |
3770 | ||
87e44f2a | 3771 | command = xhci_alloc_command(xhci, false, true, GFP_KERNEL); |
a00918d0 CB |
3772 | if (!command) { |
3773 | ret = -ENOMEM; | |
3774 | goto out; | |
3775 | } | |
ddba5cd0 MN |
3776 | |
3777 | command->in_ctx = virt_dev->in_ctx; | |
ddba5cd0 | 3778 | |
f0615c45 | 3779 | slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx); |
4daf9df5 | 3780 | ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); |
92f8e767 SS |
3781 | if (!ctrl_ctx) { |
3782 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3783 | __func__); | |
a00918d0 CB |
3784 | ret = -EINVAL; |
3785 | goto out; | |
92f8e767 | 3786 | } |
f0615c45 AX |
3787 | /* |
3788 | * If this is the first Set Address since device plug-in or | |
3789 | * virt_device realloaction after a resume with an xHCI power loss, | |
3790 | * then set up the slot context. | |
3791 | */ | |
3792 | if (!slot_ctx->dev_info) | |
3ffbba95 | 3793 | xhci_setup_addressable_virt_dev(xhci, udev); |
f0615c45 | 3794 | /* Otherwise, update the control endpoint ring enqueue pointer. */ |
2d1ee590 SS |
3795 | else |
3796 | xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev); | |
d31c285b SS |
3797 | ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG); |
3798 | ctrl_ctx->drop_flags = 0; | |
3799 | ||
1d27fabe | 3800 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
0c052aab | 3801 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3ffbba95 | 3802 | |
f88ba78d | 3803 | spin_lock_irqsave(&xhci->lock, flags); |
a711edee | 3804 | trace_xhci_setup_device(virt_dev); |
ddba5cd0 | 3805 | ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma, |
48fc7dbd | 3806 | udev->slot_id, setup); |
3ffbba95 SS |
3807 | if (ret) { |
3808 | spin_unlock_irqrestore(&xhci->lock, flags); | |
84a99f6f XR |
3809 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3810 | "FIXME: allocate a command ring segment"); | |
a00918d0 | 3811 | goto out; |
3ffbba95 | 3812 | } |
23e3be11 | 3813 | xhci_ring_cmd_db(xhci); |
3ffbba95 SS |
3814 | spin_unlock_irqrestore(&xhci->lock, flags); |
3815 | ||
3816 | /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */ | |
c311e391 MN |
3817 | wait_for_completion(command->completion); |
3818 | ||
3ffbba95 SS |
3819 | /* FIXME: From section 4.3.4: "Software shall be responsible for timing |
3820 | * the SetAddress() "recovery interval" required by USB and aborting the | |
3821 | * command on a timeout. | |
3822 | */ | |
9ea1833e | 3823 | switch (command->status) { |
0b7c105a | 3824 | case COMP_COMMAND_ABORTED: |
604d02a2 | 3825 | case COMP_COMMAND_RING_STOPPED: |
c311e391 MN |
3826 | xhci_warn(xhci, "Timeout while waiting for setup device command\n"); |
3827 | ret = -ETIME; | |
3828 | break; | |
0b7c105a FB |
3829 | case COMP_CONTEXT_STATE_ERROR: |
3830 | case COMP_SLOT_NOT_ENABLED_ERROR: | |
6f8ffc0b DW |
3831 | xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n", |
3832 | act, udev->slot_id); | |
3ffbba95 SS |
3833 | ret = -EINVAL; |
3834 | break; | |
0b7c105a | 3835 | case COMP_USB_TRANSACTION_ERROR: |
6f8ffc0b | 3836 | dev_warn(&udev->dev, "Device not responding to setup %s.\n", act); |
651aaf36 LB |
3837 | |
3838 | mutex_unlock(&xhci->mutex); | |
3839 | ret = xhci_disable_slot(xhci, udev->slot_id); | |
3840 | if (!ret) | |
3841 | xhci_alloc_dev(hcd, udev); | |
3842 | kfree(command->completion); | |
3843 | kfree(command); | |
3844 | return -EPROTO; | |
0b7c105a | 3845 | case COMP_INCOMPATIBLE_DEVICE_ERROR: |
6f8ffc0b DW |
3846 | dev_warn(&udev->dev, |
3847 | "ERROR: Incompatible device for setup %s command\n", act); | |
f6ba6fe2 AH |
3848 | ret = -ENODEV; |
3849 | break; | |
3ffbba95 | 3850 | case COMP_SUCCESS: |
84a99f6f | 3851 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
6f8ffc0b | 3852 | "Successful setup %s command", act); |
3ffbba95 SS |
3853 | break; |
3854 | default: | |
6f8ffc0b DW |
3855 | xhci_err(xhci, |
3856 | "ERROR: unexpected setup %s command completion code 0x%x.\n", | |
9ea1833e | 3857 | act, command->status); |
1d27fabe | 3858 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1); |
3ffbba95 SS |
3859 | ret = -EINVAL; |
3860 | break; | |
3861 | } | |
a00918d0 CB |
3862 | if (ret) |
3863 | goto out; | |
f7b2e403 | 3864 | temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); |
84a99f6f XR |
3865 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
3866 | "Op regs DCBAA ptr = %#016llx", temp_64); | |
3867 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
3868 | "Slot ID %d dcbaa entry @%p = %#016llx", | |
3869 | udev->slot_id, | |
3870 | &xhci->dcbaa->dev_context_ptrs[udev->slot_id], | |
3871 | (unsigned long long) | |
3872 | le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id])); | |
3873 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, | |
3874 | "Output Context DMA address = %#08llx", | |
d115b048 | 3875 | (unsigned long long)virt_dev->out_ctx->dma); |
1d27fabe | 3876 | trace_xhci_address_ctx(xhci, virt_dev->in_ctx, |
0c052aab | 3877 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
3ffbba95 SS |
3878 | /* |
3879 | * USB core uses address 1 for the roothubs, so we add one to the | |
3880 | * address given back to us by the HC. | |
3881 | */ | |
1d27fabe | 3882 | trace_xhci_address_ctx(xhci, virt_dev->out_ctx, |
0c052aab | 3883 | le32_to_cpu(slot_ctx->dev_info) >> 27); |
f94e0186 | 3884 | /* Zero the input context control for later use */ |
d115b048 JY |
3885 | ctrl_ctx->add_flags = 0; |
3886 | ctrl_ctx->drop_flags = 0; | |
3ffbba95 | 3887 | |
84a99f6f | 3888 | xhci_dbg_trace(xhci, trace_xhci_dbg_address, |
a2cdc343 DW |
3889 | "Internal device address = %d", |
3890 | le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK); | |
a00918d0 CB |
3891 | out: |
3892 | mutex_unlock(&xhci->mutex); | |
87e44f2a LB |
3893 | if (command) { |
3894 | kfree(command->completion); | |
3895 | kfree(command); | |
3896 | } | |
a00918d0 | 3897 | return ret; |
3ffbba95 SS |
3898 | } |
3899 | ||
3969384c | 3900 | static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev) |
48fc7dbd DW |
3901 | { |
3902 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS); | |
3903 | } | |
3904 | ||
3969384c | 3905 | static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev) |
48fc7dbd DW |
3906 | { |
3907 | return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY); | |
3908 | } | |
3909 | ||
3f5eb141 LT |
3910 | /* |
3911 | * Transfer the port index into real index in the HW port status | |
3912 | * registers. Caculate offset between the port's PORTSC register | |
3913 | * and port status base. Divide the number of per port register | |
3914 | * to get the real index. The raw port number bases 1. | |
3915 | */ | |
3916 | int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1) | |
3917 | { | |
3918 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
3919 | __le32 __iomem *base_addr = &xhci->op_regs->port_status_base; | |
3920 | __le32 __iomem *addr; | |
3921 | int raw_port; | |
3922 | ||
b50107bb | 3923 | if (hcd->speed < HCD_USB3) |
3f5eb141 LT |
3924 | addr = xhci->usb2_ports[port1 - 1]; |
3925 | else | |
3926 | addr = xhci->usb3_ports[port1 - 1]; | |
3927 | ||
3928 | raw_port = (addr - base_addr)/NUM_PORT_REGS + 1; | |
3929 | return raw_port; | |
3930 | } | |
3931 | ||
a558ccdc MN |
3932 | /* |
3933 | * Issue an Evaluate Context command to change the Maximum Exit Latency in the | |
3934 | * slot context. If that succeeds, store the new MEL in the xhci_virt_device. | |
3935 | */ | |
d5c82feb | 3936 | static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci, |
a558ccdc MN |
3937 | struct usb_device *udev, u16 max_exit_latency) |
3938 | { | |
3939 | struct xhci_virt_device *virt_dev; | |
3940 | struct xhci_command *command; | |
3941 | struct xhci_input_control_ctx *ctrl_ctx; | |
3942 | struct xhci_slot_ctx *slot_ctx; | |
3943 | unsigned long flags; | |
3944 | int ret; | |
3945 | ||
3946 | spin_lock_irqsave(&xhci->lock, flags); | |
96044694 MN |
3947 | |
3948 | virt_dev = xhci->devs[udev->slot_id]; | |
3949 | ||
3950 | /* | |
3951 | * virt_dev might not exists yet if xHC resumed from hibernate (S4) and | |
3952 | * xHC was re-initialized. Exit latency will be set later after | |
3953 | * hub_port_finish_reset() is done and xhci->devs[] are re-allocated | |
3954 | */ | |
3955 | ||
3956 | if (!virt_dev || max_exit_latency == virt_dev->current_mel) { | |
a558ccdc MN |
3957 | spin_unlock_irqrestore(&xhci->lock, flags); |
3958 | return 0; | |
3959 | } | |
3960 | ||
3961 | /* Attempt to issue an Evaluate Context command to change the MEL. */ | |
a558ccdc | 3962 | command = xhci->lpm_command; |
4daf9df5 | 3963 | ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); |
92f8e767 SS |
3964 | if (!ctrl_ctx) { |
3965 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3966 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
3967 | __func__); | |
3968 | return -ENOMEM; | |
3969 | } | |
3970 | ||
a558ccdc MN |
3971 | xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx); |
3972 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3973 | ||
a558ccdc MN |
3974 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
3975 | slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx); | |
3976 | slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT)); | |
3977 | slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency); | |
4801d4ea | 3978 | slot_ctx->dev_state = 0; |
a558ccdc | 3979 | |
3a7fa5be XR |
3980 | xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, |
3981 | "Set up evaluate context for LPM MEL change."); | |
a558ccdc MN |
3982 | |
3983 | /* Issue and wait for the evaluate context command. */ | |
3984 | ret = xhci_configure_endpoint(xhci, udev, command, | |
3985 | true, true); | |
a558ccdc MN |
3986 | |
3987 | if (!ret) { | |
3988 | spin_lock_irqsave(&xhci->lock, flags); | |
3989 | virt_dev->current_mel = max_exit_latency; | |
3990 | spin_unlock_irqrestore(&xhci->lock, flags); | |
3991 | } | |
3992 | return ret; | |
3993 | } | |
3994 | ||
ceb6c9c8 | 3995 | #ifdef CONFIG_PM |
9574323c AX |
3996 | |
3997 | /* BESL to HIRD Encoding array for USB2 LPM */ | |
3998 | static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000, | |
3999 | 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000}; | |
4000 | ||
4001 | /* Calculate HIRD/BESL for USB2 PORTPMSC*/ | |
f99298bf AX |
4002 | static int xhci_calculate_hird_besl(struct xhci_hcd *xhci, |
4003 | struct usb_device *udev) | |
9574323c | 4004 | { |
f99298bf AX |
4005 | int u2del, besl, besl_host; |
4006 | int besl_device = 0; | |
4007 | u32 field; | |
4008 | ||
4009 | u2del = HCS_U2_LATENCY(xhci->hcs_params3); | |
4010 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
9574323c | 4011 | |
f99298bf AX |
4012 | if (field & USB_BESL_SUPPORT) { |
4013 | for (besl_host = 0; besl_host < 16; besl_host++) { | |
4014 | if (xhci_besl_encoding[besl_host] >= u2del) | |
9574323c AX |
4015 | break; |
4016 | } | |
f99298bf AX |
4017 | /* Use baseline BESL value as default */ |
4018 | if (field & USB_BESL_BASELINE_VALID) | |
4019 | besl_device = USB_GET_BESL_BASELINE(field); | |
4020 | else if (field & USB_BESL_DEEP_VALID) | |
4021 | besl_device = USB_GET_BESL_DEEP(field); | |
9574323c AX |
4022 | } else { |
4023 | if (u2del <= 50) | |
f99298bf | 4024 | besl_host = 0; |
9574323c | 4025 | else |
f99298bf | 4026 | besl_host = (u2del - 51) / 75 + 1; |
9574323c AX |
4027 | } |
4028 | ||
f99298bf AX |
4029 | besl = besl_host + besl_device; |
4030 | if (besl > 15) | |
4031 | besl = 15; | |
4032 | ||
4033 | return besl; | |
9574323c AX |
4034 | } |
4035 | ||
a558ccdc MN |
4036 | /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */ |
4037 | static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev) | |
4038 | { | |
4039 | u32 field; | |
4040 | int l1; | |
4041 | int besld = 0; | |
4042 | int hirdm = 0; | |
4043 | ||
4044 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
4045 | ||
4046 | /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */ | |
17f34867 | 4047 | l1 = udev->l1_params.timeout / 256; |
a558ccdc MN |
4048 | |
4049 | /* device has preferred BESLD */ | |
4050 | if (field & USB_BESL_DEEP_VALID) { | |
4051 | besld = USB_GET_BESL_DEEP(field); | |
4052 | hirdm = 1; | |
4053 | } | |
4054 | ||
4055 | return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm); | |
4056 | } | |
4057 | ||
3969384c | 4058 | static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, |
65580b43 AX |
4059 | struct usb_device *udev, int enable) |
4060 | { | |
4061 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4062 | __le32 __iomem **port_array; | |
a558ccdc MN |
4063 | __le32 __iomem *pm_addr, *hlpm_addr; |
4064 | u32 pm_val, hlpm_val, field; | |
65580b43 AX |
4065 | unsigned int port_num; |
4066 | unsigned long flags; | |
a558ccdc MN |
4067 | int hird, exit_latency; |
4068 | int ret; | |
65580b43 | 4069 | |
b50107bb | 4070 | if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support || |
65580b43 AX |
4071 | !udev->lpm_capable) |
4072 | return -EPERM; | |
4073 | ||
4074 | if (!udev->parent || udev->parent->parent || | |
4075 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4076 | return -EPERM; | |
4077 | ||
4078 | if (udev->usb2_hw_lpm_capable != 1) | |
4079 | return -EPERM; | |
4080 | ||
4081 | spin_lock_irqsave(&xhci->lock, flags); | |
4082 | ||
4083 | port_array = xhci->usb2_ports; | |
4084 | port_num = udev->portnum - 1; | |
b6e76371 | 4085 | pm_addr = port_array[port_num] + PORTPMSC; |
b0ba9720 | 4086 | pm_val = readl(pm_addr); |
a558ccdc MN |
4087 | hlpm_addr = port_array[port_num] + PORTHLPMC; |
4088 | field = le32_to_cpu(udev->bos->ext_cap->bmAttributes); | |
65580b43 AX |
4089 | |
4090 | xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n", | |
654a55d3 | 4091 | enable ? "enable" : "disable", port_num + 1); |
65580b43 | 4092 | |
4750bc78 | 4093 | if (enable && !(xhci->quirks & XHCI_HW_LPM_DISABLE)) { |
a558ccdc MN |
4094 | /* Host supports BESL timeout instead of HIRD */ |
4095 | if (udev->usb2_hw_lpm_besl_capable) { | |
4096 | /* if device doesn't have a preferred BESL value use a | |
4097 | * default one which works with mixed HIRD and BESL | |
4098 | * systems. See XHCI_DEFAULT_BESL definition in xhci.h | |
4099 | */ | |
4100 | if ((field & USB_BESL_SUPPORT) && | |
4101 | (field & USB_BESL_BASELINE_VALID)) | |
4102 | hird = USB_GET_BESL_BASELINE(field); | |
4103 | else | |
17f34867 | 4104 | hird = udev->l1_params.besl; |
a558ccdc MN |
4105 | |
4106 | exit_latency = xhci_besl_encoding[hird]; | |
4107 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4108 | ||
4109 | /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx | |
4110 | * input context for link powermanagement evaluate | |
4111 | * context commands. It is protected by hcd->bandwidth | |
4112 | * mutex and is shared by all devices. We need to set | |
4113 | * the max ext latency in USB 2 BESL LPM as well, so | |
4114 | * use the same mutex and xhci_change_max_exit_latency() | |
4115 | */ | |
4116 | mutex_lock(hcd->bandwidth_mutex); | |
4117 | ret = xhci_change_max_exit_latency(xhci, udev, | |
4118 | exit_latency); | |
4119 | mutex_unlock(hcd->bandwidth_mutex); | |
4120 | ||
4121 | if (ret < 0) | |
4122 | return ret; | |
4123 | spin_lock_irqsave(&xhci->lock, flags); | |
4124 | ||
4125 | hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev); | |
204b7793 | 4126 | writel(hlpm_val, hlpm_addr); |
a558ccdc | 4127 | /* flush write */ |
b0ba9720 | 4128 | readl(hlpm_addr); |
a558ccdc MN |
4129 | } else { |
4130 | hird = xhci_calculate_hird_besl(xhci, udev); | |
4131 | } | |
4132 | ||
4133 | pm_val &= ~PORT_HIRD_MASK; | |
58e21f73 | 4134 | pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id); |
204b7793 | 4135 | writel(pm_val, pm_addr); |
b0ba9720 | 4136 | pm_val = readl(pm_addr); |
a558ccdc | 4137 | pm_val |= PORT_HLE; |
204b7793 | 4138 | writel(pm_val, pm_addr); |
a558ccdc | 4139 | /* flush write */ |
b0ba9720 | 4140 | readl(pm_addr); |
65580b43 | 4141 | } else { |
58e21f73 | 4142 | pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK); |
204b7793 | 4143 | writel(pm_val, pm_addr); |
a558ccdc | 4144 | /* flush write */ |
b0ba9720 | 4145 | readl(pm_addr); |
a558ccdc MN |
4146 | if (udev->usb2_hw_lpm_besl_capable) { |
4147 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4148 | mutex_lock(hcd->bandwidth_mutex); | |
4149 | xhci_change_max_exit_latency(xhci, udev, 0); | |
4150 | mutex_unlock(hcd->bandwidth_mutex); | |
4151 | return 0; | |
4152 | } | |
65580b43 AX |
4153 | } |
4154 | ||
4155 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4156 | return 0; | |
4157 | } | |
4158 | ||
b630d4b9 MN |
4159 | /* check if a usb2 port supports a given extened capability protocol |
4160 | * only USB2 ports extended protocol capability values are cached. | |
4161 | * Return 1 if capability is supported | |
4162 | */ | |
4163 | static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port, | |
4164 | unsigned capability) | |
4165 | { | |
4166 | u32 port_offset, port_count; | |
4167 | int i; | |
4168 | ||
4169 | for (i = 0; i < xhci->num_ext_caps; i++) { | |
4170 | if (xhci->ext_caps[i] & capability) { | |
4171 | /* port offsets starts at 1 */ | |
4172 | port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1; | |
4173 | port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]); | |
4174 | if (port >= port_offset && | |
4175 | port < port_offset + port_count) | |
4176 | return 1; | |
4177 | } | |
4178 | } | |
4179 | return 0; | |
4180 | } | |
4181 | ||
3969384c | 4182 | static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
b01bcbf7 SS |
4183 | { |
4184 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
b630d4b9 | 4185 | int portnum = udev->portnum - 1; |
b01bcbf7 | 4186 | |
b50107bb | 4187 | if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support || |
de68bab4 SS |
4188 | !udev->lpm_capable) |
4189 | return 0; | |
4190 | ||
4191 | /* we only support lpm for non-hub device connected to root hub yet */ | |
4192 | if (!udev->parent || udev->parent->parent || | |
4193 | udev->descriptor.bDeviceClass == USB_CLASS_HUB) | |
4194 | return 0; | |
4195 | ||
4196 | if (xhci->hw_lpm_support == 1 && | |
4197 | xhci_check_usb2_port_capability( | |
4198 | xhci, portnum, XHCI_HLC)) { | |
4199 | udev->usb2_hw_lpm_capable = 1; | |
4200 | udev->l1_params.timeout = XHCI_L1_TIMEOUT; | |
4201 | udev->l1_params.besl = XHCI_DEFAULT_BESL; | |
4202 | if (xhci_check_usb2_port_capability(xhci, portnum, | |
4203 | XHCI_BLC)) | |
4204 | udev->usb2_hw_lpm_besl_capable = 1; | |
b01bcbf7 SS |
4205 | } |
4206 | ||
4207 | return 0; | |
4208 | } | |
4209 | ||
3b3db026 SS |
4210 | /*---------------------- USB 3.0 Link PM functions ------------------------*/ |
4211 | ||
e3567d2c SS |
4212 | /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */ |
4213 | static unsigned long long xhci_service_interval_to_ns( | |
4214 | struct usb_endpoint_descriptor *desc) | |
4215 | { | |
16b45fdf | 4216 | return (1ULL << (desc->bInterval - 1)) * 125 * 1000; |
e3567d2c SS |
4217 | } |
4218 | ||
3b3db026 SS |
4219 | static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev, |
4220 | enum usb3_link_state state) | |
4221 | { | |
4222 | unsigned long long sel; | |
4223 | unsigned long long pel; | |
4224 | unsigned int max_sel_pel; | |
4225 | char *state_name; | |
4226 | ||
4227 | switch (state) { | |
4228 | case USB3_LPM_U1: | |
4229 | /* Convert SEL and PEL stored in nanoseconds to microseconds */ | |
4230 | sel = DIV_ROUND_UP(udev->u1_params.sel, 1000); | |
4231 | pel = DIV_ROUND_UP(udev->u1_params.pel, 1000); | |
4232 | max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL; | |
4233 | state_name = "U1"; | |
4234 | break; | |
4235 | case USB3_LPM_U2: | |
4236 | sel = DIV_ROUND_UP(udev->u2_params.sel, 1000); | |
4237 | pel = DIV_ROUND_UP(udev->u2_params.pel, 1000); | |
4238 | max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL; | |
4239 | state_name = "U2"; | |
4240 | break; | |
4241 | default: | |
4242 | dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n", | |
4243 | __func__); | |
e25e62ae | 4244 | return USB3_LPM_DISABLED; |
3b3db026 SS |
4245 | } |
4246 | ||
4247 | if (sel <= max_sel_pel && pel <= max_sel_pel) | |
4248 | return USB3_LPM_DEVICE_INITIATED; | |
4249 | ||
4250 | if (sel > max_sel_pel) | |
4251 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
4252 | "due to long SEL %llu ms\n", | |
4253 | state_name, sel); | |
4254 | else | |
4255 | dev_dbg(&udev->dev, "Device-initiated %s disabled " | |
03e64e96 | 4256 | "due to long PEL %llu ms\n", |
3b3db026 SS |
4257 | state_name, pel); |
4258 | return USB3_LPM_DISABLED; | |
4259 | } | |
4260 | ||
9502c46c | 4261 | /* The U1 timeout should be the maximum of the following values: |
e3567d2c SS |
4262 | * - For control endpoints, U1 system exit latency (SEL) * 3 |
4263 | * - For bulk endpoints, U1 SEL * 5 | |
4264 | * - For interrupt endpoints: | |
4265 | * - Notification EPs, U1 SEL * 3 | |
4266 | * - Periodic EPs, max(105% of bInterval, U1 SEL * 2) | |
4267 | * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2) | |
4268 | */ | |
9502c46c PA |
4269 | static unsigned long long xhci_calculate_intel_u1_timeout( |
4270 | struct usb_device *udev, | |
e3567d2c SS |
4271 | struct usb_endpoint_descriptor *desc) |
4272 | { | |
4273 | unsigned long long timeout_ns; | |
4274 | int ep_type; | |
4275 | int intr_type; | |
4276 | ||
4277 | ep_type = usb_endpoint_type(desc); | |
4278 | switch (ep_type) { | |
4279 | case USB_ENDPOINT_XFER_CONTROL: | |
4280 | timeout_ns = udev->u1_params.sel * 3; | |
4281 | break; | |
4282 | case USB_ENDPOINT_XFER_BULK: | |
4283 | timeout_ns = udev->u1_params.sel * 5; | |
4284 | break; | |
4285 | case USB_ENDPOINT_XFER_INT: | |
4286 | intr_type = usb_endpoint_interrupt_type(desc); | |
4287 | if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) { | |
4288 | timeout_ns = udev->u1_params.sel * 3; | |
4289 | break; | |
4290 | } | |
4291 | /* Otherwise the calculation is the same as isoc eps */ | |
7d864999 | 4292 | /* fall through */ |
e3567d2c SS |
4293 | case USB_ENDPOINT_XFER_ISOC: |
4294 | timeout_ns = xhci_service_interval_to_ns(desc); | |
c88db160 | 4295 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100); |
e3567d2c SS |
4296 | if (timeout_ns < udev->u1_params.sel * 2) |
4297 | timeout_ns = udev->u1_params.sel * 2; | |
4298 | break; | |
4299 | default: | |
4300 | return 0; | |
4301 | } | |
4302 | ||
9502c46c PA |
4303 | return timeout_ns; |
4304 | } | |
4305 | ||
4306 | /* Returns the hub-encoded U1 timeout value. */ | |
4307 | static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci, | |
4308 | struct usb_device *udev, | |
4309 | struct usb_endpoint_descriptor *desc) | |
4310 | { | |
4311 | unsigned long long timeout_ns; | |
4312 | ||
4313 | if (xhci->quirks & XHCI_INTEL_HOST) | |
4314 | timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc); | |
4315 | else | |
4316 | timeout_ns = udev->u1_params.sel; | |
4317 | ||
4318 | /* The U1 timeout is encoded in 1us intervals. | |
4319 | * Don't return a timeout of zero, because that's USB3_LPM_DISABLED. | |
4320 | */ | |
e3567d2c | 4321 | if (timeout_ns == USB3_LPM_DISABLED) |
9502c46c PA |
4322 | timeout_ns = 1; |
4323 | else | |
4324 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000); | |
e3567d2c SS |
4325 | |
4326 | /* If the necessary timeout value is bigger than what we can set in the | |
4327 | * USB 3.0 hub, we have to disable hub-initiated U1. | |
4328 | */ | |
4329 | if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT) | |
4330 | return timeout_ns; | |
4331 | dev_dbg(&udev->dev, "Hub-initiated U1 disabled " | |
4332 | "due to long timeout %llu ms\n", timeout_ns); | |
4333 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1); | |
4334 | } | |
4335 | ||
9502c46c | 4336 | /* The U2 timeout should be the maximum of: |
e3567d2c SS |
4337 | * - 10 ms (to avoid the bandwidth impact on the scheduler) |
4338 | * - largest bInterval of any active periodic endpoint (to avoid going | |
4339 | * into lower power link states between intervals). | |
4340 | * - the U2 Exit Latency of the device | |
4341 | */ | |
9502c46c PA |
4342 | static unsigned long long xhci_calculate_intel_u2_timeout( |
4343 | struct usb_device *udev, | |
e3567d2c SS |
4344 | struct usb_endpoint_descriptor *desc) |
4345 | { | |
4346 | unsigned long long timeout_ns; | |
4347 | unsigned long long u2_del_ns; | |
4348 | ||
4349 | timeout_ns = 10 * 1000 * 1000; | |
4350 | ||
4351 | if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) && | |
4352 | (xhci_service_interval_to_ns(desc) > timeout_ns)) | |
4353 | timeout_ns = xhci_service_interval_to_ns(desc); | |
4354 | ||
966e7a85 | 4355 | u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL; |
e3567d2c SS |
4356 | if (u2_del_ns > timeout_ns) |
4357 | timeout_ns = u2_del_ns; | |
4358 | ||
9502c46c PA |
4359 | return timeout_ns; |
4360 | } | |
4361 | ||
4362 | /* Returns the hub-encoded U2 timeout value. */ | |
4363 | static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci, | |
4364 | struct usb_device *udev, | |
4365 | struct usb_endpoint_descriptor *desc) | |
4366 | { | |
4367 | unsigned long long timeout_ns; | |
4368 | ||
4369 | if (xhci->quirks & XHCI_INTEL_HOST) | |
4370 | timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc); | |
4371 | else | |
4372 | timeout_ns = udev->u2_params.sel; | |
4373 | ||
e3567d2c | 4374 | /* The U2 timeout is encoded in 256us intervals */ |
c88db160 | 4375 | timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000); |
e3567d2c SS |
4376 | /* If the necessary timeout value is bigger than what we can set in the |
4377 | * USB 3.0 hub, we have to disable hub-initiated U2. | |
4378 | */ | |
4379 | if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT) | |
4380 | return timeout_ns; | |
4381 | dev_dbg(&udev->dev, "Hub-initiated U2 disabled " | |
4382 | "due to long timeout %llu ms\n", timeout_ns); | |
4383 | return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2); | |
4384 | } | |
4385 | ||
3b3db026 SS |
4386 | static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci, |
4387 | struct usb_device *udev, | |
4388 | struct usb_endpoint_descriptor *desc, | |
4389 | enum usb3_link_state state, | |
4390 | u16 *timeout) | |
4391 | { | |
9502c46c PA |
4392 | if (state == USB3_LPM_U1) |
4393 | return xhci_calculate_u1_timeout(xhci, udev, desc); | |
4394 | else if (state == USB3_LPM_U2) | |
4395 | return xhci_calculate_u2_timeout(xhci, udev, desc); | |
e3567d2c | 4396 | |
3b3db026 SS |
4397 | return USB3_LPM_DISABLED; |
4398 | } | |
4399 | ||
4400 | static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci, | |
4401 | struct usb_device *udev, | |
4402 | struct usb_endpoint_descriptor *desc, | |
4403 | enum usb3_link_state state, | |
4404 | u16 *timeout) | |
4405 | { | |
4406 | u16 alt_timeout; | |
4407 | ||
4408 | alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev, | |
4409 | desc, state, timeout); | |
4410 | ||
4411 | /* If we found we can't enable hub-initiated LPM, or | |
4412 | * the U1 or U2 exit latency was too high to allow | |
4413 | * device-initiated LPM as well, just stop searching. | |
4414 | */ | |
4415 | if (alt_timeout == USB3_LPM_DISABLED || | |
4416 | alt_timeout == USB3_LPM_DEVICE_INITIATED) { | |
4417 | *timeout = alt_timeout; | |
4418 | return -E2BIG; | |
4419 | } | |
4420 | if (alt_timeout > *timeout) | |
4421 | *timeout = alt_timeout; | |
4422 | return 0; | |
4423 | } | |
4424 | ||
4425 | static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci, | |
4426 | struct usb_device *udev, | |
4427 | struct usb_host_interface *alt, | |
4428 | enum usb3_link_state state, | |
4429 | u16 *timeout) | |
4430 | { | |
4431 | int j; | |
4432 | ||
4433 | for (j = 0; j < alt->desc.bNumEndpoints; j++) { | |
4434 | if (xhci_update_timeout_for_endpoint(xhci, udev, | |
4435 | &alt->endpoint[j].desc, state, timeout)) | |
4436 | return -E2BIG; | |
4437 | continue; | |
4438 | } | |
4439 | return 0; | |
4440 | } | |
4441 | ||
e3567d2c SS |
4442 | static int xhci_check_intel_tier_policy(struct usb_device *udev, |
4443 | enum usb3_link_state state) | |
4444 | { | |
4445 | struct usb_device *parent; | |
4446 | unsigned int num_hubs; | |
4447 | ||
4448 | if (state == USB3_LPM_U2) | |
4449 | return 0; | |
4450 | ||
4451 | /* Don't enable U1 if the device is on a 2nd tier hub or lower. */ | |
4452 | for (parent = udev->parent, num_hubs = 0; parent->parent; | |
4453 | parent = parent->parent) | |
4454 | num_hubs++; | |
4455 | ||
4456 | if (num_hubs < 2) | |
4457 | return 0; | |
4458 | ||
4459 | dev_dbg(&udev->dev, "Disabling U1 link state for device" | |
4460 | " below second-tier hub.\n"); | |
4461 | dev_dbg(&udev->dev, "Plug device into first-tier hub " | |
4462 | "to decrease power consumption.\n"); | |
4463 | return -E2BIG; | |
4464 | } | |
4465 | ||
3b3db026 SS |
4466 | static int xhci_check_tier_policy(struct xhci_hcd *xhci, |
4467 | struct usb_device *udev, | |
4468 | enum usb3_link_state state) | |
4469 | { | |
e3567d2c SS |
4470 | if (xhci->quirks & XHCI_INTEL_HOST) |
4471 | return xhci_check_intel_tier_policy(udev, state); | |
9502c46c PA |
4472 | else |
4473 | return 0; | |
3b3db026 SS |
4474 | } |
4475 | ||
4476 | /* Returns the U1 or U2 timeout that should be enabled. | |
4477 | * If the tier check or timeout setting functions return with a non-zero exit | |
4478 | * code, that means the timeout value has been finalized and we shouldn't look | |
4479 | * at any more endpoints. | |
4480 | */ | |
4481 | static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd, | |
4482 | struct usb_device *udev, enum usb3_link_state state) | |
4483 | { | |
4484 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4485 | struct usb_host_config *config; | |
4486 | char *state_name; | |
4487 | int i; | |
4488 | u16 timeout = USB3_LPM_DISABLED; | |
4489 | ||
4490 | if (state == USB3_LPM_U1) | |
4491 | state_name = "U1"; | |
4492 | else if (state == USB3_LPM_U2) | |
4493 | state_name = "U2"; | |
4494 | else { | |
4495 | dev_warn(&udev->dev, "Can't enable unknown link state %i\n", | |
4496 | state); | |
4497 | return timeout; | |
4498 | } | |
4499 | ||
4500 | if (xhci_check_tier_policy(xhci, udev, state) < 0) | |
4501 | return timeout; | |
4502 | ||
4503 | /* Gather some information about the currently installed configuration | |
4504 | * and alternate interface settings. | |
4505 | */ | |
4506 | if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc, | |
4507 | state, &timeout)) | |
4508 | return timeout; | |
4509 | ||
4510 | config = udev->actconfig; | |
4511 | if (!config) | |
4512 | return timeout; | |
4513 | ||
64ba419b | 4514 | for (i = 0; i < config->desc.bNumInterfaces; i++) { |
3b3db026 SS |
4515 | struct usb_driver *driver; |
4516 | struct usb_interface *intf = config->interface[i]; | |
4517 | ||
4518 | if (!intf) | |
4519 | continue; | |
4520 | ||
4521 | /* Check if any currently bound drivers want hub-initiated LPM | |
4522 | * disabled. | |
4523 | */ | |
4524 | if (intf->dev.driver) { | |
4525 | driver = to_usb_driver(intf->dev.driver); | |
4526 | if (driver && driver->disable_hub_initiated_lpm) { | |
4527 | dev_dbg(&udev->dev, "Hub-initiated %s disabled " | |
4528 | "at request of driver %s\n", | |
4529 | state_name, driver->name); | |
4530 | return xhci_get_timeout_no_hub_lpm(udev, state); | |
4531 | } | |
4532 | } | |
4533 | ||
4534 | /* Not sure how this could happen... */ | |
4535 | if (!intf->cur_altsetting) | |
4536 | continue; | |
4537 | ||
4538 | if (xhci_update_timeout_for_interface(xhci, udev, | |
4539 | intf->cur_altsetting, | |
4540 | state, &timeout)) | |
4541 | return timeout; | |
4542 | } | |
4543 | return timeout; | |
4544 | } | |
4545 | ||
3b3db026 SS |
4546 | static int calculate_max_exit_latency(struct usb_device *udev, |
4547 | enum usb3_link_state state_changed, | |
4548 | u16 hub_encoded_timeout) | |
4549 | { | |
4550 | unsigned long long u1_mel_us = 0; | |
4551 | unsigned long long u2_mel_us = 0; | |
4552 | unsigned long long mel_us = 0; | |
4553 | bool disabling_u1; | |
4554 | bool disabling_u2; | |
4555 | bool enabling_u1; | |
4556 | bool enabling_u2; | |
4557 | ||
4558 | disabling_u1 = (state_changed == USB3_LPM_U1 && | |
4559 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4560 | disabling_u2 = (state_changed == USB3_LPM_U2 && | |
4561 | hub_encoded_timeout == USB3_LPM_DISABLED); | |
4562 | ||
4563 | enabling_u1 = (state_changed == USB3_LPM_U1 && | |
4564 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4565 | enabling_u2 = (state_changed == USB3_LPM_U2 && | |
4566 | hub_encoded_timeout != USB3_LPM_DISABLED); | |
4567 | ||
4568 | /* If U1 was already enabled and we're not disabling it, | |
4569 | * or we're going to enable U1, account for the U1 max exit latency. | |
4570 | */ | |
4571 | if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) || | |
4572 | enabling_u1) | |
4573 | u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000); | |
4574 | if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) || | |
4575 | enabling_u2) | |
4576 | u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000); | |
4577 | ||
4578 | if (u1_mel_us > u2_mel_us) | |
4579 | mel_us = u1_mel_us; | |
4580 | else | |
4581 | mel_us = u2_mel_us; | |
4582 | /* xHCI host controller max exit latency field is only 16 bits wide. */ | |
4583 | if (mel_us > MAX_EXIT) { | |
4584 | dev_warn(&udev->dev, "Link PM max exit latency of %lluus " | |
4585 | "is too big.\n", mel_us); | |
4586 | return -E2BIG; | |
4587 | } | |
4588 | return mel_us; | |
4589 | } | |
4590 | ||
4591 | /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */ | |
3969384c | 4592 | static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, |
3b3db026 SS |
4593 | struct usb_device *udev, enum usb3_link_state state) |
4594 | { | |
4595 | struct xhci_hcd *xhci; | |
4596 | u16 hub_encoded_timeout; | |
4597 | int mel; | |
4598 | int ret; | |
4599 | ||
4600 | xhci = hcd_to_xhci(hcd); | |
4601 | /* The LPM timeout values are pretty host-controller specific, so don't | |
4602 | * enable hub-initiated timeouts unless the vendor has provided | |
4603 | * information about their timeout algorithm. | |
4604 | */ | |
4605 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4606 | !xhci->devs[udev->slot_id]) | |
4607 | return USB3_LPM_DISABLED; | |
4608 | ||
4609 | hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state); | |
4610 | mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout); | |
4611 | if (mel < 0) { | |
4612 | /* Max Exit Latency is too big, disable LPM. */ | |
4613 | hub_encoded_timeout = USB3_LPM_DISABLED; | |
4614 | mel = 0; | |
4615 | } | |
4616 | ||
4617 | ret = xhci_change_max_exit_latency(xhci, udev, mel); | |
4618 | if (ret) | |
4619 | return ret; | |
4620 | return hub_encoded_timeout; | |
4621 | } | |
4622 | ||
3969384c | 4623 | static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, |
3b3db026 SS |
4624 | struct usb_device *udev, enum usb3_link_state state) |
4625 | { | |
4626 | struct xhci_hcd *xhci; | |
4627 | u16 mel; | |
3b3db026 SS |
4628 | |
4629 | xhci = hcd_to_xhci(hcd); | |
4630 | if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) || | |
4631 | !xhci->devs[udev->slot_id]) | |
4632 | return 0; | |
4633 | ||
4634 | mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED); | |
f1cda54c | 4635 | return xhci_change_max_exit_latency(xhci, udev, mel); |
3b3db026 | 4636 | } |
b01bcbf7 | 4637 | #else /* CONFIG_PM */ |
9574323c | 4638 | |
3969384c | 4639 | static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, |
ceb6c9c8 RW |
4640 | struct usb_device *udev, int enable) |
4641 | { | |
4642 | return 0; | |
4643 | } | |
4644 | ||
3969384c | 4645 | static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev) |
ceb6c9c8 RW |
4646 | { |
4647 | return 0; | |
4648 | } | |
4649 | ||
3969384c | 4650 | static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, |
b01bcbf7 | 4651 | struct usb_device *udev, enum usb3_link_state state) |
65580b43 | 4652 | { |
b01bcbf7 | 4653 | return USB3_LPM_DISABLED; |
65580b43 AX |
4654 | } |
4655 | ||
3969384c | 4656 | static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, |
b01bcbf7 | 4657 | struct usb_device *udev, enum usb3_link_state state) |
9574323c AX |
4658 | { |
4659 | return 0; | |
4660 | } | |
b01bcbf7 | 4661 | #endif /* CONFIG_PM */ |
9574323c | 4662 | |
b01bcbf7 | 4663 | /*-------------------------------------------------------------------------*/ |
9574323c | 4664 | |
ac1c1b7f SS |
4665 | /* Once a hub descriptor is fetched for a device, we need to update the xHC's |
4666 | * internal data structures for the device. | |
4667 | */ | |
3969384c | 4668 | static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, |
ac1c1b7f SS |
4669 | struct usb_tt *tt, gfp_t mem_flags) |
4670 | { | |
4671 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4672 | struct xhci_virt_device *vdev; | |
4673 | struct xhci_command *config_cmd; | |
4674 | struct xhci_input_control_ctx *ctrl_ctx; | |
4675 | struct xhci_slot_ctx *slot_ctx; | |
4676 | unsigned long flags; | |
4677 | unsigned think_time; | |
4678 | int ret; | |
4679 | ||
4680 | /* Ignore root hubs */ | |
4681 | if (!hdev->parent) | |
4682 | return 0; | |
4683 | ||
4684 | vdev = xhci->devs[hdev->slot_id]; | |
4685 | if (!vdev) { | |
4686 | xhci_warn(xhci, "Cannot update hub desc for unknown device.\n"); | |
4687 | return -EINVAL; | |
4688 | } | |
74e0b564 | 4689 | |
a1d78c16 | 4690 | config_cmd = xhci_alloc_command(xhci, true, true, mem_flags); |
74e0b564 | 4691 | if (!config_cmd) |
ac1c1b7f | 4692 | return -ENOMEM; |
74e0b564 | 4693 | |
4daf9df5 | 4694 | ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx); |
92f8e767 SS |
4695 | if (!ctrl_ctx) { |
4696 | xhci_warn(xhci, "%s: Could not get input context, bad type.\n", | |
4697 | __func__); | |
4698 | xhci_free_command(xhci, config_cmd); | |
4699 | return -ENOMEM; | |
4700 | } | |
ac1c1b7f SS |
4701 | |
4702 | spin_lock_irqsave(&xhci->lock, flags); | |
839c817c SS |
4703 | if (hdev->speed == USB_SPEED_HIGH && |
4704 | xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) { | |
4705 | xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n"); | |
4706 | xhci_free_command(xhci, config_cmd); | |
4707 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4708 | return -ENOMEM; | |
4709 | } | |
4710 | ||
ac1c1b7f | 4711 | xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx); |
28ccd296 | 4712 | ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG); |
ac1c1b7f | 4713 | slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx); |
28ccd296 | 4714 | slot_ctx->dev_info |= cpu_to_le32(DEV_HUB); |
096b110a CY |
4715 | /* |
4716 | * refer to section 6.2.2: MTT should be 0 for full speed hub, | |
4717 | * but it may be already set to 1 when setup an xHCI virtual | |
4718 | * device, so clear it anyway. | |
4719 | */ | |
ac1c1b7f | 4720 | if (tt->multi) |
28ccd296 | 4721 | slot_ctx->dev_info |= cpu_to_le32(DEV_MTT); |
096b110a CY |
4722 | else if (hdev->speed == USB_SPEED_FULL) |
4723 | slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT); | |
4724 | ||
ac1c1b7f SS |
4725 | if (xhci->hci_version > 0x95) { |
4726 | xhci_dbg(xhci, "xHCI version %x needs hub " | |
4727 | "TT think time and number of ports\n", | |
4728 | (unsigned int) xhci->hci_version); | |
28ccd296 | 4729 | slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild)); |
ac1c1b7f SS |
4730 | /* Set TT think time - convert from ns to FS bit times. |
4731 | * 0 = 8 FS bit times, 1 = 16 FS bit times, | |
4732 | * 2 = 24 FS bit times, 3 = 32 FS bit times. | |
700b4173 AX |
4733 | * |
4734 | * xHCI 1.0: this field shall be 0 if the device is not a | |
4735 | * High-spped hub. | |
ac1c1b7f SS |
4736 | */ |
4737 | think_time = tt->think_time; | |
4738 | if (think_time != 0) | |
4739 | think_time = (think_time / 666) - 1; | |
700b4173 AX |
4740 | if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH) |
4741 | slot_ctx->tt_info |= | |
4742 | cpu_to_le32(TT_THINK_TIME(think_time)); | |
ac1c1b7f SS |
4743 | } else { |
4744 | xhci_dbg(xhci, "xHCI version %x doesn't need hub " | |
4745 | "TT think time or number of ports\n", | |
4746 | (unsigned int) xhci->hci_version); | |
4747 | } | |
4748 | slot_ctx->dev_state = 0; | |
4749 | spin_unlock_irqrestore(&xhci->lock, flags); | |
4750 | ||
4751 | xhci_dbg(xhci, "Set up %s for hub device.\n", | |
4752 | (xhci->hci_version > 0x95) ? | |
4753 | "configure endpoint" : "evaluate context"); | |
ac1c1b7f SS |
4754 | |
4755 | /* Issue and wait for the configure endpoint or | |
4756 | * evaluate context command. | |
4757 | */ | |
4758 | if (xhci->hci_version > 0x95) | |
4759 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
4760 | false, false); | |
4761 | else | |
4762 | ret = xhci_configure_endpoint(xhci, hdev, config_cmd, | |
4763 | true, false); | |
4764 | ||
ac1c1b7f SS |
4765 | xhci_free_command(xhci, config_cmd); |
4766 | return ret; | |
4767 | } | |
4768 | ||
3969384c | 4769 | static int xhci_get_frame(struct usb_hcd *hcd) |
66d4eadd SS |
4770 | { |
4771 | struct xhci_hcd *xhci = hcd_to_xhci(hcd); | |
4772 | /* EHCI mods by the periodic size. Why? */ | |
b0ba9720 | 4773 | return readl(&xhci->run_regs->microframe_index) >> 3; |
66d4eadd SS |
4774 | } |
4775 | ||
552e0c4f SAS |
4776 | int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) |
4777 | { | |
4778 | struct xhci_hcd *xhci; | |
4c39d4b9 AB |
4779 | /* |
4780 | * TODO: Check with DWC3 clients for sysdev according to | |
4781 | * quirks | |
4782 | */ | |
4783 | struct device *dev = hcd->self.sysdev; | |
552e0c4f | 4784 | int retval; |
552e0c4f | 4785 | |
1386ff75 SS |
4786 | /* Accept arbitrarily long scatter-gather lists */ |
4787 | hcd->self.sg_tablesize = ~0; | |
fc76051c | 4788 | |
e2ed5114 MN |
4789 | /* support to build packet from discontinuous buffers */ |
4790 | hcd->self.no_sg_constraint = 1; | |
4791 | ||
19181bc5 HG |
4792 | /* XHCI controllers don't stop the ep queue on short packets :| */ |
4793 | hcd->self.no_stop_on_short = 1; | |
552e0c4f | 4794 | |
b50107bb MN |
4795 | xhci = hcd_to_xhci(hcd); |
4796 | ||
552e0c4f | 4797 | if (usb_hcd_is_primary_hcd(hcd)) { |
552e0c4f SAS |
4798 | xhci->main_hcd = hcd; |
4799 | /* Mark the first roothub as being USB 2.0. | |
4800 | * The xHCI driver will register the USB 3.0 roothub. | |
4801 | */ | |
4802 | hcd->speed = HCD_USB2; | |
4803 | hcd->self.root_hub->speed = USB_SPEED_HIGH; | |
4804 | /* | |
4805 | * USB 2.0 roothub under xHCI has an integrated TT, | |
4806 | * (rate matching hub) as opposed to having an OHCI/UHCI | |
4807 | * companion controller. | |
4808 | */ | |
4809 | hcd->has_tt = 1; | |
4810 | } else { | |
ea7d0d69 MN |
4811 | /* Some 3.1 hosts return sbrn 0x30, can't rely on sbrn alone */ |
4812 | if (xhci->sbrn == 0x31 || xhci->usb3_rhub.min_rev >= 1) { | |
b50107bb MN |
4813 | xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n"); |
4814 | hcd->speed = HCD_USB31; | |
2c0e06f8 | 4815 | hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS; |
b50107bb | 4816 | } |
552e0c4f SAS |
4817 | /* xHCI private pointer was set in xhci_pci_probe for the second |
4818 | * registered roothub. | |
4819 | */ | |
552e0c4f SAS |
4820 | return 0; |
4821 | } | |
4822 | ||
a00918d0 | 4823 | mutex_init(&xhci->mutex); |
552e0c4f SAS |
4824 | xhci->cap_regs = hcd->regs; |
4825 | xhci->op_regs = hcd->regs + | |
b0ba9720 | 4826 | HC_LENGTH(readl(&xhci->cap_regs->hc_capbase)); |
552e0c4f | 4827 | xhci->run_regs = hcd->regs + |
b0ba9720 | 4828 | (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK); |
552e0c4f | 4829 | /* Cache read-only capability registers */ |
b0ba9720 XR |
4830 | xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1); |
4831 | xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2); | |
4832 | xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3); | |
4833 | xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase); | |
552e0c4f | 4834 | xhci->hci_version = HC_VERSION(xhci->hcc_params); |
b0ba9720 | 4835 | xhci->hcc_params = readl(&xhci->cap_regs->hcc_params); |
04abb6de LB |
4836 | if (xhci->hci_version > 0x100) |
4837 | xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2); | |
552e0c4f SAS |
4838 | xhci_print_registers(xhci); |
4839 | ||
757de492 | 4840 | xhci->quirks |= quirks; |
4e6a1ee7 | 4841 | |
552e0c4f SAS |
4842 | get_quirks(dev, xhci); |
4843 | ||
07f3cb7c GC |
4844 | /* In xhci controllers which follow xhci 1.0 spec gives a spurious |
4845 | * success event after a short transfer. This quirk will ignore such | |
4846 | * spurious event. | |
4847 | */ | |
4848 | if (xhci->hci_version > 0x96) | |
4849 | xhci->quirks |= XHCI_SPURIOUS_SUCCESS; | |
4850 | ||
552e0c4f SAS |
4851 | /* Make sure the HC is halted. */ |
4852 | retval = xhci_halt(xhci); | |
4853 | if (retval) | |
cd33a321 | 4854 | return retval; |
552e0c4f SAS |
4855 | |
4856 | xhci_dbg(xhci, "Resetting HCD\n"); | |
4857 | /* Reset the internal HC memory state and registers. */ | |
4858 | retval = xhci_reset(xhci); | |
4859 | if (retval) | |
cd33a321 | 4860 | return retval; |
552e0c4f SAS |
4861 | xhci_dbg(xhci, "Reset complete\n"); |
4862 | ||
0a380be8 YS |
4863 | /* |
4864 | * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0) | |
4865 | * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit | |
4866 | * address memory pointers actually. So, this driver clears the AC64 | |
4867 | * bit of xhci->hcc_params to call dma_set_coherent_mask(dev, | |
4868 | * DMA_BIT_MASK(32)) in this xhci_gen_setup(). | |
4869 | */ | |
4870 | if (xhci->quirks & XHCI_NO_64BIT_SUPPORT) | |
4871 | xhci->hcc_params &= ~BIT(0); | |
4872 | ||
c10cf118 XR |
4873 | /* Set dma_mask and coherent_dma_mask to 64-bits, |
4874 | * if xHC supports 64-bit addressing */ | |
4875 | if (HCC_64BIT_ADDR(xhci->hcc_params) && | |
4876 | !dma_set_mask(dev, DMA_BIT_MASK(64))) { | |
552e0c4f | 4877 | xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n"); |
c10cf118 | 4878 | dma_set_coherent_mask(dev, DMA_BIT_MASK(64)); |
fda182d8 DD |
4879 | } else { |
4880 | /* | |
4881 | * This is to avoid error in cases where a 32-bit USB | |
4882 | * controller is used on a 64-bit capable system. | |
4883 | */ | |
4884 | retval = dma_set_mask(dev, DMA_BIT_MASK(32)); | |
4885 | if (retval) | |
4886 | return retval; | |
4887 | xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n"); | |
4888 | dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); | |
552e0c4f SAS |
4889 | } |
4890 | ||
4891 | xhci_dbg(xhci, "Calling HCD init\n"); | |
4892 | /* Initialize HCD and host controller data structures. */ | |
4893 | retval = xhci_init(hcd); | |
4894 | if (retval) | |
cd33a321 | 4895 | return retval; |
552e0c4f | 4896 | xhci_dbg(xhci, "Called HCD init\n"); |
99705092 HG |
4897 | |
4898 | xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n", | |
4899 | xhci->hcc_params, xhci->hci_version, xhci->quirks); | |
4900 | ||
552e0c4f | 4901 | return 0; |
552e0c4f | 4902 | } |
436e8c7d | 4903 | EXPORT_SYMBOL_GPL(xhci_gen_setup); |
552e0c4f | 4904 | |
1885d9a3 AB |
4905 | static const struct hc_driver xhci_hc_driver = { |
4906 | .description = "xhci-hcd", | |
4907 | .product_desc = "xHCI Host Controller", | |
32479d4b | 4908 | .hcd_priv_size = sizeof(struct xhci_hcd), |
1885d9a3 AB |
4909 | |
4910 | /* | |
4911 | * generic hardware linkage | |
4912 | */ | |
4913 | .irq = xhci_irq, | |
4914 | .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED, | |
4915 | ||
4916 | /* | |
4917 | * basic lifecycle operations | |
4918 | */ | |
4919 | .reset = NULL, /* set in xhci_init_driver() */ | |
4920 | .start = xhci_run, | |
4921 | .stop = xhci_stop, | |
4922 | .shutdown = xhci_shutdown, | |
4923 | ||
4924 | /* | |
4925 | * managing i/o requests and associated device resources | |
4926 | */ | |
4927 | .urb_enqueue = xhci_urb_enqueue, | |
4928 | .urb_dequeue = xhci_urb_dequeue, | |
4929 | .alloc_dev = xhci_alloc_dev, | |
4930 | .free_dev = xhci_free_dev, | |
4931 | .alloc_streams = xhci_alloc_streams, | |
4932 | .free_streams = xhci_free_streams, | |
4933 | .add_endpoint = xhci_add_endpoint, | |
4934 | .drop_endpoint = xhci_drop_endpoint, | |
4935 | .endpoint_reset = xhci_endpoint_reset, | |
4936 | .check_bandwidth = xhci_check_bandwidth, | |
4937 | .reset_bandwidth = xhci_reset_bandwidth, | |
4938 | .address_device = xhci_address_device, | |
4939 | .enable_device = xhci_enable_device, | |
4940 | .update_hub_device = xhci_update_hub_device, | |
4941 | .reset_device = xhci_discover_or_reset_device, | |
4942 | ||
4943 | /* | |
4944 | * scheduling support | |
4945 | */ | |
4946 | .get_frame_number = xhci_get_frame, | |
4947 | ||
4948 | /* | |
4949 | * root hub support | |
4950 | */ | |
4951 | .hub_control = xhci_hub_control, | |
4952 | .hub_status_data = xhci_hub_status_data, | |
4953 | .bus_suspend = xhci_bus_suspend, | |
4954 | .bus_resume = xhci_bus_resume, | |
4955 | ||
4956 | /* | |
4957 | * call back when device connected and addressed | |
4958 | */ | |
4959 | .update_device = xhci_update_device, | |
4960 | .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm, | |
4961 | .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout, | |
4962 | .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout, | |
4963 | .find_raw_port_number = xhci_find_raw_port_number, | |
4964 | }; | |
4965 | ||
cd33a321 RQ |
4966 | void xhci_init_driver(struct hc_driver *drv, |
4967 | const struct xhci_driver_overrides *over) | |
1885d9a3 | 4968 | { |
cd33a321 RQ |
4969 | BUG_ON(!over); |
4970 | ||
4971 | /* Copy the generic table to drv then apply the overrides */ | |
1885d9a3 | 4972 | *drv = xhci_hc_driver; |
cd33a321 RQ |
4973 | |
4974 | if (over) { | |
4975 | drv->hcd_priv_size += over->extra_priv_size; | |
4976 | if (over->reset) | |
4977 | drv->reset = over->reset; | |
4978 | if (over->start) | |
4979 | drv->start = over->start; | |
4980 | } | |
1885d9a3 AB |
4981 | } |
4982 | EXPORT_SYMBOL_GPL(xhci_init_driver); | |
4983 | ||
66d4eadd SS |
4984 | MODULE_DESCRIPTION(DRIVER_DESC); |
4985 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
4986 | MODULE_LICENSE("GPL"); | |
4987 | ||
4988 | static int __init xhci_hcd_init(void) | |
4989 | { | |
98441973 SS |
4990 | /* |
4991 | * Check the compiler generated sizes of structures that must be laid | |
4992 | * out in specific ways for hardware access. | |
4993 | */ | |
4994 | BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8); | |
4995 | BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8); | |
4996 | BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8); | |
4997 | /* xhci_device_control has eight fields, and also | |
4998 | * embeds one xhci_slot_ctx and 31 xhci_ep_ctx | |
4999 | */ | |
98441973 SS |
5000 | BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8); |
5001 | BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8); | |
5002 | BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8); | |
04abb6de | 5003 | BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8); |
98441973 SS |
5004 | BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8); |
5005 | /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */ | |
5006 | BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8); | |
1eaf35e4 ON |
5007 | |
5008 | if (usb_disabled()) | |
5009 | return -ENODEV; | |
5010 | ||
02b6fdc2 LB |
5011 | xhci_debugfs_create_root(); |
5012 | ||
66d4eadd SS |
5013 | return 0; |
5014 | } | |
b04c846c AD |
5015 | |
5016 | /* | |
5017 | * If an init function is provided, an exit function must also be provided | |
5018 | * to allow module unload. | |
5019 | */ | |
02b6fdc2 LB |
5020 | static void __exit xhci_hcd_fini(void) |
5021 | { | |
5022 | xhci_debugfs_remove_root(); | |
5023 | } | |
b04c846c | 5024 | |
66d4eadd | 5025 | module_init(xhci_hcd_init); |
b04c846c | 5026 | module_exit(xhci_hcd_fini); |