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74c68741 SS |
2 | /* |
3 | * xHCI host controller driver | |
4 | * | |
5 | * Copyright (C) 2008 Intel Corp. | |
6 | * | |
7 | * Author: Sarah Sharp | |
8 | * Some code borrowed from the Linux EHCI driver. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | * for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software Foundation, | |
21 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | #ifndef __LINUX_XHCI_HCD_H | |
25 | #define __LINUX_XHCI_HCD_H | |
26 | ||
27 | #include <linux/usb.h> | |
7f84eef0 | 28 | #include <linux/timer.h> |
8e595a5d | 29 | #include <linux/kernel.h> |
27729aad | 30 | #include <linux/usb/hcd.h> |
74c68741 | 31 | |
74c68741 SS |
32 | /* Code sharing between pci-quirks and xhci hcd */ |
33 | #include "xhci-ext-caps.h" | |
c41136b0 | 34 | #include "pci-quirks.h" |
74c68741 SS |
35 | |
36 | /* xHCI PCI Configuration Registers */ | |
37 | #define XHCI_SBRN_OFFSET (0x60) | |
38 | ||
66d4eadd SS |
39 | /* Max number of USB devices for any host controller - limit in section 6.1 */ |
40 | #define MAX_HC_SLOTS 256 | |
0f2a7930 SS |
41 | /* Section 5.3.3 - MaxPorts */ |
42 | #define MAX_HC_PORTS 127 | |
66d4eadd | 43 | |
74c68741 SS |
44 | /* |
45 | * xHCI register interface. | |
46 | * This corresponds to the eXtensible Host Controller Interface (xHCI) | |
47 | * Revision 0.95 specification | |
74c68741 SS |
48 | */ |
49 | ||
50 | /** | |
51 | * struct xhci_cap_regs - xHCI Host Controller Capability Registers. | |
52 | * @hc_capbase: length of the capabilities register and HC version number | |
53 | * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 | |
54 | * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 | |
55 | * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 | |
56 | * @hcc_params: HCCPARAMS - Capability Parameters | |
57 | * @db_off: DBOFF - Doorbell array offset | |
58 | * @run_regs_off: RTSOFF - Runtime register space offset | |
04abb6de | 59 | * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only |
74c68741 SS |
60 | */ |
61 | struct xhci_cap_regs { | |
28ccd296 ME |
62 | __le32 hc_capbase; |
63 | __le32 hcs_params1; | |
64 | __le32 hcs_params2; | |
65 | __le32 hcs_params3; | |
66 | __le32 hcc_params; | |
67 | __le32 db_off; | |
68 | __le32 run_regs_off; | |
04abb6de | 69 | __le32 hcc_params2; /* xhci 1.1 */ |
74c68741 | 70 | /* Reserved up to (CAPLENGTH - 0x1C) */ |
98441973 | 71 | }; |
74c68741 SS |
72 | |
73 | /* hc_capbase bitmasks */ | |
74 | /* bits 7:0 - how long is the Capabilities register */ | |
75 | #define HC_LENGTH(p) XHCI_HC_LENGTH(p) | |
76 | /* bits 31:16 */ | |
77 | #define HC_VERSION(p) (((p) >> 16) & 0xffff) | |
78 | ||
79 | /* HCSPARAMS1 - hcs_params1 - bitmasks */ | |
80 | /* bits 0:7, Max Device Slots */ | |
81 | #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) | |
82 | #define HCS_SLOTS_MASK 0xff | |
83 | /* bits 8:18, Max Interrupters */ | |
84 | #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) | |
85 | /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ | |
86 | #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) | |
87 | ||
88 | /* HCSPARAMS2 - hcs_params2 - bitmasks */ | |
89 | /* bits 0:3, frames or uframes that SW needs to queue transactions | |
90 | * ahead of the HW to meet periodic deadlines */ | |
91 | #define HCS_IST(p) (((p) >> 0) & 0xf) | |
92 | /* bits 4:7, max number of Event Ring segments */ | |
93 | #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) | |
6596a926 | 94 | /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ |
74c68741 | 95 | /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ |
6596a926 MN |
96 | /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ |
97 | #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) | |
74c68741 SS |
98 | |
99 | /* HCSPARAMS3 - hcs_params3 - bitmasks */ | |
100 | /* bits 0:7, Max U1 to U0 latency for the roothub ports */ | |
101 | #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) | |
102 | /* bits 16:31, Max U2 to U0 latency for the roothub ports */ | |
103 | #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) | |
104 | ||
105 | /* HCCPARAMS - hcc_params - bitmasks */ | |
106 | /* true: HC can use 64-bit address pointers */ | |
107 | #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) | |
108 | /* true: HC can do bandwidth negotiation */ | |
109 | #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) | |
110 | /* true: HC uses 64-byte Device Context structures | |
111 | * FIXME 64-byte context structures aren't supported yet. | |
112 | */ | |
113 | #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) | |
114 | /* true: HC has port power switches */ | |
115 | #define HCC_PPC(p) ((p) & (1 << 3)) | |
116 | /* true: HC has port indicators */ | |
117 | #define HCS_INDICATOR(p) ((p) & (1 << 4)) | |
118 | /* true: HC has Light HC Reset Capability */ | |
119 | #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) | |
120 | /* true: HC supports latency tolerance messaging */ | |
121 | #define HCC_LTC(p) ((p) & (1 << 6)) | |
122 | /* true: no secondary Stream ID Support */ | |
123 | #define HCC_NSS(p) ((p) & (1 << 7)) | |
40a3b775 LB |
124 | /* true: HC supports Stopped - Short Packet */ |
125 | #define HCC_SPC(p) ((p) & (1 << 9)) | |
79b8094f LB |
126 | /* true: HC has Contiguous Frame ID Capability */ |
127 | #define HCC_CFC(p) ((p) & (1 << 11)) | |
74c68741 | 128 | /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ |
8df75f42 | 129 | #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) |
74c68741 SS |
130 | /* Extended Capabilities pointer from PCI base - section 5.3.6 */ |
131 | #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) | |
132 | ||
133 | /* db_off bitmask - bits 0:1 reserved */ | |
134 | #define DBOFF_MASK (~0x3) | |
135 | ||
136 | /* run_regs_off bitmask - bits 0:4 reserved */ | |
137 | #define RTSOFF_MASK (~0x1f) | |
138 | ||
04abb6de LB |
139 | /* HCCPARAMS2 - hcc_params2 - bitmasks */ |
140 | /* true: HC supports U3 entry Capability */ | |
141 | #define HCC2_U3C(p) ((p) & (1 << 0)) | |
142 | /* true: HC supports Configure endpoint command Max exit latency too large */ | |
143 | #define HCC2_CMC(p) ((p) & (1 << 1)) | |
144 | /* true: HC supports Force Save context Capability */ | |
145 | #define HCC2_FSC(p) ((p) & (1 << 2)) | |
146 | /* true: HC supports Compliance Transition Capability */ | |
147 | #define HCC2_CTC(p) ((p) & (1 << 3)) | |
148 | /* true: HC support Large ESIT payload Capability > 48k */ | |
149 | #define HCC2_LEC(p) ((p) & (1 << 4)) | |
150 | /* true: HC support Configuration Information Capability */ | |
151 | #define HCC2_CIC(p) ((p) & (1 << 5)) | |
152 | /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ | |
153 | #define HCC2_ETC(p) ((p) & (1 << 6)) | |
74c68741 SS |
154 | |
155 | /* Number of registers per port */ | |
156 | #define NUM_PORT_REGS 4 | |
157 | ||
b6e76371 MN |
158 | #define PORTSC 0 |
159 | #define PORTPMSC 1 | |
160 | #define PORTLI 2 | |
161 | #define PORTHLPMC 3 | |
162 | ||
74c68741 SS |
163 | /** |
164 | * struct xhci_op_regs - xHCI Host Controller Operational Registers. | |
165 | * @command: USBCMD - xHC command register | |
166 | * @status: USBSTS - xHC status register | |
167 | * @page_size: This indicates the page size that the host controller | |
168 | * supports. If bit n is set, the HC supports a page size | |
169 | * of 2^(n+12), up to a 128MB page size. | |
170 | * 4K is the minimum page size. | |
171 | * @cmd_ring: CRP - 64-bit Command Ring Pointer | |
172 | * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer | |
173 | * @config_reg: CONFIG - Configure Register | |
174 | * @port_status_base: PORTSCn - base address for Port Status and Control | |
175 | * Each port has a Port Status and Control register, | |
176 | * followed by a Port Power Management Status and Control | |
177 | * register, a Port Link Info register, and a reserved | |
178 | * register. | |
179 | * @port_power_base: PORTPMSCn - base address for | |
180 | * Port Power Management Status and Control | |
181 | * @port_link_base: PORTLIn - base address for Port Link Info (current | |
182 | * Link PM state and control) for USB 2.1 and USB 3.0 | |
183 | * devices. | |
184 | */ | |
185 | struct xhci_op_regs { | |
28ccd296 ME |
186 | __le32 command; |
187 | __le32 status; | |
188 | __le32 page_size; | |
189 | __le32 reserved1; | |
190 | __le32 reserved2; | |
191 | __le32 dev_notification; | |
192 | __le64 cmd_ring; | |
74c68741 | 193 | /* rsvd: offset 0x20-2F */ |
28ccd296 ME |
194 | __le32 reserved3[4]; |
195 | __le64 dcbaa_ptr; | |
196 | __le32 config_reg; | |
74c68741 | 197 | /* rsvd: offset 0x3C-3FF */ |
28ccd296 | 198 | __le32 reserved4[241]; |
74c68741 | 199 | /* port 1 registers, which serve as a base address for other ports */ |
28ccd296 ME |
200 | __le32 port_status_base; |
201 | __le32 port_power_base; | |
202 | __le32 port_link_base; | |
203 | __le32 reserved5; | |
74c68741 | 204 | /* registers for ports 2-255 */ |
28ccd296 | 205 | __le32 reserved6[NUM_PORT_REGS*254]; |
98441973 | 206 | }; |
74c68741 SS |
207 | |
208 | /* USBCMD - USB command - command bitmasks */ | |
209 | /* start/stop HC execution - do not write unless HC is halted*/ | |
210 | #define CMD_RUN XHCI_CMD_RUN | |
211 | /* Reset HC - resets internal HC state machine and all registers (except | |
212 | * PCI config regs). HC does NOT drive a USB reset on the downstream ports. | |
213 | * The xHCI driver must reinitialize the xHC after setting this bit. | |
214 | */ | |
215 | #define CMD_RESET (1 << 1) | |
216 | /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ | |
217 | #define CMD_EIE XHCI_CMD_EIE | |
218 | /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ | |
219 | #define CMD_HSEIE XHCI_CMD_HSEIE | |
220 | /* bits 4:6 are reserved (and should be preserved on writes). */ | |
221 | /* light reset (port status stays unchanged) - reset completed when this is 0 */ | |
222 | #define CMD_LRESET (1 << 7) | |
5535b1d5 | 223 | /* host controller save/restore state. */ |
74c68741 SS |
224 | #define CMD_CSS (1 << 8) |
225 | #define CMD_CRS (1 << 9) | |
226 | /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ | |
227 | #define CMD_EWE XHCI_CMD_EWE | |
228 | /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root | |
229 | * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. | |
230 | * '0' means the xHC can power it off if all ports are in the disconnect, | |
231 | * disabled, or powered-off state. | |
232 | */ | |
233 | #define CMD_PM_INDEX (1 << 11) | |
234 | /* bits 12:31 are reserved (and should be preserved on writes). */ | |
235 | ||
4e833c0b | 236 | /* IMAN - Interrupt Management Register */ |
f8264340 DT |
237 | #define IMAN_IE (1 << 1) |
238 | #define IMAN_IP (1 << 0) | |
4e833c0b | 239 | |
74c68741 SS |
240 | /* USBSTS - USB status - status bitmasks */ |
241 | /* HC not running - set to 1 when run/stop bit is cleared. */ | |
242 | #define STS_HALT XHCI_STS_HALT | |
243 | /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ | |
244 | #define STS_FATAL (1 << 2) | |
245 | /* event interrupt - clear this prior to clearing any IP flags in IR set*/ | |
246 | #define STS_EINT (1 << 3) | |
247 | /* port change detect */ | |
248 | #define STS_PORT (1 << 4) | |
249 | /* bits 5:7 reserved and zeroed */ | |
250 | /* save state status - '1' means xHC is saving state */ | |
251 | #define STS_SAVE (1 << 8) | |
252 | /* restore state status - '1' means xHC is restoring state */ | |
253 | #define STS_RESTORE (1 << 9) | |
254 | /* true: save or restore error */ | |
255 | #define STS_SRE (1 << 10) | |
256 | /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ | |
257 | #define STS_CNR XHCI_STS_CNR | |
258 | /* true: internal Host Controller Error - SW needs to reset and reinitialize */ | |
259 | #define STS_HCE (1 << 12) | |
260 | /* bits 13:31 reserved and should be preserved */ | |
261 | ||
262 | /* | |
263 | * DNCTRL - Device Notification Control Register - dev_notification bitmasks | |
264 | * Generate a device notification event when the HC sees a transaction with a | |
265 | * notification type that matches a bit set in this bit field. | |
266 | */ | |
267 | #define DEV_NOTE_MASK (0xffff) | |
5a6c2f3f | 268 | #define ENABLE_DEV_NOTE(x) (1 << (x)) |
74c68741 SS |
269 | /* Most of the device notification types should only be used for debug. |
270 | * SW does need to pay attention to function wake notifications. | |
271 | */ | |
272 | #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) | |
273 | ||
0ebbab37 SS |
274 | /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ |
275 | /* bit 0 is the command ring cycle state */ | |
276 | /* stop ring operation after completion of the currently executing command */ | |
277 | #define CMD_RING_PAUSE (1 << 1) | |
278 | /* stop ring immediately - abort the currently executing command */ | |
279 | #define CMD_RING_ABORT (1 << 2) | |
280 | /* true: command ring is running */ | |
281 | #define CMD_RING_RUNNING (1 << 3) | |
282 | /* bits 4:5 reserved and should be preserved */ | |
283 | /* Command Ring pointer - bit mask for the lower 32 bits. */ | |
8e595a5d | 284 | #define CMD_RING_RSVD_BITS (0x3f) |
0ebbab37 | 285 | |
74c68741 SS |
286 | /* CONFIG - Configure Register - config_reg bitmasks */ |
287 | /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ | |
288 | #define MAX_DEVS(p) ((p) & 0xff) | |
04abb6de LB |
289 | /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ |
290 | #define CONFIG_U3E (1 << 8) | |
291 | /* bit 9: Configuration Information Enable, xhci 1.1 */ | |
292 | #define CONFIG_CIE (1 << 9) | |
293 | /* bits 10:31 - reserved and should be preserved */ | |
74c68741 SS |
294 | |
295 | /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ | |
296 | /* true: device connected */ | |
297 | #define PORT_CONNECT (1 << 0) | |
298 | /* true: port enabled */ | |
299 | #define PORT_PE (1 << 1) | |
300 | /* bit 2 reserved and zeroed */ | |
301 | /* true: port has an over-current condition */ | |
302 | #define PORT_OC (1 << 3) | |
303 | /* true: port reset signaling asserted */ | |
304 | #define PORT_RESET (1 << 4) | |
305 | /* Port Link State - bits 5:8 | |
306 | * A read gives the current link PM state of the port, | |
307 | * a write with Link State Write Strobe set sets the link state. | |
308 | */ | |
be88fe4f AX |
309 | #define PORT_PLS_MASK (0xf << 5) |
310 | #define XDEV_U0 (0x0 << 5) | |
9574323c | 311 | #define XDEV_U2 (0x2 << 5) |
be88fe4f | 312 | #define XDEV_U3 (0x3 << 5) |
fac4271d | 313 | #define XDEV_INACTIVE (0x6 << 5) |
be88fe4f | 314 | #define XDEV_RESUME (0xf << 5) |
74c68741 SS |
315 | /* true: port has power (see HCC_PPC) */ |
316 | #define PORT_POWER (1 << 9) | |
317 | /* bits 10:13 indicate device speed: | |
318 | * 0 - undefined speed - port hasn't be initialized by a reset yet | |
319 | * 1 - full speed | |
320 | * 2 - low speed | |
321 | * 3 - high speed | |
322 | * 4 - super speed | |
323 | * 5-15 reserved | |
324 | */ | |
3ffbba95 SS |
325 | #define DEV_SPEED_MASK (0xf << 10) |
326 | #define XDEV_FS (0x1 << 10) | |
327 | #define XDEV_LS (0x2 << 10) | |
328 | #define XDEV_HS (0x3 << 10) | |
329 | #define XDEV_SS (0x4 << 10) | |
74c68741 | 330 | #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) |
3ffbba95 SS |
331 | #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) |
332 | #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) | |
333 | #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) | |
334 | #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) | |
335 | /* Bits 20:23 in the Slot Context are the speed for the device */ | |
336 | #define SLOT_SPEED_FS (XDEV_FS << 10) | |
337 | #define SLOT_SPEED_LS (XDEV_LS << 10) | |
338 | #define SLOT_SPEED_HS (XDEV_HS << 10) | |
339 | #define SLOT_SPEED_SS (XDEV_SS << 10) | |
74c68741 SS |
340 | /* Port Indicator Control */ |
341 | #define PORT_LED_OFF (0 << 14) | |
342 | #define PORT_LED_AMBER (1 << 14) | |
343 | #define PORT_LED_GREEN (2 << 14) | |
344 | #define PORT_LED_MASK (3 << 14) | |
345 | /* Port Link State Write Strobe - set this when changing link state */ | |
346 | #define PORT_LINK_STROBE (1 << 16) | |
347 | /* true: connect status change */ | |
348 | #define PORT_CSC (1 << 17) | |
349 | /* true: port enable change */ | |
350 | #define PORT_PEC (1 << 18) | |
351 | /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port | |
352 | * into an enabled state, and the device into the default state. A "warm" reset | |
353 | * also resets the link, forcing the device through the link training sequence. | |
354 | * SW can also look at the Port Reset register to see when warm reset is done. | |
355 | */ | |
356 | #define PORT_WRC (1 << 19) | |
357 | /* true: over-current change */ | |
358 | #define PORT_OCC (1 << 20) | |
359 | /* true: reset change - 1 to 0 transition of PORT_RESET */ | |
360 | #define PORT_RC (1 << 21) | |
361 | /* port link status change - set on some port link state transitions: | |
362 | * Transition Reason | |
363 | * ------------------------------------------------------------------------------ | |
364 | * - U3 to Resume Wakeup signaling from a device | |
365 | * - Resume to Recovery to U0 USB 3.0 device resume | |
366 | * - Resume to U0 USB 2.0 device resume | |
367 | * - U3 to Recovery to U0 Software resume of USB 3.0 device complete | |
368 | * - U3 to U0 Software resume of USB 2.0 device complete | |
369 | * - U2 to U0 L1 resume of USB 2.1 device complete | |
370 | * - U0 to U0 (???) L1 entry rejection by USB 2.1 device | |
371 | * - U0 to disabled L1 entry error with USB 2.1 device | |
372 | * - Any state to inactive Error on USB 3.0 port | |
373 | */ | |
374 | #define PORT_PLC (1 << 22) | |
375 | /* port configure error change - port failed to configure its link partner */ | |
376 | #define PORT_CEC (1 << 23) | |
8bea2bd3 SL |
377 | /* Cold Attach Status - xHC can set this bit to report device attached during |
378 | * Sx state. Warm port reset should be perfomed to clear this bit and move port | |
379 | * to connected state. | |
380 | */ | |
381 | #define PORT_CAS (1 << 24) | |
74c68741 SS |
382 | /* wake on connect (enable) */ |
383 | #define PORT_WKCONN_E (1 << 25) | |
384 | /* wake on disconnect (enable) */ | |
385 | #define PORT_WKDISC_E (1 << 26) | |
386 | /* wake on over-current (enable) */ | |
387 | #define PORT_WKOC_E (1 << 27) | |
388 | /* bits 28:29 reserved */ | |
e1fd1dc8 | 389 | /* true: device is non-removable - for USB 3.0 roothub emulation */ |
74c68741 SS |
390 | #define PORT_DEV_REMOVE (1 << 30) |
391 | /* Initiate a warm port reset - complete when PORT_WRC is '1' */ | |
392 | #define PORT_WR (1 << 31) | |
393 | ||
22e04870 DC |
394 | /* We mark duplicate entries with -1 */ |
395 | #define DUPLICATE_ENTRY ((u8)(-1)) | |
396 | ||
74c68741 SS |
397 | /* Port Power Management Status and Control - port_power_base bitmasks */ |
398 | /* Inactivity timer value for transitions into U1, in microseconds. | |
399 | * Timeout can be up to 127us. 0xFF means an infinite timeout. | |
400 | */ | |
401 | #define PORT_U1_TIMEOUT(p) ((p) & 0xff) | |
797b0ca5 | 402 | #define PORT_U1_TIMEOUT_MASK 0xff |
74c68741 SS |
403 | /* Inactivity timer value for transitions into U2 */ |
404 | #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) | |
797b0ca5 | 405 | #define PORT_U2_TIMEOUT_MASK (0xff << 8) |
74c68741 SS |
406 | /* Bits 24:31 for port testing */ |
407 | ||
9777e3ce | 408 | /* USB2 Protocol PORTSPMSC */ |
9574323c AX |
409 | #define PORT_L1S_MASK 7 |
410 | #define PORT_L1S_SUCCESS 1 | |
411 | #define PORT_RWE (1 << 3) | |
412 | #define PORT_HIRD(p) (((p) & 0xf) << 4) | |
65580b43 | 413 | #define PORT_HIRD_MASK (0xf << 4) |
58e21f73 | 414 | #define PORT_L1DS_MASK (0xff << 8) |
9574323c | 415 | #define PORT_L1DS(p) (((p) & 0xff) << 8) |
65580b43 | 416 | #define PORT_HLE (1 << 16) |
74c68741 | 417 | |
a558ccdc MN |
418 | |
419 | /* USB2 Protocol PORTHLPMC */ | |
420 | #define PORT_HIRDM(p)((p) & 3) | |
421 | #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) | |
422 | #define PORT_BESLD(p)(((p) & 0xf) << 10) | |
423 | ||
424 | /* use 512 microseconds as USB2 LPM L1 default timeout. */ | |
425 | #define XHCI_L1_TIMEOUT 512 | |
426 | ||
427 | /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. | |
428 | * Safe to use with mixed HIRD and BESL systems (host and device) and is used | |
429 | * by other operating systems. | |
430 | * | |
431 | * XHCI 1.0 errata 8/14/12 Table 13 notes: | |
432 | * "Software should choose xHC BESL/BESLD field values that do not violate a | |
433 | * device's resume latency requirements, | |
434 | * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, | |
435 | * or not program values < '4' if BLC = '0' and a BESL device is attached. | |
436 | */ | |
437 | #define XHCI_DEFAULT_BESL 4 | |
438 | ||
74c68741 | 439 | /** |
98441973 | 440 | * struct xhci_intr_reg - Interrupt Register Set |
74c68741 SS |
441 | * @irq_pending: IMAN - Interrupt Management Register. Used to enable |
442 | * interrupts and check for pending interrupts. | |
443 | * @irq_control: IMOD - Interrupt Moderation Register. | |
444 | * Used to throttle interrupts. | |
445 | * @erst_size: Number of segments in the Event Ring Segment Table (ERST). | |
446 | * @erst_base: ERST base address. | |
447 | * @erst_dequeue: Event ring dequeue pointer. | |
448 | * | |
449 | * Each interrupter (defined by a MSI-X vector) has an event ring and an Event | |
450 | * Ring Segment Table (ERST) associated with it. The event ring is comprised of | |
451 | * multiple segments of the same size. The HC places events on the ring and | |
452 | * "updates the Cycle bit in the TRBs to indicate to software the current | |
453 | * position of the Enqueue Pointer." The HCD (Linux) processes those events and | |
454 | * updates the dequeue pointer. | |
455 | */ | |
98441973 | 456 | struct xhci_intr_reg { |
28ccd296 ME |
457 | __le32 irq_pending; |
458 | __le32 irq_control; | |
459 | __le32 erst_size; | |
460 | __le32 rsvd; | |
461 | __le64 erst_base; | |
462 | __le64 erst_dequeue; | |
98441973 | 463 | }; |
74c68741 | 464 | |
66d4eadd | 465 | /* irq_pending bitmasks */ |
74c68741 | 466 | #define ER_IRQ_PENDING(p) ((p) & 0x1) |
66d4eadd | 467 | /* bits 2:31 need to be preserved */ |
7f84eef0 | 468 | /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ |
66d4eadd SS |
469 | #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) |
470 | #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) | |
471 | #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) | |
472 | ||
473 | /* irq_control bitmasks */ | |
474 | /* Minimum interval between interrupts (in 250ns intervals). The interval | |
475 | * between interrupts will be longer if there are no events on the event ring. | |
476 | * Default is 4000 (1 ms). | |
477 | */ | |
478 | #define ER_IRQ_INTERVAL_MASK (0xffff) | |
479 | /* Counter used to count down the time to the next interrupt - HW use only */ | |
480 | #define ER_IRQ_COUNTER_MASK (0xffff << 16) | |
481 | ||
482 | /* erst_size bitmasks */ | |
74c68741 | 483 | /* Preserve bits 16:31 of erst_size */ |
66d4eadd SS |
484 | #define ERST_SIZE_MASK (0xffff << 16) |
485 | ||
486 | /* erst_dequeue bitmasks */ | |
487 | /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) | |
488 | * where the current dequeue pointer lies. This is an optional HW hint. | |
489 | */ | |
490 | #define ERST_DESI_MASK (0x7) | |
491 | /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by | |
492 | * a work queue (or delayed service routine)? | |
493 | */ | |
494 | #define ERST_EHB (1 << 3) | |
0ebbab37 | 495 | #define ERST_PTR_MASK (0xf) |
74c68741 SS |
496 | |
497 | /** | |
498 | * struct xhci_run_regs | |
499 | * @microframe_index: | |
500 | * MFINDEX - current microframe number | |
501 | * | |
502 | * Section 5.5 Host Controller Runtime Registers: | |
503 | * "Software should read and write these registers using only Dword (32 bit) | |
504 | * or larger accesses" | |
505 | */ | |
506 | struct xhci_run_regs { | |
28ccd296 ME |
507 | __le32 microframe_index; |
508 | __le32 rsvd[7]; | |
98441973 SS |
509 | struct xhci_intr_reg ir_set[128]; |
510 | }; | |
74c68741 | 511 | |
0ebbab37 SS |
512 | /** |
513 | * struct doorbell_array | |
514 | * | |
50d64676 MW |
515 | * Bits 0 - 7: Endpoint target |
516 | * Bits 8 - 15: RsvdZ | |
517 | * Bits 16 - 31: Stream ID | |
518 | * | |
0ebbab37 SS |
519 | * Section 5.6 |
520 | */ | |
521 | struct xhci_doorbell_array { | |
28ccd296 | 522 | __le32 doorbell[256]; |
98441973 | 523 | }; |
0ebbab37 | 524 | |
50d64676 MW |
525 | #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) |
526 | #define DB_VALUE_HOST 0x00000000 | |
0ebbab37 | 527 | |
da6699ce SS |
528 | /** |
529 | * struct xhci_protocol_caps | |
530 | * @revision: major revision, minor revision, capability ID, | |
531 | * and next capability pointer. | |
532 | * @name_string: Four ASCII characters to say which spec this xHC | |
533 | * follows, typically "USB ". | |
534 | * @port_info: Port offset, count, and protocol-defined information. | |
535 | */ | |
536 | struct xhci_protocol_caps { | |
537 | u32 revision; | |
538 | u32 name_string; | |
539 | u32 port_info; | |
540 | }; | |
541 | ||
542 | #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) | |
543 | #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) | |
544 | #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) | |
545 | ||
d115b048 JY |
546 | /** |
547 | * struct xhci_container_ctx | |
548 | * @type: Type of context. Used to calculated offsets to contained contexts. | |
549 | * @size: Size of the context data | |
550 | * @bytes: The raw context data given to HW | |
551 | * @dma: dma address of the bytes | |
552 | * | |
553 | * Represents either a Device or Input context. Holds a pointer to the raw | |
554 | * memory used for the context (bytes) and dma address of it (dma). | |
555 | */ | |
556 | struct xhci_container_ctx { | |
557 | unsigned type; | |
558 | #define XHCI_CTX_TYPE_DEVICE 0x1 | |
559 | #define XHCI_CTX_TYPE_INPUT 0x2 | |
560 | ||
561 | int size; | |
562 | ||
563 | u8 *bytes; | |
564 | dma_addr_t dma; | |
565 | }; | |
566 | ||
a74588f9 SS |
567 | /** |
568 | * struct xhci_slot_ctx | |
569 | * @dev_info: Route string, device speed, hub info, and last valid endpoint | |
570 | * @dev_info2: Max exit latency for device number, root hub port number | |
571 | * @tt_info: tt_info is used to construct split transaction tokens | |
572 | * @dev_state: slot state and device address | |
573 | * | |
574 | * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context | |
575 | * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes | |
576 | * reserved at the end of the slot context for HC internal use. | |
577 | */ | |
578 | struct xhci_slot_ctx { | |
28ccd296 ME |
579 | __le32 dev_info; |
580 | __le32 dev_info2; | |
581 | __le32 tt_info; | |
582 | __le32 dev_state; | |
a74588f9 | 583 | /* offset 0x10 to 0x1f reserved for HC internal use */ |
28ccd296 | 584 | __le32 reserved[4]; |
98441973 | 585 | }; |
a74588f9 SS |
586 | |
587 | /* dev_info bitmasks */ | |
588 | /* Route String - 0:19 */ | |
589 | #define ROUTE_STRING_MASK (0xfffff) | |
590 | /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ | |
591 | #define DEV_SPEED (0xf << 20) | |
592 | /* bit 24 reserved */ | |
593 | /* Is this LS/FS device connected through a HS hub? - bit 25 */ | |
594 | #define DEV_MTT (0x1 << 25) | |
595 | /* Set if the device is a hub - bit 26 */ | |
596 | #define DEV_HUB (0x1 << 26) | |
597 | /* Index of the last valid endpoint context in this device context - 27:31 */ | |
3ffbba95 SS |
598 | #define LAST_CTX_MASK (0x1f << 27) |
599 | #define LAST_CTX(p) ((p) << 27) | |
600 | #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) | |
3ffbba95 SS |
601 | #define SLOT_FLAG (1 << 0) |
602 | #define EP0_FLAG (1 << 1) | |
a74588f9 SS |
603 | |
604 | /* dev_info2 bitmasks */ | |
605 | /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ | |
606 | #define MAX_EXIT (0xffff) | |
607 | /* Root hub port number that is needed to access the USB device */ | |
3ffbba95 | 608 | #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) |
be88fe4f | 609 | #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) |
ac1c1b7f SS |
610 | /* Maximum number of ports under a hub device */ |
611 | #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) | |
a74588f9 SS |
612 | |
613 | /* tt_info bitmasks */ | |
614 | /* | |
615 | * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub | |
616 | * The Slot ID of the hub that isolates the high speed signaling from | |
617 | * this low or full-speed device. '0' if attached to root hub port. | |
618 | */ | |
619 | #define TT_SLOT (0xff) | |
620 | /* | |
621 | * The number of the downstream facing port of the high-speed hub | |
622 | * '0' if the device is not low or full speed. | |
623 | */ | |
624 | #define TT_PORT (0xff << 8) | |
ac1c1b7f | 625 | #define TT_THINK_TIME(p) (((p) & 0x3) << 16) |
a74588f9 SS |
626 | |
627 | /* dev_state bitmasks */ | |
628 | /* USB device address - assigned by the HC */ | |
3ffbba95 | 629 | #define DEV_ADDR_MASK (0xff) |
a74588f9 SS |
630 | /* bits 8:26 reserved */ |
631 | /* Slot state */ | |
632 | #define SLOT_STATE (0x1f << 27) | |
ae636747 | 633 | #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) |
a74588f9 | 634 | |
e2b02177 ML |
635 | #define SLOT_STATE_DISABLED 0 |
636 | #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED | |
637 | #define SLOT_STATE_DEFAULT 1 | |
638 | #define SLOT_STATE_ADDRESSED 2 | |
639 | #define SLOT_STATE_CONFIGURED 3 | |
a74588f9 SS |
640 | |
641 | /** | |
642 | * struct xhci_ep_ctx | |
643 | * @ep_info: endpoint state, streams, mult, and interval information. | |
644 | * @ep_info2: information on endpoint type, max packet size, max burst size, | |
645 | * error count, and whether the HC will force an event for all | |
646 | * transactions. | |
3ffbba95 SS |
647 | * @deq: 64-bit ring dequeue pointer address. If the endpoint only |
648 | * defines one stream, this points to the endpoint transfer ring. | |
649 | * Otherwise, it points to a stream context array, which has a | |
650 | * ring pointer for each flow. | |
651 | * @tx_info: | |
652 | * Average TRB lengths for the endpoint ring and | |
653 | * max payload within an Endpoint Service Interval Time (ESIT). | |
a74588f9 SS |
654 | * |
655 | * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context | |
656 | * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes | |
657 | * reserved at the end of the endpoint context for HC internal use. | |
658 | */ | |
659 | struct xhci_ep_ctx { | |
28ccd296 ME |
660 | __le32 ep_info; |
661 | __le32 ep_info2; | |
662 | __le64 deq; | |
663 | __le32 tx_info; | |
a74588f9 | 664 | /* offset 0x14 - 0x1f reserved for HC internal use */ |
28ccd296 | 665 | __le32 reserved[3]; |
98441973 | 666 | }; |
a74588f9 SS |
667 | |
668 | /* ep_info bitmasks */ | |
669 | /* | |
670 | * Endpoint State - bits 0:2 | |
671 | * 0 - disabled | |
672 | * 1 - running | |
673 | * 2 - halted due to halt condition - ok to manipulate endpoint ring | |
674 | * 3 - stopped | |
675 | * 4 - TRB error | |
676 | * 5-7 - reserved | |
677 | */ | |
d0e96f5a SS |
678 | #define EP_STATE_MASK (0xf) |
679 | #define EP_STATE_DISABLED 0 | |
680 | #define EP_STATE_RUNNING 1 | |
681 | #define EP_STATE_HALTED 2 | |
682 | #define EP_STATE_STOPPED 3 | |
683 | #define EP_STATE_ERROR 4 | |
a74588f9 | 684 | /* Mult - Max number of burtst within an interval, in EP companion desc. */ |
5a6c2f3f | 685 | #define EP_MULT(p) (((p) & 0x3) << 8) |
9af5d71d | 686 | #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) |
a74588f9 SS |
687 | /* bits 10:14 are Max Primary Streams */ |
688 | /* bit 15 is Linear Stream Array */ | |
689 | /* Interval - period between requests to an endpoint - 125u increments. */ | |
5a6c2f3f | 690 | #define EP_INTERVAL(p) (((p) & 0xff) << 16) |
624defa1 | 691 | #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) |
9af5d71d | 692 | #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) |
8df75f42 SS |
693 | #define EP_MAXPSTREAMS_MASK (0x1f << 10) |
694 | #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) | |
695 | /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ | |
696 | #define EP_HAS_LSA (1 << 15) | |
a74588f9 SS |
697 | |
698 | /* ep_info2 bitmasks */ | |
699 | /* | |
700 | * Force Event - generate transfer events for all TRBs for this endpoint | |
701 | * This will tell the HC to ignore the IOC and ISP flags (for debugging only). | |
702 | */ | |
703 | #define FORCE_EVENT (0x1) | |
704 | #define ERROR_COUNT(p) (((p) & 0x3) << 1) | |
82d1009f | 705 | #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) |
a74588f9 SS |
706 | #define EP_TYPE(p) ((p) << 3) |
707 | #define ISOC_OUT_EP 1 | |
708 | #define BULK_OUT_EP 2 | |
709 | #define INT_OUT_EP 3 | |
710 | #define CTRL_EP 4 | |
711 | #define ISOC_IN_EP 5 | |
712 | #define BULK_IN_EP 6 | |
713 | #define INT_IN_EP 7 | |
714 | /* bit 6 reserved */ | |
715 | /* bit 7 is Host Initiate Disable - for disabling stream selection */ | |
716 | #define MAX_BURST(p) (((p)&0xff) << 8) | |
9af5d71d | 717 | #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) |
a74588f9 | 718 | #define MAX_PACKET(p) (((p)&0xffff) << 16) |
2d3f1fac SS |
719 | #define MAX_PACKET_MASK (0xffff << 16) |
720 | #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) | |
a74588f9 | 721 | |
dc07c91b AX |
722 | /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. |
723 | * USB2.0 spec 9.6.6. | |
724 | */ | |
725 | #define GET_MAX_PACKET(p) ((p) & 0x7ff) | |
726 | ||
9238f25d SS |
727 | /* tx_info bitmasks */ |
728 | #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff) | |
729 | #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16) | |
9af5d71d | 730 | #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) |
9238f25d | 731 | |
bf161e85 SS |
732 | /* deq bitmasks */ |
733 | #define EP_CTX_CYCLE_MASK (1 << 0) | |
9aad95e2 | 734 | #define SCTX_DEQ_MASK (~0xfL) |
bf161e85 | 735 | |
a74588f9 SS |
736 | |
737 | /** | |
d115b048 JY |
738 | * struct xhci_input_control_context |
739 | * Input control context; see section 6.2.5. | |
a74588f9 SS |
740 | * |
741 | * @drop_context: set the bit of the endpoint context you want to disable | |
742 | * @add_context: set the bit of the endpoint context you want to enable | |
743 | */ | |
d115b048 | 744 | struct xhci_input_control_ctx { |
28ccd296 ME |
745 | __le32 drop_flags; |
746 | __le32 add_flags; | |
747 | __le32 rsvd2[6]; | |
98441973 | 748 | }; |
a74588f9 | 749 | |
9af5d71d SS |
750 | #define EP_IS_ADDED(ctrl_ctx, i) \ |
751 | (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) | |
752 | #define EP_IS_DROPPED(ctrl_ctx, i) \ | |
753 | (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) | |
754 | ||
913a8a34 SS |
755 | /* Represents everything that is needed to issue a command on the command ring. |
756 | * It's useful to pre-allocate these for commands that cannot fail due to | |
757 | * out-of-memory errors, like freeing streams. | |
758 | */ | |
759 | struct xhci_command { | |
760 | /* Input context for changing device state */ | |
761 | struct xhci_container_ctx *in_ctx; | |
762 | u32 status; | |
763 | /* If completion is null, no one is waiting on this command | |
764 | * and the structure can be freed after the command completes. | |
765 | */ | |
766 | struct completion *completion; | |
767 | union xhci_trb *command_trb; | |
768 | struct list_head cmd_list; | |
769 | }; | |
770 | ||
a74588f9 SS |
771 | /* drop context bitmasks */ |
772 | #define DROP_EP(x) (0x1 << x) | |
773 | /* add context bitmasks */ | |
774 | #define ADD_EP(x) (0x1 << x) | |
775 | ||
8df75f42 SS |
776 | struct xhci_stream_ctx { |
777 | /* 64-bit stream ring address, cycle state, and stream type */ | |
28ccd296 | 778 | __le64 stream_ring; |
8df75f42 | 779 | /* offset 0x14 - 0x1f reserved for HC internal use */ |
28ccd296 | 780 | __le32 reserved[2]; |
8df75f42 SS |
781 | }; |
782 | ||
783 | /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ | |
63a67a72 | 784 | #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) |
8df75f42 SS |
785 | /* Secondary stream array type, dequeue pointer is to a transfer ring */ |
786 | #define SCT_SEC_TR 0 | |
787 | /* Primary stream array type, dequeue pointer is to a transfer ring */ | |
788 | #define SCT_PRI_TR 1 | |
789 | /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ | |
790 | #define SCT_SSA_8 2 | |
791 | #define SCT_SSA_16 3 | |
792 | #define SCT_SSA_32 4 | |
793 | #define SCT_SSA_64 5 | |
794 | #define SCT_SSA_128 6 | |
795 | #define SCT_SSA_256 7 | |
796 | ||
797 | /* Assume no secondary streams for now */ | |
798 | struct xhci_stream_info { | |
799 | struct xhci_ring **stream_rings; | |
800 | /* Number of streams, including stream 0 (which drivers can't use) */ | |
801 | unsigned int num_streams; | |
802 | /* The stream context array may be bigger than | |
803 | * the number of streams the driver asked for | |
804 | */ | |
805 | struct xhci_stream_ctx *stream_ctx_array; | |
806 | unsigned int num_stream_ctxs; | |
807 | dma_addr_t ctx_array_dma; | |
808 | /* For mapping physical TRB addresses to segments in stream rings */ | |
809 | struct radix_tree_root trb_address_map; | |
810 | struct xhci_command *free_streams_command; | |
811 | }; | |
812 | ||
813 | #define SMALL_STREAM_ARRAY_SIZE 256 | |
814 | #define MEDIUM_STREAM_ARRAY_SIZE 1024 | |
815 | ||
9af5d71d SS |
816 | /* Some Intel xHCI host controllers need software to keep track of the bus |
817 | * bandwidth. Keep track of endpoint info here. Each root port is allocated | |
818 | * the full bus bandwidth. We must also treat TTs (including each port under a | |
819 | * multi-TT hub) as a separate bandwidth domain. The direct memory interface | |
820 | * (DMI) also limits the total bandwidth (across all domains) that can be used. | |
821 | */ | |
822 | struct xhci_bw_info { | |
170c0263 | 823 | /* ep_interval is zero-based */ |
9af5d71d | 824 | unsigned int ep_interval; |
170c0263 | 825 | /* mult and num_packets are one-based */ |
9af5d71d SS |
826 | unsigned int mult; |
827 | unsigned int num_packets; | |
828 | unsigned int max_packet_size; | |
829 | unsigned int max_esit_payload; | |
830 | unsigned int type; | |
831 | }; | |
832 | ||
c29eea62 SS |
833 | /* "Block" sizes in bytes the hardware uses for different device speeds. |
834 | * The logic in this part of the hardware limits the number of bits the hardware | |
835 | * can use, so must represent bandwidth in a less precise manner to mimic what | |
836 | * the scheduler hardware computes. | |
837 | */ | |
838 | #define FS_BLOCK 1 | |
839 | #define HS_BLOCK 4 | |
840 | #define SS_BLOCK 16 | |
841 | #define DMI_BLOCK 32 | |
842 | ||
843 | /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated | |
844 | * with each byte transferred. SuperSpeed devices have an initial overhead to | |
845 | * set up bursts. These are in blocks, see above. LS overhead has already been | |
846 | * translated into FS blocks. | |
847 | */ | |
848 | #define DMI_OVERHEAD 8 | |
849 | #define DMI_OVERHEAD_BURST 4 | |
850 | #define SS_OVERHEAD 8 | |
851 | #define SS_OVERHEAD_BURST 32 | |
852 | #define HS_OVERHEAD 26 | |
853 | #define FS_OVERHEAD 20 | |
854 | #define LS_OVERHEAD 128 | |
855 | /* The TTs need to claim roughly twice as much bandwidth (94 bytes per | |
856 | * microframe ~= 24Mbps) of the HS bus as the devices can actually use because | |
857 | * of overhead associated with split transfers crossing microframe boundaries. | |
858 | * 31 blocks is pure protocol overhead. | |
859 | */ | |
860 | #define TT_HS_OVERHEAD (31 + 94) | |
861 | #define TT_DMI_OVERHEAD (25 + 12) | |
862 | ||
863 | /* Bandwidth limits in blocks */ | |
864 | #define FS_BW_LIMIT 1285 | |
865 | #define TT_BW_LIMIT 1320 | |
866 | #define HS_BW_LIMIT 1607 | |
867 | #define SS_BW_LIMIT_IN 3906 | |
868 | #define DMI_BW_LIMIT_IN 3906 | |
869 | #define SS_BW_LIMIT_OUT 3906 | |
870 | #define DMI_BW_LIMIT_OUT 3906 | |
871 | ||
872 | /* Percentage of bus bandwidth reserved for non-periodic transfers */ | |
873 | #define FS_BW_RESERVED 10 | |
874 | #define HS_BW_RESERVED 20 | |
2b698999 | 875 | #define SS_BW_RESERVED 10 |
c29eea62 | 876 | |
63a0d9ab SS |
877 | struct xhci_virt_ep { |
878 | struct xhci_ring *ring; | |
8df75f42 SS |
879 | /* Related to endpoints that are configured to use stream IDs only */ |
880 | struct xhci_stream_info *stream_info; | |
63a0d9ab SS |
881 | /* Temporary storage in case the configure endpoint command fails and we |
882 | * have to restore the device state to the previous state | |
883 | */ | |
884 | struct xhci_ring *new_ring; | |
885 | unsigned int ep_state; | |
886 | #define SET_DEQ_PENDING (1 << 0) | |
678539cf SS |
887 | #define EP_HALTED (1 << 1) /* For stall handling */ |
888 | #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */ | |
8df75f42 SS |
889 | /* Transitioning the endpoint to using streams, don't enqueue URBs */ |
890 | #define EP_GETTING_STREAMS (1 << 3) | |
891 | #define EP_HAS_STREAMS (1 << 4) | |
892 | /* Transitioning the endpoint to not using streams, don't enqueue URBs */ | |
893 | #define EP_GETTING_NO_STREAMS (1 << 5) | |
63a0d9ab SS |
894 | /* ---- Related to URB cancellation ---- */ |
895 | struct list_head cancelled_td_list; | |
63a0d9ab | 896 | struct xhci_td *stopped_td; |
e9df17eb | 897 | unsigned int stopped_stream; |
6f5165cf SS |
898 | /* Watchdog timer for stop endpoint command to cancel URBs */ |
899 | struct timer_list stop_cmd_timer; | |
900 | int stop_cmds_pending; | |
901 | struct xhci_hcd *xhci; | |
bf161e85 SS |
902 | /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue |
903 | * command. We'll need to update the ring's dequeue segment and dequeue | |
904 | * pointer after the command completes. | |
905 | */ | |
906 | struct xhci_segment *queued_deq_seg; | |
907 | union xhci_trb *queued_deq_ptr; | |
d18240db AX |
908 | /* |
909 | * Sometimes the xHC can not process isochronous endpoint ring quickly | |
910 | * enough, and it will miss some isoc tds on the ring and generate | |
911 | * a Missed Service Error Event. | |
912 | * Set skip flag when receive a Missed Service Error Event and | |
913 | * process the missed tds on the endpoint ring. | |
914 | */ | |
915 | bool skip; | |
2e27980e | 916 | /* Bandwidth checking storage */ |
9af5d71d | 917 | struct xhci_bw_info bw_info; |
2e27980e | 918 | struct list_head bw_endpoint_list; |
79b8094f LB |
919 | /* Isoch Frame ID checking storage */ |
920 | int next_frame_id; | |
63a0d9ab SS |
921 | }; |
922 | ||
839c817c SS |
923 | enum xhci_overhead_type { |
924 | LS_OVERHEAD_TYPE = 0, | |
925 | FS_OVERHEAD_TYPE, | |
926 | HS_OVERHEAD_TYPE, | |
927 | }; | |
928 | ||
929 | struct xhci_interval_bw { | |
930 | unsigned int num_packets; | |
2e27980e SS |
931 | /* Sorted by max packet size. |
932 | * Head of the list is the greatest max packet size. | |
933 | */ | |
934 | struct list_head endpoints; | |
839c817c SS |
935 | /* How many endpoints of each speed are present. */ |
936 | unsigned int overhead[3]; | |
937 | }; | |
938 | ||
939 | #define XHCI_MAX_INTERVAL 16 | |
940 | ||
941 | struct xhci_interval_bw_table { | |
942 | unsigned int interval0_esit_payload; | |
943 | struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; | |
c29eea62 SS |
944 | /* Includes reserved bandwidth for async endpoints */ |
945 | unsigned int bw_used; | |
2b698999 SS |
946 | unsigned int ss_bw_in; |
947 | unsigned int ss_bw_out; | |
839c817c SS |
948 | }; |
949 | ||
950 | ||
3ffbba95 | 951 | struct xhci_virt_device { |
64927730 | 952 | struct usb_device *udev; |
3ffbba95 SS |
953 | /* |
954 | * Commands to the hardware are passed an "input context" that | |
955 | * tells the hardware what to change in its data structures. | |
956 | * The hardware will return changes in an "output context" that | |
957 | * software must allocate for the hardware. We need to keep | |
958 | * track of input and output contexts separately because | |
959 | * these commands might fail and we don't trust the hardware. | |
960 | */ | |
d115b048 | 961 | struct xhci_container_ctx *out_ctx; |
3ffbba95 | 962 | /* Used for addressing devices and configuration changes */ |
d115b048 | 963 | struct xhci_container_ctx *in_ctx; |
74f9fe21 SS |
964 | /* Rings saved to ensure old alt settings can be re-instated */ |
965 | struct xhci_ring **ring_cache; | |
966 | int num_rings_cached; | |
967 | #define XHCI_MAX_RINGS_CACHED 31 | |
63a0d9ab | 968 | struct xhci_virt_ep eps[31]; |
f94e0186 | 969 | struct completion cmd_completion; |
fe30182c | 970 | u8 fake_port; |
66381755 | 971 | u8 real_port; |
839c817c SS |
972 | struct xhci_interval_bw_table *bw_table; |
973 | struct xhci_tt_bw_info *tt_info; | |
3b3db026 SS |
974 | /* The current max exit latency for the enabled USB3 link states. */ |
975 | u16 current_mel; | |
839c817c SS |
976 | }; |
977 | ||
978 | /* | |
979 | * For each roothub, keep track of the bandwidth information for each periodic | |
980 | * interval. | |
981 | * | |
982 | * If a high speed hub is attached to the roothub, each TT associated with that | |
983 | * hub is a separate bandwidth domain. The interval information for the | |
984 | * endpoints on the devices under that TT will appear in the TT structure. | |
985 | */ | |
986 | struct xhci_root_port_bw_info { | |
987 | struct list_head tts; | |
988 | unsigned int num_active_tts; | |
989 | struct xhci_interval_bw_table bw_table; | |
990 | }; | |
991 | ||
992 | struct xhci_tt_bw_info { | |
993 | struct list_head tt_list; | |
994 | int slot_id; | |
995 | int ttport; | |
996 | struct xhci_interval_bw_table bw_table; | |
997 | int active_eps; | |
3ffbba95 SS |
998 | }; |
999 | ||
1000 | ||
a74588f9 SS |
1001 | /** |
1002 | * struct xhci_device_context_array | |
1003 | * @dev_context_ptr array of 64-bit DMA addresses for device contexts | |
1004 | */ | |
1005 | struct xhci_device_context_array { | |
1006 | /* 64-bit device addresses; we only write 32-bit addresses */ | |
28ccd296 | 1007 | __le64 dev_context_ptrs[MAX_HC_SLOTS]; |
a74588f9 SS |
1008 | /* private xHCD pointers */ |
1009 | dma_addr_t dma; | |
98441973 | 1010 | }; |
a74588f9 SS |
1011 | /* TODO: write function to set the 64-bit device DMA address */ |
1012 | /* | |
1013 | * TODO: change this to be dynamically sized at HC mem init time since the HC | |
1014 | * might not be able to handle the maximum number of devices possible. | |
1015 | */ | |
1016 | ||
1017 | ||
0ebbab37 SS |
1018 | struct xhci_transfer_event { |
1019 | /* 64-bit buffer address, or immediate data */ | |
28ccd296 ME |
1020 | __le64 buffer; |
1021 | __le32 transfer_len; | |
0ebbab37 | 1022 | /* This field is interpreted differently based on the type of TRB */ |
28ccd296 | 1023 | __le32 flags; |
98441973 | 1024 | }; |
0ebbab37 | 1025 | |
1c11a172 VG |
1026 | /* Transfer event TRB length bit mask */ |
1027 | /* bits 0:23 */ | |
1028 | #define EVENT_TRB_LEN(p) ((p) & 0xffffff) | |
1029 | ||
d0e96f5a SS |
1030 | /** Transfer Event bit fields **/ |
1031 | #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) | |
1032 | ||
0ebbab37 SS |
1033 | /* Completion Code - only applicable for some types of TRBs */ |
1034 | #define COMP_CODE_MASK (0xff << 24) | |
1035 | #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) | |
1036 | #define COMP_SUCCESS 1 | |
1037 | /* Data Buffer Error */ | |
1038 | #define COMP_DB_ERR 2 | |
1039 | /* Babble Detected Error */ | |
1040 | #define COMP_BABBLE 3 | |
1041 | /* USB Transaction Error */ | |
1042 | #define COMP_TX_ERR 4 | |
1043 | /* TRB Error - some TRB field is invalid */ | |
1044 | #define COMP_TRB_ERR 5 | |
1045 | /* Stall Error - USB device is stalled */ | |
1046 | #define COMP_STALL 6 | |
1047 | /* Resource Error - HC doesn't have memory for that device configuration */ | |
1048 | #define COMP_ENOMEM 7 | |
1049 | /* Bandwidth Error - not enough room in schedule for this dev config */ | |
1050 | #define COMP_BW_ERR 8 | |
1051 | /* No Slots Available Error - HC ran out of device slots */ | |
1052 | #define COMP_ENOSLOTS 9 | |
1053 | /* Invalid Stream Type Error */ | |
1054 | #define COMP_STREAM_ERR 10 | |
1055 | /* Slot Not Enabled Error - doorbell rung for disabled device slot */ | |
1056 | #define COMP_EBADSLT 11 | |
1057 | /* Endpoint Not Enabled Error */ | |
1058 | #define COMP_EBADEP 12 | |
1059 | /* Short Packet */ | |
1060 | #define COMP_SHORT_TX 13 | |
1061 | /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ | |
1062 | #define COMP_UNDERRUN 14 | |
1063 | /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ | |
1064 | #define COMP_OVERRUN 15 | |
1065 | /* Virtual Function Event Ring Full Error */ | |
1066 | #define COMP_VF_FULL 16 | |
1067 | /* Parameter Error - Context parameter is invalid */ | |
1068 | #define COMP_EINVAL 17 | |
1069 | /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ | |
1070 | #define COMP_BW_OVER 18 | |
1071 | /* Context State Error - illegal context state transition requested */ | |
1072 | #define COMP_CTX_STATE 19 | |
1073 | /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ | |
1074 | #define COMP_PING_ERR 20 | |
1075 | /* Event Ring is full */ | |
1076 | #define COMP_ER_FULL 21 | |
f6ba6fe2 AH |
1077 | /* Incompatible Device Error */ |
1078 | #define COMP_DEV_ERR 22 | |
0ebbab37 SS |
1079 | /* Missed Service Error - HC couldn't service an isoc ep within interval */ |
1080 | #define COMP_MISSED_INT 23 | |
1081 | /* Successfully stopped command ring */ | |
1082 | #define COMP_CMD_STOP 24 | |
1083 | /* Successfully aborted current command and stopped command ring */ | |
1084 | #define COMP_CMD_ABORT 25 | |
1085 | /* Stopped - transfer was terminated by a stop endpoint command */ | |
1086 | #define COMP_STOP 26 | |
25985edc | 1087 | /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */ |
0ebbab37 | 1088 | #define COMP_STOP_INVAL 27 |
40a3b775 LB |
1089 | /* Same as COMP_EP_STOPPED, but a short packet detected */ |
1090 | #define COMP_STOP_SHORT 28 | |
1bb73a88 AH |
1091 | /* Max Exit Latency Too Large Error */ |
1092 | #define COMP_MEL_ERR 29 | |
1093 | /* TRB type 30 reserved */ | |
0ebbab37 SS |
1094 | /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ |
1095 | #define COMP_BUFF_OVER 31 | |
1096 | /* Event Lost Error - xHC has an "internal event overrun condition" */ | |
1097 | #define COMP_ISSUES 32 | |
1098 | /* Undefined Error - reported when other error codes don't apply */ | |
1099 | #define COMP_UNKNOWN 33 | |
1100 | /* Invalid Stream ID Error */ | |
1101 | #define COMP_STRID_ERR 34 | |
1102 | /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ | |
0ebbab37 SS |
1103 | #define COMP_2ND_BW_ERR 35 |
1104 | /* Split Transaction Error */ | |
1105 | #define COMP_SPLIT_ERR 36 | |
1106 | ||
1107 | struct xhci_link_trb { | |
1108 | /* 64-bit segment pointer*/ | |
28ccd296 ME |
1109 | __le64 segment_ptr; |
1110 | __le32 intr_target; | |
1111 | __le32 control; | |
98441973 | 1112 | }; |
0ebbab37 SS |
1113 | |
1114 | /* control bitfields */ | |
1115 | #define LINK_TOGGLE (0x1<<1) | |
1116 | ||
7f84eef0 SS |
1117 | /* Command completion event TRB */ |
1118 | struct xhci_event_cmd { | |
1119 | /* Pointer to command TRB, or the value passed by the event data trb */ | |
28ccd296 ME |
1120 | __le64 cmd_trb; |
1121 | __le32 status; | |
1122 | __le32 flags; | |
98441973 | 1123 | }; |
0ebbab37 | 1124 | |
3ffbba95 | 1125 | /* flags bitmasks */ |
48fc7dbd DW |
1126 | |
1127 | /* Address device - disable SetAddress */ | |
1128 | #define TRB_BSR (1<<9) | |
1129 | enum xhci_setup_dev { | |
1130 | SETUP_CONTEXT_ONLY, | |
1131 | SETUP_CONTEXT_ADDRESS, | |
1132 | }; | |
1133 | ||
3ffbba95 SS |
1134 | /* bits 16:23 are the virtual function ID */ |
1135 | /* bits 24:31 are the slot ID */ | |
1136 | #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) | |
1137 | #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) | |
0ebbab37 | 1138 | |
ae636747 SS |
1139 | /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ |
1140 | #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) | |
1141 | #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) | |
1142 | ||
be88fe4f AX |
1143 | #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) |
1144 | #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) | |
1145 | #define LAST_EP_INDEX 30 | |
1146 | ||
95241dbd | 1147 | /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ |
e9df17eb SS |
1148 | #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) |
1149 | #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) | |
95241dbd | 1150 | #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) |
e9df17eb | 1151 | |
ae636747 | 1152 | |
0f2a7930 SS |
1153 | /* Port Status Change Event TRB fields */ |
1154 | /* Port ID - bits 31:24 */ | |
1155 | #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) | |
1156 | ||
0ebbab37 SS |
1157 | /* Normal TRB fields */ |
1158 | /* transfer_len bitmasks - bits 0:16 */ | |
1159 | #define TRB_LEN(p) ((p) & 0x1ffff) | |
0ebbab37 SS |
1160 | /* Interrupter Target - which MSI-X vector to target the completion event at */ |
1161 | #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) | |
1162 | #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) | |
5cd43e33 | 1163 | #define TRB_TBC(p) (((p) & 0x3) << 7) |
b61d378f | 1164 | #define TRB_TLBPC(p) (((p) & 0xf) << 16) |
0ebbab37 SS |
1165 | |
1166 | /* Cycle bit - indicates TRB ownership by HC or HCD */ | |
1167 | #define TRB_CYCLE (1<<0) | |
1168 | /* | |
1169 | * Force next event data TRB to be evaluated before task switch. | |
1170 | * Used to pass OS data back after a TD completes. | |
1171 | */ | |
1172 | #define TRB_ENT (1<<1) | |
1173 | /* Interrupt on short packet */ | |
1174 | #define TRB_ISP (1<<2) | |
1175 | /* Set PCIe no snoop attribute */ | |
1176 | #define TRB_NO_SNOOP (1<<3) | |
1177 | /* Chain multiple TRBs into a TD */ | |
1178 | #define TRB_CHAIN (1<<4) | |
1179 | /* Interrupt on completion */ | |
1180 | #define TRB_IOC (1<<5) | |
1181 | /* The buffer pointer contains immediate data */ | |
1182 | #define TRB_IDT (1<<6) | |
1183 | ||
ad106f29 AX |
1184 | /* Block Event Interrupt */ |
1185 | #define TRB_BEI (1<<9) | |
0ebbab37 SS |
1186 | |
1187 | /* Control transfer TRB specific fields */ | |
1188 | #define TRB_DIR_IN (1<<16) | |
b83cdc8f AX |
1189 | #define TRB_TX_TYPE(p) ((p) << 16) |
1190 | #define TRB_DATA_OUT 2 | |
1191 | #define TRB_DATA_IN 3 | |
0ebbab37 | 1192 | |
04e51901 AX |
1193 | /* Isochronous TRB specific fields */ |
1194 | #define TRB_SIA (1<<31) | |
79b8094f | 1195 | #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) |
04e51901 | 1196 | |
7f84eef0 | 1197 | struct xhci_generic_trb { |
28ccd296 | 1198 | __le32 field[4]; |
98441973 | 1199 | }; |
7f84eef0 SS |
1200 | |
1201 | union xhci_trb { | |
1202 | struct xhci_link_trb link; | |
1203 | struct xhci_transfer_event trans_event; | |
1204 | struct xhci_event_cmd event_cmd; | |
1205 | struct xhci_generic_trb generic; | |
1206 | }; | |
1207 | ||
0ebbab37 SS |
1208 | /* TRB bit mask */ |
1209 | #define TRB_TYPE_BITMASK (0xfc00) | |
1210 | #define TRB_TYPE(p) ((p) << 10) | |
0238634d | 1211 | #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) |
0ebbab37 SS |
1212 | /* TRB type IDs */ |
1213 | /* bulk, interrupt, isoc scatter/gather, and control data stage */ | |
1214 | #define TRB_NORMAL 1 | |
1215 | /* setup stage for control transfers */ | |
1216 | #define TRB_SETUP 2 | |
1217 | /* data stage for control transfers */ | |
1218 | #define TRB_DATA 3 | |
1219 | /* status stage for control transfers */ | |
1220 | #define TRB_STATUS 4 | |
1221 | /* isoc transfers */ | |
1222 | #define TRB_ISOC 5 | |
1223 | /* TRB for linking ring segments */ | |
1224 | #define TRB_LINK 6 | |
1225 | #define TRB_EVENT_DATA 7 | |
1226 | /* Transfer Ring No-op (not for the command ring) */ | |
1227 | #define TRB_TR_NOOP 8 | |
1228 | /* Command TRBs */ | |
1229 | /* Enable Slot Command */ | |
1230 | #define TRB_ENABLE_SLOT 9 | |
1231 | /* Disable Slot Command */ | |
1232 | #define TRB_DISABLE_SLOT 10 | |
1233 | /* Address Device Command */ | |
1234 | #define TRB_ADDR_DEV 11 | |
1235 | /* Configure Endpoint Command */ | |
1236 | #define TRB_CONFIG_EP 12 | |
1237 | /* Evaluate Context Command */ | |
1238 | #define TRB_EVAL_CONTEXT 13 | |
a1587d97 SS |
1239 | /* Reset Endpoint Command */ |
1240 | #define TRB_RESET_EP 14 | |
0ebbab37 SS |
1241 | /* Stop Transfer Ring Command */ |
1242 | #define TRB_STOP_RING 15 | |
1243 | /* Set Transfer Ring Dequeue Pointer Command */ | |
1244 | #define TRB_SET_DEQ 16 | |
1245 | /* Reset Device Command */ | |
1246 | #define TRB_RESET_DEV 17 | |
1247 | /* Force Event Command (opt) */ | |
1248 | #define TRB_FORCE_EVENT 18 | |
1249 | /* Negotiate Bandwidth Command (opt) */ | |
1250 | #define TRB_NEG_BANDWIDTH 19 | |
1251 | /* Set Latency Tolerance Value Command (opt) */ | |
1252 | #define TRB_SET_LT 20 | |
1253 | /* Get port bandwidth Command */ | |
1254 | #define TRB_GET_BW 21 | |
1255 | /* Force Header Command - generate a transaction or link management packet */ | |
1256 | #define TRB_FORCE_HEADER 22 | |
1257 | /* No-op Command - not for transfer rings */ | |
1258 | #define TRB_CMD_NOOP 23 | |
1259 | /* TRB IDs 24-31 reserved */ | |
1260 | /* Event TRBS */ | |
1261 | /* Transfer Event */ | |
1262 | #define TRB_TRANSFER 32 | |
1263 | /* Command Completion Event */ | |
1264 | #define TRB_COMPLETION 33 | |
1265 | /* Port Status Change Event */ | |
1266 | #define TRB_PORT_STATUS 34 | |
1267 | /* Bandwidth Request Event (opt) */ | |
1268 | #define TRB_BANDWIDTH_EVENT 35 | |
1269 | /* Doorbell Event (opt) */ | |
1270 | #define TRB_DOORBELL 36 | |
1271 | /* Host Controller Event */ | |
1272 | #define TRB_HC_EVENT 37 | |
1273 | /* Device Notification Event - device sent function wake notification */ | |
1274 | #define TRB_DEV_NOTE 38 | |
1275 | /* MFINDEX Wrap Event - microframe counter wrapped */ | |
1276 | #define TRB_MFINDEX_WRAP 39 | |
1277 | /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ | |
1278 | ||
0238634d SS |
1279 | /* Nec vendor-specific command completion event. */ |
1280 | #define TRB_NEC_CMD_COMP 48 | |
1281 | /* Get NEC firmware revision. */ | |
1282 | #define TRB_NEC_GET_FW 49 | |
1283 | ||
f5960b69 ME |
1284 | #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) |
1285 | /* Above, but for __le32 types -- can avoid work by swapping constants: */ | |
1286 | #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ | |
1287 | cpu_to_le32(TRB_TYPE(TRB_LINK))) | |
1288 | #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ | |
1289 | cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) | |
1290 | ||
0238634d SS |
1291 | #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) |
1292 | #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) | |
1293 | ||
0ebbab37 SS |
1294 | /* |
1295 | * TRBS_PER_SEGMENT must be a multiple of 4, | |
1296 | * since the command ring is 64-byte aligned. | |
1297 | * It must also be greater than 16. | |
1298 | */ | |
18cc2f4c | 1299 | #define TRBS_PER_SEGMENT 256 |
913a8a34 SS |
1300 | /* Allow two commands + a link TRB, along with any reserved command TRBs */ |
1301 | #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) | |
eb8ccd2b DH |
1302 | #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) |
1303 | #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) | |
b10de142 SS |
1304 | /* TRB buffer pointers can't cross 64KB boundaries */ |
1305 | #define TRB_MAX_BUFF_SHIFT 16 | |
1306 | #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) | |
0ebbab37 SS |
1307 | |
1308 | struct xhci_segment { | |
1309 | union xhci_trb *trbs; | |
1310 | /* private to HCD */ | |
1311 | struct xhci_segment *next; | |
1312 | dma_addr_t dma; | |
98441973 | 1313 | }; |
0ebbab37 | 1314 | |
ae636747 SS |
1315 | struct xhci_td { |
1316 | struct list_head td_list; | |
1317 | struct list_head cancelled_td_list; | |
1318 | struct urb *urb; | |
1319 | struct xhci_segment *start_seg; | |
1320 | union xhci_trb *first_trb; | |
1321 | union xhci_trb *last_trb; | |
45ba2154 AM |
1322 | /* actual_length of the URB has already been set */ |
1323 | bool urb_length_set; | |
ae636747 SS |
1324 | }; |
1325 | ||
6e4468b9 EF |
1326 | /* xHCI command default timeout value */ |
1327 | #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) | |
1328 | ||
b92cc66c EF |
1329 | /* command descriptor */ |
1330 | struct xhci_cd { | |
b92cc66c EF |
1331 | struct xhci_command *command; |
1332 | union xhci_trb *cmd_trb; | |
1333 | }; | |
1334 | ||
ac9d8fe7 SS |
1335 | struct xhci_dequeue_state { |
1336 | struct xhci_segment *new_deq_seg; | |
1337 | union xhci_trb *new_deq_ptr; | |
1338 | int new_cycle_state; | |
1339 | }; | |
1340 | ||
3b72fca0 AX |
1341 | enum xhci_ring_type { |
1342 | TYPE_CTRL = 0, | |
1343 | TYPE_ISOC, | |
1344 | TYPE_BULK, | |
1345 | TYPE_INTR, | |
1346 | TYPE_STREAM, | |
1347 | TYPE_COMMAND, | |
1348 | TYPE_EVENT, | |
1349 | }; | |
1350 | ||
0ebbab37 SS |
1351 | struct xhci_ring { |
1352 | struct xhci_segment *first_seg; | |
3fe4fe08 | 1353 | struct xhci_segment *last_seg; |
0ebbab37 | 1354 | union xhci_trb *enqueue; |
7f84eef0 SS |
1355 | struct xhci_segment *enq_seg; |
1356 | unsigned int enq_updates; | |
0ebbab37 | 1357 | union xhci_trb *dequeue; |
7f84eef0 SS |
1358 | struct xhci_segment *deq_seg; |
1359 | unsigned int deq_updates; | |
d0e96f5a | 1360 | struct list_head td_list; |
0ebbab37 SS |
1361 | /* |
1362 | * Write the cycle state into the TRB cycle field to give ownership of | |
1363 | * the TRB to the host controller (if we are the producer), or to check | |
1364 | * if we own the TRB (if we are the consumer). See section 4.9.1. | |
1365 | */ | |
1366 | u32 cycle_state; | |
e9df17eb | 1367 | unsigned int stream_id; |
3fe4fe08 | 1368 | unsigned int num_segs; |
b008df60 AX |
1369 | unsigned int num_trbs_free; |
1370 | unsigned int num_trbs_free_temp; | |
3b72fca0 | 1371 | enum xhci_ring_type type; |
ad808333 | 1372 | bool last_td_was_short; |
15341303 | 1373 | struct radix_tree_root *trb_address_map; |
0ebbab37 SS |
1374 | }; |
1375 | ||
1376 | struct xhci_erst_entry { | |
1377 | /* 64-bit event ring segment address */ | |
28ccd296 ME |
1378 | __le64 seg_addr; |
1379 | __le32 seg_size; | |
0ebbab37 | 1380 | /* Set to zero */ |
28ccd296 | 1381 | __le32 rsvd; |
98441973 | 1382 | }; |
0ebbab37 SS |
1383 | |
1384 | struct xhci_erst { | |
1385 | struct xhci_erst_entry *entries; | |
1386 | unsigned int num_entries; | |
1387 | /* xhci->event_ring keeps track of segment dma addresses */ | |
1388 | dma_addr_t erst_dma_addr; | |
1389 | /* Num entries the ERST can contain */ | |
1390 | unsigned int erst_size; | |
1391 | }; | |
1392 | ||
254c80a3 JY |
1393 | struct xhci_scratchpad { |
1394 | u64 *sp_array; | |
1395 | dma_addr_t sp_dma; | |
1396 | void **sp_buffers; | |
1397 | dma_addr_t *sp_dma_buffers; | |
1398 | }; | |
1399 | ||
8e51adcc AX |
1400 | struct urb_priv { |
1401 | int length; | |
1402 | int td_cnt; | |
1403 | struct xhci_td *td[0]; | |
1404 | }; | |
1405 | ||
0ebbab37 SS |
1406 | /* |
1407 | * Each segment table entry is 4*32bits long. 1K seems like an ok size: | |
1408 | * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, | |
1409 | * meaning 64 ring segments. | |
1410 | * Initial allocated size of the ERST, in number of entries */ | |
1411 | #define ERST_NUM_SEGS 1 | |
1412 | /* Initial allocated size of the ERST, in number of entries */ | |
1413 | #define ERST_SIZE 64 | |
1414 | /* Initial number of event segment rings allocated */ | |
1415 | #define ERST_ENTRIES 1 | |
7f84eef0 SS |
1416 | /* Poll every 60 seconds */ |
1417 | #define POLL_TIMEOUT 60 | |
6f5165cf SS |
1418 | /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ |
1419 | #define XHCI_STOP_EP_CMD_TIMEOUT 5 | |
0ebbab37 SS |
1420 | /* XXX: Make these module parameters */ |
1421 | ||
5535b1d5 AX |
1422 | struct s3_save { |
1423 | u32 command; | |
1424 | u32 dev_nt; | |
1425 | u64 dcbaa_ptr; | |
1426 | u32 config_reg; | |
1427 | u32 irq_pending; | |
1428 | u32 irq_control; | |
1429 | u32 erst_size; | |
1430 | u64 erst_base; | |
1431 | u64 erst_dequeue; | |
1432 | }; | |
74c68741 | 1433 | |
9574323c AX |
1434 | /* Use for lpm */ |
1435 | struct dev_info { | |
1436 | u32 dev_id; | |
1437 | struct list_head list; | |
1438 | }; | |
1439 | ||
20b67cf5 SS |
1440 | struct xhci_bus_state { |
1441 | unsigned long bus_suspended; | |
1442 | unsigned long next_statechange; | |
1443 | ||
1444 | /* Port suspend arrays are indexed by the portnum of the fake roothub */ | |
1445 | /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ | |
1446 | u32 port_c_suspend; | |
1447 | u32 suspended_ports; | |
4ee823b8 | 1448 | u32 port_remote_wakeup; |
20b67cf5 | 1449 | unsigned long resume_done[USB_MAXCHILDREN]; |
f370b996 AX |
1450 | /* which ports have started to resume */ |
1451 | unsigned long resuming_ports; | |
8b3d4570 SS |
1452 | /* Which ports are waiting on RExit to U0 transition. */ |
1453 | unsigned long rexit_ports; | |
1454 | struct completion rexit_done[USB_MAXCHILDREN]; | |
20b67cf5 SS |
1455 | }; |
1456 | ||
8b3d4570 SS |
1457 | |
1458 | /* | |
1459 | * It can take up to 20 ms to transition from RExit to U0 on the | |
1460 | * Intel Lynx Point LP xHCI host. | |
1461 | */ | |
1462 | #define XHCI_MAX_REXIT_TIMEOUT (20 * 1000) | |
1463 | ||
20b67cf5 SS |
1464 | static inline unsigned int hcd_index(struct usb_hcd *hcd) |
1465 | { | |
f6ff0ac8 SS |
1466 | if (hcd->speed == HCD_USB3) |
1467 | return 0; | |
1468 | else | |
1469 | return 1; | |
20b67cf5 SS |
1470 | } |
1471 | ||
05103114 | 1472 | /* There is one xhci_hcd structure per controller */ |
74c68741 | 1473 | struct xhci_hcd { |
b02d0ed6 | 1474 | struct usb_hcd *main_hcd; |
f6ff0ac8 | 1475 | struct usb_hcd *shared_hcd; |
74c68741 SS |
1476 | /* glue to PCI and HCD framework */ |
1477 | struct xhci_cap_regs __iomem *cap_regs; | |
1478 | struct xhci_op_regs __iomem *op_regs; | |
1479 | struct xhci_run_regs __iomem *run_regs; | |
0ebbab37 | 1480 | struct xhci_doorbell_array __iomem *dba; |
66d4eadd | 1481 | /* Our HCD's current interrupter register set */ |
98441973 | 1482 | struct xhci_intr_reg __iomem *ir_set; |
74c68741 SS |
1483 | |
1484 | /* Cached register copies of read-only HC data */ | |
1485 | __u32 hcs_params1; | |
1486 | __u32 hcs_params2; | |
1487 | __u32 hcs_params3; | |
1488 | __u32 hcc_params; | |
04abb6de | 1489 | __u32 hcc_params2; |
74c68741 SS |
1490 | |
1491 | spinlock_t lock; | |
1492 | ||
1493 | /* packed release number */ | |
1494 | u8 sbrn; | |
1495 | u16 hci_version; | |
1496 | u8 max_slots; | |
1497 | u8 max_interrupters; | |
1498 | u8 max_ports; | |
1499 | u8 isoc_threshold; | |
1500 | int event_ring_max; | |
1501 | int addr_64; | |
66d4eadd | 1502 | /* 4KB min, 128MB max */ |
74c68741 | 1503 | int page_size; |
66d4eadd SS |
1504 | /* Valid values are 12 to 20, inclusive */ |
1505 | int page_shift; | |
43b86af8 | 1506 | /* msi-x vectors */ |
66d4eadd SS |
1507 | int msix_count; |
1508 | struct msix_entry *msix_entries; | |
4718c177 GC |
1509 | /* optional clock */ |
1510 | struct clk *clk; | |
0ebbab37 | 1511 | /* data structures */ |
a74588f9 | 1512 | struct xhci_device_context_array *dcbaa; |
0ebbab37 | 1513 | struct xhci_ring *cmd_ring; |
c181bc5b EF |
1514 | unsigned int cmd_ring_state; |
1515 | #define CMD_RING_STATE_RUNNING (1 << 0) | |
1516 | #define CMD_RING_STATE_ABORTED (1 << 1) | |
1517 | #define CMD_RING_STATE_STOPPED (1 << 2) | |
c9aa1a2d | 1518 | struct list_head cmd_list; |
913a8a34 | 1519 | unsigned int cmd_ring_reserved_trbs; |
c311e391 MN |
1520 | struct timer_list cmd_timer; |
1521 | struct xhci_command *current_cmd; | |
0ebbab37 SS |
1522 | struct xhci_ring *event_ring; |
1523 | struct xhci_erst erst; | |
254c80a3 JY |
1524 | /* Scratchpad */ |
1525 | struct xhci_scratchpad *scratchpad; | |
9574323c AX |
1526 | /* Store LPM test failed devices' information */ |
1527 | struct list_head lpm_failed_devs; | |
254c80a3 | 1528 | |
3ffbba95 | 1529 | /* slot enabling and address device helpers */ |
a00918d0 CB |
1530 | /* these are not thread safe so use mutex */ |
1531 | struct mutex mutex; | |
3ffbba95 SS |
1532 | struct completion addr_dev; |
1533 | int slot_id; | |
dbc33303 SS |
1534 | /* For USB 3.0 LPM enable/disable. */ |
1535 | struct xhci_command *lpm_command; | |
3ffbba95 SS |
1536 | /* Internal mirror of the HW's dcbaa */ |
1537 | struct xhci_virt_device *devs[MAX_HC_SLOTS]; | |
839c817c SS |
1538 | /* For keeping track of bandwidth domains per roothub. */ |
1539 | struct xhci_root_port_bw_info *rh_bw; | |
0ebbab37 SS |
1540 | |
1541 | /* DMA pools */ | |
1542 | struct dma_pool *device_pool; | |
1543 | struct dma_pool *segment_pool; | |
8df75f42 SS |
1544 | struct dma_pool *small_streams_pool; |
1545 | struct dma_pool *medium_streams_pool; | |
7f84eef0 | 1546 | |
6f5165cf SS |
1547 | /* Host controller watchdog timer structures */ |
1548 | unsigned int xhc_state; | |
9777e3ce | 1549 | |
9777e3ce | 1550 | u32 command; |
5535b1d5 | 1551 | struct s3_save s3; |
6f5165cf SS |
1552 | /* Host controller is dying - not responding to commands. "I'm not dead yet!" |
1553 | * | |
1554 | * xHC interrupts have been disabled and a watchdog timer will (or has already) | |
1555 | * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code | |
1556 | * that sees this status (other than the timer that set it) should stop touching | |
1557 | * hardware immediately. Interrupt handlers should return immediately when | |
1558 | * they see this status (any time they drop and re-acquire xhci->lock). | |
1559 | * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without | |
1560 | * putting the TD on the canceled list, etc. | |
1561 | * | |
1562 | * There are no reports of xHCI host controllers that display this issue. | |
1563 | */ | |
1564 | #define XHCI_STATE_DYING (1 << 0) | |
c6cc27c7 | 1565 | #define XHCI_STATE_HALTED (1 << 1) |
7f84eef0 | 1566 | /* Statistics */ |
7f84eef0 | 1567 | int error_bitmask; |
b0567b3f SS |
1568 | unsigned int quirks; |
1569 | #define XHCI_LINK_TRB_QUIRK (1 << 0) | |
ac9d8fe7 | 1570 | #define XHCI_RESET_EP_QUIRK (1 << 1) |
0238634d | 1571 | #define XHCI_NEC_HOST (1 << 2) |
c41136b0 | 1572 | #define XHCI_AMD_PLL_FIX (1 << 3) |
ad808333 | 1573 | #define XHCI_SPURIOUS_SUCCESS (1 << 4) |
2cf95c18 SS |
1574 | /* |
1575 | * Certain Intel host controllers have a limit to the number of endpoint | |
1576 | * contexts they can handle. Ideally, they would signal that they can't handle | |
1577 | * anymore endpoint contexts by returning a Resource Error for the Configure | |
1578 | * Endpoint command, but they don't. Instead they expect software to keep track | |
1579 | * of the number of active endpoints for them, across configure endpoint | |
1580 | * commands, reset device commands, disable slot commands, and address device | |
1581 | * commands. | |
1582 | */ | |
1583 | #define XHCI_EP_LIMIT_QUIRK (1 << 5) | |
f5182b41 | 1584 | #define XHCI_BROKEN_MSI (1 << 6) |
c877b3b2 | 1585 | #define XHCI_RESET_ON_RESUME (1 << 7) |
c29eea62 | 1586 | #define XHCI_SW_BW_CHECKING (1 << 8) |
7e393a83 | 1587 | #define XHCI_AMD_0x96_HOST (1 << 9) |
1530bbc6 | 1588 | #define XHCI_TRUST_TX_LENGTH (1 << 10) |
3b3db026 | 1589 | #define XHCI_LPM_SUPPORT (1 << 11) |
e3567d2c | 1590 | #define XHCI_INTEL_HOST (1 << 12) |
e95829f4 | 1591 | #define XHCI_SPURIOUS_REBOOT (1 << 13) |
71c731a2 | 1592 | #define XHCI_COMP_MODE_QUIRK (1 << 14) |
80fab3b2 | 1593 | #define XHCI_AVOID_BEI (1 << 15) |
52fb6125 | 1594 | #define XHCI_PLAT (1 << 16) |
455f5892 | 1595 | #define XHCI_SLOW_SUSPEND (1 << 17) |
638298dc | 1596 | #define XHCI_SPURIOUS_WAKEUP (1 << 18) |
8f873c1f HG |
1597 | /* For controllers with a broken beyond repair streams implementation */ |
1598 | #define XHCI_BROKEN_STREAMS (1 << 19) | |
b8cb91e0 | 1599 | #define XHCI_PME_STUCK_QUIRK (1 << 20) |
2cf95c18 SS |
1600 | unsigned int num_active_eps; |
1601 | unsigned int limit_active_eps; | |
f6ff0ac8 SS |
1602 | /* There are two roothubs to keep track of bus suspend info for */ |
1603 | struct xhci_bus_state bus_state[2]; | |
da6699ce SS |
1604 | /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ |
1605 | u8 *port_array; | |
1606 | /* Array of pointers to USB 3.0 PORTSC registers */ | |
28ccd296 | 1607 | __le32 __iomem **usb3_ports; |
da6699ce SS |
1608 | unsigned int num_usb3_ports; |
1609 | /* Array of pointers to USB 2.0 PORTSC registers */ | |
28ccd296 | 1610 | __le32 __iomem **usb2_ports; |
da6699ce | 1611 | unsigned int num_usb2_ports; |
fc71ff75 AX |
1612 | /* support xHCI 0.96 spec USB2 software LPM */ |
1613 | unsigned sw_lpm_support:1; | |
1614 | /* support xHCI 1.0 spec USB2 hardware LPM */ | |
1615 | unsigned hw_lpm_support:1; | |
b630d4b9 MN |
1616 | /* cached usb2 extened protocol capabilites */ |
1617 | u32 *ext_caps; | |
1618 | unsigned int num_ext_caps; | |
71c731a2 AC |
1619 | /* Compliance Mode Recovery Data */ |
1620 | struct timer_list comp_mode_recovery_timer; | |
1621 | u32 port_status_u0; | |
1622 | /* Compliance Mode Timer Triggered every 2 seconds */ | |
1623 | #define COMP_MODE_RCVRY_MSECS 2000 | |
74c68741 SS |
1624 | }; |
1625 | ||
cd33a321 RQ |
1626 | /* Platform specific overrides to generic XHCI hc_driver ops */ |
1627 | struct xhci_driver_overrides { | |
1628 | size_t extra_priv_size; | |
1629 | int (*reset)(struct usb_hcd *hcd); | |
1630 | int (*start)(struct usb_hcd *hcd); | |
1631 | }; | |
1632 | ||
79b8094f LB |
1633 | #define XHCI_CFC_DELAY 10 |
1634 | ||
74c68741 SS |
1635 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
1636 | static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) | |
1637 | { | |
cd33a321 RQ |
1638 | struct usb_hcd *primary_hcd; |
1639 | ||
1640 | if (usb_hcd_is_primary_hcd(hcd)) | |
1641 | primary_hcd = hcd; | |
1642 | else | |
1643 | primary_hcd = hcd->primary_hcd; | |
1644 | ||
1645 | return (struct xhci_hcd *) (primary_hcd->hcd_priv); | |
74c68741 SS |
1646 | } |
1647 | ||
1648 | static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) | |
1649 | { | |
b02d0ed6 | 1650 | return xhci->main_hcd; |
74c68741 SS |
1651 | } |
1652 | ||
74c68741 | 1653 | #define xhci_dbg(xhci, fmt, args...) \ |
b2497509 | 1654 | dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) |
74c68741 SS |
1655 | #define xhci_err(xhci, fmt, args...) \ |
1656 | dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) | |
1657 | #define xhci_warn(xhci, fmt, args...) \ | |
1658 | dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) | |
8202ce2e SS |
1659 | #define xhci_warn_ratelimited(xhci, fmt, args...) \ |
1660 | dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) | |
99705092 HG |
1661 | #define xhci_info(xhci, fmt, args...) \ |
1662 | dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) | |
74c68741 | 1663 | |
477632df SS |
1664 | /* |
1665 | * Registers should always be accessed with double word or quad word accesses. | |
1666 | * | |
1667 | * Some xHCI implementations may support 64-bit address pointers. Registers | |
1668 | * with 64-bit address pointers should be written to with dword accesses by | |
1669 | * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. | |
1670 | * xHCI implementations that do not support 64-bit address pointers will ignore | |
1671 | * the high dword, and write order is irrelevant. | |
1672 | */ | |
f7b2e403 SS |
1673 | static inline u64 xhci_read_64(const struct xhci_hcd *xhci, |
1674 | __le64 __iomem *regs) | |
1675 | { | |
1676 | __u32 __iomem *ptr = (__u32 __iomem *) regs; | |
1677 | u64 val_lo = readl(ptr); | |
1678 | u64 val_hi = readl(ptr + 1); | |
1679 | return val_lo + (val_hi << 32); | |
1680 | } | |
477632df SS |
1681 | static inline void xhci_write_64(struct xhci_hcd *xhci, |
1682 | const u64 val, __le64 __iomem *regs) | |
1683 | { | |
1684 | __u32 __iomem *ptr = (__u32 __iomem *) regs; | |
1685 | u32 val_lo = lower_32_bits(val); | |
1686 | u32 val_hi = upper_32_bits(val); | |
1687 | ||
1688 | writel(val_lo, ptr); | |
1689 | writel(val_hi, ptr + 1); | |
1690 | } | |
1691 | ||
b0567b3f SS |
1692 | static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) |
1693 | { | |
d7826599 | 1694 | return xhci->quirks & XHCI_LINK_TRB_QUIRK; |
b0567b3f SS |
1695 | } |
1696 | ||
66d4eadd | 1697 | /* xHCI debugging */ |
09ece30e | 1698 | void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num); |
66d4eadd | 1699 | void xhci_print_registers(struct xhci_hcd *xhci); |
0ebbab37 SS |
1700 | void xhci_dbg_regs(struct xhci_hcd *xhci); |
1701 | void xhci_print_run_regs(struct xhci_hcd *xhci); | |
d0e96f5a SS |
1702 | void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb); |
1703 | void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb); | |
7f84eef0 | 1704 | void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); |
0ebbab37 SS |
1705 | void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); |
1706 | void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); | |
1707 | void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); | |
7f84eef0 | 1708 | void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); |
d115b048 | 1709 | void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep); |
9c9a7dbf | 1710 | char *xhci_get_slot_state(struct xhci_hcd *xhci, |
2a8f82c4 | 1711 | struct xhci_container_ctx *ctx); |
e9df17eb SS |
1712 | void xhci_dbg_ep_rings(struct xhci_hcd *xhci, |
1713 | unsigned int slot_id, unsigned int ep_index, | |
1714 | struct xhci_virt_ep *ep); | |
84a99f6f XR |
1715 | void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), |
1716 | const char *fmt, ...); | |
66d4eadd | 1717 | |
3dbda77e | 1718 | /* xHCI memory management */ |
66d4eadd SS |
1719 | void xhci_mem_cleanup(struct xhci_hcd *xhci); |
1720 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); | |
3ffbba95 SS |
1721 | void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); |
1722 | int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); | |
1723 | int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); | |
2d1ee590 SS |
1724 | void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, |
1725 | struct usb_device *udev); | |
d0e96f5a | 1726 | unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); |
01c5f447 | 1727 | unsigned int xhci_get_endpoint_address(unsigned int ep_index); |
f94e0186 | 1728 | unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc); |
ac9d8fe7 SS |
1729 | unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index); |
1730 | unsigned int xhci_last_valid_endpoint(u32 added_ctxs); | |
f94e0186 | 1731 | void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); |
2e27980e SS |
1732 | void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci, |
1733 | struct xhci_bw_info *ep_bw, | |
1734 | struct xhci_interval_bw_table *bw_table, | |
1735 | struct usb_device *udev, | |
1736 | struct xhci_virt_ep *virt_ep, | |
1737 | struct xhci_tt_bw_info *tt_info); | |
1738 | void xhci_update_tt_active_eps(struct xhci_hcd *xhci, | |
1739 | struct xhci_virt_device *virt_dev, | |
1740 | int old_active_eps); | |
9af5d71d SS |
1741 | void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); |
1742 | void xhci_update_bw_info(struct xhci_hcd *xhci, | |
1743 | struct xhci_container_ctx *in_ctx, | |
1744 | struct xhci_input_control_ctx *ctrl_ctx, | |
1745 | struct xhci_virt_device *virt_dev); | |
f2217e8e | 1746 | void xhci_endpoint_copy(struct xhci_hcd *xhci, |
913a8a34 SS |
1747 | struct xhci_container_ctx *in_ctx, |
1748 | struct xhci_container_ctx *out_ctx, | |
1749 | unsigned int ep_index); | |
1750 | void xhci_slot_copy(struct xhci_hcd *xhci, | |
1751 | struct xhci_container_ctx *in_ctx, | |
1752 | struct xhci_container_ctx *out_ctx); | |
f88ba78d SS |
1753 | int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, |
1754 | struct usb_device *udev, struct usb_host_endpoint *ep, | |
1755 | gfp_t mem_flags); | |
f94e0186 | 1756 | void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); |
8dfec614 AX |
1757 | int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, |
1758 | unsigned int num_trbs, gfp_t flags); | |
412566bd SS |
1759 | void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci, |
1760 | struct xhci_virt_device *virt_dev, | |
1761 | unsigned int ep_index); | |
8df75f42 SS |
1762 | struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, |
1763 | unsigned int num_stream_ctxs, | |
1764 | unsigned int num_streams, gfp_t flags); | |
1765 | void xhci_free_stream_info(struct xhci_hcd *xhci, | |
1766 | struct xhci_stream_info *stream_info); | |
1767 | void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, | |
1768 | struct xhci_ep_ctx *ep_ctx, | |
1769 | struct xhci_stream_info *stream_info); | |
4daf9df5 | 1770 | void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, |
8df75f42 | 1771 | struct xhci_virt_ep *ep); |
2cf95c18 SS |
1772 | void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, |
1773 | struct xhci_virt_device *virt_dev, bool drop_control_ep); | |
e9df17eb SS |
1774 | struct xhci_ring *xhci_dma_to_transfer_ring( |
1775 | struct xhci_virt_ep *ep, | |
1776 | u64 address); | |
e9df17eb SS |
1777 | struct xhci_ring *xhci_stream_id_to_ring( |
1778 | struct xhci_virt_device *dev, | |
1779 | unsigned int ep_index, | |
1780 | unsigned int stream_id); | |
913a8a34 | 1781 | struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, |
a1d78c16 SS |
1782 | bool allocate_in_ctx, bool allocate_completion, |
1783 | gfp_t mem_flags); | |
4daf9df5 | 1784 | void xhci_urb_free_priv(struct urb_priv *urb_priv); |
913a8a34 SS |
1785 | void xhci_free_command(struct xhci_hcd *xhci, |
1786 | struct xhci_command *command); | |
66d4eadd | 1787 | |
66d4eadd | 1788 | /* xHCI host controller glue */ |
552e0c4f | 1789 | typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); |
dc0b177c | 1790 | int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); |
4f0f0bae | 1791 | void xhci_quiesce(struct xhci_hcd *xhci); |
66d4eadd SS |
1792 | int xhci_halt(struct xhci_hcd *xhci); |
1793 | int xhci_reset(struct xhci_hcd *xhci); | |
1794 | int xhci_init(struct usb_hcd *hcd); | |
1795 | int xhci_run(struct usb_hcd *hcd); | |
1796 | void xhci_stop(struct usb_hcd *hcd); | |
1797 | void xhci_shutdown(struct usb_hcd *hcd); | |
552e0c4f | 1798 | int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); |
cd33a321 RQ |
1799 | void xhci_init_driver(struct hc_driver *drv, |
1800 | const struct xhci_driver_overrides *over); | |
436a3890 SS |
1801 | |
1802 | #ifdef CONFIG_PM | |
a1377e53 | 1803 | int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); |
5535b1d5 | 1804 | int xhci_resume(struct xhci_hcd *xhci, bool hibernated); |
436a3890 SS |
1805 | #else |
1806 | #define xhci_suspend NULL | |
1807 | #define xhci_resume NULL | |
1808 | #endif | |
1809 | ||
66d4eadd | 1810 | int xhci_get_frame(struct usb_hcd *hcd); |
7f84eef0 | 1811 | irqreturn_t xhci_irq(struct usb_hcd *hcd); |
851ec164 | 1812 | irqreturn_t xhci_msi_irq(int irq, void *hcd); |
3ffbba95 SS |
1813 | int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); |
1814 | void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev); | |
839c817c SS |
1815 | int xhci_alloc_tt_info(struct xhci_hcd *xhci, |
1816 | struct xhci_virt_device *virt_dev, | |
1817 | struct usb_device *hdev, | |
1818 | struct usb_tt *tt, gfp_t mem_flags); | |
8df75f42 SS |
1819 | int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev, |
1820 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
1821 | unsigned int num_streams, gfp_t mem_flags); | |
1822 | int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev, | |
1823 | struct usb_host_endpoint **eps, unsigned int num_eps, | |
1824 | gfp_t mem_flags); | |
3ffbba95 | 1825 | int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev); |
48fc7dbd | 1826 | int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev); |
9574323c | 1827 | int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev); |
65580b43 AX |
1828 | int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, |
1829 | struct usb_device *udev, int enable); | |
ac1c1b7f SS |
1830 | int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev, |
1831 | struct usb_tt *tt, gfp_t mem_flags); | |
d0e96f5a SS |
1832 | int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags); |
1833 | int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status); | |
f94e0186 SS |
1834 | int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); |
1835 | int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep); | |
a1587d97 | 1836 | void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); |
f0615c45 | 1837 | int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev); |
f94e0186 SS |
1838 | int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); |
1839 | void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev); | |
7f84eef0 SS |
1840 | |
1841 | /* xHCI ring, segment, TRB, and TD functions */ | |
23e3be11 | 1842 | dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); |
cffb9be8 HG |
1843 | struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, |
1844 | struct xhci_segment *start_seg, union xhci_trb *start_trb, | |
1845 | union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); | |
b45b5069 | 1846 | int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); |
23e3be11 | 1847 | void xhci_ring_cmd_db(struct xhci_hcd *xhci); |
ddba5cd0 MN |
1848 | int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, |
1849 | u32 trb_type, u32 slot_id); | |
1850 | int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, | |
1851 | dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); | |
1852 | int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, | |
0238634d | 1853 | u32 field1, u32 field2, u32 field3, u32 field4); |
ddba5cd0 MN |
1854 | int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, |
1855 | int slot_id, unsigned int ep_index, int suspend); | |
23e3be11 SS |
1856 | int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, |
1857 | int slot_id, unsigned int ep_index); | |
1858 | int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, | |
1859 | int slot_id, unsigned int ep_index); | |
624defa1 SS |
1860 | int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, |
1861 | int slot_id, unsigned int ep_index); | |
04e51901 AX |
1862 | int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, |
1863 | struct urb *urb, int slot_id, unsigned int ep_index); | |
ddba5cd0 MN |
1864 | int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, |
1865 | struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, | |
1866 | bool command_must_succeed); | |
1867 | int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, | |
1868 | dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); | |
1869 | int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, | |
1870 | int slot_id, unsigned int ep_index); | |
1871 | int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, | |
1872 | u32 slot_id); | |
c92bcfa7 SS |
1873 | void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, |
1874 | unsigned int slot_id, unsigned int ep_index, | |
e9df17eb SS |
1875 | unsigned int stream_id, struct xhci_td *cur_td, |
1876 | struct xhci_dequeue_state *state); | |
c92bcfa7 | 1877 | void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, |
63a0d9ab | 1878 | unsigned int slot_id, unsigned int ep_index, |
e9df17eb | 1879 | unsigned int stream_id, |
63a0d9ab | 1880 | struct xhci_dequeue_state *deq_state); |
82d1009f | 1881 | void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, |
d97b4f8d | 1882 | unsigned int ep_index, struct xhci_td *td); |
ac9d8fe7 SS |
1883 | void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci, |
1884 | unsigned int slot_id, unsigned int ep_index, | |
1885 | struct xhci_dequeue_state *deq_state); | |
6f5165cf | 1886 | void xhci_stop_endpoint_command_watchdog(unsigned long arg); |
c311e391 MN |
1887 | void xhci_handle_command_timeout(unsigned long data); |
1888 | ||
be88fe4f AX |
1889 | void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, |
1890 | unsigned int ep_index, unsigned int stream_id); | |
c9aa1a2d | 1891 | void xhci_cleanup_command_queue(struct xhci_hcd *xhci); |
66d4eadd | 1892 | |
0f2a7930 | 1893 | /* xHCI roothub code */ |
c9682dff AX |
1894 | void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, |
1895 | int port_id, u32 link_state); | |
3b3db026 SS |
1896 | int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd, |
1897 | struct usb_device *udev, enum usb3_link_state state); | |
1898 | int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd, | |
1899 | struct usb_device *udev, enum usb3_link_state state); | |
d2f52c9e AX |
1900 | void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, |
1901 | int port_id, u32 port_bit); | |
0f2a7930 SS |
1902 | int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, |
1903 | char *buf, u16 wLength); | |
1904 | int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); | |
3f5eb141 | 1905 | int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); |
436a3890 SS |
1906 | |
1907 | #ifdef CONFIG_PM | |
9777e3ce AX |
1908 | int xhci_bus_suspend(struct usb_hcd *hcd); |
1909 | int xhci_bus_resume(struct usb_hcd *hcd); | |
436a3890 SS |
1910 | #else |
1911 | #define xhci_bus_suspend NULL | |
1912 | #define xhci_bus_resume NULL | |
1913 | #endif /* CONFIG_PM */ | |
1914 | ||
56192531 | 1915 | u32 xhci_port_state_to_neutral(u32 state); |
5233630f SS |
1916 | int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, |
1917 | u16 port); | |
56192531 | 1918 | void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); |
0f2a7930 | 1919 | |
d115b048 | 1920 | /* xHCI contexts */ |
4daf9df5 | 1921 | struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); |
d115b048 JY |
1922 | struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); |
1923 | struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); | |
1924 | ||
74c68741 | 1925 | #endif /* __LINUX_XHCI_HCD_H */ |