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74c68741 SS |
1 | /* |
2 | * xHCI host controller driver | |
3 | * | |
4 | * Copyright (C) 2008 Intel Corp. | |
5 | * | |
6 | * Author: Sarah Sharp | |
7 | * Some code borrowed from the Linux EHCI driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | * for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software Foundation, | |
20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #ifndef __LINUX_XHCI_HCD_H | |
24 | #define __LINUX_XHCI_HCD_H | |
25 | ||
26 | #include <linux/usb.h> | |
7f84eef0 | 27 | #include <linux/timer.h> |
74c68741 SS |
28 | |
29 | #include "../core/hcd.h" | |
30 | /* Code sharing between pci-quirks and xhci hcd */ | |
31 | #include "xhci-ext-caps.h" | |
32 | ||
33 | /* xHCI PCI Configuration Registers */ | |
34 | #define XHCI_SBRN_OFFSET (0x60) | |
35 | ||
66d4eadd SS |
36 | /* Max number of USB devices for any host controller - limit in section 6.1 */ |
37 | #define MAX_HC_SLOTS 256 | |
38 | ||
74c68741 SS |
39 | /* |
40 | * xHCI register interface. | |
41 | * This corresponds to the eXtensible Host Controller Interface (xHCI) | |
42 | * Revision 0.95 specification | |
43 | * | |
44 | * Registers should always be accessed with double word or quad word accesses. | |
45 | * | |
46 | * Some xHCI implementations may support 64-bit address pointers. Registers | |
47 | * with 64-bit address pointers should be written to with dword accesses by | |
48 | * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. | |
49 | * xHCI implementations that do not support 64-bit address pointers will ignore | |
50 | * the high dword, and write order is irrelevant. | |
51 | */ | |
52 | ||
53 | /** | |
54 | * struct xhci_cap_regs - xHCI Host Controller Capability Registers. | |
55 | * @hc_capbase: length of the capabilities register and HC version number | |
56 | * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 | |
57 | * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 | |
58 | * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 | |
59 | * @hcc_params: HCCPARAMS - Capability Parameters | |
60 | * @db_off: DBOFF - Doorbell array offset | |
61 | * @run_regs_off: RTSOFF - Runtime register space offset | |
62 | */ | |
63 | struct xhci_cap_regs { | |
64 | u32 hc_capbase; | |
65 | u32 hcs_params1; | |
66 | u32 hcs_params2; | |
67 | u32 hcs_params3; | |
68 | u32 hcc_params; | |
69 | u32 db_off; | |
70 | u32 run_regs_off; | |
71 | /* Reserved up to (CAPLENGTH - 0x1C) */ | |
72 | } __attribute__ ((packed)); | |
73 | ||
74 | /* hc_capbase bitmasks */ | |
75 | /* bits 7:0 - how long is the Capabilities register */ | |
76 | #define HC_LENGTH(p) XHCI_HC_LENGTH(p) | |
77 | /* bits 31:16 */ | |
78 | #define HC_VERSION(p) (((p) >> 16) & 0xffff) | |
79 | ||
80 | /* HCSPARAMS1 - hcs_params1 - bitmasks */ | |
81 | /* bits 0:7, Max Device Slots */ | |
82 | #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) | |
83 | #define HCS_SLOTS_MASK 0xff | |
84 | /* bits 8:18, Max Interrupters */ | |
85 | #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) | |
86 | /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ | |
87 | #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) | |
88 | ||
89 | /* HCSPARAMS2 - hcs_params2 - bitmasks */ | |
90 | /* bits 0:3, frames or uframes that SW needs to queue transactions | |
91 | * ahead of the HW to meet periodic deadlines */ | |
92 | #define HCS_IST(p) (((p) >> 0) & 0xf) | |
93 | /* bits 4:7, max number of Event Ring segments */ | |
94 | #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) | |
95 | /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ | |
96 | /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */ | |
97 | ||
98 | /* HCSPARAMS3 - hcs_params3 - bitmasks */ | |
99 | /* bits 0:7, Max U1 to U0 latency for the roothub ports */ | |
100 | #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) | |
101 | /* bits 16:31, Max U2 to U0 latency for the roothub ports */ | |
102 | #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) | |
103 | ||
104 | /* HCCPARAMS - hcc_params - bitmasks */ | |
105 | /* true: HC can use 64-bit address pointers */ | |
106 | #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) | |
107 | /* true: HC can do bandwidth negotiation */ | |
108 | #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) | |
109 | /* true: HC uses 64-byte Device Context structures | |
110 | * FIXME 64-byte context structures aren't supported yet. | |
111 | */ | |
112 | #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) | |
113 | /* true: HC has port power switches */ | |
114 | #define HCC_PPC(p) ((p) & (1 << 3)) | |
115 | /* true: HC has port indicators */ | |
116 | #define HCS_INDICATOR(p) ((p) & (1 << 4)) | |
117 | /* true: HC has Light HC Reset Capability */ | |
118 | #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) | |
119 | /* true: HC supports latency tolerance messaging */ | |
120 | #define HCC_LTC(p) ((p) & (1 << 6)) | |
121 | /* true: no secondary Stream ID Support */ | |
122 | #define HCC_NSS(p) ((p) & (1 << 7)) | |
123 | /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ | |
124 | #define HCC_MAX_PSA (1 << ((((p) >> 12) & 0xf) + 1)) | |
125 | /* Extended Capabilities pointer from PCI base - section 5.3.6 */ | |
126 | #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) | |
127 | ||
128 | /* db_off bitmask - bits 0:1 reserved */ | |
129 | #define DBOFF_MASK (~0x3) | |
130 | ||
131 | /* run_regs_off bitmask - bits 0:4 reserved */ | |
132 | #define RTSOFF_MASK (~0x1f) | |
133 | ||
134 | ||
135 | /* Number of registers per port */ | |
136 | #define NUM_PORT_REGS 4 | |
137 | ||
138 | /** | |
139 | * struct xhci_op_regs - xHCI Host Controller Operational Registers. | |
140 | * @command: USBCMD - xHC command register | |
141 | * @status: USBSTS - xHC status register | |
142 | * @page_size: This indicates the page size that the host controller | |
143 | * supports. If bit n is set, the HC supports a page size | |
144 | * of 2^(n+12), up to a 128MB page size. | |
145 | * 4K is the minimum page size. | |
146 | * @cmd_ring: CRP - 64-bit Command Ring Pointer | |
147 | * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer | |
148 | * @config_reg: CONFIG - Configure Register | |
149 | * @port_status_base: PORTSCn - base address for Port Status and Control | |
150 | * Each port has a Port Status and Control register, | |
151 | * followed by a Port Power Management Status and Control | |
152 | * register, a Port Link Info register, and a reserved | |
153 | * register. | |
154 | * @port_power_base: PORTPMSCn - base address for | |
155 | * Port Power Management Status and Control | |
156 | * @port_link_base: PORTLIn - base address for Port Link Info (current | |
157 | * Link PM state and control) for USB 2.1 and USB 3.0 | |
158 | * devices. | |
159 | */ | |
160 | struct xhci_op_regs { | |
161 | u32 command; | |
162 | u32 status; | |
163 | u32 page_size; | |
164 | u32 reserved1; | |
165 | u32 reserved2; | |
166 | u32 dev_notification; | |
167 | u32 cmd_ring[2]; | |
168 | /* rsvd: offset 0x20-2F */ | |
169 | u32 reserved3[4]; | |
170 | u32 dcbaa_ptr[2]; | |
171 | u32 config_reg; | |
172 | /* rsvd: offset 0x3C-3FF */ | |
173 | u32 reserved4[241]; | |
174 | /* port 1 registers, which serve as a base address for other ports */ | |
175 | u32 port_status_base; | |
176 | u32 port_power_base; | |
177 | u32 port_link_base; | |
178 | u32 reserved5; | |
179 | /* registers for ports 2-255 */ | |
180 | u32 reserved6[NUM_PORT_REGS*254]; | |
181 | } __attribute__ ((packed)); | |
182 | ||
183 | /* USBCMD - USB command - command bitmasks */ | |
184 | /* start/stop HC execution - do not write unless HC is halted*/ | |
185 | #define CMD_RUN XHCI_CMD_RUN | |
186 | /* Reset HC - resets internal HC state machine and all registers (except | |
187 | * PCI config regs). HC does NOT drive a USB reset on the downstream ports. | |
188 | * The xHCI driver must reinitialize the xHC after setting this bit. | |
189 | */ | |
190 | #define CMD_RESET (1 << 1) | |
191 | /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ | |
192 | #define CMD_EIE XHCI_CMD_EIE | |
193 | /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ | |
194 | #define CMD_HSEIE XHCI_CMD_HSEIE | |
195 | /* bits 4:6 are reserved (and should be preserved on writes). */ | |
196 | /* light reset (port status stays unchanged) - reset completed when this is 0 */ | |
197 | #define CMD_LRESET (1 << 7) | |
198 | /* FIXME: ignoring host controller save/restore state for now. */ | |
199 | #define CMD_CSS (1 << 8) | |
200 | #define CMD_CRS (1 << 9) | |
201 | /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ | |
202 | #define CMD_EWE XHCI_CMD_EWE | |
203 | /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root | |
204 | * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. | |
205 | * '0' means the xHC can power it off if all ports are in the disconnect, | |
206 | * disabled, or powered-off state. | |
207 | */ | |
208 | #define CMD_PM_INDEX (1 << 11) | |
209 | /* bits 12:31 are reserved (and should be preserved on writes). */ | |
210 | ||
211 | /* USBSTS - USB status - status bitmasks */ | |
212 | /* HC not running - set to 1 when run/stop bit is cleared. */ | |
213 | #define STS_HALT XHCI_STS_HALT | |
214 | /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ | |
215 | #define STS_FATAL (1 << 2) | |
216 | /* event interrupt - clear this prior to clearing any IP flags in IR set*/ | |
217 | #define STS_EINT (1 << 3) | |
218 | /* port change detect */ | |
219 | #define STS_PORT (1 << 4) | |
220 | /* bits 5:7 reserved and zeroed */ | |
221 | /* save state status - '1' means xHC is saving state */ | |
222 | #define STS_SAVE (1 << 8) | |
223 | /* restore state status - '1' means xHC is restoring state */ | |
224 | #define STS_RESTORE (1 << 9) | |
225 | /* true: save or restore error */ | |
226 | #define STS_SRE (1 << 10) | |
227 | /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ | |
228 | #define STS_CNR XHCI_STS_CNR | |
229 | /* true: internal Host Controller Error - SW needs to reset and reinitialize */ | |
230 | #define STS_HCE (1 << 12) | |
231 | /* bits 13:31 reserved and should be preserved */ | |
232 | ||
233 | /* | |
234 | * DNCTRL - Device Notification Control Register - dev_notification bitmasks | |
235 | * Generate a device notification event when the HC sees a transaction with a | |
236 | * notification type that matches a bit set in this bit field. | |
237 | */ | |
238 | #define DEV_NOTE_MASK (0xffff) | |
239 | #define ENABLE_DEV_NOTE(x) (1 << x) | |
240 | /* Most of the device notification types should only be used for debug. | |
241 | * SW does need to pay attention to function wake notifications. | |
242 | */ | |
243 | #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) | |
244 | ||
0ebbab37 SS |
245 | /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ |
246 | /* bit 0 is the command ring cycle state */ | |
247 | /* stop ring operation after completion of the currently executing command */ | |
248 | #define CMD_RING_PAUSE (1 << 1) | |
249 | /* stop ring immediately - abort the currently executing command */ | |
250 | #define CMD_RING_ABORT (1 << 2) | |
251 | /* true: command ring is running */ | |
252 | #define CMD_RING_RUNNING (1 << 3) | |
253 | /* bits 4:5 reserved and should be preserved */ | |
254 | /* Command Ring pointer - bit mask for the lower 32 bits. */ | |
255 | #define CMD_RING_ADDR_MASK (0xffffffc0) | |
256 | ||
74c68741 SS |
257 | /* CONFIG - Configure Register - config_reg bitmasks */ |
258 | /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ | |
259 | #define MAX_DEVS(p) ((p) & 0xff) | |
260 | /* bits 8:31 - reserved and should be preserved */ | |
261 | ||
262 | /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ | |
263 | /* true: device connected */ | |
264 | #define PORT_CONNECT (1 << 0) | |
265 | /* true: port enabled */ | |
266 | #define PORT_PE (1 << 1) | |
267 | /* bit 2 reserved and zeroed */ | |
268 | /* true: port has an over-current condition */ | |
269 | #define PORT_OC (1 << 3) | |
270 | /* true: port reset signaling asserted */ | |
271 | #define PORT_RESET (1 << 4) | |
272 | /* Port Link State - bits 5:8 | |
273 | * A read gives the current link PM state of the port, | |
274 | * a write with Link State Write Strobe set sets the link state. | |
275 | */ | |
276 | /* true: port has power (see HCC_PPC) */ | |
277 | #define PORT_POWER (1 << 9) | |
278 | /* bits 10:13 indicate device speed: | |
279 | * 0 - undefined speed - port hasn't be initialized by a reset yet | |
280 | * 1 - full speed | |
281 | * 2 - low speed | |
282 | * 3 - high speed | |
283 | * 4 - super speed | |
284 | * 5-15 reserved | |
285 | */ | |
286 | #define DEV_SPEED_MASK (0xf<<10) | |
287 | #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) | |
288 | #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == (0x1<<10)) | |
289 | #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == (0x2<<10)) | |
290 | #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == (0x3<<10)) | |
291 | #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == (0x4<<10)) | |
292 | /* Port Indicator Control */ | |
293 | #define PORT_LED_OFF (0 << 14) | |
294 | #define PORT_LED_AMBER (1 << 14) | |
295 | #define PORT_LED_GREEN (2 << 14) | |
296 | #define PORT_LED_MASK (3 << 14) | |
297 | /* Port Link State Write Strobe - set this when changing link state */ | |
298 | #define PORT_LINK_STROBE (1 << 16) | |
299 | /* true: connect status change */ | |
300 | #define PORT_CSC (1 << 17) | |
301 | /* true: port enable change */ | |
302 | #define PORT_PEC (1 << 18) | |
303 | /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port | |
304 | * into an enabled state, and the device into the default state. A "warm" reset | |
305 | * also resets the link, forcing the device through the link training sequence. | |
306 | * SW can also look at the Port Reset register to see when warm reset is done. | |
307 | */ | |
308 | #define PORT_WRC (1 << 19) | |
309 | /* true: over-current change */ | |
310 | #define PORT_OCC (1 << 20) | |
311 | /* true: reset change - 1 to 0 transition of PORT_RESET */ | |
312 | #define PORT_RC (1 << 21) | |
313 | /* port link status change - set on some port link state transitions: | |
314 | * Transition Reason | |
315 | * ------------------------------------------------------------------------------ | |
316 | * - U3 to Resume Wakeup signaling from a device | |
317 | * - Resume to Recovery to U0 USB 3.0 device resume | |
318 | * - Resume to U0 USB 2.0 device resume | |
319 | * - U3 to Recovery to U0 Software resume of USB 3.0 device complete | |
320 | * - U3 to U0 Software resume of USB 2.0 device complete | |
321 | * - U2 to U0 L1 resume of USB 2.1 device complete | |
322 | * - U0 to U0 (???) L1 entry rejection by USB 2.1 device | |
323 | * - U0 to disabled L1 entry error with USB 2.1 device | |
324 | * - Any state to inactive Error on USB 3.0 port | |
325 | */ | |
326 | #define PORT_PLC (1 << 22) | |
327 | /* port configure error change - port failed to configure its link partner */ | |
328 | #define PORT_CEC (1 << 23) | |
329 | /* bit 24 reserved */ | |
330 | /* wake on connect (enable) */ | |
331 | #define PORT_WKCONN_E (1 << 25) | |
332 | /* wake on disconnect (enable) */ | |
333 | #define PORT_WKDISC_E (1 << 26) | |
334 | /* wake on over-current (enable) */ | |
335 | #define PORT_WKOC_E (1 << 27) | |
336 | /* bits 28:29 reserved */ | |
337 | /* true: device is removable - for USB 3.0 roothub emulation */ | |
338 | #define PORT_DEV_REMOVE (1 << 30) | |
339 | /* Initiate a warm port reset - complete when PORT_WRC is '1' */ | |
340 | #define PORT_WR (1 << 31) | |
341 | ||
342 | /* Port Power Management Status and Control - port_power_base bitmasks */ | |
343 | /* Inactivity timer value for transitions into U1, in microseconds. | |
344 | * Timeout can be up to 127us. 0xFF means an infinite timeout. | |
345 | */ | |
346 | #define PORT_U1_TIMEOUT(p) ((p) & 0xff) | |
347 | /* Inactivity timer value for transitions into U2 */ | |
348 | #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) | |
349 | /* Bits 24:31 for port testing */ | |
350 | ||
351 | ||
352 | /** | |
353 | * struct intr_reg - Interrupt Register Set | |
354 | * @irq_pending: IMAN - Interrupt Management Register. Used to enable | |
355 | * interrupts and check for pending interrupts. | |
356 | * @irq_control: IMOD - Interrupt Moderation Register. | |
357 | * Used to throttle interrupts. | |
358 | * @erst_size: Number of segments in the Event Ring Segment Table (ERST). | |
359 | * @erst_base: ERST base address. | |
360 | * @erst_dequeue: Event ring dequeue pointer. | |
361 | * | |
362 | * Each interrupter (defined by a MSI-X vector) has an event ring and an Event | |
363 | * Ring Segment Table (ERST) associated with it. The event ring is comprised of | |
364 | * multiple segments of the same size. The HC places events on the ring and | |
365 | * "updates the Cycle bit in the TRBs to indicate to software the current | |
366 | * position of the Enqueue Pointer." The HCD (Linux) processes those events and | |
367 | * updates the dequeue pointer. | |
368 | */ | |
369 | struct intr_reg { | |
370 | u32 irq_pending; | |
371 | u32 irq_control; | |
372 | u32 erst_size; | |
373 | u32 rsvd; | |
374 | u32 erst_base[2]; | |
375 | u32 erst_dequeue[2]; | |
376 | } __attribute__ ((packed)); | |
377 | ||
66d4eadd | 378 | /* irq_pending bitmasks */ |
74c68741 | 379 | #define ER_IRQ_PENDING(p) ((p) & 0x1) |
66d4eadd | 380 | /* bits 2:31 need to be preserved */ |
7f84eef0 | 381 | /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ |
66d4eadd SS |
382 | #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) |
383 | #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) | |
384 | #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) | |
385 | ||
386 | /* irq_control bitmasks */ | |
387 | /* Minimum interval between interrupts (in 250ns intervals). The interval | |
388 | * between interrupts will be longer if there are no events on the event ring. | |
389 | * Default is 4000 (1 ms). | |
390 | */ | |
391 | #define ER_IRQ_INTERVAL_MASK (0xffff) | |
392 | /* Counter used to count down the time to the next interrupt - HW use only */ | |
393 | #define ER_IRQ_COUNTER_MASK (0xffff << 16) | |
394 | ||
395 | /* erst_size bitmasks */ | |
74c68741 | 396 | /* Preserve bits 16:31 of erst_size */ |
66d4eadd SS |
397 | #define ERST_SIZE_MASK (0xffff << 16) |
398 | ||
399 | /* erst_dequeue bitmasks */ | |
400 | /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) | |
401 | * where the current dequeue pointer lies. This is an optional HW hint. | |
402 | */ | |
403 | #define ERST_DESI_MASK (0x7) | |
404 | /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by | |
405 | * a work queue (or delayed service routine)? | |
406 | */ | |
407 | #define ERST_EHB (1 << 3) | |
0ebbab37 | 408 | #define ERST_PTR_MASK (0xf) |
74c68741 SS |
409 | |
410 | /** | |
411 | * struct xhci_run_regs | |
412 | * @microframe_index: | |
413 | * MFINDEX - current microframe number | |
414 | * | |
415 | * Section 5.5 Host Controller Runtime Registers: | |
416 | * "Software should read and write these registers using only Dword (32 bit) | |
417 | * or larger accesses" | |
418 | */ | |
419 | struct xhci_run_regs { | |
420 | u32 microframe_index; | |
421 | u32 rsvd[7]; | |
422 | struct intr_reg ir_set[128]; | |
423 | } __attribute__ ((packed)); | |
424 | ||
0ebbab37 SS |
425 | /** |
426 | * struct doorbell_array | |
427 | * | |
428 | * Section 5.6 | |
429 | */ | |
430 | struct xhci_doorbell_array { | |
431 | u32 doorbell[256]; | |
432 | } __attribute__ ((packed)); | |
433 | ||
434 | #define DB_TARGET_MASK 0xFFFFFF00 | |
435 | #define DB_STREAM_ID_MASK 0x0000FFFF | |
436 | #define DB_TARGET_HOST 0x0 | |
437 | #define DB_STREAM_ID_HOST 0x0 | |
438 | #define DB_MASK (0xff << 8) | |
439 | ||
440 | ||
a74588f9 SS |
441 | /** |
442 | * struct xhci_slot_ctx | |
443 | * @dev_info: Route string, device speed, hub info, and last valid endpoint | |
444 | * @dev_info2: Max exit latency for device number, root hub port number | |
445 | * @tt_info: tt_info is used to construct split transaction tokens | |
446 | * @dev_state: slot state and device address | |
447 | * | |
448 | * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context | |
449 | * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes | |
450 | * reserved at the end of the slot context for HC internal use. | |
451 | */ | |
452 | struct xhci_slot_ctx { | |
453 | u32 dev_info; | |
454 | u32 dev_info2; | |
455 | u32 tt_info; | |
456 | u32 dev_state; | |
457 | /* offset 0x10 to 0x1f reserved for HC internal use */ | |
458 | u32 reserved[4]; | |
459 | } __attribute__ ((packed)); | |
460 | ||
461 | /* dev_info bitmasks */ | |
462 | /* Route String - 0:19 */ | |
463 | #define ROUTE_STRING_MASK (0xfffff) | |
464 | /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ | |
465 | #define DEV_SPEED (0xf << 20) | |
466 | /* bit 24 reserved */ | |
467 | /* Is this LS/FS device connected through a HS hub? - bit 25 */ | |
468 | #define DEV_MTT (0x1 << 25) | |
469 | /* Set if the device is a hub - bit 26 */ | |
470 | #define DEV_HUB (0x1 << 26) | |
471 | /* Index of the last valid endpoint context in this device context - 27:31 */ | |
472 | #define LAST_EP_MASK (0x1f << 27) | |
473 | #define LAST_EP(p) ((p) << 27) | |
474 | ||
475 | /* dev_info2 bitmasks */ | |
476 | /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ | |
477 | #define MAX_EXIT (0xffff) | |
478 | /* Root hub port number that is needed to access the USB device */ | |
479 | #define ROOT_HUB_PORT (0xff << 16) | |
480 | ||
481 | /* tt_info bitmasks */ | |
482 | /* | |
483 | * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub | |
484 | * The Slot ID of the hub that isolates the high speed signaling from | |
485 | * this low or full-speed device. '0' if attached to root hub port. | |
486 | */ | |
487 | #define TT_SLOT (0xff) | |
488 | /* | |
489 | * The number of the downstream facing port of the high-speed hub | |
490 | * '0' if the device is not low or full speed. | |
491 | */ | |
492 | #define TT_PORT (0xff << 8) | |
493 | ||
494 | /* dev_state bitmasks */ | |
495 | /* USB device address - assigned by the HC */ | |
496 | #define DEV_ADDR (0xff) | |
497 | /* bits 8:26 reserved */ | |
498 | /* Slot state */ | |
499 | #define SLOT_STATE (0x1f << 27) | |
500 | ||
501 | ||
502 | /** | |
503 | * struct xhci_ep_ctx | |
504 | * @ep_info: endpoint state, streams, mult, and interval information. | |
505 | * @ep_info2: information on endpoint type, max packet size, max burst size, | |
506 | * error count, and whether the HC will force an event for all | |
507 | * transactions. | |
508 | * @ep_ring: 64-bit ring address. If the endpoint only defines one flow, | |
509 | * this points to the endpoint transfer ring. Otherwise, it points | |
510 | * to a flow context array, which has a ring pointer for each flow. | |
511 | * @intr_target: | |
512 | * 64-bit address of the Interrupter Target that will receive | |
513 | * events from this endpoint. | |
514 | * | |
515 | * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context | |
516 | * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes | |
517 | * reserved at the end of the endpoint context for HC internal use. | |
518 | */ | |
519 | struct xhci_ep_ctx { | |
520 | u32 ep_info; | |
521 | u32 ep_info2; | |
522 | /* 64-bit endpoint ring address */ | |
523 | u32 ep_ring[2]; | |
524 | /* 64-bit address of the interrupter target */ | |
525 | u32 intr_target[2]; | |
526 | /* offset 0x14 - 0x1f reserved for HC internal use */ | |
527 | u32 reserved[2]; | |
528 | } __attribute__ ((packed)); | |
529 | ||
530 | /* ep_info bitmasks */ | |
531 | /* | |
532 | * Endpoint State - bits 0:2 | |
533 | * 0 - disabled | |
534 | * 1 - running | |
535 | * 2 - halted due to halt condition - ok to manipulate endpoint ring | |
536 | * 3 - stopped | |
537 | * 4 - TRB error | |
538 | * 5-7 - reserved | |
539 | */ | |
540 | #define EP_STATE (0xf) | |
541 | /* Mult - Max number of burtst within an interval, in EP companion desc. */ | |
542 | #define EP_MULT(p) ((p & 0x3) << 8) | |
543 | /* bits 10:14 are Max Primary Streams */ | |
544 | /* bit 15 is Linear Stream Array */ | |
545 | /* Interval - period between requests to an endpoint - 125u increments. */ | |
546 | #define EP_INTERVAL (0xff << 16) | |
547 | ||
548 | /* ep_info2 bitmasks */ | |
549 | /* | |
550 | * Force Event - generate transfer events for all TRBs for this endpoint | |
551 | * This will tell the HC to ignore the IOC and ISP flags (for debugging only). | |
552 | */ | |
553 | #define FORCE_EVENT (0x1) | |
554 | #define ERROR_COUNT(p) (((p) & 0x3) << 1) | |
555 | #define EP_TYPE(p) ((p) << 3) | |
556 | #define ISOC_OUT_EP 1 | |
557 | #define BULK_OUT_EP 2 | |
558 | #define INT_OUT_EP 3 | |
559 | #define CTRL_EP 4 | |
560 | #define ISOC_IN_EP 5 | |
561 | #define BULK_IN_EP 6 | |
562 | #define INT_IN_EP 7 | |
563 | /* bit 6 reserved */ | |
564 | /* bit 7 is Host Initiate Disable - for disabling stream selection */ | |
565 | #define MAX_BURST(p) (((p)&0xff) << 8) | |
566 | #define MAX_PACKET(p) (((p)&0xffff) << 16) | |
567 | ||
568 | ||
569 | /** | |
570 | * struct xhci_device_control | |
571 | * Input/Output context; see section 6.2.5. | |
572 | * | |
573 | * @drop_context: set the bit of the endpoint context you want to disable | |
574 | * @add_context: set the bit of the endpoint context you want to enable | |
575 | */ | |
576 | struct xhci_device_control { | |
577 | u32 drop_flags; | |
578 | u32 add_flags; | |
579 | u32 rsvd[6]; | |
580 | struct xhci_slot_ctx slot; | |
581 | struct xhci_ep_ctx ep[31]; | |
582 | } __attribute__ ((packed)); | |
583 | ||
584 | /* drop context bitmasks */ | |
585 | #define DROP_EP(x) (0x1 << x) | |
586 | /* add context bitmasks */ | |
587 | #define ADD_EP(x) (0x1 << x) | |
588 | ||
589 | ||
590 | /** | |
591 | * struct xhci_device_context_array | |
592 | * @dev_context_ptr array of 64-bit DMA addresses for device contexts | |
593 | */ | |
594 | struct xhci_device_context_array { | |
595 | /* 64-bit device addresses; we only write 32-bit addresses */ | |
596 | u32 dev_context_ptrs[2*MAX_HC_SLOTS]; | |
597 | /* private xHCD pointers */ | |
598 | dma_addr_t dma; | |
599 | } __attribute__ ((packed)); | |
600 | /* TODO: write function to set the 64-bit device DMA address */ | |
601 | /* | |
602 | * TODO: change this to be dynamically sized at HC mem init time since the HC | |
603 | * might not be able to handle the maximum number of devices possible. | |
604 | */ | |
605 | ||
606 | ||
607 | struct xhci_stream_ctx { | |
608 | /* 64-bit stream ring address, cycle state, and stream type */ | |
609 | u32 stream_ring[2]; | |
610 | /* offset 0x14 - 0x1f reserved for HC internal use */ | |
611 | u32 reserved[2]; | |
612 | } __attribute__ ((packed)); | |
613 | ||
614 | ||
0ebbab37 SS |
615 | struct xhci_transfer_event { |
616 | /* 64-bit buffer address, or immediate data */ | |
617 | u32 buffer[2]; | |
618 | u32 transfer_len; | |
619 | /* This field is interpreted differently based on the type of TRB */ | |
620 | u32 flags; | |
621 | } __attribute__ ((packed)); | |
622 | ||
623 | /* Completion Code - only applicable for some types of TRBs */ | |
624 | #define COMP_CODE_MASK (0xff << 24) | |
625 | #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) | |
626 | #define COMP_SUCCESS 1 | |
627 | /* Data Buffer Error */ | |
628 | #define COMP_DB_ERR 2 | |
629 | /* Babble Detected Error */ | |
630 | #define COMP_BABBLE 3 | |
631 | /* USB Transaction Error */ | |
632 | #define COMP_TX_ERR 4 | |
633 | /* TRB Error - some TRB field is invalid */ | |
634 | #define COMP_TRB_ERR 5 | |
635 | /* Stall Error - USB device is stalled */ | |
636 | #define COMP_STALL 6 | |
637 | /* Resource Error - HC doesn't have memory for that device configuration */ | |
638 | #define COMP_ENOMEM 7 | |
639 | /* Bandwidth Error - not enough room in schedule for this dev config */ | |
640 | #define COMP_BW_ERR 8 | |
641 | /* No Slots Available Error - HC ran out of device slots */ | |
642 | #define COMP_ENOSLOTS 9 | |
643 | /* Invalid Stream Type Error */ | |
644 | #define COMP_STREAM_ERR 10 | |
645 | /* Slot Not Enabled Error - doorbell rung for disabled device slot */ | |
646 | #define COMP_EBADSLT 11 | |
647 | /* Endpoint Not Enabled Error */ | |
648 | #define COMP_EBADEP 12 | |
649 | /* Short Packet */ | |
650 | #define COMP_SHORT_TX 13 | |
651 | /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */ | |
652 | #define COMP_UNDERRUN 14 | |
653 | /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */ | |
654 | #define COMP_OVERRUN 15 | |
655 | /* Virtual Function Event Ring Full Error */ | |
656 | #define COMP_VF_FULL 16 | |
657 | /* Parameter Error - Context parameter is invalid */ | |
658 | #define COMP_EINVAL 17 | |
659 | /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */ | |
660 | #define COMP_BW_OVER 18 | |
661 | /* Context State Error - illegal context state transition requested */ | |
662 | #define COMP_CTX_STATE 19 | |
663 | /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */ | |
664 | #define COMP_PING_ERR 20 | |
665 | /* Event Ring is full */ | |
666 | #define COMP_ER_FULL 21 | |
667 | /* Missed Service Error - HC couldn't service an isoc ep within interval */ | |
668 | #define COMP_MISSED_INT 23 | |
669 | /* Successfully stopped command ring */ | |
670 | #define COMP_CMD_STOP 24 | |
671 | /* Successfully aborted current command and stopped command ring */ | |
672 | #define COMP_CMD_ABORT 25 | |
673 | /* Stopped - transfer was terminated by a stop endpoint command */ | |
674 | #define COMP_STOP 26 | |
675 | /* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */ | |
676 | #define COMP_STOP_INVAL 27 | |
677 | /* Control Abort Error - Debug Capability - control pipe aborted */ | |
678 | #define COMP_DBG_ABORT 28 | |
679 | /* TRB type 29 and 30 reserved */ | |
680 | /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */ | |
681 | #define COMP_BUFF_OVER 31 | |
682 | /* Event Lost Error - xHC has an "internal event overrun condition" */ | |
683 | #define COMP_ISSUES 32 | |
684 | /* Undefined Error - reported when other error codes don't apply */ | |
685 | #define COMP_UNKNOWN 33 | |
686 | /* Invalid Stream ID Error */ | |
687 | #define COMP_STRID_ERR 34 | |
688 | /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */ | |
689 | /* FIXME - check for this */ | |
690 | #define COMP_2ND_BW_ERR 35 | |
691 | /* Split Transaction Error */ | |
692 | #define COMP_SPLIT_ERR 36 | |
693 | ||
694 | struct xhci_link_trb { | |
695 | /* 64-bit segment pointer*/ | |
696 | u32 segment_ptr[2]; | |
697 | u32 intr_target; | |
698 | u32 control; | |
699 | } __attribute__ ((packed)); | |
700 | ||
701 | /* control bitfields */ | |
702 | #define LINK_TOGGLE (0x1<<1) | |
703 | ||
7f84eef0 SS |
704 | /* Command completion event TRB */ |
705 | struct xhci_event_cmd { | |
706 | /* Pointer to command TRB, or the value passed by the event data trb */ | |
707 | u32 cmd_trb[2]; | |
708 | u32 status; | |
709 | u32 flags; | |
710 | } __attribute__ ((packed)); | |
0ebbab37 | 711 | |
0ebbab37 SS |
712 | |
713 | /* Normal TRB fields */ | |
714 | /* transfer_len bitmasks - bits 0:16 */ | |
715 | #define TRB_LEN(p) ((p) & 0x1ffff) | |
716 | /* TD size - number of bytes remaining in the TD (including this TRB): | |
717 | * bits 17 - 21. Shift the number of bytes by 10. */ | |
718 | #define TD_REMAINDER(p) ((((p) >> 10) & 0x1f) << 17) | |
719 | /* Interrupter Target - which MSI-X vector to target the completion event at */ | |
720 | #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) | |
721 | #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) | |
722 | ||
723 | /* Cycle bit - indicates TRB ownership by HC or HCD */ | |
724 | #define TRB_CYCLE (1<<0) | |
725 | /* | |
726 | * Force next event data TRB to be evaluated before task switch. | |
727 | * Used to pass OS data back after a TD completes. | |
728 | */ | |
729 | #define TRB_ENT (1<<1) | |
730 | /* Interrupt on short packet */ | |
731 | #define TRB_ISP (1<<2) | |
732 | /* Set PCIe no snoop attribute */ | |
733 | #define TRB_NO_SNOOP (1<<3) | |
734 | /* Chain multiple TRBs into a TD */ | |
735 | #define TRB_CHAIN (1<<4) | |
736 | /* Interrupt on completion */ | |
737 | #define TRB_IOC (1<<5) | |
738 | /* The buffer pointer contains immediate data */ | |
739 | #define TRB_IDT (1<<6) | |
740 | ||
741 | ||
742 | /* Control transfer TRB specific fields */ | |
743 | #define TRB_DIR_IN (1<<16) | |
744 | ||
7f84eef0 SS |
745 | struct xhci_generic_trb { |
746 | u32 field[4]; | |
747 | } __attribute__ ((packed)); | |
748 | ||
749 | union xhci_trb { | |
750 | struct xhci_link_trb link; | |
751 | struct xhci_transfer_event trans_event; | |
752 | struct xhci_event_cmd event_cmd; | |
753 | struct xhci_generic_trb generic; | |
754 | }; | |
755 | ||
0ebbab37 SS |
756 | /* TRB bit mask */ |
757 | #define TRB_TYPE_BITMASK (0xfc00) | |
758 | #define TRB_TYPE(p) ((p) << 10) | |
759 | /* TRB type IDs */ | |
760 | /* bulk, interrupt, isoc scatter/gather, and control data stage */ | |
761 | #define TRB_NORMAL 1 | |
762 | /* setup stage for control transfers */ | |
763 | #define TRB_SETUP 2 | |
764 | /* data stage for control transfers */ | |
765 | #define TRB_DATA 3 | |
766 | /* status stage for control transfers */ | |
767 | #define TRB_STATUS 4 | |
768 | /* isoc transfers */ | |
769 | #define TRB_ISOC 5 | |
770 | /* TRB for linking ring segments */ | |
771 | #define TRB_LINK 6 | |
772 | #define TRB_EVENT_DATA 7 | |
773 | /* Transfer Ring No-op (not for the command ring) */ | |
774 | #define TRB_TR_NOOP 8 | |
775 | /* Command TRBs */ | |
776 | /* Enable Slot Command */ | |
777 | #define TRB_ENABLE_SLOT 9 | |
778 | /* Disable Slot Command */ | |
779 | #define TRB_DISABLE_SLOT 10 | |
780 | /* Address Device Command */ | |
781 | #define TRB_ADDR_DEV 11 | |
782 | /* Configure Endpoint Command */ | |
783 | #define TRB_CONFIG_EP 12 | |
784 | /* Evaluate Context Command */ | |
785 | #define TRB_EVAL_CONTEXT 13 | |
786 | /* Reset Transfer Ring Command */ | |
787 | #define TRB_RESET_RING 14 | |
788 | /* Stop Transfer Ring Command */ | |
789 | #define TRB_STOP_RING 15 | |
790 | /* Set Transfer Ring Dequeue Pointer Command */ | |
791 | #define TRB_SET_DEQ 16 | |
792 | /* Reset Device Command */ | |
793 | #define TRB_RESET_DEV 17 | |
794 | /* Force Event Command (opt) */ | |
795 | #define TRB_FORCE_EVENT 18 | |
796 | /* Negotiate Bandwidth Command (opt) */ | |
797 | #define TRB_NEG_BANDWIDTH 19 | |
798 | /* Set Latency Tolerance Value Command (opt) */ | |
799 | #define TRB_SET_LT 20 | |
800 | /* Get port bandwidth Command */ | |
801 | #define TRB_GET_BW 21 | |
802 | /* Force Header Command - generate a transaction or link management packet */ | |
803 | #define TRB_FORCE_HEADER 22 | |
804 | /* No-op Command - not for transfer rings */ | |
805 | #define TRB_CMD_NOOP 23 | |
806 | /* TRB IDs 24-31 reserved */ | |
807 | /* Event TRBS */ | |
808 | /* Transfer Event */ | |
809 | #define TRB_TRANSFER 32 | |
810 | /* Command Completion Event */ | |
811 | #define TRB_COMPLETION 33 | |
812 | /* Port Status Change Event */ | |
813 | #define TRB_PORT_STATUS 34 | |
814 | /* Bandwidth Request Event (opt) */ | |
815 | #define TRB_BANDWIDTH_EVENT 35 | |
816 | /* Doorbell Event (opt) */ | |
817 | #define TRB_DOORBELL 36 | |
818 | /* Host Controller Event */ | |
819 | #define TRB_HC_EVENT 37 | |
820 | /* Device Notification Event - device sent function wake notification */ | |
821 | #define TRB_DEV_NOTE 38 | |
822 | /* MFINDEX Wrap Event - microframe counter wrapped */ | |
823 | #define TRB_MFINDEX_WRAP 39 | |
824 | /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ | |
825 | ||
826 | /* | |
827 | * TRBS_PER_SEGMENT must be a multiple of 4, | |
828 | * since the command ring is 64-byte aligned. | |
829 | * It must also be greater than 16. | |
830 | */ | |
831 | #define TRBS_PER_SEGMENT 64 | |
832 | #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16) | |
833 | ||
834 | struct xhci_segment { | |
835 | union xhci_trb *trbs; | |
836 | /* private to HCD */ | |
837 | struct xhci_segment *next; | |
838 | dma_addr_t dma; | |
839 | } __attribute__ ((packed)); | |
840 | ||
841 | struct xhci_ring { | |
842 | struct xhci_segment *first_seg; | |
843 | union xhci_trb *enqueue; | |
7f84eef0 SS |
844 | struct xhci_segment *enq_seg; |
845 | unsigned int enq_updates; | |
0ebbab37 | 846 | union xhci_trb *dequeue; |
7f84eef0 SS |
847 | struct xhci_segment *deq_seg; |
848 | unsigned int deq_updates; | |
0ebbab37 SS |
849 | /* |
850 | * Write the cycle state into the TRB cycle field to give ownership of | |
851 | * the TRB to the host controller (if we are the producer), or to check | |
852 | * if we own the TRB (if we are the consumer). See section 4.9.1. | |
853 | */ | |
854 | u32 cycle_state; | |
855 | }; | |
856 | ||
857 | struct xhci_erst_entry { | |
858 | /* 64-bit event ring segment address */ | |
859 | u32 seg_addr[2]; | |
860 | u32 seg_size; | |
861 | /* Set to zero */ | |
862 | u32 rsvd; | |
863 | } __attribute__ ((packed)); | |
864 | ||
865 | struct xhci_erst { | |
866 | struct xhci_erst_entry *entries; | |
867 | unsigned int num_entries; | |
868 | /* xhci->event_ring keeps track of segment dma addresses */ | |
869 | dma_addr_t erst_dma_addr; | |
870 | /* Num entries the ERST can contain */ | |
871 | unsigned int erst_size; | |
872 | }; | |
873 | ||
874 | /* | |
875 | * Each segment table entry is 4*32bits long. 1K seems like an ok size: | |
876 | * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, | |
877 | * meaning 64 ring segments. | |
878 | * Initial allocated size of the ERST, in number of entries */ | |
879 | #define ERST_NUM_SEGS 1 | |
880 | /* Initial allocated size of the ERST, in number of entries */ | |
881 | #define ERST_SIZE 64 | |
882 | /* Initial number of event segment rings allocated */ | |
883 | #define ERST_ENTRIES 1 | |
7f84eef0 SS |
884 | /* Poll every 60 seconds */ |
885 | #define POLL_TIMEOUT 60 | |
0ebbab37 SS |
886 | /* XXX: Make these module parameters */ |
887 | ||
74c68741 SS |
888 | |
889 | /* There is one ehci_hci structure per controller */ | |
890 | struct xhci_hcd { | |
891 | /* glue to PCI and HCD framework */ | |
892 | struct xhci_cap_regs __iomem *cap_regs; | |
893 | struct xhci_op_regs __iomem *op_regs; | |
894 | struct xhci_run_regs __iomem *run_regs; | |
0ebbab37 | 895 | struct xhci_doorbell_array __iomem *dba; |
66d4eadd SS |
896 | /* Our HCD's current interrupter register set */ |
897 | struct intr_reg __iomem *ir_set; | |
74c68741 SS |
898 | |
899 | /* Cached register copies of read-only HC data */ | |
900 | __u32 hcs_params1; | |
901 | __u32 hcs_params2; | |
902 | __u32 hcs_params3; | |
903 | __u32 hcc_params; | |
904 | ||
905 | spinlock_t lock; | |
906 | ||
907 | /* packed release number */ | |
908 | u8 sbrn; | |
909 | u16 hci_version; | |
910 | u8 max_slots; | |
911 | u8 max_interrupters; | |
912 | u8 max_ports; | |
913 | u8 isoc_threshold; | |
914 | int event_ring_max; | |
915 | int addr_64; | |
66d4eadd | 916 | /* 4KB min, 128MB max */ |
74c68741 | 917 | int page_size; |
66d4eadd SS |
918 | /* Valid values are 12 to 20, inclusive */ |
919 | int page_shift; | |
920 | /* only one MSI vector for now, but might need more later */ | |
921 | int msix_count; | |
922 | struct msix_entry *msix_entries; | |
0ebbab37 | 923 | /* data structures */ |
a74588f9 | 924 | struct xhci_device_context_array *dcbaa; |
0ebbab37 SS |
925 | struct xhci_ring *cmd_ring; |
926 | struct xhci_ring *event_ring; | |
927 | struct xhci_erst erst; | |
928 | ||
929 | /* DMA pools */ | |
930 | struct dma_pool *device_pool; | |
931 | struct dma_pool *segment_pool; | |
7f84eef0 SS |
932 | |
933 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING | |
934 | /* Poll the rings - for debugging */ | |
935 | struct timer_list event_ring_timer; | |
936 | int zombie; | |
937 | #endif | |
938 | /* Statistics */ | |
939 | int noops_submitted; | |
940 | int noops_handled; | |
941 | int error_bitmask; | |
74c68741 SS |
942 | }; |
943 | ||
7f84eef0 SS |
944 | /* For testing purposes */ |
945 | #define NUM_TEST_NOOPS 0 | |
946 | ||
74c68741 SS |
947 | /* convert between an HCD pointer and the corresponding EHCI_HCD */ |
948 | static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) | |
949 | { | |
950 | return (struct xhci_hcd *) (hcd->hcd_priv); | |
951 | } | |
952 | ||
953 | static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) | |
954 | { | |
955 | return container_of((void *) xhci, struct usb_hcd, hcd_priv); | |
956 | } | |
957 | ||
958 | #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING | |
959 | #define XHCI_DEBUG 1 | |
960 | #else | |
961 | #define XHCI_DEBUG 0 | |
962 | #endif | |
963 | ||
964 | #define xhci_dbg(xhci, fmt, args...) \ | |
965 | do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) | |
966 | #define xhci_info(xhci, fmt, args...) \ | |
967 | do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0) | |
968 | #define xhci_err(xhci, fmt, args...) \ | |
969 | dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) | |
970 | #define xhci_warn(xhci, fmt, args...) \ | |
971 | dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) | |
972 | ||
973 | /* TODO: copied from ehci.h - can be refactored? */ | |
974 | /* xHCI spec says all registers are little endian */ | |
975 | static inline unsigned int xhci_readl(const struct xhci_hcd *xhci, | |
976 | __u32 __iomem *regs) | |
977 | { | |
978 | return readl(regs); | |
979 | } | |
980 | static inline void xhci_writel(const struct xhci_hcd *xhci, | |
981 | const unsigned int val, __u32 __iomem *regs) | |
982 | { | |
983 | if (!in_interrupt()) | |
984 | xhci_dbg(xhci, "`MEM_WRITE_DWORD(3'b000, 32'h%0x, 32'h%0x, 4'hf);\n", | |
985 | (unsigned int) regs, val); | |
986 | writel(val, regs); | |
987 | } | |
988 | ||
66d4eadd SS |
989 | /* xHCI debugging */ |
990 | void xhci_print_ir_set(struct xhci_hcd *xhci, struct intr_reg *ir_set, int set_num); | |
991 | void xhci_print_registers(struct xhci_hcd *xhci); | |
0ebbab37 SS |
992 | void xhci_dbg_regs(struct xhci_hcd *xhci); |
993 | void xhci_print_run_regs(struct xhci_hcd *xhci); | |
7f84eef0 | 994 | void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg); |
0ebbab37 SS |
995 | void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring); |
996 | void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); | |
997 | void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci); | |
7f84eef0 | 998 | void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring); |
66d4eadd SS |
999 | |
1000 | /* xHCI memory managment */ | |
1001 | void xhci_mem_cleanup(struct xhci_hcd *xhci); | |
1002 | int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); | |
1003 | ||
1004 | #ifdef CONFIG_PCI | |
1005 | /* xHCI PCI glue */ | |
1006 | int xhci_register_pci(void); | |
1007 | void xhci_unregister_pci(void); | |
1008 | #endif | |
1009 | ||
1010 | /* xHCI host controller glue */ | |
1011 | int xhci_halt(struct xhci_hcd *xhci); | |
1012 | int xhci_reset(struct xhci_hcd *xhci); | |
1013 | int xhci_init(struct usb_hcd *hcd); | |
1014 | int xhci_run(struct usb_hcd *hcd); | |
1015 | void xhci_stop(struct usb_hcd *hcd); | |
1016 | void xhci_shutdown(struct usb_hcd *hcd); | |
1017 | int xhci_get_frame(struct usb_hcd *hcd); | |
7f84eef0 SS |
1018 | irqreturn_t xhci_irq(struct usb_hcd *hcd); |
1019 | ||
1020 | /* xHCI ring, segment, TRB, and TD functions */ | |
1021 | dma_addr_t trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); | |
1022 | void ring_cmd_db(struct xhci_hcd *xhci); | |
1023 | void *setup_one_noop(struct xhci_hcd *xhci); | |
1024 | void handle_event(struct xhci_hcd *xhci); | |
1025 | void set_hc_event_deq(struct xhci_hcd *xhci); | |
66d4eadd | 1026 | |
74c68741 | 1027 | #endif /* __LINUX_XHCI_HCD_H */ |