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USB: add SPDX identifiers to all remaining files in drivers/usb/
[mirror_ubuntu-jammy-kernel.git] / drivers / usb / mtu3 / mtu3_core.c
CommitLineData
5fd54ace 1// SPDX-License-Identifier: GPL-2.0
df2069ac
CY		 2/*
3 * mtu3_core.c - hardware access layer and gadget init/exit of
4 * MediaTek usb3 Dual-Role Controller Driver
5 *
6 * Copyright (C) 2016 MediaTek Inc.
7 *
8 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
1a46dfea 21#include <linux/dma-mapping.h>
df2069ac
CY		 22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
26#include <linux/platform_device.h>
27
28#include "mtu3.h"
29
30static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
31{
32 struct mtu3_fifo_info *fifo = mep->fifo;
33 u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
34 u32 start_bit;
35
36 /* ensure that @mep->fifo_seg_size is power of two */
37 num_bits = roundup_pow_of_two(num_bits);
38 if (num_bits > fifo->limit)
39 return -EINVAL;
40
41 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
42 num_bits = num_bits * (mep->slot + 1);
43 start_bit = bitmap_find_next_zero_area(fifo->bitmap,
44 fifo->limit, 0, num_bits, 0);
45 if (start_bit >= fifo->limit)
46 return -EOVERFLOW;
47
48 bitmap_set(fifo->bitmap, start_bit, num_bits);
49 mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
50 mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
51
52 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
53 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
54
55 return mep->fifo_addr;
56}
57
58static void ep_fifo_free(struct mtu3_ep *mep)
59{
60 struct mtu3_fifo_info *fifo = mep->fifo;
61 u32 addr = mep->fifo_addr;
62 u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
63 u32 start_bit;
64
65 if (unlikely(addr < fifo->base || bits > fifo->limit))
66 return;
67
68 start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
69 bitmap_clear(fifo->bitmap, start_bit, bits);
70 mep->fifo_size = 0;
71 mep->fifo_seg_size = 0;
72
73 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
74 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
75}
76
a29de31b
CY		 77/* enable/disable U3D SS function */
78static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
79{
80 /* If usb3_en==0, LTSSM will go to SS.Disable state */
81 if (enable)
82 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
83 else
84 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
85
86 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
87}
88
df2069ac 89/* set/clear U3D HS device soft connect */
a29de31b 90static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
df2069ac
CY		 91{
92 if (enable) {
93 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
94 SOFT_CONN | SUSPENDM_ENABLE);
95 } else {
96 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
97 SOFT_CONN | SUSPENDM_ENABLE);
98 }
99 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
100}
101
102/* only port0 of U2/U3 supports device mode */
103static int mtu3_device_enable(struct mtu3 *mtu)
104{
105 void __iomem *ibase = mtu->ippc_base;
106 u32 check_clk = 0;
107
108 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
a29de31b
CY		 109
110 if (mtu->is_u3_ip) {
111 check_clk = SSUSB_U3_MAC_RST_B_STS;
112 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
113 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
114 SSUSB_U3_PORT_HOST_SEL));
115 }
df2069ac
CY		 116 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
117 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
118 SSUSB_U2_PORT_HOST_SEL));
4da72e6d
CY		 119
120 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
121 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
df2069ac 122
b3f4e727 123 return ssusb_check_clocks(mtu->ssusb, check_clk);
df2069ac
CY		 124}
125
126static void mtu3_device_disable(struct mtu3 *mtu)
127{
128 void __iomem *ibase = mtu->ippc_base;
129
a29de31b
CY		 130 if (mtu->is_u3_ip)
131 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
132 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
133
df2069ac
CY		 134 mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
135 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
4da72e6d
CY		 136
137 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
138 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
139
df2069ac
CY		 140 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
141}
142
143/* reset U3D's device module. */
144static void mtu3_device_reset(struct mtu3 *mtu)
145{
146 void __iomem *ibase = mtu->ippc_base;
147
148 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
149 udelay(1);
150 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
151}
152
153/* disable all interrupts */
154static void mtu3_intr_disable(struct mtu3 *mtu)
155{
156 void __iomem *mbase = mtu->mac_base;
157
158 /* Disable level 1 interrupts */
159 mtu3_writel(mbase, U3D_LV1IECR, ~0x0);
df2069ac
CY		 160 /* Disable endpoint interrupts */
161 mtu3_writel(mbase, U3D_EPIECR, ~0x0);
162}
163
164static void mtu3_intr_status_clear(struct mtu3 *mtu)
165{
166 void __iomem *mbase = mtu->mac_base;
167
168 /* Clear EP0 and Tx/Rx EPn interrupts status */
169 mtu3_writel(mbase, U3D_EPISR, ~0x0);
df2069ac
CY		 170 /* Clear U2 USB common interrupts status */
171 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
a29de31b
CY		 172 /* Clear U3 LTSSM interrupts status */
173 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
df2069ac
CY		 174 /* Clear speed change interrupt status */
175 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
176}
177
178/* enable system global interrupt */
179static void mtu3_intr_enable(struct mtu3 *mtu)
180{
181 void __iomem *mbase = mtu->mac_base;
182 u32 value;
183
184 /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
a29de31b 185 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
df2069ac
CY		 186 mtu3_writel(mbase, U3D_LV1IESR, value);
187
188 /* Enable U2 common USB interrupts */
189 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
190 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
191
a29de31b
CY		 192 if (mtu->is_u3_ip) {
193 /* Enable U3 LTSSM interrupts */
194 value = HOT_RST_INTR | WARM_RST_INTR | VBUS_RISE_INTR |
195 VBUS_FALL_INTR | ENTER_U3_INTR | EXIT_U3_INTR;
196 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
197 }
198
df2069ac
CY		 199 /* Enable QMU interrupts. */
200 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
201 RXQ_LENERR_INT | RXQ_ZLPERR_INT;
202 mtu3_writel(mbase, U3D_QIESR1, value);
203
204 /* Enable speed change interrupt */
205 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
206}
207
208/* set/clear the stall and toggle bits for non-ep0 */
209void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
210{
211 struct mtu3 *mtu = mep->mtu;
212 void __iomem *mbase = mtu->mac_base;
213 u8 epnum = mep->epnum;
214 u32 csr;
215
216 if (mep->is_in) { /* TX */
217 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
218 if (set)
219 csr |= TX_SENDSTALL;
220 else
221 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
222 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
223 } else { /* RX */
224 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
225 if (set)
226 csr |= RX_SENDSTALL;
227 else
228 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
229 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
230 }
231
232 if (!set) {
233 mtu3_setbits(mbase, U3D_EP_RST, EP_RST(mep->is_in, epnum));
234 mtu3_clrbits(mbase, U3D_EP_RST, EP_RST(mep->is_in, epnum));
235 mep->flags &= ~MTU3_EP_STALL;
236 } else {
237 mep->flags |= MTU3_EP_STALL;
238 }
239
240 dev_dbg(mtu->dev, "%s: %s\n", mep->name,
241 set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
242}
243
a29de31b
CY		 244void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
245{
4d79e042 246 if (mtu->is_u3_ip && mtu->max_speed >= USB_SPEED_SUPER)
a29de31b
CY		 247 mtu3_ss_func_set(mtu, is_on);
248 else
249 mtu3_hs_softconn_set(mtu, is_on);
250
251 dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
252 usb_speed_string(mtu->max_speed), is_on ? "+" : "-");
253}
254
df2069ac
CY		 255void mtu3_start(struct mtu3 *mtu)
256{
257 void __iomem *mbase = mtu->mac_base;
258
259 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
260 mtu3_readl(mbase, U3D_DEVICE_CONTROL));
261
262 mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
263
a29de31b
CY		 264 /*
265 * When disable U2 port, USB2_CSR's register will be reset to
266 * default value after re-enable it again(HS is enabled by default).
267 * So if force mac to work as FS, disable HS function.
268 */
269 if (mtu->max_speed == USB_SPEED_FULL)
270 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
271
df2069ac
CY		 272 /* Initialize the default interrupts */
273 mtu3_intr_enable(mtu);
df2069ac
CY		 274 mtu->is_active = 1;
275
276 if (mtu->softconnect)
a29de31b 277 mtu3_dev_on_off(mtu, 1);
df2069ac
CY		 278}
279
280void mtu3_stop(struct mtu3 *mtu)
281{
282 dev_dbg(mtu->dev, "%s\n", __func__);
283
284 mtu3_intr_disable(mtu);
285 mtu3_intr_status_clear(mtu);
286
287 if (mtu->softconnect)
a29de31b 288 mtu3_dev_on_off(mtu, 0);
df2069ac
CY		 289
290 mtu->is_active = 0;
291 mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
292}
293
294/* for non-ep0 */
295int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
296 int interval, int burst, int mult)
297{
298 void __iomem *mbase = mtu->mac_base;
299 int epnum = mep->epnum;
300 u32 csr0, csr1, csr2;
301 int fifo_sgsz, fifo_addr;
302 int num_pkts;
303
304 fifo_addr = ep_fifo_alloc(mep, mep->maxp);
305 if (fifo_addr < 0) {
306 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
307 return -ENOMEM;
308 }
309 fifo_sgsz = ilog2(mep->fifo_seg_size);
310 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
311 mep->fifo_seg_size, mep->fifo_size);
312
313 if (mep->is_in) {
314 csr0 = TX_TXMAXPKTSZ(mep->maxp);
315 csr0 |= TX_DMAREQEN;
316
317 num_pkts = (burst + 1) * (mult + 1) - 1;
318 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
319 csr1 |= TX_MAX_PKT(num_pkts) | TX_MULT(mult);
320
321 csr2 = TX_FIFOADDR(fifo_addr >> 4);
322 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
323
324 switch (mep->type) {
325 case USB_ENDPOINT_XFER_BULK:
326 csr1 |= TX_TYPE(TYPE_BULK);
327 break;
328 case USB_ENDPOINT_XFER_ISOC:
329 csr1 |= TX_TYPE(TYPE_ISO);
330 csr2 |= TX_BINTERVAL(interval);
331 break;
332 case USB_ENDPOINT_XFER_INT:
333 csr1 |= TX_TYPE(TYPE_INT);
334 csr2 |= TX_BINTERVAL(interval);
335 break;
336 }
337
338 /* Enable QMU Done interrupt */
339 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
340
341 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
342 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
343 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
344
345 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
346 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
347 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
348 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
349 } else {
350 csr0 = RX_RXMAXPKTSZ(mep->maxp);
351 csr0 |= RX_DMAREQEN;
352
353 num_pkts = (burst + 1) * (mult + 1) - 1;
354 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
355 csr1 |= RX_MAX_PKT(num_pkts) | RX_MULT(mult);
356
357 csr2 = RX_FIFOADDR(fifo_addr >> 4);
358 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
359
360 switch (mep->type) {
361 case USB_ENDPOINT_XFER_BULK:
362 csr1 |= RX_TYPE(TYPE_BULK);
363 break;
364 case USB_ENDPOINT_XFER_ISOC:
365 csr1 |= RX_TYPE(TYPE_ISO);
366 csr2 |= RX_BINTERVAL(interval);
367 break;
368 case USB_ENDPOINT_XFER_INT:
369 csr1 |= RX_TYPE(TYPE_INT);
370 csr2 |= RX_BINTERVAL(interval);
371 break;
372 }
373
374 /*Enable QMU Done interrupt */
375 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
376
377 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
378 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
379 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
380
381 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
382 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
383 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
384 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
385 }
386
387 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
388 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
389 __func__, mep->name, mep->fifo_addr, mep->fifo_size,
390 fifo_sgsz, mep->fifo_seg_size);
391
392 return 0;
393}
394
395/* for non-ep0 */
396void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
397{
398 void __iomem *mbase = mtu->mac_base;
399 int epnum = mep->epnum;
400
401 if (mep->is_in) {
402 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
403 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
404 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
405 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
406 } else {
407 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
408 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
409 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
410 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
411 }
412
413 ep_fifo_free(mep);
414
415 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
416}
417
418/*
a29de31b
CY		 419 * Two scenarios:
420 * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
421 * are separated;
422 * 2. when supports only HS, the fifo is shared for all EPs, and
df2069ac
CY		 423 * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
424 * the total fifo size of non-ep0, and ep0's is fixed to 64B,
425 * so the total fifo size is 64B + @EPNTXFFSZ;
426 * Due to the first 64B should be reserved for EP0, non-ep0's fifo
427 * starts from offset 64 and are divided into two equal parts for
428 * TX or RX EPs for simplification.
429 */
430static void get_ep_fifo_config(struct mtu3 *mtu)
431{
432 struct mtu3_fifo_info *tx_fifo;
433 struct mtu3_fifo_info *rx_fifo;
434 u32 fifosize;
435
a29de31b
CY		 436 if (mtu->is_u3_ip) {
437 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
438 tx_fifo = &mtu->tx_fifo;
439 tx_fifo->base = 0;
440 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
441 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
442
443 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
444 rx_fifo = &mtu->rx_fifo;
445 rx_fifo->base = 0;
446 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
447 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
448 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
449 } else {
450 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
451 tx_fifo = &mtu->tx_fifo;
452 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
453 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
454 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
455
456 rx_fifo = &mtu->rx_fifo;
457 rx_fifo->base =
458 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
459 rx_fifo->limit = tx_fifo->limit;
460 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
461 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
462 }
df2069ac
CY		 463
464 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
465 __func__, tx_fifo->base, tx_fifo->limit,
466 rx_fifo->base, rx_fifo->limit);
467}
468
469void mtu3_ep0_setup(struct mtu3 *mtu)
470{
471 u32 maxpacket = mtu->g.ep0->maxpacket;
472 u32 csr;
473
474 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
475
476 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
477 csr &= ~EP0_MAXPKTSZ_MSK;
478 csr |= EP0_MAXPKTSZ(maxpacket);
479 csr &= EP0_W1C_BITS;
480 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
481
482 /* Enable EP0 interrupt */
483 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR);
484}
485
486static int mtu3_mem_alloc(struct mtu3 *mtu)
487{
488 void __iomem *mbase = mtu->mac_base;
489 struct mtu3_ep *ep_array;
490 int in_ep_num, out_ep_num;
220d88ea 491 u32 cap_epinfo;
df2069ac
CY		 492 int ret;
493 int i;
494
df2069ac
CY		 495 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
496 in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
497 out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
498
df2069ac
CY		 499 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
500 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
501 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
502
503 /* one for ep0, another is reserved */
504 mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
505 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
506 if (ep_array == NULL)
507 return -ENOMEM;
508
509 mtu->ep_array = ep_array;
510 mtu->in_eps = ep_array;
511 mtu->out_eps = &ep_array[mtu->num_eps];
512 /* ep0 uses in_eps[0], out_eps[0] is reserved */
513 mtu->ep0 = mtu->in_eps;
df2069ac
CY		 514 mtu->ep0->mtu = mtu;
515 mtu->ep0->epnum = 0;
516
517 for (i = 1; i < mtu->num_eps; i++) {
518 struct mtu3_ep *mep = mtu->in_eps + i;
519
520 mep->fifo = &mtu->tx_fifo;
521 mep = mtu->out_eps + i;
522 mep->fifo = &mtu->rx_fifo;
523 }
524
525 get_ep_fifo_config(mtu);
526
527 ret = mtu3_qmu_init(mtu);
528 if (ret)
529 kfree(mtu->ep_array);
530
531 return ret;
532}
533
534static void mtu3_mem_free(struct mtu3 *mtu)
535{
536 mtu3_qmu_exit(mtu);
537 kfree(mtu->ep_array);
538}
539
a29de31b
CY		 540static void mtu3_set_speed(struct mtu3 *mtu)
541{
542 void __iomem *mbase = mtu->mac_base;
543
544 if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
545 mtu->max_speed = USB_SPEED_HIGH;
546
547 if (mtu->max_speed == USB_SPEED_FULL) {
548 /* disable U3 SS function */
549 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
550 /* disable HS function */
551 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
552 } else if (mtu->max_speed == USB_SPEED_HIGH) {
553 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
554 /* HS/FS detected by HW */
555 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
4d79e042
CY		 556 } else if (mtu->max_speed == USB_SPEED_SUPER) {
557 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
558 SSUSB_U3_PORT_SSP_SPEED);
a29de31b 559 }
d0ed062a 560
a29de31b
CY		 561 dev_info(mtu->dev, "max_speed: %s\n",
562 usb_speed_string(mtu->max_speed));
563}
564
df2069ac
CY		 565static void mtu3_regs_init(struct mtu3 *mtu)
566{
567
568 void __iomem *mbase = mtu->mac_base;
569
570 /* be sure interrupts are disabled before registration of ISR */
571 mtu3_intr_disable(mtu);
572 mtu3_intr_status_clear(mtu);
573
a29de31b
CY		 574 if (mtu->is_u3_ip) {
575 /* disable LGO_U1/U2 by default */
576 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
577 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE |
578 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
579 /* device responses to u3_exit from host automatically */
580 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
c7d4abbc
CY		 581 /* automatically build U2 link when U3 detect fail */
582 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
a29de31b
CY		 583 }
584
585 mtu3_set_speed(mtu);
df2069ac
CY		 586
587 /* delay about 0.1us from detecting reset to send chirp-K */
588 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
df2069ac
CY		 589 /* U2/U3 detected by HW */
590 mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
df2069ac
CY		 591 /* enable QMU 16B checksum */
592 mtu3_setbits(mbase, U3D_QCR0, QMU_CS16B_EN);
df2069ac
CY		 593 /* vbus detected by HW */
594 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
595}
596
597static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
598{
599 void __iomem *mbase = mtu->mac_base;
600 enum usb_device_speed udev_speed;
601 u32 maxpkt = 64;
602 u32 link;
603 u32 speed;
604
605 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
606 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
607 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
608 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
609
610 if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
611 return IRQ_NONE;
612
613 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
614
615 switch (speed) {
616 case MTU3_SPEED_FULL:
617 udev_speed = USB_SPEED_FULL;
618 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
619 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
620 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
621 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
622 LPM_BESL_STALL | LPM_BESLD_STALL);
623 break;
624 case MTU3_SPEED_HIGH:
625 udev_speed = USB_SPEED_HIGH;
626 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
627 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
628 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
629 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
630 LPM_BESL_STALL | LPM_BESLD_STALL);
631 break;
a29de31b
CY		 632 case MTU3_SPEED_SUPER:
633 udev_speed = USB_SPEED_SUPER;
634 maxpkt = 512;
635 break;
4d79e042
CY		 636 case MTU3_SPEED_SUPER_PLUS:
637 udev_speed = USB_SPEED_SUPER_PLUS;
638 maxpkt = 512;
639 break;
df2069ac
CY		 640 default:
641 udev_speed = USB_SPEED_UNKNOWN;
642 break;
643 }
644 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
645
646 mtu->g.speed = udev_speed;
647 mtu->g.ep0->maxpacket = maxpkt;
648 mtu->ep0_state = MU3D_EP0_STATE_SETUP;
649
650 if (udev_speed == USB_SPEED_UNKNOWN)
651 mtu3_gadget_disconnect(mtu);
652 else
653 mtu3_ep0_setup(mtu);
654
655 return IRQ_HANDLED;
656}
657
a29de31b
CY		 658static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
659{
660 void __iomem *mbase = mtu->mac_base;
661 u32 ltssm;
662
663 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
664 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
665 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
666 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
667
668 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
669 mtu3_gadget_reset(mtu);
670
671 if (ltssm & VBUS_FALL_INTR)
672 mtu3_ss_func_set(mtu, false);
673
674 if (ltssm & VBUS_RISE_INTR)
675 mtu3_ss_func_set(mtu, true);
676
677 if (ltssm & EXIT_U3_INTR)
678 mtu3_gadget_resume(mtu);
679
680 if (ltssm & ENTER_U3_INTR)
681 mtu3_gadget_suspend(mtu);
682
683 return IRQ_HANDLED;
684}
685
df2069ac
CY		 686static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
687{
688 void __iomem *mbase = mtu->mac_base;
689 u32 u2comm;
690
691 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
692 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
693 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
694 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
695
696 if (u2comm & SUSPEND_INTR)
697 mtu3_gadget_suspend(mtu);
698
699 if (u2comm & RESUME_INTR)
700 mtu3_gadget_resume(mtu);
701
702 if (u2comm & RESET_INTR)
703 mtu3_gadget_reset(mtu);
704
705 return IRQ_HANDLED;
706}
707
a8bac371 708static irqreturn_t mtu3_irq(int irq, void *data)
df2069ac
CY		 709{
710 struct mtu3 *mtu = (struct mtu3 *)data;
711 unsigned long flags;
712 u32 level1;
713
714 spin_lock_irqsave(&mtu->lock, flags);
715
716 /* U3D_LV1ISR is RU */
717 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
718 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
719
720 if (level1 & EP_CTRL_INTR)
721 mtu3_link_isr(mtu);
722
723 if (level1 & MAC2_INTR)
724 mtu3_u2_common_isr(mtu);
725
a29de31b
CY		 726 if (level1 & MAC3_INTR)
727 mtu3_u3_ltssm_isr(mtu);
728
df2069ac
CY		 729 if (level1 & BMU_INTR)
730 mtu3_ep0_isr(mtu);
731
732 if (level1 & QMU_INTR)
733 mtu3_qmu_isr(mtu);
734
735 spin_unlock_irqrestore(&mtu->lock, flags);
736
737 return IRQ_HANDLED;
738}
739
740static int mtu3_hw_init(struct mtu3 *mtu)
741{
220d88ea 742 u32 cap_dev;
df2069ac
CY		 743 int ret;
744
220d88ea
CY		 745 mtu->hw_version = mtu3_readl(mtu->ippc_base, U3D_SSUSB_HW_ID);
746
747 cap_dev = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
748 mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(cap_dev);
749
750 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
751 mtu->is_u3_ip ? "U3" : "U2");
752
df2069ac
CY		 753 mtu3_device_reset(mtu);
754
755 ret = mtu3_device_enable(mtu);
756 if (ret) {
757 dev_err(mtu->dev, "device enable failed %d\n", ret);
758 return ret;
759 }
760
761 ret = mtu3_mem_alloc(mtu);
762 if (ret)
763 return -ENOMEM;
764
765 mtu3_regs_init(mtu);
766
767 return 0;
768}
769
770static void mtu3_hw_exit(struct mtu3 *mtu)
771{
772 mtu3_device_disable(mtu);
773 mtu3_mem_free(mtu);
774}
775
1a46dfea
CY		 776/**
777 * we set 32-bit DMA mask by default, here check whether the controller
778 * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
779 */
780static int mtu3_set_dma_mask(struct mtu3 *mtu)
781{
782 struct device *dev = mtu->dev;
783 bool is_36bit = false;
784 int ret = 0;
785 u32 value;
786
787 value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
788 if (value & DMA_ADDR_36BIT) {
789 is_36bit = true;
790 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
791 /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
792 if (ret) {
793 is_36bit = false;
794 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
795 }
796 }
797 dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
798
799 return ret;
800}
df2069ac 801
b3f4e727 802int ssusb_gadget_init(struct ssusb_mtk *ssusb)
df2069ac 803{
b3f4e727
CY		 804 struct device *dev = ssusb->dev;
805 struct platform_device *pdev = to_platform_device(dev);
806 struct mtu3 *mtu = NULL;
807 struct resource *res;
808 int ret = -ENOMEM;
809
810 mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
811 if (mtu == NULL)
812 return -ENOMEM;
813
814 mtu->irq = platform_get_irq(pdev, 0);
c162ff0a 815 if (mtu->irq < 0) {
b3f4e727 816 dev_err(dev, "fail to get irq number\n");
c162ff0a 817 return mtu->irq;
b3f4e727
CY		 818 }
819 dev_info(dev, "irq %d\n", mtu->irq);
df2069ac 820
b3f4e727
CY		 821 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
822 mtu->mac_base = devm_ioremap_resource(dev, res);
823 if (IS_ERR(mtu->mac_base)) {
824 dev_err(dev, "error mapping memory for dev mac\n");
825 return PTR_ERR(mtu->mac_base);
826 }
827
828 spin_lock_init(&mtu->lock);
829 mtu->dev = dev;
830 mtu->ippc_base = ssusb->ippc_base;
831 ssusb->mac_base = mtu->mac_base;
832 ssusb->u3d = mtu;
833 mtu->ssusb = ssusb;
a29de31b
CY		 834 mtu->max_speed = usb_get_maximum_speed(dev);
835
836 /* check the max_speed parameter */
837 switch (mtu->max_speed) {
838 case USB_SPEED_FULL:
839 case USB_SPEED_HIGH:
840 case USB_SPEED_SUPER:
4d79e042 841 case USB_SPEED_SUPER_PLUS:
a29de31b
CY		 842 break;
843 default:
844 dev_err(dev, "invalid max_speed: %s\n",
845 usb_speed_string(mtu->max_speed));
846 /* fall through */
847 case USB_SPEED_UNKNOWN:
4d79e042
CY		 848 /* default as SSP */
849 mtu->max_speed = USB_SPEED_SUPER_PLUS;
a29de31b
CY		 850 break;
851 }
852
853 dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
854 mtu->mac_base, mtu->ippc_base);
855
df2069ac
CY		 856 ret = mtu3_hw_init(mtu);
857 if (ret) {
858 dev_err(dev, "mtu3 hw init failed:%d\n", ret);
859 return ret;
860 }
861
1a46dfea
CY		 862 ret = mtu3_set_dma_mask(mtu);
863 if (ret) {
864 dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
865 goto dma_mask_err;
866 }
867
df2069ac
CY		 868 ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
869 if (ret) {
870 dev_err(dev, "request irq %d failed!\n", mtu->irq);
871 goto irq_err;
872 }
873
874 device_init_wakeup(dev, true);
875
876 ret = mtu3_gadget_setup(mtu);
877 if (ret) {
878 dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
879 goto gadget_err;
880 }
881
d0ed062a
CY		 882 /* init as host mode, power down device IP for power saving */
883 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
884 mtu3_stop(mtu);
885
df2069ac
CY		 886 dev_dbg(dev, " %s() done...\n", __func__);
887
888 return 0;
889
890gadget_err:
891 device_init_wakeup(dev, false);
892
1a46dfea 893dma_mask_err:
df2069ac
CY		 894irq_err:
895 mtu3_hw_exit(mtu);
b3f4e727 896 ssusb->u3d = NULL;
df2069ac
CY		 897 dev_err(dev, " %s() fail...\n", __func__);
898
899 return ret;
900}
901
b3f4e727 902void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
df2069ac 903{
b3f4e727
CY		 904 struct mtu3 *mtu = ssusb->u3d;
905
df2069ac 906 mtu3_gadget_cleanup(mtu);
b3f4e727 907 device_init_wakeup(ssusb->dev, false);
df2069ac
CY		 908 mtu3_hw_exit(mtu);
909}
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