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df2069ac CY |
1 | /* |
2 | * mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions | |
3 | * | |
4 | * Copyright (C) 2016 MediaTek Inc. | |
5 | * | |
6 | * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | */ | |
18 | ||
19 | #ifndef _SSUSB_HW_REGS_H_ | |
20 | #define _SSUSB_HW_REGS_H_ | |
21 | ||
22 | /* segment offset of MAC register */ | |
23 | #define SSUSB_DEV_BASE 0x0000 | |
24 | #define SSUSB_EPCTL_CSR_BASE 0x0800 | |
25 | #define SSUSB_USB3_MAC_CSR_BASE 0x1400 | |
26 | #define SSUSB_USB3_SYS_CSR_BASE 0x1400 | |
27 | #define SSUSB_USB2_CSR_BASE 0x2400 | |
28 | ||
29 | /* IPPC register in Infra */ | |
30 | #define SSUSB_SIFSLV_IPPC_BASE 0x0000 | |
31 | ||
32 | /* --------------- SSUSB_DEV REGISTER DEFINITION --------------- */ | |
33 | ||
34 | #define U3D_LV1ISR (SSUSB_DEV_BASE + 0x0000) | |
35 | #define U3D_LV1IER (SSUSB_DEV_BASE + 0x0004) | |
36 | #define U3D_LV1IESR (SSUSB_DEV_BASE + 0x0008) | |
37 | #define U3D_LV1IECR (SSUSB_DEV_BASE + 0x000C) | |
38 | ||
39 | #define U3D_EPISR (SSUSB_DEV_BASE + 0x0080) | |
40 | #define U3D_EPIER (SSUSB_DEV_BASE + 0x0084) | |
41 | #define U3D_EPIESR (SSUSB_DEV_BASE + 0x0088) | |
42 | #define U3D_EPIECR (SSUSB_DEV_BASE + 0x008C) | |
43 | ||
44 | #define U3D_EP0CSR (SSUSB_DEV_BASE + 0x0100) | |
45 | #define U3D_RXCOUNT0 (SSUSB_DEV_BASE + 0x0108) | |
46 | #define U3D_RESERVED (SSUSB_DEV_BASE + 0x010C) | |
47 | #define U3D_TX1CSR0 (SSUSB_DEV_BASE + 0x0110) | |
48 | #define U3D_TX1CSR1 (SSUSB_DEV_BASE + 0x0114) | |
49 | #define U3D_TX1CSR2 (SSUSB_DEV_BASE + 0x0118) | |
50 | ||
51 | #define U3D_RX1CSR0 (SSUSB_DEV_BASE + 0x0210) | |
52 | #define U3D_RX1CSR1 (SSUSB_DEV_BASE + 0x0214) | |
53 | #define U3D_RX1CSR2 (SSUSB_DEV_BASE + 0x0218) | |
54 | ||
55 | #define U3D_FIFO0 (SSUSB_DEV_BASE + 0x0300) | |
56 | ||
57 | #define U3D_QCR0 (SSUSB_DEV_BASE + 0x0400) | |
58 | #define U3D_QCR1 (SSUSB_DEV_BASE + 0x0404) | |
59 | #define U3D_QCR2 (SSUSB_DEV_BASE + 0x0408) | |
60 | #define U3D_QCR3 (SSUSB_DEV_BASE + 0x040C) | |
1a46dfea CY |
61 | #define U3D_TXQHIAR1 (SSUSB_DEV_BASE + 0x0484) |
62 | #define U3D_RXQHIAR1 (SSUSB_DEV_BASE + 0x04C4) | |
df2069ac CY |
63 | |
64 | #define U3D_TXQCSR1 (SSUSB_DEV_BASE + 0x0510) | |
65 | #define U3D_TXQSAR1 (SSUSB_DEV_BASE + 0x0514) | |
66 | #define U3D_TXQCPR1 (SSUSB_DEV_BASE + 0x0518) | |
67 | ||
68 | #define U3D_RXQCSR1 (SSUSB_DEV_BASE + 0x0610) | |
69 | #define U3D_RXQSAR1 (SSUSB_DEV_BASE + 0x0614) | |
70 | #define U3D_RXQCPR1 (SSUSB_DEV_BASE + 0x0618) | |
71 | #define U3D_RXQLDPR1 (SSUSB_DEV_BASE + 0x061C) | |
72 | ||
73 | #define U3D_QISAR0 (SSUSB_DEV_BASE + 0x0700) | |
74 | #define U3D_QIER0 (SSUSB_DEV_BASE + 0x0704) | |
75 | #define U3D_QIESR0 (SSUSB_DEV_BASE + 0x0708) | |
76 | #define U3D_QIECR0 (SSUSB_DEV_BASE + 0x070C) | |
77 | #define U3D_QISAR1 (SSUSB_DEV_BASE + 0x0710) | |
78 | #define U3D_QIER1 (SSUSB_DEV_BASE + 0x0714) | |
79 | #define U3D_QIESR1 (SSUSB_DEV_BASE + 0x0718) | |
80 | #define U3D_QIECR1 (SSUSB_DEV_BASE + 0x071C) | |
81 | ||
82 | #define U3D_TQERRIR0 (SSUSB_DEV_BASE + 0x0780) | |
83 | #define U3D_TQERRIER0 (SSUSB_DEV_BASE + 0x0784) | |
84 | #define U3D_TQERRIESR0 (SSUSB_DEV_BASE + 0x0788) | |
85 | #define U3D_TQERRIECR0 (SSUSB_DEV_BASE + 0x078C) | |
86 | #define U3D_RQERRIR0 (SSUSB_DEV_BASE + 0x07C0) | |
87 | #define U3D_RQERRIER0 (SSUSB_DEV_BASE + 0x07C4) | |
88 | #define U3D_RQERRIESR0 (SSUSB_DEV_BASE + 0x07C8) | |
89 | #define U3D_RQERRIECR0 (SSUSB_DEV_BASE + 0x07CC) | |
90 | #define U3D_RQERRIR1 (SSUSB_DEV_BASE + 0x07D0) | |
91 | #define U3D_RQERRIER1 (SSUSB_DEV_BASE + 0x07D4) | |
92 | #define U3D_RQERRIESR1 (SSUSB_DEV_BASE + 0x07D8) | |
93 | #define U3D_RQERRIECR1 (SSUSB_DEV_BASE + 0x07DC) | |
94 | ||
95 | #define U3D_CAP_EP0FFSZ (SSUSB_DEV_BASE + 0x0C04) | |
96 | #define U3D_CAP_EPNTXFFSZ (SSUSB_DEV_BASE + 0x0C08) | |
97 | #define U3D_CAP_EPNRXFFSZ (SSUSB_DEV_BASE + 0x0C0C) | |
98 | #define U3D_CAP_EPINFO (SSUSB_DEV_BASE + 0x0C10) | |
99 | #define U3D_MISC_CTRL (SSUSB_DEV_BASE + 0x0C84) | |
100 | ||
101 | /*---------------- SSUSB_DEV FIELD DEFINITION ---------------*/ | |
102 | ||
103 | /* U3D_LV1ISR */ | |
104 | #define EP_CTRL_INTR BIT(5) | |
105 | #define MAC2_INTR BIT(4) | |
106 | #define DMA_INTR BIT(3) | |
107 | #define MAC3_INTR BIT(2) | |
108 | #define QMU_INTR BIT(1) | |
109 | #define BMU_INTR BIT(0) | |
110 | ||
111 | /* U3D_LV1IECR */ | |
112 | #define LV1IECR_MSK GENMASK(31, 0) | |
113 | ||
114 | /* U3D_EPISR */ | |
115 | #define EPRISR(x) (BIT(16) << (x)) | |
116 | #define EPTISR(x) (BIT(0) << (x)) | |
117 | #define EP0ISR BIT(0) | |
118 | ||
119 | /* U3D_EP0CSR */ | |
120 | #define EP0_SENDSTALL BIT(25) | |
121 | #define EP0_FIFOFULL BIT(23) | |
122 | #define EP0_SENTSTALL BIT(22) | |
123 | #define EP0_DPHTX BIT(20) | |
124 | #define EP0_DATAEND BIT(19) | |
125 | #define EP0_TXPKTRDY BIT(18) | |
126 | #define EP0_SETUPPKTRDY BIT(17) | |
127 | #define EP0_RXPKTRDY BIT(16) | |
128 | #define EP0_MAXPKTSZ_MSK GENMASK(9, 0) | |
129 | #define EP0_MAXPKTSZ(x) ((x) & EP0_MAXPKTSZ_MSK) | |
130 | #define EP0_W1C_BITS (~(EP0_RXPKTRDY | EP0_SETUPPKTRDY | EP0_SENTSTALL)) | |
131 | ||
132 | /* U3D_TX1CSR0 */ | |
133 | #define TX_DMAREQEN BIT(29) | |
134 | #define TX_FIFOFULL BIT(25) | |
135 | #define TX_FIFOEMPTY BIT(24) | |
136 | #define TX_SENTSTALL BIT(22) | |
137 | #define TX_SENDSTALL BIT(21) | |
138 | #define TX_TXPKTRDY BIT(16) | |
139 | #define TX_TXMAXPKTSZ_MSK GENMASK(10, 0) | |
140 | #define TX_TXMAXPKTSZ(x) ((x) & TX_TXMAXPKTSZ_MSK) | |
141 | #define TX_W1C_BITS (~(TX_SENTSTALL)) | |
142 | ||
143 | /* U3D_TX1CSR1 */ | |
144 | #define TX_MULT(x) (((x) & 0x3) << 22) | |
145 | #define TX_MAX_PKT(x) (((x) & 0x3f) << 16) | |
146 | #define TX_SLOT(x) (((x) & 0x3f) << 8) | |
147 | #define TX_TYPE(x) (((x) & 0x3) << 4) | |
148 | #define TX_SS_BURST(x) (((x) & 0xf) << 0) | |
149 | ||
150 | /* for TX_TYPE & RX_TYPE */ | |
151 | #define TYPE_BULK (0x0) | |
152 | #define TYPE_INT (0x1) | |
153 | #define TYPE_ISO (0x2) | |
154 | #define TYPE_MASK (0x3) | |
155 | ||
156 | /* U3D_TX1CSR2 */ | |
157 | #define TX_BINTERVAL(x) (((x) & 0xff) << 24) | |
158 | #define TX_FIFOSEGSIZE(x) (((x) & 0xf) << 16) | |
159 | #define TX_FIFOADDR(x) (((x) & 0x1fff) << 0) | |
160 | ||
161 | /* U3D_RX1CSR0 */ | |
162 | #define RX_DMAREQEN BIT(29) | |
163 | #define RX_SENTSTALL BIT(22) | |
164 | #define RX_SENDSTALL BIT(21) | |
165 | #define RX_RXPKTRDY BIT(16) | |
166 | #define RX_RXMAXPKTSZ_MSK GENMASK(10, 0) | |
167 | #define RX_RXMAXPKTSZ(x) ((x) & RX_RXMAXPKTSZ_MSK) | |
168 | #define RX_W1C_BITS (~(RX_SENTSTALL | RX_RXPKTRDY)) | |
169 | ||
170 | /* U3D_RX1CSR1 */ | |
171 | #define RX_MULT(x) (((x) & 0x3) << 22) | |
172 | #define RX_MAX_PKT(x) (((x) & 0x3f) << 16) | |
173 | #define RX_SLOT(x) (((x) & 0x3f) << 8) | |
174 | #define RX_TYPE(x) (((x) & 0x3) << 4) | |
175 | #define RX_SS_BURST(x) (((x) & 0xf) << 0) | |
176 | ||
177 | /* U3D_RX1CSR2 */ | |
178 | #define RX_BINTERVAL(x) (((x) & 0xff) << 24) | |
179 | #define RX_FIFOSEGSIZE(x) (((x) & 0xf) << 16) | |
180 | #define RX_FIFOADDR(x) (((x) & 0x1fff) << 0) | |
181 | ||
182 | /* U3D_QCR0 */ | |
183 | #define QMU_RX_CS_EN(x) (BIT(16) << (x)) | |
184 | #define QMU_TX_CS_EN(x) (BIT(0) << (x)) | |
185 | #define QMU_CS16B_EN BIT(0) | |
186 | ||
187 | /* U3D_QCR1 */ | |
188 | #define QMU_TX_ZLP(x) (BIT(0) << (x)) | |
189 | ||
190 | /* U3D_QCR3 */ | |
191 | #define QMU_RX_COZ(x) (BIT(16) << (x)) | |
192 | #define QMU_RX_ZLP(x) (BIT(0) << (x)) | |
193 | ||
1a46dfea CY |
194 | /* U3D_TXQHIAR1 */ |
195 | /* U3D_RXQHIAR1 */ | |
196 | #define QMU_LAST_DONE_PTR_HI(x) (((x) >> 16) & 0xf) | |
197 | #define QMU_CUR_GPD_ADDR_HI(x) (((x) >> 8) & 0xf) | |
198 | #define QMU_START_ADDR_HI_MSK GENMASK(3, 0) | |
199 | #define QMU_START_ADDR_HI(x) (((x) & 0xf) << 0) | |
200 | ||
df2069ac CY |
201 | /* U3D_TXQCSR1 */ |
202 | /* U3D_RXQCSR1 */ | |
203 | #define QMU_Q_ACTIVE BIT(15) | |
204 | #define QMU_Q_STOP BIT(2) | |
205 | #define QMU_Q_RESUME BIT(1) | |
206 | #define QMU_Q_START BIT(0) | |
207 | ||
208 | /* U3D_QISAR0, U3D_QIER0, U3D_QIESR0, U3D_QIECR0 */ | |
209 | #define QMU_RX_DONE_INT(x) (BIT(16) << (x)) | |
210 | #define QMU_TX_DONE_INT(x) (BIT(0) << (x)) | |
211 | ||
212 | /* U3D_QISAR1, U3D_QIER1, U3D_QIESR1, U3D_QIECR1 */ | |
213 | #define RXQ_ZLPERR_INT BIT(20) | |
214 | #define RXQ_LENERR_INT BIT(18) | |
215 | #define RXQ_CSERR_INT BIT(17) | |
216 | #define RXQ_EMPTY_INT BIT(16) | |
217 | #define TXQ_LENERR_INT BIT(2) | |
218 | #define TXQ_CSERR_INT BIT(1) | |
219 | #define TXQ_EMPTY_INT BIT(0) | |
220 | ||
221 | /* U3D_TQERRIR0, U3D_TQERRIER0, U3D_TQERRIESR0, U3D_TQERRIECR0 */ | |
222 | #define QMU_TX_LEN_ERR(x) (BIT(16) << (x)) | |
223 | #define QMU_TX_CS_ERR(x) (BIT(0) << (x)) | |
224 | ||
225 | /* U3D_RQERRIR0, U3D_RQERRIER0, U3D_RQERRIESR0, U3D_RQERRIECR0 */ | |
226 | #define QMU_RX_LEN_ERR(x) (BIT(16) << (x)) | |
227 | #define QMU_RX_CS_ERR(x) (BIT(0) << (x)) | |
228 | ||
229 | /* U3D_RQERRIR1, U3D_RQERRIER1, U3D_RQERRIESR1, U3D_RQERRIECR1 */ | |
230 | #define QMU_RX_ZLP_ERR(n) (BIT(16) << (n)) | |
231 | ||
232 | /* U3D_CAP_EPINFO */ | |
233 | #define CAP_RX_EP_NUM(x) (((x) >> 8) & 0x1f) | |
234 | #define CAP_TX_EP_NUM(x) ((x) & 0x1f) | |
235 | ||
236 | /* U3D_MISC_CTRL */ | |
1a46dfea | 237 | #define DMA_ADDR_36BIT BIT(31) |
df2069ac CY |
238 | #define VBUS_ON BIT(1) |
239 | #define VBUS_FRC_EN BIT(0) | |
240 | ||
241 | ||
242 | /*---------------- SSUSB_EPCTL_CSR REGISTER DEFINITION ----------------*/ | |
243 | ||
244 | #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000) | |
245 | #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004) | |
246 | ||
247 | #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050) | |
248 | #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054) | |
249 | ||
250 | /*---------------- SSUSB_EPCTL_CSR FIELD DEFINITION ----------------*/ | |
251 | ||
252 | /* U3D_DEVICE_CONF */ | |
253 | #define DEV_ADDR_MSK GENMASK(30, 24) | |
254 | #define DEV_ADDR(x) ((0x7f & (x)) << 24) | |
255 | #define HW_USB2_3_SEL BIT(18) | |
256 | #define SW_USB2_3_SEL_EN BIT(17) | |
257 | #define SW_USB2_3_SEL BIT(16) | |
258 | #define SSUSB_DEV_SPEED(x) ((x) & 0x7) | |
259 | ||
260 | /* U3D_EP_RST */ | |
261 | #define EP1_IN_RST BIT(17) | |
262 | #define EP1_OUT_RST BIT(1) | |
263 | #define EP_RST(is_in, epnum) (((is_in) ? BIT(16) : BIT(0)) << (epnum)) | |
264 | #define EP0_RST BIT(0) | |
265 | ||
266 | /* U3D_DEV_LINK_INTR_ENABLE */ | |
267 | /* U3D_DEV_LINK_INTR */ | |
268 | #define SSUSB_DEV_SPEED_CHG_INTR BIT(0) | |
269 | ||
270 | ||
271 | /*---------------- SSUSB_USB3_MAC_CSR REGISTER DEFINITION ----------------*/ | |
272 | ||
a29de31b | 273 | #define U3D_LTSSM_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0010) |
df2069ac CY |
274 | #define U3D_USB3_CONFIG (SSUSB_USB3_MAC_CSR_BASE + 0x001C) |
275 | ||
a29de31b CY |
276 | #define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE + 0x013C) |
277 | #define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE + 0x0140) | |
278 | ||
df2069ac CY |
279 | /*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/ |
280 | ||
a29de31b CY |
281 | /* U3D_LTSSM_CTRL */ |
282 | #define FORCE_POLLING_FAIL BIT(4) | |
283 | #define FORCE_RXDETECT_FAIL BIT(3) | |
284 | #define SOFT_U3_EXIT_EN BIT(2) | |
285 | #define COMPLIANCE_EN BIT(1) | |
286 | #define U1_GO_U2_EN BIT(0) | |
287 | ||
df2069ac CY |
288 | /* U3D_USB3_CONFIG */ |
289 | #define USB3_EN BIT(0) | |
290 | ||
a29de31b CY |
291 | /* U3D_LTSSM_INTR_ENABLE */ |
292 | /* U3D_LTSSM_INTR */ | |
293 | #define U3_RESUME_INTR BIT(18) | |
294 | #define U3_LFPS_TMOUT_INTR BIT(17) | |
295 | #define VBUS_FALL_INTR BIT(16) | |
296 | #define VBUS_RISE_INTR BIT(15) | |
297 | #define RXDET_SUCCESS_INTR BIT(14) | |
298 | #define EXIT_U3_INTR BIT(13) | |
299 | #define EXIT_U2_INTR BIT(12) | |
300 | #define EXIT_U1_INTR BIT(11) | |
301 | #define ENTER_U3_INTR BIT(10) | |
302 | #define ENTER_U2_INTR BIT(9) | |
303 | #define ENTER_U1_INTR BIT(8) | |
304 | #define ENTER_U0_INTR BIT(7) | |
305 | #define RECOVERY_INTR BIT(6) | |
306 | #define WARM_RST_INTR BIT(5) | |
307 | #define HOT_RST_INTR BIT(4) | |
308 | #define LOOPBACK_INTR BIT(3) | |
309 | #define COMPLIANCE_INTR BIT(2) | |
310 | #define SS_DISABLE_INTR BIT(1) | |
311 | #define SS_INACTIVE_INTR BIT(0) | |
312 | ||
df2069ac CY |
313 | /*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/ |
314 | ||
315 | #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C) | |
316 | #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210) | |
317 | #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214) | |
318 | ||
319 | /*---------------- SSUSB_USB3_SYS_CSR FIELD DEFINITION ----------------*/ | |
320 | ||
321 | /* U3D_LINK_UX_INACT_TIMER */ | |
322 | #define DEV_U2_INACT_TIMEOUT_MSK GENMASK(23, 16) | |
323 | #define DEV_U2_INACT_TIMEOUT_VALUE(x) (((x) & 0xff) << 16) | |
324 | #define U2_INACT_TIMEOUT_MSK GENMASK(15, 8) | |
325 | #define U1_INACT_TIMEOUT_MSK GENMASK(7, 0) | |
326 | #define U1_INACT_TIMEOUT_VALUE(x) ((x) & 0xff) | |
327 | ||
328 | /* U3D_LINK_POWER_CONTROL */ | |
329 | #define SW_U2_ACCEPT_ENABLE BIT(9) | |
330 | #define SW_U1_ACCEPT_ENABLE BIT(8) | |
331 | #define UX_EXIT BIT(5) | |
332 | #define LGO_U3 BIT(4) | |
333 | #define LGO_U2 BIT(3) | |
334 | #define LGO_U1 BIT(2) | |
335 | #define SW_U2_REQUEST_ENABLE BIT(1) | |
336 | #define SW_U1_REQUEST_ENABLE BIT(0) | |
337 | ||
338 | /* U3D_LINK_ERR_COUNT */ | |
339 | #define CLR_LINK_ERR_CNT BIT(16) | |
340 | #define LINK_ERROR_COUNT GENMASK(15, 0) | |
341 | ||
342 | /*---------------- SSUSB_USB2_CSR REGISTER DEFINITION ----------------*/ | |
343 | ||
344 | #define U3D_POWER_MANAGEMENT (SSUSB_USB2_CSR_BASE + 0x0004) | |
345 | #define U3D_DEVICE_CONTROL (SSUSB_USB2_CSR_BASE + 0x000C) | |
346 | #define U3D_USB2_TEST_MODE (SSUSB_USB2_CSR_BASE + 0x0014) | |
347 | #define U3D_COMMON_USB_INTR_ENABLE (SSUSB_USB2_CSR_BASE + 0x0018) | |
348 | #define U3D_COMMON_USB_INTR (SSUSB_USB2_CSR_BASE + 0x001C) | |
349 | #define U3D_LINK_RESET_INFO (SSUSB_USB2_CSR_BASE + 0x0024) | |
350 | #define U3D_USB20_FRAME_NUM (SSUSB_USB2_CSR_BASE + 0x003C) | |
351 | #define U3D_USB20_LPM_PARAMETER (SSUSB_USB2_CSR_BASE + 0x0044) | |
352 | #define U3D_USB20_MISC_CONTROL (SSUSB_USB2_CSR_BASE + 0x004C) | |
353 | ||
354 | /*---------------- SSUSB_USB2_CSR FIELD DEFINITION ----------------*/ | |
355 | ||
356 | /* U3D_POWER_MANAGEMENT */ | |
357 | #define LPM_BESL_STALL BIT(14) | |
358 | #define LPM_BESLD_STALL BIT(13) | |
359 | #define LPM_RWP BIT(11) | |
360 | #define LPM_HRWE BIT(10) | |
361 | #define LPM_MODE(x) (((x) & 0x3) << 8) | |
362 | #define ISO_UPDATE BIT(7) | |
363 | #define SOFT_CONN BIT(6) | |
364 | #define HS_ENABLE BIT(5) | |
365 | #define RESUME BIT(2) | |
366 | #define SUSPENDM_ENABLE BIT(0) | |
367 | ||
368 | /* U3D_DEVICE_CONTROL */ | |
369 | #define DC_HOSTREQ BIT(1) | |
370 | #define DC_SESSION BIT(0) | |
371 | ||
372 | /* U3D_USB2_TEST_MODE */ | |
373 | #define U2U3_AUTO_SWITCH BIT(10) | |
374 | #define LPM_FORCE_STALL BIT(8) | |
375 | #define FIFO_ACCESS BIT(6) | |
376 | #define FORCE_FS BIT(5) | |
377 | #define FORCE_HS BIT(4) | |
378 | #define TEST_PACKET_MODE BIT(3) | |
379 | #define TEST_K_MODE BIT(2) | |
380 | #define TEST_J_MODE BIT(1) | |
381 | #define TEST_SE0_NAK_MODE BIT(0) | |
382 | ||
383 | /* U3D_COMMON_USB_INTR_ENABLE */ | |
384 | /* U3D_COMMON_USB_INTR */ | |
385 | #define LPM_RESUME_INTR BIT(9) | |
386 | #define LPM_INTR BIT(8) | |
387 | #define DISCONN_INTR BIT(5) | |
388 | #define CONN_INTR BIT(4) | |
389 | #define SOF_INTR BIT(3) | |
390 | #define RESET_INTR BIT(2) | |
391 | #define RESUME_INTR BIT(1) | |
392 | #define SUSPEND_INTR BIT(0) | |
393 | ||
394 | /* U3D_LINK_RESET_INFO */ | |
395 | #define WTCHRP_MSK GENMASK(19, 16) | |
396 | ||
397 | /* U3D_USB20_LPM_PARAMETER */ | |
398 | #define LPM_BESLCK_U3(x) (((x) & 0xf) << 12) | |
399 | #define LPM_BESLCK(x) (((x) & 0xf) << 8) | |
400 | #define LPM_BESLDCK(x) (((x) & 0xf) << 4) | |
401 | #define LPM_BESL GENMASK(3, 0) | |
402 | ||
403 | /* U3D_USB20_MISC_CONTROL */ | |
404 | #define LPM_U3_ACK_EN BIT(0) | |
405 | ||
406 | /*---------------- SSUSB_SIFSLV_IPPC REGISTER DEFINITION ----------------*/ | |
407 | ||
408 | #define U3D_SSUSB_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x0000) | |
409 | #define U3D_SSUSB_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x0004) | |
410 | #define U3D_SSUSB_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x0008) | |
411 | #define U3D_SSUSB_IP_PW_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x000C) | |
412 | #define U3D_SSUSB_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE + 0x0010) | |
413 | #define U3D_SSUSB_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE + 0x0014) | |
414 | #define U3D_SSUSB_OTG_STS (SSUSB_SIFSLV_IPPC_BASE + 0x0018) | |
415 | #define U3D_SSUSB_OTG_STS_CLR (SSUSB_SIFSLV_IPPC_BASE + 0x001C) | |
416 | #define U3D_SSUSB_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0024) | |
417 | #define U3D_SSUSB_IP_DEV_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0028) | |
418 | #define U3D_SSUSB_OTG_INT_EN (SSUSB_SIFSLV_IPPC_BASE + 0x002C) | |
419 | #define U3D_SSUSB_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0030) | |
420 | #define U3D_SSUSB_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0050) | |
421 | #define U3D_SSUSB_REF_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x008C) | |
422 | #define U3D_SSUSB_DEV_RST_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x0098) | |
423 | #define U3D_SSUSB_HW_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A0) | |
424 | #define U3D_SSUSB_HW_SUB_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A4) | |
425 | #define U3D_SSUSB_IP_SPARE0 (SSUSB_SIFSLV_IPPC_BASE + 0x00C8) | |
426 | ||
427 | /*---------------- SSUSB_SIFSLV_IPPC FIELD DEFINITION ----------------*/ | |
428 | ||
429 | /* U3D_SSUSB_IP_PW_CTRL0 */ | |
430 | #define SSUSB_IP_SW_RST BIT(0) | |
431 | ||
432 | /* U3D_SSUSB_IP_PW_CTRL1 */ | |
433 | #define SSUSB_IP_HOST_PDN BIT(0) | |
434 | ||
435 | /* U3D_SSUSB_IP_PW_CTRL2 */ | |
436 | #define SSUSB_IP_DEV_PDN BIT(0) | |
437 | ||
438 | /* U3D_SSUSB_IP_PW_CTRL3 */ | |
439 | #define SSUSB_IP_PCIE_PDN BIT(0) | |
440 | ||
441 | /* U3D_SSUSB_IP_PW_STS1 */ | |
442 | #define SSUSB_IP_SLEEP_STS BIT(30) | |
443 | #define SSUSB_U3_MAC_RST_B_STS BIT(16) | |
444 | #define SSUSB_XHCI_RST_B_STS BIT(11) | |
445 | #define SSUSB_SYS125_RST_B_STS BIT(10) | |
446 | #define SSUSB_REF_RST_B_STS BIT(8) | |
447 | #define SSUSB_SYSPLL_STABLE BIT(0) | |
448 | ||
449 | /* U3D_SSUSB_IP_PW_STS2 */ | |
450 | #define SSUSB_U2_MAC_SYS_RST_B_STS BIT(0) | |
451 | ||
452 | /* U3D_SSUSB_OTG_STS */ | |
453 | #define SSUSB_VBUS_VALID BIT(9) | |
454 | ||
455 | /* U3D_SSUSB_OTG_STS_CLR */ | |
456 | #define SSUSB_VBUS_INTR_CLR BIT(6) | |
457 | ||
458 | /* U3D_SSUSB_IP_XHCI_CAP */ | |
459 | #define SSUSB_IP_XHCI_U2_PORT_NUM(x) (((x) >> 8) & 0xff) | |
460 | #define SSUSB_IP_XHCI_U3_PORT_NUM(x) ((x) & 0xff) | |
461 | ||
462 | /* U3D_SSUSB_IP_DEV_CAP */ | |
463 | #define SSUSB_IP_DEV_U3_PORT_NUM(x) ((x) & 0xff) | |
464 | ||
465 | /* U3D_SSUSB_OTG_INT_EN */ | |
466 | #define SSUSB_VBUS_CHG_INT_A_EN BIT(7) | |
467 | #define SSUSB_VBUS_CHG_INT_B_EN BIT(6) | |
468 | ||
469 | /* U3D_SSUSB_U3_CTRL_0P */ | |
470 | #define SSUSB_U3_PORT_HOST_SEL BIT(2) | |
471 | #define SSUSB_U3_PORT_PDN BIT(1) | |
472 | #define SSUSB_U3_PORT_DIS BIT(0) | |
473 | ||
474 | /* U3D_SSUSB_U2_CTRL_0P */ | |
b9582d2f | 475 | #define SSUSB_U2_PORT_VBUSVALID BIT(9) |
df2069ac | 476 | #define SSUSB_U2_PORT_OTG_SEL BIT(7) |
b9582d2f | 477 | #define SSUSB_U2_PORT_HOST BIT(2) |
df2069ac CY |
478 | #define SSUSB_U2_PORT_PDN BIT(1) |
479 | #define SSUSB_U2_PORT_DIS BIT(0) | |
b9582d2f | 480 | #define SSUSB_U2_PORT_HOST_SEL (SSUSB_U2_PORT_VBUSVALID | SSUSB_U2_PORT_HOST) |
df2069ac CY |
481 | |
482 | /* U3D_SSUSB_DEV_RST_CTRL */ | |
483 | #define SSUSB_DEV_SW_RST BIT(0) | |
484 | ||
485 | #endif /* _SSUSB_HW_REGS_H_ */ |