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37ebb549 | 1 | |
eb83092c AKG |
2 | /* |
3 | * Texas Instruments AM35x "glue layer" | |
4 | * | |
5 | * Copyright (c) 2010, by Texas Instruments | |
6 | * | |
7 | * Based on the DA8xx "glue layer" code. | |
8 | * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com> | |
9 | * | |
10 | * This file is part of the Inventra Controller Driver for Linux. | |
11 | * | |
12 | * The Inventra Controller Driver for Linux is free software; you | |
13 | * can redistribute it and/or modify it under the terms of the GNU | |
14 | * General Public License version 2 as published by the Free Software | |
15 | * Foundation. | |
16 | * | |
17 | * The Inventra Controller Driver for Linux is distributed in | |
18 | * the hope that it will be useful, but WITHOUT ANY WARRANTY; | |
19 | * without even the implied warranty of MERCHANTABILITY or | |
20 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
21 | * License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with The Inventra Controller Driver for Linux ; if not, | |
25 | * write to the Free Software Foundation, Inc., 59 Temple Place, | |
26 | * Suite 330, Boston, MA 02111-1307 USA | |
27 | * | |
28 | */ | |
29 | ||
ab570da2 | 30 | #include <linux/module.h> |
eb83092c | 31 | #include <linux/clk.h> |
ded017ee | 32 | #include <linux/err.h> |
eb83092c | 33 | #include <linux/io.h> |
ce40c576 FB |
34 | #include <linux/platform_device.h> |
35 | #include <linux/dma-mapping.h> | |
d7078df6 | 36 | #include <linux/usb/usb_phy_generic.h> |
e8c4a7ac | 37 | #include <linux/platform_data/usb-omap.h> |
eb83092c AKG |
38 | |
39 | #include "musb_core.h" | |
40 | ||
41 | /* | |
42 | * AM35x specific definitions | |
43 | */ | |
44 | /* USB 2.0 OTG module registers */ | |
45 | #define USB_REVISION_REG 0x00 | |
46 | #define USB_CTRL_REG 0x04 | |
47 | #define USB_STAT_REG 0x08 | |
48 | #define USB_EMULATION_REG 0x0c | |
49 | /* 0x10 Reserved */ | |
50 | #define USB_AUTOREQ_REG 0x14 | |
51 | #define USB_SRP_FIX_TIME_REG 0x18 | |
52 | #define USB_TEARDOWN_REG 0x1c | |
53 | #define EP_INTR_SRC_REG 0x20 | |
54 | #define EP_INTR_SRC_SET_REG 0x24 | |
55 | #define EP_INTR_SRC_CLEAR_REG 0x28 | |
56 | #define EP_INTR_MASK_REG 0x2c | |
57 | #define EP_INTR_MASK_SET_REG 0x30 | |
58 | #define EP_INTR_MASK_CLEAR_REG 0x34 | |
59 | #define EP_INTR_SRC_MASKED_REG 0x38 | |
60 | #define CORE_INTR_SRC_REG 0x40 | |
61 | #define CORE_INTR_SRC_SET_REG 0x44 | |
62 | #define CORE_INTR_SRC_CLEAR_REG 0x48 | |
63 | #define CORE_INTR_MASK_REG 0x4c | |
64 | #define CORE_INTR_MASK_SET_REG 0x50 | |
65 | #define CORE_INTR_MASK_CLEAR_REG 0x54 | |
66 | #define CORE_INTR_SRC_MASKED_REG 0x58 | |
67 | /* 0x5c Reserved */ | |
68 | #define USB_END_OF_INTR_REG 0x60 | |
69 | ||
70 | /* Control register bits */ | |
71 | #define AM35X_SOFT_RESET_MASK 1 | |
72 | ||
73 | /* USB interrupt register bits */ | |
74 | #define AM35X_INTR_USB_SHIFT 16 | |
75 | #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT) | |
76 | #define AM35X_INTR_DRVVBUS 0x100 | |
77 | #define AM35X_INTR_RX_SHIFT 16 | |
78 | #define AM35X_INTR_TX_SHIFT 0 | |
79 | #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */ | |
80 | #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */ | |
81 | #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT) | |
82 | #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT) | |
83 | ||
84 | #define USB_MENTOR_CORE_OFFSET 0x400 | |
85 | ||
0919dfc1 FB |
86 | struct am35x_glue { |
87 | struct device *dev; | |
88 | struct platform_device *musb; | |
2f36ff69 | 89 | struct platform_device *phy; |
03491761 FB |
90 | struct clk *phy_clk; |
91 | struct clk *clk; | |
0919dfc1 FB |
92 | }; |
93 | ||
eb83092c | 94 | /* |
743411b3 | 95 | * am35x_musb_enable - enable interrupts |
eb83092c | 96 | */ |
743411b3 | 97 | static void am35x_musb_enable(struct musb *musb) |
eb83092c AKG |
98 | { |
99 | void __iomem *reg_base = musb->ctrl_base; | |
100 | u32 epmask; | |
101 | ||
102 | /* Workaround: setup IRQs through both register sets. */ | |
103 | epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) | | |
104 | ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT); | |
105 | ||
106 | musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); | |
107 | musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); | |
108 | ||
109 | /* Force the DRVVBUS IRQ so we can start polling for ID change. */ | |
032ec49f FB |
110 | musb_writel(reg_base, CORE_INTR_SRC_SET_REG, |
111 | AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT); | |
eb83092c AKG |
112 | } |
113 | ||
114 | /* | |
743411b3 | 115 | * am35x_musb_disable - disable HDRC and flush interrupts |
eb83092c | 116 | */ |
743411b3 | 117 | static void am35x_musb_disable(struct musb *musb) |
eb83092c AKG |
118 | { |
119 | void __iomem *reg_base = musb->ctrl_base; | |
120 | ||
121 | musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); | |
122 | musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, | |
123 | AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK); | |
124 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
125 | musb_writel(reg_base, USB_END_OF_INTR_REG, 0); | |
126 | } | |
127 | ||
eb83092c | 128 | #define portstate(stmt) stmt |
eb83092c | 129 | |
743411b3 | 130 | static void am35x_musb_set_vbus(struct musb *musb, int is_on) |
eb83092c AKG |
131 | { |
132 | WARN_ON(is_on && is_peripheral_active(musb)); | |
133 | } | |
134 | ||
135 | #define POLL_SECONDS 2 | |
136 | ||
137 | static struct timer_list otg_workaround; | |
138 | ||
139 | static void otg_timer(unsigned long _musb) | |
140 | { | |
141 | struct musb *musb = (void *)_musb; | |
142 | void __iomem *mregs = musb->mregs; | |
143 | u8 devctl; | |
144 | unsigned long flags; | |
145 | ||
146 | /* | |
147 | * We poll because AM35x's won't expose several OTG-critical | |
148 | * status change events (from the transceiver) otherwise. | |
149 | */ | |
150 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
5c8a86e1 | 151 | dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl, |
e47d9254 | 152 | usb_otg_state_string(musb->xceiv->otg->state)); |
eb83092c AKG |
153 | |
154 | spin_lock_irqsave(&musb->lock, flags); | |
e47d9254 | 155 | switch (musb->xceiv->otg->state) { |
eb83092c AKG |
156 | case OTG_STATE_A_WAIT_BCON: |
157 | devctl &= ~MUSB_DEVCTL_SESSION; | |
158 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); | |
159 | ||
160 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
161 | if (devctl & MUSB_DEVCTL_BDEVICE) { | |
e47d9254 | 162 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
eb83092c AKG |
163 | MUSB_DEV_MODE(musb); |
164 | } else { | |
e47d9254 | 165 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
eb83092c AKG |
166 | MUSB_HST_MODE(musb); |
167 | } | |
168 | break; | |
169 | case OTG_STATE_A_WAIT_VFALL: | |
e47d9254 | 170 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; |
eb83092c AKG |
171 | musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG, |
172 | MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT); | |
173 | break; | |
174 | case OTG_STATE_B_IDLE: | |
eb83092c AKG |
175 | devctl = musb_readb(mregs, MUSB_DEVCTL); |
176 | if (devctl & MUSB_DEVCTL_BDEVICE) | |
177 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
178 | else | |
e47d9254 | 179 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
eb83092c AKG |
180 | break; |
181 | default: | |
182 | break; | |
183 | } | |
184 | spin_unlock_irqrestore(&musb->lock, flags); | |
185 | } | |
186 | ||
743411b3 | 187 | static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout) |
eb83092c AKG |
188 | { |
189 | static unsigned long last_timer; | |
190 | ||
eb83092c AKG |
191 | if (timeout == 0) |
192 | timeout = jiffies + msecs_to_jiffies(3); | |
193 | ||
194 | /* Never idle if active, or when VBUS timeout is not set as host */ | |
195 | if (musb->is_active || (musb->a_wait_bcon == 0 && | |
e47d9254 | 196 | musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) { |
5c8a86e1 | 197 | dev_dbg(musb->controller, "%s active, deleting timer\n", |
e47d9254 | 198 | usb_otg_state_string(musb->xceiv->otg->state)); |
eb83092c AKG |
199 | del_timer(&otg_workaround); |
200 | last_timer = jiffies; | |
201 | return; | |
202 | } | |
203 | ||
204 | if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) { | |
5c8a86e1 | 205 | dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n"); |
eb83092c AKG |
206 | return; |
207 | } | |
208 | last_timer = timeout; | |
209 | ||
5c8a86e1 | 210 | dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n", |
e47d9254 | 211 | usb_otg_state_string(musb->xceiv->otg->state), |
3df00453 | 212 | jiffies_to_msecs(timeout - jiffies)); |
eb83092c AKG |
213 | mod_timer(&otg_workaround, timeout); |
214 | } | |
215 | ||
743411b3 | 216 | static irqreturn_t am35x_musb_interrupt(int irq, void *hci) |
eb83092c AKG |
217 | { |
218 | struct musb *musb = hci; | |
219 | void __iomem *reg_base = musb->ctrl_base; | |
a9c03783 | 220 | struct device *dev = musb->controller; |
c1a7d67c | 221 | struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
a9c03783 | 222 | struct omap_musb_board_data *data = plat->board_data; |
d445b6da | 223 | struct usb_otg *otg = musb->xceiv->otg; |
eb83092c AKG |
224 | unsigned long flags; |
225 | irqreturn_t ret = IRQ_NONE; | |
a9c03783 | 226 | u32 epintr, usbintr; |
eb83092c AKG |
227 | |
228 | spin_lock_irqsave(&musb->lock, flags); | |
229 | ||
230 | /* Get endpoint interrupts */ | |
231 | epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); | |
232 | ||
233 | if (epintr) { | |
234 | musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr); | |
235 | ||
236 | musb->int_rx = | |
237 | (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT; | |
238 | musb->int_tx = | |
239 | (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT; | |
240 | } | |
241 | ||
242 | /* Get usb core interrupts */ | |
243 | usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG); | |
244 | if (!usbintr && !epintr) | |
245 | goto eoi; | |
246 | ||
247 | if (usbintr) { | |
248 | musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr); | |
249 | ||
250 | musb->int_usb = | |
251 | (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT; | |
252 | } | |
253 | /* | |
254 | * DRVVBUS IRQs are the only proxy we have (a very poor one!) for | |
255 | * AM35x's missing ID change IRQ. We need an ID change IRQ to | |
256 | * switch appropriately between halves of the OTG state machine. | |
257 | * Managing DEVCTL.SESSION per Mentor docs requires that we know its | |
258 | * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. | |
259 | * Also, DRVVBUS pulses for SRP (but not at 5V) ... | |
260 | */ | |
261 | if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) { | |
262 | int drvvbus = musb_readl(reg_base, USB_STAT_REG); | |
263 | void __iomem *mregs = musb->mregs; | |
264 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
265 | int err; | |
266 | ||
032ec49f | 267 | err = musb->int_usb & MUSB_INTR_VBUSERROR; |
eb83092c AKG |
268 | if (err) { |
269 | /* | |
270 | * The Mentor core doesn't debounce VBUS as needed | |
271 | * to cope with device connect current spikes. This | |
272 | * means it's not uncommon for bus-powered devices | |
273 | * to get VBUS errors during enumeration. | |
274 | * | |
275 | * This is a workaround, but newer RTL from Mentor | |
276 | * seems to allow a better one: "re"-starting sessions | |
277 | * without waiting for VBUS to stop registering in | |
278 | * devctl. | |
279 | */ | |
280 | musb->int_usb &= ~MUSB_INTR_VBUSERROR; | |
e47d9254 | 281 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; |
eb83092c AKG |
282 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
283 | WARNING("VBUS error workaround (delay coming)\n"); | |
032ec49f | 284 | } else if (drvvbus) { |
eb83092c | 285 | MUSB_HST_MODE(musb); |
d445b6da | 286 | otg->default_a = 1; |
e47d9254 | 287 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; |
eb83092c AKG |
288 | portstate(musb->port1_status |= USB_PORT_STAT_POWER); |
289 | del_timer(&otg_workaround); | |
290 | } else { | |
291 | musb->is_active = 0; | |
292 | MUSB_DEV_MODE(musb); | |
d445b6da | 293 | otg->default_a = 0; |
e47d9254 | 294 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
eb83092c AKG |
295 | portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); |
296 | } | |
297 | ||
298 | /* NOTE: this must complete power-on within 100 ms. */ | |
5c8a86e1 | 299 | dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", |
eb83092c | 300 | drvvbus ? "on" : "off", |
e47d9254 | 301 | usb_otg_state_string(musb->xceiv->otg->state), |
eb83092c AKG |
302 | err ? " ERROR" : "", |
303 | devctl); | |
304 | ret = IRQ_HANDLED; | |
305 | } | |
306 | ||
6ff1f3d3 SB |
307 | /* Drop spurious RX and TX if device is disconnected */ |
308 | if (musb->int_usb & MUSB_INTR_DISCONNECT) { | |
309 | musb->int_tx = 0; | |
310 | musb->int_rx = 0; | |
311 | } | |
312 | ||
eb83092c AKG |
313 | if (musb->int_tx || musb->int_rx || musb->int_usb) |
314 | ret |= musb_interrupt(musb); | |
315 | ||
316 | eoi: | |
317 | /* EOI needs to be written for the IRQ to be re-asserted. */ | |
318 | if (ret == IRQ_HANDLED || epintr || usbintr) { | |
319 | /* clear level interrupt */ | |
a9c03783 AKG |
320 | if (data->clear_irq) |
321 | data->clear_irq(); | |
eb83092c AKG |
322 | /* write EOI */ |
323 | musb_writel(reg_base, USB_END_OF_INTR_REG, 0); | |
324 | } | |
325 | ||
326 | /* Poll for ID change */ | |
e47d9254 | 327 | if (musb->xceiv->otg->state == OTG_STATE_B_IDLE) |
eb83092c AKG |
328 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
329 | ||
330 | spin_unlock_irqrestore(&musb->lock, flags); | |
331 | ||
332 | return ret; | |
333 | } | |
334 | ||
743411b3 | 335 | static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode) |
eb83092c | 336 | { |
a9c03783 | 337 | struct device *dev = musb->controller; |
c1a7d67c | 338 | struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
a9c03783 AKG |
339 | struct omap_musb_board_data *data = plat->board_data; |
340 | int retval = 0; | |
eb83092c | 341 | |
a9c03783 AKG |
342 | if (data->set_mode) |
343 | data->set_mode(musb_mode); | |
344 | else | |
345 | retval = -EIO; | |
eb83092c | 346 | |
a9c03783 | 347 | return retval; |
eb83092c AKG |
348 | } |
349 | ||
743411b3 | 350 | static int am35x_musb_init(struct musb *musb) |
eb83092c | 351 | { |
a9c03783 | 352 | struct device *dev = musb->controller; |
c1a7d67c | 353 | struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
a9c03783 | 354 | struct omap_musb_board_data *data = plat->board_data; |
eb83092c | 355 | void __iomem *reg_base = musb->ctrl_base; |
a9c03783 | 356 | u32 rev; |
eb83092c AKG |
357 | |
358 | musb->mregs += USB_MENTOR_CORE_OFFSET; | |
359 | ||
eb83092c AKG |
360 | /* Returns zero if e.g. not clocked */ |
361 | rev = musb_readl(reg_base, USB_REVISION_REG); | |
03491761 FB |
362 | if (!rev) |
363 | return -ENODEV; | |
eb83092c | 364 | |
662dca54 | 365 | musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); |
ded017ee | 366 | if (IS_ERR_OR_NULL(musb->xceiv)) |
25736e0c | 367 | return -EPROBE_DEFER; |
eb83092c | 368 | |
032ec49f | 369 | setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); |
eb83092c | 370 | |
a9c03783 AKG |
371 | /* Reset the musb */ |
372 | if (data->reset) | |
373 | data->reset(); | |
eb83092c AKG |
374 | |
375 | /* Reset the controller */ | |
376 | musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK); | |
377 | ||
378 | /* Start the on-chip PHY and its PLL. */ | |
a9c03783 AKG |
379 | if (data->set_phy_power) |
380 | data->set_phy_power(1); | |
eb83092c AKG |
381 | |
382 | msleep(5); | |
383 | ||
743411b3 | 384 | musb->isr = am35x_musb_interrupt; |
eb83092c AKG |
385 | |
386 | /* clear level interrupt */ | |
a9c03783 AKG |
387 | if (data->clear_irq) |
388 | data->clear_irq(); | |
03491761 | 389 | |
eb83092c | 390 | return 0; |
eb83092c AKG |
391 | } |
392 | ||
743411b3 | 393 | static int am35x_musb_exit(struct musb *musb) |
eb83092c | 394 | { |
a9c03783 | 395 | struct device *dev = musb->controller; |
c1a7d67c | 396 | struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
a9c03783 AKG |
397 | struct omap_musb_board_data *data = plat->board_data; |
398 | ||
032ec49f | 399 | del_timer_sync(&otg_workaround); |
eb83092c | 400 | |
a9c03783 AKG |
401 | /* Shutdown the on-chip PHY and its PLL. */ |
402 | if (data->set_phy_power) | |
403 | data->set_phy_power(0); | |
eb83092c | 404 | |
721002ec | 405 | usb_put_phy(musb->xceiv); |
eb83092c | 406 | |
eb83092c AKG |
407 | return 0; |
408 | } | |
409 | ||
843bb1d0 | 410 | /* AM35x supports only 32bit read operation */ |
1b40fc57 | 411 | static void am35x_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) |
843bb1d0 AKG |
412 | { |
413 | void __iomem *fifo = hw_ep->fifo; | |
414 | u32 val; | |
415 | int i; | |
416 | ||
417 | /* Read for 32bit-aligned destination address */ | |
418 | if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) { | |
419 | readsl(fifo, dst, len >> 2); | |
420 | dst += len & ~0x03; | |
421 | len &= 0x03; | |
422 | } | |
423 | /* | |
424 | * Now read the remaining 1 to 3 byte or complete length if | |
425 | * unaligned address. | |
426 | */ | |
427 | if (len > 4) { | |
428 | for (i = 0; i < (len >> 2); i++) { | |
429 | *(u32 *) dst = musb_readl(fifo, 0); | |
430 | dst += 4; | |
431 | } | |
432 | len &= 0x03; | |
433 | } | |
434 | if (len > 0) { | |
435 | val = musb_readl(fifo, 0); | |
436 | memcpy(dst, &val, len); | |
437 | } | |
438 | } | |
743411b3 | 439 | |
f7ec9437 | 440 | static const struct musb_platform_ops am35x_ops = { |
f8e9f34f | 441 | .quirks = MUSB_DMA_INVENTRA | MUSB_INDEXED_EP, |
743411b3 FB |
442 | .init = am35x_musb_init, |
443 | .exit = am35x_musb_exit, | |
444 | ||
1b40fc57 | 445 | .read_fifo = am35x_read_fifo, |
7f6283ed TL |
446 | #ifdef CONFIG_USB_INVENTRA_DMA |
447 | .dma_init = musbhs_dma_controller_create, | |
448 | .dma_exit = musbhs_dma_controller_destroy, | |
449 | #endif | |
743411b3 FB |
450 | .enable = am35x_musb_enable, |
451 | .disable = am35x_musb_disable, | |
452 | ||
453 | .set_mode = am35x_musb_set_mode, | |
454 | .try_idle = am35x_musb_try_idle, | |
455 | ||
456 | .set_vbus = am35x_musb_set_vbus, | |
457 | }; | |
ce40c576 | 458 | |
af384875 RK |
459 | static const struct platform_device_info am35x_dev_info = { |
460 | .name = "musb-hdrc", | |
461 | .id = PLATFORM_DEVID_AUTO, | |
462 | .dma_mask = DMA_BIT_MASK(32), | |
463 | }; | |
ce40c576 | 464 | |
41ac7b3a | 465 | static int am35x_probe(struct platform_device *pdev) |
ce40c576 | 466 | { |
c1a7d67c | 467 | struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
ce40c576 | 468 | struct platform_device *musb; |
0919dfc1 | 469 | struct am35x_glue *glue; |
af384875 | 470 | struct platform_device_info pinfo; |
03491761 FB |
471 | struct clk *phy_clk; |
472 | struct clk *clk; | |
473 | ||
ce40c576 FB |
474 | int ret = -ENOMEM; |
475 | ||
0919dfc1 FB |
476 | glue = kzalloc(sizeof(*glue), GFP_KERNEL); |
477 | if (!glue) { | |
478 | dev_err(&pdev->dev, "failed to allocate glue context\n"); | |
479 | goto err0; | |
480 | } | |
481 | ||
03491761 FB |
482 | phy_clk = clk_get(&pdev->dev, "fck"); |
483 | if (IS_ERR(phy_clk)) { | |
484 | dev_err(&pdev->dev, "failed to get PHY clock\n"); | |
485 | ret = PTR_ERR(phy_clk); | |
65b3d52d | 486 | goto err3; |
03491761 FB |
487 | } |
488 | ||
489 | clk = clk_get(&pdev->dev, "ick"); | |
490 | if (IS_ERR(clk)) { | |
491 | dev_err(&pdev->dev, "failed to get clock\n"); | |
492 | ret = PTR_ERR(clk); | |
65b3d52d | 493 | goto err4; |
03491761 FB |
494 | } |
495 | ||
496 | ret = clk_enable(phy_clk); | |
497 | if (ret) { | |
498 | dev_err(&pdev->dev, "failed to enable PHY clock\n"); | |
65b3d52d | 499 | goto err5; |
03491761 FB |
500 | } |
501 | ||
502 | ret = clk_enable(clk); | |
503 | if (ret) { | |
504 | dev_err(&pdev->dev, "failed to enable clock\n"); | |
65b3d52d | 505 | goto err6; |
03491761 FB |
506 | } |
507 | ||
0919dfc1 | 508 | glue->dev = &pdev->dev; |
03491761 FB |
509 | glue->phy_clk = phy_clk; |
510 | glue->clk = clk; | |
0919dfc1 | 511 | |
f7ec9437 FB |
512 | pdata->platform_ops = &am35x_ops; |
513 | ||
2f36ff69 FB |
514 | glue->phy = usb_phy_generic_register(); |
515 | if (IS_ERR(glue->phy)) | |
516 | goto err7; | |
0919dfc1 | 517 | platform_set_drvdata(pdev, glue); |
ce40c576 | 518 | |
af384875 RK |
519 | pinfo = am35x_dev_info; |
520 | pinfo.parent = &pdev->dev; | |
521 | pinfo.res = pdev->resource; | |
522 | pinfo.num_res = pdev->num_resources; | |
523 | pinfo.data = pdata; | |
524 | pinfo.size_data = sizeof(*pdata); | |
525 | ||
526 | glue->musb = musb = platform_device_register_full(&pinfo); | |
527 | if (IS_ERR(musb)) { | |
528 | ret = PTR_ERR(musb); | |
529 | dev_err(&pdev->dev, "failed to register musb device: %d\n", ret); | |
2f36ff69 | 530 | goto err8; |
ce40c576 FB |
531 | } |
532 | ||
533 | return 0; | |
534 | ||
2f36ff69 FB |
535 | err8: |
536 | usb_phy_generic_unregister(glue->phy); | |
537 | ||
65b3d52d | 538 | err7: |
03491761 FB |
539 | clk_disable(clk); |
540 | ||
65b3d52d | 541 | err6: |
03491761 FB |
542 | clk_disable(phy_clk); |
543 | ||
65b3d52d | 544 | err5: |
03491761 FB |
545 | clk_put(clk); |
546 | ||
65b3d52d | 547 | err4: |
03491761 FB |
548 | clk_put(phy_clk); |
549 | ||
65b3d52d | 550 | err3: |
0919dfc1 FB |
551 | kfree(glue); |
552 | ||
ce40c576 FB |
553 | err0: |
554 | return ret; | |
555 | } | |
556 | ||
fb4e98ab | 557 | static int am35x_remove(struct platform_device *pdev) |
ce40c576 | 558 | { |
0919dfc1 | 559 | struct am35x_glue *glue = platform_get_drvdata(pdev); |
ce40c576 | 560 | |
56291515 | 561 | platform_device_unregister(glue->musb); |
2f36ff69 | 562 | usb_phy_generic_unregister(glue->phy); |
03491761 FB |
563 | clk_disable(glue->clk); |
564 | clk_disable(glue->phy_clk); | |
565 | clk_put(glue->clk); | |
566 | clk_put(glue->phy_clk); | |
0919dfc1 | 567 | kfree(glue); |
ce40c576 FB |
568 | |
569 | return 0; | |
570 | } | |
571 | ||
fea2fc6e | 572 | #ifdef CONFIG_PM_SLEEP |
6f783e28 FB |
573 | static int am35x_suspend(struct device *dev) |
574 | { | |
575 | struct am35x_glue *glue = dev_get_drvdata(dev); | |
c1a7d67c | 576 | struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
a9c03783 AKG |
577 | struct omap_musb_board_data *data = plat->board_data; |
578 | ||
579 | /* Shutdown the on-chip PHY and its PLL. */ | |
580 | if (data->set_phy_power) | |
581 | data->set_phy_power(0); | |
6f783e28 | 582 | |
6f783e28 FB |
583 | clk_disable(glue->phy_clk); |
584 | clk_disable(glue->clk); | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
589 | static int am35x_resume(struct device *dev) | |
590 | { | |
591 | struct am35x_glue *glue = dev_get_drvdata(dev); | |
c1a7d67c | 592 | struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
a9c03783 | 593 | struct omap_musb_board_data *data = plat->board_data; |
6f783e28 FB |
594 | int ret; |
595 | ||
a9c03783 AKG |
596 | /* Start the on-chip PHY and its PLL. */ |
597 | if (data->set_phy_power) | |
598 | data->set_phy_power(1); | |
599 | ||
6f783e28 FB |
600 | ret = clk_enable(glue->phy_clk); |
601 | if (ret) { | |
602 | dev_err(dev, "failed to enable PHY clock\n"); | |
603 | return ret; | |
604 | } | |
605 | ||
606 | ret = clk_enable(glue->clk); | |
607 | if (ret) { | |
608 | dev_err(dev, "failed to enable clock\n"); | |
609 | return ret; | |
610 | } | |
611 | ||
612 | return 0; | |
613 | } | |
6f783e28 FB |
614 | #endif |
615 | ||
a49be8f2 DM |
616 | static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume); |
617 | ||
ce40c576 | 618 | static struct platform_driver am35x_driver = { |
e9e8c85e | 619 | .probe = am35x_probe, |
7690417d | 620 | .remove = am35x_remove, |
ce40c576 FB |
621 | .driver = { |
622 | .name = "musb-am35x", | |
a49be8f2 | 623 | .pm = &am35x_pm_ops, |
ce40c576 FB |
624 | }, |
625 | }; | |
626 | ||
627 | MODULE_DESCRIPTION("AM35x MUSB Glue Layer"); | |
628 | MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>"); | |
629 | MODULE_LICENSE("GPL v2"); | |
a0a83eb4 | 630 | module_platform_driver(am35x_driver); |