[mirror_ubuntu-jammy-kernel.git] / drivers / usb / musb / blackfin.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * MUSB OTG controller driver for Blackfin Processors
 *
 * Copyright 2006-2008 Analog Devices Inc.
 *
 * Enter bugs at http://blackfin.uclinux.org/
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/list.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/prefetch.h>
#include <linux/usb/usb_phy_generic.h>

#include <asm/cacheflush.h>

#include "musb_core.h"
#include "musbhsdma.h"
#include "blackfin.h"

struct bfin_glue {
	struct device		*dev;
	struct platform_device	*musb;
	struct platform_device	*phy;
};
#define glue_to_musb(g)		platform_get_drvdata(g->musb)

static u32 bfin_fifo_offset(u8 epnum)
{
	return USB_OFFSET(USB_EP0_FIFO) + (epnum * 8);
}

static u8 bfin_readb(const void __iomem *addr, unsigned offset)
{
	return (u8)(bfin_read16(addr + offset));
}

static u16 bfin_readw(const void __iomem *addr, unsigned offset)
{
	return bfin_read16(addr + offset);
}

static u32 bfin_readl(const void __iomem *addr, unsigned offset)
{
	return (u32)(bfin_read16(addr + offset));
}

static void bfin_writeb(void __iomem *addr, unsigned offset, u8 data)
{
	bfin_write16(addr + offset, (u16)data);
}

static void bfin_writew(void __iomem *addr, unsigned offset, u16 data)
{
	bfin_write16(addr + offset, data);
}

static void bfin_writel(void __iomem *addr, unsigned offset, u32 data)
{
	bfin_write16(addr + offset, (u16)data);
}

/*
 * Load an endpoint's FIFO
 */
static void bfin_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
{
	struct musb *musb = hw_ep->musb;
	void __iomem *fifo = hw_ep->fifo;
	void __iomem *epio = hw_ep->regs;
	u8 epnum = hw_ep->epnum;

	prefetch((u8 *)src);

	musb_writew(epio, MUSB_TXCOUNT, len);

	dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
			hw_ep->epnum, fifo, len, src, epio);

	dump_fifo_data(src, len);

	if (!ANOMALY_05000380 && epnum != 0) {
		u16 dma_reg;

		flush_dcache_range((unsigned long)src,
			(unsigned long)(src + len));

		/* Setup DMA address register */
		dma_reg = (u32)src;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)src >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for complete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();

		if (unlikely((unsigned long)src & 0x01))
			outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
		else
			outsw((unsigned long)fifo, src, (len + 1) >> 1);
	}
}
/*
 * Unload an endpoint's FIFO
 */
static void bfin_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
	struct musb *musb = hw_ep->musb;
	void __iomem *fifo = hw_ep->fifo;
	u8 epnum = hw_ep->epnum;

	if (ANOMALY_05000467 && epnum != 0) {
		u16 dma_reg;

		invalidate_dcache_range((unsigned long)dst,
			(unsigned long)(dst + len));

		/* Setup DMA address register */
		dma_reg = (u32)dst;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
		SSYNC();

		dma_reg = (u32)dst >> 16;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
		SSYNC();

		/* Setup DMA count register */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
		SSYNC();

		/* Enable the DMA */
		dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
		SSYNC();

		/* Wait for complete */
		while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
			cpu_relax();

		/* acknowledge dma interrupt */
		bfin_write_USB_DMA_INTERRUPT(1 << epnum);
		SSYNC();

		/* Reset DMA */
		bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
		SSYNC();
	} else {
		SSYNC();
		/* Read the last byte of packet with odd size from address fifo + 4
		 * to trigger 1 byte access to EP0 FIFO.
		 */
		if (len == 1)
			*dst = (u8)inw((unsigned long)fifo + 4);
		else {
			if (unlikely((unsigned long)dst & 0x01))
				insw_8((unsigned long)fifo, dst, len >> 1);
			else
				insw((unsigned long)fifo, dst, len >> 1);

			if (len & 0x01)
				*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
		}
	}
	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
			'R', hw_ep->epnum, fifo, len, dst);

	dump_fifo_data(dst, len);
}

static irqreturn_t blackfin_interrupt(int irq, void *__hci)
{
	unsigned long	flags;
	irqreturn_t	retval = IRQ_NONE;
	struct musb	*musb = __hci;

	spin_lock_irqsave(&musb->lock, flags);

	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);

	if (musb->int_usb || musb->int_tx || musb->int_rx) {
		musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
		musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
		musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
		retval = musb_interrupt(musb);
	}

	/* Start sampling ID pin, when plug is removed from MUSB */
	if ((musb->xceiv->otg->state == OTG_STATE_B_IDLE
		|| musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) ||
		(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
		mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY);
		musb->a_wait_bcon = TIMER_DELAY;
	}

	spin_unlock_irqrestore(&musb->lock, flags);

	return retval;
}

static void musb_conn_timer_handler(struct timer_list *t)
{
	struct musb *musb = from_timer(musb, t, dev_timer);
	unsigned long flags;
	u16 val;
	static u8 toggle;

	spin_lock_irqsave(&musb->lock, flags);
	switch (musb->xceiv->otg->state) {
	case OTG_STATE_A_IDLE:
	case OTG_STATE_A_WAIT_BCON:
		/* Start a new session */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val &= ~MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		/* Check if musb is host or peripheral. */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);

		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);
			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);
			musb->xceiv->otg->state = OTG_STATE_B_IDLE;
		}
		mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY);
		break;
	case OTG_STATE_B_IDLE:
		/*
		 * Start a new session.  It seems that MUSB needs taking
		 * some time to recognize the type of the plug inserted?
		 */
		val = musb_readw(musb->mregs, MUSB_DEVCTL);
		val |= MUSB_DEVCTL_SESSION;
		musb_writew(musb->mregs, MUSB_DEVCTL, val);
		val = musb_readw(musb->mregs, MUSB_DEVCTL);

		if (!(val & MUSB_DEVCTL_BDEVICE)) {
			gpio_set_value(musb->config->gpio_vrsel, 1);
			musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
		} else {
			gpio_set_value(musb->config->gpio_vrsel, 0);

			/* Ignore VBUSERROR and SUSPEND IRQ */
			val = musb_readb(musb->mregs, MUSB_INTRUSBE);
			val &= ~MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSBE, val);

			val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
			musb_writeb(musb->mregs, MUSB_INTRUSB, val);

			/* Toggle the Soft Conn bit, so that we can response to
			 * the inserting of either A-plug or B-plug.
			 */
			if (toggle) {
				val = musb_readb(musb->mregs, MUSB_POWER);
				val &= ~MUSB_POWER_SOFTCONN;
				musb_writeb(musb->mregs, MUSB_POWER, val);
				toggle = 0;
			} else {
				val = musb_readb(musb->mregs, MUSB_POWER);
				val |= MUSB_POWER_SOFTCONN;
				musb_writeb(musb->mregs, MUSB_POWER, val);
				toggle = 1;
			}
			/* The delay time is set to 1/4 second by default,
			 * shortening it, if accelerating A-plug detection
			 * is needed in OTG mode.
			 */
			mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY / 4);
		}
		break;
	default:
		dev_dbg(musb->controller, "%s state not handled\n",
			usb_otg_state_string(musb->xceiv->otg->state));
		break;
	}
	spin_unlock_irqrestore(&musb->lock, flags);

	dev_dbg(musb->controller, "state is %s\n",
		usb_otg_state_string(musb->xceiv->otg->state));
}

static void bfin_musb_enable(struct musb *musb)
{
	/* REVISIT is this really correct ? */
}

static void bfin_musb_disable(struct musb *musb)
{
}

static void bfin_musb_set_vbus(struct musb *musb, int is_on)
{
	int value = musb->config->gpio_vrsel_active;
	if (!is_on)
		value = !value;
	gpio_set_value(musb->config->gpio_vrsel, value);

	dev_dbg(musb->controller, "VBUS %s, devctl %02x "
		/* otg %3x conf %08x prcm %08x */ "\n",
		usb_otg_state_string(musb->xceiv->otg->state),
		musb_readb(musb->mregs, MUSB_DEVCTL));
}

static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
{
	return 0;
}

static int bfin_musb_vbus_status(struct musb *musb)
{
	return 0;
}

static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
{
	return -EIO;
}

static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
				u16 packet_sz, u8 *mode,
				dma_addr_t *dma_addr, u32 *len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;

	/*
	 * Anomaly 05000450 might cause data corruption when using DMA
	 * MODE 1 transmits with short packet.  So to work around this,
	 * we truncate all MODE 1 transfers down to a multiple of the
	 * max packet size, and then do the last short packet transfer
	 * (if there is any) using MODE 0.
	 */
	if (ANOMALY_05000450) {
		if (musb_channel->transmit && *mode == 1)
			*len = *len - (*len % packet_sz);
	}

	return 0;
}

static void bfin_musb_reg_init(struct musb *musb)
{
	if (ANOMALY_05000346) {
		bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
		SSYNC();
	}

	if (ANOMALY_05000347) {
		bfin_write_USB_APHY_CNTRL(0x0);
		SSYNC();
	}

	/* Configure PLL oscillator register */
	bfin_write_USB_PLLOSC_CTRL(0x3080 |
			((480/musb->config->clkin) << 1));
	SSYNC();

	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	SSYNC();

	bfin_write_USB_EP_NI0_RXMAXP(64);
	SSYNC();

	bfin_write_USB_EP_NI0_TXMAXP(64);
	SSYNC();

	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	bfin_write_USB_GLOBINTR(0x7);
	SSYNC();

	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
				EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
				EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
				EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
				EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
	SSYNC();
}

static int bfin_musb_init(struct musb *musb)
{

	/*
	 * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	 * and OTG HOST modes, while rev 1.1 and greater require PE7 to
	 * be low for DEVICE mode and high for HOST mode. We set it high
	 * here because we are in host mode
	 */

	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
		printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
			musb->config->gpio_vrsel);
		return -ENODEV;
	}
	gpio_direction_output(musb->config->gpio_vrsel, 0);

	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
	if (IS_ERR_OR_NULL(musb->xceiv)) {
		gpio_free(musb->config->gpio_vrsel);
		return -EPROBE_DEFER;
	}

	bfin_musb_reg_init(musb);

	timer_setup(&musb->dev_timer, musb_conn_timer_handler, 0);

	musb->xceiv->set_power = bfin_musb_set_power;

	musb->isr = blackfin_interrupt;
	musb->double_buffer_not_ok = true;

	return 0;
}

static int bfin_musb_exit(struct musb *musb)
{
	gpio_free(musb->config->gpio_vrsel);
	usb_put_phy(musb->xceiv);

	return 0;
}

static const struct musb_platform_ops bfin_ops = {
	.quirks		= MUSB_DMA_INVENTRA,
	.init		= bfin_musb_init,
	.exit		= bfin_musb_exit,

	.fifo_offset	= bfin_fifo_offset,
	.readb		= bfin_readb,
	.writeb		= bfin_writeb,
	.readw		= bfin_readw,
	.writew		= bfin_writew,
	.readl		= bfin_readl,
	.writel		= bfin_writel,
	.fifo_mode	= 2,
	.read_fifo	= bfin_read_fifo,
	.write_fifo	= bfin_write_fifo,
#ifdef CONFIG_USB_INVENTRA_DMA
	.dma_init	= musbhs_dma_controller_create,
	.dma_exit	= musbhs_dma_controller_destroy,
#endif
	.enable		= bfin_musb_enable,
	.disable	= bfin_musb_disable,

	.set_mode	= bfin_musb_set_mode,

	.vbus_status	= bfin_musb_vbus_status,
	.set_vbus	= bfin_musb_set_vbus,

	.adjust_channel_params = bfin_musb_adjust_channel_params,
};

static u64 bfin_dmamask = DMA_BIT_MASK(32);

static int bfin_probe(struct platform_device *pdev)
{
	struct resource musb_resources[2];
	struct musb_hdrc_platform_data	*pdata = dev_get_platdata(&pdev->dev);
	struct platform_device		*musb;
	struct bfin_glue		*glue;

	int				ret = -ENOMEM;

	glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
	if (!glue)
		goto err0;

	musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
	if (!musb)
		goto err0;

	musb->dev.parent		= &pdev->dev;
	musb->dev.dma_mask		= &bfin_dmamask;
	musb->dev.coherent_dma_mask	= bfin_dmamask;

	glue->dev			= &pdev->dev;
	glue->musb			= musb;

	pdata->platform_ops		= &bfin_ops;

	glue->phy = usb_phy_generic_register();
	if (IS_ERR(glue->phy))
		goto err1;
	platform_set_drvdata(pdev, glue);

	memset(musb_resources, 0x00, sizeof(*musb_resources) *
			ARRAY_SIZE(musb_resources));

	musb_resources[0].name = pdev->resource[0].name;
	musb_resources[0].start = pdev->resource[0].start;
	musb_resources[0].end = pdev->resource[0].end;
	musb_resources[0].flags = pdev->resource[0].flags;

	musb_resources[1].name = pdev->resource[1].name;
	musb_resources[1].start = pdev->resource[1].start;
	musb_resources[1].end = pdev->resource[1].end;
	musb_resources[1].flags = pdev->resource[1].flags;

	ret = platform_device_add_resources(musb, musb_resources,
			ARRAY_SIZE(musb_resources));
	if (ret) {
		dev_err(&pdev->dev, "failed to add resources\n");
		goto err2;
	}

	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	if (ret) {
		dev_err(&pdev->dev, "failed to add platform_data\n");
		goto err2;
	}

	ret = platform_device_add(musb);
	if (ret) {
		dev_err(&pdev->dev, "failed to register musb device\n");
		goto err2;
	}

	return 0;

err2:
	usb_phy_generic_unregister(glue->phy);

err1:
	platform_device_put(musb);

err0:
	return ret;
}

static int bfin_remove(struct platform_device *pdev)
{
	struct bfin_glue		*glue = platform_get_drvdata(pdev);

	platform_device_unregister(glue->musb);
	usb_phy_generic_unregister(glue->phy);

	return 0;
}

static int __maybe_unused bfin_suspend(struct device *dev)
{
	struct bfin_glue	*glue = dev_get_drvdata(dev);
	struct musb		*musb = glue_to_musb(glue);

	if (is_host_active(musb))
		/*
		 * During hibernate gpio_vrsel will change from high to low
		 * low which will generate wakeup event resume the system
		 * immediately.  Set it to 0 before hibernate to avoid this
		 * wakeup event.
		 */
		gpio_set_value(musb->config->gpio_vrsel, 0);

	return 0;
}

static int __maybe_unused bfin_resume(struct device *dev)
{
	struct bfin_glue	*glue = dev_get_drvdata(dev);
	struct musb		*musb = glue_to_musb(glue);

	bfin_musb_reg_init(musb);

	return 0;
}

static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);

static struct platform_driver bfin_driver = {
	.probe		= bfin_probe,
	.remove		= bfin_remove,
	.driver		= {
		.name	= "musb-blackfin",
		.pm	= &bfin_pm_ops,
	},
};

MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
MODULE_LICENSE("GPL v2");
module_platform_driver(bfin_driver);
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0+
0c6a8818 BW	2	/*
	3	* MUSB OTG controller driver for Blackfin Processors
	4	*
	5	* Copyright 2006-2008 Analog Devices Inc.
	6	*
	7	* Enter bugs at http://blackfin.uclinux.org/
	8	*
	9	* Licensed under the GPL-2 or later.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/sched.h>
0c6a8818	15	#include <linux/list.h>
0c6a8818 BW	16	#include <linux/gpio.h>
0c6a8818 BW	17	#include <linux/io.h>
ded017ee	18	#include <linux/err.h>
9cb0308e FB	19	#include <linux/platform_device.h>
9cb0308e FB	20	#include <linux/dma-mapping.h>
ad50c1b2	21	#include <linux/prefetch.h>
d7078df6	22	#include <linux/usb/usb_phy_generic.h>
0c6a8818 BW	23
	24	#include <asm/cacheflush.h>
	25
	26	#include "musb_core.h"
13254307	27	#include "musbhsdma.h"
0c6a8818 BW	28	#include "blackfin.h"
0c6a8818 BW	29
a023c631 FB	30	struct bfin_glue {
	31	struct device *dev;
	32	struct platform_device *musb;
2f36ff69	33	struct platform_device *phy;
a023c631	34	};
fcd22e3b	35	#define glue_to_musb(g) platform_get_drvdata(g->musb)
a023c631	36
cc92f681 TL	37	static u32 bfin_fifo_offset(u8 epnum)
	38	{
	39	return USB_OFFSET(USB_EP0_FIFO) + (epnum * 8);
	40	}
	41
	42	static u8 bfin_readb(const void __iomem *addr, unsigned offset)
	43	{
	44	return (u8)(bfin_read16(addr + offset));
	45	}
	46
	47	static u16 bfin_readw(const void __iomem *addr, unsigned offset)
	48	{
	49	return bfin_read16(addr + offset);
	50	}
	51
	52	static u32 bfin_readl(const void __iomem *addr, unsigned offset)
	53	{
	54	return (u32)(bfin_read16(addr + offset));
	55	}
	56
	57	static void bfin_writeb(void __iomem *addr, unsigned offset, u8 data)
	58	{
	59	bfin_write16(addr + offset, (u16)data);
	60	}
	61
	62	static void bfin_writew(void __iomem *addr, unsigned offset, u16 data)
	63	{
	64	bfin_write16(addr + offset, data);
	65	}
	66
b1d34783	67	static void bfin_writel(void __iomem *addr, unsigned offset, u32 data)
cc92f681 TL	68	{
	69	bfin_write16(addr + offset, (u16)data);
	70	}
	71
0c6a8818 BW	72	/*
	73	* Load an endpoint's FIFO
	74	*/
1b40fc57	75	static void bfin_write_fifo(struct musb_hw_ep hw_ep, u16 len, const u8 src)
0c6a8818	76	{
28e49705	77	struct musb *musb = hw_ep->musb;
0c6a8818 BW	78	void __iomem *fifo = hw_ep->fifo;
0c6a8818 BW	79	void __iomem *epio = hw_ep->regs;
1c4bdc01	80	u8 epnum = hw_ep->epnum;
0c6a8818 BW	81
	82	prefetch((u8 *)src);
	83
	84	musb_writew(epio, MUSB_TXCOUNT, len);
	85
5c8a86e1	86	dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
0c6a8818 BW	87	hw_ep->epnum, fifo, len, src, epio);
	88
	89	dump_fifo_data(src, len);
	90
1c4bdc01	91	if (!ANOMALY_05000380 && epnum != 0) {
1ca9e9ca BW	92	u16 dma_reg;
	93
	94	flush_dcache_range((unsigned long)src,
	95	(unsigned long)(src + len));
1c4bdc01 BW	96
1c4bdc01 BW	97	/* Setup DMA address register */
1ca9e9ca	98	dma_reg = (u32)src;
1c4bdc01 BW	99	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	100	SSYNC();
	101
1ca9e9ca	102	dma_reg = (u32)src >> 16;
1c4bdc01 BW	103	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	104	SSYNC();
	105
	106	/* Setup DMA count register */
	107	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	108	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	109	SSYNC();
	110
	111	/* Enable the DMA */
	112	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA \| DIRECTION;
	113	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	114	SSYNC();
	115
5ae477b0	116	/* Wait for complete */
1c4bdc01 BW	117	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	118	cpu_relax();
	119
	120	/* acknowledge dma interrupt */
	121	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	122	SSYNC();
	123
	124	/* Reset DMA */
	125	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	126	SSYNC();
	127	} else {
	128	SSYNC();
	129
	130	if (unlikely((unsigned long)src & 0x01))
1ca9e9ca	131	outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	132	else
1ca9e9ca	133	outsw((unsigned long)fifo, src, (len + 1) >> 1);
1c4bdc01	134	}
0c6a8818	135	}
0c6a8818 BW	136	/*
	137	* Unload an endpoint's FIFO
	138	*/
1b40fc57	139	static void bfin_read_fifo(struct musb_hw_ep hw_ep, u16 len, u8 dst)
0c6a8818	140	{
28e49705	141	struct musb *musb = hw_ep->musb;
0c6a8818 BW	142	void __iomem *fifo = hw_ep->fifo;
0c6a8818 BW	143	u8 epnum = hw_ep->epnum;
0c6a8818	144
1c4bdc01	145	if (ANOMALY_05000467 && epnum != 0) {
1ca9e9ca	146	u16 dma_reg;
1c4bdc01	147
1ca9e9ca BW	148	invalidate_dcache_range((unsigned long)dst,
1ca9e9ca BW	149	(unsigned long)(dst + len));
1c4bdc01 BW	150
1c4bdc01 BW	151	/* Setup DMA address register */
1ca9e9ca	152	dma_reg = (u32)dst;
1c4bdc01 BW	153	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
	154	SSYNC();
	155
1ca9e9ca	156	dma_reg = (u32)dst >> 16;
1c4bdc01 BW	157	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
	158	SSYNC();
	159
	160	/* Setup DMA count register */
	161	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
	162	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
	163	SSYNC();
	164
	165	/* Enable the DMA */
	166	dma_reg = (epnum << 4) \| DMA_ENA \| INT_ENA;
	167	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
	168	SSYNC();
	169
5ae477b0	170	/* Wait for complete */
1c4bdc01 BW	171	while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
	172	cpu_relax();
	173
	174	/* acknowledge dma interrupt */
	175	bfin_write_USB_DMA_INTERRUPT(1 << epnum);
	176	SSYNC();
	177
	178	/* Reset DMA */
	179	bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
	180	SSYNC();
	181	} else {
	182	SSYNC();
	183	/* Read the last byte of packet with odd size from address fifo + 4
	184	* to trigger 1 byte access to EP0 FIFO.
	185	*/
	186	if (len == 1)
	187	*dst = (u8)inw((unsigned long)fifo + 4);
	188	else {
	189	if (unlikely((unsigned long)dst & 0x01))
	190	insw_8((unsigned long)fifo, dst, len >> 1);
	191	else
	192	insw((unsigned long)fifo, dst, len >> 1);
	193
	194	if (len & 0x01)
	195	*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
	196	}
	197	}
5c8a86e1	198	dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
04f4086f MF	199	'R', hw_ep->epnum, fifo, len, dst);
04f4086f MF	200
0c6a8818 BW	201	dump_fifo_data(dst, len);
	202	}
	203
	204	static irqreturn_t blackfin_interrupt(int irq, void *__hci)
	205	{
	206	unsigned long flags;
	207	irqreturn_t retval = IRQ_NONE;
	208	struct musb *musb = __hci;
	209
	210	spin_lock_irqsave(&musb->lock, flags);
	211
	212	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
	213	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
	214	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
	215
	216	if (musb->int_usb \|\| musb->int_tx \|\| musb->int_rx) {
	217	musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
	218	musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
	219	musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
	220	retval = musb_interrupt(musb);
	221	}
	222
ff927add	223	/* Start sampling ID pin, when plug is removed from MUSB */
e47d9254 AT	224	if ((musb->xceiv->otg->state == OTG_STATE_B_IDLE
e47d9254 AT	225	\|\| musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) \|\|
68f64714	226	(musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
05678497	227	mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY);
ff927add CC	228	musb->a_wait_bcon = TIMER_DELAY;
	229	}
	230
0c6a8818 BW	231	spin_unlock_irqrestore(&musb->lock, flags);
0c6a8818 BW	232
2f831751	233	return retval;
0c6a8818 BW	234	}
0c6a8818 BW	235
05678497	236	static void musb_conn_timer_handler(struct timer_list *t)
0c6a8818	237	{
05678497	238	struct musb *musb = from_timer(musb, t, dev_timer);
0c6a8818 BW	239	unsigned long flags;
0c6a8818 BW	240	u16 val;
ff927add	241	static u8 toggle;
0c6a8818 BW	242
0c6a8818 BW	243	spin_lock_irqsave(&musb->lock, flags);
e47d9254	244	switch (musb->xceiv->otg->state) {
0c6a8818 BW	245	case OTG_STATE_A_IDLE:
	246	case OTG_STATE_A_WAIT_BCON:
	247	/* Start a new session */
	248	val = musb_readw(musb->mregs, MUSB_DEVCTL);
ff927add CC	249	val &= ~MUSB_DEVCTL_SESSION;
ff927add CC	250	musb_writew(musb->mregs, MUSB_DEVCTL, val);
0c6a8818 BW	251	val \|= MUSB_DEVCTL_SESSION;
0c6a8818 BW	252	musb_writew(musb->mregs, MUSB_DEVCTL, val);
ff927add CC	253	/* Check if musb is host or peripheral. */
	254	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	255
	256	if (!(val & MUSB_DEVCTL_BDEVICE)) {
	257	gpio_set_value(musb->config->gpio_vrsel, 1);
e47d9254	258	musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
ff927add CC	259	} else {
	260	gpio_set_value(musb->config->gpio_vrsel, 0);
	261	/* Ignore VBUSERROR and SUSPEND IRQ */
	262	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	263	val &= ~MUSB_INTR_VBUSERROR;
	264	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	265
	266	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	267	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
e47d9254	268	musb->xceiv->otg->state = OTG_STATE_B_IDLE;
ff927add	269	}
05678497	270	mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY);
ff927add CC	271	break;
ff927add CC	272	case OTG_STATE_B_IDLE:
032ec49f FB	273	/*
032ec49f FB	274	* Start a new session. It seems that MUSB needs taking
ff927add CC	275	* some time to recognize the type of the plug inserted?
	276	*/
	277	val = musb_readw(musb->mregs, MUSB_DEVCTL);
	278	val \|= MUSB_DEVCTL_SESSION;
	279	musb_writew(musb->mregs, MUSB_DEVCTL, val);
0c6a8818	280	val = musb_readw(musb->mregs, MUSB_DEVCTL);
ff927add	281
0c6a8818 BW	282	if (!(val & MUSB_DEVCTL_BDEVICE)) {
0c6a8818 BW	283	gpio_set_value(musb->config->gpio_vrsel, 1);
e47d9254	284	musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
0c6a8818 BW	285	} else {
	286	gpio_set_value(musb->config->gpio_vrsel, 0);
	287
	288	/* Ignore VBUSERROR and SUSPEND IRQ */
	289	val = musb_readb(musb->mregs, MUSB_INTRUSBE);
	290	val &= ~MUSB_INTR_VBUSERROR;
	291	musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
	292
	293	val = MUSB_INTR_SUSPEND \| MUSB_INTR_VBUSERROR;
	294	musb_writeb(musb->mregs, MUSB_INTRUSB, val);
	295
ff927add CC	296	/* Toggle the Soft Conn bit, so that we can response to
	297	* the inserting of either A-plug or B-plug.
	298	*/
	299	if (toggle) {
	300	val = musb_readb(musb->mregs, MUSB_POWER);
	301	val &= ~MUSB_POWER_SOFTCONN;
	302	musb_writeb(musb->mregs, MUSB_POWER, val);
	303	toggle = 0;
	304	} else {
	305	val = musb_readb(musb->mregs, MUSB_POWER);
	306	val \|= MUSB_POWER_SOFTCONN;
	307	musb_writeb(musb->mregs, MUSB_POWER, val);
	308	toggle = 1;
	309	}
	310	/* The delay time is set to 1/4 second by default,
	311	* shortening it, if accelerating A-plug detection
	312	* is needed in OTG mode.
	313	*/
05678497	314	mod_timer(&musb->dev_timer, jiffies + TIMER_DELAY / 4);
0c6a8818	315	}
0c6a8818	316	break;
0c6a8818	317	default:
5c8a86e1	318	dev_dbg(musb->controller, "%s state not handled\n",
e47d9254	319	usb_otg_state_string(musb->xceiv->otg->state));
0c6a8818 BW	320	break;
	321	}
	322	spin_unlock_irqrestore(&musb->lock, flags);
	323
5c8a86e1	324	dev_dbg(musb->controller, "state is %s\n",
e47d9254	325	usb_otg_state_string(musb->xceiv->otg->state));
0c6a8818 BW	326	}
0c6a8818 BW	327
743411b3	328	static void bfin_musb_enable(struct musb *musb)
0c6a8818	329	{
032ec49f	330	/* REVISIT is this really correct ? */
0c6a8818 BW	331	}
0c6a8818 BW	332
743411b3	333	static void bfin_musb_disable(struct musb *musb)
0c6a8818 BW	334	{
	335	}
	336
743411b3	337	static void bfin_musb_set_vbus(struct musb *musb, int is_on)
0c6a8818	338	{
6ddc6dae CC	339	int value = musb->config->gpio_vrsel_active;
	340	if (!is_on)
	341	value = !value;
	342	gpio_set_value(musb->config->gpio_vrsel, value);
0c6a8818	343
5c8a86e1	344	dev_dbg(musb->controller, "VBUS %s, devctl %02x "
0c6a8818	345	/* otg %3x conf %08x prcm %08x */ "\n",
e47d9254	346	usb_otg_state_string(musb->xceiv->otg->state),
0c6a8818 BW	347	musb_readb(musb->mregs, MUSB_DEVCTL));
	348	}
	349
86753811	350	static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
0c6a8818 BW	351	{
	352	return 0;
	353	}
	354
45567c28	355	static int bfin_musb_vbus_status(struct musb *musb)
0c6a8818 BW	356	{
	357	return 0;
	358	}
	359
743411b3	360	static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
0c6a8818	361	{
2002e768	362	return -EIO;
0c6a8818 BW	363	}
0c6a8818 BW	364
13254307 MF	365	static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
	366	u16 packet_sz, u8 *mode,
	367	dma_addr_t dma_addr, u32 len)
	368	{
	369	struct musb_dma_channel *musb_channel = channel->private_data;
	370
	371	/*
	372	* Anomaly 05000450 might cause data corruption when using DMA
	373	* MODE 1 transmits with short packet. So to work around this,
	374	* we truncate all MODE 1 transfers down to a multiple of the
	375	* max packet size, and then do the last short packet transfer
	376	* (if there is any) using MODE 0.
	377	*/
	378	if (ANOMALY_05000450) {
	379	if (musb_channel->transmit && *mode == 1)
	380	len = len - (*len % packet_sz);
	381	}
	382
	383	return 0;
	384	}
	385
743411b3	386	static void bfin_musb_reg_init(struct musb *musb)
0c6a8818	387	{
d426e60d RG	388	if (ANOMALY_05000346) {
	389	bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
	390	SSYNC();
	391	}
0c6a8818	392
d426e60d RG	393	if (ANOMALY_05000347) {
	394	bfin_write_USB_APHY_CNTRL(0x0);
	395	SSYNC();
	396	}
0c6a8818	397
0c6a8818	398	/* Configure PLL oscillator register */
9c756462 BL	399	bfin_write_USB_PLLOSC_CTRL(0x3080 \|
9c756462 BL	400	((480/musb->config->clkin) << 1));
0c6a8818 BW	401	SSYNC();
	402
	403	bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
	404	SSYNC();
	405
	406	bfin_write_USB_EP_NI0_RXMAXP(64);
	407	SSYNC();
	408
	409	bfin_write_USB_EP_NI0_TXMAXP(64);
	410	SSYNC();
	411
	412	/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
	413	bfin_write_USB_GLOBINTR(0x7);
	414	SSYNC();
	415
	416	bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA \| EP1_TX_ENA \| EP2_TX_ENA \|
	417	EP3_TX_ENA \| EP4_TX_ENA \| EP5_TX_ENA \|
	418	EP6_TX_ENA \| EP7_TX_ENA \| EP1_RX_ENA \|
	419	EP2_RX_ENA \| EP3_RX_ENA \| EP4_RX_ENA \|
	420	EP5_RX_ENA \| EP6_RX_ENA \| EP7_RX_ENA);
	421	SSYNC();
743411b3 FB	422	}
	423
	424	static int bfin_musb_init(struct musb *musb)
	425	{
	426
	427	/*
	428	* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
	429	* and OTG HOST modes, while rev 1.1 and greater require PE7 to
	430	* be low for DEVICE mode and high for HOST mode. We set it high
	431	* here because we are in host mode
	432	*/
	433
	434	if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
	435	printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
	436	musb->config->gpio_vrsel);
	437	return -ENODEV;
	438	}
	439	gpio_direction_output(musb->config->gpio_vrsel, 0);
	440
662dca54	441	musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
ded017ee	442	if (IS_ERR_OR_NULL(musb->xceiv)) {
743411b3	443	gpio_free(musb->config->gpio_vrsel);
25736e0c	444	return -EPROBE_DEFER;
743411b3 FB	445	}
	446
	447	bfin_musb_reg_init(musb);
0c6a8818	448
05678497	449	timer_setup(&musb->dev_timer, musb_conn_timer_handler, 0);
032ec49f FB	450
032ec49f FB	451	musb->xceiv->set_power = bfin_musb_set_power;
0c6a8818 BW	452
0c6a8818 BW	453	musb->isr = blackfin_interrupt;
06624818	454	musb->double_buffer_not_ok = true;
0c6a8818 BW	455
	456	return 0;
	457	}
	458
743411b3	459	static int bfin_musb_exit(struct musb *musb)
0c6a8818	460	{
0c6a8818	461	gpio_free(musb->config->gpio_vrsel);
721002ec	462	usb_put_phy(musb->xceiv);
e741e637	463
0c6a8818 BW	464	return 0;
0c6a8818 BW	465	}
743411b3	466
f7ec9437	467	static const struct musb_platform_ops bfin_ops = {
f8e9f34f	468	.quirks = MUSB_DMA_INVENTRA,
743411b3 FB	469	.init = bfin_musb_init,
	470	.exit = bfin_musb_exit,
	471
5563bb57	472	.fifo_offset = bfin_fifo_offset,
cc92f681 TL	473	.readb = bfin_readb,
	474	.writeb = bfin_writeb,
	475	.readw = bfin_readw,
	476	.writew = bfin_writew,
	477	.readl = bfin_readl,
	478	.writel = bfin_writel,
8a77f05a	479	.fifo_mode = 2,
1b40fc57 TL	480	.read_fifo = bfin_read_fifo,
1b40fc57 TL	481	.write_fifo = bfin_write_fifo,
7f6283ed TL	482	#ifdef CONFIG_USB_INVENTRA_DMA
	483	.dma_init = musbhs_dma_controller_create,
	484	.dma_exit = musbhs_dma_controller_destroy,
	485	#endif
743411b3 FB	486	.enable = bfin_musb_enable,
	487	.disable = bfin_musb_disable,
	488
	489	.set_mode = bfin_musb_set_mode,
743411b3 FB	490
	491	.vbus_status = bfin_musb_vbus_status,
	492	.set_vbus = bfin_musb_set_vbus,
13254307 MF	493
13254307 MF	494	.adjust_channel_params = bfin_musb_adjust_channel_params,
743411b3	495	};
9cb0308e FB	496
	497	static u64 bfin_dmamask = DMA_BIT_MASK(32);
	498
41ac7b3a	499	static int bfin_probe(struct platform_device *pdev)
9cb0308e	500	{
09fc7d22	501	struct resource musb_resources[2];
c1a7d67c	502	struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
9cb0308e	503	struct platform_device *musb;
a023c631	504	struct bfin_glue *glue;
9cb0308e FB	505
	506	int ret = -ENOMEM;
	507
f875bf35	508	glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
65469790	509	if (!glue)
a023c631	510	goto err0;
a023c631	511
2f771164	512	musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
65469790	513	if (!musb)
f875bf35	514	goto err0;
9cb0308e FB	515
	516	musb->dev.parent = &pdev->dev;
	517	musb->dev.dma_mask = &bfin_dmamask;
	518	musb->dev.coherent_dma_mask = bfin_dmamask;
	519
a023c631 FB	520	glue->dev = &pdev->dev;
	521	glue->musb = musb;
	522
f7ec9437 FB	523	pdata->platform_ops = &bfin_ops;
f7ec9437 FB	524
2f36ff69 FB	525	glue->phy = usb_phy_generic_register();
2f36ff69 FB	526	if (IS_ERR(glue->phy))
f875bf35	527	goto err1;
a023c631	528	platform_set_drvdata(pdev, glue);
9cb0308e	529
09fc7d22 FB	530	memset(musb_resources, 0x00, sizeof(musb_resources)
	531	ARRAY_SIZE(musb_resources));
	532
	533	musb_resources[0].name = pdev->resource[0].name;
	534	musb_resources[0].start = pdev->resource[0].start;
	535	musb_resources[0].end = pdev->resource[0].end;
	536	musb_resources[0].flags = pdev->resource[0].flags;
	537
	538	musb_resources[1].name = pdev->resource[1].name;
	539	musb_resources[1].start = pdev->resource[1].start;
	540	musb_resources[1].end = pdev->resource[1].end;
	541	musb_resources[1].flags = pdev->resource[1].flags;
	542
	543	ret = platform_device_add_resources(musb, musb_resources,
	544	ARRAY_SIZE(musb_resources));
9cb0308e FB	545	if (ret) {
9cb0308e FB	546	dev_err(&pdev->dev, "failed to add resources\n");
f875bf35	547	goto err2;
9cb0308e FB	548	}
	549
	550	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
	551	if (ret) {
	552	dev_err(&pdev->dev, "failed to add platform_data\n");
f875bf35	553	goto err2;
9cb0308e FB	554	}
	555
	556	ret = platform_device_add(musb);
	557	if (ret) {
	558	dev_err(&pdev->dev, "failed to register musb device\n");
f875bf35	559	goto err2;
9cb0308e FB	560	}
	561
	562	return 0;
	563
2f36ff69	564	err2:
f875bf35	565	usb_phy_generic_unregister(glue->phy);
9cb0308e	566
a023c631	567	err1:
f875bf35	568	platform_device_put(musb);
a023c631	569
9cb0308e FB	570	err0:
	571	return ret;
	572	}
	573
fb4e98ab	574	static int bfin_remove(struct platform_device *pdev)
9cb0308e	575	{
a023c631	576	struct bfin_glue *glue = platform_get_drvdata(pdev);
9cb0308e	577
01e40da0	578	platform_device_unregister(glue->musb);
2f36ff69	579	usb_phy_generic_unregister(glue->phy);
9cb0308e FB	580
	581	return 0;
	582	}
	583
1ef2bcef	584	static int __maybe_unused bfin_suspend(struct device *dev)
fcd22e3b FB	585	{
	586	struct bfin_glue *glue = dev_get_drvdata(dev);
	587	struct musb *musb = glue_to_musb(glue);
	588
	589	if (is_host_active(musb))
	590	/*
	591	* During hibernate gpio_vrsel will change from high to low
	592	* low which will generate wakeup event resume the system
	593	* immediately. Set it to 0 before hibernate to avoid this
	594	* wakeup event.
	595	*/
	596	gpio_set_value(musb->config->gpio_vrsel, 0);
	597
	598	return 0;
	599	}
	600
1ef2bcef	601	static int __maybe_unused bfin_resume(struct device *dev)
fcd22e3b FB	602	{
	603	struct bfin_glue *glue = dev_get_drvdata(dev);
	604	struct musb *musb = glue_to_musb(glue);
	605
	606	bfin_musb_reg_init(musb);
	607
	608	return 0;
	609	}
fcd22e3b	610
0967313b DM	611	static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);
0967313b DM	612
9cb0308e	613	static struct platform_driver bfin_driver = {
e9e8c85e	614	.probe = bfin_probe,
d9b2b19f	615	.remove = bfin_remove,
9cb0308e	616	.driver = {
417ddf86	617	.name = "musb-blackfin",
0967313b	618	.pm = &bfin_pm_ops,
9cb0308e FB	619	},
	620	};
	621
	622	MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
	623	MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
	624	MODULE_LICENSE("GPL v2");
692373e1	625	module_platform_driver(bfin_driver);