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550a7375 FB |
1 | /* |
2 | * Copyright (C) 2005-2006 by Texas Instruments | |
3 | * | |
4 | * This file is part of the Inventra Controller Driver for Linux. | |
5 | * | |
6 | * The Inventra Controller Driver for Linux is free software; you | |
7 | * can redistribute it and/or modify it under the terms of the GNU | |
8 | * General Public License version 2 as published by the Free Software | |
9 | * Foundation. | |
10 | * | |
11 | * The Inventra Controller Driver for Linux is distributed in | |
12 | * the hope that it will be useful, but WITHOUT ANY WARRANTY; | |
13 | * without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | * License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with The Inventra Controller Driver for Linux ; if not, | |
19 | * write to the Free Software Foundation, Inc., 59 Temple Place, | |
20 | * Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
550a7375 FB |
27 | #include <linux/init.h> |
28 | #include <linux/list.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/clk.h> | |
ded017ee | 31 | #include <linux/err.h> |
550a7375 | 32 | #include <linux/io.h> |
c767c1c6 | 33 | #include <linux/gpio.h> |
73b089b0 FB |
34 | #include <linux/platform_device.h> |
35 | #include <linux/dma-mapping.h> | |
78c289f8 | 36 | #include <linux/usb/nop-usb-xceiv.h> |
550a7375 | 37 | |
d163ef24 | 38 | #include <mach/cputype.h> |
6594b2d7 | 39 | #include <mach/hardware.h> |
10b4eade | 40 | |
550a7375 FB |
41 | #include <asm/mach-types.h> |
42 | ||
43 | #include "musb_core.h" | |
44 | ||
45 | #ifdef CONFIG_MACH_DAVINCI_EVM | |
a2396a32 | 46 | #define GPIO_nVBUS_DRV 160 |
550a7375 FB |
47 | #endif |
48 | ||
49 | #include "davinci.h" | |
50 | #include "cppi_dma.h" | |
51 | ||
52 | ||
a227fd7d DB |
53 | #define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR) |
54 | #define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR) | |
55 | ||
e110de4d FB |
56 | struct davinci_glue { |
57 | struct device *dev; | |
58 | struct platform_device *musb; | |
03491761 | 59 | struct clk *clk; |
e110de4d FB |
60 | }; |
61 | ||
550a7375 FB |
62 | /* REVISIT (PM) we should be able to keep the PHY in low power mode most |
63 | * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0 | |
64 | * and, when in host mode, autosuspending idle root ports... PHYPLLON | |
65 | * (overriding SUSPENDM?) then likely needs to stay off. | |
66 | */ | |
67 | ||
68 | static inline void phy_on(void) | |
69 | { | |
a227fd7d DB |
70 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); |
71 | ||
72 | /* power everything up; start the on-chip PHY and its PLL */ | |
73 | phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN); | |
74 | phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON; | |
75 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
76 | ||
77 | /* wait for PLL to lock before proceeding */ | |
78 | while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0) | |
550a7375 FB |
79 | cpu_relax(); |
80 | } | |
81 | ||
82 | static inline void phy_off(void) | |
83 | { | |
a227fd7d DB |
84 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); |
85 | ||
86 | /* powerdown the on-chip PHY, its PLL, and the OTG block */ | |
87 | phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON); | |
88 | phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN; | |
89 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
550a7375 FB |
90 | } |
91 | ||
92 | static int dma_off = 1; | |
93 | ||
743411b3 | 94 | static void davinci_musb_enable(struct musb *musb) |
550a7375 FB |
95 | { |
96 | u32 tmp, old, val; | |
97 | ||
98 | /* workaround: setup irqs through both register sets */ | |
99 | tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK) | |
100 | << DAVINCI_USB_TXINT_SHIFT; | |
101 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
102 | old = tmp; | |
103 | tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK)) | |
104 | << DAVINCI_USB_RXINT_SHIFT; | |
105 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
106 | tmp |= old; | |
107 | ||
108 | val = ~MUSB_INTR_SOF; | |
109 | tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT); | |
110 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
111 | ||
112 | if (is_dma_capable() && !dma_off) | |
113 | printk(KERN_WARNING "%s %s: dma not reactivated\n", | |
114 | __FILE__, __func__); | |
115 | else | |
116 | dma_off = 0; | |
117 | ||
118 | /* force a DRVVBUS irq so we can start polling for ID change */ | |
032ec49f | 119 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, |
550a7375 FB |
120 | DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT); |
121 | } | |
122 | ||
123 | /* | |
124 | * Disable the HDRC and flush interrupts | |
125 | */ | |
743411b3 | 126 | static void davinci_musb_disable(struct musb *musb) |
550a7375 FB |
127 | { |
128 | /* because we don't set CTRLR.UINT, "important" to: | |
129 | * - not read/write INTRUSB/INTRUSBE | |
130 | * - (except during initial setup, as workaround) | |
131 | * - use INTSETR/INTCLRR instead | |
132 | */ | |
133 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG, | |
134 | DAVINCI_USB_USBINT_MASK | |
135 | | DAVINCI_USB_TXINT_MASK | |
136 | | DAVINCI_USB_RXINT_MASK); | |
137 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
138 | musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0); | |
139 | ||
140 | if (is_dma_capable() && !dma_off) | |
141 | WARNING("dma still active\n"); | |
142 | } | |
143 | ||
144 | ||
550a7375 | 145 | #define portstate(stmt) stmt |
550a7375 | 146 | |
a227fd7d DB |
147 | /* |
148 | * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM, | |
149 | * which doesn't wire DRVVBUS to the FET that switches it. Unclear | |
150 | * if that's a problem with the DM6446 chip or just with that board. | |
151 | * | |
152 | * In either case, the DM355 EVM automates DRVVBUS the normal way, | |
153 | * when J10 is out, and TI documents it as handling OTG. | |
154 | */ | |
550a7375 FB |
155 | |
156 | #ifdef CONFIG_MACH_DAVINCI_EVM | |
550a7375 | 157 | |
a227fd7d DB |
158 | static int vbus_state = -1; |
159 | ||
550a7375 FB |
160 | /* I2C operations are always synchronous, and require a task context. |
161 | * With unloaded systems, using the shared workqueue seems to suffice | |
162 | * to satisfy the 100msec A_WAIT_VRISE timeout... | |
163 | */ | |
164 | static void evm_deferred_drvvbus(struct work_struct *ignored) | |
165 | { | |
c767c1c6 | 166 | gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state); |
550a7375 FB |
167 | vbus_state = !vbus_state; |
168 | } | |
550a7375 | 169 | |
550a7375 FB |
170 | #endif /* EVM */ |
171 | ||
743411b3 | 172 | static void davinci_musb_source_power(struct musb *musb, int is_on, int immediate) |
550a7375 | 173 | { |
a227fd7d | 174 | #ifdef CONFIG_MACH_DAVINCI_EVM |
550a7375 FB |
175 | if (is_on) |
176 | is_on = 1; | |
177 | ||
178 | if (vbus_state == is_on) | |
179 | return; | |
180 | vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */ | |
181 | ||
550a7375 | 182 | if (machine_is_davinci_evm()) { |
a227fd7d DB |
183 | static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus); |
184 | ||
550a7375 | 185 | if (immediate) |
c767c1c6 | 186 | gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state); |
550a7375 FB |
187 | else |
188 | schedule_work(&evm_vbus_work); | |
550a7375 | 189 | } |
550a7375 FB |
190 | if (immediate) |
191 | vbus_state = is_on; | |
a227fd7d | 192 | #endif |
550a7375 FB |
193 | } |
194 | ||
743411b3 | 195 | static void davinci_musb_set_vbus(struct musb *musb, int is_on) |
550a7375 FB |
196 | { |
197 | WARN_ON(is_on && is_peripheral_active(musb)); | |
743411b3 | 198 | davinci_musb_source_power(musb, is_on, 0); |
550a7375 FB |
199 | } |
200 | ||
201 | ||
202 | #define POLL_SECONDS 2 | |
203 | ||
204 | static struct timer_list otg_workaround; | |
205 | ||
206 | static void otg_timer(unsigned long _musb) | |
207 | { | |
208 | struct musb *musb = (void *)_musb; | |
209 | void __iomem *mregs = musb->mregs; | |
210 | u8 devctl; | |
211 | unsigned long flags; | |
212 | ||
213 | /* We poll because DaVinci's won't expose several OTG-critical | |
214 | * status change events (from the transceiver) otherwise. | |
215 | */ | |
216 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
5c8a86e1 | 217 | dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl, |
3df00453 | 218 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
219 | |
220 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 221 | switch (musb->xceiv->state) { |
550a7375 FB |
222 | case OTG_STATE_A_WAIT_VFALL: |
223 | /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL | |
224 | * seems to mis-handle session "start" otherwise (or in our | |
225 | * case "recover"), in routine "VBUS was valid by the time | |
226 | * VBUSERR got reported during enumeration" cases. | |
227 | */ | |
228 | if (devctl & MUSB_DEVCTL_VBUS) { | |
229 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
230 | break; | |
231 | } | |
84e250ff | 232 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; |
550a7375 FB |
233 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, |
234 | MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT); | |
235 | break; | |
236 | case OTG_STATE_B_IDLE: | |
032ec49f FB |
237 | /* |
238 | * There's no ID-changed IRQ, so we have no good way to tell | |
550a7375 FB |
239 | * when to switch to the A-Default state machine (by setting |
240 | * the DEVCTL.SESSION flag). | |
241 | * | |
242 | * Workaround: whenever we're in B_IDLE, try setting the | |
243 | * session flag every few seconds. If it works, ID was | |
244 | * grounded and we're now in the A-Default state machine. | |
245 | * | |
246 | * NOTE setting the session flag is _supposed_ to trigger | |
247 | * SRP, but clearly it doesn't. | |
248 | */ | |
249 | musb_writeb(mregs, MUSB_DEVCTL, | |
250 | devctl | MUSB_DEVCTL_SESSION); | |
251 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
252 | if (devctl & MUSB_DEVCTL_BDEVICE) | |
253 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
254 | else | |
84e250ff | 255 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 FB |
256 | break; |
257 | default: | |
258 | break; | |
259 | } | |
260 | spin_unlock_irqrestore(&musb->lock, flags); | |
261 | } | |
262 | ||
743411b3 | 263 | static irqreturn_t davinci_musb_interrupt(int irq, void *__hci) |
550a7375 FB |
264 | { |
265 | unsigned long flags; | |
266 | irqreturn_t retval = IRQ_NONE; | |
267 | struct musb *musb = __hci; | |
d445b6da | 268 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 | 269 | void __iomem *tibase = musb->ctrl_base; |
91e9c4fe | 270 | struct cppi *cppi; |
550a7375 FB |
271 | u32 tmp; |
272 | ||
273 | spin_lock_irqsave(&musb->lock, flags); | |
274 | ||
275 | /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through | |
276 | * the Mentor registers (except for setup), use the TI ones and EOI. | |
277 | * | |
dfff0615 | 278 | * Docs describe irq "vector" registers associated with the CPPI and |
550a7375 FB |
279 | * USB EOI registers. These hold a bitmask corresponding to the |
280 | * current IRQ, not an irq handler address. Would using those bits | |
281 | * resolve some of the races observed in this dispatch code?? | |
282 | */ | |
283 | ||
284 | /* CPPI interrupts share the same IRQ line, but have their own | |
285 | * mask, state, "vector", and EOI registers. | |
286 | */ | |
91e9c4fe SS |
287 | cppi = container_of(musb->dma_controller, struct cppi, controller); |
288 | if (is_cppi_enabled() && musb->dma_controller && !cppi->irq) | |
289 | retval = cppi_interrupt(irq, __hci); | |
550a7375 FB |
290 | |
291 | /* ack and handle non-CPPI interrupts */ | |
292 | tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG); | |
293 | musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp); | |
5c8a86e1 | 294 | dev_dbg(musb->controller, "IRQ %08x\n", tmp); |
550a7375 FB |
295 | |
296 | musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK) | |
297 | >> DAVINCI_USB_RXINT_SHIFT; | |
298 | musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK) | |
299 | >> DAVINCI_USB_TXINT_SHIFT; | |
300 | musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK) | |
301 | >> DAVINCI_USB_USBINT_SHIFT; | |
302 | ||
303 | /* DRVVBUS irqs are the only proxy we have (a very poor one!) for | |
304 | * DaVinci's missing ID change IRQ. We need an ID change IRQ to | |
305 | * switch appropriately between halves of the OTG state machine. | |
306 | * Managing DEVCTL.SESSION per Mentor docs requires we know its | |
307 | * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. | |
308 | * Also, DRVVBUS pulses for SRP (but not at 5V) ... | |
309 | */ | |
310 | if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) { | |
311 | int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG); | |
312 | void __iomem *mregs = musb->mregs; | |
313 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
314 | int err = musb->int_usb & MUSB_INTR_VBUSERROR; | |
315 | ||
032ec49f | 316 | err = musb->int_usb & MUSB_INTR_VBUSERROR; |
550a7375 FB |
317 | if (err) { |
318 | /* The Mentor core doesn't debounce VBUS as needed | |
319 | * to cope with device connect current spikes. This | |
320 | * means it's not uncommon for bus-powered devices | |
321 | * to get VBUS errors during enumeration. | |
322 | * | |
323 | * This is a workaround, but newer RTL from Mentor | |
324 | * seems to allow a better one: "re"starting sessions | |
325 | * without waiting (on EVM, a **long** time) for VBUS | |
326 | * to stop registering in devctl. | |
327 | */ | |
328 | musb->int_usb &= ~MUSB_INTR_VBUSERROR; | |
84e250ff | 329 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
330 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
331 | WARNING("VBUS error workaround (delay coming)\n"); | |
032ec49f | 332 | } else if (drvvbus) { |
550a7375 | 333 | MUSB_HST_MODE(musb); |
d445b6da | 334 | otg->default_a = 1; |
84e250ff | 335 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; |
550a7375 FB |
336 | portstate(musb->port1_status |= USB_PORT_STAT_POWER); |
337 | del_timer(&otg_workaround); | |
338 | } else { | |
339 | musb->is_active = 0; | |
340 | MUSB_DEV_MODE(musb); | |
d445b6da | 341 | otg->default_a = 0; |
84e250ff | 342 | musb->xceiv->state = OTG_STATE_B_IDLE; |
550a7375 FB |
343 | portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); |
344 | } | |
345 | ||
89368d3d DB |
346 | /* NOTE: this must complete poweron within 100 msec |
347 | * (OTG_TIME_A_WAIT_VRISE) but we don't check for that. | |
348 | */ | |
743411b3 | 349 | davinci_musb_source_power(musb, drvvbus, 0); |
5c8a86e1 | 350 | dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n", |
550a7375 | 351 | drvvbus ? "on" : "off", |
3df00453 | 352 | otg_state_string(musb->xceiv->state), |
550a7375 FB |
353 | err ? " ERROR" : "", |
354 | devctl); | |
355 | retval = IRQ_HANDLED; | |
356 | } | |
357 | ||
358 | if (musb->int_tx || musb->int_rx || musb->int_usb) | |
359 | retval |= musb_interrupt(musb); | |
360 | ||
361 | /* irq stays asserted until EOI is written */ | |
362 | musb_writel(tibase, DAVINCI_USB_EOI_REG, 0); | |
363 | ||
364 | /* poll for ID change */ | |
032ec49f | 365 | if (musb->xceiv->state == OTG_STATE_B_IDLE) |
550a7375 FB |
366 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
367 | ||
368 | spin_unlock_irqrestore(&musb->lock, flags); | |
369 | ||
a5073b52 | 370 | return retval; |
550a7375 FB |
371 | } |
372 | ||
743411b3 | 373 | static int davinci_musb_set_mode(struct musb *musb, u8 mode) |
96a274d1 DB |
374 | { |
375 | /* EVM can't do this (right?) */ | |
376 | return -EIO; | |
377 | } | |
378 | ||
743411b3 | 379 | static int davinci_musb_init(struct musb *musb) |
550a7375 FB |
380 | { |
381 | void __iomem *tibase = musb->ctrl_base; | |
382 | u32 revision; | |
383 | ||
84e250ff | 384 | usb_nop_xceiv_register(); |
662dca54 | 385 | musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); |
ded017ee | 386 | if (IS_ERR_OR_NULL(musb->xceiv)) |
c67dd31c | 387 | goto unregister; |
84e250ff | 388 | |
550a7375 | 389 | musb->mregs += DAVINCI_BASE_OFFSET; |
550a7375 | 390 | |
550a7375 FB |
391 | /* returns zero if e.g. not clocked */ |
392 | revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG); | |
393 | if (revision == 0) | |
84e250ff | 394 | goto fail; |
550a7375 | 395 | |
032ec49f | 396 | setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); |
550a7375 | 397 | |
743411b3 | 398 | davinci_musb_source_power(musb, 0, 1); |
550a7375 | 399 | |
a227fd7d DB |
400 | /* dm355 EVM swaps D+/D- for signal integrity, and |
401 | * is clocked from the main 24 MHz crystal. | |
402 | */ | |
403 | if (machine_is_davinci_dm355_evm()) { | |
404 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); | |
405 | ||
406 | phy_ctrl &= ~(3 << 9); | |
407 | phy_ctrl |= USBPHY_DATAPOL; | |
408 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
409 | } | |
410 | ||
d163ef24 DB |
411 | /* On dm355, the default-A state machine needs DRVVBUS control. |
412 | * If we won't be a host, there's no need to turn it on. | |
413 | */ | |
414 | if (cpu_is_davinci_dm355()) { | |
415 | u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); | |
416 | ||
032ec49f | 417 | deepsleep &= ~DRVVBUS_FORCE; |
d163ef24 DB |
418 | __raw_writel(deepsleep, DM355_DEEPSLEEP); |
419 | } | |
420 | ||
550a7375 FB |
421 | /* reset the controller */ |
422 | musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1); | |
423 | ||
424 | /* start the on-chip PHY and its PLL */ | |
425 | phy_on(); | |
426 | ||
427 | msleep(5); | |
428 | ||
429 | /* NOTE: irqs are in mixed mode, not bypass to pure-musb */ | |
430 | pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n", | |
a227fd7d | 431 | revision, __raw_readl(USB_PHY_CTRL), |
550a7375 FB |
432 | musb_readb(tibase, DAVINCI_USB_CTRL_REG)); |
433 | ||
743411b3 | 434 | musb->isr = davinci_musb_interrupt; |
550a7375 | 435 | return 0; |
84e250ff DB |
436 | |
437 | fail: | |
721002ec | 438 | usb_put_phy(musb->xceiv); |
c67dd31c | 439 | unregister: |
84e250ff DB |
440 | usb_nop_xceiv_unregister(); |
441 | return -ENODEV; | |
550a7375 FB |
442 | } |
443 | ||
743411b3 | 444 | static int davinci_musb_exit(struct musb *musb) |
550a7375 | 445 | { |
032ec49f | 446 | del_timer_sync(&otg_workaround); |
550a7375 | 447 | |
d163ef24 DB |
448 | /* force VBUS off */ |
449 | if (cpu_is_davinci_dm355()) { | |
450 | u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); | |
451 | ||
452 | deepsleep &= ~DRVVBUS_FORCE; | |
453 | deepsleep |= DRVVBUS_OVERRIDE; | |
454 | __raw_writel(deepsleep, DM355_DEEPSLEEP); | |
455 | } | |
456 | ||
743411b3 | 457 | davinci_musb_source_power(musb, 0 /*off*/, 1); |
550a7375 FB |
458 | |
459 | /* delay, to avoid problems with module reload */ | |
032ec49f | 460 | if (musb->xceiv->otg->default_a) { |
550a7375 FB |
461 | int maxdelay = 30; |
462 | u8 devctl, warn = 0; | |
463 | ||
464 | /* if there's no peripheral connected, this can take a | |
465 | * long time to fall, especially on EVM with huge C133. | |
466 | */ | |
467 | do { | |
468 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
469 | if (!(devctl & MUSB_DEVCTL_VBUS)) | |
470 | break; | |
471 | if ((devctl & MUSB_DEVCTL_VBUS) != warn) { | |
472 | warn = devctl & MUSB_DEVCTL_VBUS; | |
5c8a86e1 | 473 | dev_dbg(musb->controller, "VBUS %d\n", |
550a7375 FB |
474 | warn >> MUSB_DEVCTL_VBUS_SHIFT); |
475 | } | |
476 | msleep(1000); | |
477 | maxdelay--; | |
478 | } while (maxdelay > 0); | |
479 | ||
480 | /* in OTG mode, another host might be connected */ | |
481 | if (devctl & MUSB_DEVCTL_VBUS) | |
5c8a86e1 | 482 | dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl); |
550a7375 FB |
483 | } |
484 | ||
485 | phy_off(); | |
34f32c97 | 486 | |
721002ec | 487 | usb_put_phy(musb->xceiv); |
84e250ff DB |
488 | usb_nop_xceiv_unregister(); |
489 | ||
550a7375 FB |
490 | return 0; |
491 | } | |
743411b3 | 492 | |
f7ec9437 | 493 | static const struct musb_platform_ops davinci_ops = { |
743411b3 FB |
494 | .init = davinci_musb_init, |
495 | .exit = davinci_musb_exit, | |
496 | ||
497 | .enable = davinci_musb_enable, | |
498 | .disable = davinci_musb_disable, | |
499 | ||
500 | .set_mode = davinci_musb_set_mode, | |
501 | ||
502 | .set_vbus = davinci_musb_set_vbus, | |
503 | }; | |
73b089b0 FB |
504 | |
505 | static u64 davinci_dmamask = DMA_BIT_MASK(32); | |
506 | ||
e9e8c85e | 507 | static int __devinit davinci_probe(struct platform_device *pdev) |
73b089b0 FB |
508 | { |
509 | struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; | |
510 | struct platform_device *musb; | |
e110de4d | 511 | struct davinci_glue *glue; |
03491761 | 512 | struct clk *clk; |
73b089b0 FB |
513 | |
514 | int ret = -ENOMEM; | |
515 | ||
e110de4d FB |
516 | glue = kzalloc(sizeof(*glue), GFP_KERNEL); |
517 | if (!glue) { | |
518 | dev_err(&pdev->dev, "failed to allocate glue context\n"); | |
519 | goto err0; | |
520 | } | |
521 | ||
2f771164 | 522 | musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO); |
73b089b0 FB |
523 | if (!musb) { |
524 | dev_err(&pdev->dev, "failed to allocate musb device\n"); | |
2f771164 | 525 | goto err1; |
73b089b0 FB |
526 | } |
527 | ||
03491761 FB |
528 | clk = clk_get(&pdev->dev, "usb"); |
529 | if (IS_ERR(clk)) { | |
530 | dev_err(&pdev->dev, "failed to get clock\n"); | |
531 | ret = PTR_ERR(clk); | |
65b3d52d | 532 | goto err3; |
03491761 FB |
533 | } |
534 | ||
535 | ret = clk_enable(clk); | |
536 | if (ret) { | |
537 | dev_err(&pdev->dev, "failed to enable clock\n"); | |
65b3d52d | 538 | goto err4; |
03491761 FB |
539 | } |
540 | ||
73b089b0 FB |
541 | musb->dev.parent = &pdev->dev; |
542 | musb->dev.dma_mask = &davinci_dmamask; | |
543 | musb->dev.coherent_dma_mask = davinci_dmamask; | |
544 | ||
e110de4d FB |
545 | glue->dev = &pdev->dev; |
546 | glue->musb = musb; | |
03491761 | 547 | glue->clk = clk; |
e110de4d | 548 | |
f7ec9437 FB |
549 | pdata->platform_ops = &davinci_ops; |
550 | ||
e110de4d | 551 | platform_set_drvdata(pdev, glue); |
73b089b0 FB |
552 | |
553 | ret = platform_device_add_resources(musb, pdev->resource, | |
554 | pdev->num_resources); | |
555 | if (ret) { | |
556 | dev_err(&pdev->dev, "failed to add resources\n"); | |
65b3d52d | 557 | goto err5; |
73b089b0 FB |
558 | } |
559 | ||
560 | ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); | |
561 | if (ret) { | |
562 | dev_err(&pdev->dev, "failed to add platform_data\n"); | |
65b3d52d | 563 | goto err5; |
73b089b0 FB |
564 | } |
565 | ||
566 | ret = platform_device_add(musb); | |
567 | if (ret) { | |
568 | dev_err(&pdev->dev, "failed to register musb device\n"); | |
65b3d52d | 569 | goto err5; |
73b089b0 FB |
570 | } |
571 | ||
572 | return 0; | |
573 | ||
65b3d52d | 574 | err5: |
03491761 FB |
575 | clk_disable(clk); |
576 | ||
65b3d52d | 577 | err4: |
03491761 FB |
578 | clk_put(clk); |
579 | ||
65b3d52d | 580 | err3: |
73b089b0 FB |
581 | platform_device_put(musb); |
582 | ||
e110de4d FB |
583 | err1: |
584 | kfree(glue); | |
585 | ||
73b089b0 FB |
586 | err0: |
587 | return ret; | |
588 | } | |
589 | ||
e9e8c85e | 590 | static int __devexit davinci_remove(struct platform_device *pdev) |
73b089b0 | 591 | { |
e110de4d | 592 | struct davinci_glue *glue = platform_get_drvdata(pdev); |
73b089b0 | 593 | |
12a71f5b | 594 | platform_device_unregister(glue->musb); |
03491761 FB |
595 | clk_disable(glue->clk); |
596 | clk_put(glue->clk); | |
e110de4d | 597 | kfree(glue); |
73b089b0 FB |
598 | |
599 | return 0; | |
600 | } | |
601 | ||
602 | static struct platform_driver davinci_driver = { | |
e9e8c85e FB |
603 | .probe = davinci_probe, |
604 | .remove = __devexit_p(davinci_remove), | |
73b089b0 FB |
605 | .driver = { |
606 | .name = "musb-davinci", | |
607 | }, | |
608 | }; | |
609 | ||
610 | MODULE_DESCRIPTION("DaVinci MUSB Glue Layer"); | |
611 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); | |
612 | MODULE_LICENSE("GPL v2"); | |
8d92f6d4 | 613 | module_platform_driver(davinci_driver); |