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550a7375 FB |
1 | /* |
2 | * Copyright (C) 2005-2006 by Texas Instruments | |
3 | * | |
4 | * This file is part of the Inventra Controller Driver for Linux. | |
5 | * | |
6 | * The Inventra Controller Driver for Linux is free software; you | |
7 | * can redistribute it and/or modify it under the terms of the GNU | |
8 | * General Public License version 2 as published by the Free Software | |
9 | * Foundation. | |
10 | * | |
11 | * The Inventra Controller Driver for Linux is distributed in | |
12 | * the hope that it will be useful, but WITHOUT ANY WARRANTY; | |
13 | * without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | * License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with The Inventra Controller Driver for Linux ; if not, | |
19 | * write to the Free Software Foundation, Inc., 59 Temple Place, | |
20 | * Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
550a7375 FB |
27 | #include <linux/init.h> |
28 | #include <linux/list.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/clk.h> | |
31 | #include <linux/io.h> | |
c767c1c6 | 32 | #include <linux/gpio.h> |
73b089b0 FB |
33 | #include <linux/platform_device.h> |
34 | #include <linux/dma-mapping.h> | |
550a7375 | 35 | |
10b4eade DB |
36 | #include <mach/hardware.h> |
37 | #include <mach/memory.h> | |
38 | #include <mach/gpio.h> | |
d163ef24 | 39 | #include <mach/cputype.h> |
10b4eade | 40 | |
550a7375 FB |
41 | #include <asm/mach-types.h> |
42 | ||
43 | #include "musb_core.h" | |
44 | ||
45 | #ifdef CONFIG_MACH_DAVINCI_EVM | |
a2396a32 | 46 | #define GPIO_nVBUS_DRV 160 |
550a7375 FB |
47 | #endif |
48 | ||
49 | #include "davinci.h" | |
50 | #include "cppi_dma.h" | |
51 | ||
52 | ||
a227fd7d DB |
53 | #define USB_PHY_CTRL IO_ADDRESS(USBPHY_CTL_PADDR) |
54 | #define DM355_DEEPSLEEP IO_ADDRESS(DM355_DEEPSLEEP_PADDR) | |
55 | ||
e110de4d FB |
56 | struct davinci_glue { |
57 | struct device *dev; | |
58 | struct platform_device *musb; | |
59 | }; | |
60 | ||
550a7375 FB |
61 | /* REVISIT (PM) we should be able to keep the PHY in low power mode most |
62 | * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0 | |
63 | * and, when in host mode, autosuspending idle root ports... PHYPLLON | |
64 | * (overriding SUSPENDM?) then likely needs to stay off. | |
65 | */ | |
66 | ||
67 | static inline void phy_on(void) | |
68 | { | |
a227fd7d DB |
69 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); |
70 | ||
71 | /* power everything up; start the on-chip PHY and its PLL */ | |
72 | phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN); | |
73 | phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON; | |
74 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
75 | ||
76 | /* wait for PLL to lock before proceeding */ | |
77 | while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0) | |
550a7375 FB |
78 | cpu_relax(); |
79 | } | |
80 | ||
81 | static inline void phy_off(void) | |
82 | { | |
a227fd7d DB |
83 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); |
84 | ||
85 | /* powerdown the on-chip PHY, its PLL, and the OTG block */ | |
86 | phy_ctrl &= ~(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON); | |
87 | phy_ctrl |= USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN; | |
88 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
550a7375 FB |
89 | } |
90 | ||
91 | static int dma_off = 1; | |
92 | ||
743411b3 | 93 | static void davinci_musb_enable(struct musb *musb) |
550a7375 FB |
94 | { |
95 | u32 tmp, old, val; | |
96 | ||
97 | /* workaround: setup irqs through both register sets */ | |
98 | tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK) | |
99 | << DAVINCI_USB_TXINT_SHIFT; | |
100 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
101 | old = tmp; | |
102 | tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK)) | |
103 | << DAVINCI_USB_RXINT_SHIFT; | |
104 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
105 | tmp |= old; | |
106 | ||
107 | val = ~MUSB_INTR_SOF; | |
108 | tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT); | |
109 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp); | |
110 | ||
111 | if (is_dma_capable() && !dma_off) | |
112 | printk(KERN_WARNING "%s %s: dma not reactivated\n", | |
113 | __FILE__, __func__); | |
114 | else | |
115 | dma_off = 0; | |
116 | ||
117 | /* force a DRVVBUS irq so we can start polling for ID change */ | |
118 | if (is_otg_enabled(musb)) | |
119 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, | |
120 | DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT); | |
121 | } | |
122 | ||
123 | /* | |
124 | * Disable the HDRC and flush interrupts | |
125 | */ | |
743411b3 | 126 | static void davinci_musb_disable(struct musb *musb) |
550a7375 FB |
127 | { |
128 | /* because we don't set CTRLR.UINT, "important" to: | |
129 | * - not read/write INTRUSB/INTRUSBE | |
130 | * - (except during initial setup, as workaround) | |
131 | * - use INTSETR/INTCLRR instead | |
132 | */ | |
133 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG, | |
134 | DAVINCI_USB_USBINT_MASK | |
135 | | DAVINCI_USB_TXINT_MASK | |
136 | | DAVINCI_USB_RXINT_MASK); | |
137 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
138 | musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0); | |
139 | ||
140 | if (is_dma_capable() && !dma_off) | |
141 | WARNING("dma still active\n"); | |
142 | } | |
143 | ||
144 | ||
550a7375 FB |
145 | #ifdef CONFIG_USB_MUSB_HDRC_HCD |
146 | #define portstate(stmt) stmt | |
147 | #else | |
148 | #define portstate(stmt) | |
149 | #endif | |
150 | ||
151 | ||
a227fd7d DB |
152 | /* |
153 | * VBUS SWITCHING IS BOARD-SPECIFIC ... at least for the DM6446 EVM, | |
154 | * which doesn't wire DRVVBUS to the FET that switches it. Unclear | |
155 | * if that's a problem with the DM6446 chip or just with that board. | |
156 | * | |
157 | * In either case, the DM355 EVM automates DRVVBUS the normal way, | |
158 | * when J10 is out, and TI documents it as handling OTG. | |
159 | */ | |
550a7375 FB |
160 | |
161 | #ifdef CONFIG_MACH_DAVINCI_EVM | |
550a7375 | 162 | |
a227fd7d DB |
163 | static int vbus_state = -1; |
164 | ||
550a7375 FB |
165 | /* I2C operations are always synchronous, and require a task context. |
166 | * With unloaded systems, using the shared workqueue seems to suffice | |
167 | * to satisfy the 100msec A_WAIT_VRISE timeout... | |
168 | */ | |
169 | static void evm_deferred_drvvbus(struct work_struct *ignored) | |
170 | { | |
c767c1c6 | 171 | gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state); |
550a7375 FB |
172 | vbus_state = !vbus_state; |
173 | } | |
550a7375 | 174 | |
550a7375 FB |
175 | #endif /* EVM */ |
176 | ||
743411b3 | 177 | static void davinci_musb_source_power(struct musb *musb, int is_on, int immediate) |
550a7375 | 178 | { |
a227fd7d | 179 | #ifdef CONFIG_MACH_DAVINCI_EVM |
550a7375 FB |
180 | if (is_on) |
181 | is_on = 1; | |
182 | ||
183 | if (vbus_state == is_on) | |
184 | return; | |
185 | vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */ | |
186 | ||
550a7375 | 187 | if (machine_is_davinci_evm()) { |
a227fd7d DB |
188 | static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus); |
189 | ||
550a7375 | 190 | if (immediate) |
c767c1c6 | 191 | gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state); |
550a7375 FB |
192 | else |
193 | schedule_work(&evm_vbus_work); | |
550a7375 | 194 | } |
550a7375 FB |
195 | if (immediate) |
196 | vbus_state = is_on; | |
a227fd7d | 197 | #endif |
550a7375 FB |
198 | } |
199 | ||
743411b3 | 200 | static void davinci_musb_set_vbus(struct musb *musb, int is_on) |
550a7375 FB |
201 | { |
202 | WARN_ON(is_on && is_peripheral_active(musb)); | |
743411b3 | 203 | davinci_musb_source_power(musb, is_on, 0); |
550a7375 FB |
204 | } |
205 | ||
206 | ||
207 | #define POLL_SECONDS 2 | |
208 | ||
209 | static struct timer_list otg_workaround; | |
210 | ||
211 | static void otg_timer(unsigned long _musb) | |
212 | { | |
213 | struct musb *musb = (void *)_musb; | |
214 | void __iomem *mregs = musb->mregs; | |
215 | u8 devctl; | |
216 | unsigned long flags; | |
217 | ||
218 | /* We poll because DaVinci's won't expose several OTG-critical | |
219 | * status change events (from the transceiver) otherwise. | |
220 | */ | |
221 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
222 | DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb)); | |
223 | ||
224 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 225 | switch (musb->xceiv->state) { |
550a7375 FB |
226 | case OTG_STATE_A_WAIT_VFALL: |
227 | /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL | |
228 | * seems to mis-handle session "start" otherwise (or in our | |
229 | * case "recover"), in routine "VBUS was valid by the time | |
230 | * VBUSERR got reported during enumeration" cases. | |
231 | */ | |
232 | if (devctl & MUSB_DEVCTL_VBUS) { | |
233 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
234 | break; | |
235 | } | |
84e250ff | 236 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; |
550a7375 FB |
237 | musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG, |
238 | MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT); | |
239 | break; | |
240 | case OTG_STATE_B_IDLE: | |
241 | if (!is_peripheral_enabled(musb)) | |
242 | break; | |
243 | ||
244 | /* There's no ID-changed IRQ, so we have no good way to tell | |
245 | * when to switch to the A-Default state machine (by setting | |
246 | * the DEVCTL.SESSION flag). | |
247 | * | |
248 | * Workaround: whenever we're in B_IDLE, try setting the | |
249 | * session flag every few seconds. If it works, ID was | |
250 | * grounded and we're now in the A-Default state machine. | |
251 | * | |
252 | * NOTE setting the session flag is _supposed_ to trigger | |
253 | * SRP, but clearly it doesn't. | |
254 | */ | |
255 | musb_writeb(mregs, MUSB_DEVCTL, | |
256 | devctl | MUSB_DEVCTL_SESSION); | |
257 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
258 | if (devctl & MUSB_DEVCTL_BDEVICE) | |
259 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); | |
260 | else | |
84e250ff | 261 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 FB |
262 | break; |
263 | default: | |
264 | break; | |
265 | } | |
266 | spin_unlock_irqrestore(&musb->lock, flags); | |
267 | } | |
268 | ||
743411b3 | 269 | static irqreturn_t davinci_musb_interrupt(int irq, void *__hci) |
550a7375 FB |
270 | { |
271 | unsigned long flags; | |
272 | irqreturn_t retval = IRQ_NONE; | |
273 | struct musb *musb = __hci; | |
274 | void __iomem *tibase = musb->ctrl_base; | |
91e9c4fe | 275 | struct cppi *cppi; |
550a7375 FB |
276 | u32 tmp; |
277 | ||
278 | spin_lock_irqsave(&musb->lock, flags); | |
279 | ||
280 | /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through | |
281 | * the Mentor registers (except for setup), use the TI ones and EOI. | |
282 | * | |
dfff0615 | 283 | * Docs describe irq "vector" registers associated with the CPPI and |
550a7375 FB |
284 | * USB EOI registers. These hold a bitmask corresponding to the |
285 | * current IRQ, not an irq handler address. Would using those bits | |
286 | * resolve some of the races observed in this dispatch code?? | |
287 | */ | |
288 | ||
289 | /* CPPI interrupts share the same IRQ line, but have their own | |
290 | * mask, state, "vector", and EOI registers. | |
291 | */ | |
91e9c4fe SS |
292 | cppi = container_of(musb->dma_controller, struct cppi, controller); |
293 | if (is_cppi_enabled() && musb->dma_controller && !cppi->irq) | |
294 | retval = cppi_interrupt(irq, __hci); | |
550a7375 FB |
295 | |
296 | /* ack and handle non-CPPI interrupts */ | |
297 | tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG); | |
298 | musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp); | |
299 | DBG(4, "IRQ %08x\n", tmp); | |
300 | ||
301 | musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK) | |
302 | >> DAVINCI_USB_RXINT_SHIFT; | |
303 | musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK) | |
304 | >> DAVINCI_USB_TXINT_SHIFT; | |
305 | musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK) | |
306 | >> DAVINCI_USB_USBINT_SHIFT; | |
307 | ||
308 | /* DRVVBUS irqs are the only proxy we have (a very poor one!) for | |
309 | * DaVinci's missing ID change IRQ. We need an ID change IRQ to | |
310 | * switch appropriately between halves of the OTG state machine. | |
311 | * Managing DEVCTL.SESSION per Mentor docs requires we know its | |
312 | * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set. | |
313 | * Also, DRVVBUS pulses for SRP (but not at 5V) ... | |
314 | */ | |
315 | if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) { | |
316 | int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG); | |
317 | void __iomem *mregs = musb->mregs; | |
318 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
319 | int err = musb->int_usb & MUSB_INTR_VBUSERROR; | |
320 | ||
321 | err = is_host_enabled(musb) | |
322 | && (musb->int_usb & MUSB_INTR_VBUSERROR); | |
323 | if (err) { | |
324 | /* The Mentor core doesn't debounce VBUS as needed | |
325 | * to cope with device connect current spikes. This | |
326 | * means it's not uncommon for bus-powered devices | |
327 | * to get VBUS errors during enumeration. | |
328 | * | |
329 | * This is a workaround, but newer RTL from Mentor | |
330 | * seems to allow a better one: "re"starting sessions | |
331 | * without waiting (on EVM, a **long** time) for VBUS | |
332 | * to stop registering in devctl. | |
333 | */ | |
334 | musb->int_usb &= ~MUSB_INTR_VBUSERROR; | |
84e250ff | 335 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
336 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
337 | WARNING("VBUS error workaround (delay coming)\n"); | |
338 | } else if (is_host_enabled(musb) && drvvbus) { | |
550a7375 | 339 | MUSB_HST_MODE(musb); |
84e250ff DB |
340 | musb->xceiv->default_a = 1; |
341 | musb->xceiv->state = OTG_STATE_A_WAIT_VRISE; | |
550a7375 FB |
342 | portstate(musb->port1_status |= USB_PORT_STAT_POWER); |
343 | del_timer(&otg_workaround); | |
344 | } else { | |
345 | musb->is_active = 0; | |
346 | MUSB_DEV_MODE(musb); | |
84e250ff DB |
347 | musb->xceiv->default_a = 0; |
348 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
550a7375 FB |
349 | portstate(musb->port1_status &= ~USB_PORT_STAT_POWER); |
350 | } | |
351 | ||
89368d3d DB |
352 | /* NOTE: this must complete poweron within 100 msec |
353 | * (OTG_TIME_A_WAIT_VRISE) but we don't check for that. | |
354 | */ | |
743411b3 | 355 | davinci_musb_source_power(musb, drvvbus, 0); |
550a7375 FB |
356 | DBG(2, "VBUS %s (%s)%s, devctl %02x\n", |
357 | drvvbus ? "on" : "off", | |
358 | otg_state_string(musb), | |
359 | err ? " ERROR" : "", | |
360 | devctl); | |
361 | retval = IRQ_HANDLED; | |
362 | } | |
363 | ||
364 | if (musb->int_tx || musb->int_rx || musb->int_usb) | |
365 | retval |= musb_interrupt(musb); | |
366 | ||
367 | /* irq stays asserted until EOI is written */ | |
368 | musb_writel(tibase, DAVINCI_USB_EOI_REG, 0); | |
369 | ||
370 | /* poll for ID change */ | |
371 | if (is_otg_enabled(musb) | |
84e250ff | 372 | && musb->xceiv->state == OTG_STATE_B_IDLE) |
550a7375 FB |
373 | mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ); |
374 | ||
375 | spin_unlock_irqrestore(&musb->lock, flags); | |
376 | ||
a5073b52 | 377 | return retval; |
550a7375 FB |
378 | } |
379 | ||
743411b3 | 380 | static int davinci_musb_set_mode(struct musb *musb, u8 mode) |
96a274d1 DB |
381 | { |
382 | /* EVM can't do this (right?) */ | |
383 | return -EIO; | |
384 | } | |
385 | ||
743411b3 | 386 | static int davinci_musb_init(struct musb *musb) |
550a7375 FB |
387 | { |
388 | void __iomem *tibase = musb->ctrl_base; | |
389 | u32 revision; | |
390 | ||
84e250ff DB |
391 | usb_nop_xceiv_register(); |
392 | musb->xceiv = otg_get_transceiver(); | |
393 | if (!musb->xceiv) | |
394 | return -ENODEV; | |
395 | ||
550a7375 | 396 | musb->mregs += DAVINCI_BASE_OFFSET; |
550a7375 | 397 | |
34f32c97 | 398 | clk_enable(musb->clock); |
550a7375 FB |
399 | |
400 | /* returns zero if e.g. not clocked */ | |
401 | revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG); | |
402 | if (revision == 0) | |
84e250ff | 403 | goto fail; |
550a7375 FB |
404 | |
405 | if (is_host_enabled(musb)) | |
406 | setup_timer(&otg_workaround, otg_timer, (unsigned long) musb); | |
407 | ||
743411b3 FB |
408 | musb->board_set_vbus = davinci_musb_set_vbus; |
409 | davinci_musb_source_power(musb, 0, 1); | |
550a7375 | 410 | |
a227fd7d DB |
411 | /* dm355 EVM swaps D+/D- for signal integrity, and |
412 | * is clocked from the main 24 MHz crystal. | |
413 | */ | |
414 | if (machine_is_davinci_dm355_evm()) { | |
415 | u32 phy_ctrl = __raw_readl(USB_PHY_CTRL); | |
416 | ||
417 | phy_ctrl &= ~(3 << 9); | |
418 | phy_ctrl |= USBPHY_DATAPOL; | |
419 | __raw_writel(phy_ctrl, USB_PHY_CTRL); | |
420 | } | |
421 | ||
d163ef24 DB |
422 | /* On dm355, the default-A state machine needs DRVVBUS control. |
423 | * If we won't be a host, there's no need to turn it on. | |
424 | */ | |
425 | if (cpu_is_davinci_dm355()) { | |
426 | u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); | |
427 | ||
428 | if (is_host_enabled(musb)) { | |
429 | deepsleep &= ~DRVVBUS_OVERRIDE; | |
430 | } else { | |
431 | deepsleep &= ~DRVVBUS_FORCE; | |
432 | deepsleep |= DRVVBUS_OVERRIDE; | |
433 | } | |
434 | __raw_writel(deepsleep, DM355_DEEPSLEEP); | |
435 | } | |
436 | ||
550a7375 FB |
437 | /* reset the controller */ |
438 | musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1); | |
439 | ||
440 | /* start the on-chip PHY and its PLL */ | |
441 | phy_on(); | |
442 | ||
443 | msleep(5); | |
444 | ||
445 | /* NOTE: irqs are in mixed mode, not bypass to pure-musb */ | |
446 | pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n", | |
a227fd7d | 447 | revision, __raw_readl(USB_PHY_CTRL), |
550a7375 FB |
448 | musb_readb(tibase, DAVINCI_USB_CTRL_REG)); |
449 | ||
743411b3 | 450 | musb->isr = davinci_musb_interrupt; |
550a7375 | 451 | return 0; |
84e250ff DB |
452 | |
453 | fail: | |
13962c74 SS |
454 | clk_disable(musb->clock); |
455 | ||
f4053874 | 456 | otg_put_transceiver(musb->xceiv); |
84e250ff DB |
457 | usb_nop_xceiv_unregister(); |
458 | return -ENODEV; | |
550a7375 FB |
459 | } |
460 | ||
743411b3 | 461 | static int davinci_musb_exit(struct musb *musb) |
550a7375 FB |
462 | { |
463 | if (is_host_enabled(musb)) | |
464 | del_timer_sync(&otg_workaround); | |
465 | ||
d163ef24 DB |
466 | /* force VBUS off */ |
467 | if (cpu_is_davinci_dm355()) { | |
468 | u32 deepsleep = __raw_readl(DM355_DEEPSLEEP); | |
469 | ||
470 | deepsleep &= ~DRVVBUS_FORCE; | |
471 | deepsleep |= DRVVBUS_OVERRIDE; | |
472 | __raw_writel(deepsleep, DM355_DEEPSLEEP); | |
473 | } | |
474 | ||
743411b3 | 475 | davinci_musb_source_power(musb, 0 /*off*/, 1); |
550a7375 FB |
476 | |
477 | /* delay, to avoid problems with module reload */ | |
84e250ff | 478 | if (is_host_enabled(musb) && musb->xceiv->default_a) { |
550a7375 FB |
479 | int maxdelay = 30; |
480 | u8 devctl, warn = 0; | |
481 | ||
482 | /* if there's no peripheral connected, this can take a | |
483 | * long time to fall, especially on EVM with huge C133. | |
484 | */ | |
485 | do { | |
486 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
487 | if (!(devctl & MUSB_DEVCTL_VBUS)) | |
488 | break; | |
489 | if ((devctl & MUSB_DEVCTL_VBUS) != warn) { | |
490 | warn = devctl & MUSB_DEVCTL_VBUS; | |
491 | DBG(1, "VBUS %d\n", | |
492 | warn >> MUSB_DEVCTL_VBUS_SHIFT); | |
493 | } | |
494 | msleep(1000); | |
495 | maxdelay--; | |
496 | } while (maxdelay > 0); | |
497 | ||
498 | /* in OTG mode, another host might be connected */ | |
499 | if (devctl & MUSB_DEVCTL_VBUS) | |
500 | DBG(1, "VBUS off timeout (devctl %02x)\n", devctl); | |
501 | } | |
502 | ||
503 | phy_off(); | |
34f32c97 DB |
504 | |
505 | clk_disable(musb->clock); | |
506 | ||
f4053874 | 507 | otg_put_transceiver(musb->xceiv); |
84e250ff DB |
508 | usb_nop_xceiv_unregister(); |
509 | ||
550a7375 FB |
510 | return 0; |
511 | } | |
743411b3 | 512 | |
f7ec9437 | 513 | static const struct musb_platform_ops davinci_ops = { |
743411b3 FB |
514 | .init = davinci_musb_init, |
515 | .exit = davinci_musb_exit, | |
516 | ||
517 | .enable = davinci_musb_enable, | |
518 | .disable = davinci_musb_disable, | |
519 | ||
520 | .set_mode = davinci_musb_set_mode, | |
521 | ||
522 | .set_vbus = davinci_musb_set_vbus, | |
523 | }; | |
73b089b0 FB |
524 | |
525 | static u64 davinci_dmamask = DMA_BIT_MASK(32); | |
526 | ||
527 | static int __init davinci_probe(struct platform_device *pdev) | |
528 | { | |
529 | struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data; | |
530 | struct platform_device *musb; | |
e110de4d | 531 | struct davinci_glue *glue; |
73b089b0 FB |
532 | |
533 | int ret = -ENOMEM; | |
534 | ||
e110de4d FB |
535 | glue = kzalloc(sizeof(*glue), GFP_KERNEL); |
536 | if (!glue) { | |
537 | dev_err(&pdev->dev, "failed to allocate glue context\n"); | |
538 | goto err0; | |
539 | } | |
540 | ||
73b089b0 FB |
541 | musb = platform_device_alloc("musb-hdrc", -1); |
542 | if (!musb) { | |
543 | dev_err(&pdev->dev, "failed to allocate musb device\n"); | |
e110de4d | 544 | goto err1; |
73b089b0 FB |
545 | } |
546 | ||
547 | musb->dev.parent = &pdev->dev; | |
548 | musb->dev.dma_mask = &davinci_dmamask; | |
549 | musb->dev.coherent_dma_mask = davinci_dmamask; | |
550 | ||
e110de4d FB |
551 | glue->dev = &pdev->dev; |
552 | glue->musb = musb; | |
553 | ||
f7ec9437 FB |
554 | pdata->platform_ops = &davinci_ops; |
555 | ||
e110de4d | 556 | platform_set_drvdata(pdev, glue); |
73b089b0 FB |
557 | |
558 | ret = platform_device_add_resources(musb, pdev->resource, | |
559 | pdev->num_resources); | |
560 | if (ret) { | |
561 | dev_err(&pdev->dev, "failed to add resources\n"); | |
e110de4d | 562 | goto err2; |
73b089b0 FB |
563 | } |
564 | ||
565 | ret = platform_device_add_data(musb, pdata, sizeof(*pdata)); | |
566 | if (ret) { | |
567 | dev_err(&pdev->dev, "failed to add platform_data\n"); | |
e110de4d | 568 | goto err2; |
73b089b0 FB |
569 | } |
570 | ||
571 | ret = platform_device_add(musb); | |
572 | if (ret) { | |
573 | dev_err(&pdev->dev, "failed to register musb device\n"); | |
e110de4d | 574 | goto err2; |
73b089b0 FB |
575 | } |
576 | ||
577 | return 0; | |
578 | ||
e110de4d | 579 | err2: |
73b089b0 FB |
580 | platform_device_put(musb); |
581 | ||
e110de4d FB |
582 | err1: |
583 | kfree(glue); | |
584 | ||
73b089b0 FB |
585 | err0: |
586 | return ret; | |
587 | } | |
588 | ||
589 | static int __exit davinci_remove(struct platform_device *pdev) | |
590 | { | |
e110de4d | 591 | struct davinci_glue *glue = platform_get_drvdata(pdev); |
73b089b0 | 592 | |
e110de4d FB |
593 | platform_device_del(glue->musb); |
594 | platform_device_put(glue->musb); | |
595 | kfree(glue); | |
73b089b0 FB |
596 | |
597 | return 0; | |
598 | } | |
599 | ||
600 | static struct platform_driver davinci_driver = { | |
601 | .remove = __exit_p(davinci_remove), | |
602 | .driver = { | |
603 | .name = "musb-davinci", | |
604 | }, | |
605 | }; | |
606 | ||
607 | MODULE_DESCRIPTION("DaVinci MUSB Glue Layer"); | |
608 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); | |
609 | MODULE_LICENSE("GPL v2"); | |
610 | ||
611 | static int __init davinci_init(void) | |
612 | { | |
613 | return platform_driver_probe(&davinci_driver, davinci_probe); | |
614 | } | |
615 | subsys_initcall(davinci_init); | |
616 | ||
617 | static void __exit davinci_exit(void) | |
618 | { | |
619 | platform_driver_unregister(&davinci_driver); | |
620 | } | |
621 | module_exit(davinci_exit); |