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usb: musb: Convert timers to use timer_setup()
[mirror_ubuntu-bionic-kernel.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375 85 * - platform_device for addressing, irq, and platform_data
5ae477b0 86 * - platform_data is mostly for board-specific information
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
550a7375
FB		 96#include <linux/list.h>
97#include <linux/kobject.h>
9303961f 98#include <linux/prefetch.h>
550a7375
FB		 99#include <linux/platform_device.h>
100#include <linux/io.h>
8d2421e6 101#include <linux/dma-mapping.h>
309be239 102#include <linux/usb.h>
830fc64c 103#include <linux/usb/of.h>
550a7375 104
550a7375 105#include "musb_core.h"
c74173fd 106#include "musb_trace.h"
550a7375 107
f7f9d63e 108#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 109
110
550a7375
FB		 111#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
112#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
113
e8164f64 114#define MUSB_VERSION "6.0"
550a7375
FB		 115
116#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
117
05ac10dd 118#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375
FB		 119const char musb_driver_name[] = MUSB_DRIVER_NAME;
120
121MODULE_DESCRIPTION(DRIVER_INFO);
122MODULE_AUTHOR(DRIVER_AUTHOR);
123MODULE_LICENSE("GPL");
124MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
125
126
127/*-------------------------------------------------------------------------*/
128
129static inline struct musb *dev_to_musb(struct device *dev)
130{
550a7375 131 return dev_get_drvdata(dev);
550a7375
FB		 132}
133
830fc64c
PK		 134enum musb_mode musb_get_mode(struct device *dev)
135{
136 enum usb_dr_mode mode;
137
138 mode = usb_get_dr_mode(dev);
139 switch (mode) {
140 case USB_DR_MODE_HOST:
141 return MUSB_HOST;
142 case USB_DR_MODE_PERIPHERAL:
143 return MUSB_PERIPHERAL;
144 case USB_DR_MODE_OTG:
145 case USB_DR_MODE_UNKNOWN:
146 default:
147 return MUSB_OTG;
148 }
149}
150EXPORT_SYMBOL_GPL(musb_get_mode);
151
550a7375
FB		 152/*-------------------------------------------------------------------------*/
153
ffb865b1 154#ifndef CONFIG_BLACKFIN
705e63d2 155static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
ffb865b1 156{
b96d3b08 157 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 158 int i = 0;
159 u8 r;
160 u8 power;
bf070bc1
GI		 161 int ret;
162
163 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 164
165 /* Make sure the transceiver is not in low power mode */
166 power = musb_readb(addr, MUSB_POWER);
167 power &= ~MUSB_POWER_SUSPENDM;
168 musb_writeb(addr, MUSB_POWER, power);
169
170 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
171 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
172 */
173
705e63d2 174 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
ffb865b1
HK		 175 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
176 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
177
178 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
179 & MUSB_ULPI_REG_CMPLT)) {
180 i++;
bf070bc1
GI		 181 if (i == 10000) {
182 ret = -ETIMEDOUT;
183 goto out;
184 }
ffb865b1
HK		 185
186 }
187 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
188 r &= ~MUSB_ULPI_REG_CMPLT;
189 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
190
bf070bc1
GI		 191 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
192
193out:
194 pm_runtime_put(phy->io_dev);
195
196 return ret;
ffb865b1
HK		 197}
198
705e63d2 199static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
ffb865b1 200{
b96d3b08 201 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 202 int i = 0;
203 u8 r = 0;
204 u8 power;
bf070bc1
GI		 205 int ret = 0;
206
207 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 208
209 /* Make sure the transceiver is not in low power mode */
210 power = musb_readb(addr, MUSB_POWER);
211 power &= ~MUSB_POWER_SUSPENDM;
212 musb_writeb(addr, MUSB_POWER, power);
213
705e63d2
UKK		 214 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
215 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
ffb865b1
HK		 216 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
217
218 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
219 & MUSB_ULPI_REG_CMPLT)) {
220 i++;
bf070bc1
GI		 221 if (i == 10000) {
222 ret = -ETIMEDOUT;
223 goto out;
224 }
ffb865b1
HK		 225 }
226
227 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
228 r &= ~MUSB_ULPI_REG_CMPLT;
229 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
230
bf070bc1
GI		 231out:
232 pm_runtime_put(phy->io_dev);
233
234 return ret;
ffb865b1
HK		 235}
236#else
f2263db7
MF		 237#define musb_ulpi_read NULL
238#define musb_ulpi_write NULL
ffb865b1
HK		 239#endif
240
b96d3b08 241static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 242 .read = musb_ulpi_read,
243 .write = musb_ulpi_write,
244};
245
246/*-------------------------------------------------------------------------*/
247
1b40fc57
TL		 248static u32 musb_default_fifo_offset(u8 epnum)
249{
250 return 0x20 + (epnum * 4);
251}
252
d026e9c7
TL		 253/* "flat" mapping: each endpoint has its own i/o address */
254static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
255{
256}
257
258static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
259{
260 return 0x100 + (0x10 * epnum) + offset;
261}
262
263/* "indexed" mapping: INDEX register controls register bank select */
264static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
265{
266 musb_writeb(mbase, MUSB_INDEX, epnum);
267}
268
269static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
270{
271 return 0x10 + offset;
272}
273
6cc2af6d
HG		 274static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
275{
276 return 0x80 + (0x08 * epnum) + offset;
277}
278
1b40fc57
TL		 279static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
280{
c74173fd
BL		 281 u8 data = __raw_readb(addr + offset);
282
283 trace_musb_readb(__builtin_return_address(0), addr, offset, data);
284 return data;
1b40fc57
TL		 285}
286
287static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
288{
c74173fd 289 trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 290 __raw_writeb(data, addr + offset);
291}
292
293static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
294{
c74173fd
BL		 295 u16 data = __raw_readw(addr + offset);
296
297 trace_musb_readw(__builtin_return_address(0), addr, offset, data);
298 return data;
1b40fc57
TL		 299}
300
301static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
302{
c74173fd 303 trace_musb_writew(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 304 __raw_writew(data, addr + offset);
305}
306
307static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
308{
c74173fd
BL		 309 u32 data = __raw_readl(addr + offset);
310
311 trace_musb_readl(__builtin_return_address(0), addr, offset, data);
312 return data;
1b40fc57
TL		 313}
314
315static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
316{
c74173fd 317 trace_musb_writel(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 318 __raw_writel(data, addr + offset);
319}
c6cf8b00 320
550a7375
FB		 321/*
322 * Load an endpoint's FIFO
323 */
1b40fc57
TL		 324static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
325 const u8 *src)
550a7375 326{
5c8a86e1 327 struct musb *musb = hw_ep->musb;
550a7375
FB		 328 void __iomem *fifo = hw_ep->fifo;
329
603fe2b2
AKG		 330 if (unlikely(len == 0))
331 return;
332
550a7375
FB		 333 prefetch((u8 *)src);
334
5c8a86e1 335 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 336 'T', hw_ep->epnum, fifo, len, src);
337
338 /* we can't assume unaligned reads work */
339 if (likely((0x01 & (unsigned long) src) == 0)) {
340 u16 index = 0;
341
342 /* best case is 32bit-aligned source address */
343 if ((0x02 & (unsigned long) src) == 0) {
344 if (len >= 4) {
2bf0a8f6 345 iowrite32_rep(fifo, src + index, len >> 2);
550a7375
FB		 346 index += len & ~0x03;
347 }
348 if (len & 0x02) {
be780381 349 __raw_writew(*(u16 *)&src[index], fifo);
550a7375
FB		 350 index += 2;
351 }
352 } else {
353 if (len >= 2) {
2bf0a8f6 354 iowrite16_rep(fifo, src + index, len >> 1);
550a7375
FB		 355 index += len & ~0x01;
356 }
357 }
358 if (len & 0x01)
be780381 359 __raw_writeb(src[index], fifo);
550a7375
FB		 360 } else {
361 /* byte aligned */
2bf0a8f6 362 iowrite8_rep(fifo, src, len);
550a7375
FB		 363 }
364}
365
366/*
367 * Unload an endpoint's FIFO
368 */
1b40fc57 369static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
550a7375 370{
5c8a86e1 371 struct musb *musb = hw_ep->musb;
550a7375
FB		 372 void __iomem *fifo = hw_ep->fifo;
373
603fe2b2
AKG		 374 if (unlikely(len == 0))
375 return;
376
5c8a86e1 377 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 378 'R', hw_ep->epnum, fifo, len, dst);
379
380 /* we can't assume unaligned writes work */
381 if (likely((0x01 & (unsigned long) dst) == 0)) {
382 u16 index = 0;
383
384 /* best case is 32bit-aligned destination address */
385 if ((0x02 & (unsigned long) dst) == 0) {
386 if (len >= 4) {
2bf0a8f6 387 ioread32_rep(fifo, dst, len >> 2);
550a7375
FB		 388 index = len & ~0x03;
389 }
390 if (len & 0x02) {
be780381 391 *(u16 *)&dst[index] = __raw_readw(fifo);
550a7375
FB		 392 index += 2;
393 }
394 } else {
395 if (len >= 2) {
2bf0a8f6 396 ioread16_rep(fifo, dst, len >> 1);
550a7375
FB		 397 index = len & ~0x01;
398 }
399 }
400 if (len & 0x01)
be780381 401 dst[index] = __raw_readb(fifo);
550a7375
FB		 402 } else {
403 /* byte aligned */
2bf0a8f6 404 ioread8_rep(fifo, dst, len);
550a7375
FB		 405 }
406}
407
1b40fc57
TL		 408/*
409 * Old style IO functions
410 */
411u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
412EXPORT_SYMBOL_GPL(musb_readb);
413
414void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
415EXPORT_SYMBOL_GPL(musb_writeb);
550a7375 416
1b40fc57
TL		 417u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
418EXPORT_SYMBOL_GPL(musb_readw);
419
420void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
421EXPORT_SYMBOL_GPL(musb_writew);
422
423u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
424EXPORT_SYMBOL_GPL(musb_readl);
425
426void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
427EXPORT_SYMBOL_GPL(musb_writel);
428
7f6283ed
TL		 429#ifndef CONFIG_MUSB_PIO_ONLY
430struct dma_controller *
431(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
432EXPORT_SYMBOL(musb_dma_controller_create);
433
434void (*musb_dma_controller_destroy)(struct dma_controller *c);
435EXPORT_SYMBOL(musb_dma_controller_destroy);
436#endif
437
1b40fc57
TL		 438/*
439 * New style IO functions
440 */
441void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
442{
443 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
444}
445
446void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
447{
448 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
449}
550a7375
FB		 450
451/*-------------------------------------------------------------------------*/
452
453/* for high speed test mode; see USB 2.0 spec 7.1.20 */
454static const u8 musb_test_packet[53] = {
455 /* implicit SYNC then DATA0 to start */
456
457 /* JKJKJKJK x9 */
458 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
459 /* JJKKJJKK x8 */
460 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
461 /* JJJJKKKK x8 */
462 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
463 /* JJJJJJJKKKKKKK x8 */
464 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
465 /* JJJJJJJK x8 */
466 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
467 /* JKKKKKKK x10, JK */
468 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
469
470 /* implicit CRC16 then EOP to end */
471};
472
473void musb_load_testpacket(struct musb *musb)
474{
475 void __iomem *regs = musb->endpoints[0].regs;
476
477 musb_ep_select(musb->mregs, 0);
478 musb_write_fifo(musb->control_ep,
479 sizeof(musb_test_packet), musb_test_packet);
480 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
481}
482
483/*-------------------------------------------------------------------------*/
484
550a7375
FB		 485/*
486 * Handles OTG hnp timeouts, such as b_ase0_brst
487 */
05678497 488static void musb_otg_timer_func(struct timer_list *t)
550a7375 489{
05678497 490 struct musb *musb = from_timer(musb, t, otg_timer);
550a7375
FB		 491 unsigned long flags;
492
493 spin_lock_irqsave(&musb->lock, flags);
e47d9254 494 switch (musb->xceiv->otg->state) {
550a7375 495 case OTG_STATE_B_WAIT_ACON:
b99d3659
BL		 496 musb_dbg(musb,
497 "HNP: b_wait_acon timeout; back to b_peripheral");
550a7375 498 musb_g_disconnect(musb);
e47d9254 499 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 500 musb->is_active = 0;
501 break;
ab983f2a 502 case OTG_STATE_A_SUSPEND:
550a7375 503 case OTG_STATE_A_WAIT_BCON:
b99d3659 504 musb_dbg(musb, "HNP: %s timeout",
e47d9254 505 usb_otg_state_string(musb->xceiv->otg->state));
743411b3 506 musb_platform_set_vbus(musb, 0);
e47d9254 507 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 508 break;
509 default:
b99d3659 510 musb_dbg(musb, "HNP: Unhandled mode %s",
e47d9254 511 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 512 }
550a7375
FB		 513 spin_unlock_irqrestore(&musb->lock, flags);
514}
515
550a7375 516/*
f7f9d63e 517 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 518 */
519void musb_hnp_stop(struct musb *musb)
520{
8b125df5 521 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 522 void __iomem *mbase = musb->mregs;
523 u8 reg;
524
b99d3659 525 musb_dbg(musb, "HNP: stop from %s",
e47d9254 526 usb_otg_state_string(musb->xceiv->otg->state));
ab983f2a 527
e47d9254 528 switch (musb->xceiv->otg->state) {
550a7375 529 case OTG_STATE_A_PERIPHERAL:
550a7375 530 musb_g_disconnect(musb);
b99d3659 531 musb_dbg(musb, "HNP: back to %s",
e47d9254 532 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 533 break;
534 case OTG_STATE_B_HOST:
b99d3659 535 musb_dbg(musb, "HNP: Disabling HR");
74c2e936
DM		 536 if (hcd)
537 hcd->self.is_b_host = 0;
e47d9254 538 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 539 MUSB_DEV_MODE(musb);
540 reg = musb_readb(mbase, MUSB_POWER);
541 reg |= MUSB_POWER_SUSPENDM;
542 musb_writeb(mbase, MUSB_POWER, reg);
543 /* REVISIT: Start SESSION_REQUEST here? */
544 break;
545 default:
b99d3659 546 musb_dbg(musb, "HNP: Stopping in unknown state %s",
e47d9254 547 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 548 }
549
550 /*
551 * When returning to A state after HNP, avoid hub_port_rebounce(),
552 * which cause occasional OPT A "Did not receive reset after connect"
553 * errors.
554 */
749da5f8 555 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 556}
557
83b8f5b8 558static void musb_recover_from_babble(struct musb *musb);
e1eb3eb8 559
550a7375
FB		 560/*
561 * Interrupt Service Routine to record USB "global" interrupts.
562 * Since these do not happen often and signify things of
563 * paramount importance, it seems OK to check them individually;
564 * the order of the tests is specified in the manual
565 *
566 * @param musb instance pointer
567 * @param int_usb register contents
568 * @param devctl
569 * @param power
570 */
571
550a7375 572static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 573 u8 devctl)
550a7375
FB		 574{
575 irqreturn_t handled = IRQ_NONE;
550a7375 576
b99d3659 577 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
550a7375
FB		 578
579 /* in host mode, the peripheral may issue remote wakeup.
580 * in peripheral mode, the host may resume the link.
581 * spurious RESUME irqs happen too, paired with SUSPEND.
582 */
583 if (int_usb & MUSB_INTR_RESUME) {
584 handled = IRQ_HANDLED;
b99d3659 585 musb_dbg(musb, "RESUME (%s)",
0acff6b8 586 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 587
588 if (devctl & MUSB_DEVCTL_HM) {
e47d9254 589 switch (musb->xceiv->otg->state) {
550a7375 590 case OTG_STATE_A_SUSPEND:
65322797 591 /* remote wakeup? */
550a7375
FB		 592 musb->port1_status |=
593 (USB_PORT_STAT_C_SUSPEND << 16)
594 | MUSB_PORT_STAT_RESUME;
30d361bf 595 musb->rh_timer = jiffies
309be239 596 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
e47d9254 597 musb->xceiv->otg->state = OTG_STATE_A_HOST;
550a7375 598 musb->is_active = 1;
9298b4aa 599 musb_host_resume_root_hub(musb);
407788b5
TL		 600 schedule_delayed_work(&musb->finish_resume_work,
601 msecs_to_jiffies(USB_RESUME_TIMEOUT));
550a7375
FB		 602 break;
603 case OTG_STATE_B_WAIT_ACON:
e47d9254 604 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 605 musb->is_active = 1;
606 MUSB_DEV_MODE(musb);
607 break;
608 default:
609 WARNING("bogus %s RESUME (%s)\n",
610 "host",
e47d9254 611 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 612 }
550a7375 613 } else {
e47d9254 614 switch (musb->xceiv->otg->state) {
550a7375
FB		 615 case OTG_STATE_A_SUSPEND:
616 /* possibly DISCONNECT is upcoming */
e47d9254 617 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44 618 musb_host_resume_root_hub(musb);
550a7375 619 break;
550a7375
FB		 620 case OTG_STATE_B_WAIT_ACON:
621 case OTG_STATE_B_PERIPHERAL:
622 /* disconnect while suspended? we may
623 * not get a disconnect irq...
624 */
625 if ((devctl & MUSB_DEVCTL_VBUS)
626 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
627 ) {
628 musb->int_usb |= MUSB_INTR_DISCONNECT;
629 musb->int_usb &= ~MUSB_INTR_SUSPEND;
630 break;
631 }
632 musb_g_resume(musb);
633 break;
634 case OTG_STATE_B_IDLE:
635 musb->int_usb &= ~MUSB_INTR_SUSPEND;
636 break;
550a7375
FB		 637 default:
638 WARNING("bogus %s RESUME (%s)\n",
639 "peripheral",
e47d9254 640 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 641 }
642 }
643 }
644
550a7375
FB		 645 /* see manual for the order of the tests */
646 if (int_usb & MUSB_INTR_SESSREQ) {
aa471456
FB		 647 void __iomem *mbase = musb->mregs;
648
19aab56c
HK		 649 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
650 && (devctl & MUSB_DEVCTL_BDEVICE)) {
b99d3659 651 musb_dbg(musb, "SessReq while on B state");
a6038ee7
HK		 652 return IRQ_HANDLED;
653 }
654
b99d3659 655 musb_dbg(musb, "SESSION_REQUEST (%s)",
e47d9254 656 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 657
658 /* IRQ arrives from ID pin sense or (later, if VBUS power
659 * is removed) SRP. responses are time critical:
660 * - turn on VBUS (with silicon-specific mechanism)
661 * - go through A_WAIT_VRISE
662 * - ... to A_WAIT_BCON.
663 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
664 */
665 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
666 musb->ep0_stage = MUSB_EP0_START;
e47d9254 667 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
550a7375 668 MUSB_HST_MODE(musb);
743411b3 669 musb_platform_set_vbus(musb, 1);
550a7375
FB		 670
671 handled = IRQ_HANDLED;
672 }
673
674 if (int_usb & MUSB_INTR_VBUSERROR) {
675 int ignore = 0;
676
677 /* During connection as an A-Device, we may see a short
678 * current spikes causing voltage drop, because of cable
679 * and peripheral capacitance combined with vbus draw.
680 * (So: less common with truly self-powered devices, where
681 * vbus doesn't act like a power supply.)
682 *
683 * Such spikes are short; usually less than ~500 usec, max
684 * of ~2 msec. That is, they're not sustained overcurrent
685 * errors, though they're reported using VBUSERROR irqs.
686 *
687 * Workarounds: (a) hardware: use self powered devices.
688 * (b) software: ignore non-repeated VBUS errors.
689 *
690 * REVISIT: do delays from lots of DEBUG_KERNEL checks
691 * make trouble here, keeping VBUS < 4.4V ?
692 */
e47d9254 693 switch (musb->xceiv->otg->state) {
550a7375
FB		 694 case OTG_STATE_A_HOST:
695 /* recovery is dicey once we've gotten past the
696 * initial stages of enumeration, but if VBUS
697 * stayed ok at the other end of the link, and
698 * another reset is due (at least for high speed,
699 * to redo the chirp etc), it might work OK...
700 */
701 case OTG_STATE_A_WAIT_BCON:
702 case OTG_STATE_A_WAIT_VRISE:
703 if (musb->vbuserr_retry) {
aa471456
FB		 704 void __iomem *mbase = musb->mregs;
705
550a7375
FB		 706 musb->vbuserr_retry--;
707 ignore = 1;
708 devctl |= MUSB_DEVCTL_SESSION;
709 musb_writeb(mbase, MUSB_DEVCTL, devctl);
710 } else {
711 musb->port1_status |=
749da5f8
AS		 712 USB_PORT_STAT_OVERCURRENT
713 | (USB_PORT_STAT_C_OVERCURRENT << 16);
550a7375
FB		 714 }
715 break;
716 default:
717 break;
718 }
719
54485116
GI		 720 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
721 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
e47d9254 722 usb_otg_state_string(musb->xceiv->otg->state),
550a7375
FB		 723 devctl,
724 ({ char *s;
725 switch (devctl & MUSB_DEVCTL_VBUS) {
726 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
727 s = "<SessEnd"; break;
728 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
729 s = "<AValid"; break;
730 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
731 s = "<VBusValid"; break;
732 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
733 default:
734 s = "VALID"; break;
2b84f92b 735 } s; }),
550a7375
FB		 736 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
737 musb->port1_status);
738
739 /* go through A_WAIT_VFALL then start a new session */
740 if (!ignore)
743411b3 741 musb_platform_set_vbus(musb, 0);
550a7375
FB		 742 handled = IRQ_HANDLED;
743 }
744
1c25fda4 745 if (int_usb & MUSB_INTR_SUSPEND) {
b99d3659 746 musb_dbg(musb, "SUSPEND (%s) devctl %02x",
e47d9254 747 usb_otg_state_string(musb->xceiv->otg->state), devctl);
1c25fda4
AM		 748 handled = IRQ_HANDLED;
749
e47d9254 750 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 751 case OTG_STATE_A_PERIPHERAL:
752 /* We also come here if the cable is removed, since
753 * this silicon doesn't report ID-no-longer-grounded.
754 *
755 * We depend on T(a_wait_bcon) to shut us down, and
756 * hope users don't do anything dicey during this
757 * undesired detour through A_WAIT_BCON.
758 */
759 musb_hnp_stop(musb);
0b3eba44 760 musb_host_resume_root_hub(musb);
1c25fda4
AM		 761 musb_root_disconnect(musb);
762 musb_platform_try_idle(musb, jiffies
763 + msecs_to_jiffies(musb->a_wait_bcon
764 ? : OTG_TIME_A_WAIT_BCON));
765
766 break;
1c25fda4
AM		 767 case OTG_STATE_B_IDLE:
768 if (!musb->is_active)
769 break;
0c636364 770 /* fall through */
1c25fda4
AM		 771 case OTG_STATE_B_PERIPHERAL:
772 musb_g_suspend(musb);
eee3f15d 773 musb->is_active = musb->g.b_hnp_enable;
1c25fda4 774 if (musb->is_active) {
e47d9254 775 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
b99d3659 776 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
1c25fda4
AM		 777 mod_timer(&musb->otg_timer, jiffies
778 + msecs_to_jiffies(
779 OTG_TIME_B_ASE0_BRST));
1c25fda4
AM		 780 }
781 break;
782 case OTG_STATE_A_WAIT_BCON:
783 if (musb->a_wait_bcon != 0)
784 musb_platform_try_idle(musb, jiffies
785 + msecs_to_jiffies(musb->a_wait_bcon));
786 break;
787 case OTG_STATE_A_HOST:
e47d9254 788 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
eee3f15d 789 musb->is_active = musb->hcd->self.b_hnp_enable;
1c25fda4
AM		 790 break;
791 case OTG_STATE_B_HOST:
792 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
b99d3659 793 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
1c25fda4
AM		 794 break;
795 default:
796 /* "should not happen" */
797 musb->is_active = 0;
798 break;
799 }
800 }
801
550a7375 802 if (int_usb & MUSB_INTR_CONNECT) {
8b125df5 803 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 804
805 handled = IRQ_HANDLED;
806 musb->is_active = 1;
550a7375
FB		 807
808 musb->ep0_stage = MUSB_EP0_START;
809
b18d26f6
SAS		 810 musb->intrtxe = musb->epmask;
811 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
af5ec14d
SAS		 812 musb->intrrxe = musb->epmask & 0xfffe;
813 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
d709d22e 814 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 815 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
816 |USB_PORT_STAT_HIGH_SPEED
817 |USB_PORT_STAT_ENABLE
818 );
819 musb->port1_status |= USB_PORT_STAT_CONNECTION
820 |(USB_PORT_STAT_C_CONNECTION << 16);
821
822 /* high vs full speed is just a guess until after reset */
823 if (devctl & MUSB_DEVCTL_LSDEV)
824 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
825
550a7375 826 /* indicate new connection to OTG machine */
e47d9254 827 switch (musb->xceiv->otg->state) {
550a7375
FB		 828 case OTG_STATE_B_PERIPHERAL:
829 if (int_usb & MUSB_INTR_SUSPEND) {
b99d3659 830 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
550a7375 831 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 832 goto b_host;
550a7375 833 } else
b99d3659 834 musb_dbg(musb, "CONNECT as b_peripheral???");
550a7375
FB		 835 break;
836 case OTG_STATE_B_WAIT_ACON:
b99d3659 837 musb_dbg(musb, "HNP: CONNECT, now b_host");
1de00dae 838b_host:
e47d9254 839 musb->xceiv->otg->state = OTG_STATE_B_HOST;
74c2e936
DM		 840 if (musb->hcd)
841 musb->hcd->self.is_b_host = 1;
1de00dae 842 del_timer(&musb->otg_timer);
550a7375
FB		 843 break;
844 default:
845 if ((devctl & MUSB_DEVCTL_VBUS)
846 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
e47d9254 847 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44
DM		 848 if (hcd)
849 hcd->self.is_b_host = 0;
550a7375
FB		 850 }
851 break;
852 }
1de00dae 853
0b3eba44 854 musb_host_poke_root_hub(musb);
1de00dae 855
b99d3659 856 musb_dbg(musb, "CONNECT (%s) devctl %02x",
e47d9254 857 usb_otg_state_string(musb->xceiv->otg->state), devctl);
550a7375 858 }
550a7375 859
6d349671 860 if (int_usb & MUSB_INTR_DISCONNECT) {
b99d3659 861 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
e47d9254 862 usb_otg_state_string(musb->xceiv->otg->state),
1c25fda4
AM		 863 MUSB_MODE(musb), devctl);
864 handled = IRQ_HANDLED;
865
e47d9254 866 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 867 case OTG_STATE_A_HOST:
868 case OTG_STATE_A_SUSPEND:
0b3eba44 869 musb_host_resume_root_hub(musb);
1c25fda4 870 musb_root_disconnect(musb);
032ec49f 871 if (musb->a_wait_bcon != 0)
1c25fda4
AM		 872 musb_platform_try_idle(musb, jiffies
873 + msecs_to_jiffies(musb->a_wait_bcon));
874 break;
1c25fda4
AM		 875 case OTG_STATE_B_HOST:
876 /* REVISIT this behaves for "real disconnect"
877 * cases; make sure the other transitions from
878 * from B_HOST act right too. The B_HOST code
879 * in hnp_stop() is currently not used...
880 */
881 musb_root_disconnect(musb);
74c2e936
DM		 882 if (musb->hcd)
883 musb->hcd->self.is_b_host = 0;
e47d9254 884 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1c25fda4
AM		 885 MUSB_DEV_MODE(musb);
886 musb_g_disconnect(musb);
887 break;
888 case OTG_STATE_A_PERIPHERAL:
889 musb_hnp_stop(musb);
890 musb_root_disconnect(musb);
891 /* FALLTHROUGH */
892 case OTG_STATE_B_WAIT_ACON:
893 /* FALLTHROUGH */
1c25fda4
AM		 894 case OTG_STATE_B_PERIPHERAL:
895 case OTG_STATE_B_IDLE:
896 musb_g_disconnect(musb);
897 break;
1c25fda4
AM		 898 default:
899 WARNING("unhandled DISCONNECT transition (%s)\n",
e47d9254 900 usb_otg_state_string(musb->xceiv->otg->state));
1c25fda4
AM		 901 break;
902 }
903 }
904
550a7375
FB		 905 /* mentor saves a bit: bus reset and babble share the same irq.
906 * only host sees babble; only peripheral sees bus reset.
907 */
908 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 909 handled = IRQ_HANDLED;
445ef615 910 if (is_host_active(musb)) {
550a7375 911 /*
34754dec 912 * When BABBLE happens what we can depends on which
28378d5e
FB		 913 * platform MUSB is running, because some platforms
914 * implemented proprietary means for 'recovering' from
915 * Babble conditions. One such platform is AM335x. In
34754dec
FB		 916 * most cases, however, the only thing we can do is
917 * drop the session.
550a7375 918 */
34754dec 919 dev_err(musb->controller, "Babble\n");
445ef615 920 musb_recover_from_babble(musb);
a04d46d0 921 } else {
b99d3659 922 musb_dbg(musb, "BUS RESET as %s",
e47d9254
AT		 923 usb_otg_state_string(musb->xceiv->otg->state));
924 switch (musb->xceiv->otg->state) {
550a7375 925 case OTG_STATE_A_SUSPEND:
550a7375
FB		 926 musb_g_reset(musb);
927 /* FALLTHROUGH */
928 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e 929 /* never use invalid T(a_wait_bcon) */
b99d3659 930 musb_dbg(musb, "HNP: in %s, %d msec timeout",
e47d9254 931 usb_otg_state_string(musb->xceiv->otg->state),
3df00453 932 TA_WAIT_BCON(musb));
f7f9d63e
DB		 933 mod_timer(&musb->otg_timer, jiffies
934 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 935 break;
936 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 937 del_timer(&musb->otg_timer);
938 musb_g_reset(musb);
550a7375
FB		 939 break;
940 case OTG_STATE_B_WAIT_ACON:
b99d3659 941 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
e47d9254
AT		 942 usb_otg_state_string(musb->xceiv->otg->state));
943 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 944 musb_g_reset(musb);
945 break;
550a7375 946 case OTG_STATE_B_IDLE:
e47d9254 947 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 948 /* FALLTHROUGH */
949 case OTG_STATE_B_PERIPHERAL:
950 musb_g_reset(musb);
951 break;
952 default:
b99d3659 953 musb_dbg(musb, "Unhandled BUS RESET as %s",
e47d9254 954 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 955 }
956 }
550a7375 957 }
550a7375
FB		 958
959#if 0
960/* REVISIT ... this would be for multiplexing periodic endpoints, or
961 * supporting transfer phasing to prevent exceeding ISO bandwidth
962 * limits of a given frame or microframe.
963 *
964 * It's not needed for peripheral side, which dedicates endpoints;
965 * though it _might_ use SOF irqs for other purposes.
966 *
967 * And it's not currently needed for host side, which also dedicates
968 * endpoints, relies on TX/RX interval registers, and isn't claimed
969 * to support ISO transfers yet.
970 */
971 if (int_usb & MUSB_INTR_SOF) {
972 void __iomem *mbase = musb->mregs;
973 struct musb_hw_ep *ep;
974 u8 epnum;
975 u16 frame;
976
5c8a86e1 977 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 978 handled = IRQ_HANDLED;
979
980 /* start any periodic Tx transfers waiting for current frame */
981 frame = musb_readw(mbase, MUSB_FRAME);
982 ep = musb->endpoints;
983 for (epnum = 1; (epnum < musb->nr_endpoints)
984 && (musb->epmask >= (1 << epnum));
985 epnum++, ep++) {
986 /*
987 * FIXME handle framecounter wraps (12 bits)
988 * eliminate duplicated StartUrb logic
989 */
990 if (ep->dwWaitFrame >= frame) {
991 ep->dwWaitFrame = 0;
992 pr_debug("SOF --> periodic TX%s on %d\n",
993 ep->tx_channel ? " DMA" : "",
994 epnum);
995 if (!ep->tx_channel)
996 musb_h_tx_start(musb, epnum);
997 else
998 cppi_hostdma_start(musb, epnum);
999 }
1000 } /* end of for loop */
1001 }
1002#endif
1003
2bff3916 1004 schedule_delayed_work(&musb->irq_work, 0);
550a7375
FB		 1005
1006 return handled;
1007}
1008
1009/*-------------------------------------------------------------------------*/
1010
e1eb3eb8 1011static void musb_disable_interrupts(struct musb *musb)
550a7375
FB		 1012{
1013 void __iomem *mbase = musb->mregs;
1014 u16 temp;
1015
1016 /* disable interrupts */
1017 musb_writeb(mbase, MUSB_INTRUSBE, 0);
b18d26f6 1018 musb->intrtxe = 0;
550a7375 1019 musb_writew(mbase, MUSB_INTRTXE, 0);
af5ec14d 1020 musb->intrrxe = 0;
550a7375
FB		 1021 musb_writew(mbase, MUSB_INTRRXE, 0);
1022
550a7375
FB		 1023 /* flush pending interrupts */
1024 temp = musb_readb(mbase, MUSB_INTRUSB);
1025 temp = musb_readw(mbase, MUSB_INTRTX);
1026 temp = musb_readw(mbase, MUSB_INTRRX);
e1eb3eb8
FB		 1027}
1028
1029static void musb_enable_interrupts(struct musb *musb)
1030{
1031 void __iomem *regs = musb->mregs;
1032
1033 /* Set INT enable registers, enable interrupts */
1034 musb->intrtxe = musb->epmask;
1035 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1036 musb->intrrxe = musb->epmask & 0xfffe;
1037 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1038 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 1039
1040}
1041
001dd84a
SAS		 1042/*
1043 * Program the HDRC to start (enable interrupts, dma, etc.).
1044 */
1045void musb_start(struct musb *musb)
1046{
1047 void __iomem *regs = musb->mregs;
1048 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
9b753764 1049 u8 power;
001dd84a 1050
b99d3659 1051 musb_dbg(musb, "<== devctl %02x", devctl);
001dd84a 1052
e1eb3eb8 1053 musb_enable_interrupts(musb);
001dd84a
SAS		 1054 musb_writeb(regs, MUSB_TESTMODE, 0);
1055
9b753764
BL		 1056 power = MUSB_POWER_ISOUPDATE;
1057 /*
1058 * treating UNKNOWN as unspecified maximum speed, in which case
1059 * we will default to high-speed.
1060 */
1061 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1062 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1063 power |= MUSB_POWER_HSENAB;
1064 musb_writeb(regs, MUSB_POWER, power);
001dd84a
SAS		 1065
1066 musb->is_active = 0;
1067 devctl = musb_readb(regs, MUSB_DEVCTL);
1068 devctl &= ~MUSB_DEVCTL_SESSION;
1069
1070 /* session started after:
1071 * (a) ID-grounded irq, host mode;
1072 * (b) vbus present/connect IRQ, peripheral mode;
1073 * (c) peripheral initiates, using SRP
1074 */
1075 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
40af177e 1076 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
001dd84a
SAS		 1077 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1078 musb->is_active = 1;
1079 } else {
1080 devctl |= MUSB_DEVCTL_SESSION;
1081 }
1082
1083 musb_platform_enable(musb);
1084 musb_writeb(regs, MUSB_DEVCTL, devctl);
1085}
1086
550a7375
FB		 1087/*
1088 * Make the HDRC stop (disable interrupts, etc.);
1089 * reversible by musb_start
1090 * called on gadget driver unregister
1091 * with controller locked, irqs blocked
1092 * acts as a NOP unless some role activated the hardware
1093 */
1094void musb_stop(struct musb *musb)
1095{
1096 /* stop IRQs, timers, ... */
1097 musb_platform_disable(musb);
e945953d
BL		 1098 musb_disable_interrupts(musb);
1099 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
550a7375
FB		 1100
1101 /* FIXME
1102 * - mark host and/or peripheral drivers unusable/inactive
1103 * - disable DMA (and enable it in HdrcStart)
1104 * - make sure we can musb_start() after musb_stop(); with
1105 * OTG mode, gadget driver module rmmod/modprobe cycles that
1106 * - ...
1107 */
1108 musb_platform_try_idle(musb, 0);
1109}
1110
550a7375
FB		 1111/*-------------------------------------------------------------------------*/
1112
1113/*
1114 * The silicon either has hard-wired endpoint configurations, or else
1115 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1116 * writing only the dynamic sizing is very well tested. Since we switched
1117 * away from compile-time hardware parameters, we can no longer rely on
1118 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1119 *
1120 * We don't currently use dynamic fifo setup capability to do anything
1121 * more than selecting one of a bunch of predefined configurations.
1122 */
8a77f05a 1123static ushort fifo_mode;
550a7375
FB		 1124
1125/* "modprobe ... fifo_mode=1" etc */
1126module_param(fifo_mode, ushort, 0);
1127MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1128
550a7375
FB		 1129/*
1130 * tables defining fifo_mode values. define more if you like.
1131 * for host side, make sure both halves of ep1 are set up.
1132 */
1133
1134/* mode 0 - fits in 2KB */
d3608b6d 1135static struct musb_fifo_cfg mode_0_cfg[] = {
550a7375
FB		 1136{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1137{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1138{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1139{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1140{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1141};
1142
1143/* mode 1 - fits in 4KB */
d3608b6d 1144static struct musb_fifo_cfg mode_1_cfg[] = {
550a7375
FB		 1145{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1146{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1147{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1148{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1149{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1150};
1151
1152/* mode 2 - fits in 4KB */
d3608b6d 1153static struct musb_fifo_cfg mode_2_cfg[] = {
550a7375
FB		 1154{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1155{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1156{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1157{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
55aad53f
BL		 1158{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, },
1159{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, },
550a7375
FB		 1160};
1161
1162/* mode 3 - fits in 4KB */
d3608b6d 1163static struct musb_fifo_cfg mode_3_cfg[] = {
550a7375
FB		 1164{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1165{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1166{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1167{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1168{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1169{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1170};
1171
1172/* mode 4 - fits in 16KB */
d3608b6d 1173static struct musb_fifo_cfg mode_4_cfg[] = {
550a7375
FB		 1174{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1175{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1176{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1177{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1178{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1179{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1180{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1181{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1182{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1183{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1184{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1185{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1186{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1187{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1188{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1189{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1190{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1191{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1192{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1193{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1194{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1195{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1196{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1197{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1198{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1199{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1200{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1201};
1202
3b151526 1203/* mode 5 - fits in 8KB */
d3608b6d 1204static struct musb_fifo_cfg mode_5_cfg[] = {
3b151526
AKG		 1205{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1206{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1207{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1208{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1209{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1210{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1211{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1212{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1213{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1214{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1215{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1216{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1217{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1218{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1219{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1220{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1221{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1222{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1223{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1224{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1225{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1226{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1227{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1228{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1229{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1230{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1231{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1232};
550a7375
FB		 1233
1234/*
1235 * configure a fifo; for non-shared endpoints, this may be called
1236 * once for a tx fifo and once for an rx fifo.
1237 *
1238 * returns negative errno or offset for next fifo.
1239 */
41ac7b3a 1240static int
550a7375 1241fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1242 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1243{
1244 void __iomem *mbase = musb->mregs;
1245 int size = 0;
1246 u16 maxpacket = cfg->maxpacket;
1247 u16 c_off = offset >> 3;
1248 u8 c_size;
1249
1250 /* expect hw_ep has already been zero-initialized */
1251
1252 size = ffs(max(maxpacket, (u16) 8)) - 1;
1253 maxpacket = 1 << size;
1254
1255 c_size = size - 3;
1256 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1257 if ((offset + (maxpacket << 1)) >
1258 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1259 return -EMSGSIZE;
1260 c_size |= MUSB_FIFOSZ_DPB;
1261 } else {
ca6d1b13 1262 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1263 return -EMSGSIZE;
1264 }
1265
1266 /* configure the FIFO */
1267 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1268
550a7375 1269 /* EP0 reserved endpoint for control, bidirectional;
5ae477b0 1270 * EP1 reserved for bulk, two unidirectional halves.
550a7375
FB		 1271 */
1272 if (hw_ep->epnum == 1)
1273 musb->bulk_ep = hw_ep;
1274 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1275 switch (cfg->style) {
1276 case FIFO_TX:
c6cf8b00
BW		 1277 musb_write_txfifosz(mbase, c_size);
1278 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1279 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1280 hw_ep->max_packet_sz_tx = maxpacket;
1281 break;
1282 case FIFO_RX:
c6cf8b00
BW		 1283 musb_write_rxfifosz(mbase, c_size);
1284 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1285 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1286 hw_ep->max_packet_sz_rx = maxpacket;
1287 break;
1288 case FIFO_RXTX:
c6cf8b00
BW		 1289 musb_write_txfifosz(mbase, c_size);
1290 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1291 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1292 hw_ep->max_packet_sz_rx = maxpacket;
1293
c6cf8b00
BW		 1294 musb_write_rxfifosz(mbase, c_size);
1295 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1296 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1297 hw_ep->max_packet_sz_tx = maxpacket;
1298
1299 hw_ep->is_shared_fifo = true;
1300 break;
1301 }
1302
1303 /* NOTE rx and tx endpoint irqs aren't managed separately,
1304 * which happens to be ok
1305 */
1306 musb->epmask |= (1 << hw_ep->epnum);
1307
1308 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1309}
1310
d3608b6d 1311static struct musb_fifo_cfg ep0_cfg = {
550a7375
FB		 1312 .style = FIFO_RXTX, .maxpacket = 64,
1313};
1314
41ac7b3a 1315static int ep_config_from_table(struct musb *musb)
550a7375 1316{
e6c213b2 1317 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1318 unsigned i, n;
1319 int offset;
1320 struct musb_hw_ep *hw_ep = musb->endpoints;
1321
e6c213b2
FB		 1322 if (musb->config->fifo_cfg) {
1323 cfg = musb->config->fifo_cfg;
1324 n = musb->config->fifo_cfg_size;
1325 goto done;
1326 }
1327
550a7375
FB		 1328 switch (fifo_mode) {
1329 default:
1330 fifo_mode = 0;
1331 /* FALLTHROUGH */
1332 case 0:
1333 cfg = mode_0_cfg;
1334 n = ARRAY_SIZE(mode_0_cfg);
1335 break;
1336 case 1:
1337 cfg = mode_1_cfg;
1338 n = ARRAY_SIZE(mode_1_cfg);
1339 break;
1340 case 2:
1341 cfg = mode_2_cfg;
1342 n = ARRAY_SIZE(mode_2_cfg);
1343 break;
1344 case 3:
1345 cfg = mode_3_cfg;
1346 n = ARRAY_SIZE(mode_3_cfg);
1347 break;
1348 case 4:
1349 cfg = mode_4_cfg;
1350 n = ARRAY_SIZE(mode_4_cfg);
1351 break;
3b151526
AKG		 1352 case 5:
1353 cfg = mode_5_cfg;
1354 n = ARRAY_SIZE(mode_5_cfg);
1355 break;
550a7375
FB		 1356 }
1357
3ff4b573 1358 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
550a7375
FB		 1359
1360
e6c213b2 1361done:
550a7375
FB		 1362 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1363 /* assert(offset > 0) */
1364
1365 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1366 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1367 */
1368
1369 for (i = 0; i < n; i++) {
1370 u8 epn = cfg->hw_ep_num;
1371
ca6d1b13 1372 if (epn >= musb->config->num_eps) {
550a7375
FB		 1373 pr_debug("%s: invalid ep %d\n",
1374 musb_driver_name, epn);
bb1c9ef1 1375 return -EINVAL;
550a7375
FB		 1376 }
1377 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1378 if (offset < 0) {
1379 pr_debug("%s: mem overrun, ep %d\n",
1380 musb_driver_name, epn);
f69dfa1f 1381 return offset;
550a7375
FB		 1382 }
1383 epn++;
1384 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1385 }
1386
3ff4b573 1387 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
550a7375 1388 musb_driver_name,
ca6d1b13
FB		 1389 n + 1, musb->config->num_eps * 2 - 1,
1390 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1391
550a7375
FB		 1392 if (!musb->bulk_ep) {
1393 pr_debug("%s: missing bulk\n", musb_driver_name);
1394 return -EINVAL;
1395 }
550a7375
FB		 1396
1397 return 0;
1398}
1399
1400
1401/*
1402 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1403 * @param musb the controller
1404 */
41ac7b3a 1405static int ep_config_from_hw(struct musb *musb)
550a7375 1406{
c6cf8b00 1407 u8 epnum = 0;
550a7375 1408 struct musb_hw_ep *hw_ep;
a156544b 1409 void __iomem *mbase = musb->mregs;
c6cf8b00 1410 int ret = 0;
550a7375 1411
b99d3659 1412 musb_dbg(musb, "<== static silicon ep config");
550a7375
FB		 1413
1414 /* FIXME pick up ep0 maxpacket size */
1415
ca6d1b13 1416 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1417 musb_ep_select(mbase, epnum);
1418 hw_ep = musb->endpoints + epnum;
1419
c6cf8b00
BW		 1420 ret = musb_read_fifosize(musb, hw_ep, epnum);
1421 if (ret < 0)
550a7375 1422 break;
550a7375
FB		 1423
1424 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1425
550a7375
FB		 1426 /* pick an RX/TX endpoint for bulk */
1427 if (hw_ep->max_packet_sz_tx < 512
1428 || hw_ep->max_packet_sz_rx < 512)
1429 continue;
1430
1431 /* REVISIT: this algorithm is lazy, we should at least
1432 * try to pick a double buffered endpoint.
1433 */
1434 if (musb->bulk_ep)
1435 continue;
1436 musb->bulk_ep = hw_ep;
550a7375
FB		 1437 }
1438
550a7375
FB		 1439 if (!musb->bulk_ep) {
1440 pr_debug("%s: missing bulk\n", musb_driver_name);
1441 return -EINVAL;
1442 }
550a7375
FB		 1443
1444 return 0;
1445}
1446
1447enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1448
1449/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1450 * configure endpoints, or take their config from silicon
1451 */
41ac7b3a 1452static int musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1453{
550a7375
FB		 1454 u8 reg;
1455 char *type;
21b031fb 1456 char aInfo[90];
550a7375
FB		 1457 void __iomem *mbase = musb->mregs;
1458 int status = 0;
1459 int i;
1460
1461 /* log core options (read using indexed model) */
c6cf8b00 1462 reg = musb_read_configdata(mbase);
550a7375
FB		 1463
1464 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1465 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1466 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1467 musb->dyn_fifo = true;
1468 }
550a7375
FB		 1469 if (reg & MUSB_CONFIGDATA_MPRXE) {
1470 strcat(aInfo, ", bulk combine");
550a7375 1471 musb->bulk_combine = true;
550a7375
FB		 1472 }
1473 if (reg & MUSB_CONFIGDATA_MPTXE) {
1474 strcat(aInfo, ", bulk split");
550a7375 1475 musb->bulk_split = true;
550a7375
FB		 1476 }
1477 if (reg & MUSB_CONFIGDATA_HBRXE) {
1478 strcat(aInfo, ", HB-ISO Rx");
a483d706 1479 musb->hb_iso_rx = true;
550a7375
FB		 1480 }
1481 if (reg & MUSB_CONFIGDATA_HBTXE) {
1482 strcat(aInfo, ", HB-ISO Tx");
a483d706 1483 musb->hb_iso_tx = true;
550a7375
FB		 1484 }
1485 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1486 strcat(aInfo, ", SoftConn");
1487
3ff4b573 1488 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
550a7375 1489
550a7375
FB		 1490 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1491 musb->is_multipoint = 1;
1492 type = "M";
1493 } else {
1494 musb->is_multipoint = 0;
1495 type = "";
550a7375 1496#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
3ff4b573
RV		 1497 pr_err("%s: kernel must blacklist external hubs\n",
1498 musb_driver_name);
550a7375
FB		 1499#endif
1500 }
1501
1502 /* log release info */
32c3b94e 1503 musb->hwvers = musb_read_hwvers(mbase);
21b031fb
RV		 1504 pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1505 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1506 MUSB_HWVERS_MINOR(musb->hwvers),
1507 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1508
1509 /* configure ep0 */
c6cf8b00 1510 musb_configure_ep0(musb);
550a7375
FB		 1511
1512 /* discover endpoint configuration */
1513 musb->nr_endpoints = 1;
1514 musb->epmask = 1;
1515
ad517e9e
FB		 1516 if (musb->dyn_fifo)
1517 status = ep_config_from_table(musb);
1518 else
1519 status = ep_config_from_hw(musb);
550a7375
FB		 1520
1521 if (status < 0)
1522 return status;
1523
1524 /* finish init, and print endpoint config */
1525 for (i = 0; i < musb->nr_endpoints; i++) {
1526 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1527
1b40fc57 1528 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
ebf39920 1529#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1b40fc57
TL		 1530 if (musb->io.quirks & MUSB_IN_TUSB) {
1531 hw_ep->fifo_async = musb->async + 0x400 +
1532 musb->io.fifo_offset(i);
1533 hw_ep->fifo_sync = musb->sync + 0x400 +
1534 musb->io.fifo_offset(i);
1535 hw_ep->fifo_sync_va =
1536 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1537
1538 if (i == 0)
1539 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1540 else
1541 hw_ep->conf = mbase + 0x400 +
1542 (((i - 1) & 0xf) << 2);
1543 }
550a7375
FB		 1544#endif
1545
d026e9c7 1546 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
550a7375
FB		 1547 hw_ep->rx_reinit = 1;
1548 hw_ep->tx_reinit = 1;
550a7375
FB		 1549
1550 if (hw_ep->max_packet_sz_tx) {
b99d3659 1551 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
550a7375
FB		 1552 musb_driver_name, i,
1553 hw_ep->is_shared_fifo ? "shared" : "tx",
1554 hw_ep->tx_double_buffered
1555 ? "doublebuffer, " : "",
1556 hw_ep->max_packet_sz_tx);
1557 }
1558 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
b99d3659 1559 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
550a7375
FB		 1560 musb_driver_name, i,
1561 "rx",
1562 hw_ep->rx_double_buffered
1563 ? "doublebuffer, " : "",
1564 hw_ep->max_packet_sz_rx);
1565 }
1566 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
b99d3659 1567 musb_dbg(musb, "hw_ep %d not configured", i);
550a7375
FB		 1568 }
1569
1570 return 0;
1571}
1572
1573/*-------------------------------------------------------------------------*/
1574
550a7375
FB		 1575/*
1576 * handle all the irqs defined by the HDRC core. for now we expect: other
1577 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1578 * will be assigned, and the irq will already have been acked.
1579 *
1580 * called in irq context with spinlock held, irqs blocked
1581 */
1582irqreturn_t musb_interrupt(struct musb *musb)
1583{
1584 irqreturn_t retval = IRQ_NONE;
31a0ede0
FB		 1585 unsigned long status;
1586 unsigned long epnum;
b11e94d0 1587 u8 devctl;
31a0ede0
FB		 1588
1589 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1590 return IRQ_NONE;
550a7375
FB		 1591
1592 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1593
cfb9a1bc 1594 trace_musb_isr(musb);
550a7375 1595
e3c93e1a
FB		 1596 /**
1597 * According to Mentor Graphics' documentation, flowchart on page 98,
1598 * IRQ should be handled as follows:
1599 *
1600 * . Resume IRQ
1601 * . Session Request IRQ
1602 * . VBUS Error IRQ
1603 * . Suspend IRQ
1604 * . Connect IRQ
1605 * . Disconnect IRQ
1606 * . Reset/Babble IRQ
1607 * . SOF IRQ (we're not using this one)
1608 * . Endpoint 0 IRQ
1609 * . TX Endpoints
1610 * . RX Endpoints
1611 *
1612 * We will be following that flowchart in order to avoid any problems
1613 * that might arise with internal Finite State Machine.
550a7375 1614 */
e3c93e1a 1615
7d9645fd 1616 if (musb->int_usb)
31a0ede0 1617 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
550a7375 1618
550a7375 1619 if (musb->int_tx & 1) {
c03da38d 1620 if (is_host_active(musb))
550a7375
FB		 1621 retval |= musb_h_ep0_irq(musb);
1622 else
1623 retval |= musb_g_ep0_irq(musb);
31a0ede0
FB		 1624
1625 /* we have just handled endpoint 0 IRQ, clear it */
1626 musb->int_tx &= ~BIT(0);
550a7375
FB		 1627 }
1628
31a0ede0
FB		 1629 status = musb->int_tx;
1630
1631 for_each_set_bit(epnum, &status, 16) {
1632 retval = IRQ_HANDLED;
1633 if (is_host_active(musb))
1634 musb_host_tx(musb, epnum);
1635 else
1636 musb_g_tx(musb, epnum);
550a7375
FB		 1637 }
1638
31a0ede0 1639 status = musb->int_rx;
e3c93e1a 1640
31a0ede0
FB		 1641 for_each_set_bit(epnum, &status, 16) {
1642 retval = IRQ_HANDLED;
1643 if (is_host_active(musb))
1644 musb_host_rx(musb, epnum);
1645 else
1646 musb_g_rx(musb, epnum);
550a7375
FB		 1647 }
1648
550a7375
FB		 1649 return retval;
1650}
981430a1 1651EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1652
1653#ifndef CONFIG_MUSB_PIO_ONLY
d3608b6d 1654static bool use_dma = 1;
550a7375
FB		 1655
1656/* "modprobe ... use_dma=0" etc */
51676c8d 1657module_param(use_dma, bool, 0644);
550a7375
FB		 1658MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1659
1660void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1661{
550a7375
FB		 1662 /* called with controller lock already held */
1663
1664 if (!epnum) {
f8e9f34f 1665 if (!is_cppi_enabled(musb)) {
550a7375 1666 /* endpoint 0 */
c03da38d 1667 if (is_host_active(musb))
550a7375
FB		 1668 musb_h_ep0_irq(musb);
1669 else
1670 musb_g_ep0_irq(musb);
1671 }
550a7375
FB		 1672 } else {
1673 /* endpoints 1..15 */
1674 if (transmit) {
c03da38d 1675 if (is_host_active(musb))
a04d46d0
FB		 1676 musb_host_tx(musb, epnum);
1677 else
1678 musb_g_tx(musb, epnum);
550a7375
FB		 1679 } else {
1680 /* receive */
c03da38d 1681 if (is_host_active(musb))
a04d46d0
FB		 1682 musb_host_rx(musb, epnum);
1683 else
1684 musb_g_rx(musb, epnum);
550a7375
FB		 1685 }
1686 }
1687}
9a35f876 1688EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1689
1690#else
1691#define use_dma 0
1692#endif
1693
12b7db2b 1694static int (*musb_phy_callback)(enum musb_vbus_id_status status);
8055555f
TL		 1695
1696/*
1697 * musb_mailbox - optional phy notifier function
1698 * @status phy state change
1699 *
1700 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1701 * disabled at the point the phy_callback is registered or unregistered.
1702 */
12b7db2b 1703int musb_mailbox(enum musb_vbus_id_status status)
8055555f
TL		 1704{
1705 if (musb_phy_callback)
12b7db2b 1706 return musb_phy_callback(status);
8055555f 1707
12b7db2b 1708 return -ENODEV;
8055555f
TL		 1709};
1710EXPORT_SYMBOL_GPL(musb_mailbox);
1711
550a7375
FB		 1712/*-------------------------------------------------------------------------*/
1713
550a7375
FB		 1714static ssize_t
1715musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1716{
1717 struct musb *musb = dev_to_musb(dev);
1718 unsigned long flags;
1719 int ret = -EINVAL;
1720
1721 spin_lock_irqsave(&musb->lock, flags);
e47d9254 1722 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 1723 spin_unlock_irqrestore(&musb->lock, flags);
1724
1725 return ret;
1726}
1727
1728static ssize_t
1729musb_mode_store(struct device *dev, struct device_attribute *attr,
1730 const char *buf, size_t n)
1731{
1732 struct musb *musb = dev_to_musb(dev);
1733 unsigned long flags;
96a274d1 1734 int status;
550a7375
FB		 1735
1736 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1737 if (sysfs_streq(buf, "host"))
1738 status = musb_platform_set_mode(musb, MUSB_HOST);
1739 else if (sysfs_streq(buf, "peripheral"))
1740 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1741 else if (sysfs_streq(buf, "otg"))
1742 status = musb_platform_set_mode(musb, MUSB_OTG);
1743 else
1744 status = -EINVAL;
550a7375
FB		 1745 spin_unlock_irqrestore(&musb->lock, flags);
1746
96a274d1 1747 return (status == 0) ? n : status;
550a7375
FB		 1748}
1749static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1750
1751static ssize_t
1752musb_vbus_store(struct device *dev, struct device_attribute *attr,
1753 const char *buf, size_t n)
1754{
1755 struct musb *musb = dev_to_musb(dev);
1756 unsigned long flags;
1757 unsigned long val;
1758
1759 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1760 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1761 return -EINVAL;
1762 }
1763
1764 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1765 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1766 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
e47d9254 1767 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1768 musb->is_active = 0;
1769 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1770 spin_unlock_irqrestore(&musb->lock, flags);
1771
1772 return n;
1773}
1774
1775static ssize_t
1776musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1777{
1778 struct musb *musb = dev_to_musb(dev);
1779 unsigned long flags;
1780 unsigned long val;
1781 int vbus;
3bbafac8 1782 u8 devctl;
550a7375
FB		 1783
1784 spin_lock_irqsave(&musb->lock, flags);
1785 val = musb->a_wait_bcon;
1786 vbus = musb_platform_get_vbus_status(musb);
3bbafac8
RA		 1787 if (vbus < 0) {
1788 /* Use default MUSB method by means of DEVCTL register */
1789 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1790 if ((devctl & MUSB_DEVCTL_VBUS)
1791 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1792 vbus = 1;
1793 else
1794 vbus = 0;
1795 }
550a7375
FB		 1796 spin_unlock_irqrestore(&musb->lock, flags);
1797
f7f9d63e 1798 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1799 vbus ? "on" : "off", val);
1800}
1801static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1802
550a7375
FB		 1803/* Gadget drivers can't know that a host is connected so they might want
1804 * to start SRP, but users can. This allows userspace to trigger SRP.
1805 */
1806static ssize_t
1807musb_srp_store(struct device *dev, struct device_attribute *attr,
1808 const char *buf, size_t n)
1809{
1810 struct musb *musb = dev_to_musb(dev);
1811 unsigned short srp;
1812
1813 if (sscanf(buf, "%hu", &srp) != 1
1814 || (srp != 1)) {
b3b1cc3b 1815 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1816 return -EINVAL;
1817 }
1818
1819 if (srp == 1)
1820 musb_g_wakeup(musb);
1821
1822 return n;
1823}
1824static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1825
94375751
FB		 1826static struct attribute *musb_attributes[] = {
1827 &dev_attr_mode.attr,
1828 &dev_attr_vbus.attr,
94375751 1829 &dev_attr_srp.attr,
94375751
FB		 1830 NULL
1831};
1832
1833static const struct attribute_group musb_attr_group = {
1834 .attrs = musb_attributes,
1835};
1836
467d5c98
TL		 1837#define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
1838 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1839 MUSB_DEVCTL_SESSION)
1840#define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1841 MUSB_DEVCTL_SESSION)
1842
1843/*
1844 * Check the musb devctl session bit to determine if we want to
1845 * allow PM runtime for the device. In general, we want to keep things
1846 * active when the session bit is set except after host disconnect.
1847 *
1848 * Only called from musb_irq_work. If this ever needs to get called
1849 * elsewhere, proper locking must be implemented for musb->session.
1850 */
1851static void musb_pm_runtime_check_session(struct musb *musb)
1852{
1853 u8 devctl, s;
1854 int error;
1855
1856 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1857
1858 /* Handle session status quirks first */
1859 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
1860 MUSB_DEVCTL_HR;
1861 switch (devctl & ~s) {
1862 case MUSB_QUIRK_B_INVALID_VBUS_91:
0c3aae9b 1863 if (musb->quirk_retries && !musb->flush_irq_work) {
2b9a8c40 1864 musb_dbg(musb,
2bff3916
TL		 1865 "Poll devctl on invalid vbus, assume no session");
1866 schedule_delayed_work(&musb->irq_work,
1867 msecs_to_jiffies(1000));
4f190e0b 1868 musb->quirk_retries--;
2b9a8c40
TL		 1869 return;
1870 }
eff0b85e 1871 /* fall through */
467d5c98 1872 case MUSB_QUIRK_A_DISCONNECT_19:
0c3aae9b 1873 if (musb->quirk_retries && !musb->flush_irq_work) {
2bff3916
TL		 1874 musb_dbg(musb,
1875 "Poll devctl on possible host mode disconnect");
1876 schedule_delayed_work(&musb->irq_work,
1877 msecs_to_jiffies(1000));
4f190e0b 1878 musb->quirk_retries--;
2bff3916
TL		 1879 return;
1880 }
467d5c98
TL		 1881 if (!musb->session)
1882 break;
1883 musb_dbg(musb, "Allow PM on possible host mode disconnect");
1884 pm_runtime_mark_last_busy(musb->controller);
1885 pm_runtime_put_autosuspend(musb->controller);
1886 musb->session = false;
1887 return;
1888 default:
1889 break;
1890 }
1891
1892 /* No need to do anything if session has not changed */
1893 s = devctl & MUSB_DEVCTL_SESSION;
1894 if (s == musb->session)
1895 return;
1896
1897 /* Block PM or allow PM? */
1898 if (s) {
1899 musb_dbg(musb, "Block PM on active session: %02x", devctl);
1900 error = pm_runtime_get_sync(musb->controller);
1901 if (error < 0)
1902 dev_err(musb->controller, "Could not enable: %i\n",
1903 error);
2bff3916 1904 musb->quirk_retries = 3;
467d5c98
TL		 1905 } else {
1906 musb_dbg(musb, "Allow PM with no session: %02x", devctl);
1907 pm_runtime_mark_last_busy(musb->controller);
1908 pm_runtime_put_autosuspend(musb->controller);
1909 }
1910
1911 musb->session = s;
1912}
1913
550a7375
FB		 1914/* Only used to provide driver mode change events */
1915static void musb_irq_work(struct work_struct *data)
1916{
2bff3916 1917 struct musb *musb = container_of(data, struct musb, irq_work.work);
3ba7b779
TL		 1918 int error;
1919
1920 error = pm_runtime_get_sync(musb->controller);
1921 if (error < 0) {
1922 dev_err(musb->controller, "Could not enable: %i\n", error);
1923
1924 return;
1925 }
550a7375 1926
467d5c98
TL		 1927 musb_pm_runtime_check_session(musb);
1928
e47d9254
AT		 1929 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1930 musb->xceiv_old_state = musb->xceiv->otg->state;
550a7375
FB		 1931 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1932 }
3ba7b779
TL		 1933
1934 pm_runtime_mark_last_busy(musb->controller);
1935 pm_runtime_put_autosuspend(musb->controller);
550a7375
FB		 1936}
1937
83b8f5b8 1938static void musb_recover_from_babble(struct musb *musb)
ca88fc2e 1939{
b4dc38fd
FB		 1940 int ret;
1941 u8 devctl;
ca88fc2e 1942
0244336f
FB		 1943 musb_disable_interrupts(musb);
1944
83b8f5b8
FB		 1945 /*
1946 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1947 * it some slack and wait for 10us.
1948 */
1949 udelay(10);
1950
b28a6432 1951 ret = musb_platform_recover(musb);
ba7ee8bb
FB		 1952 if (ret) {
1953 musb_enable_interrupts(musb);
d871c622 1954 return;
ba7ee8bb 1955 }
ca88fc2e 1956
b4dc38fd
FB		 1957 /* drop session bit */
1958 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1959 devctl &= ~MUSB_DEVCTL_SESSION;
1960 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
ca88fc2e 1961
b4dc38fd
FB		 1962 /* tell usbcore about it */
1963 musb_root_disconnect(musb);
ca88fc2e
DM		 1964
1965 /*
d871c622
GC		 1966 * When a babble condition occurs, the musb controller
1967 * removes the session bit and the endpoint config is lost.
ca88fc2e
DM		 1968 */
1969 if (musb->dyn_fifo)
b4dc38fd 1970 ret = ep_config_from_table(musb);
ca88fc2e 1971 else
b4dc38fd 1972 ret = ep_config_from_hw(musb);
ca88fc2e 1973
b4dc38fd
FB		 1974 /* restart session */
1975 if (ret == 0)
ca88fc2e
DM		 1976 musb_start(musb);
1977}
1978
550a7375
FB		 1979/* --------------------------------------------------------------------------
1980 * Init support
1981 */
1982
41ac7b3a 1983static struct musb *allocate_instance(struct device *dev,
ead22caf 1984 const struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1985{
1986 struct musb *musb;
1987 struct musb_hw_ep *ep;
1988 int epnum;
74c2e936 1989 int ret;
550a7375 1990
74c2e936
DM		 1991 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1992 if (!musb)
550a7375 1993 return NULL;
550a7375 1994
550a7375
FB		 1995 INIT_LIST_HEAD(&musb->control);
1996 INIT_LIST_HEAD(&musb->in_bulk);
1997 INIT_LIST_HEAD(&musb->out_bulk);
ea2f35c0 1998 INIT_LIST_HEAD(&musb->pending_list);
550a7375 1999
550a7375 2000 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 2001 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
550a7375
FB		 2002 musb->mregs = mbase;
2003 musb->ctrl_base = mbase;
2004 musb->nIrq = -ENODEV;
ca6d1b13 2005 musb->config = config;
02582b92 2006 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 2007 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 2008 epnum < musb->config->num_eps;
550a7375 2009 epnum++, ep++) {
550a7375
FB		 2010 ep->musb = musb;
2011 ep->epnum = epnum;
2012 }
2013
2014 musb->controller = dev;
743411b3 2015
74c2e936
DM		 2016 ret = musb_host_alloc(musb);
2017 if (ret < 0)
2018 goto err_free;
2019
2020 dev_set_drvdata(dev, musb);
2021
550a7375 2022 return musb;
74c2e936
DM		 2023
2024err_free:
2025 return NULL;
550a7375
FB		 2026}
2027
2028static void musb_free(struct musb *musb)
2029{
2030 /* this has multiple entry modes. it handles fault cleanup after
2031 * probe(), where things may be partially set up, as well as rmmod
2032 * cleanup after everything's been de-activated.
2033 */
2034
2035#ifdef CONFIG_SYSFS
94375751 2036 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 2037#endif
2038
97a39896
AKG		 2039 if (musb->nIrq >= 0) {
2040 if (musb->irq_wake)
2041 disable_irq_wake(musb->nIrq);
550a7375
FB		 2042 free_irq(musb->nIrq, musb);
2043 }
550a7375 2044
74c2e936 2045 musb_host_free(musb);
550a7375
FB		 2046}
2047
ea2f35c0
TL		 2048struct musb_pending_work {
2049 int (*callback)(struct musb *musb, void *data);
2050 void *data;
2051 struct list_head node;
2052};
2053
c8bd2ac3 2054#ifdef CONFIG_PM
ea2f35c0
TL		 2055/*
2056 * Called from musb_runtime_resume(), musb_resume(), and
2057 * musb_queue_resume_work(). Callers must take musb->lock.
2058 */
2059static int musb_run_resume_work(struct musb *musb)
2060{
2061 struct musb_pending_work *w, *_w;
2062 unsigned long flags;
2063 int error = 0;
2064
2065 spin_lock_irqsave(&musb->list_lock, flags);
2066 list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
2067 if (w->callback) {
2068 error = w->callback(musb, w->data);
2069 if (error < 0) {
2070 dev_err(musb->controller,
2071 "resume callback %p failed: %i\n",
2072 w->callback, error);
2073 }
2074 }
2075 list_del(&w->node);
2076 devm_kfree(musb->controller, w);
2077 }
2078 spin_unlock_irqrestore(&musb->list_lock, flags);
2079
2080 return error;
2081}
c8bd2ac3 2082#endif
ea2f35c0
TL		 2083
2084/*
2085 * Called to run work if device is active or else queue the work to happen
2086 * on resume. Caller must take musb->lock and must hold an RPM reference.
2087 *
2088 * Note that we cowardly refuse queuing work after musb PM runtime
2089 * resume is done calling musb_run_resume_work() and return -EINPROGRESS
2090 * instead.
2091 */
2092int musb_queue_resume_work(struct musb *musb,
2093 int (*callback)(struct musb *musb, void *data),
2094 void *data)
2095{
2096 struct musb_pending_work *w;
2097 unsigned long flags;
2098 int error;
2099
2100 if (WARN_ON(!callback))
2101 return -EINVAL;
2102
2103 if (pm_runtime_active(musb->controller))
2104 return callback(musb, data);
2105
2106 w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
2107 if (!w)
2108 return -ENOMEM;
2109
2110 w->callback = callback;
2111 w->data = data;
2112 spin_lock_irqsave(&musb->list_lock, flags);
2113 if (musb->is_runtime_suspended) {
2114 list_add_tail(&w->node, &musb->pending_list);
2115 error = 0;
2116 } else {
2117 dev_err(musb->controller, "could not add resume work %p\n",
2118 callback);
2119 devm_kfree(musb->controller, w);
2120 error = -EINPROGRESS;
2121 }
2122 spin_unlock_irqrestore(&musb->list_lock, flags);
2123
2124 return error;
2125}
2126EXPORT_SYMBOL_GPL(musb_queue_resume_work);
2127
8ed1fb79
DM		 2128static void musb_deassert_reset(struct work_struct *work)
2129{
2130 struct musb *musb;
2131 unsigned long flags;
2132
2133 musb = container_of(work, struct musb, deassert_reset_work.work);
2134
2135 spin_lock_irqsave(&musb->lock, flags);
2136
2137 if (musb->port1_status & USB_PORT_STAT_RESET)
2138 musb_port_reset(musb, false);
2139
2140 spin_unlock_irqrestore(&musb->lock, flags);
2141}
2142
550a7375
FB		 2143/*
2144 * Perform generic per-controller initialization.
2145 *
28dd924a
SS		 2146 * @dev: the controller (already clocked, etc)
2147 * @nIrq: IRQ number
2148 * @ctrl: virtual address of controller registers,
550a7375
FB		 2149 * not yet corrected for platform-specific offsets
2150 */
41ac7b3a 2151static int
550a7375
FB		 2152musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2153{
2154 int status;
2155 struct musb *musb;
c1a7d67c 2156 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
550a7375
FB		 2157
2158 /* The driver might handle more features than the board; OK.
2159 * Fail when the board needs a feature that's not enabled.
2160 */
2161 if (!plat) {
b99d3659 2162 dev_err(dev, "no platform_data?\n");
34e2beb2
SS		 2163 status = -ENODEV;
2164 goto fail0;
550a7375 2165 }
34e2beb2 2166
550a7375 2167 /* allocate */
ca6d1b13 2168 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 2169 if (!musb) {
2170 status = -ENOMEM;
2171 goto fail0;
2172 }
550a7375
FB		 2173
2174 spin_lock_init(&musb->lock);
ea2f35c0 2175 spin_lock_init(&musb->list_lock);
550a7375 2176 musb->board_set_power = plat->set_power;
550a7375 2177 musb->min_power = plat->min_power;
f7ec9437 2178 musb->ops = plat->platform_ops;
9ad96e69 2179 musb->port_mode = plat->mode;
550a7375 2180
1b40fc57
TL		 2181 /*
2182 * Initialize the default IO functions. At least omap2430 needs
2183 * these early. We initialize the platform specific IO functions
2184 * later on.
2185 */
2186 musb_readb = musb_default_readb;
2187 musb_writeb = musb_default_writeb;
2188 musb_readw = musb_default_readw;
2189 musb_writew = musb_default_writew;
2190 musb_readl = musb_default_readl;
2191 musb_writel = musb_default_writel;
2192
84e250ff 2193 /* The musb_platform_init() call:
baef653a
PDS		 2194 * - adjusts musb->mregs
2195 * - sets the musb->isr
5ae477b0 2196 * - may initialize an integrated transceiver
721002ec 2197 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 2198 * - stops powering VBUS
84e250ff 2199 *
7c9d440e 2200 * There are various transceiver configurations. Blackfin,
84e250ff
DB		 2201 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2202 * external/discrete ones in various flavors (twl4030 family,
2203 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375 2204 */
ea65df57 2205 status = musb_platform_init(musb);
550a7375 2206 if (status < 0)
03491761 2207 goto fail1;
34e2beb2 2208
550a7375
FB		 2209 if (!musb->isr) {
2210 status = -ENODEV;
c04352a5 2211 goto fail2;
550a7375
FB		 2212 }
2213
1b40fc57
TL		 2214 if (musb->ops->quirks)
2215 musb->io.quirks = musb->ops->quirks;
2216
da96cfc1 2217 /* Most devices use indexed offset or flat offset */
d026e9c7
TL		 2218 if (musb->io.quirks & MUSB_INDEXED_EP) {
2219 musb->io.ep_offset = musb_indexed_ep_offset;
2220 musb->io.ep_select = musb_indexed_ep_select;
2221 } else {
2222 musb->io.ep_offset = musb_flat_ep_offset;
2223 musb->io.ep_select = musb_flat_ep_select;
2224 }
2225
1fa07c37
PU		 2226 if (musb->io.quirks & MUSB_G_NO_SKB_RESERVE)
2227 musb->g.quirk_avoids_skb_reserve = 1;
2228
da96cfc1
BH		 2229 /* At least tusb6010 has its own offsets */
2230 if (musb->ops->ep_offset)
2231 musb->io.ep_offset = musb->ops->ep_offset;
2232 if (musb->ops->ep_select)
2233 musb->io.ep_select = musb->ops->ep_select;
2234
8a77f05a
TL		 2235 if (musb->ops->fifo_mode)
2236 fifo_mode = musb->ops->fifo_mode;
2237 else
2238 fifo_mode = 4;
2239
1b40fc57
TL		 2240 if (musb->ops->fifo_offset)
2241 musb->io.fifo_offset = musb->ops->fifo_offset;
2242 else
2243 musb->io.fifo_offset = musb_default_fifo_offset;
2244
6cc2af6d
HG		 2245 if (musb->ops->busctl_offset)
2246 musb->io.busctl_offset = musb->ops->busctl_offset;
2247 else
2248 musb->io.busctl_offset = musb_default_busctl_offset;
2249
1b40fc57
TL		 2250 if (musb->ops->readb)
2251 musb_readb = musb->ops->readb;
2252 if (musb->ops->writeb)
2253 musb_writeb = musb->ops->writeb;
2254 if (musb->ops->readw)
2255 musb_readw = musb->ops->readw;
2256 if (musb->ops->writew)
2257 musb_writew = musb->ops->writew;
2258 if (musb->ops->readl)
2259 musb_readl = musb->ops->readl;
2260 if (musb->ops->writel)
2261 musb_writel = musb->ops->writel;
2262
7f6283ed
TL		 2263#ifndef CONFIG_MUSB_PIO_ONLY
2264 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2265 dev_err(dev, "DMA controller not set\n");
7d32cdef 2266 status = -ENODEV;
7f6283ed
TL		 2267 goto fail2;
2268 }
2269 musb_dma_controller_create = musb->ops->dma_init;
2270 musb_dma_controller_destroy = musb->ops->dma_exit;
2271#endif
2272
1b40fc57
TL		 2273 if (musb->ops->read_fifo)
2274 musb->io.read_fifo = musb->ops->read_fifo;
2275 else
2276 musb->io.read_fifo = musb_default_read_fifo;
2277
2278 if (musb->ops->write_fifo)
2279 musb->io.write_fifo = musb->ops->write_fifo;
2280 else
2281 musb->io.write_fifo = musb_default_write_fifo;
2282
ffb865b1 2283 if (!musb->xceiv->io_ops) {
bf070bc1 2284 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 2285 musb->xceiv->io_priv = musb->mregs;
2286 musb->xceiv->io_ops = &musb_ulpi_access;
2287 }
2288
8055555f
TL		 2289 if (musb->ops->phy_callback)
2290 musb_phy_callback = musb->ops->phy_callback;
2291
f730f205
TL		 2292 /*
2293 * We need musb_read/write functions initialized for PM.
2294 * Note that at least 2430 glue needs autosuspend delay
2295 * somewhere above 300 ms for the hardware to idle properly
2296 * after disconnecting the cable in host mode. Let's use
2297 * 500 ms for some margin.
2298 */
2299 pm_runtime_use_autosuspend(musb->controller);
2300 pm_runtime_set_autosuspend_delay(musb->controller, 500);
2301 pm_runtime_enable(musb->controller);
c04352a5
GI		 2302 pm_runtime_get_sync(musb->controller);
2303
39cee200
UKK		 2304 status = usb_phy_init(musb->xceiv);
2305 if (status < 0)
2306 goto err_usb_phy_init;
2307
48054147 2308 if (use_dma && dev->dma_mask) {
7f6283ed
TL		 2309 musb->dma_controller =
2310 musb_dma_controller_create(musb, musb->mregs);
48054147
SAS		 2311 if (IS_ERR(musb->dma_controller)) {
2312 status = PTR_ERR(musb->dma_controller);
2313 goto fail2_5;
2314 }
2315 }
550a7375
FB		 2316
2317 /* be sure interrupts are disabled before connecting ISR */
2318 musb_platform_disable(musb);
e945953d
BL		 2319 musb_disable_interrupts(musb);
2320 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
550a7375 2321
66fadea5 2322 /* Init IRQ workqueue before request_irq */
2bff3916 2323 INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
8ed1fb79
DM		 2324 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2325 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
66fadea5 2326
550a7375 2327 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 2328 status = musb_core_init(plat->config->multipoint
550a7375
FB		 2329 ? MUSB_CONTROLLER_MHDRC
2330 : MUSB_CONTROLLER_HDRC, musb);
2331 if (status < 0)
34e2beb2 2332 goto fail3;
550a7375 2333
05678497 2334 timer_setup(&musb->otg_timer, musb_otg_timer_func, 0);
f7f9d63e 2335
550a7375 2336 /* attach to the IRQ */
aa2fb886 2337 if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) {
550a7375
FB		 2338 dev_err(dev, "request_irq %d failed!\n", nIrq);
2339 status = -ENODEV;
34e2beb2 2340 goto fail3;
550a7375
FB		 2341 }
2342 musb->nIrq = nIrq;
032ec49f 2343 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 2344 if (enable_irq_wake(nIrq) == 0) {
2345 musb->irq_wake = 1;
550a7375 2346 device_init_wakeup(dev, 1);
c48a5155
FB		 2347 } else {
2348 musb->irq_wake = 0;
2349 }
550a7375 2350
032ec49f
FB		 2351 /* program PHY to use external vBus if required */
2352 if (plat->extvbus) {
2353 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2354 busctl |= MUSB_ULPI_USE_EXTVBUS;
2355 musb_write_ulpi_buscontrol(musb->mregs, busctl);
550a7375 2356 }
550a7375 2357
e5615112
GI		 2358 if (musb->xceiv->otg->default_a) {
2359 MUSB_HST_MODE(musb);
e47d9254 2360 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
e5615112
GI		 2361 } else {
2362 MUSB_DEV_MODE(musb);
e47d9254 2363 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
e5615112 2364 }
550a7375 2365
6c5f6a6f
DM		 2366 switch (musb->port_mode) {
2367 case MUSB_PORT_MODE_HOST:
2368 status = musb_host_setup(musb, plat->power);
2df6761e
FB		 2369 if (status < 0)
2370 goto fail3;
2371 status = musb_platform_set_mode(musb, MUSB_HOST);
6c5f6a6f
DM		 2372 break;
2373 case MUSB_PORT_MODE_GADGET:
2374 status = musb_gadget_setup(musb);
2df6761e
FB		 2375 if (status < 0)
2376 goto fail3;
2377 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
6c5f6a6f
DM		 2378 break;
2379 case MUSB_PORT_MODE_DUAL_ROLE:
2380 status = musb_host_setup(musb, plat->power);
2381 if (status < 0)
2382 goto fail3;
2383 status = musb_gadget_setup(musb);
2df6761e 2384 if (status) {
0d2dd7ea 2385 musb_host_cleanup(musb);
2df6761e
FB		 2386 goto fail3;
2387 }
2388 status = musb_platform_set_mode(musb, MUSB_OTG);
6c5f6a6f
DM		 2389 break;
2390 default:
2391 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2392 break;
2393 }
550a7375 2394
461972d8 2395 if (status < 0)
34e2beb2 2396 goto fail3;
550a7375 2397
7f7f9e2a
FB		 2398 status = musb_init_debugfs(musb);
2399 if (status < 0)
b0f9da7e 2400 goto fail4;
7f7f9e2a 2401
94375751 2402 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
28c2c51c 2403 if (status)
b0f9da7e 2404 goto fail5;
550a7375 2405
c723bd6e 2406 musb->is_initialized = 1;
7099dbc5
TL		 2407 pm_runtime_mark_last_busy(musb->controller);
2408 pm_runtime_put_autosuspend(musb->controller);
c04352a5 2409
28c2c51c 2410 return 0;
550a7375 2411
b0f9da7e
FB		 2412fail5:
2413 musb_exit_debugfs(musb);
2414
34e2beb2 2415fail4:
032ec49f 2416 musb_gadget_cleanup(musb);
0d2dd7ea 2417 musb_host_cleanup(musb);
34e2beb2
SS		 2418
2419fail3:
2bff3916 2420 cancel_delayed_work_sync(&musb->irq_work);
8ed1fb79
DM		 2421 cancel_delayed_work_sync(&musb->finish_resume_work);
2422 cancel_delayed_work_sync(&musb->deassert_reset_work);
f3ce4d5b 2423 if (musb->dma_controller)
7f6283ed 2424 musb_dma_controller_destroy(musb->dma_controller);
39cee200 2425
48054147 2426fail2_5:
39cee200
UKK		 2427 usb_phy_shutdown(musb->xceiv);
2428
2429err_usb_phy_init:
7099dbc5 2430 pm_runtime_dont_use_autosuspend(musb->controller);
c04352a5 2431 pm_runtime_put_sync(musb->controller);
f730f205 2432 pm_runtime_disable(musb->controller);
c04352a5
GI		 2433
2434fail2:
34e2beb2
SS		 2435 if (musb->irq_wake)
2436 device_init_wakeup(dev, 0);
550a7375 2437 musb_platform_exit(musb);
28c2c51c 2438
34e2beb2 2439fail1:
3df08dc7
LM		 2440 if (status != -EPROBE_DEFER)
2441 dev_err(musb->controller,
2442 "%s failed with status %d\n", __func__, status);
34e2beb2 2443
28c2c51c
FB		 2444 musb_free(musb);
2445
34e2beb2
SS		 2446fail0:
2447
28c2c51c
FB		 2448 return status;
2449
550a7375
FB		 2450}
2451
2452/*-------------------------------------------------------------------------*/
2453
2454/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2455 * bridge to a platform device; this driver then suffices.
2456 */
41ac7b3a 2457static int musb_probe(struct platform_device *pdev)
550a7375
FB		 2458{
2459 struct device *dev = &pdev->dev;
fcf173e4 2460 int irq = platform_get_irq_byname(pdev, "mc");
550a7375
FB		 2461 struct resource *iomem;
2462 void __iomem *base;
2463
1f79b26c 2464 if (irq <= 0)
550a7375
FB		 2465 return -ENODEV;
2466
1f79b26c 2467 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b42f7f30
FB		 2468 base = devm_ioremap_resource(dev, iomem);
2469 if (IS_ERR(base))
2470 return PTR_ERR(base);
550a7375 2471
b42f7f30 2472 return musb_init_controller(dev, irq, base);
550a7375
FB		 2473}
2474
fb4e98ab 2475static int musb_remove(struct platform_device *pdev)
550a7375 2476{
8d2421e6
AKG		 2477 struct device *dev = &pdev->dev;
2478 struct musb *musb = dev_to_musb(dev);
302f6802 2479 unsigned long flags;
550a7375
FB		 2480
2481 /* this gets called on rmmod.
2482 * - Host mode: host may still be active
2483 * - Peripheral mode: peripheral is deactivated (or never-activated)
2484 * - OTG mode: both roles are deactivated (or never-activated)
2485 */
7f7f9e2a 2486 musb_exit_debugfs(musb);
302f6802 2487
2bff3916 2488 cancel_delayed_work_sync(&musb->irq_work);
f730f205
TL		 2489 cancel_delayed_work_sync(&musb->finish_resume_work);
2490 cancel_delayed_work_sync(&musb->deassert_reset_work);
302f6802
TL		 2491 pm_runtime_get_sync(musb->controller);
2492 musb_host_cleanup(musb);
2493 musb_gadget_cleanup(musb);
e945953d 2494
302f6802 2495 musb_platform_disable(musb);
bc1e2154 2496 spin_lock_irqsave(&musb->lock, flags);
e945953d 2497 musb_disable_interrupts(musb);
302f6802 2498 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
e945953d
BL		 2499 spin_unlock_irqrestore(&musb->lock, flags);
2500
f730f205
TL		 2501 pm_runtime_dont_use_autosuspend(musb->controller);
2502 pm_runtime_put_sync(musb->controller);
2503 pm_runtime_disable(musb->controller);
302f6802 2504 musb_platform_exit(musb);
8055555f 2505 musb_phy_callback = NULL;
8d1aad74 2506 if (musb->dma_controller)
7f6283ed 2507 musb_dma_controller_destroy(musb->dma_controller);
39cee200 2508 usb_phy_shutdown(musb->xceiv);
550a7375 2509 musb_free(musb);
8d2421e6 2510 device_init_wakeup(dev, 0);
550a7375
FB		 2511 return 0;
2512}
2513
2514#ifdef CONFIG_PM
2515
3c8a5fcc 2516static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2517{
2518 int i;
2519 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2520 void __iomem *epio;
4f712e01 2521
032ec49f
FB		 2522 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2523 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2524 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
7421107b 2525 musb->context.power = musb_readb(musb_base, MUSB_POWER);
7421107b
FB		 2526 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2527 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2528 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2529
ae9b2ad2 2530 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2531 struct musb_hw_ep *hw_ep;
2532
2533 hw_ep = &musb->endpoints[i];
2534 if (!hw_ep)
2535 continue;
2536
2537 epio = hw_ep->regs;
2538 if (!epio)
2539 continue;
2540
ea737554 2541 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2542 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2543 musb_readw(epio, MUSB_TXMAXP);
7421107b 2544 musb->context.index_regs[i].txcsr =
ae9b2ad2 2545 musb_readw(epio, MUSB_TXCSR);
7421107b 2546 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2547 musb_readw(epio, MUSB_RXMAXP);
7421107b 2548 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2549 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2550
2551 if (musb->dyn_fifo) {
7421107b 2552 musb->context.index_regs[i].txfifoadd =
4f712e01 2553 musb_read_txfifoadd(musb_base);
7421107b 2554 musb->context.index_regs[i].rxfifoadd =
4f712e01 2555 musb_read_rxfifoadd(musb_base);
7421107b 2556 musb->context.index_regs[i].txfifosz =
4f712e01 2557 musb_read_txfifosz(musb_base);
7421107b 2558 musb->context.index_regs[i].rxfifosz =
4f712e01
AKG		 2559 musb_read_rxfifosz(musb_base);
2560 }
032ec49f
FB		 2561
2562 musb->context.index_regs[i].txtype =
2563 musb_readb(epio, MUSB_TXTYPE);
2564 musb->context.index_regs[i].txinterval =
2565 musb_readb(epio, MUSB_TXINTERVAL);
2566 musb->context.index_regs[i].rxtype =
2567 musb_readb(epio, MUSB_RXTYPE);
2568 musb->context.index_regs[i].rxinterval =
2569 musb_readb(epio, MUSB_RXINTERVAL);
2570
2571 musb->context.index_regs[i].txfunaddr =
6cc2af6d 2572 musb_read_txfunaddr(musb, i);
032ec49f 2573 musb->context.index_regs[i].txhubaddr =
6cc2af6d 2574 musb_read_txhubaddr(musb, i);
032ec49f 2575 musb->context.index_regs[i].txhubport =
6cc2af6d 2576 musb_read_txhubport(musb, i);
032ec49f
FB		 2577
2578 musb->context.index_regs[i].rxfunaddr =
6cc2af6d 2579 musb_read_rxfunaddr(musb, i);
032ec49f 2580 musb->context.index_regs[i].rxhubaddr =
6cc2af6d 2581 musb_read_rxhubaddr(musb, i);
032ec49f 2582 musb->context.index_regs[i].rxhubport =
6cc2af6d 2583 musb_read_rxhubport(musb, i);
4f712e01 2584 }
4f712e01
AKG		 2585}
2586
3c8a5fcc 2587static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2588{
2589 int i;
2590 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2591 void __iomem *epio;
33f8d75f 2592 u8 power;
4f712e01 2593
032ec49f
FB		 2594 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2595 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2596 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
33f8d75f
RQ		 2597
2598 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2599 power = musb_readb(musb_base, MUSB_POWER);
2600 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2601 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2602 power |= musb->context.power;
2603 musb_writeb(musb_base, MUSB_POWER, power);
2604
b18d26f6 2605 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
af5ec14d 2606 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
7421107b 2607 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
84ac5d11
BL		 2608 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2609 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2610
ae9b2ad2 2611 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2612 struct musb_hw_ep *hw_ep;
2613
2614 hw_ep = &musb->endpoints[i];
2615 if (!hw_ep)
2616 continue;
2617
2618 epio = hw_ep->regs;
2619 if (!epio)
2620 continue;
2621
ea737554 2622 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2623 musb_writew(epio, MUSB_TXMAXP,
7421107b 2624 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2625 musb_writew(epio, MUSB_TXCSR,
7421107b 2626 musb->context.index_regs[i].txcsr);
ae9b2ad2 2627 musb_writew(epio, MUSB_RXMAXP,
7421107b 2628 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2629 musb_writew(epio, MUSB_RXCSR,
7421107b 2630 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2631
2632 if (musb->dyn_fifo) {
2633 musb_write_txfifosz(musb_base,
7421107b 2634 musb->context.index_regs[i].txfifosz);
4f712e01 2635 musb_write_rxfifosz(musb_base,
7421107b 2636 musb->context.index_regs[i].rxfifosz);
4f712e01 2637 musb_write_txfifoadd(musb_base,
7421107b 2638 musb->context.index_regs[i].txfifoadd);
4f712e01 2639 musb_write_rxfifoadd(musb_base,
7421107b 2640 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2641 }
2642
032ec49f 2643 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2644 musb->context.index_regs[i].txtype);
032ec49f 2645 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2646 musb->context.index_regs[i].txinterval);
032ec49f 2647 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2648 musb->context.index_regs[i].rxtype);
032ec49f 2649 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2650
032ec49f 2651 musb->context.index_regs[i].rxinterval);
6cc2af6d 2652 musb_write_txfunaddr(musb, i,
7421107b 2653 musb->context.index_regs[i].txfunaddr);
6cc2af6d 2654 musb_write_txhubaddr(musb, i,
7421107b 2655 musb->context.index_regs[i].txhubaddr);
6cc2af6d 2656 musb_write_txhubport(musb, i,
7421107b 2657 musb->context.index_regs[i].txhubport);
4f712e01 2658
6cc2af6d 2659 musb_write_rxfunaddr(musb, i,
7421107b 2660 musb->context.index_regs[i].rxfunaddr);
6cc2af6d 2661 musb_write_rxhubaddr(musb, i,
7421107b 2662 musb->context.index_regs[i].rxhubaddr);
6cc2af6d 2663 musb_write_rxhubport(musb, i,
7421107b 2664 musb->context.index_regs[i].rxhubport);
4f712e01 2665 }
3c5fec75 2666 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2667}
2668
48fea965 2669static int musb_suspend(struct device *dev)
550a7375 2670{
8220796d 2671 struct musb *musb = dev_to_musb(dev);
550a7375 2672 unsigned long flags;
082df8be
JH		 2673 int ret;
2674
2675 ret = pm_runtime_get_sync(dev);
2676 if (ret < 0) {
2677 pm_runtime_put_noidle(dev);
2678 return ret;
2679 }
550a7375 2680
6fc6f4b8 2681 musb_platform_disable(musb);
e945953d 2682 musb_disable_interrupts(musb);
0c3aae9b
JH		 2683
2684 musb->flush_irq_work = true;
2685 while (flush_delayed_work(&musb->irq_work))
2686 ;
2687 musb->flush_irq_work = false;
2688
a926ed11
AB		 2689 if (!(musb->io.quirks & MUSB_PRESERVE_SESSION))
2690 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
0c3aae9b 2691
ea2f35c0 2692 WARN_ON(!list_empty(&musb->pending_list));
6fc6f4b8 2693
550a7375
FB		 2694 spin_lock_irqsave(&musb->lock, flags);
2695
2696 if (is_peripheral_active(musb)) {
2697 /* FIXME force disconnect unless we know USB will wake
2698 * the system up quickly enough to respond ...
2699 */
2700 } else if (is_host_active(musb)) {
2701 /* we know all the children are suspended; sometimes
2702 * they will even be wakeup-enabled.
2703 */
2704 }
2705
c338412b
DM		 2706 musb_save_context(musb);
2707
550a7375
FB		 2708 spin_unlock_irqrestore(&musb->lock, flags);
2709 return 0;
2710}
2711
3e87d9a3 2712static int musb_resume(struct device *dev)
550a7375 2713{
ea2f35c0
TL		 2714 struct musb *musb = dev_to_musb(dev);
2715 unsigned long flags;
2716 int error;
2717 u8 devctl;
2718 u8 mask;
c338412b
DM		 2719
2720 /*
2721 * For static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2722 * unless for some reason the whole soc powered down or the USB
2723 * module got reset through the PSC (vs just being disabled).
c338412b
DM		 2724 *
2725 * For the DSPS glue layer though, a full register restore has to
2726 * be done. As it shouldn't harm other platforms, we do it
2727 * unconditionally.
550a7375 2728 */
c338412b
DM		 2729
2730 musb_restore_context(musb);
2731
b87fd2f7
SAS		 2732 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2733 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2734 if ((devctl & mask) != (musb->context.devctl & mask))
2735 musb->port1_status = 0;
a1fc1920 2736
6fc6f4b8
PH		 2737 musb_start(musb);
2738
ea2f35c0
TL		 2739 spin_lock_irqsave(&musb->lock, flags);
2740 error = musb_run_resume_work(musb);
2741 if (error)
2742 dev_err(musb->controller, "resume work failed with %i\n",
2743 error);
2744 spin_unlock_irqrestore(&musb->lock, flags);
2745
082df8be
JH		 2746 pm_runtime_mark_last_busy(dev);
2747 pm_runtime_put_autosuspend(dev);
2748
550a7375
FB		 2749 return 0;
2750}
2751
7acc6197
HH		 2752static int musb_runtime_suspend(struct device *dev)
2753{
2754 struct musb *musb = dev_to_musb(dev);
2755
2756 musb_save_context(musb);
ea2f35c0 2757 musb->is_runtime_suspended = 1;
7acc6197
HH		 2758
2759 return 0;
2760}
2761
2762static int musb_runtime_resume(struct device *dev)
2763{
ea2f35c0
TL		 2764 struct musb *musb = dev_to_musb(dev);
2765 unsigned long flags;
2766 int error;
7acc6197
HH		 2767
2768 /*
2769 * When pm_runtime_get_sync called for the first time in driver
2770 * init, some of the structure is still not initialized which is
2771 * used in restore function. But clock needs to be
2772 * enabled before any register access, so
2773 * pm_runtime_get_sync has to be called.
2774 * Also context restore without save does not make
2775 * any sense
2776 */
c723bd6e
TL		 2777 if (!musb->is_initialized)
2778 return 0;
2779
2780 musb_restore_context(musb);
7acc6197 2781
ea2f35c0
TL		 2782 spin_lock_irqsave(&musb->lock, flags);
2783 error = musb_run_resume_work(musb);
2784 if (error)
2785 dev_err(musb->controller, "resume work failed with %i\n",
2786 error);
2787 musb->is_runtime_suspended = 0;
2788 spin_unlock_irqrestore(&musb->lock, flags);
2789
7acc6197
HH		 2790 return 0;
2791}
2792
47145210 2793static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965 2794 .suspend = musb_suspend,
3e87d9a3 2795 .resume = musb_resume,
7acc6197
HH		 2796 .runtime_suspend = musb_runtime_suspend,
2797 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2798};
2799
2800#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2801#else
48fea965 2802#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2803#endif
2804
2805static struct platform_driver musb_driver = {
2806 .driver = {
2807 .name = (char *)musb_driver_name,
2808 .bus = &platform_bus_type,
48fea965 2809 .pm = MUSB_DEV_PM_OPS,
550a7375 2810 },
e9e8c85e 2811 .probe = musb_probe,
7690417d 2812 .remove = musb_remove,
550a7375
FB		 2813};
2814
89f836a8 2815module_platform_driver(musb_driver);
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