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[mirror_ubuntu-bionic-kernel.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375 85 * - platform_device for addressing, irq, and platform_data
5ae477b0 86 * - platform_data is mostly for board-specific information
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
550a7375
FB		 96#include <linux/list.h>
97#include <linux/kobject.h>
9303961f 98#include <linux/prefetch.h>
550a7375
FB		 99#include <linux/platform_device.h>
100#include <linux/io.h>
8d2421e6 101#include <linux/dma-mapping.h>
309be239 102#include <linux/usb.h>
830fc64c 103#include <linux/usb/of.h>
550a7375 104
550a7375 105#include "musb_core.h"
c74173fd 106#include "musb_trace.h"
550a7375 107
f7f9d63e 108#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 109
110
550a7375
FB		 111#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
112#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
113
e8164f64 114#define MUSB_VERSION "6.0"
550a7375
FB		 115
116#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
117
05ac10dd 118#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375
FB		 119const char musb_driver_name[] = MUSB_DRIVER_NAME;
120
121MODULE_DESCRIPTION(DRIVER_INFO);
122MODULE_AUTHOR(DRIVER_AUTHOR);
123MODULE_LICENSE("GPL");
124MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
125
126
127/*-------------------------------------------------------------------------*/
128
129static inline struct musb *dev_to_musb(struct device *dev)
130{
550a7375 131 return dev_get_drvdata(dev);
550a7375
FB		 132}
133
830fc64c
PK		 134enum musb_mode musb_get_mode(struct device *dev)
135{
136 enum usb_dr_mode mode;
137
138 mode = usb_get_dr_mode(dev);
139 switch (mode) {
140 case USB_DR_MODE_HOST:
141 return MUSB_HOST;
142 case USB_DR_MODE_PERIPHERAL:
143 return MUSB_PERIPHERAL;
144 case USB_DR_MODE_OTG:
145 case USB_DR_MODE_UNKNOWN:
146 default:
147 return MUSB_OTG;
148 }
149}
150EXPORT_SYMBOL_GPL(musb_get_mode);
151
550a7375
FB		 152/*-------------------------------------------------------------------------*/
153
ffb865b1 154#ifndef CONFIG_BLACKFIN
705e63d2 155static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
ffb865b1 156{
b96d3b08 157 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 158 int i = 0;
159 u8 r;
160 u8 power;
bf070bc1
GI		 161 int ret;
162
163 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 164
165 /* Make sure the transceiver is not in low power mode */
166 power = musb_readb(addr, MUSB_POWER);
167 power &= ~MUSB_POWER_SUSPENDM;
168 musb_writeb(addr, MUSB_POWER, power);
169
170 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
171 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
172 */
173
705e63d2 174 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
ffb865b1
HK		 175 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
176 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
177
178 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
179 & MUSB_ULPI_REG_CMPLT)) {
180 i++;
bf070bc1
GI		 181 if (i == 10000) {
182 ret = -ETIMEDOUT;
183 goto out;
184 }
ffb865b1
HK		 185
186 }
187 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
188 r &= ~MUSB_ULPI_REG_CMPLT;
189 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
190
bf070bc1
GI		 191 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
192
193out:
194 pm_runtime_put(phy->io_dev);
195
196 return ret;
ffb865b1
HK		 197}
198
705e63d2 199static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
ffb865b1 200{
b96d3b08 201 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 202 int i = 0;
203 u8 r = 0;
204 u8 power;
bf070bc1
GI		 205 int ret = 0;
206
207 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 208
209 /* Make sure the transceiver is not in low power mode */
210 power = musb_readb(addr, MUSB_POWER);
211 power &= ~MUSB_POWER_SUSPENDM;
212 musb_writeb(addr, MUSB_POWER, power);
213
705e63d2
UKK		 214 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
215 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
ffb865b1
HK		 216 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
217
218 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
219 & MUSB_ULPI_REG_CMPLT)) {
220 i++;
bf070bc1
GI		 221 if (i == 10000) {
222 ret = -ETIMEDOUT;
223 goto out;
224 }
ffb865b1
HK		 225 }
226
227 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
228 r &= ~MUSB_ULPI_REG_CMPLT;
229 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
230
bf070bc1
GI		 231out:
232 pm_runtime_put(phy->io_dev);
233
234 return ret;
ffb865b1
HK		 235}
236#else
f2263db7
MF		 237#define musb_ulpi_read NULL
238#define musb_ulpi_write NULL
ffb865b1
HK		 239#endif
240
b96d3b08 241static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 242 .read = musb_ulpi_read,
243 .write = musb_ulpi_write,
244};
245
246/*-------------------------------------------------------------------------*/
247
1b40fc57
TL		 248static u32 musb_default_fifo_offset(u8 epnum)
249{
250 return 0x20 + (epnum * 4);
251}
252
d026e9c7
TL		 253/* "flat" mapping: each endpoint has its own i/o address */
254static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
255{
256}
257
258static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
259{
260 return 0x100 + (0x10 * epnum) + offset;
261}
262
263/* "indexed" mapping: INDEX register controls register bank select */
264static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
265{
266 musb_writeb(mbase, MUSB_INDEX, epnum);
267}
268
269static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
270{
271 return 0x10 + offset;
272}
273
6cc2af6d
HG		 274static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
275{
276 return 0x80 + (0x08 * epnum) + offset;
277}
278
1b40fc57
TL		 279static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
280{
c74173fd
BL		 281 u8 data = __raw_readb(addr + offset);
282
283 trace_musb_readb(__builtin_return_address(0), addr, offset, data);
284 return data;
1b40fc57
TL		 285}
286
287static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
288{
c74173fd 289 trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 290 __raw_writeb(data, addr + offset);
291}
292
293static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
294{
c74173fd
BL		 295 u16 data = __raw_readw(addr + offset);
296
297 trace_musb_readw(__builtin_return_address(0), addr, offset, data);
298 return data;
1b40fc57
TL		 299}
300
301static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
302{
c74173fd 303 trace_musb_writew(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 304 __raw_writew(data, addr + offset);
305}
306
307static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
308{
c74173fd
BL		 309 u32 data = __raw_readl(addr + offset);
310
311 trace_musb_readl(__builtin_return_address(0), addr, offset, data);
312 return data;
1b40fc57
TL		 313}
314
315static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
316{
c74173fd 317 trace_musb_writel(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 318 __raw_writel(data, addr + offset);
319}
c6cf8b00 320
550a7375
FB		 321/*
322 * Load an endpoint's FIFO
323 */
1b40fc57
TL		 324static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
325 const u8 *src)
550a7375 326{
5c8a86e1 327 struct musb *musb = hw_ep->musb;
550a7375
FB		 328 void __iomem *fifo = hw_ep->fifo;
329
603fe2b2
AKG		 330 if (unlikely(len == 0))
331 return;
332
550a7375
FB		 333 prefetch((u8 *)src);
334
5c8a86e1 335 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 336 'T', hw_ep->epnum, fifo, len, src);
337
338 /* we can't assume unaligned reads work */
339 if (likely((0x01 & (unsigned long) src) == 0)) {
340 u16 index = 0;
341
342 /* best case is 32bit-aligned source address */
343 if ((0x02 & (unsigned long) src) == 0) {
344 if (len >= 4) {
2bf0a8f6 345 iowrite32_rep(fifo, src + index, len >> 2);
550a7375
FB		 346 index += len & ~0x03;
347 }
348 if (len & 0x02) {
be780381 349 __raw_writew(*(u16 *)&src[index], fifo);
550a7375
FB		 350 index += 2;
351 }
352 } else {
353 if (len >= 2) {
2bf0a8f6 354 iowrite16_rep(fifo, src + index, len >> 1);
550a7375
FB		 355 index += len & ~0x01;
356 }
357 }
358 if (len & 0x01)
be780381 359 __raw_writeb(src[index], fifo);
550a7375
FB		 360 } else {
361 /* byte aligned */
2bf0a8f6 362 iowrite8_rep(fifo, src, len);
550a7375
FB		 363 }
364}
365
366/*
367 * Unload an endpoint's FIFO
368 */
1b40fc57 369static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
550a7375 370{
5c8a86e1 371 struct musb *musb = hw_ep->musb;
550a7375
FB		 372 void __iomem *fifo = hw_ep->fifo;
373
603fe2b2
AKG		 374 if (unlikely(len == 0))
375 return;
376
5c8a86e1 377 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 378 'R', hw_ep->epnum, fifo, len, dst);
379
380 /* we can't assume unaligned writes work */
381 if (likely((0x01 & (unsigned long) dst) == 0)) {
382 u16 index = 0;
383
384 /* best case is 32bit-aligned destination address */
385 if ((0x02 & (unsigned long) dst) == 0) {
386 if (len >= 4) {
2bf0a8f6 387 ioread32_rep(fifo, dst, len >> 2);
550a7375
FB		 388 index = len & ~0x03;
389 }
390 if (len & 0x02) {
be780381 391 *(u16 *)&dst[index] = __raw_readw(fifo);
550a7375
FB		 392 index += 2;
393 }
394 } else {
395 if (len >= 2) {
2bf0a8f6 396 ioread16_rep(fifo, dst, len >> 1);
550a7375
FB		 397 index = len & ~0x01;
398 }
399 }
400 if (len & 0x01)
be780381 401 dst[index] = __raw_readb(fifo);
550a7375
FB		 402 } else {
403 /* byte aligned */
2bf0a8f6 404 ioread8_rep(fifo, dst, len);
550a7375
FB		 405 }
406}
407
1b40fc57
TL		 408/*
409 * Old style IO functions
410 */
411u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
412EXPORT_SYMBOL_GPL(musb_readb);
413
414void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
415EXPORT_SYMBOL_GPL(musb_writeb);
550a7375 416
1b40fc57
TL		 417u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
418EXPORT_SYMBOL_GPL(musb_readw);
419
420void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
421EXPORT_SYMBOL_GPL(musb_writew);
422
423u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
424EXPORT_SYMBOL_GPL(musb_readl);
425
426void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
427EXPORT_SYMBOL_GPL(musb_writel);
428
7f6283ed
TL		 429#ifndef CONFIG_MUSB_PIO_ONLY
430struct dma_controller *
431(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
432EXPORT_SYMBOL(musb_dma_controller_create);
433
434void (*musb_dma_controller_destroy)(struct dma_controller *c);
435EXPORT_SYMBOL(musb_dma_controller_destroy);
436#endif
437
1b40fc57
TL		 438/*
439 * New style IO functions
440 */
441void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
442{
443 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
444}
445
446void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
447{
448 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
449}
550a7375
FB		 450
451/*-------------------------------------------------------------------------*/
452
453/* for high speed test mode; see USB 2.0 spec 7.1.20 */
454static const u8 musb_test_packet[53] = {
455 /* implicit SYNC then DATA0 to start */
456
457 /* JKJKJKJK x9 */
458 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
459 /* JJKKJJKK x8 */
460 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
461 /* JJJJKKKK x8 */
462 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
463 /* JJJJJJJKKKKKKK x8 */
464 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
465 /* JJJJJJJK x8 */
466 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
467 /* JKKKKKKK x10, JK */
468 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
469
470 /* implicit CRC16 then EOP to end */
471};
472
473void musb_load_testpacket(struct musb *musb)
474{
475 void __iomem *regs = musb->endpoints[0].regs;
476
477 musb_ep_select(musb->mregs, 0);
478 musb_write_fifo(musb->control_ep,
479 sizeof(musb_test_packet), musb_test_packet);
480 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
481}
482
483/*-------------------------------------------------------------------------*/
484
550a7375
FB		 485/*
486 * Handles OTG hnp timeouts, such as b_ase0_brst
487 */
a156544b 488static void musb_otg_timer_func(unsigned long data)
550a7375
FB		 489{
490 struct musb *musb = (struct musb *)data;
491 unsigned long flags;
492
493 spin_lock_irqsave(&musb->lock, flags);
e47d9254 494 switch (musb->xceiv->otg->state) {
550a7375 495 case OTG_STATE_B_WAIT_ACON:
b99d3659
BL		 496 musb_dbg(musb,
497 "HNP: b_wait_acon timeout; back to b_peripheral");
550a7375 498 musb_g_disconnect(musb);
e47d9254 499 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 500 musb->is_active = 0;
501 break;
ab983f2a 502 case OTG_STATE_A_SUSPEND:
550a7375 503 case OTG_STATE_A_WAIT_BCON:
b99d3659 504 musb_dbg(musb, "HNP: %s timeout",
e47d9254 505 usb_otg_state_string(musb->xceiv->otg->state));
743411b3 506 musb_platform_set_vbus(musb, 0);
e47d9254 507 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 508 break;
509 default:
b99d3659 510 musb_dbg(musb, "HNP: Unhandled mode %s",
e47d9254 511 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 512 }
550a7375
FB		 513 spin_unlock_irqrestore(&musb->lock, flags);
514}
515
550a7375 516/*
f7f9d63e 517 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 518 */
519void musb_hnp_stop(struct musb *musb)
520{
8b125df5 521 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 522 void __iomem *mbase = musb->mregs;
523 u8 reg;
524
b99d3659 525 musb_dbg(musb, "HNP: stop from %s",
e47d9254 526 usb_otg_state_string(musb->xceiv->otg->state));
ab983f2a 527
e47d9254 528 switch (musb->xceiv->otg->state) {
550a7375 529 case OTG_STATE_A_PERIPHERAL:
550a7375 530 musb_g_disconnect(musb);
b99d3659 531 musb_dbg(musb, "HNP: back to %s",
e47d9254 532 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 533 break;
534 case OTG_STATE_B_HOST:
b99d3659 535 musb_dbg(musb, "HNP: Disabling HR");
74c2e936
DM		 536 if (hcd)
537 hcd->self.is_b_host = 0;
e47d9254 538 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 539 MUSB_DEV_MODE(musb);
540 reg = musb_readb(mbase, MUSB_POWER);
541 reg |= MUSB_POWER_SUSPENDM;
542 musb_writeb(mbase, MUSB_POWER, reg);
543 /* REVISIT: Start SESSION_REQUEST here? */
544 break;
545 default:
b99d3659 546 musb_dbg(musb, "HNP: Stopping in unknown state %s",
e47d9254 547 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 548 }
549
550 /*
551 * When returning to A state after HNP, avoid hub_port_rebounce(),
552 * which cause occasional OPT A "Did not receive reset after connect"
553 * errors.
554 */
749da5f8 555 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 556}
557
83b8f5b8 558static void musb_recover_from_babble(struct musb *musb);
e1eb3eb8 559
550a7375
FB		 560/*
561 * Interrupt Service Routine to record USB "global" interrupts.
562 * Since these do not happen often and signify things of
563 * paramount importance, it seems OK to check them individually;
564 * the order of the tests is specified in the manual
565 *
566 * @param musb instance pointer
567 * @param int_usb register contents
568 * @param devctl
569 * @param power
570 */
571
550a7375 572static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 573 u8 devctl)
550a7375
FB		 574{
575 irqreturn_t handled = IRQ_NONE;
550a7375 576
b99d3659 577 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
550a7375
FB		 578
579 /* in host mode, the peripheral may issue remote wakeup.
580 * in peripheral mode, the host may resume the link.
581 * spurious RESUME irqs happen too, paired with SUSPEND.
582 */
583 if (int_usb & MUSB_INTR_RESUME) {
584 handled = IRQ_HANDLED;
b99d3659 585 musb_dbg(musb, "RESUME (%s)",
0acff6b8 586 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 587
588 if (devctl & MUSB_DEVCTL_HM) {
e47d9254 589 switch (musb->xceiv->otg->state) {
550a7375 590 case OTG_STATE_A_SUSPEND:
65322797 591 /* remote wakeup? */
550a7375
FB		 592 musb->port1_status |=
593 (USB_PORT_STAT_C_SUSPEND << 16)
594 | MUSB_PORT_STAT_RESUME;
30d361bf 595 musb->rh_timer = jiffies
309be239 596 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
e47d9254 597 musb->xceiv->otg->state = OTG_STATE_A_HOST;
550a7375 598 musb->is_active = 1;
9298b4aa 599 musb_host_resume_root_hub(musb);
407788b5
TL		 600 schedule_delayed_work(&musb->finish_resume_work,
601 msecs_to_jiffies(USB_RESUME_TIMEOUT));
550a7375
FB		 602 break;
603 case OTG_STATE_B_WAIT_ACON:
e47d9254 604 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 605 musb->is_active = 1;
606 MUSB_DEV_MODE(musb);
607 break;
608 default:
609 WARNING("bogus %s RESUME (%s)\n",
610 "host",
e47d9254 611 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 612 }
550a7375 613 } else {
e47d9254 614 switch (musb->xceiv->otg->state) {
550a7375
FB		 615 case OTG_STATE_A_SUSPEND:
616 /* possibly DISCONNECT is upcoming */
e47d9254 617 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44 618 musb_host_resume_root_hub(musb);
550a7375 619 break;
550a7375
FB		 620 case OTG_STATE_B_WAIT_ACON:
621 case OTG_STATE_B_PERIPHERAL:
622 /* disconnect while suspended? we may
623 * not get a disconnect irq...
624 */
625 if ((devctl & MUSB_DEVCTL_VBUS)
626 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
627 ) {
628 musb->int_usb |= MUSB_INTR_DISCONNECT;
629 musb->int_usb &= ~MUSB_INTR_SUSPEND;
630 break;
631 }
632 musb_g_resume(musb);
633 break;
634 case OTG_STATE_B_IDLE:
635 musb->int_usb &= ~MUSB_INTR_SUSPEND;
636 break;
550a7375
FB		 637 default:
638 WARNING("bogus %s RESUME (%s)\n",
639 "peripheral",
e47d9254 640 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 641 }
642 }
643 }
644
550a7375
FB		 645 /* see manual for the order of the tests */
646 if (int_usb & MUSB_INTR_SESSREQ) {
aa471456
FB		 647 void __iomem *mbase = musb->mregs;
648
19aab56c
HK		 649 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
650 && (devctl & MUSB_DEVCTL_BDEVICE)) {
b99d3659 651 musb_dbg(musb, "SessReq while on B state");
a6038ee7
HK		 652 return IRQ_HANDLED;
653 }
654
b99d3659 655 musb_dbg(musb, "SESSION_REQUEST (%s)",
e47d9254 656 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 657
658 /* IRQ arrives from ID pin sense or (later, if VBUS power
659 * is removed) SRP. responses are time critical:
660 * - turn on VBUS (with silicon-specific mechanism)
661 * - go through A_WAIT_VRISE
662 * - ... to A_WAIT_BCON.
663 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
664 */
665 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
666 musb->ep0_stage = MUSB_EP0_START;
e47d9254 667 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
550a7375 668 MUSB_HST_MODE(musb);
743411b3 669 musb_platform_set_vbus(musb, 1);
550a7375
FB		 670
671 handled = IRQ_HANDLED;
672 }
673
674 if (int_usb & MUSB_INTR_VBUSERROR) {
675 int ignore = 0;
676
677 /* During connection as an A-Device, we may see a short
678 * current spikes causing voltage drop, because of cable
679 * and peripheral capacitance combined with vbus draw.
680 * (So: less common with truly self-powered devices, where
681 * vbus doesn't act like a power supply.)
682 *
683 * Such spikes are short; usually less than ~500 usec, max
684 * of ~2 msec. That is, they're not sustained overcurrent
685 * errors, though they're reported using VBUSERROR irqs.
686 *
687 * Workarounds: (a) hardware: use self powered devices.
688 * (b) software: ignore non-repeated VBUS errors.
689 *
690 * REVISIT: do delays from lots of DEBUG_KERNEL checks
691 * make trouble here, keeping VBUS < 4.4V ?
692 */
e47d9254 693 switch (musb->xceiv->otg->state) {
550a7375
FB		 694 case OTG_STATE_A_HOST:
695 /* recovery is dicey once we've gotten past the
696 * initial stages of enumeration, but if VBUS
697 * stayed ok at the other end of the link, and
698 * another reset is due (at least for high speed,
699 * to redo the chirp etc), it might work OK...
700 */
701 case OTG_STATE_A_WAIT_BCON:
702 case OTG_STATE_A_WAIT_VRISE:
703 if (musb->vbuserr_retry) {
aa471456
FB		 704 void __iomem *mbase = musb->mregs;
705
550a7375
FB		 706 musb->vbuserr_retry--;
707 ignore = 1;
708 devctl |= MUSB_DEVCTL_SESSION;
709 musb_writeb(mbase, MUSB_DEVCTL, devctl);
710 } else {
711 musb->port1_status |=
749da5f8
AS		 712 USB_PORT_STAT_OVERCURRENT
713 | (USB_PORT_STAT_C_OVERCURRENT << 16);
550a7375
FB		 714 }
715 break;
716 default:
717 break;
718 }
719
54485116
GI		 720 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
721 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
e47d9254 722 usb_otg_state_string(musb->xceiv->otg->state),
550a7375
FB		 723 devctl,
724 ({ char *s;
725 switch (devctl & MUSB_DEVCTL_VBUS) {
726 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
727 s = "<SessEnd"; break;
728 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
729 s = "<AValid"; break;
730 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
731 s = "<VBusValid"; break;
732 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
733 default:
734 s = "VALID"; break;
2b84f92b 735 } s; }),
550a7375
FB		 736 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
737 musb->port1_status);
738
739 /* go through A_WAIT_VFALL then start a new session */
740 if (!ignore)
743411b3 741 musb_platform_set_vbus(musb, 0);
550a7375
FB		 742 handled = IRQ_HANDLED;
743 }
744
1c25fda4 745 if (int_usb & MUSB_INTR_SUSPEND) {
b99d3659 746 musb_dbg(musb, "SUSPEND (%s) devctl %02x",
e47d9254 747 usb_otg_state_string(musb->xceiv->otg->state), devctl);
1c25fda4
AM		 748 handled = IRQ_HANDLED;
749
e47d9254 750 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 751 case OTG_STATE_A_PERIPHERAL:
752 /* We also come here if the cable is removed, since
753 * this silicon doesn't report ID-no-longer-grounded.
754 *
755 * We depend on T(a_wait_bcon) to shut us down, and
756 * hope users don't do anything dicey during this
757 * undesired detour through A_WAIT_BCON.
758 */
759 musb_hnp_stop(musb);
0b3eba44 760 musb_host_resume_root_hub(musb);
1c25fda4
AM		 761 musb_root_disconnect(musb);
762 musb_platform_try_idle(musb, jiffies
763 + msecs_to_jiffies(musb->a_wait_bcon
764 ? : OTG_TIME_A_WAIT_BCON));
765
766 break;
1c25fda4
AM		 767 case OTG_STATE_B_IDLE:
768 if (!musb->is_active)
769 break;
770 case OTG_STATE_B_PERIPHERAL:
771 musb_g_suspend(musb);
eee3f15d 772 musb->is_active = musb->g.b_hnp_enable;
1c25fda4 773 if (musb->is_active) {
e47d9254 774 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
b99d3659 775 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
1c25fda4
AM		 776 mod_timer(&musb->otg_timer, jiffies
777 + msecs_to_jiffies(
778 OTG_TIME_B_ASE0_BRST));
1c25fda4
AM		 779 }
780 break;
781 case OTG_STATE_A_WAIT_BCON:
782 if (musb->a_wait_bcon != 0)
783 musb_platform_try_idle(musb, jiffies
784 + msecs_to_jiffies(musb->a_wait_bcon));
785 break;
786 case OTG_STATE_A_HOST:
e47d9254 787 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
eee3f15d 788 musb->is_active = musb->hcd->self.b_hnp_enable;
1c25fda4
AM		 789 break;
790 case OTG_STATE_B_HOST:
791 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
b99d3659 792 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
1c25fda4
AM		 793 break;
794 default:
795 /* "should not happen" */
796 musb->is_active = 0;
797 break;
798 }
799 }
800
550a7375 801 if (int_usb & MUSB_INTR_CONNECT) {
8b125df5 802 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 803
804 handled = IRQ_HANDLED;
805 musb->is_active = 1;
550a7375
FB		 806
807 musb->ep0_stage = MUSB_EP0_START;
808
b18d26f6
SAS		 809 musb->intrtxe = musb->epmask;
810 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
af5ec14d
SAS		 811 musb->intrrxe = musb->epmask & 0xfffe;
812 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
d709d22e 813 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 814 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
815 |USB_PORT_STAT_HIGH_SPEED
816 |USB_PORT_STAT_ENABLE
817 );
818 musb->port1_status |= USB_PORT_STAT_CONNECTION
819 |(USB_PORT_STAT_C_CONNECTION << 16);
820
821 /* high vs full speed is just a guess until after reset */
822 if (devctl & MUSB_DEVCTL_LSDEV)
823 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
824
550a7375 825 /* indicate new connection to OTG machine */
e47d9254 826 switch (musb->xceiv->otg->state) {
550a7375
FB		 827 case OTG_STATE_B_PERIPHERAL:
828 if (int_usb & MUSB_INTR_SUSPEND) {
b99d3659 829 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
550a7375 830 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 831 goto b_host;
550a7375 832 } else
b99d3659 833 musb_dbg(musb, "CONNECT as b_peripheral???");
550a7375
FB		 834 break;
835 case OTG_STATE_B_WAIT_ACON:
b99d3659 836 musb_dbg(musb, "HNP: CONNECT, now b_host");
1de00dae 837b_host:
e47d9254 838 musb->xceiv->otg->state = OTG_STATE_B_HOST;
74c2e936
DM		 839 if (musb->hcd)
840 musb->hcd->self.is_b_host = 1;
1de00dae 841 del_timer(&musb->otg_timer);
550a7375
FB		 842 break;
843 default:
844 if ((devctl & MUSB_DEVCTL_VBUS)
845 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
e47d9254 846 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44
DM		 847 if (hcd)
848 hcd->self.is_b_host = 0;
550a7375
FB		 849 }
850 break;
851 }
1de00dae 852
0b3eba44 853 musb_host_poke_root_hub(musb);
1de00dae 854
b99d3659 855 musb_dbg(musb, "CONNECT (%s) devctl %02x",
e47d9254 856 usb_otg_state_string(musb->xceiv->otg->state), devctl);
550a7375 857 }
550a7375 858
6d349671 859 if (int_usb & MUSB_INTR_DISCONNECT) {
b99d3659 860 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
e47d9254 861 usb_otg_state_string(musb->xceiv->otg->state),
1c25fda4
AM		 862 MUSB_MODE(musb), devctl);
863 handled = IRQ_HANDLED;
864
e47d9254 865 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 866 case OTG_STATE_A_HOST:
867 case OTG_STATE_A_SUSPEND:
0b3eba44 868 musb_host_resume_root_hub(musb);
1c25fda4 869 musb_root_disconnect(musb);
032ec49f 870 if (musb->a_wait_bcon != 0)
1c25fda4
AM		 871 musb_platform_try_idle(musb, jiffies
872 + msecs_to_jiffies(musb->a_wait_bcon));
873 break;
1c25fda4
AM		 874 case OTG_STATE_B_HOST:
875 /* REVISIT this behaves for "real disconnect"
876 * cases; make sure the other transitions from
877 * from B_HOST act right too. The B_HOST code
878 * in hnp_stop() is currently not used...
879 */
880 musb_root_disconnect(musb);
74c2e936
DM		 881 if (musb->hcd)
882 musb->hcd->self.is_b_host = 0;
e47d9254 883 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1c25fda4
AM		 884 MUSB_DEV_MODE(musb);
885 musb_g_disconnect(musb);
886 break;
887 case OTG_STATE_A_PERIPHERAL:
888 musb_hnp_stop(musb);
889 musb_root_disconnect(musb);
890 /* FALLTHROUGH */
891 case OTG_STATE_B_WAIT_ACON:
892 /* FALLTHROUGH */
1c25fda4
AM		 893 case OTG_STATE_B_PERIPHERAL:
894 case OTG_STATE_B_IDLE:
895 musb_g_disconnect(musb);
896 break;
1c25fda4
AM		 897 default:
898 WARNING("unhandled DISCONNECT transition (%s)\n",
e47d9254 899 usb_otg_state_string(musb->xceiv->otg->state));
1c25fda4
AM		 900 break;
901 }
902 }
903
550a7375
FB		 904 /* mentor saves a bit: bus reset and babble share the same irq.
905 * only host sees babble; only peripheral sees bus reset.
906 */
907 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 908 handled = IRQ_HANDLED;
896f7ea3 909 if (devctl & MUSB_DEVCTL_HM) {
550a7375 910 /*
34754dec 911 * When BABBLE happens what we can depends on which
28378d5e
FB		 912 * platform MUSB is running, because some platforms
913 * implemented proprietary means for 'recovering' from
914 * Babble conditions. One such platform is AM335x. In
34754dec
FB		 915 * most cases, however, the only thing we can do is
916 * drop the session.
550a7375 917 */
34754dec 918 dev_err(musb->controller, "Babble\n");
d0fc0a20 919
34754dec
FB		 920 if (is_host_active(musb))
921 musb_recover_from_babble(musb);
a04d46d0 922 } else {
b99d3659 923 musb_dbg(musb, "BUS RESET as %s",
e47d9254
AT		 924 usb_otg_state_string(musb->xceiv->otg->state));
925 switch (musb->xceiv->otg->state) {
550a7375 926 case OTG_STATE_A_SUSPEND:
550a7375
FB		 927 musb_g_reset(musb);
928 /* FALLTHROUGH */
929 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e 930 /* never use invalid T(a_wait_bcon) */
b99d3659 931 musb_dbg(musb, "HNP: in %s, %d msec timeout",
e47d9254 932 usb_otg_state_string(musb->xceiv->otg->state),
3df00453 933 TA_WAIT_BCON(musb));
f7f9d63e
DB		 934 mod_timer(&musb->otg_timer, jiffies
935 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 936 break;
937 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 938 del_timer(&musb->otg_timer);
939 musb_g_reset(musb);
550a7375
FB		 940 break;
941 case OTG_STATE_B_WAIT_ACON:
b99d3659 942 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
e47d9254
AT		 943 usb_otg_state_string(musb->xceiv->otg->state));
944 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 945 musb_g_reset(musb);
946 break;
550a7375 947 case OTG_STATE_B_IDLE:
e47d9254 948 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 949 /* FALLTHROUGH */
950 case OTG_STATE_B_PERIPHERAL:
951 musb_g_reset(musb);
952 break;
953 default:
b99d3659 954 musb_dbg(musb, "Unhandled BUS RESET as %s",
e47d9254 955 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 956 }
957 }
550a7375 958 }
550a7375
FB		 959
960#if 0
961/* REVISIT ... this would be for multiplexing periodic endpoints, or
962 * supporting transfer phasing to prevent exceeding ISO bandwidth
963 * limits of a given frame or microframe.
964 *
965 * It's not needed for peripheral side, which dedicates endpoints;
966 * though it _might_ use SOF irqs for other purposes.
967 *
968 * And it's not currently needed for host side, which also dedicates
969 * endpoints, relies on TX/RX interval registers, and isn't claimed
970 * to support ISO transfers yet.
971 */
972 if (int_usb & MUSB_INTR_SOF) {
973 void __iomem *mbase = musb->mregs;
974 struct musb_hw_ep *ep;
975 u8 epnum;
976 u16 frame;
977
5c8a86e1 978 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 979 handled = IRQ_HANDLED;
980
981 /* start any periodic Tx transfers waiting for current frame */
982 frame = musb_readw(mbase, MUSB_FRAME);
983 ep = musb->endpoints;
984 for (epnum = 1; (epnum < musb->nr_endpoints)
985 && (musb->epmask >= (1 << epnum));
986 epnum++, ep++) {
987 /*
988 * FIXME handle framecounter wraps (12 bits)
989 * eliminate duplicated StartUrb logic
990 */
991 if (ep->dwWaitFrame >= frame) {
992 ep->dwWaitFrame = 0;
993 pr_debug("SOF --> periodic TX%s on %d\n",
994 ep->tx_channel ? " DMA" : "",
995 epnum);
996 if (!ep->tx_channel)
997 musb_h_tx_start(musb, epnum);
998 else
999 cppi_hostdma_start(musb, epnum);
1000 }
1001 } /* end of for loop */
1002 }
1003#endif
1004
2bff3916 1005 schedule_delayed_work(&musb->irq_work, 0);
550a7375
FB		 1006
1007 return handled;
1008}
1009
1010/*-------------------------------------------------------------------------*/
1011
e1eb3eb8 1012static void musb_disable_interrupts(struct musb *musb)
550a7375
FB		 1013{
1014 void __iomem *mbase = musb->mregs;
1015 u16 temp;
1016
1017 /* disable interrupts */
1018 musb_writeb(mbase, MUSB_INTRUSBE, 0);
b18d26f6 1019 musb->intrtxe = 0;
550a7375 1020 musb_writew(mbase, MUSB_INTRTXE, 0);
af5ec14d 1021 musb->intrrxe = 0;
550a7375
FB		 1022 musb_writew(mbase, MUSB_INTRRXE, 0);
1023
550a7375
FB		 1024 /* flush pending interrupts */
1025 temp = musb_readb(mbase, MUSB_INTRUSB);
1026 temp = musb_readw(mbase, MUSB_INTRTX);
1027 temp = musb_readw(mbase, MUSB_INTRRX);
e1eb3eb8
FB		 1028}
1029
1030static void musb_enable_interrupts(struct musb *musb)
1031{
1032 void __iomem *regs = musb->mregs;
1033
1034 /* Set INT enable registers, enable interrupts */
1035 musb->intrtxe = musb->epmask;
1036 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1037 musb->intrrxe = musb->epmask & 0xfffe;
1038 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1039 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 1040
1041}
1042
001dd84a
SAS		 1043/*
1044 * Program the HDRC to start (enable interrupts, dma, etc.).
1045 */
1046void musb_start(struct musb *musb)
1047{
1048 void __iomem *regs = musb->mregs;
1049 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
9b753764 1050 u8 power;
001dd84a 1051
b99d3659 1052 musb_dbg(musb, "<== devctl %02x", devctl);
001dd84a 1053
e1eb3eb8 1054 musb_enable_interrupts(musb);
001dd84a
SAS		 1055 musb_writeb(regs, MUSB_TESTMODE, 0);
1056
9b753764
BL		 1057 power = MUSB_POWER_ISOUPDATE;
1058 /*
1059 * treating UNKNOWN as unspecified maximum speed, in which case
1060 * we will default to high-speed.
1061 */
1062 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1063 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1064 power |= MUSB_POWER_HSENAB;
1065 musb_writeb(regs, MUSB_POWER, power);
001dd84a
SAS		 1066
1067 musb->is_active = 0;
1068 devctl = musb_readb(regs, MUSB_DEVCTL);
1069 devctl &= ~MUSB_DEVCTL_SESSION;
1070
1071 /* session started after:
1072 * (a) ID-grounded irq, host mode;
1073 * (b) vbus present/connect IRQ, peripheral mode;
1074 * (c) peripheral initiates, using SRP
1075 */
1076 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
40af177e 1077 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
001dd84a
SAS		 1078 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1079 musb->is_active = 1;
1080 } else {
1081 devctl |= MUSB_DEVCTL_SESSION;
1082 }
1083
1084 musb_platform_enable(musb);
1085 musb_writeb(regs, MUSB_DEVCTL, devctl);
1086}
1087
550a7375
FB		 1088/*
1089 * Make the HDRC stop (disable interrupts, etc.);
1090 * reversible by musb_start
1091 * called on gadget driver unregister
1092 * with controller locked, irqs blocked
1093 * acts as a NOP unless some role activated the hardware
1094 */
1095void musb_stop(struct musb *musb)
1096{
1097 /* stop IRQs, timers, ... */
1098 musb_platform_disable(musb);
e945953d
BL		 1099 musb_disable_interrupts(musb);
1100 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
550a7375
FB		 1101
1102 /* FIXME
1103 * - mark host and/or peripheral drivers unusable/inactive
1104 * - disable DMA (and enable it in HdrcStart)
1105 * - make sure we can musb_start() after musb_stop(); with
1106 * OTG mode, gadget driver module rmmod/modprobe cycles that
1107 * - ...
1108 */
1109 musb_platform_try_idle(musb, 0);
1110}
1111
550a7375
FB		 1112/*-------------------------------------------------------------------------*/
1113
1114/*
1115 * The silicon either has hard-wired endpoint configurations, or else
1116 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1117 * writing only the dynamic sizing is very well tested. Since we switched
1118 * away from compile-time hardware parameters, we can no longer rely on
1119 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1120 *
1121 * We don't currently use dynamic fifo setup capability to do anything
1122 * more than selecting one of a bunch of predefined configurations.
1123 */
8a77f05a 1124static ushort fifo_mode;
550a7375
FB		 1125
1126/* "modprobe ... fifo_mode=1" etc */
1127module_param(fifo_mode, ushort, 0);
1128MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1129
550a7375
FB		 1130/*
1131 * tables defining fifo_mode values. define more if you like.
1132 * for host side, make sure both halves of ep1 are set up.
1133 */
1134
1135/* mode 0 - fits in 2KB */
d3608b6d 1136static struct musb_fifo_cfg mode_0_cfg[] = {
550a7375
FB		 1137{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1138{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1139{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1140{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1141{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1142};
1143
1144/* mode 1 - fits in 4KB */
d3608b6d 1145static struct musb_fifo_cfg mode_1_cfg[] = {
550a7375
FB		 1146{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1147{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1148{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1149{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1150{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1151};
1152
1153/* mode 2 - fits in 4KB */
d3608b6d 1154static struct musb_fifo_cfg mode_2_cfg[] = {
550a7375
FB		 1155{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1156{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1157{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1158{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1159{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1160{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1161};
1162
1163/* mode 3 - fits in 4KB */
d3608b6d 1164static struct musb_fifo_cfg mode_3_cfg[] = {
550a7375
FB		 1165{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1166{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1167{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1168{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1169{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1170{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1171};
1172
1173/* mode 4 - fits in 16KB */
d3608b6d 1174static struct musb_fifo_cfg mode_4_cfg[] = {
550a7375
FB		 1175{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1176{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1177{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1178{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1179{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1180{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1181{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1182{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1183{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1184{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1185{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1186{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1187{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1188{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1189{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1190{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1191{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1192{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1193{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1194{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1195{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1196{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1197{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1198{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1199{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1200{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1201{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1202};
1203
3b151526 1204/* mode 5 - fits in 8KB */
d3608b6d 1205static struct musb_fifo_cfg mode_5_cfg[] = {
3b151526
AKG		 1206{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1207{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1208{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1209{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1210{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1211{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1212{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1213{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1214{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1215{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1216{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1217{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1218{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1219{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1220{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1221{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1222{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1223{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1224{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1225{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1226{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1227{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1228{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1229{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1230{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1231{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1232{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1233};
550a7375
FB		 1234
1235/*
1236 * configure a fifo; for non-shared endpoints, this may be called
1237 * once for a tx fifo and once for an rx fifo.
1238 *
1239 * returns negative errno or offset for next fifo.
1240 */
41ac7b3a 1241static int
550a7375 1242fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1243 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1244{
1245 void __iomem *mbase = musb->mregs;
1246 int size = 0;
1247 u16 maxpacket = cfg->maxpacket;
1248 u16 c_off = offset >> 3;
1249 u8 c_size;
1250
1251 /* expect hw_ep has already been zero-initialized */
1252
1253 size = ffs(max(maxpacket, (u16) 8)) - 1;
1254 maxpacket = 1 << size;
1255
1256 c_size = size - 3;
1257 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1258 if ((offset + (maxpacket << 1)) >
1259 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1260 return -EMSGSIZE;
1261 c_size |= MUSB_FIFOSZ_DPB;
1262 } else {
ca6d1b13 1263 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1264 return -EMSGSIZE;
1265 }
1266
1267 /* configure the FIFO */
1268 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1269
550a7375 1270 /* EP0 reserved endpoint for control, bidirectional;
5ae477b0 1271 * EP1 reserved for bulk, two unidirectional halves.
550a7375
FB		 1272 */
1273 if (hw_ep->epnum == 1)
1274 musb->bulk_ep = hw_ep;
1275 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1276 switch (cfg->style) {
1277 case FIFO_TX:
c6cf8b00
BW		 1278 musb_write_txfifosz(mbase, c_size);
1279 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1280 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1281 hw_ep->max_packet_sz_tx = maxpacket;
1282 break;
1283 case FIFO_RX:
c6cf8b00
BW		 1284 musb_write_rxfifosz(mbase, c_size);
1285 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1286 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1287 hw_ep->max_packet_sz_rx = maxpacket;
1288 break;
1289 case FIFO_RXTX:
c6cf8b00
BW		 1290 musb_write_txfifosz(mbase, c_size);
1291 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1292 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1293 hw_ep->max_packet_sz_rx = maxpacket;
1294
c6cf8b00
BW		 1295 musb_write_rxfifosz(mbase, c_size);
1296 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1297 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1298 hw_ep->max_packet_sz_tx = maxpacket;
1299
1300 hw_ep->is_shared_fifo = true;
1301 break;
1302 }
1303
1304 /* NOTE rx and tx endpoint irqs aren't managed separately,
1305 * which happens to be ok
1306 */
1307 musb->epmask |= (1 << hw_ep->epnum);
1308
1309 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1310}
1311
d3608b6d 1312static struct musb_fifo_cfg ep0_cfg = {
550a7375
FB		 1313 .style = FIFO_RXTX, .maxpacket = 64,
1314};
1315
41ac7b3a 1316static int ep_config_from_table(struct musb *musb)
550a7375 1317{
e6c213b2 1318 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1319 unsigned i, n;
1320 int offset;
1321 struct musb_hw_ep *hw_ep = musb->endpoints;
1322
e6c213b2
FB		 1323 if (musb->config->fifo_cfg) {
1324 cfg = musb->config->fifo_cfg;
1325 n = musb->config->fifo_cfg_size;
1326 goto done;
1327 }
1328
550a7375
FB		 1329 switch (fifo_mode) {
1330 default:
1331 fifo_mode = 0;
1332 /* FALLTHROUGH */
1333 case 0:
1334 cfg = mode_0_cfg;
1335 n = ARRAY_SIZE(mode_0_cfg);
1336 break;
1337 case 1:
1338 cfg = mode_1_cfg;
1339 n = ARRAY_SIZE(mode_1_cfg);
1340 break;
1341 case 2:
1342 cfg = mode_2_cfg;
1343 n = ARRAY_SIZE(mode_2_cfg);
1344 break;
1345 case 3:
1346 cfg = mode_3_cfg;
1347 n = ARRAY_SIZE(mode_3_cfg);
1348 break;
1349 case 4:
1350 cfg = mode_4_cfg;
1351 n = ARRAY_SIZE(mode_4_cfg);
1352 break;
3b151526
AKG		 1353 case 5:
1354 cfg = mode_5_cfg;
1355 n = ARRAY_SIZE(mode_5_cfg);
1356 break;
550a7375
FB		 1357 }
1358
3ff4b573 1359 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
550a7375
FB		 1360
1361
e6c213b2 1362done:
550a7375
FB		 1363 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1364 /* assert(offset > 0) */
1365
1366 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1367 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1368 */
1369
1370 for (i = 0; i < n; i++) {
1371 u8 epn = cfg->hw_ep_num;
1372
ca6d1b13 1373 if (epn >= musb->config->num_eps) {
550a7375
FB		 1374 pr_debug("%s: invalid ep %d\n",
1375 musb_driver_name, epn);
bb1c9ef1 1376 return -EINVAL;
550a7375
FB		 1377 }
1378 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1379 if (offset < 0) {
1380 pr_debug("%s: mem overrun, ep %d\n",
1381 musb_driver_name, epn);
f69dfa1f 1382 return offset;
550a7375
FB		 1383 }
1384 epn++;
1385 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1386 }
1387
3ff4b573 1388 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
550a7375 1389 musb_driver_name,
ca6d1b13
FB		 1390 n + 1, musb->config->num_eps * 2 - 1,
1391 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1392
550a7375
FB		 1393 if (!musb->bulk_ep) {
1394 pr_debug("%s: missing bulk\n", musb_driver_name);
1395 return -EINVAL;
1396 }
550a7375
FB		 1397
1398 return 0;
1399}
1400
1401
1402/*
1403 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1404 * @param musb the controller
1405 */
41ac7b3a 1406static int ep_config_from_hw(struct musb *musb)
550a7375 1407{
c6cf8b00 1408 u8 epnum = 0;
550a7375 1409 struct musb_hw_ep *hw_ep;
a156544b 1410 void __iomem *mbase = musb->mregs;
c6cf8b00 1411 int ret = 0;
550a7375 1412
b99d3659 1413 musb_dbg(musb, "<== static silicon ep config");
550a7375
FB		 1414
1415 /* FIXME pick up ep0 maxpacket size */
1416
ca6d1b13 1417 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1418 musb_ep_select(mbase, epnum);
1419 hw_ep = musb->endpoints + epnum;
1420
c6cf8b00
BW		 1421 ret = musb_read_fifosize(musb, hw_ep, epnum);
1422 if (ret < 0)
550a7375 1423 break;
550a7375
FB		 1424
1425 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1426
550a7375
FB		 1427 /* pick an RX/TX endpoint for bulk */
1428 if (hw_ep->max_packet_sz_tx < 512
1429 || hw_ep->max_packet_sz_rx < 512)
1430 continue;
1431
1432 /* REVISIT: this algorithm is lazy, we should at least
1433 * try to pick a double buffered endpoint.
1434 */
1435 if (musb->bulk_ep)
1436 continue;
1437 musb->bulk_ep = hw_ep;
550a7375
FB		 1438 }
1439
550a7375
FB		 1440 if (!musb->bulk_ep) {
1441 pr_debug("%s: missing bulk\n", musb_driver_name);
1442 return -EINVAL;
1443 }
550a7375
FB		 1444
1445 return 0;
1446}
1447
1448enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1449
1450/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1451 * configure endpoints, or take their config from silicon
1452 */
41ac7b3a 1453static int musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1454{
550a7375
FB		 1455 u8 reg;
1456 char *type;
21b031fb 1457 char aInfo[90];
550a7375
FB		 1458 void __iomem *mbase = musb->mregs;
1459 int status = 0;
1460 int i;
1461
1462 /* log core options (read using indexed model) */
c6cf8b00 1463 reg = musb_read_configdata(mbase);
550a7375
FB		 1464
1465 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1466 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1467 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1468 musb->dyn_fifo = true;
1469 }
550a7375
FB		 1470 if (reg & MUSB_CONFIGDATA_MPRXE) {
1471 strcat(aInfo, ", bulk combine");
550a7375 1472 musb->bulk_combine = true;
550a7375
FB		 1473 }
1474 if (reg & MUSB_CONFIGDATA_MPTXE) {
1475 strcat(aInfo, ", bulk split");
550a7375 1476 musb->bulk_split = true;
550a7375
FB		 1477 }
1478 if (reg & MUSB_CONFIGDATA_HBRXE) {
1479 strcat(aInfo, ", HB-ISO Rx");
a483d706 1480 musb->hb_iso_rx = true;
550a7375
FB		 1481 }
1482 if (reg & MUSB_CONFIGDATA_HBTXE) {
1483 strcat(aInfo, ", HB-ISO Tx");
a483d706 1484 musb->hb_iso_tx = true;
550a7375
FB		 1485 }
1486 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1487 strcat(aInfo, ", SoftConn");
1488
3ff4b573 1489 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
550a7375 1490
550a7375
FB		 1491 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1492 musb->is_multipoint = 1;
1493 type = "M";
1494 } else {
1495 musb->is_multipoint = 0;
1496 type = "";
550a7375 1497#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
3ff4b573
RV		 1498 pr_err("%s: kernel must blacklist external hubs\n",
1499 musb_driver_name);
550a7375
FB		 1500#endif
1501 }
1502
1503 /* log release info */
32c3b94e 1504 musb->hwvers = musb_read_hwvers(mbase);
21b031fb
RV		 1505 pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1506 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1507 MUSB_HWVERS_MINOR(musb->hwvers),
1508 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1509
1510 /* configure ep0 */
c6cf8b00 1511 musb_configure_ep0(musb);
550a7375
FB		 1512
1513 /* discover endpoint configuration */
1514 musb->nr_endpoints = 1;
1515 musb->epmask = 1;
1516
ad517e9e
FB		 1517 if (musb->dyn_fifo)
1518 status = ep_config_from_table(musb);
1519 else
1520 status = ep_config_from_hw(musb);
550a7375
FB		 1521
1522 if (status < 0)
1523 return status;
1524
1525 /* finish init, and print endpoint config */
1526 for (i = 0; i < musb->nr_endpoints; i++) {
1527 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1528
1b40fc57 1529 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
ebf39920 1530#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1b40fc57
TL		 1531 if (musb->io.quirks & MUSB_IN_TUSB) {
1532 hw_ep->fifo_async = musb->async + 0x400 +
1533 musb->io.fifo_offset(i);
1534 hw_ep->fifo_sync = musb->sync + 0x400 +
1535 musb->io.fifo_offset(i);
1536 hw_ep->fifo_sync_va =
1537 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1538
1539 if (i == 0)
1540 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1541 else
1542 hw_ep->conf = mbase + 0x400 +
1543 (((i - 1) & 0xf) << 2);
1544 }
550a7375
FB		 1545#endif
1546
d026e9c7 1547 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
550a7375
FB		 1548 hw_ep->rx_reinit = 1;
1549 hw_ep->tx_reinit = 1;
550a7375
FB		 1550
1551 if (hw_ep->max_packet_sz_tx) {
b99d3659 1552 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
550a7375
FB		 1553 musb_driver_name, i,
1554 hw_ep->is_shared_fifo ? "shared" : "tx",
1555 hw_ep->tx_double_buffered
1556 ? "doublebuffer, " : "",
1557 hw_ep->max_packet_sz_tx);
1558 }
1559 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
b99d3659 1560 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
550a7375
FB		 1561 musb_driver_name, i,
1562 "rx",
1563 hw_ep->rx_double_buffered
1564 ? "doublebuffer, " : "",
1565 hw_ep->max_packet_sz_rx);
1566 }
1567 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
b99d3659 1568 musb_dbg(musb, "hw_ep %d not configured", i);
550a7375
FB		 1569 }
1570
1571 return 0;
1572}
1573
1574/*-------------------------------------------------------------------------*/
1575
550a7375
FB		 1576/*
1577 * handle all the irqs defined by the HDRC core. for now we expect: other
1578 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1579 * will be assigned, and the irq will already have been acked.
1580 *
1581 * called in irq context with spinlock held, irqs blocked
1582 */
1583irqreturn_t musb_interrupt(struct musb *musb)
1584{
1585 irqreturn_t retval = IRQ_NONE;
31a0ede0
FB		 1586 unsigned long status;
1587 unsigned long epnum;
b11e94d0 1588 u8 devctl;
31a0ede0
FB		 1589
1590 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1591 return IRQ_NONE;
550a7375
FB		 1592
1593 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1594
cfb9a1bc 1595 trace_musb_isr(musb);
550a7375 1596
e3c93e1a
FB		 1597 /**
1598 * According to Mentor Graphics' documentation, flowchart on page 98,
1599 * IRQ should be handled as follows:
1600 *
1601 * . Resume IRQ
1602 * . Session Request IRQ
1603 * . VBUS Error IRQ
1604 * . Suspend IRQ
1605 * . Connect IRQ
1606 * . Disconnect IRQ
1607 * . Reset/Babble IRQ
1608 * . SOF IRQ (we're not using this one)
1609 * . Endpoint 0 IRQ
1610 * . TX Endpoints
1611 * . RX Endpoints
1612 *
1613 * We will be following that flowchart in order to avoid any problems
1614 * that might arise with internal Finite State Machine.
550a7375 1615 */
e3c93e1a 1616
7d9645fd 1617 if (musb->int_usb)
31a0ede0 1618 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
550a7375 1619
550a7375 1620 if (musb->int_tx & 1) {
c03da38d 1621 if (is_host_active(musb))
550a7375
FB		 1622 retval |= musb_h_ep0_irq(musb);
1623 else
1624 retval |= musb_g_ep0_irq(musb);
31a0ede0
FB		 1625
1626 /* we have just handled endpoint 0 IRQ, clear it */
1627 musb->int_tx &= ~BIT(0);
550a7375
FB		 1628 }
1629
31a0ede0
FB		 1630 status = musb->int_tx;
1631
1632 for_each_set_bit(epnum, &status, 16) {
1633 retval = IRQ_HANDLED;
1634 if (is_host_active(musb))
1635 musb_host_tx(musb, epnum);
1636 else
1637 musb_g_tx(musb, epnum);
550a7375
FB		 1638 }
1639
31a0ede0 1640 status = musb->int_rx;
e3c93e1a 1641
31a0ede0
FB		 1642 for_each_set_bit(epnum, &status, 16) {
1643 retval = IRQ_HANDLED;
1644 if (is_host_active(musb))
1645 musb_host_rx(musb, epnum);
1646 else
1647 musb_g_rx(musb, epnum);
550a7375
FB		 1648 }
1649
550a7375
FB		 1650 return retval;
1651}
981430a1 1652EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1653
1654#ifndef CONFIG_MUSB_PIO_ONLY
d3608b6d 1655static bool use_dma = 1;
550a7375
FB		 1656
1657/* "modprobe ... use_dma=0" etc */
51676c8d 1658module_param(use_dma, bool, 0644);
550a7375
FB		 1659MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1660
1661void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1662{
550a7375
FB		 1663 /* called with controller lock already held */
1664
1665 if (!epnum) {
f8e9f34f 1666 if (!is_cppi_enabled(musb)) {
550a7375 1667 /* endpoint 0 */
c03da38d 1668 if (is_host_active(musb))
550a7375
FB		 1669 musb_h_ep0_irq(musb);
1670 else
1671 musb_g_ep0_irq(musb);
1672 }
550a7375
FB		 1673 } else {
1674 /* endpoints 1..15 */
1675 if (transmit) {
c03da38d 1676 if (is_host_active(musb))
a04d46d0
FB		 1677 musb_host_tx(musb, epnum);
1678 else
1679 musb_g_tx(musb, epnum);
550a7375
FB		 1680 } else {
1681 /* receive */
c03da38d 1682 if (is_host_active(musb))
a04d46d0
FB		 1683 musb_host_rx(musb, epnum);
1684 else
1685 musb_g_rx(musb, epnum);
550a7375
FB		 1686 }
1687 }
1688}
9a35f876 1689EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1690
1691#else
1692#define use_dma 0
1693#endif
1694
12b7db2b 1695static int (*musb_phy_callback)(enum musb_vbus_id_status status);
8055555f
TL		 1696
1697/*
1698 * musb_mailbox - optional phy notifier function
1699 * @status phy state change
1700 *
1701 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1702 * disabled at the point the phy_callback is registered or unregistered.
1703 */
12b7db2b 1704int musb_mailbox(enum musb_vbus_id_status status)
8055555f
TL		 1705{
1706 if (musb_phy_callback)
12b7db2b 1707 return musb_phy_callback(status);
8055555f 1708
12b7db2b 1709 return -ENODEV;
8055555f
TL		 1710};
1711EXPORT_SYMBOL_GPL(musb_mailbox);
1712
550a7375
FB		 1713/*-------------------------------------------------------------------------*/
1714
550a7375
FB		 1715static ssize_t
1716musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1717{
1718 struct musb *musb = dev_to_musb(dev);
1719 unsigned long flags;
1720 int ret = -EINVAL;
1721
1722 spin_lock_irqsave(&musb->lock, flags);
e47d9254 1723 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 1724 spin_unlock_irqrestore(&musb->lock, flags);
1725
1726 return ret;
1727}
1728
1729static ssize_t
1730musb_mode_store(struct device *dev, struct device_attribute *attr,
1731 const char *buf, size_t n)
1732{
1733 struct musb *musb = dev_to_musb(dev);
1734 unsigned long flags;
96a274d1 1735 int status;
550a7375
FB		 1736
1737 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1738 if (sysfs_streq(buf, "host"))
1739 status = musb_platform_set_mode(musb, MUSB_HOST);
1740 else if (sysfs_streq(buf, "peripheral"))
1741 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1742 else if (sysfs_streq(buf, "otg"))
1743 status = musb_platform_set_mode(musb, MUSB_OTG);
1744 else
1745 status = -EINVAL;
550a7375
FB		 1746 spin_unlock_irqrestore(&musb->lock, flags);
1747
96a274d1 1748 return (status == 0) ? n : status;
550a7375
FB		 1749}
1750static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1751
1752static ssize_t
1753musb_vbus_store(struct device *dev, struct device_attribute *attr,
1754 const char *buf, size_t n)
1755{
1756 struct musb *musb = dev_to_musb(dev);
1757 unsigned long flags;
1758 unsigned long val;
1759
1760 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1761 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1762 return -EINVAL;
1763 }
1764
1765 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1766 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1767 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
e47d9254 1768 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1769 musb->is_active = 0;
1770 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1771 spin_unlock_irqrestore(&musb->lock, flags);
1772
1773 return n;
1774}
1775
1776static ssize_t
1777musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1778{
1779 struct musb *musb = dev_to_musb(dev);
1780 unsigned long flags;
1781 unsigned long val;
1782 int vbus;
3bbafac8 1783 u8 devctl;
550a7375
FB		 1784
1785 spin_lock_irqsave(&musb->lock, flags);
1786 val = musb->a_wait_bcon;
1787 vbus = musb_platform_get_vbus_status(musb);
3bbafac8
RA		 1788 if (vbus < 0) {
1789 /* Use default MUSB method by means of DEVCTL register */
1790 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1791 if ((devctl & MUSB_DEVCTL_VBUS)
1792 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1793 vbus = 1;
1794 else
1795 vbus = 0;
1796 }
550a7375
FB		 1797 spin_unlock_irqrestore(&musb->lock, flags);
1798
f7f9d63e 1799 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1800 vbus ? "on" : "off", val);
1801}
1802static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1803
550a7375
FB		 1804/* Gadget drivers can't know that a host is connected so they might want
1805 * to start SRP, but users can. This allows userspace to trigger SRP.
1806 */
1807static ssize_t
1808musb_srp_store(struct device *dev, struct device_attribute *attr,
1809 const char *buf, size_t n)
1810{
1811 struct musb *musb = dev_to_musb(dev);
1812 unsigned short srp;
1813
1814 if (sscanf(buf, "%hu", &srp) != 1
1815 || (srp != 1)) {
b3b1cc3b 1816 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1817 return -EINVAL;
1818 }
1819
1820 if (srp == 1)
1821 musb_g_wakeup(musb);
1822
1823 return n;
1824}
1825static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1826
94375751
FB		 1827static struct attribute *musb_attributes[] = {
1828 &dev_attr_mode.attr,
1829 &dev_attr_vbus.attr,
94375751 1830 &dev_attr_srp.attr,
94375751
FB		 1831 NULL
1832};
1833
1834static const struct attribute_group musb_attr_group = {
1835 .attrs = musb_attributes,
1836};
1837
467d5c98
TL		 1838#define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
1839 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1840 MUSB_DEVCTL_SESSION)
1841#define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1842 MUSB_DEVCTL_SESSION)
1843
1844/*
1845 * Check the musb devctl session bit to determine if we want to
1846 * allow PM runtime for the device. In general, we want to keep things
1847 * active when the session bit is set except after host disconnect.
1848 *
1849 * Only called from musb_irq_work. If this ever needs to get called
1850 * elsewhere, proper locking must be implemented for musb->session.
1851 */
1852static void musb_pm_runtime_check_session(struct musb *musb)
1853{
1854 u8 devctl, s;
1855 int error;
1856
1857 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1858
1859 /* Handle session status quirks first */
1860 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
1861 MUSB_DEVCTL_HR;
1862 switch (devctl & ~s) {
1863 case MUSB_QUIRK_B_INVALID_VBUS_91:
2bff3916 1864 if (musb->quirk_retries--) {
2b9a8c40 1865 musb_dbg(musb,
2bff3916
TL		 1866 "Poll devctl on invalid vbus, assume no session");
1867 schedule_delayed_work(&musb->irq_work,
1868 msecs_to_jiffies(1000));
1869
2b9a8c40
TL		 1870 return;
1871 }
eff0b85e 1872 /* fall through */
467d5c98 1873 case MUSB_QUIRK_A_DISCONNECT_19:
2bff3916
TL		 1874 if (musb->quirk_retries--) {
1875 musb_dbg(musb,
1876 "Poll devctl on possible host mode disconnect");
1877 schedule_delayed_work(&musb->irq_work,
1878 msecs_to_jiffies(1000));
1879
1880 return;
1881 }
467d5c98
TL		 1882 if (!musb->session)
1883 break;
1884 musb_dbg(musb, "Allow PM on possible host mode disconnect");
1885 pm_runtime_mark_last_busy(musb->controller);
1886 pm_runtime_put_autosuspend(musb->controller);
1887 musb->session = false;
1888 return;
1889 default:
1890 break;
1891 }
1892
1893 /* No need to do anything if session has not changed */
1894 s = devctl & MUSB_DEVCTL_SESSION;
1895 if (s == musb->session)
1896 return;
1897
1898 /* Block PM or allow PM? */
1899 if (s) {
1900 musb_dbg(musb, "Block PM on active session: %02x", devctl);
1901 error = pm_runtime_get_sync(musb->controller);
1902 if (error < 0)
1903 dev_err(musb->controller, "Could not enable: %i\n",
1904 error);
2bff3916 1905 musb->quirk_retries = 3;
467d5c98
TL		 1906 } else {
1907 musb_dbg(musb, "Allow PM with no session: %02x", devctl);
1908 pm_runtime_mark_last_busy(musb->controller);
1909 pm_runtime_put_autosuspend(musb->controller);
1910 }
1911
1912 musb->session = s;
1913}
1914
550a7375
FB		 1915/* Only used to provide driver mode change events */
1916static void musb_irq_work(struct work_struct *data)
1917{
2bff3916 1918 struct musb *musb = container_of(data, struct musb, irq_work.work);
3ba7b779
TL		 1919 int error;
1920
1921 error = pm_runtime_get_sync(musb->controller);
1922 if (error < 0) {
1923 dev_err(musb->controller, "Could not enable: %i\n", error);
1924
1925 return;
1926 }
550a7375 1927
467d5c98
TL		 1928 musb_pm_runtime_check_session(musb);
1929
e47d9254
AT		 1930 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1931 musb->xceiv_old_state = musb->xceiv->otg->state;
550a7375
FB		 1932 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1933 }
3ba7b779
TL		 1934
1935 pm_runtime_mark_last_busy(musb->controller);
1936 pm_runtime_put_autosuspend(musb->controller);
550a7375
FB		 1937}
1938
83b8f5b8 1939static void musb_recover_from_babble(struct musb *musb)
ca88fc2e 1940{
b4dc38fd
FB		 1941 int ret;
1942 u8 devctl;
ca88fc2e 1943
0244336f
FB		 1944 musb_disable_interrupts(musb);
1945
83b8f5b8
FB		 1946 /*
1947 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1948 * it some slack and wait for 10us.
1949 */
1950 udelay(10);
1951
b28a6432 1952 ret = musb_platform_recover(musb);
ba7ee8bb
FB		 1953 if (ret) {
1954 musb_enable_interrupts(musb);
d871c622 1955 return;
ba7ee8bb 1956 }
ca88fc2e 1957
b4dc38fd
FB		 1958 /* drop session bit */
1959 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1960 devctl &= ~MUSB_DEVCTL_SESSION;
1961 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
ca88fc2e 1962
b4dc38fd
FB		 1963 /* tell usbcore about it */
1964 musb_root_disconnect(musb);
ca88fc2e
DM		 1965
1966 /*
d871c622
GC		 1967 * When a babble condition occurs, the musb controller
1968 * removes the session bit and the endpoint config is lost.
ca88fc2e
DM		 1969 */
1970 if (musb->dyn_fifo)
b4dc38fd 1971 ret = ep_config_from_table(musb);
ca88fc2e 1972 else
b4dc38fd 1973 ret = ep_config_from_hw(musb);
ca88fc2e 1974
b4dc38fd
FB		 1975 /* restart session */
1976 if (ret == 0)
ca88fc2e
DM		 1977 musb_start(musb);
1978}
1979
550a7375
FB		 1980/* --------------------------------------------------------------------------
1981 * Init support
1982 */
1983
41ac7b3a 1984static struct musb *allocate_instance(struct device *dev,
ead22caf 1985 const struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1986{
1987 struct musb *musb;
1988 struct musb_hw_ep *ep;
1989 int epnum;
74c2e936 1990 int ret;
550a7375 1991
74c2e936
DM		 1992 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1993 if (!musb)
550a7375 1994 return NULL;
550a7375 1995
550a7375
FB		 1996 INIT_LIST_HEAD(&musb->control);
1997 INIT_LIST_HEAD(&musb->in_bulk);
1998 INIT_LIST_HEAD(&musb->out_bulk);
ea2f35c0 1999 INIT_LIST_HEAD(&musb->pending_list);
550a7375 2000
550a7375 2001 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 2002 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
550a7375
FB		 2003 musb->mregs = mbase;
2004 musb->ctrl_base = mbase;
2005 musb->nIrq = -ENODEV;
ca6d1b13 2006 musb->config = config;
02582b92 2007 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 2008 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 2009 epnum < musb->config->num_eps;
550a7375 2010 epnum++, ep++) {
550a7375
FB		 2011 ep->musb = musb;
2012 ep->epnum = epnum;
2013 }
2014
2015 musb->controller = dev;
743411b3 2016
74c2e936
DM		 2017 ret = musb_host_alloc(musb);
2018 if (ret < 0)
2019 goto err_free;
2020
2021 dev_set_drvdata(dev, musb);
2022
550a7375 2023 return musb;
74c2e936
DM		 2024
2025err_free:
2026 return NULL;
550a7375
FB		 2027}
2028
2029static void musb_free(struct musb *musb)
2030{
2031 /* this has multiple entry modes. it handles fault cleanup after
2032 * probe(), where things may be partially set up, as well as rmmod
2033 * cleanup after everything's been de-activated.
2034 */
2035
2036#ifdef CONFIG_SYSFS
94375751 2037 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 2038#endif
2039
97a39896
AKG		 2040 if (musb->nIrq >= 0) {
2041 if (musb->irq_wake)
2042 disable_irq_wake(musb->nIrq);
550a7375
FB		 2043 free_irq(musb->nIrq, musb);
2044 }
550a7375 2045
74c2e936 2046 musb_host_free(musb);
550a7375
FB		 2047}
2048
ea2f35c0
TL		 2049struct musb_pending_work {
2050 int (*callback)(struct musb *musb, void *data);
2051 void *data;
2052 struct list_head node;
2053};
2054
c8bd2ac3 2055#ifdef CONFIG_PM
ea2f35c0
TL		 2056/*
2057 * Called from musb_runtime_resume(), musb_resume(), and
2058 * musb_queue_resume_work(). Callers must take musb->lock.
2059 */
2060static int musb_run_resume_work(struct musb *musb)
2061{
2062 struct musb_pending_work *w, *_w;
2063 unsigned long flags;
2064 int error = 0;
2065
2066 spin_lock_irqsave(&musb->list_lock, flags);
2067 list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
2068 if (w->callback) {
2069 error = w->callback(musb, w->data);
2070 if (error < 0) {
2071 dev_err(musb->controller,
2072 "resume callback %p failed: %i\n",
2073 w->callback, error);
2074 }
2075 }
2076 list_del(&w->node);
2077 devm_kfree(musb->controller, w);
2078 }
2079 spin_unlock_irqrestore(&musb->list_lock, flags);
2080
2081 return error;
2082}
c8bd2ac3 2083#endif
ea2f35c0
TL		 2084
2085/*
2086 * Called to run work if device is active or else queue the work to happen
2087 * on resume. Caller must take musb->lock and must hold an RPM reference.
2088 *
2089 * Note that we cowardly refuse queuing work after musb PM runtime
2090 * resume is done calling musb_run_resume_work() and return -EINPROGRESS
2091 * instead.
2092 */
2093int musb_queue_resume_work(struct musb *musb,
2094 int (*callback)(struct musb *musb, void *data),
2095 void *data)
2096{
2097 struct musb_pending_work *w;
2098 unsigned long flags;
2099 int error;
2100
2101 if (WARN_ON(!callback))
2102 return -EINVAL;
2103
2104 if (pm_runtime_active(musb->controller))
2105 return callback(musb, data);
2106
2107 w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
2108 if (!w)
2109 return -ENOMEM;
2110
2111 w->callback = callback;
2112 w->data = data;
2113 spin_lock_irqsave(&musb->list_lock, flags);
2114 if (musb->is_runtime_suspended) {
2115 list_add_tail(&w->node, &musb->pending_list);
2116 error = 0;
2117 } else {
2118 dev_err(musb->controller, "could not add resume work %p\n",
2119 callback);
2120 devm_kfree(musb->controller, w);
2121 error = -EINPROGRESS;
2122 }
2123 spin_unlock_irqrestore(&musb->list_lock, flags);
2124
2125 return error;
2126}
2127EXPORT_SYMBOL_GPL(musb_queue_resume_work);
2128
8ed1fb79
DM		 2129static void musb_deassert_reset(struct work_struct *work)
2130{
2131 struct musb *musb;
2132 unsigned long flags;
2133
2134 musb = container_of(work, struct musb, deassert_reset_work.work);
2135
2136 spin_lock_irqsave(&musb->lock, flags);
2137
2138 if (musb->port1_status & USB_PORT_STAT_RESET)
2139 musb_port_reset(musb, false);
2140
2141 spin_unlock_irqrestore(&musb->lock, flags);
2142}
2143
550a7375
FB		 2144/*
2145 * Perform generic per-controller initialization.
2146 *
28dd924a
SS		 2147 * @dev: the controller (already clocked, etc)
2148 * @nIrq: IRQ number
2149 * @ctrl: virtual address of controller registers,
550a7375
FB		 2150 * not yet corrected for platform-specific offsets
2151 */
41ac7b3a 2152static int
550a7375
FB		 2153musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2154{
2155 int status;
2156 struct musb *musb;
c1a7d67c 2157 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
550a7375
FB		 2158
2159 /* The driver might handle more features than the board; OK.
2160 * Fail when the board needs a feature that's not enabled.
2161 */
2162 if (!plat) {
b99d3659 2163 dev_err(dev, "no platform_data?\n");
34e2beb2
SS		 2164 status = -ENODEV;
2165 goto fail0;
550a7375 2166 }
34e2beb2 2167
550a7375 2168 /* allocate */
ca6d1b13 2169 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 2170 if (!musb) {
2171 status = -ENOMEM;
2172 goto fail0;
2173 }
550a7375
FB		 2174
2175 spin_lock_init(&musb->lock);
ea2f35c0 2176 spin_lock_init(&musb->list_lock);
550a7375 2177 musb->board_set_power = plat->set_power;
550a7375 2178 musb->min_power = plat->min_power;
f7ec9437 2179 musb->ops = plat->platform_ops;
9ad96e69 2180 musb->port_mode = plat->mode;
550a7375 2181
1b40fc57
TL		 2182 /*
2183 * Initialize the default IO functions. At least omap2430 needs
2184 * these early. We initialize the platform specific IO functions
2185 * later on.
2186 */
2187 musb_readb = musb_default_readb;
2188 musb_writeb = musb_default_writeb;
2189 musb_readw = musb_default_readw;
2190 musb_writew = musb_default_writew;
2191 musb_readl = musb_default_readl;
2192 musb_writel = musb_default_writel;
2193
84e250ff 2194 /* The musb_platform_init() call:
baef653a
PDS		 2195 * - adjusts musb->mregs
2196 * - sets the musb->isr
5ae477b0 2197 * - may initialize an integrated transceiver
721002ec 2198 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 2199 * - stops powering VBUS
84e250ff 2200 *
7c9d440e 2201 * There are various transceiver configurations. Blackfin,
84e250ff
DB		 2202 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2203 * external/discrete ones in various flavors (twl4030 family,
2204 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375 2205 */
ea65df57 2206 status = musb_platform_init(musb);
550a7375 2207 if (status < 0)
03491761 2208 goto fail1;
34e2beb2 2209
550a7375
FB		 2210 if (!musb->isr) {
2211 status = -ENODEV;
c04352a5 2212 goto fail2;
550a7375
FB		 2213 }
2214
1b40fc57
TL		 2215 if (musb->ops->quirks)
2216 musb->io.quirks = musb->ops->quirks;
2217
da96cfc1 2218 /* Most devices use indexed offset or flat offset */
d026e9c7
TL		 2219 if (musb->io.quirks & MUSB_INDEXED_EP) {
2220 musb->io.ep_offset = musb_indexed_ep_offset;
2221 musb->io.ep_select = musb_indexed_ep_select;
2222 } else {
2223 musb->io.ep_offset = musb_flat_ep_offset;
2224 musb->io.ep_select = musb_flat_ep_select;
2225 }
2226
da96cfc1
BH		 2227 /* At least tusb6010 has its own offsets */
2228 if (musb->ops->ep_offset)
2229 musb->io.ep_offset = musb->ops->ep_offset;
2230 if (musb->ops->ep_select)
2231 musb->io.ep_select = musb->ops->ep_select;
2232
8a77f05a
TL		 2233 if (musb->ops->fifo_mode)
2234 fifo_mode = musb->ops->fifo_mode;
2235 else
2236 fifo_mode = 4;
2237
1b40fc57
TL		 2238 if (musb->ops->fifo_offset)
2239 musb->io.fifo_offset = musb->ops->fifo_offset;
2240 else
2241 musb->io.fifo_offset = musb_default_fifo_offset;
2242
6cc2af6d
HG		 2243 if (musb->ops->busctl_offset)
2244 musb->io.busctl_offset = musb->ops->busctl_offset;
2245 else
2246 musb->io.busctl_offset = musb_default_busctl_offset;
2247
1b40fc57
TL		 2248 if (musb->ops->readb)
2249 musb_readb = musb->ops->readb;
2250 if (musb->ops->writeb)
2251 musb_writeb = musb->ops->writeb;
2252 if (musb->ops->readw)
2253 musb_readw = musb->ops->readw;
2254 if (musb->ops->writew)
2255 musb_writew = musb->ops->writew;
2256 if (musb->ops->readl)
2257 musb_readl = musb->ops->readl;
2258 if (musb->ops->writel)
2259 musb_writel = musb->ops->writel;
2260
7f6283ed
TL		 2261#ifndef CONFIG_MUSB_PIO_ONLY
2262 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2263 dev_err(dev, "DMA controller not set\n");
7d32cdef 2264 status = -ENODEV;
7f6283ed
TL		 2265 goto fail2;
2266 }
2267 musb_dma_controller_create = musb->ops->dma_init;
2268 musb_dma_controller_destroy = musb->ops->dma_exit;
2269#endif
2270
1b40fc57
TL		 2271 if (musb->ops->read_fifo)
2272 musb->io.read_fifo = musb->ops->read_fifo;
2273 else
2274 musb->io.read_fifo = musb_default_read_fifo;
2275
2276 if (musb->ops->write_fifo)
2277 musb->io.write_fifo = musb->ops->write_fifo;
2278 else
2279 musb->io.write_fifo = musb_default_write_fifo;
2280
ffb865b1 2281 if (!musb->xceiv->io_ops) {
bf070bc1 2282 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 2283 musb->xceiv->io_priv = musb->mregs;
2284 musb->xceiv->io_ops = &musb_ulpi_access;
2285 }
2286
8055555f
TL		 2287 if (musb->ops->phy_callback)
2288 musb_phy_callback = musb->ops->phy_callback;
2289
f730f205
TL		 2290 /*
2291 * We need musb_read/write functions initialized for PM.
2292 * Note that at least 2430 glue needs autosuspend delay
2293 * somewhere above 300 ms for the hardware to idle properly
2294 * after disconnecting the cable in host mode. Let's use
2295 * 500 ms for some margin.
2296 */
2297 pm_runtime_use_autosuspend(musb->controller);
2298 pm_runtime_set_autosuspend_delay(musb->controller, 500);
2299 pm_runtime_enable(musb->controller);
c04352a5
GI		 2300 pm_runtime_get_sync(musb->controller);
2301
39cee200
UKK		 2302 status = usb_phy_init(musb->xceiv);
2303 if (status < 0)
2304 goto err_usb_phy_init;
2305
48054147 2306 if (use_dma && dev->dma_mask) {
7f6283ed
TL		 2307 musb->dma_controller =
2308 musb_dma_controller_create(musb, musb->mregs);
48054147
SAS		 2309 if (IS_ERR(musb->dma_controller)) {
2310 status = PTR_ERR(musb->dma_controller);
2311 goto fail2_5;
2312 }
2313 }
550a7375
FB		 2314
2315 /* be sure interrupts are disabled before connecting ISR */
2316 musb_platform_disable(musb);
e945953d
BL		 2317 musb_disable_interrupts(musb);
2318 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
550a7375 2319
66fadea5 2320 /* Init IRQ workqueue before request_irq */
2bff3916 2321 INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
8ed1fb79
DM		 2322 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2323 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
66fadea5 2324
550a7375 2325 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 2326 status = musb_core_init(plat->config->multipoint
550a7375
FB		 2327 ? MUSB_CONTROLLER_MHDRC
2328 : MUSB_CONTROLLER_HDRC, musb);
2329 if (status < 0)
34e2beb2 2330 goto fail3;
550a7375 2331
f7f9d63e 2332 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
f7f9d63e 2333
550a7375 2334 /* attach to the IRQ */
427c4f33 2335 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
550a7375
FB		 2336 dev_err(dev, "request_irq %d failed!\n", nIrq);
2337 status = -ENODEV;
34e2beb2 2338 goto fail3;
550a7375
FB		 2339 }
2340 musb->nIrq = nIrq;
032ec49f 2341 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 2342 if (enable_irq_wake(nIrq) == 0) {
2343 musb->irq_wake = 1;
550a7375 2344 device_init_wakeup(dev, 1);
c48a5155
FB		 2345 } else {
2346 musb->irq_wake = 0;
2347 }
550a7375 2348
032ec49f
FB		 2349 /* program PHY to use external vBus if required */
2350 if (plat->extvbus) {
2351 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2352 busctl |= MUSB_ULPI_USE_EXTVBUS;
2353 musb_write_ulpi_buscontrol(musb->mregs, busctl);
550a7375 2354 }
550a7375 2355
e5615112
GI		 2356 if (musb->xceiv->otg->default_a) {
2357 MUSB_HST_MODE(musb);
e47d9254 2358 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
e5615112
GI		 2359 } else {
2360 MUSB_DEV_MODE(musb);
e47d9254 2361 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
e5615112 2362 }
550a7375 2363
6c5f6a6f
DM		 2364 switch (musb->port_mode) {
2365 case MUSB_PORT_MODE_HOST:
2366 status = musb_host_setup(musb, plat->power);
2df6761e
FB		 2367 if (status < 0)
2368 goto fail3;
2369 status = musb_platform_set_mode(musb, MUSB_HOST);
6c5f6a6f
DM		 2370 break;
2371 case MUSB_PORT_MODE_GADGET:
2372 status = musb_gadget_setup(musb);
2df6761e
FB		 2373 if (status < 0)
2374 goto fail3;
2375 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
6c5f6a6f
DM		 2376 break;
2377 case MUSB_PORT_MODE_DUAL_ROLE:
2378 status = musb_host_setup(musb, plat->power);
2379 if (status < 0)
2380 goto fail3;
2381 status = musb_gadget_setup(musb);
2df6761e 2382 if (status) {
0d2dd7ea 2383 musb_host_cleanup(musb);
2df6761e
FB		 2384 goto fail3;
2385 }
2386 status = musb_platform_set_mode(musb, MUSB_OTG);
6c5f6a6f
DM		 2387 break;
2388 default:
2389 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2390 break;
2391 }
550a7375 2392
461972d8 2393 if (status < 0)
34e2beb2 2394 goto fail3;
550a7375 2395
7f7f9e2a
FB		 2396 status = musb_init_debugfs(musb);
2397 if (status < 0)
b0f9da7e 2398 goto fail4;
7f7f9e2a 2399
94375751 2400 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
28c2c51c 2401 if (status)
b0f9da7e 2402 goto fail5;
550a7375 2403
c723bd6e 2404 musb->is_initialized = 1;
7099dbc5
TL		 2405 pm_runtime_mark_last_busy(musb->controller);
2406 pm_runtime_put_autosuspend(musb->controller);
c04352a5 2407
28c2c51c 2408 return 0;
550a7375 2409
b0f9da7e
FB		 2410fail5:
2411 musb_exit_debugfs(musb);
2412
34e2beb2 2413fail4:
032ec49f 2414 musb_gadget_cleanup(musb);
0d2dd7ea 2415 musb_host_cleanup(musb);
34e2beb2
SS		 2416
2417fail3:
2bff3916 2418 cancel_delayed_work_sync(&musb->irq_work);
8ed1fb79
DM		 2419 cancel_delayed_work_sync(&musb->finish_resume_work);
2420 cancel_delayed_work_sync(&musb->deassert_reset_work);
f3ce4d5b 2421 if (musb->dma_controller)
7f6283ed 2422 musb_dma_controller_destroy(musb->dma_controller);
39cee200 2423
48054147 2424fail2_5:
39cee200
UKK		 2425 usb_phy_shutdown(musb->xceiv);
2426
2427err_usb_phy_init:
7099dbc5 2428 pm_runtime_dont_use_autosuspend(musb->controller);
c04352a5 2429 pm_runtime_put_sync(musb->controller);
f730f205 2430 pm_runtime_disable(musb->controller);
c04352a5
GI		 2431
2432fail2:
34e2beb2
SS		 2433 if (musb->irq_wake)
2434 device_init_wakeup(dev, 0);
550a7375 2435 musb_platform_exit(musb);
28c2c51c 2436
34e2beb2 2437fail1:
3df08dc7
LM		 2438 if (status != -EPROBE_DEFER)
2439 dev_err(musb->controller,
2440 "%s failed with status %d\n", __func__, status);
34e2beb2 2441
28c2c51c
FB		 2442 musb_free(musb);
2443
34e2beb2
SS		 2444fail0:
2445
28c2c51c
FB		 2446 return status;
2447
550a7375
FB		 2448}
2449
2450/*-------------------------------------------------------------------------*/
2451
2452/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2453 * bridge to a platform device; this driver then suffices.
2454 */
41ac7b3a 2455static int musb_probe(struct platform_device *pdev)
550a7375
FB		 2456{
2457 struct device *dev = &pdev->dev;
fcf173e4 2458 int irq = platform_get_irq_byname(pdev, "mc");
550a7375
FB		 2459 struct resource *iomem;
2460 void __iomem *base;
2461
1f79b26c 2462 if (irq <= 0)
550a7375
FB		 2463 return -ENODEV;
2464
1f79b26c 2465 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b42f7f30
FB		 2466 base = devm_ioremap_resource(dev, iomem);
2467 if (IS_ERR(base))
2468 return PTR_ERR(base);
550a7375 2469
b42f7f30 2470 return musb_init_controller(dev, irq, base);
550a7375
FB		 2471}
2472
fb4e98ab 2473static int musb_remove(struct platform_device *pdev)
550a7375 2474{
8d2421e6
AKG		 2475 struct device *dev = &pdev->dev;
2476 struct musb *musb = dev_to_musb(dev);
302f6802 2477 unsigned long flags;
550a7375
FB		 2478
2479 /* this gets called on rmmod.
2480 * - Host mode: host may still be active
2481 * - Peripheral mode: peripheral is deactivated (or never-activated)
2482 * - OTG mode: both roles are deactivated (or never-activated)
2483 */
7f7f9e2a 2484 musb_exit_debugfs(musb);
302f6802 2485
2bff3916 2486 cancel_delayed_work_sync(&musb->irq_work);
f730f205
TL		 2487 cancel_delayed_work_sync(&musb->finish_resume_work);
2488 cancel_delayed_work_sync(&musb->deassert_reset_work);
302f6802
TL		 2489 pm_runtime_get_sync(musb->controller);
2490 musb_host_cleanup(musb);
2491 musb_gadget_cleanup(musb);
e945953d 2492
302f6802 2493 musb_platform_disable(musb);
bc1e2154 2494 spin_lock_irqsave(&musb->lock, flags);
e945953d 2495 musb_disable_interrupts(musb);
302f6802 2496 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
e945953d
BL		 2497 spin_unlock_irqrestore(&musb->lock, flags);
2498
f730f205
TL		 2499 pm_runtime_dont_use_autosuspend(musb->controller);
2500 pm_runtime_put_sync(musb->controller);
2501 pm_runtime_disable(musb->controller);
302f6802 2502 musb_platform_exit(musb);
8055555f 2503 musb_phy_callback = NULL;
8d1aad74 2504 if (musb->dma_controller)
7f6283ed 2505 musb_dma_controller_destroy(musb->dma_controller);
39cee200 2506 usb_phy_shutdown(musb->xceiv);
550a7375 2507 musb_free(musb);
8d2421e6 2508 device_init_wakeup(dev, 0);
550a7375
FB		 2509 return 0;
2510}
2511
2512#ifdef CONFIG_PM
2513
3c8a5fcc 2514static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2515{
2516 int i;
2517 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2518 void __iomem *epio;
4f712e01 2519
032ec49f
FB		 2520 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2521 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2522 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
7421107b 2523 musb->context.power = musb_readb(musb_base, MUSB_POWER);
7421107b
FB		 2524 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2525 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2526 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2527
ae9b2ad2 2528 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2529 struct musb_hw_ep *hw_ep;
2530
2531 hw_ep = &musb->endpoints[i];
2532 if (!hw_ep)
2533 continue;
2534
2535 epio = hw_ep->regs;
2536 if (!epio)
2537 continue;
2538
ea737554 2539 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2540 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2541 musb_readw(epio, MUSB_TXMAXP);
7421107b 2542 musb->context.index_regs[i].txcsr =
ae9b2ad2 2543 musb_readw(epio, MUSB_TXCSR);
7421107b 2544 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2545 musb_readw(epio, MUSB_RXMAXP);
7421107b 2546 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2547 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2548
2549 if (musb->dyn_fifo) {
7421107b 2550 musb->context.index_regs[i].txfifoadd =
4f712e01 2551 musb_read_txfifoadd(musb_base);
7421107b 2552 musb->context.index_regs[i].rxfifoadd =
4f712e01 2553 musb_read_rxfifoadd(musb_base);
7421107b 2554 musb->context.index_regs[i].txfifosz =
4f712e01 2555 musb_read_txfifosz(musb_base);
7421107b 2556 musb->context.index_regs[i].rxfifosz =
4f712e01
AKG		 2557 musb_read_rxfifosz(musb_base);
2558 }
032ec49f
FB		 2559
2560 musb->context.index_regs[i].txtype =
2561 musb_readb(epio, MUSB_TXTYPE);
2562 musb->context.index_regs[i].txinterval =
2563 musb_readb(epio, MUSB_TXINTERVAL);
2564 musb->context.index_regs[i].rxtype =
2565 musb_readb(epio, MUSB_RXTYPE);
2566 musb->context.index_regs[i].rxinterval =
2567 musb_readb(epio, MUSB_RXINTERVAL);
2568
2569 musb->context.index_regs[i].txfunaddr =
6cc2af6d 2570 musb_read_txfunaddr(musb, i);
032ec49f 2571 musb->context.index_regs[i].txhubaddr =
6cc2af6d 2572 musb_read_txhubaddr(musb, i);
032ec49f 2573 musb->context.index_regs[i].txhubport =
6cc2af6d 2574 musb_read_txhubport(musb, i);
032ec49f
FB		 2575
2576 musb->context.index_regs[i].rxfunaddr =
6cc2af6d 2577 musb_read_rxfunaddr(musb, i);
032ec49f 2578 musb->context.index_regs[i].rxhubaddr =
6cc2af6d 2579 musb_read_rxhubaddr(musb, i);
032ec49f 2580 musb->context.index_regs[i].rxhubport =
6cc2af6d 2581 musb_read_rxhubport(musb, i);
4f712e01 2582 }
4f712e01
AKG		 2583}
2584
3c8a5fcc 2585static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2586{
2587 int i;
2588 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2589 void __iomem *epio;
33f8d75f 2590 u8 power;
4f712e01 2591
032ec49f
FB		 2592 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2593 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2594 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
33f8d75f
RQ		 2595
2596 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2597 power = musb_readb(musb_base, MUSB_POWER);
2598 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2599 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2600 power |= musb->context.power;
2601 musb_writeb(musb_base, MUSB_POWER, power);
2602
b18d26f6 2603 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
af5ec14d 2604 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
7421107b 2605 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
84ac5d11
BL		 2606 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2607 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2608
ae9b2ad2 2609 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2610 struct musb_hw_ep *hw_ep;
2611
2612 hw_ep = &musb->endpoints[i];
2613 if (!hw_ep)
2614 continue;
2615
2616 epio = hw_ep->regs;
2617 if (!epio)
2618 continue;
2619
ea737554 2620 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2621 musb_writew(epio, MUSB_TXMAXP,
7421107b 2622 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2623 musb_writew(epio, MUSB_TXCSR,
7421107b 2624 musb->context.index_regs[i].txcsr);
ae9b2ad2 2625 musb_writew(epio, MUSB_RXMAXP,
7421107b 2626 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2627 musb_writew(epio, MUSB_RXCSR,
7421107b 2628 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2629
2630 if (musb->dyn_fifo) {
2631 musb_write_txfifosz(musb_base,
7421107b 2632 musb->context.index_regs[i].txfifosz);
4f712e01 2633 musb_write_rxfifosz(musb_base,
7421107b 2634 musb->context.index_regs[i].rxfifosz);
4f712e01 2635 musb_write_txfifoadd(musb_base,
7421107b 2636 musb->context.index_regs[i].txfifoadd);
4f712e01 2637 musb_write_rxfifoadd(musb_base,
7421107b 2638 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2639 }
2640
032ec49f 2641 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2642 musb->context.index_regs[i].txtype);
032ec49f 2643 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2644 musb->context.index_regs[i].txinterval);
032ec49f 2645 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2646 musb->context.index_regs[i].rxtype);
032ec49f 2647 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2648
032ec49f 2649 musb->context.index_regs[i].rxinterval);
6cc2af6d 2650 musb_write_txfunaddr(musb, i,
7421107b 2651 musb->context.index_regs[i].txfunaddr);
6cc2af6d 2652 musb_write_txhubaddr(musb, i,
7421107b 2653 musb->context.index_regs[i].txhubaddr);
6cc2af6d 2654 musb_write_txhubport(musb, i,
7421107b 2655 musb->context.index_regs[i].txhubport);
4f712e01 2656
6cc2af6d 2657 musb_write_rxfunaddr(musb, i,
7421107b 2658 musb->context.index_regs[i].rxfunaddr);
6cc2af6d 2659 musb_write_rxhubaddr(musb, i,
7421107b 2660 musb->context.index_regs[i].rxhubaddr);
6cc2af6d 2661 musb_write_rxhubport(musb, i,
7421107b 2662 musb->context.index_regs[i].rxhubport);
4f712e01 2663 }
3c5fec75 2664 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2665}
2666
48fea965 2667static int musb_suspend(struct device *dev)
550a7375 2668{
8220796d 2669 struct musb *musb = dev_to_musb(dev);
550a7375 2670 unsigned long flags;
550a7375 2671
6fc6f4b8 2672 musb_platform_disable(musb);
e945953d 2673 musb_disable_interrupts(musb);
a926ed11
AB		 2674 if (!(musb->io.quirks & MUSB_PRESERVE_SESSION))
2675 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
ea2f35c0 2676 WARN_ON(!list_empty(&musb->pending_list));
6fc6f4b8 2677
550a7375
FB		 2678 spin_lock_irqsave(&musb->lock, flags);
2679
2680 if (is_peripheral_active(musb)) {
2681 /* FIXME force disconnect unless we know USB will wake
2682 * the system up quickly enough to respond ...
2683 */
2684 } else if (is_host_active(musb)) {
2685 /* we know all the children are suspended; sometimes
2686 * they will even be wakeup-enabled.
2687 */
2688 }
2689
c338412b
DM		 2690 musb_save_context(musb);
2691
550a7375
FB		 2692 spin_unlock_irqrestore(&musb->lock, flags);
2693 return 0;
2694}
2695
3e87d9a3 2696static int musb_resume(struct device *dev)
550a7375 2697{
ea2f35c0
TL		 2698 struct musb *musb = dev_to_musb(dev);
2699 unsigned long flags;
2700 int error;
2701 u8 devctl;
2702 u8 mask;
c338412b
DM		 2703
2704 /*
2705 * For static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2706 * unless for some reason the whole soc powered down or the USB
2707 * module got reset through the PSC (vs just being disabled).
c338412b
DM		 2708 *
2709 * For the DSPS glue layer though, a full register restore has to
2710 * be done. As it shouldn't harm other platforms, we do it
2711 * unconditionally.
550a7375 2712 */
c338412b
DM		 2713
2714 musb_restore_context(musb);
2715
b87fd2f7
SAS		 2716 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2717 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2718 if ((devctl & mask) != (musb->context.devctl & mask))
2719 musb->port1_status = 0;
a1fc1920
SAS		 2720
2721 /*
2722 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2723 * out of suspend
2724 */
2725 pm_runtime_disable(dev);
2726 pm_runtime_set_active(dev);
2727 pm_runtime_enable(dev);
6fc6f4b8
PH		 2728
2729 musb_start(musb);
2730
ea2f35c0
TL		 2731 spin_lock_irqsave(&musb->lock, flags);
2732 error = musb_run_resume_work(musb);
2733 if (error)
2734 dev_err(musb->controller, "resume work failed with %i\n",
2735 error);
2736 spin_unlock_irqrestore(&musb->lock, flags);
2737
550a7375
FB		 2738 return 0;
2739}
2740
7acc6197
HH		 2741static int musb_runtime_suspend(struct device *dev)
2742{
2743 struct musb *musb = dev_to_musb(dev);
2744
2745 musb_save_context(musb);
ea2f35c0 2746 musb->is_runtime_suspended = 1;
7acc6197
HH		 2747
2748 return 0;
2749}
2750
2751static int musb_runtime_resume(struct device *dev)
2752{
ea2f35c0
TL		 2753 struct musb *musb = dev_to_musb(dev);
2754 unsigned long flags;
2755 int error;
7acc6197
HH		 2756
2757 /*
2758 * When pm_runtime_get_sync called for the first time in driver
2759 * init, some of the structure is still not initialized which is
2760 * used in restore function. But clock needs to be
2761 * enabled before any register access, so
2762 * pm_runtime_get_sync has to be called.
2763 * Also context restore without save does not make
2764 * any sense
2765 */
c723bd6e
TL		 2766 if (!musb->is_initialized)
2767 return 0;
2768
2769 musb_restore_context(musb);
7acc6197 2770
ea2f35c0
TL		 2771 spin_lock_irqsave(&musb->lock, flags);
2772 error = musb_run_resume_work(musb);
2773 if (error)
2774 dev_err(musb->controller, "resume work failed with %i\n",
2775 error);
2776 musb->is_runtime_suspended = 0;
2777 spin_unlock_irqrestore(&musb->lock, flags);
2778
7acc6197
HH		 2779 return 0;
2780}
2781
47145210 2782static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965 2783 .suspend = musb_suspend,
3e87d9a3 2784 .resume = musb_resume,
7acc6197
HH		 2785 .runtime_suspend = musb_runtime_suspend,
2786 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2787};
2788
2789#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2790#else
48fea965 2791#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2792#endif
2793
2794static struct platform_driver musb_driver = {
2795 .driver = {
2796 .name = (char *)musb_driver_name,
2797 .bus = &platform_bus_type,
48fea965 2798 .pm = MUSB_DEV_PM_OPS,
550a7375 2799 },
e9e8c85e 2800 .probe = musb_probe,
7690417d 2801 .remove = musb_remove,
550a7375
FB		 2802};
2803
89f836a8 2804module_platform_driver(musb_driver);
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