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[mirror_ubuntu-hirsute-kernel.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375 85 * - platform_device for addressing, irq, and platform_data
5ae477b0 86 * - platform_data is mostly for board-specific information
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
550a7375
FB		 96#include <linux/list.h>
97#include <linux/kobject.h>
9303961f 98#include <linux/prefetch.h>
550a7375
FB		 99#include <linux/platform_device.h>
100#include <linux/io.h>
8d2421e6 101#include <linux/dma-mapping.h>
309be239 102#include <linux/usb.h>
550a7375 103
550a7375 104#include "musb_core.h"
c74173fd 105#include "musb_trace.h"
550a7375 106
f7f9d63e 107#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 108
109
550a7375
FB		 110#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
111#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
112
e8164f64 113#define MUSB_VERSION "6.0"
550a7375
FB		 114
115#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
116
05ac10dd 117#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375
FB		 118const char musb_driver_name[] = MUSB_DRIVER_NAME;
119
120MODULE_DESCRIPTION(DRIVER_INFO);
121MODULE_AUTHOR(DRIVER_AUTHOR);
122MODULE_LICENSE("GPL");
123MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
124
125
126/*-------------------------------------------------------------------------*/
127
128static inline struct musb *dev_to_musb(struct device *dev)
129{
550a7375 130 return dev_get_drvdata(dev);
550a7375
FB		 131}
132
133/*-------------------------------------------------------------------------*/
134
ffb865b1 135#ifndef CONFIG_BLACKFIN
705e63d2 136static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
ffb865b1 137{
b96d3b08 138 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 139 int i = 0;
140 u8 r;
141 u8 power;
bf070bc1
GI		 142 int ret;
143
144 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 145
146 /* Make sure the transceiver is not in low power mode */
147 power = musb_readb(addr, MUSB_POWER);
148 power &= ~MUSB_POWER_SUSPENDM;
149 musb_writeb(addr, MUSB_POWER, power);
150
151 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
152 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
153 */
154
705e63d2 155 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
ffb865b1
HK		 156 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
157 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
158
159 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
160 & MUSB_ULPI_REG_CMPLT)) {
161 i++;
bf070bc1
GI		 162 if (i == 10000) {
163 ret = -ETIMEDOUT;
164 goto out;
165 }
ffb865b1
HK		 166
167 }
168 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
169 r &= ~MUSB_ULPI_REG_CMPLT;
170 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
171
bf070bc1
GI		 172 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
173
174out:
175 pm_runtime_put(phy->io_dev);
176
177 return ret;
ffb865b1
HK		 178}
179
705e63d2 180static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
ffb865b1 181{
b96d3b08 182 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 183 int i = 0;
184 u8 r = 0;
185 u8 power;
bf070bc1
GI		 186 int ret = 0;
187
188 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 189
190 /* Make sure the transceiver is not in low power mode */
191 power = musb_readb(addr, MUSB_POWER);
192 power &= ~MUSB_POWER_SUSPENDM;
193 musb_writeb(addr, MUSB_POWER, power);
194
705e63d2
UKK		 195 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
196 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
ffb865b1
HK		 197 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
198
199 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
200 & MUSB_ULPI_REG_CMPLT)) {
201 i++;
bf070bc1
GI		 202 if (i == 10000) {
203 ret = -ETIMEDOUT;
204 goto out;
205 }
ffb865b1
HK		 206 }
207
208 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
209 r &= ~MUSB_ULPI_REG_CMPLT;
210 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
211
bf070bc1
GI		 212out:
213 pm_runtime_put(phy->io_dev);
214
215 return ret;
ffb865b1
HK		 216}
217#else
f2263db7
MF		 218#define musb_ulpi_read NULL
219#define musb_ulpi_write NULL
ffb865b1
HK		 220#endif
221
b96d3b08 222static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 223 .read = musb_ulpi_read,
224 .write = musb_ulpi_write,
225};
226
227/*-------------------------------------------------------------------------*/
228
1b40fc57
TL		 229static u32 musb_default_fifo_offset(u8 epnum)
230{
231 return 0x20 + (epnum * 4);
232}
233
d026e9c7
TL		 234/* "flat" mapping: each endpoint has its own i/o address */
235static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
236{
237}
238
239static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
240{
241 return 0x100 + (0x10 * epnum) + offset;
242}
243
244/* "indexed" mapping: INDEX register controls register bank select */
245static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
246{
247 musb_writeb(mbase, MUSB_INDEX, epnum);
248}
249
250static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
251{
252 return 0x10 + offset;
253}
254
6cc2af6d
HG		 255static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
256{
257 return 0x80 + (0x08 * epnum) + offset;
258}
259
1b40fc57
TL		 260static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
261{
c74173fd
BL		 262 u8 data = __raw_readb(addr + offset);
263
264 trace_musb_readb(__builtin_return_address(0), addr, offset, data);
265 return data;
1b40fc57
TL		 266}
267
268static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
269{
c74173fd 270 trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 271 __raw_writeb(data, addr + offset);
272}
273
274static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
275{
c74173fd
BL		 276 u16 data = __raw_readw(addr + offset);
277
278 trace_musb_readw(__builtin_return_address(0), addr, offset, data);
279 return data;
1b40fc57
TL		 280}
281
282static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
283{
c74173fd 284 trace_musb_writew(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 285 __raw_writew(data, addr + offset);
286}
287
288static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
289{
c74173fd
BL		 290 u32 data = __raw_readl(addr + offset);
291
292 trace_musb_readl(__builtin_return_address(0), addr, offset, data);
293 return data;
1b40fc57
TL		 294}
295
296static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
297{
c74173fd 298 trace_musb_writel(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 299 __raw_writel(data, addr + offset);
300}
c6cf8b00 301
550a7375
FB		 302/*
303 * Load an endpoint's FIFO
304 */
1b40fc57
TL		 305static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
306 const u8 *src)
550a7375 307{
5c8a86e1 308 struct musb *musb = hw_ep->musb;
550a7375
FB		 309 void __iomem *fifo = hw_ep->fifo;
310
603fe2b2
AKG		 311 if (unlikely(len == 0))
312 return;
313
550a7375
FB		 314 prefetch((u8 *)src);
315
5c8a86e1 316 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 317 'T', hw_ep->epnum, fifo, len, src);
318
319 /* we can't assume unaligned reads work */
320 if (likely((0x01 & (unsigned long) src) == 0)) {
321 u16 index = 0;
322
323 /* best case is 32bit-aligned source address */
324 if ((0x02 & (unsigned long) src) == 0) {
325 if (len >= 4) {
2bf0a8f6 326 iowrite32_rep(fifo, src + index, len >> 2);
550a7375
FB		 327 index += len & ~0x03;
328 }
329 if (len & 0x02) {
be780381 330 __raw_writew(*(u16 *)&src[index], fifo);
550a7375
FB		 331 index += 2;
332 }
333 } else {
334 if (len >= 2) {
2bf0a8f6 335 iowrite16_rep(fifo, src + index, len >> 1);
550a7375
FB		 336 index += len & ~0x01;
337 }
338 }
339 if (len & 0x01)
be780381 340 __raw_writeb(src[index], fifo);
550a7375
FB		 341 } else {
342 /* byte aligned */
2bf0a8f6 343 iowrite8_rep(fifo, src, len);
550a7375
FB		 344 }
345}
346
347/*
348 * Unload an endpoint's FIFO
349 */
1b40fc57 350static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
550a7375 351{
5c8a86e1 352 struct musb *musb = hw_ep->musb;
550a7375
FB		 353 void __iomem *fifo = hw_ep->fifo;
354
603fe2b2
AKG		 355 if (unlikely(len == 0))
356 return;
357
5c8a86e1 358 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 359 'R', hw_ep->epnum, fifo, len, dst);
360
361 /* we can't assume unaligned writes work */
362 if (likely((0x01 & (unsigned long) dst) == 0)) {
363 u16 index = 0;
364
365 /* best case is 32bit-aligned destination address */
366 if ((0x02 & (unsigned long) dst) == 0) {
367 if (len >= 4) {
2bf0a8f6 368 ioread32_rep(fifo, dst, len >> 2);
550a7375
FB		 369 index = len & ~0x03;
370 }
371 if (len & 0x02) {
be780381 372 *(u16 *)&dst[index] = __raw_readw(fifo);
550a7375
FB		 373 index += 2;
374 }
375 } else {
376 if (len >= 2) {
2bf0a8f6 377 ioread16_rep(fifo, dst, len >> 1);
550a7375
FB		 378 index = len & ~0x01;
379 }
380 }
381 if (len & 0x01)
be780381 382 dst[index] = __raw_readb(fifo);
550a7375
FB		 383 } else {
384 /* byte aligned */
2bf0a8f6 385 ioread8_rep(fifo, dst, len);
550a7375
FB		 386 }
387}
388
1b40fc57
TL		 389/*
390 * Old style IO functions
391 */
392u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
393EXPORT_SYMBOL_GPL(musb_readb);
394
395void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
396EXPORT_SYMBOL_GPL(musb_writeb);
550a7375 397
1b40fc57
TL		 398u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
399EXPORT_SYMBOL_GPL(musb_readw);
400
401void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
402EXPORT_SYMBOL_GPL(musb_writew);
403
404u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
405EXPORT_SYMBOL_GPL(musb_readl);
406
407void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
408EXPORT_SYMBOL_GPL(musb_writel);
409
7f6283ed
TL		 410#ifndef CONFIG_MUSB_PIO_ONLY
411struct dma_controller *
412(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
413EXPORT_SYMBOL(musb_dma_controller_create);
414
415void (*musb_dma_controller_destroy)(struct dma_controller *c);
416EXPORT_SYMBOL(musb_dma_controller_destroy);
417#endif
418
1b40fc57
TL		 419/*
420 * New style IO functions
421 */
422void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
423{
424 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
425}
426
427void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
428{
429 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
430}
550a7375
FB		 431
432/*-------------------------------------------------------------------------*/
433
434/* for high speed test mode; see USB 2.0 spec 7.1.20 */
435static const u8 musb_test_packet[53] = {
436 /* implicit SYNC then DATA0 to start */
437
438 /* JKJKJKJK x9 */
439 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
440 /* JJKKJJKK x8 */
441 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
442 /* JJJJKKKK x8 */
443 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
444 /* JJJJJJJKKKKKKK x8 */
445 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
446 /* JJJJJJJK x8 */
447 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
448 /* JKKKKKKK x10, JK */
449 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
450
451 /* implicit CRC16 then EOP to end */
452};
453
454void musb_load_testpacket(struct musb *musb)
455{
456 void __iomem *regs = musb->endpoints[0].regs;
457
458 musb_ep_select(musb->mregs, 0);
459 musb_write_fifo(musb->control_ep,
460 sizeof(musb_test_packet), musb_test_packet);
461 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
462}
463
464/*-------------------------------------------------------------------------*/
465
550a7375
FB		 466/*
467 * Handles OTG hnp timeouts, such as b_ase0_brst
468 */
a156544b 469static void musb_otg_timer_func(unsigned long data)
550a7375
FB		 470{
471 struct musb *musb = (struct musb *)data;
472 unsigned long flags;
473
474 spin_lock_irqsave(&musb->lock, flags);
e47d9254 475 switch (musb->xceiv->otg->state) {
550a7375 476 case OTG_STATE_B_WAIT_ACON:
b99d3659
BL		 477 musb_dbg(musb,
478 "HNP: b_wait_acon timeout; back to b_peripheral");
550a7375 479 musb_g_disconnect(musb);
e47d9254 480 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 481 musb->is_active = 0;
482 break;
ab983f2a 483 case OTG_STATE_A_SUSPEND:
550a7375 484 case OTG_STATE_A_WAIT_BCON:
b99d3659 485 musb_dbg(musb, "HNP: %s timeout",
e47d9254 486 usb_otg_state_string(musb->xceiv->otg->state));
743411b3 487 musb_platform_set_vbus(musb, 0);
e47d9254 488 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 489 break;
490 default:
b99d3659 491 musb_dbg(musb, "HNP: Unhandled mode %s",
e47d9254 492 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 493 }
550a7375
FB		 494 spin_unlock_irqrestore(&musb->lock, flags);
495}
496
550a7375 497/*
f7f9d63e 498 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 499 */
500void musb_hnp_stop(struct musb *musb)
501{
8b125df5 502 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 503 void __iomem *mbase = musb->mregs;
504 u8 reg;
505
b99d3659 506 musb_dbg(musb, "HNP: stop from %s",
e47d9254 507 usb_otg_state_string(musb->xceiv->otg->state));
ab983f2a 508
e47d9254 509 switch (musb->xceiv->otg->state) {
550a7375 510 case OTG_STATE_A_PERIPHERAL:
550a7375 511 musb_g_disconnect(musb);
b99d3659 512 musb_dbg(musb, "HNP: back to %s",
e47d9254 513 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 514 break;
515 case OTG_STATE_B_HOST:
b99d3659 516 musb_dbg(musb, "HNP: Disabling HR");
74c2e936
DM		 517 if (hcd)
518 hcd->self.is_b_host = 0;
e47d9254 519 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 520 MUSB_DEV_MODE(musb);
521 reg = musb_readb(mbase, MUSB_POWER);
522 reg |= MUSB_POWER_SUSPENDM;
523 musb_writeb(mbase, MUSB_POWER, reg);
524 /* REVISIT: Start SESSION_REQUEST here? */
525 break;
526 default:
b99d3659 527 musb_dbg(musb, "HNP: Stopping in unknown state %s",
e47d9254 528 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 529 }
530
531 /*
532 * When returning to A state after HNP, avoid hub_port_rebounce(),
533 * which cause occasional OPT A "Did not receive reset after connect"
534 * errors.
535 */
749da5f8 536 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 537}
538
83b8f5b8 539static void musb_recover_from_babble(struct musb *musb);
e1eb3eb8 540
550a7375
FB		 541/*
542 * Interrupt Service Routine to record USB "global" interrupts.
543 * Since these do not happen often and signify things of
544 * paramount importance, it seems OK to check them individually;
545 * the order of the tests is specified in the manual
546 *
547 * @param musb instance pointer
548 * @param int_usb register contents
549 * @param devctl
550 * @param power
551 */
552
550a7375 553static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 554 u8 devctl)
550a7375
FB		 555{
556 irqreturn_t handled = IRQ_NONE;
550a7375 557
b99d3659 558 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
550a7375
FB		 559
560 /* in host mode, the peripheral may issue remote wakeup.
561 * in peripheral mode, the host may resume the link.
562 * spurious RESUME irqs happen too, paired with SUSPEND.
563 */
564 if (int_usb & MUSB_INTR_RESUME) {
565 handled = IRQ_HANDLED;
b99d3659 566 musb_dbg(musb, "RESUME (%s)",
0acff6b8 567 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 568
569 if (devctl & MUSB_DEVCTL_HM) {
e47d9254 570 switch (musb->xceiv->otg->state) {
550a7375 571 case OTG_STATE_A_SUSPEND:
65322797 572 /* remote wakeup? */
550a7375
FB		 573 musb->port1_status |=
574 (USB_PORT_STAT_C_SUSPEND << 16)
575 | MUSB_PORT_STAT_RESUME;
30d361bf 576 musb->rh_timer = jiffies
309be239 577 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
baadd52f 578 musb->need_finish_resume = 1;
550a7375 579
e47d9254 580 musb->xceiv->otg->state = OTG_STATE_A_HOST;
550a7375 581 musb->is_active = 1;
9298b4aa 582 musb_host_resume_root_hub(musb);
550a7375
FB		 583 break;
584 case OTG_STATE_B_WAIT_ACON:
e47d9254 585 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 586 musb->is_active = 1;
587 MUSB_DEV_MODE(musb);
588 break;
589 default:
590 WARNING("bogus %s RESUME (%s)\n",
591 "host",
e47d9254 592 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 593 }
550a7375 594 } else {
e47d9254 595 switch (musb->xceiv->otg->state) {
550a7375
FB		 596 case OTG_STATE_A_SUSPEND:
597 /* possibly DISCONNECT is upcoming */
e47d9254 598 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44 599 musb_host_resume_root_hub(musb);
550a7375 600 break;
550a7375
FB		 601 case OTG_STATE_B_WAIT_ACON:
602 case OTG_STATE_B_PERIPHERAL:
603 /* disconnect while suspended? we may
604 * not get a disconnect irq...
605 */
606 if ((devctl & MUSB_DEVCTL_VBUS)
607 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
608 ) {
609 musb->int_usb |= MUSB_INTR_DISCONNECT;
610 musb->int_usb &= ~MUSB_INTR_SUSPEND;
611 break;
612 }
613 musb_g_resume(musb);
614 break;
615 case OTG_STATE_B_IDLE:
616 musb->int_usb &= ~MUSB_INTR_SUSPEND;
617 break;
550a7375
FB		 618 default:
619 WARNING("bogus %s RESUME (%s)\n",
620 "peripheral",
e47d9254 621 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 622 }
623 }
624 }
625
550a7375
FB		 626 /* see manual for the order of the tests */
627 if (int_usb & MUSB_INTR_SESSREQ) {
aa471456
FB		 628 void __iomem *mbase = musb->mregs;
629
19aab56c
HK		 630 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
631 && (devctl & MUSB_DEVCTL_BDEVICE)) {
b99d3659 632 musb_dbg(musb, "SessReq while on B state");
a6038ee7
HK		 633 return IRQ_HANDLED;
634 }
635
b99d3659 636 musb_dbg(musb, "SESSION_REQUEST (%s)",
e47d9254 637 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 638
639 /* IRQ arrives from ID pin sense or (later, if VBUS power
640 * is removed) SRP. responses are time critical:
641 * - turn on VBUS (with silicon-specific mechanism)
642 * - go through A_WAIT_VRISE
643 * - ... to A_WAIT_BCON.
644 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
645 */
646 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
647 musb->ep0_stage = MUSB_EP0_START;
e47d9254 648 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
550a7375 649 MUSB_HST_MODE(musb);
743411b3 650 musb_platform_set_vbus(musb, 1);
550a7375
FB		 651
652 handled = IRQ_HANDLED;
653 }
654
655 if (int_usb & MUSB_INTR_VBUSERROR) {
656 int ignore = 0;
657
658 /* During connection as an A-Device, we may see a short
659 * current spikes causing voltage drop, because of cable
660 * and peripheral capacitance combined with vbus draw.
661 * (So: less common with truly self-powered devices, where
662 * vbus doesn't act like a power supply.)
663 *
664 * Such spikes are short; usually less than ~500 usec, max
665 * of ~2 msec. That is, they're not sustained overcurrent
666 * errors, though they're reported using VBUSERROR irqs.
667 *
668 * Workarounds: (a) hardware: use self powered devices.
669 * (b) software: ignore non-repeated VBUS errors.
670 *
671 * REVISIT: do delays from lots of DEBUG_KERNEL checks
672 * make trouble here, keeping VBUS < 4.4V ?
673 */
e47d9254 674 switch (musb->xceiv->otg->state) {
550a7375
FB		 675 case OTG_STATE_A_HOST:
676 /* recovery is dicey once we've gotten past the
677 * initial stages of enumeration, but if VBUS
678 * stayed ok at the other end of the link, and
679 * another reset is due (at least for high speed,
680 * to redo the chirp etc), it might work OK...
681 */
682 case OTG_STATE_A_WAIT_BCON:
683 case OTG_STATE_A_WAIT_VRISE:
684 if (musb->vbuserr_retry) {
aa471456
FB		 685 void __iomem *mbase = musb->mregs;
686
550a7375
FB		 687 musb->vbuserr_retry--;
688 ignore = 1;
689 devctl |= MUSB_DEVCTL_SESSION;
690 musb_writeb(mbase, MUSB_DEVCTL, devctl);
691 } else {
692 musb->port1_status |=
749da5f8
AS		 693 USB_PORT_STAT_OVERCURRENT
694 | (USB_PORT_STAT_C_OVERCURRENT << 16);
550a7375
FB		 695 }
696 break;
697 default:
698 break;
699 }
700
54485116
GI		 701 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
702 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
e47d9254 703 usb_otg_state_string(musb->xceiv->otg->state),
550a7375
FB		 704 devctl,
705 ({ char *s;
706 switch (devctl & MUSB_DEVCTL_VBUS) {
707 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
708 s = "<SessEnd"; break;
709 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
710 s = "<AValid"; break;
711 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
712 s = "<VBusValid"; break;
713 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
714 default:
715 s = "VALID"; break;
2b84f92b 716 } s; }),
550a7375
FB		 717 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
718 musb->port1_status);
719
720 /* go through A_WAIT_VFALL then start a new session */
721 if (!ignore)
743411b3 722 musb_platform_set_vbus(musb, 0);
550a7375
FB		 723 handled = IRQ_HANDLED;
724 }
725
1c25fda4 726 if (int_usb & MUSB_INTR_SUSPEND) {
b99d3659 727 musb_dbg(musb, "SUSPEND (%s) devctl %02x",
e47d9254 728 usb_otg_state_string(musb->xceiv->otg->state), devctl);
1c25fda4
AM		 729 handled = IRQ_HANDLED;
730
e47d9254 731 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 732 case OTG_STATE_A_PERIPHERAL:
733 /* We also come here if the cable is removed, since
734 * this silicon doesn't report ID-no-longer-grounded.
735 *
736 * We depend on T(a_wait_bcon) to shut us down, and
737 * hope users don't do anything dicey during this
738 * undesired detour through A_WAIT_BCON.
739 */
740 musb_hnp_stop(musb);
0b3eba44 741 musb_host_resume_root_hub(musb);
1c25fda4
AM		 742 musb_root_disconnect(musb);
743 musb_platform_try_idle(musb, jiffies
744 + msecs_to_jiffies(musb->a_wait_bcon
745 ? : OTG_TIME_A_WAIT_BCON));
746
747 break;
1c25fda4
AM		 748 case OTG_STATE_B_IDLE:
749 if (!musb->is_active)
750 break;
751 case OTG_STATE_B_PERIPHERAL:
752 musb_g_suspend(musb);
eee3f15d 753 musb->is_active = musb->g.b_hnp_enable;
1c25fda4 754 if (musb->is_active) {
e47d9254 755 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
b99d3659 756 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
1c25fda4
AM		 757 mod_timer(&musb->otg_timer, jiffies
758 + msecs_to_jiffies(
759 OTG_TIME_B_ASE0_BRST));
1c25fda4
AM		 760 }
761 break;
762 case OTG_STATE_A_WAIT_BCON:
763 if (musb->a_wait_bcon != 0)
764 musb_platform_try_idle(musb, jiffies
765 + msecs_to_jiffies(musb->a_wait_bcon));
766 break;
767 case OTG_STATE_A_HOST:
e47d9254 768 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
eee3f15d 769 musb->is_active = musb->hcd->self.b_hnp_enable;
1c25fda4
AM		 770 break;
771 case OTG_STATE_B_HOST:
772 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
b99d3659 773 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
1c25fda4
AM		 774 break;
775 default:
776 /* "should not happen" */
777 musb->is_active = 0;
778 break;
779 }
780 }
781
550a7375 782 if (int_usb & MUSB_INTR_CONNECT) {
8b125df5 783 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 784
785 handled = IRQ_HANDLED;
786 musb->is_active = 1;
550a7375
FB		 787
788 musb->ep0_stage = MUSB_EP0_START;
789
b18d26f6
SAS		 790 musb->intrtxe = musb->epmask;
791 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
af5ec14d
SAS		 792 musb->intrrxe = musb->epmask & 0xfffe;
793 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
d709d22e 794 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 795 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
796 |USB_PORT_STAT_HIGH_SPEED
797 |USB_PORT_STAT_ENABLE
798 );
799 musb->port1_status |= USB_PORT_STAT_CONNECTION
800 |(USB_PORT_STAT_C_CONNECTION << 16);
801
802 /* high vs full speed is just a guess until after reset */
803 if (devctl & MUSB_DEVCTL_LSDEV)
804 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
805
550a7375 806 /* indicate new connection to OTG machine */
e47d9254 807 switch (musb->xceiv->otg->state) {
550a7375
FB		 808 case OTG_STATE_B_PERIPHERAL:
809 if (int_usb & MUSB_INTR_SUSPEND) {
b99d3659 810 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
550a7375 811 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 812 goto b_host;
550a7375 813 } else
b99d3659 814 musb_dbg(musb, "CONNECT as b_peripheral???");
550a7375
FB		 815 break;
816 case OTG_STATE_B_WAIT_ACON:
b99d3659 817 musb_dbg(musb, "HNP: CONNECT, now b_host");
1de00dae 818b_host:
e47d9254 819 musb->xceiv->otg->state = OTG_STATE_B_HOST;
74c2e936
DM		 820 if (musb->hcd)
821 musb->hcd->self.is_b_host = 1;
1de00dae 822 del_timer(&musb->otg_timer);
550a7375
FB		 823 break;
824 default:
825 if ((devctl & MUSB_DEVCTL_VBUS)
826 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
e47d9254 827 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44
DM		 828 if (hcd)
829 hcd->self.is_b_host = 0;
550a7375
FB		 830 }
831 break;
832 }
1de00dae 833
0b3eba44 834 musb_host_poke_root_hub(musb);
1de00dae 835
b99d3659 836 musb_dbg(musb, "CONNECT (%s) devctl %02x",
e47d9254 837 usb_otg_state_string(musb->xceiv->otg->state), devctl);
550a7375 838 }
550a7375 839
6d349671 840 if (int_usb & MUSB_INTR_DISCONNECT) {
b99d3659 841 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
e47d9254 842 usb_otg_state_string(musb->xceiv->otg->state),
1c25fda4
AM		 843 MUSB_MODE(musb), devctl);
844 handled = IRQ_HANDLED;
845
e47d9254 846 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 847 case OTG_STATE_A_HOST:
848 case OTG_STATE_A_SUSPEND:
0b3eba44 849 musb_host_resume_root_hub(musb);
1c25fda4 850 musb_root_disconnect(musb);
032ec49f 851 if (musb->a_wait_bcon != 0)
1c25fda4
AM		 852 musb_platform_try_idle(musb, jiffies
853 + msecs_to_jiffies(musb->a_wait_bcon));
854 break;
1c25fda4
AM		 855 case OTG_STATE_B_HOST:
856 /* REVISIT this behaves for "real disconnect"
857 * cases; make sure the other transitions from
858 * from B_HOST act right too. The B_HOST code
859 * in hnp_stop() is currently not used...
860 */
861 musb_root_disconnect(musb);
74c2e936
DM		 862 if (musb->hcd)
863 musb->hcd->self.is_b_host = 0;
e47d9254 864 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1c25fda4
AM		 865 MUSB_DEV_MODE(musb);
866 musb_g_disconnect(musb);
867 break;
868 case OTG_STATE_A_PERIPHERAL:
869 musb_hnp_stop(musb);
870 musb_root_disconnect(musb);
871 /* FALLTHROUGH */
872 case OTG_STATE_B_WAIT_ACON:
873 /* FALLTHROUGH */
1c25fda4
AM		 874 case OTG_STATE_B_PERIPHERAL:
875 case OTG_STATE_B_IDLE:
876 musb_g_disconnect(musb);
877 break;
1c25fda4
AM		 878 default:
879 WARNING("unhandled DISCONNECT transition (%s)\n",
e47d9254 880 usb_otg_state_string(musb->xceiv->otg->state));
1c25fda4
AM		 881 break;
882 }
883 }
884
550a7375
FB		 885 /* mentor saves a bit: bus reset and babble share the same irq.
886 * only host sees babble; only peripheral sees bus reset.
887 */
888 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 889 handled = IRQ_HANDLED;
896f7ea3 890 if (devctl & MUSB_DEVCTL_HM) {
550a7375 891 /*
34754dec 892 * When BABBLE happens what we can depends on which
28378d5e
FB		 893 * platform MUSB is running, because some platforms
894 * implemented proprietary means for 'recovering' from
895 * Babble conditions. One such platform is AM335x. In
34754dec
FB		 896 * most cases, however, the only thing we can do is
897 * drop the session.
550a7375 898 */
34754dec 899 dev_err(musb->controller, "Babble\n");
d0fc0a20 900
34754dec
FB		 901 if (is_host_active(musb))
902 musb_recover_from_babble(musb);
a04d46d0 903 } else {
b99d3659 904 musb_dbg(musb, "BUS RESET as %s",
e47d9254
AT		 905 usb_otg_state_string(musb->xceiv->otg->state));
906 switch (musb->xceiv->otg->state) {
550a7375 907 case OTG_STATE_A_SUSPEND:
550a7375
FB		 908 musb_g_reset(musb);
909 /* FALLTHROUGH */
910 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e 911 /* never use invalid T(a_wait_bcon) */
b99d3659 912 musb_dbg(musb, "HNP: in %s, %d msec timeout",
e47d9254 913 usb_otg_state_string(musb->xceiv->otg->state),
3df00453 914 TA_WAIT_BCON(musb));
f7f9d63e
DB		 915 mod_timer(&musb->otg_timer, jiffies
916 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 917 break;
918 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 919 del_timer(&musb->otg_timer);
920 musb_g_reset(musb);
550a7375
FB		 921 break;
922 case OTG_STATE_B_WAIT_ACON:
b99d3659 923 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
e47d9254
AT		 924 usb_otg_state_string(musb->xceiv->otg->state));
925 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 926 musb_g_reset(musb);
927 break;
550a7375 928 case OTG_STATE_B_IDLE:
e47d9254 929 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 930 /* FALLTHROUGH */
931 case OTG_STATE_B_PERIPHERAL:
932 musb_g_reset(musb);
933 break;
934 default:
b99d3659 935 musb_dbg(musb, "Unhandled BUS RESET as %s",
e47d9254 936 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 937 }
938 }
550a7375 939 }
550a7375
FB		 940
941#if 0
942/* REVISIT ... this would be for multiplexing periodic endpoints, or
943 * supporting transfer phasing to prevent exceeding ISO bandwidth
944 * limits of a given frame or microframe.
945 *
946 * It's not needed for peripheral side, which dedicates endpoints;
947 * though it _might_ use SOF irqs for other purposes.
948 *
949 * And it's not currently needed for host side, which also dedicates
950 * endpoints, relies on TX/RX interval registers, and isn't claimed
951 * to support ISO transfers yet.
952 */
953 if (int_usb & MUSB_INTR_SOF) {
954 void __iomem *mbase = musb->mregs;
955 struct musb_hw_ep *ep;
956 u8 epnum;
957 u16 frame;
958
5c8a86e1 959 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 960 handled = IRQ_HANDLED;
961
962 /* start any periodic Tx transfers waiting for current frame */
963 frame = musb_readw(mbase, MUSB_FRAME);
964 ep = musb->endpoints;
965 for (epnum = 1; (epnum < musb->nr_endpoints)
966 && (musb->epmask >= (1 << epnum));
967 epnum++, ep++) {
968 /*
969 * FIXME handle framecounter wraps (12 bits)
970 * eliminate duplicated StartUrb logic
971 */
972 if (ep->dwWaitFrame >= frame) {
973 ep->dwWaitFrame = 0;
974 pr_debug("SOF --> periodic TX%s on %d\n",
975 ep->tx_channel ? " DMA" : "",
976 epnum);
977 if (!ep->tx_channel)
978 musb_h_tx_start(musb, epnum);
979 else
980 cppi_hostdma_start(musb, epnum);
981 }
982 } /* end of for loop */
983 }
984#endif
985
1c25fda4 986 schedule_work(&musb->irq_work);
550a7375
FB		 987
988 return handled;
989}
990
991/*-------------------------------------------------------------------------*/
992
e1eb3eb8 993static void musb_disable_interrupts(struct musb *musb)
550a7375
FB		 994{
995 void __iomem *mbase = musb->mregs;
996 u16 temp;
997
998 /* disable interrupts */
999 musb_writeb(mbase, MUSB_INTRUSBE, 0);
b18d26f6 1000 musb->intrtxe = 0;
550a7375 1001 musb_writew(mbase, MUSB_INTRTXE, 0);
af5ec14d 1002 musb->intrrxe = 0;
550a7375
FB		 1003 musb_writew(mbase, MUSB_INTRRXE, 0);
1004
550a7375
FB		 1005 /* flush pending interrupts */
1006 temp = musb_readb(mbase, MUSB_INTRUSB);
1007 temp = musb_readw(mbase, MUSB_INTRTX);
1008 temp = musb_readw(mbase, MUSB_INTRRX);
e1eb3eb8
FB		 1009}
1010
1011static void musb_enable_interrupts(struct musb *musb)
1012{
1013 void __iomem *regs = musb->mregs;
1014
1015 /* Set INT enable registers, enable interrupts */
1016 musb->intrtxe = musb->epmask;
1017 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1018 musb->intrrxe = musb->epmask & 0xfffe;
1019 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1020 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 1021
1022}
1023
e1eb3eb8
FB		 1024static void musb_generic_disable(struct musb *musb)
1025{
1026 void __iomem *mbase = musb->mregs;
1027
1028 musb_disable_interrupts(musb);
1029
1030 /* off */
1031 musb_writeb(mbase, MUSB_DEVCTL, 0);
1032}
1033
001dd84a
SAS		 1034/*
1035 * Program the HDRC to start (enable interrupts, dma, etc.).
1036 */
1037void musb_start(struct musb *musb)
1038{
1039 void __iomem *regs = musb->mregs;
1040 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
9b753764 1041 u8 power;
001dd84a 1042
b99d3659 1043 musb_dbg(musb, "<== devctl %02x", devctl);
001dd84a 1044
e1eb3eb8 1045 musb_enable_interrupts(musb);
001dd84a
SAS		 1046 musb_writeb(regs, MUSB_TESTMODE, 0);
1047
9b753764
BL		 1048 power = MUSB_POWER_ISOUPDATE;
1049 /*
1050 * treating UNKNOWN as unspecified maximum speed, in which case
1051 * we will default to high-speed.
1052 */
1053 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1054 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1055 power |= MUSB_POWER_HSENAB;
1056 musb_writeb(regs, MUSB_POWER, power);
001dd84a
SAS		 1057
1058 musb->is_active = 0;
1059 devctl = musb_readb(regs, MUSB_DEVCTL);
1060 devctl &= ~MUSB_DEVCTL_SESSION;
1061
1062 /* session started after:
1063 * (a) ID-grounded irq, host mode;
1064 * (b) vbus present/connect IRQ, peripheral mode;
1065 * (c) peripheral initiates, using SRP
1066 */
1067 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
40af177e 1068 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
001dd84a
SAS		 1069 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1070 musb->is_active = 1;
1071 } else {
1072 devctl |= MUSB_DEVCTL_SESSION;
1073 }
1074
1075 musb_platform_enable(musb);
1076 musb_writeb(regs, MUSB_DEVCTL, devctl);
1077}
1078
550a7375
FB		 1079/*
1080 * Make the HDRC stop (disable interrupts, etc.);
1081 * reversible by musb_start
1082 * called on gadget driver unregister
1083 * with controller locked, irqs blocked
1084 * acts as a NOP unless some role activated the hardware
1085 */
1086void musb_stop(struct musb *musb)
1087{
1088 /* stop IRQs, timers, ... */
1089 musb_platform_disable(musb);
1090 musb_generic_disable(musb);
b99d3659 1091 musb_dbg(musb, "HDRC disabled");
550a7375
FB		 1092
1093 /* FIXME
1094 * - mark host and/or peripheral drivers unusable/inactive
1095 * - disable DMA (and enable it in HdrcStart)
1096 * - make sure we can musb_start() after musb_stop(); with
1097 * OTG mode, gadget driver module rmmod/modprobe cycles that
1098 * - ...
1099 */
1100 musb_platform_try_idle(musb, 0);
1101}
1102
550a7375
FB		 1103/*-------------------------------------------------------------------------*/
1104
1105/*
1106 * The silicon either has hard-wired endpoint configurations, or else
1107 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1108 * writing only the dynamic sizing is very well tested. Since we switched
1109 * away from compile-time hardware parameters, we can no longer rely on
1110 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1111 *
1112 * We don't currently use dynamic fifo setup capability to do anything
1113 * more than selecting one of a bunch of predefined configurations.
1114 */
8a77f05a 1115static ushort fifo_mode;
550a7375
FB		 1116
1117/* "modprobe ... fifo_mode=1" etc */
1118module_param(fifo_mode, ushort, 0);
1119MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1120
550a7375
FB		 1121/*
1122 * tables defining fifo_mode values. define more if you like.
1123 * for host side, make sure both halves of ep1 are set up.
1124 */
1125
1126/* mode 0 - fits in 2KB */
d3608b6d 1127static struct musb_fifo_cfg mode_0_cfg[] = {
550a7375
FB		 1128{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1129{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1130{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1131{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1132{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1133};
1134
1135/* mode 1 - fits in 4KB */
d3608b6d 1136static struct musb_fifo_cfg mode_1_cfg[] = {
550a7375
FB		 1137{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1138{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1139{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1140{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1141{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1142};
1143
1144/* mode 2 - fits in 4KB */
d3608b6d 1145static struct musb_fifo_cfg mode_2_cfg[] = {
550a7375
FB		 1146{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1147{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1148{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1149{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1150{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1151{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1152};
1153
1154/* mode 3 - fits in 4KB */
d3608b6d 1155static struct musb_fifo_cfg mode_3_cfg[] = {
550a7375
FB		 1156{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1157{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1158{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1159{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1160{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1161{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1162};
1163
1164/* mode 4 - fits in 16KB */
d3608b6d 1165static struct musb_fifo_cfg mode_4_cfg[] = {
550a7375
FB		 1166{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1167{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1168{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1169{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1170{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1171{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1172{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1173{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1174{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1175{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1176{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1177{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1178{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1179{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1180{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1181{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1182{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1183{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1184{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1185{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1186{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1187{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1188{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1189{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1190{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1191{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1192{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1193};
1194
3b151526 1195/* mode 5 - fits in 8KB */
d3608b6d 1196static struct musb_fifo_cfg mode_5_cfg[] = {
3b151526
AKG		 1197{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1198{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1199{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1200{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1201{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1202{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1203{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1204{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1205{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1206{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1207{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1208{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1209{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1210{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1211{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1212{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1213{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1214{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1215{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1216{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1217{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1218{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1219{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1220{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1221{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1222{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1223{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1224};
550a7375
FB		 1225
1226/*
1227 * configure a fifo; for non-shared endpoints, this may be called
1228 * once for a tx fifo and once for an rx fifo.
1229 *
1230 * returns negative errno or offset for next fifo.
1231 */
41ac7b3a 1232static int
550a7375 1233fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1234 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1235{
1236 void __iomem *mbase = musb->mregs;
1237 int size = 0;
1238 u16 maxpacket = cfg->maxpacket;
1239 u16 c_off = offset >> 3;
1240 u8 c_size;
1241
1242 /* expect hw_ep has already been zero-initialized */
1243
1244 size = ffs(max(maxpacket, (u16) 8)) - 1;
1245 maxpacket = 1 << size;
1246
1247 c_size = size - 3;
1248 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1249 if ((offset + (maxpacket << 1)) >
1250 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1251 return -EMSGSIZE;
1252 c_size |= MUSB_FIFOSZ_DPB;
1253 } else {
ca6d1b13 1254 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1255 return -EMSGSIZE;
1256 }
1257
1258 /* configure the FIFO */
1259 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1260
550a7375 1261 /* EP0 reserved endpoint for control, bidirectional;
5ae477b0 1262 * EP1 reserved for bulk, two unidirectional halves.
550a7375
FB		 1263 */
1264 if (hw_ep->epnum == 1)
1265 musb->bulk_ep = hw_ep;
1266 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1267 switch (cfg->style) {
1268 case FIFO_TX:
c6cf8b00
BW		 1269 musb_write_txfifosz(mbase, c_size);
1270 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1271 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1272 hw_ep->max_packet_sz_tx = maxpacket;
1273 break;
1274 case FIFO_RX:
c6cf8b00
BW		 1275 musb_write_rxfifosz(mbase, c_size);
1276 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1277 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1278 hw_ep->max_packet_sz_rx = maxpacket;
1279 break;
1280 case FIFO_RXTX:
c6cf8b00
BW		 1281 musb_write_txfifosz(mbase, c_size);
1282 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1283 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1284 hw_ep->max_packet_sz_rx = maxpacket;
1285
c6cf8b00
BW		 1286 musb_write_rxfifosz(mbase, c_size);
1287 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1288 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1289 hw_ep->max_packet_sz_tx = maxpacket;
1290
1291 hw_ep->is_shared_fifo = true;
1292 break;
1293 }
1294
1295 /* NOTE rx and tx endpoint irqs aren't managed separately,
1296 * which happens to be ok
1297 */
1298 musb->epmask |= (1 << hw_ep->epnum);
1299
1300 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1301}
1302
d3608b6d 1303static struct musb_fifo_cfg ep0_cfg = {
550a7375
FB		 1304 .style = FIFO_RXTX, .maxpacket = 64,
1305};
1306
41ac7b3a 1307static int ep_config_from_table(struct musb *musb)
550a7375 1308{
e6c213b2 1309 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1310 unsigned i, n;
1311 int offset;
1312 struct musb_hw_ep *hw_ep = musb->endpoints;
1313
e6c213b2
FB		 1314 if (musb->config->fifo_cfg) {
1315 cfg = musb->config->fifo_cfg;
1316 n = musb->config->fifo_cfg_size;
1317 goto done;
1318 }
1319
550a7375
FB		 1320 switch (fifo_mode) {
1321 default:
1322 fifo_mode = 0;
1323 /* FALLTHROUGH */
1324 case 0:
1325 cfg = mode_0_cfg;
1326 n = ARRAY_SIZE(mode_0_cfg);
1327 break;
1328 case 1:
1329 cfg = mode_1_cfg;
1330 n = ARRAY_SIZE(mode_1_cfg);
1331 break;
1332 case 2:
1333 cfg = mode_2_cfg;
1334 n = ARRAY_SIZE(mode_2_cfg);
1335 break;
1336 case 3:
1337 cfg = mode_3_cfg;
1338 n = ARRAY_SIZE(mode_3_cfg);
1339 break;
1340 case 4:
1341 cfg = mode_4_cfg;
1342 n = ARRAY_SIZE(mode_4_cfg);
1343 break;
3b151526
AKG		 1344 case 5:
1345 cfg = mode_5_cfg;
1346 n = ARRAY_SIZE(mode_5_cfg);
1347 break;
550a7375
FB		 1348 }
1349
3ff4b573 1350 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
550a7375
FB		 1351
1352
e6c213b2 1353done:
550a7375
FB		 1354 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1355 /* assert(offset > 0) */
1356
1357 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1358 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1359 */
1360
1361 for (i = 0; i < n; i++) {
1362 u8 epn = cfg->hw_ep_num;
1363
ca6d1b13 1364 if (epn >= musb->config->num_eps) {
550a7375
FB		 1365 pr_debug("%s: invalid ep %d\n",
1366 musb_driver_name, epn);
bb1c9ef1 1367 return -EINVAL;
550a7375
FB		 1368 }
1369 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1370 if (offset < 0) {
1371 pr_debug("%s: mem overrun, ep %d\n",
1372 musb_driver_name, epn);
f69dfa1f 1373 return offset;
550a7375
FB		 1374 }
1375 epn++;
1376 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1377 }
1378
3ff4b573 1379 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
550a7375 1380 musb_driver_name,
ca6d1b13
FB		 1381 n + 1, musb->config->num_eps * 2 - 1,
1382 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1383
550a7375
FB		 1384 if (!musb->bulk_ep) {
1385 pr_debug("%s: missing bulk\n", musb_driver_name);
1386 return -EINVAL;
1387 }
550a7375
FB		 1388
1389 return 0;
1390}
1391
1392
1393/*
1394 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1395 * @param musb the controller
1396 */
41ac7b3a 1397static int ep_config_from_hw(struct musb *musb)
550a7375 1398{
c6cf8b00 1399 u8 epnum = 0;
550a7375 1400 struct musb_hw_ep *hw_ep;
a156544b 1401 void __iomem *mbase = musb->mregs;
c6cf8b00 1402 int ret = 0;
550a7375 1403
b99d3659 1404 musb_dbg(musb, "<== static silicon ep config");
550a7375
FB		 1405
1406 /* FIXME pick up ep0 maxpacket size */
1407
ca6d1b13 1408 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1409 musb_ep_select(mbase, epnum);
1410 hw_ep = musb->endpoints + epnum;
1411
c6cf8b00
BW		 1412 ret = musb_read_fifosize(musb, hw_ep, epnum);
1413 if (ret < 0)
550a7375 1414 break;
550a7375
FB		 1415
1416 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1417
550a7375
FB		 1418 /* pick an RX/TX endpoint for bulk */
1419 if (hw_ep->max_packet_sz_tx < 512
1420 || hw_ep->max_packet_sz_rx < 512)
1421 continue;
1422
1423 /* REVISIT: this algorithm is lazy, we should at least
1424 * try to pick a double buffered endpoint.
1425 */
1426 if (musb->bulk_ep)
1427 continue;
1428 musb->bulk_ep = hw_ep;
550a7375
FB		 1429 }
1430
550a7375
FB		 1431 if (!musb->bulk_ep) {
1432 pr_debug("%s: missing bulk\n", musb_driver_name);
1433 return -EINVAL;
1434 }
550a7375
FB		 1435
1436 return 0;
1437}
1438
1439enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1440
1441/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1442 * configure endpoints, or take their config from silicon
1443 */
41ac7b3a 1444static int musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1445{
550a7375
FB		 1446 u8 reg;
1447 char *type;
21b031fb 1448 char aInfo[90];
550a7375
FB		 1449 void __iomem *mbase = musb->mregs;
1450 int status = 0;
1451 int i;
1452
1453 /* log core options (read using indexed model) */
c6cf8b00 1454 reg = musb_read_configdata(mbase);
550a7375
FB		 1455
1456 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1457 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1458 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1459 musb->dyn_fifo = true;
1460 }
550a7375
FB		 1461 if (reg & MUSB_CONFIGDATA_MPRXE) {
1462 strcat(aInfo, ", bulk combine");
550a7375 1463 musb->bulk_combine = true;
550a7375
FB		 1464 }
1465 if (reg & MUSB_CONFIGDATA_MPTXE) {
1466 strcat(aInfo, ", bulk split");
550a7375 1467 musb->bulk_split = true;
550a7375
FB		 1468 }
1469 if (reg & MUSB_CONFIGDATA_HBRXE) {
1470 strcat(aInfo, ", HB-ISO Rx");
a483d706 1471 musb->hb_iso_rx = true;
550a7375
FB		 1472 }
1473 if (reg & MUSB_CONFIGDATA_HBTXE) {
1474 strcat(aInfo, ", HB-ISO Tx");
a483d706 1475 musb->hb_iso_tx = true;
550a7375
FB		 1476 }
1477 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1478 strcat(aInfo, ", SoftConn");
1479
3ff4b573 1480 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
550a7375 1481
550a7375
FB		 1482 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1483 musb->is_multipoint = 1;
1484 type = "M";
1485 } else {
1486 musb->is_multipoint = 0;
1487 type = "";
550a7375 1488#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
3ff4b573
RV		 1489 pr_err("%s: kernel must blacklist external hubs\n",
1490 musb_driver_name);
550a7375
FB		 1491#endif
1492 }
1493
1494 /* log release info */
32c3b94e 1495 musb->hwvers = musb_read_hwvers(mbase);
21b031fb
RV		 1496 pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1497 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1498 MUSB_HWVERS_MINOR(musb->hwvers),
1499 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1500
1501 /* configure ep0 */
c6cf8b00 1502 musb_configure_ep0(musb);
550a7375
FB		 1503
1504 /* discover endpoint configuration */
1505 musb->nr_endpoints = 1;
1506 musb->epmask = 1;
1507
ad517e9e
FB		 1508 if (musb->dyn_fifo)
1509 status = ep_config_from_table(musb);
1510 else
1511 status = ep_config_from_hw(musb);
550a7375
FB		 1512
1513 if (status < 0)
1514 return status;
1515
1516 /* finish init, and print endpoint config */
1517 for (i = 0; i < musb->nr_endpoints; i++) {
1518 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1519
1b40fc57 1520 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
ebf39920 1521#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1b40fc57
TL		 1522 if (musb->io.quirks & MUSB_IN_TUSB) {
1523 hw_ep->fifo_async = musb->async + 0x400 +
1524 musb->io.fifo_offset(i);
1525 hw_ep->fifo_sync = musb->sync + 0x400 +
1526 musb->io.fifo_offset(i);
1527 hw_ep->fifo_sync_va =
1528 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1529
1530 if (i == 0)
1531 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1532 else
1533 hw_ep->conf = mbase + 0x400 +
1534 (((i - 1) & 0xf) << 2);
1535 }
550a7375
FB		 1536#endif
1537
d026e9c7 1538 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
550a7375
FB		 1539 hw_ep->rx_reinit = 1;
1540 hw_ep->tx_reinit = 1;
550a7375
FB		 1541
1542 if (hw_ep->max_packet_sz_tx) {
b99d3659 1543 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
550a7375
FB		 1544 musb_driver_name, i,
1545 hw_ep->is_shared_fifo ? "shared" : "tx",
1546 hw_ep->tx_double_buffered
1547 ? "doublebuffer, " : "",
1548 hw_ep->max_packet_sz_tx);
1549 }
1550 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
b99d3659 1551 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
550a7375
FB		 1552 musb_driver_name, i,
1553 "rx",
1554 hw_ep->rx_double_buffered
1555 ? "doublebuffer, " : "",
1556 hw_ep->max_packet_sz_rx);
1557 }
1558 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
b99d3659 1559 musb_dbg(musb, "hw_ep %d not configured", i);
550a7375
FB		 1560 }
1561
1562 return 0;
1563}
1564
1565/*-------------------------------------------------------------------------*/
1566
550a7375
FB		 1567/*
1568 * handle all the irqs defined by the HDRC core. for now we expect: other
1569 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1570 * will be assigned, and the irq will already have been acked.
1571 *
1572 * called in irq context with spinlock held, irqs blocked
1573 */
1574irqreturn_t musb_interrupt(struct musb *musb)
1575{
1576 irqreturn_t retval = IRQ_NONE;
31a0ede0
FB		 1577 unsigned long status;
1578 unsigned long epnum;
b11e94d0 1579 u8 devctl;
31a0ede0
FB		 1580
1581 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1582 return IRQ_NONE;
550a7375
FB		 1583
1584 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1585
cfb9a1bc 1586 trace_musb_isr(musb);
550a7375 1587
e3c93e1a
FB		 1588 /**
1589 * According to Mentor Graphics' documentation, flowchart on page 98,
1590 * IRQ should be handled as follows:
1591 *
1592 * . Resume IRQ
1593 * . Session Request IRQ
1594 * . VBUS Error IRQ
1595 * . Suspend IRQ
1596 * . Connect IRQ
1597 * . Disconnect IRQ
1598 * . Reset/Babble IRQ
1599 * . SOF IRQ (we're not using this one)
1600 * . Endpoint 0 IRQ
1601 * . TX Endpoints
1602 * . RX Endpoints
1603 *
1604 * We will be following that flowchart in order to avoid any problems
1605 * that might arise with internal Finite State Machine.
550a7375 1606 */
e3c93e1a 1607
7d9645fd 1608 if (musb->int_usb)
31a0ede0 1609 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
550a7375 1610
550a7375 1611 if (musb->int_tx & 1) {
c03da38d 1612 if (is_host_active(musb))
550a7375
FB		 1613 retval |= musb_h_ep0_irq(musb);
1614 else
1615 retval |= musb_g_ep0_irq(musb);
31a0ede0
FB		 1616
1617 /* we have just handled endpoint 0 IRQ, clear it */
1618 musb->int_tx &= ~BIT(0);
550a7375
FB		 1619 }
1620
31a0ede0
FB		 1621 status = musb->int_tx;
1622
1623 for_each_set_bit(epnum, &status, 16) {
1624 retval = IRQ_HANDLED;
1625 if (is_host_active(musb))
1626 musb_host_tx(musb, epnum);
1627 else
1628 musb_g_tx(musb, epnum);
550a7375
FB		 1629 }
1630
31a0ede0 1631 status = musb->int_rx;
e3c93e1a 1632
31a0ede0
FB		 1633 for_each_set_bit(epnum, &status, 16) {
1634 retval = IRQ_HANDLED;
1635 if (is_host_active(musb))
1636 musb_host_rx(musb, epnum);
1637 else
1638 musb_g_rx(musb, epnum);
550a7375
FB		 1639 }
1640
550a7375
FB		 1641 return retval;
1642}
981430a1 1643EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1644
1645#ifndef CONFIG_MUSB_PIO_ONLY
d3608b6d 1646static bool use_dma = 1;
550a7375
FB		 1647
1648/* "modprobe ... use_dma=0" etc */
51676c8d 1649module_param(use_dma, bool, 0644);
550a7375
FB		 1650MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1651
1652void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1653{
550a7375
FB		 1654 /* called with controller lock already held */
1655
1656 if (!epnum) {
f8e9f34f 1657 if (!is_cppi_enabled(musb)) {
550a7375 1658 /* endpoint 0 */
c03da38d 1659 if (is_host_active(musb))
550a7375
FB		 1660 musb_h_ep0_irq(musb);
1661 else
1662 musb_g_ep0_irq(musb);
1663 }
550a7375
FB		 1664 } else {
1665 /* endpoints 1..15 */
1666 if (transmit) {
c03da38d 1667 if (is_host_active(musb))
a04d46d0
FB		 1668 musb_host_tx(musb, epnum);
1669 else
1670 musb_g_tx(musb, epnum);
550a7375
FB		 1671 } else {
1672 /* receive */
c03da38d 1673 if (is_host_active(musb))
a04d46d0
FB		 1674 musb_host_rx(musb, epnum);
1675 else
1676 musb_g_rx(musb, epnum);
550a7375
FB		 1677 }
1678 }
1679}
9a35f876 1680EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1681
1682#else
1683#define use_dma 0
1684#endif
1685
12b7db2b 1686static int (*musb_phy_callback)(enum musb_vbus_id_status status);
8055555f
TL		 1687
1688/*
1689 * musb_mailbox - optional phy notifier function
1690 * @status phy state change
1691 *
1692 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1693 * disabled at the point the phy_callback is registered or unregistered.
1694 */
12b7db2b 1695int musb_mailbox(enum musb_vbus_id_status status)
8055555f
TL		 1696{
1697 if (musb_phy_callback)
12b7db2b 1698 return musb_phy_callback(status);
8055555f 1699
12b7db2b 1700 return -ENODEV;
8055555f
TL		 1701};
1702EXPORT_SYMBOL_GPL(musb_mailbox);
1703
550a7375
FB		 1704/*-------------------------------------------------------------------------*/
1705
550a7375
FB		 1706static ssize_t
1707musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1708{
1709 struct musb *musb = dev_to_musb(dev);
1710 unsigned long flags;
1711 int ret = -EINVAL;
1712
1713 spin_lock_irqsave(&musb->lock, flags);
e47d9254 1714 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 1715 spin_unlock_irqrestore(&musb->lock, flags);
1716
1717 return ret;
1718}
1719
1720static ssize_t
1721musb_mode_store(struct device *dev, struct device_attribute *attr,
1722 const char *buf, size_t n)
1723{
1724 struct musb *musb = dev_to_musb(dev);
1725 unsigned long flags;
96a274d1 1726 int status;
550a7375
FB		 1727
1728 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1729 if (sysfs_streq(buf, "host"))
1730 status = musb_platform_set_mode(musb, MUSB_HOST);
1731 else if (sysfs_streq(buf, "peripheral"))
1732 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1733 else if (sysfs_streq(buf, "otg"))
1734 status = musb_platform_set_mode(musb, MUSB_OTG);
1735 else
1736 status = -EINVAL;
550a7375
FB		 1737 spin_unlock_irqrestore(&musb->lock, flags);
1738
96a274d1 1739 return (status == 0) ? n : status;
550a7375
FB		 1740}
1741static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1742
1743static ssize_t
1744musb_vbus_store(struct device *dev, struct device_attribute *attr,
1745 const char *buf, size_t n)
1746{
1747 struct musb *musb = dev_to_musb(dev);
1748 unsigned long flags;
1749 unsigned long val;
1750
1751 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1752 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1753 return -EINVAL;
1754 }
1755
1756 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1757 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1758 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
e47d9254 1759 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1760 musb->is_active = 0;
1761 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1762 spin_unlock_irqrestore(&musb->lock, flags);
1763
1764 return n;
1765}
1766
1767static ssize_t
1768musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1769{
1770 struct musb *musb = dev_to_musb(dev);
1771 unsigned long flags;
1772 unsigned long val;
1773 int vbus;
3bbafac8 1774 u8 devctl;
550a7375
FB		 1775
1776 spin_lock_irqsave(&musb->lock, flags);
1777 val = musb->a_wait_bcon;
1778 vbus = musb_platform_get_vbus_status(musb);
3bbafac8
RA		 1779 if (vbus < 0) {
1780 /* Use default MUSB method by means of DEVCTL register */
1781 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1782 if ((devctl & MUSB_DEVCTL_VBUS)
1783 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1784 vbus = 1;
1785 else
1786 vbus = 0;
1787 }
550a7375
FB		 1788 spin_unlock_irqrestore(&musb->lock, flags);
1789
f7f9d63e 1790 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1791 vbus ? "on" : "off", val);
1792}
1793static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1794
550a7375
FB		 1795/* Gadget drivers can't know that a host is connected so they might want
1796 * to start SRP, but users can. This allows userspace to trigger SRP.
1797 */
1798static ssize_t
1799musb_srp_store(struct device *dev, struct device_attribute *attr,
1800 const char *buf, size_t n)
1801{
1802 struct musb *musb = dev_to_musb(dev);
1803 unsigned short srp;
1804
1805 if (sscanf(buf, "%hu", &srp) != 1
1806 || (srp != 1)) {
b3b1cc3b 1807 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1808 return -EINVAL;
1809 }
1810
1811 if (srp == 1)
1812 musb_g_wakeup(musb);
1813
1814 return n;
1815}
1816static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1817
94375751
FB		 1818static struct attribute *musb_attributes[] = {
1819 &dev_attr_mode.attr,
1820 &dev_attr_vbus.attr,
94375751 1821 &dev_attr_srp.attr,
94375751
FB		 1822 NULL
1823};
1824
1825static const struct attribute_group musb_attr_group = {
1826 .attrs = musb_attributes,
1827};
1828
467d5c98
TL		 1829#define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
1830 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1831 MUSB_DEVCTL_SESSION)
1832#define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1833 MUSB_DEVCTL_SESSION)
1834
1835/*
1836 * Check the musb devctl session bit to determine if we want to
1837 * allow PM runtime for the device. In general, we want to keep things
1838 * active when the session bit is set except after host disconnect.
1839 *
1840 * Only called from musb_irq_work. If this ever needs to get called
1841 * elsewhere, proper locking must be implemented for musb->session.
1842 */
1843static void musb_pm_runtime_check_session(struct musb *musb)
1844{
1845 u8 devctl, s;
1846 int error;
1847
1848 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1849
1850 /* Handle session status quirks first */
1851 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
1852 MUSB_DEVCTL_HR;
1853 switch (devctl & ~s) {
1854 case MUSB_QUIRK_B_INVALID_VBUS_91:
2b9a8c40
TL		 1855 if (!musb->session && !musb->quirk_invalid_vbus) {
1856 musb->quirk_invalid_vbus = true;
1857 musb_dbg(musb,
1858 "First invalid vbus, assume no session");
1859 return;
1860 }
1861 break;
467d5c98
TL		 1862 case MUSB_QUIRK_A_DISCONNECT_19:
1863 if (!musb->session)
1864 break;
1865 musb_dbg(musb, "Allow PM on possible host mode disconnect");
1866 pm_runtime_mark_last_busy(musb->controller);
1867 pm_runtime_put_autosuspend(musb->controller);
1868 musb->session = false;
1869 return;
1870 default:
1871 break;
1872 }
1873
1874 /* No need to do anything if session has not changed */
1875 s = devctl & MUSB_DEVCTL_SESSION;
1876 if (s == musb->session)
1877 return;
1878
1879 /* Block PM or allow PM? */
1880 if (s) {
1881 musb_dbg(musb, "Block PM on active session: %02x", devctl);
1882 error = pm_runtime_get_sync(musb->controller);
1883 if (error < 0)
1884 dev_err(musb->controller, "Could not enable: %i\n",
1885 error);
1886 } else {
1887 musb_dbg(musb, "Allow PM with no session: %02x", devctl);
2b9a8c40 1888 musb->quirk_invalid_vbus = false;
467d5c98
TL		 1889 pm_runtime_mark_last_busy(musb->controller);
1890 pm_runtime_put_autosuspend(musb->controller);
1891 }
1892
1893 musb->session = s;
1894}
1895
550a7375
FB		 1896/* Only used to provide driver mode change events */
1897static void musb_irq_work(struct work_struct *data)
1898{
1899 struct musb *musb = container_of(data, struct musb, irq_work);
550a7375 1900
467d5c98
TL		 1901 musb_pm_runtime_check_session(musb);
1902
e47d9254
AT		 1903 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1904 musb->xceiv_old_state = musb->xceiv->otg->state;
550a7375
FB		 1905 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1906 }
1907}
1908
83b8f5b8 1909static void musb_recover_from_babble(struct musb *musb)
ca88fc2e 1910{
b4dc38fd
FB		 1911 int ret;
1912 u8 devctl;
ca88fc2e 1913
0244336f
FB		 1914 musb_disable_interrupts(musb);
1915
83b8f5b8
FB		 1916 /*
1917 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1918 * it some slack and wait for 10us.
1919 */
1920 udelay(10);
1921
b28a6432 1922 ret = musb_platform_recover(musb);
ba7ee8bb
FB		 1923 if (ret) {
1924 musb_enable_interrupts(musb);
d871c622 1925 return;
ba7ee8bb 1926 }
ca88fc2e 1927
b4dc38fd
FB		 1928 /* drop session bit */
1929 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1930 devctl &= ~MUSB_DEVCTL_SESSION;
1931 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
ca88fc2e 1932
b4dc38fd
FB		 1933 /* tell usbcore about it */
1934 musb_root_disconnect(musb);
ca88fc2e
DM		 1935
1936 /*
d871c622
GC		 1937 * When a babble condition occurs, the musb controller
1938 * removes the session bit and the endpoint config is lost.
ca88fc2e
DM		 1939 */
1940 if (musb->dyn_fifo)
b4dc38fd 1941 ret = ep_config_from_table(musb);
ca88fc2e 1942 else
b4dc38fd 1943 ret = ep_config_from_hw(musb);
ca88fc2e 1944
b4dc38fd
FB		 1945 /* restart session */
1946 if (ret == 0)
ca88fc2e
DM		 1947 musb_start(musb);
1948}
1949
550a7375
FB		 1950/* --------------------------------------------------------------------------
1951 * Init support
1952 */
1953
41ac7b3a 1954static struct musb *allocate_instance(struct device *dev,
ead22caf 1955 const struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1956{
1957 struct musb *musb;
1958 struct musb_hw_ep *ep;
1959 int epnum;
74c2e936 1960 int ret;
550a7375 1961
74c2e936
DM		 1962 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1963 if (!musb)
550a7375 1964 return NULL;
550a7375 1965
550a7375
FB		 1966 INIT_LIST_HEAD(&musb->control);
1967 INIT_LIST_HEAD(&musb->in_bulk);
1968 INIT_LIST_HEAD(&musb->out_bulk);
1969
550a7375 1970 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 1971 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
550a7375
FB		 1972 musb->mregs = mbase;
1973 musb->ctrl_base = mbase;
1974 musb->nIrq = -ENODEV;
ca6d1b13 1975 musb->config = config;
02582b92 1976 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 1977 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 1978 epnum < musb->config->num_eps;
550a7375 1979 epnum++, ep++) {
550a7375
FB		 1980 ep->musb = musb;
1981 ep->epnum = epnum;
1982 }
1983
1984 musb->controller = dev;
743411b3 1985
74c2e936
DM		 1986 ret = musb_host_alloc(musb);
1987 if (ret < 0)
1988 goto err_free;
1989
1990 dev_set_drvdata(dev, musb);
1991
550a7375 1992 return musb;
74c2e936
DM		 1993
1994err_free:
1995 return NULL;
550a7375
FB		 1996}
1997
1998static void musb_free(struct musb *musb)
1999{
2000 /* this has multiple entry modes. it handles fault cleanup after
2001 * probe(), where things may be partially set up, as well as rmmod
2002 * cleanup after everything's been de-activated.
2003 */
2004
2005#ifdef CONFIG_SYSFS
94375751 2006 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 2007#endif
2008
97a39896
AKG		 2009 if (musb->nIrq >= 0) {
2010 if (musb->irq_wake)
2011 disable_irq_wake(musb->nIrq);
550a7375
FB		 2012 free_irq(musb->nIrq, musb);
2013 }
550a7375 2014
74c2e936 2015 musb_host_free(musb);
550a7375
FB		 2016}
2017
8ed1fb79
DM		 2018static void musb_deassert_reset(struct work_struct *work)
2019{
2020 struct musb *musb;
2021 unsigned long flags;
2022
2023 musb = container_of(work, struct musb, deassert_reset_work.work);
2024
2025 spin_lock_irqsave(&musb->lock, flags);
2026
2027 if (musb->port1_status & USB_PORT_STAT_RESET)
2028 musb_port_reset(musb, false);
2029
2030 spin_unlock_irqrestore(&musb->lock, flags);
2031}
2032
550a7375
FB		 2033/*
2034 * Perform generic per-controller initialization.
2035 *
28dd924a
SS		 2036 * @dev: the controller (already clocked, etc)
2037 * @nIrq: IRQ number
2038 * @ctrl: virtual address of controller registers,
550a7375
FB		 2039 * not yet corrected for platform-specific offsets
2040 */
41ac7b3a 2041static int
550a7375
FB		 2042musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2043{
2044 int status;
2045 struct musb *musb;
c1a7d67c 2046 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
550a7375
FB		 2047
2048 /* The driver might handle more features than the board; OK.
2049 * Fail when the board needs a feature that's not enabled.
2050 */
2051 if (!plat) {
b99d3659 2052 dev_err(dev, "no platform_data?\n");
34e2beb2
SS		 2053 status = -ENODEV;
2054 goto fail0;
550a7375 2055 }
34e2beb2 2056
550a7375 2057 /* allocate */
ca6d1b13 2058 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 2059 if (!musb) {
2060 status = -ENOMEM;
2061 goto fail0;
2062 }
550a7375
FB		 2063
2064 spin_lock_init(&musb->lock);
550a7375 2065 musb->board_set_power = plat->set_power;
550a7375 2066 musb->min_power = plat->min_power;
f7ec9437 2067 musb->ops = plat->platform_ops;
9ad96e69 2068 musb->port_mode = plat->mode;
550a7375 2069
1b40fc57
TL		 2070 /*
2071 * Initialize the default IO functions. At least omap2430 needs
2072 * these early. We initialize the platform specific IO functions
2073 * later on.
2074 */
2075 musb_readb = musb_default_readb;
2076 musb_writeb = musb_default_writeb;
2077 musb_readw = musb_default_readw;
2078 musb_writew = musb_default_writew;
2079 musb_readl = musb_default_readl;
2080 musb_writel = musb_default_writel;
2081
84e250ff 2082 /* The musb_platform_init() call:
baef653a
PDS		 2083 * - adjusts musb->mregs
2084 * - sets the musb->isr
5ae477b0 2085 * - may initialize an integrated transceiver
721002ec 2086 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 2087 * - stops powering VBUS
84e250ff 2088 *
7c9d440e 2089 * There are various transceiver configurations. Blackfin,
84e250ff
DB		 2090 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2091 * external/discrete ones in various flavors (twl4030 family,
2092 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375 2093 */
ea65df57 2094 status = musb_platform_init(musb);
550a7375 2095 if (status < 0)
03491761 2096 goto fail1;
34e2beb2 2097
550a7375
FB		 2098 if (!musb->isr) {
2099 status = -ENODEV;
c04352a5 2100 goto fail2;
550a7375
FB		 2101 }
2102
1b40fc57
TL		 2103 if (musb->ops->quirks)
2104 musb->io.quirks = musb->ops->quirks;
2105
da96cfc1 2106 /* Most devices use indexed offset or flat offset */
d026e9c7
TL		 2107 if (musb->io.quirks & MUSB_INDEXED_EP) {
2108 musb->io.ep_offset = musb_indexed_ep_offset;
2109 musb->io.ep_select = musb_indexed_ep_select;
2110 } else {
2111 musb->io.ep_offset = musb_flat_ep_offset;
2112 musb->io.ep_select = musb_flat_ep_select;
2113 }
2114
da96cfc1
BH		 2115 /* At least tusb6010 has its own offsets */
2116 if (musb->ops->ep_offset)
2117 musb->io.ep_offset = musb->ops->ep_offset;
2118 if (musb->ops->ep_select)
2119 musb->io.ep_select = musb->ops->ep_select;
2120
8a77f05a
TL		 2121 if (musb->ops->fifo_mode)
2122 fifo_mode = musb->ops->fifo_mode;
2123 else
2124 fifo_mode = 4;
2125
1b40fc57
TL		 2126 if (musb->ops->fifo_offset)
2127 musb->io.fifo_offset = musb->ops->fifo_offset;
2128 else
2129 musb->io.fifo_offset = musb_default_fifo_offset;
2130
6cc2af6d
HG		 2131 if (musb->ops->busctl_offset)
2132 musb->io.busctl_offset = musb->ops->busctl_offset;
2133 else
2134 musb->io.busctl_offset = musb_default_busctl_offset;
2135
1b40fc57
TL		 2136 if (musb->ops->readb)
2137 musb_readb = musb->ops->readb;
2138 if (musb->ops->writeb)
2139 musb_writeb = musb->ops->writeb;
2140 if (musb->ops->readw)
2141 musb_readw = musb->ops->readw;
2142 if (musb->ops->writew)
2143 musb_writew = musb->ops->writew;
2144 if (musb->ops->readl)
2145 musb_readl = musb->ops->readl;
2146 if (musb->ops->writel)
2147 musb_writel = musb->ops->writel;
2148
7f6283ed
TL		 2149#ifndef CONFIG_MUSB_PIO_ONLY
2150 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2151 dev_err(dev, "DMA controller not set\n");
7d32cdef 2152 status = -ENODEV;
7f6283ed
TL		 2153 goto fail2;
2154 }
2155 musb_dma_controller_create = musb->ops->dma_init;
2156 musb_dma_controller_destroy = musb->ops->dma_exit;
2157#endif
2158
1b40fc57
TL		 2159 if (musb->ops->read_fifo)
2160 musb->io.read_fifo = musb->ops->read_fifo;
2161 else
2162 musb->io.read_fifo = musb_default_read_fifo;
2163
2164 if (musb->ops->write_fifo)
2165 musb->io.write_fifo = musb->ops->write_fifo;
2166 else
2167 musb->io.write_fifo = musb_default_write_fifo;
2168
ffb865b1 2169 if (!musb->xceiv->io_ops) {
bf070bc1 2170 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 2171 musb->xceiv->io_priv = musb->mregs;
2172 musb->xceiv->io_ops = &musb_ulpi_access;
2173 }
2174
8055555f
TL		 2175 if (musb->ops->phy_callback)
2176 musb_phy_callback = musb->ops->phy_callback;
2177
f730f205
TL		 2178 /*
2179 * We need musb_read/write functions initialized for PM.
2180 * Note that at least 2430 glue needs autosuspend delay
2181 * somewhere above 300 ms for the hardware to idle properly
2182 * after disconnecting the cable in host mode. Let's use
2183 * 500 ms for some margin.
2184 */
2185 pm_runtime_use_autosuspend(musb->controller);
2186 pm_runtime_set_autosuspend_delay(musb->controller, 500);
2187 pm_runtime_enable(musb->controller);
c04352a5
GI		 2188 pm_runtime_get_sync(musb->controller);
2189
39cee200
UKK		 2190 status = usb_phy_init(musb->xceiv);
2191 if (status < 0)
2192 goto err_usb_phy_init;
2193
48054147 2194 if (use_dma && dev->dma_mask) {
7f6283ed
TL		 2195 musb->dma_controller =
2196 musb_dma_controller_create(musb, musb->mregs);
48054147
SAS		 2197 if (IS_ERR(musb->dma_controller)) {
2198 status = PTR_ERR(musb->dma_controller);
2199 goto fail2_5;
2200 }
2201 }
550a7375
FB		 2202
2203 /* be sure interrupts are disabled before connecting ISR */
2204 musb_platform_disable(musb);
2205 musb_generic_disable(musb);
2206
66fadea5
SAS		 2207 /* Init IRQ workqueue before request_irq */
2208 INIT_WORK(&musb->irq_work, musb_irq_work);
8ed1fb79
DM		 2209 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2210 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
66fadea5 2211
550a7375 2212 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 2213 status = musb_core_init(plat->config->multipoint
550a7375
FB		 2214 ? MUSB_CONTROLLER_MHDRC
2215 : MUSB_CONTROLLER_HDRC, musb);
2216 if (status < 0)
34e2beb2 2217 goto fail3;
550a7375 2218
f7f9d63e 2219 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
f7f9d63e 2220
550a7375 2221 /* attach to the IRQ */
427c4f33 2222 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
550a7375
FB		 2223 dev_err(dev, "request_irq %d failed!\n", nIrq);
2224 status = -ENODEV;
34e2beb2 2225 goto fail3;
550a7375
FB		 2226 }
2227 musb->nIrq = nIrq;
032ec49f 2228 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 2229 if (enable_irq_wake(nIrq) == 0) {
2230 musb->irq_wake = 1;
550a7375 2231 device_init_wakeup(dev, 1);
c48a5155
FB		 2232 } else {
2233 musb->irq_wake = 0;
2234 }
550a7375 2235
032ec49f
FB		 2236 /* program PHY to use external vBus if required */
2237 if (plat->extvbus) {
2238 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2239 busctl |= MUSB_ULPI_USE_EXTVBUS;
2240 musb_write_ulpi_buscontrol(musb->mregs, busctl);
550a7375 2241 }
550a7375 2242
e5615112
GI		 2243 if (musb->xceiv->otg->default_a) {
2244 MUSB_HST_MODE(musb);
e47d9254 2245 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
e5615112
GI		 2246 } else {
2247 MUSB_DEV_MODE(musb);
e47d9254 2248 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
e5615112 2249 }
550a7375 2250
6c5f6a6f
DM		 2251 switch (musb->port_mode) {
2252 case MUSB_PORT_MODE_HOST:
2253 status = musb_host_setup(musb, plat->power);
2df6761e
FB		 2254 if (status < 0)
2255 goto fail3;
2256 status = musb_platform_set_mode(musb, MUSB_HOST);
6c5f6a6f
DM		 2257 break;
2258 case MUSB_PORT_MODE_GADGET:
2259 status = musb_gadget_setup(musb);
2df6761e
FB		 2260 if (status < 0)
2261 goto fail3;
2262 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
6c5f6a6f
DM		 2263 break;
2264 case MUSB_PORT_MODE_DUAL_ROLE:
2265 status = musb_host_setup(musb, plat->power);
2266 if (status < 0)
2267 goto fail3;
2268 status = musb_gadget_setup(musb);
2df6761e 2269 if (status) {
0d2dd7ea 2270 musb_host_cleanup(musb);
2df6761e
FB		 2271 goto fail3;
2272 }
2273 status = musb_platform_set_mode(musb, MUSB_OTG);
6c5f6a6f
DM		 2274 break;
2275 default:
2276 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2277 break;
2278 }
550a7375 2279
461972d8 2280 if (status < 0)
34e2beb2 2281 goto fail3;
550a7375 2282
7f7f9e2a
FB		 2283 status = musb_init_debugfs(musb);
2284 if (status < 0)
b0f9da7e 2285 goto fail4;
7f7f9e2a 2286
94375751 2287 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
28c2c51c 2288 if (status)
b0f9da7e 2289 goto fail5;
550a7375 2290
7099dbc5
TL		 2291 pm_runtime_mark_last_busy(musb->controller);
2292 pm_runtime_put_autosuspend(musb->controller);
c04352a5 2293
28c2c51c 2294 return 0;
550a7375 2295
b0f9da7e
FB		 2296fail5:
2297 musb_exit_debugfs(musb);
2298
34e2beb2 2299fail4:
032ec49f 2300 musb_gadget_cleanup(musb);
0d2dd7ea 2301 musb_host_cleanup(musb);
34e2beb2
SS		 2302
2303fail3:
66fadea5 2304 cancel_work_sync(&musb->irq_work);
8ed1fb79
DM		 2305 cancel_delayed_work_sync(&musb->finish_resume_work);
2306 cancel_delayed_work_sync(&musb->deassert_reset_work);
f3ce4d5b 2307 if (musb->dma_controller)
7f6283ed 2308 musb_dma_controller_destroy(musb->dma_controller);
39cee200 2309
48054147 2310fail2_5:
39cee200
UKK		 2311 usb_phy_shutdown(musb->xceiv);
2312
2313err_usb_phy_init:
7099dbc5 2314 pm_runtime_dont_use_autosuspend(musb->controller);
c04352a5 2315 pm_runtime_put_sync(musb->controller);
f730f205 2316 pm_runtime_disable(musb->controller);
c04352a5
GI		 2317
2318fail2:
34e2beb2
SS		 2319 if (musb->irq_wake)
2320 device_init_wakeup(dev, 0);
550a7375 2321 musb_platform_exit(musb);
28c2c51c 2322
34e2beb2
SS		 2323fail1:
2324 dev_err(musb->controller,
2325 "musb_init_controller failed with status %d\n", status);
2326
28c2c51c
FB		 2327 musb_free(musb);
2328
34e2beb2
SS		 2329fail0:
2330
28c2c51c
FB		 2331 return status;
2332
550a7375
FB		 2333}
2334
2335/*-------------------------------------------------------------------------*/
2336
2337/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2338 * bridge to a platform device; this driver then suffices.
2339 */
41ac7b3a 2340static int musb_probe(struct platform_device *pdev)
550a7375
FB		 2341{
2342 struct device *dev = &pdev->dev;
fcf173e4 2343 int irq = platform_get_irq_byname(pdev, "mc");
550a7375
FB		 2344 struct resource *iomem;
2345 void __iomem *base;
2346
1f79b26c 2347 if (irq <= 0)
550a7375
FB		 2348 return -ENODEV;
2349
1f79b26c 2350 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b42f7f30
FB		 2351 base = devm_ioremap_resource(dev, iomem);
2352 if (IS_ERR(base))
2353 return PTR_ERR(base);
550a7375 2354
b42f7f30 2355 return musb_init_controller(dev, irq, base);
550a7375
FB		 2356}
2357
fb4e98ab 2358static int musb_remove(struct platform_device *pdev)
550a7375 2359{
8d2421e6
AKG		 2360 struct device *dev = &pdev->dev;
2361 struct musb *musb = dev_to_musb(dev);
302f6802 2362 unsigned long flags;
550a7375
FB		 2363
2364 /* this gets called on rmmod.
2365 * - Host mode: host may still be active
2366 * - Peripheral mode: peripheral is deactivated (or never-activated)
2367 * - OTG mode: both roles are deactivated (or never-activated)
2368 */
7f7f9e2a 2369 musb_exit_debugfs(musb);
302f6802 2370
f730f205
TL		 2371 cancel_work_sync(&musb->irq_work);
2372 cancel_delayed_work_sync(&musb->finish_resume_work);
2373 cancel_delayed_work_sync(&musb->deassert_reset_work);
302f6802
TL		 2374 pm_runtime_get_sync(musb->controller);
2375 musb_host_cleanup(musb);
2376 musb_gadget_cleanup(musb);
2377 spin_lock_irqsave(&musb->lock, flags);
2378 musb_platform_disable(musb);
2379 musb_generic_disable(musb);
2380 spin_unlock_irqrestore(&musb->lock, flags);
2381 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
f730f205
TL		 2382 pm_runtime_dont_use_autosuspend(musb->controller);
2383 pm_runtime_put_sync(musb->controller);
2384 pm_runtime_disable(musb->controller);
302f6802 2385 musb_platform_exit(musb);
8055555f 2386 musb_phy_callback = NULL;
8d1aad74 2387 if (musb->dma_controller)
7f6283ed 2388 musb_dma_controller_destroy(musb->dma_controller);
39cee200 2389 usb_phy_shutdown(musb->xceiv);
550a7375 2390 musb_free(musb);
8d2421e6 2391 device_init_wakeup(dev, 0);
550a7375
FB		 2392 return 0;
2393}
2394
2395#ifdef CONFIG_PM
2396
3c8a5fcc 2397static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2398{
2399 int i;
2400 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2401 void __iomem *epio;
4f712e01 2402
032ec49f
FB		 2403 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2404 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2405 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
7421107b 2406 musb->context.power = musb_readb(musb_base, MUSB_POWER);
7421107b
FB		 2407 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2408 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2409 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2410
ae9b2ad2 2411 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2412 struct musb_hw_ep *hw_ep;
2413
2414 hw_ep = &musb->endpoints[i];
2415 if (!hw_ep)
2416 continue;
2417
2418 epio = hw_ep->regs;
2419 if (!epio)
2420 continue;
2421
ea737554 2422 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2423 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2424 musb_readw(epio, MUSB_TXMAXP);
7421107b 2425 musb->context.index_regs[i].txcsr =
ae9b2ad2 2426 musb_readw(epio, MUSB_TXCSR);
7421107b 2427 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2428 musb_readw(epio, MUSB_RXMAXP);
7421107b 2429 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2430 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2431
2432 if (musb->dyn_fifo) {
7421107b 2433 musb->context.index_regs[i].txfifoadd =
4f712e01 2434 musb_read_txfifoadd(musb_base);
7421107b 2435 musb->context.index_regs[i].rxfifoadd =
4f712e01 2436 musb_read_rxfifoadd(musb_base);
7421107b 2437 musb->context.index_regs[i].txfifosz =
4f712e01 2438 musb_read_txfifosz(musb_base);
7421107b 2439 musb->context.index_regs[i].rxfifosz =
4f712e01
AKG		 2440 musb_read_rxfifosz(musb_base);
2441 }
032ec49f
FB		 2442
2443 musb->context.index_regs[i].txtype =
2444 musb_readb(epio, MUSB_TXTYPE);
2445 musb->context.index_regs[i].txinterval =
2446 musb_readb(epio, MUSB_TXINTERVAL);
2447 musb->context.index_regs[i].rxtype =
2448 musb_readb(epio, MUSB_RXTYPE);
2449 musb->context.index_regs[i].rxinterval =
2450 musb_readb(epio, MUSB_RXINTERVAL);
2451
2452 musb->context.index_regs[i].txfunaddr =
6cc2af6d 2453 musb_read_txfunaddr(musb, i);
032ec49f 2454 musb->context.index_regs[i].txhubaddr =
6cc2af6d 2455 musb_read_txhubaddr(musb, i);
032ec49f 2456 musb->context.index_regs[i].txhubport =
6cc2af6d 2457 musb_read_txhubport(musb, i);
032ec49f
FB		 2458
2459 musb->context.index_regs[i].rxfunaddr =
6cc2af6d 2460 musb_read_rxfunaddr(musb, i);
032ec49f 2461 musb->context.index_regs[i].rxhubaddr =
6cc2af6d 2462 musb_read_rxhubaddr(musb, i);
032ec49f 2463 musb->context.index_regs[i].rxhubport =
6cc2af6d 2464 musb_read_rxhubport(musb, i);
4f712e01 2465 }
4f712e01
AKG		 2466}
2467
3c8a5fcc 2468static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2469{
2470 int i;
2471 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2472 void __iomem *epio;
33f8d75f 2473 u8 power;
4f712e01 2474
032ec49f
FB		 2475 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2476 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2477 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
33f8d75f
RQ		 2478
2479 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2480 power = musb_readb(musb_base, MUSB_POWER);
2481 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2482 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2483 power |= musb->context.power;
2484 musb_writeb(musb_base, MUSB_POWER, power);
2485
b18d26f6 2486 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
af5ec14d 2487 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
7421107b 2488 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
84ac5d11
BL		 2489 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2490 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2491
ae9b2ad2 2492 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2493 struct musb_hw_ep *hw_ep;
2494
2495 hw_ep = &musb->endpoints[i];
2496 if (!hw_ep)
2497 continue;
2498
2499 epio = hw_ep->regs;
2500 if (!epio)
2501 continue;
2502
ea737554 2503 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2504 musb_writew(epio, MUSB_TXMAXP,
7421107b 2505 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2506 musb_writew(epio, MUSB_TXCSR,
7421107b 2507 musb->context.index_regs[i].txcsr);
ae9b2ad2 2508 musb_writew(epio, MUSB_RXMAXP,
7421107b 2509 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2510 musb_writew(epio, MUSB_RXCSR,
7421107b 2511 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2512
2513 if (musb->dyn_fifo) {
2514 musb_write_txfifosz(musb_base,
7421107b 2515 musb->context.index_regs[i].txfifosz);
4f712e01 2516 musb_write_rxfifosz(musb_base,
7421107b 2517 musb->context.index_regs[i].rxfifosz);
4f712e01 2518 musb_write_txfifoadd(musb_base,
7421107b 2519 musb->context.index_regs[i].txfifoadd);
4f712e01 2520 musb_write_rxfifoadd(musb_base,
7421107b 2521 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2522 }
2523
032ec49f 2524 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2525 musb->context.index_regs[i].txtype);
032ec49f 2526 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2527 musb->context.index_regs[i].txinterval);
032ec49f 2528 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2529 musb->context.index_regs[i].rxtype);
032ec49f 2530 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2531
032ec49f 2532 musb->context.index_regs[i].rxinterval);
6cc2af6d 2533 musb_write_txfunaddr(musb, i,
7421107b 2534 musb->context.index_regs[i].txfunaddr);
6cc2af6d 2535 musb_write_txhubaddr(musb, i,
7421107b 2536 musb->context.index_regs[i].txhubaddr);
6cc2af6d 2537 musb_write_txhubport(musb, i,
7421107b 2538 musb->context.index_regs[i].txhubport);
4f712e01 2539
6cc2af6d 2540 musb_write_rxfunaddr(musb, i,
7421107b 2541 musb->context.index_regs[i].rxfunaddr);
6cc2af6d 2542 musb_write_rxhubaddr(musb, i,
7421107b 2543 musb->context.index_regs[i].rxhubaddr);
6cc2af6d 2544 musb_write_rxhubport(musb, i,
7421107b 2545 musb->context.index_regs[i].rxhubport);
4f712e01 2546 }
3c5fec75 2547 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2548}
2549
48fea965 2550static int musb_suspend(struct device *dev)
550a7375 2551{
8220796d 2552 struct musb *musb = dev_to_musb(dev);
550a7375 2553 unsigned long flags;
550a7375 2554
6fc6f4b8
PH		 2555 musb_platform_disable(musb);
2556 musb_generic_disable(musb);
2557
550a7375
FB		 2558 spin_lock_irqsave(&musb->lock, flags);
2559
2560 if (is_peripheral_active(musb)) {
2561 /* FIXME force disconnect unless we know USB will wake
2562 * the system up quickly enough to respond ...
2563 */
2564 } else if (is_host_active(musb)) {
2565 /* we know all the children are suspended; sometimes
2566 * they will even be wakeup-enabled.
2567 */
2568 }
2569
c338412b
DM		 2570 musb_save_context(musb);
2571
550a7375
FB		 2572 spin_unlock_irqrestore(&musb->lock, flags);
2573 return 0;
2574}
2575
3e87d9a3 2576static int musb_resume(struct device *dev)
550a7375 2577{
c338412b 2578 struct musb *musb = dev_to_musb(dev);
b87fd2f7
SAS		 2579 u8 devctl;
2580 u8 mask;
c338412b
DM		 2581
2582 /*
2583 * For static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2584 * unless for some reason the whole soc powered down or the USB
2585 * module got reset through the PSC (vs just being disabled).
c338412b
DM		 2586 *
2587 * For the DSPS glue layer though, a full register restore has to
2588 * be done. As it shouldn't harm other platforms, we do it
2589 * unconditionally.
550a7375 2590 */
c338412b
DM		 2591
2592 musb_restore_context(musb);
2593
b87fd2f7
SAS		 2594 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2595 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2596 if ((devctl & mask) != (musb->context.devctl & mask))
2597 musb->port1_status = 0;
baadd52f
SAS		 2598 if (musb->need_finish_resume) {
2599 musb->need_finish_resume = 0;
2600 schedule_delayed_work(&musb->finish_resume_work,
309be239 2601 msecs_to_jiffies(USB_RESUME_TIMEOUT));
baadd52f 2602 }
a1fc1920
SAS		 2603
2604 /*
2605 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2606 * out of suspend
2607 */
2608 pm_runtime_disable(dev);
2609 pm_runtime_set_active(dev);
2610 pm_runtime_enable(dev);
6fc6f4b8
PH		 2611
2612 musb_start(musb);
2613
550a7375
FB		 2614 return 0;
2615}
2616
7acc6197
HH		 2617static int musb_runtime_suspend(struct device *dev)
2618{
2619 struct musb *musb = dev_to_musb(dev);
2620
2621 musb_save_context(musb);
2622
2623 return 0;
2624}
2625
2626static int musb_runtime_resume(struct device *dev)
2627{
2628 struct musb *musb = dev_to_musb(dev);
2629 static int first = 1;
2630
2631 /*
2632 * When pm_runtime_get_sync called for the first time in driver
2633 * init, some of the structure is still not initialized which is
2634 * used in restore function. But clock needs to be
2635 * enabled before any register access, so
2636 * pm_runtime_get_sync has to be called.
2637 * Also context restore without save does not make
2638 * any sense
2639 */
2640 if (!first)
2641 musb_restore_context(musb);
2642 first = 0;
2643
9298b4aa
BL		 2644 if (musb->need_finish_resume) {
2645 musb->need_finish_resume = 0;
2646 schedule_delayed_work(&musb->finish_resume_work,
309be239 2647 msecs_to_jiffies(USB_RESUME_TIMEOUT));
9298b4aa
BL		 2648 }
2649
7acc6197
HH		 2650 return 0;
2651}
2652
47145210 2653static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965 2654 .suspend = musb_suspend,
3e87d9a3 2655 .resume = musb_resume,
7acc6197
HH		 2656 .runtime_suspend = musb_runtime_suspend,
2657 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2658};
2659
2660#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2661#else
48fea965 2662#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2663#endif
2664
2665static struct platform_driver musb_driver = {
2666 .driver = {
2667 .name = (char *)musb_driver_name,
2668 .bus = &platform_bus_type,
48fea965 2669 .pm = MUSB_DEV_PM_OPS,
550a7375 2670 },
e9e8c85e 2671 .probe = musb_probe,
7690417d 2672 .remove = musb_remove,
550a7375
FB		 2673};
2674
89f836a8 2675module_platform_driver(musb_driver);
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