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usb: musb: Fix idling after host mode by increasing autosuspend delay
[mirror_ubuntu-hirsute-kernel.git] / drivers / usb / musb / musb_core.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35/*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82/*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
550a7375 85 * - platform_device for addressing, irq, and platform_data
5ae477b0 86 * - platform_data is mostly for board-specific information
c767c1c6 87 * (plus recentrly, SOC or family details)
550a7375
FB		 88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92#include <linux/module.h>
93#include <linux/kernel.h>
94#include <linux/sched.h>
95#include <linux/slab.h>
550a7375
FB		 96#include <linux/list.h>
97#include <linux/kobject.h>
9303961f 98#include <linux/prefetch.h>
550a7375
FB		 99#include <linux/platform_device.h>
100#include <linux/io.h>
8d2421e6 101#include <linux/dma-mapping.h>
309be239 102#include <linux/usb.h>
550a7375 103
550a7375
FB		 104#include "musb_core.h"
105
f7f9d63e 106#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 107
108
550a7375
FB		 109#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
110#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
111
e8164f64 112#define MUSB_VERSION "6.0"
550a7375
FB		 113
114#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
115
05ac10dd 116#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375
FB		 117const char musb_driver_name[] = MUSB_DRIVER_NAME;
118
119MODULE_DESCRIPTION(DRIVER_INFO);
120MODULE_AUTHOR(DRIVER_AUTHOR);
121MODULE_LICENSE("GPL");
122MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
123
124
125/*-------------------------------------------------------------------------*/
126
127static inline struct musb *dev_to_musb(struct device *dev)
128{
550a7375 129 return dev_get_drvdata(dev);
550a7375
FB		 130}
131
132/*-------------------------------------------------------------------------*/
133
ffb865b1 134#ifndef CONFIG_BLACKFIN
705e63d2 135static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
ffb865b1 136{
b96d3b08 137 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 138 int i = 0;
139 u8 r;
140 u8 power;
bf070bc1
GI		 141 int ret;
142
143 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 144
145 /* Make sure the transceiver is not in low power mode */
146 power = musb_readb(addr, MUSB_POWER);
147 power &= ~MUSB_POWER_SUSPENDM;
148 musb_writeb(addr, MUSB_POWER, power);
149
150 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
151 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
152 */
153
705e63d2 154 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
ffb865b1
HK		 155 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
156 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
157
158 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
159 & MUSB_ULPI_REG_CMPLT)) {
160 i++;
bf070bc1
GI		 161 if (i == 10000) {
162 ret = -ETIMEDOUT;
163 goto out;
164 }
ffb865b1
HK		 165
166 }
167 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
168 r &= ~MUSB_ULPI_REG_CMPLT;
169 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
170
bf070bc1
GI		 171 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
172
173out:
174 pm_runtime_put(phy->io_dev);
175
176 return ret;
ffb865b1
HK		 177}
178
705e63d2 179static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
ffb865b1 180{
b96d3b08 181 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 182 int i = 0;
183 u8 r = 0;
184 u8 power;
bf070bc1
GI		 185 int ret = 0;
186
187 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 188
189 /* Make sure the transceiver is not in low power mode */
190 power = musb_readb(addr, MUSB_POWER);
191 power &= ~MUSB_POWER_SUSPENDM;
192 musb_writeb(addr, MUSB_POWER, power);
193
705e63d2
UKK		 194 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
195 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
ffb865b1
HK		 196 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
197
198 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
199 & MUSB_ULPI_REG_CMPLT)) {
200 i++;
bf070bc1
GI		 201 if (i == 10000) {
202 ret = -ETIMEDOUT;
203 goto out;
204 }
ffb865b1
HK		 205 }
206
207 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
208 r &= ~MUSB_ULPI_REG_CMPLT;
209 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
210
bf070bc1
GI		 211out:
212 pm_runtime_put(phy->io_dev);
213
214 return ret;
ffb865b1
HK		 215}
216#else
f2263db7
MF		 217#define musb_ulpi_read NULL
218#define musb_ulpi_write NULL
ffb865b1
HK		 219#endif
220
b96d3b08 221static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 222 .read = musb_ulpi_read,
223 .write = musb_ulpi_write,
224};
225
226/*-------------------------------------------------------------------------*/
227
1b40fc57
TL		 228static u32 musb_default_fifo_offset(u8 epnum)
229{
230 return 0x20 + (epnum * 4);
231}
232
d026e9c7
TL		 233/* "flat" mapping: each endpoint has its own i/o address */
234static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
235{
236}
237
238static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
239{
240 return 0x100 + (0x10 * epnum) + offset;
241}
242
243/* "indexed" mapping: INDEX register controls register bank select */
244static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
245{
246 musb_writeb(mbase, MUSB_INDEX, epnum);
247}
248
249static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
250{
251 return 0x10 + offset;
252}
253
6cc2af6d
HG		 254static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
255{
256 return 0x80 + (0x08 * epnum) + offset;
257}
258
1b40fc57
TL		 259static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
260{
261 return __raw_readb(addr + offset);
262}
263
264static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
265{
266 __raw_writeb(data, addr + offset);
267}
268
269static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
270{
271 return __raw_readw(addr + offset);
272}
273
274static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
275{
276 __raw_writew(data, addr + offset);
277}
278
279static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
280{
281 return __raw_readl(addr + offset);
282}
283
284static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
285{
286 __raw_writel(data, addr + offset);
287}
c6cf8b00 288
550a7375
FB		 289/*
290 * Load an endpoint's FIFO
291 */
1b40fc57
TL		 292static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
293 const u8 *src)
550a7375 294{
5c8a86e1 295 struct musb *musb = hw_ep->musb;
550a7375
FB		 296 void __iomem *fifo = hw_ep->fifo;
297
603fe2b2
AKG		 298 if (unlikely(len == 0))
299 return;
300
550a7375
FB		 301 prefetch((u8 *)src);
302
5c8a86e1 303 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 304 'T', hw_ep->epnum, fifo, len, src);
305
306 /* we can't assume unaligned reads work */
307 if (likely((0x01 & (unsigned long) src) == 0)) {
308 u16 index = 0;
309
310 /* best case is 32bit-aligned source address */
311 if ((0x02 & (unsigned long) src) == 0) {
312 if (len >= 4) {
2bf0a8f6 313 iowrite32_rep(fifo, src + index, len >> 2);
550a7375
FB		 314 index += len & ~0x03;
315 }
316 if (len & 0x02) {
be780381 317 __raw_writew(*(u16 *)&src[index], fifo);
550a7375
FB		 318 index += 2;
319 }
320 } else {
321 if (len >= 2) {
2bf0a8f6 322 iowrite16_rep(fifo, src + index, len >> 1);
550a7375
FB		 323 index += len & ~0x01;
324 }
325 }
326 if (len & 0x01)
be780381 327 __raw_writeb(src[index], fifo);
550a7375
FB		 328 } else {
329 /* byte aligned */
2bf0a8f6 330 iowrite8_rep(fifo, src, len);
550a7375
FB		 331 }
332}
333
334/*
335 * Unload an endpoint's FIFO
336 */
1b40fc57 337static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
550a7375 338{
5c8a86e1 339 struct musb *musb = hw_ep->musb;
550a7375
FB		 340 void __iomem *fifo = hw_ep->fifo;
341
603fe2b2
AKG		 342 if (unlikely(len == 0))
343 return;
344
5c8a86e1 345 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 346 'R', hw_ep->epnum, fifo, len, dst);
347
348 /* we can't assume unaligned writes work */
349 if (likely((0x01 & (unsigned long) dst) == 0)) {
350 u16 index = 0;
351
352 /* best case is 32bit-aligned destination address */
353 if ((0x02 & (unsigned long) dst) == 0) {
354 if (len >= 4) {
2bf0a8f6 355 ioread32_rep(fifo, dst, len >> 2);
550a7375
FB		 356 index = len & ~0x03;
357 }
358 if (len & 0x02) {
be780381 359 *(u16 *)&dst[index] = __raw_readw(fifo);
550a7375
FB		 360 index += 2;
361 }
362 } else {
363 if (len >= 2) {
2bf0a8f6 364 ioread16_rep(fifo, dst, len >> 1);
550a7375
FB		 365 index = len & ~0x01;
366 }
367 }
368 if (len & 0x01)
be780381 369 dst[index] = __raw_readb(fifo);
550a7375
FB		 370 } else {
371 /* byte aligned */
2bf0a8f6 372 ioread8_rep(fifo, dst, len);
550a7375
FB		 373 }
374}
375
1b40fc57
TL		 376/*
377 * Old style IO functions
378 */
379u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
380EXPORT_SYMBOL_GPL(musb_readb);
381
382void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
383EXPORT_SYMBOL_GPL(musb_writeb);
550a7375 384
1b40fc57
TL		 385u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
386EXPORT_SYMBOL_GPL(musb_readw);
387
388void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
389EXPORT_SYMBOL_GPL(musb_writew);
390
391u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
392EXPORT_SYMBOL_GPL(musb_readl);
393
394void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
395EXPORT_SYMBOL_GPL(musb_writel);
396
7f6283ed
TL		 397#ifndef CONFIG_MUSB_PIO_ONLY
398struct dma_controller *
399(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
400EXPORT_SYMBOL(musb_dma_controller_create);
401
402void (*musb_dma_controller_destroy)(struct dma_controller *c);
403EXPORT_SYMBOL(musb_dma_controller_destroy);
404#endif
405
1b40fc57
TL		 406/*
407 * New style IO functions
408 */
409void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
410{
411 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
412}
413
414void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
415{
416 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
417}
550a7375
FB		 418
419/*-------------------------------------------------------------------------*/
420
421/* for high speed test mode; see USB 2.0 spec 7.1.20 */
422static const u8 musb_test_packet[53] = {
423 /* implicit SYNC then DATA0 to start */
424
425 /* JKJKJKJK x9 */
426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
427 /* JJKKJJKK x8 */
428 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
429 /* JJJJKKKK x8 */
430 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
431 /* JJJJJJJKKKKKKK x8 */
432 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
433 /* JJJJJJJK x8 */
434 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
435 /* JKKKKKKK x10, JK */
436 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
437
438 /* implicit CRC16 then EOP to end */
439};
440
441void musb_load_testpacket(struct musb *musb)
442{
443 void __iomem *regs = musb->endpoints[0].regs;
444
445 musb_ep_select(musb->mregs, 0);
446 musb_write_fifo(musb->control_ep,
447 sizeof(musb_test_packet), musb_test_packet);
448 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
449}
450
451/*-------------------------------------------------------------------------*/
452
550a7375
FB		 453/*
454 * Handles OTG hnp timeouts, such as b_ase0_brst
455 */
a156544b 456static void musb_otg_timer_func(unsigned long data)
550a7375
FB		 457{
458 struct musb *musb = (struct musb *)data;
459 unsigned long flags;
460
461 spin_lock_irqsave(&musb->lock, flags);
e47d9254 462 switch (musb->xceiv->otg->state) {
550a7375 463 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 464 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
550a7375 465 musb_g_disconnect(musb);
e47d9254 466 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 467 musb->is_active = 0;
468 break;
ab983f2a 469 case OTG_STATE_A_SUSPEND:
550a7375 470 case OTG_STATE_A_WAIT_BCON:
5c8a86e1 471 dev_dbg(musb->controller, "HNP: %s timeout\n",
e47d9254 472 usb_otg_state_string(musb->xceiv->otg->state));
743411b3 473 musb_platform_set_vbus(musb, 0);
e47d9254 474 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 475 break;
476 default:
5c8a86e1 477 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
e47d9254 478 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 479 }
550a7375
FB		 480 spin_unlock_irqrestore(&musb->lock, flags);
481}
482
550a7375 483/*
f7f9d63e 484 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 485 */
486void musb_hnp_stop(struct musb *musb)
487{
8b125df5 488 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 489 void __iomem *mbase = musb->mregs;
490 u8 reg;
491
42c0bf1c 492 dev_dbg(musb->controller, "HNP: stop from %s\n",
e47d9254 493 usb_otg_state_string(musb->xceiv->otg->state));
ab983f2a 494
e47d9254 495 switch (musb->xceiv->otg->state) {
550a7375 496 case OTG_STATE_A_PERIPHERAL:
550a7375 497 musb_g_disconnect(musb);
5c8a86e1 498 dev_dbg(musb->controller, "HNP: back to %s\n",
e47d9254 499 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 500 break;
501 case OTG_STATE_B_HOST:
5c8a86e1 502 dev_dbg(musb->controller, "HNP: Disabling HR\n");
74c2e936
DM		 503 if (hcd)
504 hcd->self.is_b_host = 0;
e47d9254 505 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 506 MUSB_DEV_MODE(musb);
507 reg = musb_readb(mbase, MUSB_POWER);
508 reg |= MUSB_POWER_SUSPENDM;
509 musb_writeb(mbase, MUSB_POWER, reg);
510 /* REVISIT: Start SESSION_REQUEST here? */
511 break;
512 default:
5c8a86e1 513 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
e47d9254 514 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 515 }
516
517 /*
518 * When returning to A state after HNP, avoid hub_port_rebounce(),
519 * which cause occasional OPT A "Did not receive reset after connect"
520 * errors.
521 */
749da5f8 522 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 523}
524
83b8f5b8 525static void musb_recover_from_babble(struct musb *musb);
e1eb3eb8 526
550a7375
FB		 527/*
528 * Interrupt Service Routine to record USB "global" interrupts.
529 * Since these do not happen often and signify things of
530 * paramount importance, it seems OK to check them individually;
531 * the order of the tests is specified in the manual
532 *
533 * @param musb instance pointer
534 * @param int_usb register contents
535 * @param devctl
536 * @param power
537 */
538
550a7375 539static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 540 u8 devctl)
550a7375
FB		 541{
542 irqreturn_t handled = IRQ_NONE;
550a7375 543
b11e94d0 544 dev_dbg(musb->controller, "<== DevCtl=%02x, int_usb=0x%x\n", devctl,
550a7375
FB		 545 int_usb);
546
547 /* in host mode, the peripheral may issue remote wakeup.
548 * in peripheral mode, the host may resume the link.
549 * spurious RESUME irqs happen too, paired with SUSPEND.
550 */
551 if (int_usb & MUSB_INTR_RESUME) {
552 handled = IRQ_HANDLED;
0acff6b8
FB		 553 dev_dbg(musb->controller, "RESUME (%s)\n",
554 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 555
556 if (devctl & MUSB_DEVCTL_HM) {
e47d9254 557 switch (musb->xceiv->otg->state) {
550a7375
FB		 558 case OTG_STATE_A_SUSPEND:
559 /* remote wakeup? later, GetPortStatus
560 * will stop RESUME signaling
561 */
562
550a7375
FB		 563 musb->port1_status |=
564 (USB_PORT_STAT_C_SUSPEND << 16)
565 | MUSB_PORT_STAT_RESUME;
30d361bf 566 musb->rh_timer = jiffies
309be239 567 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
baadd52f 568 musb->need_finish_resume = 1;
550a7375 569
e47d9254 570 musb->xceiv->otg->state = OTG_STATE_A_HOST;
550a7375 571 musb->is_active = 1;
9298b4aa 572 musb_host_resume_root_hub(musb);
550a7375
FB		 573 break;
574 case OTG_STATE_B_WAIT_ACON:
e47d9254 575 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 576 musb->is_active = 1;
577 MUSB_DEV_MODE(musb);
578 break;
579 default:
580 WARNING("bogus %s RESUME (%s)\n",
581 "host",
e47d9254 582 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 583 }
550a7375 584 } else {
e47d9254 585 switch (musb->xceiv->otg->state) {
550a7375
FB		 586 case OTG_STATE_A_SUSPEND:
587 /* possibly DISCONNECT is upcoming */
e47d9254 588 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44 589 musb_host_resume_root_hub(musb);
550a7375 590 break;
550a7375
FB		 591 case OTG_STATE_B_WAIT_ACON:
592 case OTG_STATE_B_PERIPHERAL:
593 /* disconnect while suspended? we may
594 * not get a disconnect irq...
595 */
596 if ((devctl & MUSB_DEVCTL_VBUS)
597 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
598 ) {
599 musb->int_usb |= MUSB_INTR_DISCONNECT;
600 musb->int_usb &= ~MUSB_INTR_SUSPEND;
601 break;
602 }
603 musb_g_resume(musb);
604 break;
605 case OTG_STATE_B_IDLE:
606 musb->int_usb &= ~MUSB_INTR_SUSPEND;
607 break;
550a7375
FB		 608 default:
609 WARNING("bogus %s RESUME (%s)\n",
610 "peripheral",
e47d9254 611 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 612 }
613 }
614 }
615
550a7375
FB		 616 /* see manual for the order of the tests */
617 if (int_usb & MUSB_INTR_SESSREQ) {
aa471456
FB		 618 void __iomem *mbase = musb->mregs;
619
19aab56c
HK		 620 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
621 && (devctl & MUSB_DEVCTL_BDEVICE)) {
5c8a86e1 622 dev_dbg(musb->controller, "SessReq while on B state\n");
a6038ee7
HK		 623 return IRQ_HANDLED;
624 }
625
5c8a86e1 626 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
e47d9254 627 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 628
629 /* IRQ arrives from ID pin sense or (later, if VBUS power
630 * is removed) SRP. responses are time critical:
631 * - turn on VBUS (with silicon-specific mechanism)
632 * - go through A_WAIT_VRISE
633 * - ... to A_WAIT_BCON.
634 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
635 */
636 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
637 musb->ep0_stage = MUSB_EP0_START;
e47d9254 638 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
550a7375 639 MUSB_HST_MODE(musb);
743411b3 640 musb_platform_set_vbus(musb, 1);
550a7375
FB		 641
642 handled = IRQ_HANDLED;
643 }
644
645 if (int_usb & MUSB_INTR_VBUSERROR) {
646 int ignore = 0;
647
648 /* During connection as an A-Device, we may see a short
649 * current spikes causing voltage drop, because of cable
650 * and peripheral capacitance combined with vbus draw.
651 * (So: less common with truly self-powered devices, where
652 * vbus doesn't act like a power supply.)
653 *
654 * Such spikes are short; usually less than ~500 usec, max
655 * of ~2 msec. That is, they're not sustained overcurrent
656 * errors, though they're reported using VBUSERROR irqs.
657 *
658 * Workarounds: (a) hardware: use self powered devices.
659 * (b) software: ignore non-repeated VBUS errors.
660 *
661 * REVISIT: do delays from lots of DEBUG_KERNEL checks
662 * make trouble here, keeping VBUS < 4.4V ?
663 */
e47d9254 664 switch (musb->xceiv->otg->state) {
550a7375
FB		 665 case OTG_STATE_A_HOST:
666 /* recovery is dicey once we've gotten past the
667 * initial stages of enumeration, but if VBUS
668 * stayed ok at the other end of the link, and
669 * another reset is due (at least for high speed,
670 * to redo the chirp etc), it might work OK...
671 */
672 case OTG_STATE_A_WAIT_BCON:
673 case OTG_STATE_A_WAIT_VRISE:
674 if (musb->vbuserr_retry) {
aa471456
FB		 675 void __iomem *mbase = musb->mregs;
676
550a7375
FB		 677 musb->vbuserr_retry--;
678 ignore = 1;
679 devctl |= MUSB_DEVCTL_SESSION;
680 musb_writeb(mbase, MUSB_DEVCTL, devctl);
681 } else {
682 musb->port1_status |=
749da5f8
AS		 683 USB_PORT_STAT_OVERCURRENT
684 | (USB_PORT_STAT_C_OVERCURRENT << 16);
550a7375
FB		 685 }
686 break;
687 default:
688 break;
689 }
690
54485116
GI		 691 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
692 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
e47d9254 693 usb_otg_state_string(musb->xceiv->otg->state),
550a7375
FB		 694 devctl,
695 ({ char *s;
696 switch (devctl & MUSB_DEVCTL_VBUS) {
697 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
698 s = "<SessEnd"; break;
699 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
700 s = "<AValid"; break;
701 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
702 s = "<VBusValid"; break;
703 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
704 default:
705 s = "VALID"; break;
2b84f92b 706 } s; }),
550a7375
FB		 707 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
708 musb->port1_status);
709
710 /* go through A_WAIT_VFALL then start a new session */
711 if (!ignore)
743411b3 712 musb_platform_set_vbus(musb, 0);
550a7375
FB		 713 handled = IRQ_HANDLED;
714 }
715
1c25fda4 716 if (int_usb & MUSB_INTR_SUSPEND) {
b11e94d0 717 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
e47d9254 718 usb_otg_state_string(musb->xceiv->otg->state), devctl);
1c25fda4
AM		 719 handled = IRQ_HANDLED;
720
e47d9254 721 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 722 case OTG_STATE_A_PERIPHERAL:
723 /* We also come here if the cable is removed, since
724 * this silicon doesn't report ID-no-longer-grounded.
725 *
726 * We depend on T(a_wait_bcon) to shut us down, and
727 * hope users don't do anything dicey during this
728 * undesired detour through A_WAIT_BCON.
729 */
730 musb_hnp_stop(musb);
0b3eba44 731 musb_host_resume_root_hub(musb);
1c25fda4
AM		 732 musb_root_disconnect(musb);
733 musb_platform_try_idle(musb, jiffies
734 + msecs_to_jiffies(musb->a_wait_bcon
735 ? : OTG_TIME_A_WAIT_BCON));
736
737 break;
1c25fda4
AM		 738 case OTG_STATE_B_IDLE:
739 if (!musb->is_active)
740 break;
741 case OTG_STATE_B_PERIPHERAL:
742 musb_g_suspend(musb);
eee3f15d 743 musb->is_active = musb->g.b_hnp_enable;
1c25fda4 744 if (musb->is_active) {
e47d9254 745 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
5c8a86e1 746 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
1c25fda4
AM		 747 mod_timer(&musb->otg_timer, jiffies
748 + msecs_to_jiffies(
749 OTG_TIME_B_ASE0_BRST));
1c25fda4
AM		 750 }
751 break;
752 case OTG_STATE_A_WAIT_BCON:
753 if (musb->a_wait_bcon != 0)
754 musb_platform_try_idle(musb, jiffies
755 + msecs_to_jiffies(musb->a_wait_bcon));
756 break;
757 case OTG_STATE_A_HOST:
e47d9254 758 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
eee3f15d 759 musb->is_active = musb->hcd->self.b_hnp_enable;
1c25fda4
AM		 760 break;
761 case OTG_STATE_B_HOST:
762 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
5c8a86e1 763 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
1c25fda4
AM		 764 break;
765 default:
766 /* "should not happen" */
767 musb->is_active = 0;
768 break;
769 }
770 }
771
550a7375 772 if (int_usb & MUSB_INTR_CONNECT) {
8b125df5 773 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 774
775 handled = IRQ_HANDLED;
776 musb->is_active = 1;
550a7375
FB		 777
778 musb->ep0_stage = MUSB_EP0_START;
779
b18d26f6
SAS		 780 musb->intrtxe = musb->epmask;
781 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
af5ec14d
SAS		 782 musb->intrrxe = musb->epmask & 0xfffe;
783 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
d709d22e 784 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 785 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
786 |USB_PORT_STAT_HIGH_SPEED
787 |USB_PORT_STAT_ENABLE
788 );
789 musb->port1_status |= USB_PORT_STAT_CONNECTION
790 |(USB_PORT_STAT_C_CONNECTION << 16);
791
792 /* high vs full speed is just a guess until after reset */
793 if (devctl & MUSB_DEVCTL_LSDEV)
794 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
795
550a7375 796 /* indicate new connection to OTG machine */
e47d9254 797 switch (musb->xceiv->otg->state) {
550a7375
FB		 798 case OTG_STATE_B_PERIPHERAL:
799 if (int_usb & MUSB_INTR_SUSPEND) {
5c8a86e1 800 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
550a7375 801 int_usb &= ~MUSB_INTR_SUSPEND;
1de00dae 802 goto b_host;
550a7375 803 } else
5c8a86e1 804 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
550a7375
FB		 805 break;
806 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 807 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
1de00dae 808b_host:
e47d9254 809 musb->xceiv->otg->state = OTG_STATE_B_HOST;
74c2e936
DM		 810 if (musb->hcd)
811 musb->hcd->self.is_b_host = 1;
1de00dae 812 del_timer(&musb->otg_timer);
550a7375
FB		 813 break;
814 default:
815 if ((devctl & MUSB_DEVCTL_VBUS)
816 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
e47d9254 817 musb->xceiv->otg->state = OTG_STATE_A_HOST;
0b3eba44
DM		 818 if (hcd)
819 hcd->self.is_b_host = 0;
550a7375
FB		 820 }
821 break;
822 }
1de00dae 823
0b3eba44 824 musb_host_poke_root_hub(musb);
1de00dae 825
5c8a86e1 826 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
e47d9254 827 usb_otg_state_string(musb->xceiv->otg->state), devctl);
550a7375 828 }
550a7375 829
6d349671 830 if (int_usb & MUSB_INTR_DISCONNECT) {
5c8a86e1 831 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
e47d9254 832 usb_otg_state_string(musb->xceiv->otg->state),
1c25fda4
AM		 833 MUSB_MODE(musb), devctl);
834 handled = IRQ_HANDLED;
835
e47d9254 836 switch (musb->xceiv->otg->state) {
1c25fda4
AM		 837 case OTG_STATE_A_HOST:
838 case OTG_STATE_A_SUSPEND:
0b3eba44 839 musb_host_resume_root_hub(musb);
1c25fda4 840 musb_root_disconnect(musb);
032ec49f 841 if (musb->a_wait_bcon != 0)
1c25fda4
AM		 842 musb_platform_try_idle(musb, jiffies
843 + msecs_to_jiffies(musb->a_wait_bcon));
844 break;
1c25fda4
AM		 845 case OTG_STATE_B_HOST:
846 /* REVISIT this behaves for "real disconnect"
847 * cases; make sure the other transitions from
848 * from B_HOST act right too. The B_HOST code
849 * in hnp_stop() is currently not used...
850 */
851 musb_root_disconnect(musb);
74c2e936
DM		 852 if (musb->hcd)
853 musb->hcd->self.is_b_host = 0;
e47d9254 854 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
1c25fda4
AM		 855 MUSB_DEV_MODE(musb);
856 musb_g_disconnect(musb);
857 break;
858 case OTG_STATE_A_PERIPHERAL:
859 musb_hnp_stop(musb);
860 musb_root_disconnect(musb);
861 /* FALLTHROUGH */
862 case OTG_STATE_B_WAIT_ACON:
863 /* FALLTHROUGH */
1c25fda4
AM		 864 case OTG_STATE_B_PERIPHERAL:
865 case OTG_STATE_B_IDLE:
866 musb_g_disconnect(musb);
867 break;
1c25fda4
AM		 868 default:
869 WARNING("unhandled DISCONNECT transition (%s)\n",
e47d9254 870 usb_otg_state_string(musb->xceiv->otg->state));
1c25fda4
AM		 871 break;
872 }
873 }
874
550a7375
FB		 875 /* mentor saves a bit: bus reset and babble share the same irq.
876 * only host sees babble; only peripheral sees bus reset.
877 */
878 if (int_usb & MUSB_INTR_RESET) {
1c25fda4 879 handled = IRQ_HANDLED;
896f7ea3 880 if (devctl & MUSB_DEVCTL_HM) {
550a7375 881 /*
34754dec 882 * When BABBLE happens what we can depends on which
28378d5e
FB		 883 * platform MUSB is running, because some platforms
884 * implemented proprietary means for 'recovering' from
885 * Babble conditions. One such platform is AM335x. In
34754dec
FB		 886 * most cases, however, the only thing we can do is
887 * drop the session.
550a7375 888 */
34754dec 889 dev_err(musb->controller, "Babble\n");
d0fc0a20 890
34754dec
FB		 891 if (is_host_active(musb))
892 musb_recover_from_babble(musb);
a04d46d0 893 } else {
5c8a86e1 894 dev_dbg(musb->controller, "BUS RESET as %s\n",
e47d9254
AT		 895 usb_otg_state_string(musb->xceiv->otg->state));
896 switch (musb->xceiv->otg->state) {
550a7375 897 case OTG_STATE_A_SUSPEND:
550a7375
FB		 898 musb_g_reset(musb);
899 /* FALLTHROUGH */
900 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
f7f9d63e 901 /* never use invalid T(a_wait_bcon) */
5c8a86e1 902 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
e47d9254 903 usb_otg_state_string(musb->xceiv->otg->state),
3df00453 904 TA_WAIT_BCON(musb));
f7f9d63e
DB		 905 mod_timer(&musb->otg_timer, jiffies
906 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
550a7375
FB		 907 break;
908 case OTG_STATE_A_PERIPHERAL:
1de00dae
DB		 909 del_timer(&musb->otg_timer);
910 musb_g_reset(musb);
550a7375
FB		 911 break;
912 case OTG_STATE_B_WAIT_ACON:
5c8a86e1 913 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
e47d9254
AT		 914 usb_otg_state_string(musb->xceiv->otg->state));
915 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 916 musb_g_reset(musb);
917 break;
550a7375 918 case OTG_STATE_B_IDLE:
e47d9254 919 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 920 /* FALLTHROUGH */
921 case OTG_STATE_B_PERIPHERAL:
922 musb_g_reset(musb);
923 break;
924 default:
5c8a86e1 925 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
e47d9254 926 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 927 }
928 }
550a7375 929 }
550a7375
FB		 930
931#if 0
932/* REVISIT ... this would be for multiplexing periodic endpoints, or
933 * supporting transfer phasing to prevent exceeding ISO bandwidth
934 * limits of a given frame or microframe.
935 *
936 * It's not needed for peripheral side, which dedicates endpoints;
937 * though it _might_ use SOF irqs for other purposes.
938 *
939 * And it's not currently needed for host side, which also dedicates
940 * endpoints, relies on TX/RX interval registers, and isn't claimed
941 * to support ISO transfers yet.
942 */
943 if (int_usb & MUSB_INTR_SOF) {
944 void __iomem *mbase = musb->mregs;
945 struct musb_hw_ep *ep;
946 u8 epnum;
947 u16 frame;
948
5c8a86e1 949 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 950 handled = IRQ_HANDLED;
951
952 /* start any periodic Tx transfers waiting for current frame */
953 frame = musb_readw(mbase, MUSB_FRAME);
954 ep = musb->endpoints;
955 for (epnum = 1; (epnum < musb->nr_endpoints)
956 && (musb->epmask >= (1 << epnum));
957 epnum++, ep++) {
958 /*
959 * FIXME handle framecounter wraps (12 bits)
960 * eliminate duplicated StartUrb logic
961 */
962 if (ep->dwWaitFrame >= frame) {
963 ep->dwWaitFrame = 0;
964 pr_debug("SOF --> periodic TX%s on %d\n",
965 ep->tx_channel ? " DMA" : "",
966 epnum);
967 if (!ep->tx_channel)
968 musb_h_tx_start(musb, epnum);
969 else
970 cppi_hostdma_start(musb, epnum);
971 }
972 } /* end of for loop */
973 }
974#endif
975
1c25fda4 976 schedule_work(&musb->irq_work);
550a7375
FB		 977
978 return handled;
979}
980
981/*-------------------------------------------------------------------------*/
982
e1eb3eb8 983static void musb_disable_interrupts(struct musb *musb)
550a7375
FB		 984{
985 void __iomem *mbase = musb->mregs;
986 u16 temp;
987
988 /* disable interrupts */
989 musb_writeb(mbase, MUSB_INTRUSBE, 0);
b18d26f6 990 musb->intrtxe = 0;
550a7375 991 musb_writew(mbase, MUSB_INTRTXE, 0);
af5ec14d 992 musb->intrrxe = 0;
550a7375
FB		 993 musb_writew(mbase, MUSB_INTRRXE, 0);
994
550a7375
FB		 995 /* flush pending interrupts */
996 temp = musb_readb(mbase, MUSB_INTRUSB);
997 temp = musb_readw(mbase, MUSB_INTRTX);
998 temp = musb_readw(mbase, MUSB_INTRRX);
e1eb3eb8
FB		 999}
1000
1001static void musb_enable_interrupts(struct musb *musb)
1002{
1003 void __iomem *regs = musb->mregs;
1004
1005 /* Set INT enable registers, enable interrupts */
1006 musb->intrtxe = musb->epmask;
1007 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1008 musb->intrrxe = musb->epmask & 0xfffe;
1009 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1010 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 1011
1012}
1013
e1eb3eb8
FB		 1014static void musb_generic_disable(struct musb *musb)
1015{
1016 void __iomem *mbase = musb->mregs;
1017
1018 musb_disable_interrupts(musb);
1019
1020 /* off */
1021 musb_writeb(mbase, MUSB_DEVCTL, 0);
1022}
1023
001dd84a
SAS		 1024/*
1025 * Program the HDRC to start (enable interrupts, dma, etc.).
1026 */
1027void musb_start(struct musb *musb)
1028{
1029 void __iomem *regs = musb->mregs;
1030 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
9b753764 1031 u8 power;
001dd84a
SAS		 1032
1033 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
1034
e1eb3eb8 1035 musb_enable_interrupts(musb);
001dd84a
SAS		 1036 musb_writeb(regs, MUSB_TESTMODE, 0);
1037
9b753764
BL		 1038 power = MUSB_POWER_ISOUPDATE;
1039 /*
1040 * treating UNKNOWN as unspecified maximum speed, in which case
1041 * we will default to high-speed.
1042 */
1043 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1044 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1045 power |= MUSB_POWER_HSENAB;
1046 musb_writeb(regs, MUSB_POWER, power);
001dd84a
SAS		 1047
1048 musb->is_active = 0;
1049 devctl = musb_readb(regs, MUSB_DEVCTL);
1050 devctl &= ~MUSB_DEVCTL_SESSION;
1051
1052 /* session started after:
1053 * (a) ID-grounded irq, host mode;
1054 * (b) vbus present/connect IRQ, peripheral mode;
1055 * (c) peripheral initiates, using SRP
1056 */
1057 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
40af177e 1058 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
001dd84a
SAS		 1059 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1060 musb->is_active = 1;
1061 } else {
1062 devctl |= MUSB_DEVCTL_SESSION;
1063 }
1064
1065 musb_platform_enable(musb);
1066 musb_writeb(regs, MUSB_DEVCTL, devctl);
1067}
1068
550a7375
FB		 1069/*
1070 * Make the HDRC stop (disable interrupts, etc.);
1071 * reversible by musb_start
1072 * called on gadget driver unregister
1073 * with controller locked, irqs blocked
1074 * acts as a NOP unless some role activated the hardware
1075 */
1076void musb_stop(struct musb *musb)
1077{
1078 /* stop IRQs, timers, ... */
1079 musb_platform_disable(musb);
1080 musb_generic_disable(musb);
5c8a86e1 1081 dev_dbg(musb->controller, "HDRC disabled\n");
550a7375
FB		 1082
1083 /* FIXME
1084 * - mark host and/or peripheral drivers unusable/inactive
1085 * - disable DMA (and enable it in HdrcStart)
1086 * - make sure we can musb_start() after musb_stop(); with
1087 * OTG mode, gadget driver module rmmod/modprobe cycles that
1088 * - ...
1089 */
1090 musb_platform_try_idle(musb, 0);
1091}
1092
1093static void musb_shutdown(struct platform_device *pdev)
1094{
1095 struct musb *musb = dev_to_musb(&pdev->dev);
1096 unsigned long flags;
1097
4f9edd2d 1098 pm_runtime_get_sync(musb->controller);
24307cae 1099
2cc65fea 1100 musb_host_cleanup(musb);
24307cae
GI		 1101 musb_gadget_cleanup(musb);
1102
550a7375
FB		 1103 spin_lock_irqsave(&musb->lock, flags);
1104 musb_platform_disable(musb);
1105 musb_generic_disable(musb);
550a7375
FB		 1106 spin_unlock_irqrestore(&musb->lock, flags);
1107
120d074c
GI		 1108 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1109 musb_platform_exit(musb);
120d074c 1110
4f9edd2d 1111 pm_runtime_put(musb->controller);
550a7375
FB		 1112 /* FIXME power down */
1113}
1114
1115
1116/*-------------------------------------------------------------------------*/
1117
1118/*
1119 * The silicon either has hard-wired endpoint configurations, or else
1120 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1121 * writing only the dynamic sizing is very well tested. Since we switched
1122 * away from compile-time hardware parameters, we can no longer rely on
1123 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1124 *
1125 * We don't currently use dynamic fifo setup capability to do anything
1126 * more than selecting one of a bunch of predefined configurations.
1127 */
8a77f05a 1128static ushort fifo_mode;
550a7375
FB		 1129
1130/* "modprobe ... fifo_mode=1" etc */
1131module_param(fifo_mode, ushort, 0);
1132MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1133
550a7375
FB		 1134/*
1135 * tables defining fifo_mode values. define more if you like.
1136 * for host side, make sure both halves of ep1 are set up.
1137 */
1138
1139/* mode 0 - fits in 2KB */
d3608b6d 1140static struct musb_fifo_cfg mode_0_cfg[] = {
550a7375
FB		 1141{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1142{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1143{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1144{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1145{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1146};
1147
1148/* mode 1 - fits in 4KB */
d3608b6d 1149static struct musb_fifo_cfg mode_1_cfg[] = {
550a7375
FB		 1150{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1151{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1152{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1153{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1154{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1155};
1156
1157/* mode 2 - fits in 4KB */
d3608b6d 1158static struct musb_fifo_cfg mode_2_cfg[] = {
550a7375
FB		 1159{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1160{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1161{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1162{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1163{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1164{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1165};
1166
1167/* mode 3 - fits in 4KB */
d3608b6d 1168static struct musb_fifo_cfg mode_3_cfg[] = {
550a7375
FB		 1169{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1170{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1171{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1172{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1173{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1174{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1175};
1176
1177/* mode 4 - fits in 16KB */
d3608b6d 1178static struct musb_fifo_cfg mode_4_cfg[] = {
550a7375
FB		 1179{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1180{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1181{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1182{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1183{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1184{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1185{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1186{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1187{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1188{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1189{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1190{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1191{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1192{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1193{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1194{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1195{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1196{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1197{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1198{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1199{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1200{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1201{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1202{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1203{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1204{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1205{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1206};
1207
3b151526 1208/* mode 5 - fits in 8KB */
d3608b6d 1209static struct musb_fifo_cfg mode_5_cfg[] = {
3b151526
AKG		 1210{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1211{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1212{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1213{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1214{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1215{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1216{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1217{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1218{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1219{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1220{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1221{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1222{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1223{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1224{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1225{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1226{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1227{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1228{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1229{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1230{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1231{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1232{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1233{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1234{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1235{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1236{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1237};
550a7375
FB		 1238
1239/*
1240 * configure a fifo; for non-shared endpoints, this may be called
1241 * once for a tx fifo and once for an rx fifo.
1242 *
1243 * returns negative errno or offset for next fifo.
1244 */
41ac7b3a 1245static int
550a7375 1246fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1247 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1248{
1249 void __iomem *mbase = musb->mregs;
1250 int size = 0;
1251 u16 maxpacket = cfg->maxpacket;
1252 u16 c_off = offset >> 3;
1253 u8 c_size;
1254
1255 /* expect hw_ep has already been zero-initialized */
1256
1257 size = ffs(max(maxpacket, (u16) 8)) - 1;
1258 maxpacket = 1 << size;
1259
1260 c_size = size - 3;
1261 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1262 if ((offset + (maxpacket << 1)) >
1263 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1264 return -EMSGSIZE;
1265 c_size |= MUSB_FIFOSZ_DPB;
1266 } else {
ca6d1b13 1267 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1268 return -EMSGSIZE;
1269 }
1270
1271 /* configure the FIFO */
1272 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1273
550a7375 1274 /* EP0 reserved endpoint for control, bidirectional;
5ae477b0 1275 * EP1 reserved for bulk, two unidirectional halves.
550a7375
FB		 1276 */
1277 if (hw_ep->epnum == 1)
1278 musb->bulk_ep = hw_ep;
1279 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1280 switch (cfg->style) {
1281 case FIFO_TX:
c6cf8b00
BW		 1282 musb_write_txfifosz(mbase, c_size);
1283 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1284 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1285 hw_ep->max_packet_sz_tx = maxpacket;
1286 break;
1287 case FIFO_RX:
c6cf8b00
BW		 1288 musb_write_rxfifosz(mbase, c_size);
1289 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1290 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1291 hw_ep->max_packet_sz_rx = maxpacket;
1292 break;
1293 case FIFO_RXTX:
c6cf8b00
BW		 1294 musb_write_txfifosz(mbase, c_size);
1295 musb_write_txfifoadd(mbase, c_off);
550a7375
FB		 1296 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1297 hw_ep->max_packet_sz_rx = maxpacket;
1298
c6cf8b00
BW		 1299 musb_write_rxfifosz(mbase, c_size);
1300 musb_write_rxfifoadd(mbase, c_off);
550a7375
FB		 1301 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1302 hw_ep->max_packet_sz_tx = maxpacket;
1303
1304 hw_ep->is_shared_fifo = true;
1305 break;
1306 }
1307
1308 /* NOTE rx and tx endpoint irqs aren't managed separately,
1309 * which happens to be ok
1310 */
1311 musb->epmask |= (1 << hw_ep->epnum);
1312
1313 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1314}
1315
d3608b6d 1316static struct musb_fifo_cfg ep0_cfg = {
550a7375
FB		 1317 .style = FIFO_RXTX, .maxpacket = 64,
1318};
1319
41ac7b3a 1320static int ep_config_from_table(struct musb *musb)
550a7375 1321{
e6c213b2 1322 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1323 unsigned i, n;
1324 int offset;
1325 struct musb_hw_ep *hw_ep = musb->endpoints;
1326
e6c213b2
FB		 1327 if (musb->config->fifo_cfg) {
1328 cfg = musb->config->fifo_cfg;
1329 n = musb->config->fifo_cfg_size;
1330 goto done;
1331 }
1332
550a7375
FB		 1333 switch (fifo_mode) {
1334 default:
1335 fifo_mode = 0;
1336 /* FALLTHROUGH */
1337 case 0:
1338 cfg = mode_0_cfg;
1339 n = ARRAY_SIZE(mode_0_cfg);
1340 break;
1341 case 1:
1342 cfg = mode_1_cfg;
1343 n = ARRAY_SIZE(mode_1_cfg);
1344 break;
1345 case 2:
1346 cfg = mode_2_cfg;
1347 n = ARRAY_SIZE(mode_2_cfg);
1348 break;
1349 case 3:
1350 cfg = mode_3_cfg;
1351 n = ARRAY_SIZE(mode_3_cfg);
1352 break;
1353 case 4:
1354 cfg = mode_4_cfg;
1355 n = ARRAY_SIZE(mode_4_cfg);
1356 break;
3b151526
AKG		 1357 case 5:
1358 cfg = mode_5_cfg;
1359 n = ARRAY_SIZE(mode_5_cfg);
1360 break;
550a7375
FB		 1361 }
1362
3ff4b573 1363 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
550a7375
FB		 1364
1365
e6c213b2 1366done:
550a7375
FB		 1367 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1368 /* assert(offset > 0) */
1369
1370 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1371 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1372 */
1373
1374 for (i = 0; i < n; i++) {
1375 u8 epn = cfg->hw_ep_num;
1376
ca6d1b13 1377 if (epn >= musb->config->num_eps) {
550a7375
FB		 1378 pr_debug("%s: invalid ep %d\n",
1379 musb_driver_name, epn);
bb1c9ef1 1380 return -EINVAL;
550a7375
FB		 1381 }
1382 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1383 if (offset < 0) {
1384 pr_debug("%s: mem overrun, ep %d\n",
1385 musb_driver_name, epn);
f69dfa1f 1386 return offset;
550a7375
FB		 1387 }
1388 epn++;
1389 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1390 }
1391
3ff4b573 1392 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
550a7375 1393 musb_driver_name,
ca6d1b13
FB		 1394 n + 1, musb->config->num_eps * 2 - 1,
1395 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1396
550a7375
FB		 1397 if (!musb->bulk_ep) {
1398 pr_debug("%s: missing bulk\n", musb_driver_name);
1399 return -EINVAL;
1400 }
550a7375
FB		 1401
1402 return 0;
1403}
1404
1405
1406/*
1407 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1408 * @param musb the controller
1409 */
41ac7b3a 1410static int ep_config_from_hw(struct musb *musb)
550a7375 1411{
c6cf8b00 1412 u8 epnum = 0;
550a7375 1413 struct musb_hw_ep *hw_ep;
a156544b 1414 void __iomem *mbase = musb->mregs;
c6cf8b00 1415 int ret = 0;
550a7375 1416
5c8a86e1 1417 dev_dbg(musb->controller, "<== static silicon ep config\n");
550a7375
FB		 1418
1419 /* FIXME pick up ep0 maxpacket size */
1420
ca6d1b13 1421 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1422 musb_ep_select(mbase, epnum);
1423 hw_ep = musb->endpoints + epnum;
1424
c6cf8b00
BW		 1425 ret = musb_read_fifosize(musb, hw_ep, epnum);
1426 if (ret < 0)
550a7375 1427 break;
550a7375
FB		 1428
1429 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1430
550a7375
FB		 1431 /* pick an RX/TX endpoint for bulk */
1432 if (hw_ep->max_packet_sz_tx < 512
1433 || hw_ep->max_packet_sz_rx < 512)
1434 continue;
1435
1436 /* REVISIT: this algorithm is lazy, we should at least
1437 * try to pick a double buffered endpoint.
1438 */
1439 if (musb->bulk_ep)
1440 continue;
1441 musb->bulk_ep = hw_ep;
550a7375
FB		 1442 }
1443
550a7375
FB		 1444 if (!musb->bulk_ep) {
1445 pr_debug("%s: missing bulk\n", musb_driver_name);
1446 return -EINVAL;
1447 }
550a7375
FB		 1448
1449 return 0;
1450}
1451
1452enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1453
1454/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1455 * configure endpoints, or take their config from silicon
1456 */
41ac7b3a 1457static int musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1458{
550a7375
FB		 1459 u8 reg;
1460 char *type;
0ea52ff4 1461 char aInfo[90], aRevision[32], aDate[12];
550a7375
FB		 1462 void __iomem *mbase = musb->mregs;
1463 int status = 0;
1464 int i;
1465
1466 /* log core options (read using indexed model) */
c6cf8b00 1467 reg = musb_read_configdata(mbase);
550a7375
FB		 1468
1469 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1470 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1471 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1472 musb->dyn_fifo = true;
1473 }
550a7375
FB		 1474 if (reg & MUSB_CONFIGDATA_MPRXE) {
1475 strcat(aInfo, ", bulk combine");
550a7375 1476 musb->bulk_combine = true;
550a7375
FB		 1477 }
1478 if (reg & MUSB_CONFIGDATA_MPTXE) {
1479 strcat(aInfo, ", bulk split");
550a7375 1480 musb->bulk_split = true;
550a7375
FB		 1481 }
1482 if (reg & MUSB_CONFIGDATA_HBRXE) {
1483 strcat(aInfo, ", HB-ISO Rx");
a483d706 1484 musb->hb_iso_rx = true;
550a7375
FB		 1485 }
1486 if (reg & MUSB_CONFIGDATA_HBTXE) {
1487 strcat(aInfo, ", HB-ISO Tx");
a483d706 1488 musb->hb_iso_tx = true;
550a7375
FB		 1489 }
1490 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1491 strcat(aInfo, ", SoftConn");
1492
3ff4b573 1493 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
550a7375 1494
550a7375 1495 aDate[0] = 0;
550a7375
FB		 1496 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1497 musb->is_multipoint = 1;
1498 type = "M";
1499 } else {
1500 musb->is_multipoint = 0;
1501 type = "";
550a7375 1502#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
3ff4b573
RV		 1503 pr_err("%s: kernel must blacklist external hubs\n",
1504 musb_driver_name);
550a7375
FB		 1505#endif
1506 }
1507
1508 /* log release info */
32c3b94e
AG		 1509 musb->hwvers = musb_read_hwvers(mbase);
1510 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1511 MUSB_HWVERS_MINOR(musb->hwvers),
1512 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
3ff4b573
RV		 1513 pr_debug("%s: %sHDRC RTL version %s %s\n",
1514 musb_driver_name, type, aRevision, aDate);
550a7375
FB		 1515
1516 /* configure ep0 */
c6cf8b00 1517 musb_configure_ep0(musb);
550a7375
FB		 1518
1519 /* discover endpoint configuration */
1520 musb->nr_endpoints = 1;
1521 musb->epmask = 1;
1522
ad517e9e
FB		 1523 if (musb->dyn_fifo)
1524 status = ep_config_from_table(musb);
1525 else
1526 status = ep_config_from_hw(musb);
550a7375
FB		 1527
1528 if (status < 0)
1529 return status;
1530
1531 /* finish init, and print endpoint config */
1532 for (i = 0; i < musb->nr_endpoints; i++) {
1533 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1534
1b40fc57 1535 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
ebf39920 1536#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1b40fc57
TL		 1537 if (musb->io.quirks & MUSB_IN_TUSB) {
1538 hw_ep->fifo_async = musb->async + 0x400 +
1539 musb->io.fifo_offset(i);
1540 hw_ep->fifo_sync = musb->sync + 0x400 +
1541 musb->io.fifo_offset(i);
1542 hw_ep->fifo_sync_va =
1543 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1544
1545 if (i == 0)
1546 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1547 else
1548 hw_ep->conf = mbase + 0x400 +
1549 (((i - 1) & 0xf) << 2);
1550 }
550a7375
FB		 1551#endif
1552
d026e9c7 1553 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
550a7375
FB		 1554 hw_ep->rx_reinit = 1;
1555 hw_ep->tx_reinit = 1;
550a7375
FB		 1556
1557 if (hw_ep->max_packet_sz_tx) {
5c8a86e1 1558 dev_dbg(musb->controller,
550a7375
FB		 1559 "%s: hw_ep %d%s, %smax %d\n",
1560 musb_driver_name, i,
1561 hw_ep->is_shared_fifo ? "shared" : "tx",
1562 hw_ep->tx_double_buffered
1563 ? "doublebuffer, " : "",
1564 hw_ep->max_packet_sz_tx);
1565 }
1566 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
5c8a86e1 1567 dev_dbg(musb->controller,
550a7375
FB		 1568 "%s: hw_ep %d%s, %smax %d\n",
1569 musb_driver_name, i,
1570 "rx",
1571 hw_ep->rx_double_buffered
1572 ? "doublebuffer, " : "",
1573 hw_ep->max_packet_sz_rx);
1574 }
1575 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
5c8a86e1 1576 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
550a7375
FB		 1577 }
1578
1579 return 0;
1580}
1581
1582/*-------------------------------------------------------------------------*/
1583
550a7375
FB		 1584/*
1585 * handle all the irqs defined by the HDRC core. for now we expect: other
1586 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1587 * will be assigned, and the irq will already have been acked.
1588 *
1589 * called in irq context with spinlock held, irqs blocked
1590 */
1591irqreturn_t musb_interrupt(struct musb *musb)
1592{
1593 irqreturn_t retval = IRQ_NONE;
31a0ede0
FB		 1594 unsigned long status;
1595 unsigned long epnum;
b11e94d0 1596 u8 devctl;
31a0ede0
FB		 1597
1598 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1599 return IRQ_NONE;
550a7375
FB		 1600
1601 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1602
5c8a86e1 1603 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
c03da38d 1604 is_host_active(musb) ? "host" : "peripheral",
550a7375
FB		 1605 musb->int_usb, musb->int_tx, musb->int_rx);
1606
e3c93e1a
FB		 1607 /**
1608 * According to Mentor Graphics' documentation, flowchart on page 98,
1609 * IRQ should be handled as follows:
1610 *
1611 * . Resume IRQ
1612 * . Session Request IRQ
1613 * . VBUS Error IRQ
1614 * . Suspend IRQ
1615 * . Connect IRQ
1616 * . Disconnect IRQ
1617 * . Reset/Babble IRQ
1618 * . SOF IRQ (we're not using this one)
1619 * . Endpoint 0 IRQ
1620 * . TX Endpoints
1621 * . RX Endpoints
1622 *
1623 * We will be following that flowchart in order to avoid any problems
1624 * that might arise with internal Finite State Machine.
550a7375 1625 */
e3c93e1a 1626
7d9645fd 1627 if (musb->int_usb)
31a0ede0 1628 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
550a7375 1629
550a7375 1630 if (musb->int_tx & 1) {
c03da38d 1631 if (is_host_active(musb))
550a7375
FB		 1632 retval |= musb_h_ep0_irq(musb);
1633 else
1634 retval |= musb_g_ep0_irq(musb);
31a0ede0
FB		 1635
1636 /* we have just handled endpoint 0 IRQ, clear it */
1637 musb->int_tx &= ~BIT(0);
550a7375
FB		 1638 }
1639
31a0ede0
FB		 1640 status = musb->int_tx;
1641
1642 for_each_set_bit(epnum, &status, 16) {
1643 retval = IRQ_HANDLED;
1644 if (is_host_active(musb))
1645 musb_host_tx(musb, epnum);
1646 else
1647 musb_g_tx(musb, epnum);
550a7375
FB		 1648 }
1649
31a0ede0 1650 status = musb->int_rx;
e3c93e1a 1651
31a0ede0
FB		 1652 for_each_set_bit(epnum, &status, 16) {
1653 retval = IRQ_HANDLED;
1654 if (is_host_active(musb))
1655 musb_host_rx(musb, epnum);
1656 else
1657 musb_g_rx(musb, epnum);
550a7375
FB		 1658 }
1659
550a7375
FB		 1660 return retval;
1661}
981430a1 1662EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1663
1664#ifndef CONFIG_MUSB_PIO_ONLY
d3608b6d 1665static bool use_dma = 1;
550a7375
FB		 1666
1667/* "modprobe ... use_dma=0" etc */
51676c8d 1668module_param(use_dma, bool, 0644);
550a7375
FB		 1669MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1670
1671void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1672{
550a7375
FB		 1673 /* called with controller lock already held */
1674
1675 if (!epnum) {
f8e9f34f 1676 if (!is_cppi_enabled(musb)) {
550a7375 1677 /* endpoint 0 */
c03da38d 1678 if (is_host_active(musb))
550a7375
FB		 1679 musb_h_ep0_irq(musb);
1680 else
1681 musb_g_ep0_irq(musb);
1682 }
550a7375
FB		 1683 } else {
1684 /* endpoints 1..15 */
1685 if (transmit) {
c03da38d 1686 if (is_host_active(musb))
a04d46d0
FB		 1687 musb_host_tx(musb, epnum);
1688 else
1689 musb_g_tx(musb, epnum);
550a7375
FB		 1690 } else {
1691 /* receive */
c03da38d 1692 if (is_host_active(musb))
a04d46d0
FB		 1693 musb_host_rx(musb, epnum);
1694 else
1695 musb_g_rx(musb, epnum);
550a7375
FB		 1696 }
1697 }
1698}
9a35f876 1699EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1700
1701#else
1702#define use_dma 0
1703#endif
1704
8055555f
TL		 1705static void (*musb_phy_callback)(enum musb_vbus_id_status status);
1706
1707/*
1708 * musb_mailbox - optional phy notifier function
1709 * @status phy state change
1710 *
1711 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1712 * disabled at the point the phy_callback is registered or unregistered.
1713 */
1714void musb_mailbox(enum musb_vbus_id_status status)
1715{
1716 if (musb_phy_callback)
1717 musb_phy_callback(status);
1718
1719};
1720EXPORT_SYMBOL_GPL(musb_mailbox);
1721
550a7375
FB		 1722/*-------------------------------------------------------------------------*/
1723
550a7375
FB		 1724static ssize_t
1725musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1726{
1727 struct musb *musb = dev_to_musb(dev);
1728 unsigned long flags;
1729 int ret = -EINVAL;
1730
1731 spin_lock_irqsave(&musb->lock, flags);
e47d9254 1732 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 1733 spin_unlock_irqrestore(&musb->lock, flags);
1734
1735 return ret;
1736}
1737
1738static ssize_t
1739musb_mode_store(struct device *dev, struct device_attribute *attr,
1740 const char *buf, size_t n)
1741{
1742 struct musb *musb = dev_to_musb(dev);
1743 unsigned long flags;
96a274d1 1744 int status;
550a7375
FB		 1745
1746 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1747 if (sysfs_streq(buf, "host"))
1748 status = musb_platform_set_mode(musb, MUSB_HOST);
1749 else if (sysfs_streq(buf, "peripheral"))
1750 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1751 else if (sysfs_streq(buf, "otg"))
1752 status = musb_platform_set_mode(musb, MUSB_OTG);
1753 else
1754 status = -EINVAL;
550a7375
FB		 1755 spin_unlock_irqrestore(&musb->lock, flags);
1756
96a274d1 1757 return (status == 0) ? n : status;
550a7375
FB		 1758}
1759static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1760
1761static ssize_t
1762musb_vbus_store(struct device *dev, struct device_attribute *attr,
1763 const char *buf, size_t n)
1764{
1765 struct musb *musb = dev_to_musb(dev);
1766 unsigned long flags;
1767 unsigned long val;
1768
1769 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1770 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1771 return -EINVAL;
1772 }
1773
1774 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1775 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1776 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
e47d9254 1777 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1778 musb->is_active = 0;
1779 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1780 spin_unlock_irqrestore(&musb->lock, flags);
1781
1782 return n;
1783}
1784
1785static ssize_t
1786musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1787{
1788 struct musb *musb = dev_to_musb(dev);
1789 unsigned long flags;
1790 unsigned long val;
1791 int vbus;
3bbafac8 1792 u8 devctl;
550a7375
FB		 1793
1794 spin_lock_irqsave(&musb->lock, flags);
1795 val = musb->a_wait_bcon;
1796 vbus = musb_platform_get_vbus_status(musb);
3bbafac8
RA		 1797 if (vbus < 0) {
1798 /* Use default MUSB method by means of DEVCTL register */
1799 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1800 if ((devctl & MUSB_DEVCTL_VBUS)
1801 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1802 vbus = 1;
1803 else
1804 vbus = 0;
1805 }
550a7375
FB		 1806 spin_unlock_irqrestore(&musb->lock, flags);
1807
f7f9d63e 1808 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1809 vbus ? "on" : "off", val);
1810}
1811static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1812
550a7375
FB		 1813/* Gadget drivers can't know that a host is connected so they might want
1814 * to start SRP, but users can. This allows userspace to trigger SRP.
1815 */
1816static ssize_t
1817musb_srp_store(struct device *dev, struct device_attribute *attr,
1818 const char *buf, size_t n)
1819{
1820 struct musb *musb = dev_to_musb(dev);
1821 unsigned short srp;
1822
1823 if (sscanf(buf, "%hu", &srp) != 1
1824 || (srp != 1)) {
b3b1cc3b 1825 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1826 return -EINVAL;
1827 }
1828
1829 if (srp == 1)
1830 musb_g_wakeup(musb);
1831
1832 return n;
1833}
1834static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1835
94375751
FB		 1836static struct attribute *musb_attributes[] = {
1837 &dev_attr_mode.attr,
1838 &dev_attr_vbus.attr,
94375751 1839 &dev_attr_srp.attr,
94375751
FB		 1840 NULL
1841};
1842
1843static const struct attribute_group musb_attr_group = {
1844 .attrs = musb_attributes,
1845};
1846
550a7375
FB		 1847/* Only used to provide driver mode change events */
1848static void musb_irq_work(struct work_struct *data)
1849{
1850 struct musb *musb = container_of(data, struct musb, irq_work);
550a7375 1851
e47d9254
AT		 1852 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1853 musb->xceiv_old_state = musb->xceiv->otg->state;
550a7375
FB		 1854 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1855 }
1856}
1857
83b8f5b8 1858static void musb_recover_from_babble(struct musb *musb)
ca88fc2e 1859{
b4dc38fd
FB		 1860 int ret;
1861 u8 devctl;
ca88fc2e 1862
0244336f
FB		 1863 musb_disable_interrupts(musb);
1864
83b8f5b8
FB		 1865 /*
1866 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1867 * it some slack and wait for 10us.
1868 */
1869 udelay(10);
1870
b28a6432 1871 ret = musb_platform_recover(musb);
ba7ee8bb
FB		 1872 if (ret) {
1873 musb_enable_interrupts(musb);
d871c622 1874 return;
ba7ee8bb 1875 }
ca88fc2e 1876
b4dc38fd
FB		 1877 /* drop session bit */
1878 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1879 devctl &= ~MUSB_DEVCTL_SESSION;
1880 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
ca88fc2e 1881
b4dc38fd
FB		 1882 /* tell usbcore about it */
1883 musb_root_disconnect(musb);
ca88fc2e
DM		 1884
1885 /*
d871c622
GC		 1886 * When a babble condition occurs, the musb controller
1887 * removes the session bit and the endpoint config is lost.
ca88fc2e
DM		 1888 */
1889 if (musb->dyn_fifo)
b4dc38fd 1890 ret = ep_config_from_table(musb);
ca88fc2e 1891 else
b4dc38fd 1892 ret = ep_config_from_hw(musb);
ca88fc2e 1893
b4dc38fd
FB		 1894 /* restart session */
1895 if (ret == 0)
ca88fc2e
DM		 1896 musb_start(musb);
1897}
1898
550a7375
FB		 1899/* --------------------------------------------------------------------------
1900 * Init support
1901 */
1902
41ac7b3a 1903static struct musb *allocate_instance(struct device *dev,
ead22caf 1904 const struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1905{
1906 struct musb *musb;
1907 struct musb_hw_ep *ep;
1908 int epnum;
74c2e936 1909 int ret;
550a7375 1910
74c2e936
DM		 1911 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1912 if (!musb)
550a7375 1913 return NULL;
550a7375 1914
550a7375
FB		 1915 INIT_LIST_HEAD(&musb->control);
1916 INIT_LIST_HEAD(&musb->in_bulk);
1917 INIT_LIST_HEAD(&musb->out_bulk);
1918
550a7375 1919 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 1920 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
550a7375
FB		 1921 musb->mregs = mbase;
1922 musb->ctrl_base = mbase;
1923 musb->nIrq = -ENODEV;
ca6d1b13 1924 musb->config = config;
02582b92 1925 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 1926 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 1927 epnum < musb->config->num_eps;
550a7375 1928 epnum++, ep++) {
550a7375
FB		 1929 ep->musb = musb;
1930 ep->epnum = epnum;
1931 }
1932
1933 musb->controller = dev;
743411b3 1934
74c2e936
DM		 1935 ret = musb_host_alloc(musb);
1936 if (ret < 0)
1937 goto err_free;
1938
1939 dev_set_drvdata(dev, musb);
1940
550a7375 1941 return musb;
74c2e936
DM		 1942
1943err_free:
1944 return NULL;
550a7375
FB		 1945}
1946
1947static void musb_free(struct musb *musb)
1948{
1949 /* this has multiple entry modes. it handles fault cleanup after
1950 * probe(), where things may be partially set up, as well as rmmod
1951 * cleanup after everything's been de-activated.
1952 */
1953
1954#ifdef CONFIG_SYSFS
94375751 1955 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
550a7375
FB		 1956#endif
1957
97a39896
AKG		 1958 if (musb->nIrq >= 0) {
1959 if (musb->irq_wake)
1960 disable_irq_wake(musb->nIrq);
550a7375
FB		 1961 free_irq(musb->nIrq, musb);
1962 }
550a7375 1963
74c2e936 1964 musb_host_free(musb);
550a7375
FB		 1965}
1966
8ed1fb79
DM		 1967static void musb_deassert_reset(struct work_struct *work)
1968{
1969 struct musb *musb;
1970 unsigned long flags;
1971
1972 musb = container_of(work, struct musb, deassert_reset_work.work);
1973
1974 spin_lock_irqsave(&musb->lock, flags);
1975
1976 if (musb->port1_status & USB_PORT_STAT_RESET)
1977 musb_port_reset(musb, false);
1978
1979 spin_unlock_irqrestore(&musb->lock, flags);
1980}
1981
550a7375
FB		 1982/*
1983 * Perform generic per-controller initialization.
1984 *
28dd924a
SS		 1985 * @dev: the controller (already clocked, etc)
1986 * @nIrq: IRQ number
1987 * @ctrl: virtual address of controller registers,
550a7375
FB		 1988 * not yet corrected for platform-specific offsets
1989 */
41ac7b3a 1990static int
550a7375
FB		 1991musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1992{
1993 int status;
1994 struct musb *musb;
c1a7d67c 1995 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
550a7375
FB		 1996
1997 /* The driver might handle more features than the board; OK.
1998 * Fail when the board needs a feature that's not enabled.
1999 */
2000 if (!plat) {
2001 dev_dbg(dev, "no platform_data?\n");
34e2beb2
SS		 2002 status = -ENODEV;
2003 goto fail0;
550a7375 2004 }
34e2beb2 2005
550a7375 2006 /* allocate */
ca6d1b13 2007 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 2008 if (!musb) {
2009 status = -ENOMEM;
2010 goto fail0;
2011 }
550a7375
FB		 2012
2013 spin_lock_init(&musb->lock);
550a7375 2014 musb->board_set_power = plat->set_power;
550a7375 2015 musb->min_power = plat->min_power;
f7ec9437 2016 musb->ops = plat->platform_ops;
9ad96e69 2017 musb->port_mode = plat->mode;
550a7375 2018
1b40fc57
TL		 2019 /*
2020 * Initialize the default IO functions. At least omap2430 needs
2021 * these early. We initialize the platform specific IO functions
2022 * later on.
2023 */
2024 musb_readb = musb_default_readb;
2025 musb_writeb = musb_default_writeb;
2026 musb_readw = musb_default_readw;
2027 musb_writew = musb_default_writew;
2028 musb_readl = musb_default_readl;
2029 musb_writel = musb_default_writel;
2030
7e1704dc
TL		 2031 /*
2032 * We need musb_read/write functions initialized for PM.
2033 * Note that at least 2430 glue needs autosuspend delay
2034 * somewhere above 300 ms for the hardware to idle properly
2035 * after disconnecting the cable in host mode. Let's use
2036 * 500 ms for some margin.
2037 */
3e43a072 2038 pm_runtime_use_autosuspend(musb->controller);
7e1704dc 2039 pm_runtime_set_autosuspend_delay(musb->controller, 500);
3e43a072
FB		 2040 pm_runtime_enable(musb->controller);
2041
84e250ff 2042 /* The musb_platform_init() call:
baef653a
PDS		 2043 * - adjusts musb->mregs
2044 * - sets the musb->isr
5ae477b0 2045 * - may initialize an integrated transceiver
721002ec 2046 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 2047 * - stops powering VBUS
84e250ff 2048 *
7c9d440e 2049 * There are various transceiver configurations. Blackfin,
84e250ff
DB		 2050 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2051 * external/discrete ones in various flavors (twl4030 family,
2052 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375 2053 */
ea65df57 2054 status = musb_platform_init(musb);
550a7375 2055 if (status < 0)
03491761 2056 goto fail1;
34e2beb2 2057
550a7375
FB		 2058 if (!musb->isr) {
2059 status = -ENODEV;
c04352a5 2060 goto fail2;
550a7375
FB		 2061 }
2062
1b40fc57
TL		 2063 if (musb->ops->quirks)
2064 musb->io.quirks = musb->ops->quirks;
2065
da96cfc1 2066 /* Most devices use indexed offset or flat offset */
d026e9c7
TL		 2067 if (musb->io.quirks & MUSB_INDEXED_EP) {
2068 musb->io.ep_offset = musb_indexed_ep_offset;
2069 musb->io.ep_select = musb_indexed_ep_select;
2070 } else {
2071 musb->io.ep_offset = musb_flat_ep_offset;
2072 musb->io.ep_select = musb_flat_ep_select;
2073 }
47a82730
HG		 2074 /* And override them with platform specific ops if specified. */
2075 if (musb->ops->ep_offset)
2076 musb->io.ep_offset = musb->ops->ep_offset;
2077 if (musb->ops->ep_select)
2078 musb->io.ep_select = musb->ops->ep_select;
d026e9c7 2079
da96cfc1
BH		 2080 /* At least tusb6010 has its own offsets */
2081 if (musb->ops->ep_offset)
2082 musb->io.ep_offset = musb->ops->ep_offset;
2083 if (musb->ops->ep_select)
2084 musb->io.ep_select = musb->ops->ep_select;
2085
8a77f05a
TL		 2086 if (musb->ops->fifo_mode)
2087 fifo_mode = musb->ops->fifo_mode;
2088 else
2089 fifo_mode = 4;
2090
1b40fc57
TL		 2091 if (musb->ops->fifo_offset)
2092 musb->io.fifo_offset = musb->ops->fifo_offset;
2093 else
2094 musb->io.fifo_offset = musb_default_fifo_offset;
2095
6cc2af6d
HG		 2096 if (musb->ops->busctl_offset)
2097 musb->io.busctl_offset = musb->ops->busctl_offset;
2098 else
2099 musb->io.busctl_offset = musb_default_busctl_offset;
2100
1b40fc57
TL		 2101 if (musb->ops->readb)
2102 musb_readb = musb->ops->readb;
2103 if (musb->ops->writeb)
2104 musb_writeb = musb->ops->writeb;
2105 if (musb->ops->readw)
2106 musb_readw = musb->ops->readw;
2107 if (musb->ops->writew)
2108 musb_writew = musb->ops->writew;
2109 if (musb->ops->readl)
2110 musb_readl = musb->ops->readl;
2111 if (musb->ops->writel)
2112 musb_writel = musb->ops->writel;
2113
7f6283ed
TL		 2114#ifndef CONFIG_MUSB_PIO_ONLY
2115 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2116 dev_err(dev, "DMA controller not set\n");
7d32cdef 2117 status = -ENODEV;
7f6283ed
TL		 2118 goto fail2;
2119 }
2120 musb_dma_controller_create = musb->ops->dma_init;
2121 musb_dma_controller_destroy = musb->ops->dma_exit;
2122#endif
2123
1b40fc57
TL		 2124 if (musb->ops->read_fifo)
2125 musb->io.read_fifo = musb->ops->read_fifo;
2126 else
2127 musb->io.read_fifo = musb_default_read_fifo;
2128
2129 if (musb->ops->write_fifo)
2130 musb->io.write_fifo = musb->ops->write_fifo;
2131 else
2132 musb->io.write_fifo = musb_default_write_fifo;
2133
ffb865b1 2134 if (!musb->xceiv->io_ops) {
bf070bc1 2135 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 2136 musb->xceiv->io_priv = musb->mregs;
2137 musb->xceiv->io_ops = &musb_ulpi_access;
2138 }
2139
8055555f
TL		 2140 if (musb->ops->phy_callback)
2141 musb_phy_callback = musb->ops->phy_callback;
2142
c04352a5
GI		 2143 pm_runtime_get_sync(musb->controller);
2144
39cee200
UKK		 2145 status = usb_phy_init(musb->xceiv);
2146 if (status < 0)
2147 goto err_usb_phy_init;
2148
48054147 2149 if (use_dma && dev->dma_mask) {
7f6283ed
TL		 2150 musb->dma_controller =
2151 musb_dma_controller_create(musb, musb->mregs);
48054147
SAS		 2152 if (IS_ERR(musb->dma_controller)) {
2153 status = PTR_ERR(musb->dma_controller);
2154 goto fail2_5;
2155 }
2156 }
550a7375
FB		 2157
2158 /* be sure interrupts are disabled before connecting ISR */
2159 musb_platform_disable(musb);
2160 musb_generic_disable(musb);
2161
66fadea5
SAS		 2162 /* Init IRQ workqueue before request_irq */
2163 INIT_WORK(&musb->irq_work, musb_irq_work);
8ed1fb79
DM		 2164 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2165 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
66fadea5 2166
550a7375 2167 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 2168 status = musb_core_init(plat->config->multipoint
550a7375
FB		 2169 ? MUSB_CONTROLLER_MHDRC
2170 : MUSB_CONTROLLER_HDRC, musb);
2171 if (status < 0)
34e2beb2 2172 goto fail3;
550a7375 2173
f7f9d63e 2174 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
f7f9d63e 2175
550a7375 2176 /* attach to the IRQ */
427c4f33 2177 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
550a7375
FB		 2178 dev_err(dev, "request_irq %d failed!\n", nIrq);
2179 status = -ENODEV;
34e2beb2 2180 goto fail3;
550a7375
FB		 2181 }
2182 musb->nIrq = nIrq;
032ec49f 2183 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 2184 if (enable_irq_wake(nIrq) == 0) {
2185 musb->irq_wake = 1;
550a7375 2186 device_init_wakeup(dev, 1);
c48a5155
FB		 2187 } else {
2188 musb->irq_wake = 0;
2189 }
550a7375 2190
032ec49f
FB		 2191 /* program PHY to use external vBus if required */
2192 if (plat->extvbus) {
2193 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2194 busctl |= MUSB_ULPI_USE_EXTVBUS;
2195 musb_write_ulpi_buscontrol(musb->mregs, busctl);
550a7375 2196 }
550a7375 2197
e5615112
GI		 2198 if (musb->xceiv->otg->default_a) {
2199 MUSB_HST_MODE(musb);
e47d9254 2200 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
e5615112
GI		 2201 } else {
2202 MUSB_DEV_MODE(musb);
e47d9254 2203 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
e5615112 2204 }
550a7375 2205
6c5f6a6f
DM		 2206 switch (musb->port_mode) {
2207 case MUSB_PORT_MODE_HOST:
2208 status = musb_host_setup(musb, plat->power);
2df6761e
FB		 2209 if (status < 0)
2210 goto fail3;
2211 status = musb_platform_set_mode(musb, MUSB_HOST);
6c5f6a6f
DM		 2212 break;
2213 case MUSB_PORT_MODE_GADGET:
2214 status = musb_gadget_setup(musb);
2df6761e
FB		 2215 if (status < 0)
2216 goto fail3;
2217 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
6c5f6a6f
DM		 2218 break;
2219 case MUSB_PORT_MODE_DUAL_ROLE:
2220 status = musb_host_setup(musb, plat->power);
2221 if (status < 0)
2222 goto fail3;
2223 status = musb_gadget_setup(musb);
2df6761e 2224 if (status) {
0d2dd7ea 2225 musb_host_cleanup(musb);
2df6761e
FB		 2226 goto fail3;
2227 }
2228 status = musb_platform_set_mode(musb, MUSB_OTG);
6c5f6a6f
DM		 2229 break;
2230 default:
2231 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2232 break;
2233 }
550a7375 2234
461972d8 2235 if (status < 0)
34e2beb2 2236 goto fail3;
550a7375 2237
7f7f9e2a
FB		 2238 status = musb_init_debugfs(musb);
2239 if (status < 0)
b0f9da7e 2240 goto fail4;
7f7f9e2a 2241
94375751 2242 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
28c2c51c 2243 if (status)
b0f9da7e 2244 goto fail5;
550a7375 2245
c04352a5
GI		 2246 pm_runtime_put(musb->controller);
2247
4d055910
TL		 2248 /*
2249 * For why this is currently needed, see commit 3e43a0725637
2250 * ("usb: musb: core: add pm_runtime_irq_safe()")
2251 */
2252 pm_runtime_irq_safe(musb->controller);
2253
28c2c51c 2254 return 0;
550a7375 2255
b0f9da7e
FB		 2256fail5:
2257 musb_exit_debugfs(musb);
2258
34e2beb2 2259fail4:
032ec49f 2260 musb_gadget_cleanup(musb);
0d2dd7ea 2261 musb_host_cleanup(musb);
34e2beb2
SS		 2262
2263fail3:
66fadea5 2264 cancel_work_sync(&musb->irq_work);
8ed1fb79
DM		 2265 cancel_delayed_work_sync(&musb->finish_resume_work);
2266 cancel_delayed_work_sync(&musb->deassert_reset_work);
f3ce4d5b 2267 if (musb->dma_controller)
7f6283ed 2268 musb_dma_controller_destroy(musb->dma_controller);
39cee200 2269
48054147 2270fail2_5:
39cee200
UKK		 2271 usb_phy_shutdown(musb->xceiv);
2272
2273err_usb_phy_init:
c04352a5
GI		 2274 pm_runtime_put_sync(musb->controller);
2275
2276fail2:
34e2beb2
SS		 2277 if (musb->irq_wake)
2278 device_init_wakeup(dev, 0);
550a7375 2279 musb_platform_exit(musb);
28c2c51c 2280
34e2beb2 2281fail1:
681d1e87 2282 pm_runtime_disable(musb->controller);
34e2beb2
SS		 2283 dev_err(musb->controller,
2284 "musb_init_controller failed with status %d\n", status);
2285
28c2c51c
FB		 2286 musb_free(musb);
2287
34e2beb2
SS		 2288fail0:
2289
28c2c51c
FB		 2290 return status;
2291
550a7375
FB		 2292}
2293
2294/*-------------------------------------------------------------------------*/
2295
2296/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2297 * bridge to a platform device; this driver then suffices.
2298 */
41ac7b3a 2299static int musb_probe(struct platform_device *pdev)
550a7375
FB		 2300{
2301 struct device *dev = &pdev->dev;
fcf173e4 2302 int irq = platform_get_irq_byname(pdev, "mc");
550a7375
FB		 2303 struct resource *iomem;
2304 void __iomem *base;
2305
1f79b26c 2306 if (irq <= 0)
550a7375
FB		 2307 return -ENODEV;
2308
1f79b26c 2309 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b42f7f30
FB		 2310 base = devm_ioremap_resource(dev, iomem);
2311 if (IS_ERR(base))
2312 return PTR_ERR(base);
550a7375 2313
b42f7f30 2314 return musb_init_controller(dev, irq, base);
550a7375
FB		 2315}
2316
fb4e98ab 2317static int musb_remove(struct platform_device *pdev)
550a7375 2318{
8d2421e6
AKG		 2319 struct device *dev = &pdev->dev;
2320 struct musb *musb = dev_to_musb(dev);
550a7375
FB		 2321
2322 /* this gets called on rmmod.
2323 * - Host mode: host may still be active
2324 * - Peripheral mode: peripheral is deactivated (or never-activated)
2325 * - OTG mode: both roles are deactivated (or never-activated)
2326 */
7f7f9e2a 2327 musb_exit_debugfs(musb);
550a7375 2328 musb_shutdown(pdev);
8055555f 2329 musb_phy_callback = NULL;
461972d8 2330
8d1aad74 2331 if (musb->dma_controller)
7f6283ed 2332 musb_dma_controller_destroy(musb->dma_controller);
8d1aad74 2333
39cee200
UKK		 2334 usb_phy_shutdown(musb->xceiv);
2335
66fadea5 2336 cancel_work_sync(&musb->irq_work);
8ed1fb79
DM		 2337 cancel_delayed_work_sync(&musb->finish_resume_work);
2338 cancel_delayed_work_sync(&musb->deassert_reset_work);
550a7375 2339 musb_free(musb);
8d2421e6 2340 device_init_wakeup(dev, 0);
550a7375
FB		 2341 return 0;
2342}
2343
2344#ifdef CONFIG_PM
2345
3c8a5fcc 2346static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2347{
2348 int i;
2349 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2350 void __iomem *epio;
4f712e01 2351
032ec49f
FB		 2352 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2353 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2354 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
7421107b 2355 musb->context.power = musb_readb(musb_base, MUSB_POWER);
7421107b
FB		 2356 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2357 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2358 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2359
ae9b2ad2 2360 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2361 struct musb_hw_ep *hw_ep;
2362
2363 hw_ep = &musb->endpoints[i];
2364 if (!hw_ep)
2365 continue;
2366
2367 epio = hw_ep->regs;
2368 if (!epio)
2369 continue;
2370
ea737554 2371 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2372 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2373 musb_readw(epio, MUSB_TXMAXP);
7421107b 2374 musb->context.index_regs[i].txcsr =
ae9b2ad2 2375 musb_readw(epio, MUSB_TXCSR);
7421107b 2376 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2377 musb_readw(epio, MUSB_RXMAXP);
7421107b 2378 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2379 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2380
2381 if (musb->dyn_fifo) {
7421107b 2382 musb->context.index_regs[i].txfifoadd =
4f712e01 2383 musb_read_txfifoadd(musb_base);
7421107b 2384 musb->context.index_regs[i].rxfifoadd =
4f712e01 2385 musb_read_rxfifoadd(musb_base);
7421107b 2386 musb->context.index_regs[i].txfifosz =
4f712e01 2387 musb_read_txfifosz(musb_base);
7421107b 2388 musb->context.index_regs[i].rxfifosz =
4f712e01
AKG		 2389 musb_read_rxfifosz(musb_base);
2390 }
032ec49f
FB		 2391
2392 musb->context.index_regs[i].txtype =
2393 musb_readb(epio, MUSB_TXTYPE);
2394 musb->context.index_regs[i].txinterval =
2395 musb_readb(epio, MUSB_TXINTERVAL);
2396 musb->context.index_regs[i].rxtype =
2397 musb_readb(epio, MUSB_RXTYPE);
2398 musb->context.index_regs[i].rxinterval =
2399 musb_readb(epio, MUSB_RXINTERVAL);
2400
2401 musb->context.index_regs[i].txfunaddr =
6cc2af6d 2402 musb_read_txfunaddr(musb, i);
032ec49f 2403 musb->context.index_regs[i].txhubaddr =
6cc2af6d 2404 musb_read_txhubaddr(musb, i);
032ec49f 2405 musb->context.index_regs[i].txhubport =
6cc2af6d 2406 musb_read_txhubport(musb, i);
032ec49f
FB		 2407
2408 musb->context.index_regs[i].rxfunaddr =
6cc2af6d 2409 musb_read_rxfunaddr(musb, i);
032ec49f 2410 musb->context.index_regs[i].rxhubaddr =
6cc2af6d 2411 musb_read_rxhubaddr(musb, i);
032ec49f 2412 musb->context.index_regs[i].rxhubport =
6cc2af6d 2413 musb_read_rxhubport(musb, i);
4f712e01 2414 }
4f712e01
AKG		 2415}
2416
3c8a5fcc 2417static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2418{
2419 int i;
2420 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2421 void __iomem *epio;
33f8d75f 2422 u8 power;
4f712e01 2423
032ec49f
FB		 2424 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2425 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2426 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
33f8d75f
RQ		 2427
2428 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2429 power = musb_readb(musb_base, MUSB_POWER);
2430 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2431 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2432 power |= musb->context.power;
2433 musb_writeb(musb_base, MUSB_POWER, power);
2434
b18d26f6 2435 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
af5ec14d 2436 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
7421107b
FB		 2437 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2438 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2439
ae9b2ad2 2440 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2441 struct musb_hw_ep *hw_ep;
2442
2443 hw_ep = &musb->endpoints[i];
2444 if (!hw_ep)
2445 continue;
2446
2447 epio = hw_ep->regs;
2448 if (!epio)
2449 continue;
2450
ea737554 2451 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2452 musb_writew(epio, MUSB_TXMAXP,
7421107b 2453 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2454 musb_writew(epio, MUSB_TXCSR,
7421107b 2455 musb->context.index_regs[i].txcsr);
ae9b2ad2 2456 musb_writew(epio, MUSB_RXMAXP,
7421107b 2457 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2458 musb_writew(epio, MUSB_RXCSR,
7421107b 2459 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2460
2461 if (musb->dyn_fifo) {
2462 musb_write_txfifosz(musb_base,
7421107b 2463 musb->context.index_regs[i].txfifosz);
4f712e01 2464 musb_write_rxfifosz(musb_base,
7421107b 2465 musb->context.index_regs[i].rxfifosz);
4f712e01 2466 musb_write_txfifoadd(musb_base,
7421107b 2467 musb->context.index_regs[i].txfifoadd);
4f712e01 2468 musb_write_rxfifoadd(musb_base,
7421107b 2469 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2470 }
2471
032ec49f 2472 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2473 musb->context.index_regs[i].txtype);
032ec49f 2474 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2475 musb->context.index_regs[i].txinterval);
032ec49f 2476 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2477 musb->context.index_regs[i].rxtype);
032ec49f 2478 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2479
032ec49f 2480 musb->context.index_regs[i].rxinterval);
6cc2af6d 2481 musb_write_txfunaddr(musb, i,
7421107b 2482 musb->context.index_regs[i].txfunaddr);
6cc2af6d 2483 musb_write_txhubaddr(musb, i,
7421107b 2484 musb->context.index_regs[i].txhubaddr);
6cc2af6d 2485 musb_write_txhubport(musb, i,
7421107b 2486 musb->context.index_regs[i].txhubport);
4f712e01 2487
6cc2af6d 2488 musb_write_rxfunaddr(musb, i,
7421107b 2489 musb->context.index_regs[i].rxfunaddr);
6cc2af6d 2490 musb_write_rxhubaddr(musb, i,
7421107b 2491 musb->context.index_regs[i].rxhubaddr);
6cc2af6d 2492 musb_write_rxhubport(musb, i,
7421107b 2493 musb->context.index_regs[i].rxhubport);
4f712e01 2494 }
3c5fec75 2495 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2496}
2497
48fea965 2498static int musb_suspend(struct device *dev)
550a7375 2499{
8220796d 2500 struct musb *musb = dev_to_musb(dev);
550a7375 2501 unsigned long flags;
550a7375 2502
6fc6f4b8
PH		 2503 musb_platform_disable(musb);
2504 musb_generic_disable(musb);
2505
550a7375
FB		 2506 spin_lock_irqsave(&musb->lock, flags);
2507
2508 if (is_peripheral_active(musb)) {
2509 /* FIXME force disconnect unless we know USB will wake
2510 * the system up quickly enough to respond ...
2511 */
2512 } else if (is_host_active(musb)) {
2513 /* we know all the children are suspended; sometimes
2514 * they will even be wakeup-enabled.
2515 */
2516 }
2517
c338412b
DM		 2518 musb_save_context(musb);
2519
550a7375
FB		 2520 spin_unlock_irqrestore(&musb->lock, flags);
2521 return 0;
2522}
2523
3e87d9a3 2524static int musb_resume(struct device *dev)
550a7375 2525{
c338412b 2526 struct musb *musb = dev_to_musb(dev);
b87fd2f7
SAS		 2527 u8 devctl;
2528 u8 mask;
c338412b
DM		 2529
2530 /*
2531 * For static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2532 * unless for some reason the whole soc powered down or the USB
2533 * module got reset through the PSC (vs just being disabled).
c338412b
DM		 2534 *
2535 * For the DSPS glue layer though, a full register restore has to
2536 * be done. As it shouldn't harm other platforms, we do it
2537 * unconditionally.
550a7375 2538 */
c338412b
DM		 2539
2540 musb_restore_context(musb);
2541
b87fd2f7
SAS		 2542 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2543 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2544 if ((devctl & mask) != (musb->context.devctl & mask))
2545 musb->port1_status = 0;
baadd52f
SAS		 2546 if (musb->need_finish_resume) {
2547 musb->need_finish_resume = 0;
2548 schedule_delayed_work(&musb->finish_resume_work,
309be239 2549 msecs_to_jiffies(USB_RESUME_TIMEOUT));
baadd52f 2550 }
a1fc1920
SAS		 2551
2552 /*
2553 * The USB HUB code expects the device to be in RPM_ACTIVE once it came
2554 * out of suspend
2555 */
2556 pm_runtime_disable(dev);
2557 pm_runtime_set_active(dev);
2558 pm_runtime_enable(dev);
6fc6f4b8
PH		 2559
2560 musb_start(musb);
2561
550a7375
FB		 2562 return 0;
2563}
2564
7acc6197
HH		 2565static int musb_runtime_suspend(struct device *dev)
2566{
2567 struct musb *musb = dev_to_musb(dev);
2568
2569 musb_save_context(musb);
2570
2571 return 0;
2572}
2573
2574static int musb_runtime_resume(struct device *dev)
2575{
2576 struct musb *musb = dev_to_musb(dev);
2577 static int first = 1;
2578
2579 /*
2580 * When pm_runtime_get_sync called for the first time in driver
2581 * init, some of the structure is still not initialized which is
2582 * used in restore function. But clock needs to be
2583 * enabled before any register access, so
2584 * pm_runtime_get_sync has to be called.
2585 * Also context restore without save does not make
2586 * any sense
2587 */
2588 if (!first)
2589 musb_restore_context(musb);
2590 first = 0;
2591
9298b4aa
BL		 2592 if (musb->need_finish_resume) {
2593 musb->need_finish_resume = 0;
2594 schedule_delayed_work(&musb->finish_resume_work,
309be239 2595 msecs_to_jiffies(USB_RESUME_TIMEOUT));
9298b4aa
BL		 2596 }
2597
7acc6197
HH		 2598 return 0;
2599}
2600
47145210 2601static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965 2602 .suspend = musb_suspend,
3e87d9a3 2603 .resume = musb_resume,
7acc6197
HH		 2604 .runtime_suspend = musb_runtime_suspend,
2605 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2606};
2607
2608#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2609#else
48fea965 2610#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2611#endif
2612
2613static struct platform_driver musb_driver = {
2614 .driver = {
2615 .name = (char *)musb_driver_name,
2616 .bus = &platform_bus_type,
48fea965 2617 .pm = MUSB_DEV_PM_OPS,
550a7375 2618 },
e9e8c85e 2619 .probe = musb_probe,
7690417d 2620 .remove = musb_remove,
550a7375 2621 .shutdown = musb_shutdown,
550a7375
FB		 2622};
2623
89f836a8 2624module_platform_driver(musb_driver);
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