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UBUNTU: Ubuntu-5.4.0-117.132
[mirror_ubuntu-focal-kernel.git] / drivers / usb / musb / musb_core.c
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5fd54ace 1// SPDX-License-Identifier: GPL-2.0
550a7375
FB		 2/*
3 * MUSB OTG driver core code
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
550a7375
FB		 8 */
9
10/*
11 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
12 *
13 * This consists of a Host Controller Driver (HCD) and a peripheral
14 * controller driver implementing the "Gadget" API; OTG support is
15 * in the works. These are normal Linux-USB controller drivers which
16 * use IRQs and have no dedicated thread.
17 *
18 * This version of the driver has only been used with products from
19 * Texas Instruments. Those products integrate the Inventra logic
20 * with other DMA, IRQ, and bus modules, as well as other logic that
21 * needs to be reflected in this driver.
22 *
23 *
24 * NOTE: the original Mentor code here was pretty much a collection
25 * of mechanisms that don't seem to have been fully integrated/working
26 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
27 * Key open issues include:
28 *
29 * - Lack of host-side transaction scheduling, for all transfer types.
30 * The hardware doesn't do it; instead, software must.
31 *
32 * This is not an issue for OTG devices that don't support external
33 * hubs, but for more "normal" USB hosts it's a user issue that the
34 * "multipoint" support doesn't scale in the expected ways. That
35 * includes DaVinci EVM in a common non-OTG mode.
36 *
37 * * Control and bulk use dedicated endpoints, and there's as
38 * yet no mechanism to either (a) reclaim the hardware when
39 * peripherals are NAKing, which gets complicated with bulk
40 * endpoints, or (b) use more than a single bulk endpoint in
41 * each direction.
42 *
43 * RESULT: one device may be perceived as blocking another one.
44 *
45 * * Interrupt and isochronous will dynamically allocate endpoint
46 * hardware, but (a) there's no record keeping for bandwidth;
47 * (b) in the common case that few endpoints are available, there
48 * is no mechanism to reuse endpoints to talk to multiple devices.
49 *
50 * RESULT: At one extreme, bandwidth can be overcommitted in
51 * some hardware configurations, no faults will be reported.
52 * At the other extreme, the bandwidth capabilities which do
53 * exist tend to be severely undercommitted. You can't yet hook
54 * up both a keyboard and a mouse to an external USB hub.
55 */
56
57/*
58 * This gets many kinds of configuration information:
59 * - Kconfig for everything user-configurable
550a7375 60 * - platform_device for addressing, irq, and platform_data
5ae477b0 61 * - platform_data is mostly for board-specific information
c767c1c6 62 * (plus recentrly, SOC or family details)
550a7375
FB		 63 *
64 * Most of the conditional compilation will (someday) vanish.
65 */
66
67#include <linux/module.h>
68#include <linux/kernel.h>
69#include <linux/sched.h>
70#include <linux/slab.h>
550a7375
FB		 71#include <linux/list.h>
72#include <linux/kobject.h>
9303961f 73#include <linux/prefetch.h>
550a7375
FB		 74#include <linux/platform_device.h>
75#include <linux/io.h>
8d2421e6 76#include <linux/dma-mapping.h>
309be239 77#include <linux/usb.h>
830fc64c 78#include <linux/usb/of.h>
550a7375 79
550a7375 80#include "musb_core.h"
c74173fd 81#include "musb_trace.h"
550a7375 82
f7f9d63e 83#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
550a7375
FB		 84
85
550a7375
FB		 86#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
87#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
88
e8164f64 89#define MUSB_VERSION "6.0"
550a7375
FB		 90
91#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
92
05ac10dd 93#define MUSB_DRIVER_NAME "musb-hdrc"
550a7375
FB		 94const char musb_driver_name[] = MUSB_DRIVER_NAME;
95
96MODULE_DESCRIPTION(DRIVER_INFO);
97MODULE_AUTHOR(DRIVER_AUTHOR);
98MODULE_LICENSE("GPL");
99MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
100
101
102/*-------------------------------------------------------------------------*/
103
104static inline struct musb *dev_to_musb(struct device *dev)
105{
550a7375 106 return dev_get_drvdata(dev);
550a7375
FB		 107}
108
830fc64c
PK		 109enum musb_mode musb_get_mode(struct device *dev)
110{
111 enum usb_dr_mode mode;
112
113 mode = usb_get_dr_mode(dev);
114 switch (mode) {
115 case USB_DR_MODE_HOST:
116 return MUSB_HOST;
117 case USB_DR_MODE_PERIPHERAL:
118 return MUSB_PERIPHERAL;
119 case USB_DR_MODE_OTG:
120 case USB_DR_MODE_UNKNOWN:
121 default:
122 return MUSB_OTG;
123 }
124}
125EXPORT_SYMBOL_GPL(musb_get_mode);
126
550a7375
FB		 127/*-------------------------------------------------------------------------*/
128
705e63d2 129static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
ffb865b1 130{
b96d3b08 131 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 132 int i = 0;
133 u8 r;
134 u8 power;
bf070bc1
GI		 135 int ret;
136
137 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 138
139 /* Make sure the transceiver is not in low power mode */
140 power = musb_readb(addr, MUSB_POWER);
141 power &= ~MUSB_POWER_SUSPENDM;
142 musb_writeb(addr, MUSB_POWER, power);
143
144 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
145 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
146 */
147
705e63d2 148 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
ffb865b1
HK		 149 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
150 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
151
152 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
153 & MUSB_ULPI_REG_CMPLT)) {
154 i++;
bf070bc1
GI		 155 if (i == 10000) {
156 ret = -ETIMEDOUT;
157 goto out;
158 }
ffb865b1
HK		 159
160 }
161 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
162 r &= ~MUSB_ULPI_REG_CMPLT;
163 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
164
bf070bc1
GI		 165 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
166
167out:
168 pm_runtime_put(phy->io_dev);
169
170 return ret;
ffb865b1
HK		 171}
172
705e63d2 173static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
ffb865b1 174{
b96d3b08 175 void __iomem *addr = phy->io_priv;
ffb865b1
HK		 176 int i = 0;
177 u8 r = 0;
178 u8 power;
bf070bc1
GI		 179 int ret = 0;
180
181 pm_runtime_get_sync(phy->io_dev);
ffb865b1
HK		 182
183 /* Make sure the transceiver is not in low power mode */
184 power = musb_readb(addr, MUSB_POWER);
185 power &= ~MUSB_POWER_SUSPENDM;
186 musb_writeb(addr, MUSB_POWER, power);
187
705e63d2
UKK		 188 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
189 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
ffb865b1
HK		 190 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
191
192 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
193 & MUSB_ULPI_REG_CMPLT)) {
194 i++;
bf070bc1
GI		 195 if (i == 10000) {
196 ret = -ETIMEDOUT;
197 goto out;
198 }
ffb865b1
HK		 199 }
200
201 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
202 r &= ~MUSB_ULPI_REG_CMPLT;
203 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
204
bf070bc1
GI		 205out:
206 pm_runtime_put(phy->io_dev);
207
208 return ret;
ffb865b1 209}
ffb865b1 210
b96d3b08 211static struct usb_phy_io_ops musb_ulpi_access = {
ffb865b1
HK		 212 .read = musb_ulpi_read,
213 .write = musb_ulpi_write,
214};
215
216/*-------------------------------------------------------------------------*/
217
1b40fc57
TL		 218static u32 musb_default_fifo_offset(u8 epnum)
219{
220 return 0x20 + (epnum * 4);
221}
222
d026e9c7
TL		 223/* "flat" mapping: each endpoint has its own i/o address */
224static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
225{
226}
227
228static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
229{
230 return 0x100 + (0x10 * epnum) + offset;
231}
232
233/* "indexed" mapping: INDEX register controls register bank select */
234static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
235{
236 musb_writeb(mbase, MUSB_INDEX, epnum);
237}
238
239static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
240{
241 return 0x10 + offset;
242}
243
6cc2af6d
HG		 244static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
245{
246 return 0x80 + (0x08 * epnum) + offset;
247}
248
1b40fc57
TL		 249static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
250{
c74173fd
BL		 251 u8 data = __raw_readb(addr + offset);
252
253 trace_musb_readb(__builtin_return_address(0), addr, offset, data);
254 return data;
1b40fc57
TL		 255}
256
257static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
258{
c74173fd 259 trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 260 __raw_writeb(data, addr + offset);
261}
262
263static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
264{
c74173fd
BL		 265 u16 data = __raw_readw(addr + offset);
266
267 trace_musb_readw(__builtin_return_address(0), addr, offset, data);
268 return data;
1b40fc57
TL		 269}
270
271static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
272{
c74173fd 273 trace_musb_writew(__builtin_return_address(0), addr, offset, data);
1b40fc57
TL		 274 __raw_writew(data, addr + offset);
275}
276
550a7375
FB		 277/*
278 * Load an endpoint's FIFO
279 */
1b40fc57
TL		 280static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
281 const u8 *src)
550a7375 282{
5c8a86e1 283 struct musb *musb = hw_ep->musb;
550a7375
FB		 284 void __iomem *fifo = hw_ep->fifo;
285
603fe2b2
AKG		 286 if (unlikely(len == 0))
287 return;
288
550a7375
FB		 289 prefetch((u8 *)src);
290
5c8a86e1 291 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 292 'T', hw_ep->epnum, fifo, len, src);
293
294 /* we can't assume unaligned reads work */
295 if (likely((0x01 & (unsigned long) src) == 0)) {
296 u16 index = 0;
297
298 /* best case is 32bit-aligned source address */
299 if ((0x02 & (unsigned long) src) == 0) {
300 if (len >= 4) {
2bf0a8f6 301 iowrite32_rep(fifo, src + index, len >> 2);
550a7375
FB		 302 index += len & ~0x03;
303 }
304 if (len & 0x02) {
be780381 305 __raw_writew(*(u16 *)&src[index], fifo);
550a7375
FB		 306 index += 2;
307 }
308 } else {
309 if (len >= 2) {
2bf0a8f6 310 iowrite16_rep(fifo, src + index, len >> 1);
550a7375
FB		 311 index += len & ~0x01;
312 }
313 }
314 if (len & 0x01)
be780381 315 __raw_writeb(src[index], fifo);
550a7375
FB		 316 } else {
317 /* byte aligned */
2bf0a8f6 318 iowrite8_rep(fifo, src, len);
550a7375
FB		 319 }
320}
321
322/*
323 * Unload an endpoint's FIFO
324 */
1b40fc57 325static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
550a7375 326{
5c8a86e1 327 struct musb *musb = hw_ep->musb;
550a7375
FB		 328 void __iomem *fifo = hw_ep->fifo;
329
603fe2b2
AKG		 330 if (unlikely(len == 0))
331 return;
332
5c8a86e1 333 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
550a7375
FB		 334 'R', hw_ep->epnum, fifo, len, dst);
335
336 /* we can't assume unaligned writes work */
337 if (likely((0x01 & (unsigned long) dst) == 0)) {
338 u16 index = 0;
339
340 /* best case is 32bit-aligned destination address */
341 if ((0x02 & (unsigned long) dst) == 0) {
342 if (len >= 4) {
2bf0a8f6 343 ioread32_rep(fifo, dst, len >> 2);
550a7375
FB		 344 index = len & ~0x03;
345 }
346 if (len & 0x02) {
be780381 347 *(u16 *)&dst[index] = __raw_readw(fifo);
550a7375
FB		 348 index += 2;
349 }
350 } else {
351 if (len >= 2) {
2bf0a8f6 352 ioread16_rep(fifo, dst, len >> 1);
550a7375
FB		 353 index = len & ~0x01;
354 }
355 }
356 if (len & 0x01)
be780381 357 dst[index] = __raw_readb(fifo);
550a7375
FB		 358 } else {
359 /* byte aligned */
2bf0a8f6 360 ioread8_rep(fifo, dst, len);
550a7375
FB		 361 }
362}
363
1b40fc57
TL		 364/*
365 * Old style IO functions
366 */
367u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
368EXPORT_SYMBOL_GPL(musb_readb);
369
370void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
371EXPORT_SYMBOL_GPL(musb_writeb);
550a7375 372
1b40fc57
TL		 373u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
374EXPORT_SYMBOL_GPL(musb_readw);
375
376void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
377EXPORT_SYMBOL_GPL(musb_writew);
378
42e990ea
BL		 379u32 musb_readl(const void __iomem *addr, unsigned offset)
380{
381 u32 data = __raw_readl(addr + offset);
382
383 trace_musb_readl(__builtin_return_address(0), addr, offset, data);
384 return data;
385}
1b40fc57
TL		 386EXPORT_SYMBOL_GPL(musb_readl);
387
42e990ea
BL		 388void musb_writel(void __iomem *addr, unsigned offset, u32 data)
389{
390 trace_musb_writel(__builtin_return_address(0), addr, offset, data);
391 __raw_writel(data, addr + offset);
392}
1b40fc57
TL		 393EXPORT_SYMBOL_GPL(musb_writel);
394
7f6283ed
TL		 395#ifndef CONFIG_MUSB_PIO_ONLY
396struct dma_controller *
397(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
398EXPORT_SYMBOL(musb_dma_controller_create);
399
400void (*musb_dma_controller_destroy)(struct dma_controller *c);
401EXPORT_SYMBOL(musb_dma_controller_destroy);
402#endif
403
1b40fc57
TL		 404/*
405 * New style IO functions
406 */
407void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
408{
409 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
410}
411
412void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
413{
414 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
415}
550a7375
FB		 416
417/*-------------------------------------------------------------------------*/
418
419/* for high speed test mode; see USB 2.0 spec 7.1.20 */
420static const u8 musb_test_packet[53] = {
421 /* implicit SYNC then DATA0 to start */
422
423 /* JKJKJKJK x9 */
424 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
425 /* JJKKJJKK x8 */
426 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
427 /* JJJJKKKK x8 */
428 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
429 /* JJJJJJJKKKKKKK x8 */
430 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
431 /* JJJJJJJK x8 */
432 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
433 /* JKKKKKKK x10, JK */
434 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
435
436 /* implicit CRC16 then EOP to end */
437};
438
439void musb_load_testpacket(struct musb *musb)
440{
441 void __iomem *regs = musb->endpoints[0].regs;
442
443 musb_ep_select(musb->mregs, 0);
444 musb_write_fifo(musb->control_ep,
445 sizeof(musb_test_packet), musb_test_packet);
446 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
447}
448
449/*-------------------------------------------------------------------------*/
450
550a7375
FB		 451/*
452 * Handles OTG hnp timeouts, such as b_ase0_brst
453 */
05678497 454static void musb_otg_timer_func(struct timer_list *t)
550a7375 455{
05678497 456 struct musb *musb = from_timer(musb, t, otg_timer);
550a7375
FB		 457 unsigned long flags;
458
459 spin_lock_irqsave(&musb->lock, flags);
e47d9254 460 switch (musb->xceiv->otg->state) {
550a7375 461 case OTG_STATE_B_WAIT_ACON:
b99d3659
BL		 462 musb_dbg(musb,
463 "HNP: b_wait_acon timeout; back to b_peripheral");
550a7375 464 musb_g_disconnect(musb);
e47d9254 465 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 466 musb->is_active = 0;
467 break;
ab983f2a 468 case OTG_STATE_A_SUSPEND:
550a7375 469 case OTG_STATE_A_WAIT_BCON:
b99d3659 470 musb_dbg(musb, "HNP: %s timeout",
e47d9254 471 usb_otg_state_string(musb->xceiv->otg->state));
743411b3 472 musb_platform_set_vbus(musb, 0);
e47d9254 473 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
550a7375
FB		 474 break;
475 default:
b99d3659 476 musb_dbg(musb, "HNP: Unhandled mode %s",
e47d9254 477 usb_otg_state_string(musb->xceiv->otg->state));
550a7375 478 }
550a7375
FB		 479 spin_unlock_irqrestore(&musb->lock, flags);
480}
481
550a7375 482/*
f7f9d63e 483 * Stops the HNP transition. Caller must take care of locking.
550a7375
FB		 484 */
485void musb_hnp_stop(struct musb *musb)
486{
8b125df5 487 struct usb_hcd *hcd = musb->hcd;
550a7375
FB		 488 void __iomem *mbase = musb->mregs;
489 u8 reg;
490
b99d3659 491 musb_dbg(musb, "HNP: stop from %s",
e47d9254 492 usb_otg_state_string(musb->xceiv->otg->state));
ab983f2a 493
e47d9254 494 switch (musb->xceiv->otg->state) {
550a7375 495 case OTG_STATE_A_PERIPHERAL:
550a7375 496 musb_g_disconnect(musb);
b99d3659 497 musb_dbg(musb, "HNP: back to %s",
e47d9254 498 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 499 break;
500 case OTG_STATE_B_HOST:
b99d3659 501 musb_dbg(musb, "HNP: Disabling HR");
74c2e936
DM		 502 if (hcd)
503 hcd->self.is_b_host = 0;
e47d9254 504 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
550a7375
FB		 505 MUSB_DEV_MODE(musb);
506 reg = musb_readb(mbase, MUSB_POWER);
507 reg |= MUSB_POWER_SUSPENDM;
508 musb_writeb(mbase, MUSB_POWER, reg);
509 /* REVISIT: Start SESSION_REQUEST here? */
510 break;
511 default:
b99d3659 512 musb_dbg(musb, "HNP: Stopping in unknown state %s",
e47d9254 513 usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 514 }
515
516 /*
517 * When returning to A state after HNP, avoid hub_port_rebounce(),
518 * which cause occasional OPT A "Did not receive reset after connect"
519 * errors.
520 */
749da5f8 521 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
550a7375
FB		 522}
523
83b8f5b8 524static void musb_recover_from_babble(struct musb *musb);
e1eb3eb8 525
bcb8fd3a
BL		 526static void musb_handle_intr_resume(struct musb *musb, u8 devctl)
527{
528 musb_dbg(musb, "RESUME (%s)",
529 usb_otg_state_string(musb->xceiv->otg->state));
530
531 if (devctl & MUSB_DEVCTL_HM) {
532 switch (musb->xceiv->otg->state) {
533 case OTG_STATE_A_SUSPEND:
534 /* remote wakeup? */
535 musb->port1_status |=
536 (USB_PORT_STAT_C_SUSPEND << 16)
537 | MUSB_PORT_STAT_RESUME;
538 musb->rh_timer = jiffies
539 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
540 musb->xceiv->otg->state = OTG_STATE_A_HOST;
541 musb->is_active = 1;
542 musb_host_resume_root_hub(musb);
543 schedule_delayed_work(&musb->finish_resume_work,
544 msecs_to_jiffies(USB_RESUME_TIMEOUT));
545 break;
546 case OTG_STATE_B_WAIT_ACON:
547 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
548 musb->is_active = 1;
549 MUSB_DEV_MODE(musb);
550 break;
551 default:
552 WARNING("bogus %s RESUME (%s)\n",
553 "host",
554 usb_otg_state_string(musb->xceiv->otg->state));
555 }
556 } else {
557 switch (musb->xceiv->otg->state) {
558 case OTG_STATE_A_SUSPEND:
559 /* possibly DISCONNECT is upcoming */
560 musb->xceiv->otg->state = OTG_STATE_A_HOST;
561 musb_host_resume_root_hub(musb);
562 break;
563 case OTG_STATE_B_WAIT_ACON:
564 case OTG_STATE_B_PERIPHERAL:
565 /* disconnect while suspended? we may
566 * not get a disconnect irq...
567 */
568 if ((devctl & MUSB_DEVCTL_VBUS)
569 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
570 ) {
571 musb->int_usb |= MUSB_INTR_DISCONNECT;
572 musb->int_usb &= ~MUSB_INTR_SUSPEND;
573 break;
574 }
575 musb_g_resume(musb);
576 break;
577 case OTG_STATE_B_IDLE:
578 musb->int_usb &= ~MUSB_INTR_SUSPEND;
579 break;
580 default:
581 WARNING("bogus %s RESUME (%s)\n",
582 "peripheral",
583 usb_otg_state_string(musb->xceiv->otg->state));
584 }
585 }
586}
587
588/* return IRQ_HANDLED to tell the caller to return immediately */
589static irqreturn_t musb_handle_intr_sessreq(struct musb *musb, u8 devctl)
590{
591 void __iomem *mbase = musb->mregs;
592
593 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
594 && (devctl & MUSB_DEVCTL_BDEVICE)) {
595 musb_dbg(musb, "SessReq while on B state");
596 return IRQ_HANDLED;
597 }
598
599 musb_dbg(musb, "SESSION_REQUEST (%s)",
600 usb_otg_state_string(musb->xceiv->otg->state));
601
602 /* IRQ arrives from ID pin sense or (later, if VBUS power
603 * is removed) SRP. responses are time critical:
604 * - turn on VBUS (with silicon-specific mechanism)
605 * - go through A_WAIT_VRISE
606 * - ... to A_WAIT_BCON.
607 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
608 */
609 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
610 musb->ep0_stage = MUSB_EP0_START;
611 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
612 MUSB_HST_MODE(musb);
613 musb_platform_set_vbus(musb, 1);
614
615 return IRQ_NONE;
616}
617
618static void musb_handle_intr_vbuserr(struct musb *musb, u8 devctl)
619{
620 int ignore = 0;
621
622 /* During connection as an A-Device, we may see a short
623 * current spikes causing voltage drop, because of cable
624 * and peripheral capacitance combined with vbus draw.
625 * (So: less common with truly self-powered devices, where
626 * vbus doesn't act like a power supply.)
627 *
628 * Such spikes are short; usually less than ~500 usec, max
629 * of ~2 msec. That is, they're not sustained overcurrent
630 * errors, though they're reported using VBUSERROR irqs.
631 *
632 * Workarounds: (a) hardware: use self powered devices.
633 * (b) software: ignore non-repeated VBUS errors.
634 *
635 * REVISIT: do delays from lots of DEBUG_KERNEL checks
636 * make trouble here, keeping VBUS < 4.4V ?
637 */
638 switch (musb->xceiv->otg->state) {
639 case OTG_STATE_A_HOST:
640 /* recovery is dicey once we've gotten past the
641 * initial stages of enumeration, but if VBUS
642 * stayed ok at the other end of the link, and
643 * another reset is due (at least for high speed,
644 * to redo the chirp etc), it might work OK...
645 */
646 case OTG_STATE_A_WAIT_BCON:
647 case OTG_STATE_A_WAIT_VRISE:
648 if (musb->vbuserr_retry) {
649 void __iomem *mbase = musb->mregs;
650
651 musb->vbuserr_retry--;
652 ignore = 1;
653 devctl |= MUSB_DEVCTL_SESSION;
654 musb_writeb(mbase, MUSB_DEVCTL, devctl);
655 } else {
656 musb->port1_status |=
657 USB_PORT_STAT_OVERCURRENT
658 | (USB_PORT_STAT_C_OVERCURRENT << 16);
659 }
660 break;
661 default:
662 break;
663 }
664
665 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
666 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
667 usb_otg_state_string(musb->xceiv->otg->state),
668 devctl,
669 ({ char *s;
670 switch (devctl & MUSB_DEVCTL_VBUS) {
671 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
672 s = "<SessEnd"; break;
673 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
674 s = "<AValid"; break;
675 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
676 s = "<VBusValid"; break;
677 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
678 default:
679 s = "VALID"; break;
680 } s; }),
681 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
682 musb->port1_status);
683
684 /* go through A_WAIT_VFALL then start a new session */
685 if (!ignore)
686 musb_platform_set_vbus(musb, 0);
687}
688
689static void musb_handle_intr_suspend(struct musb *musb, u8 devctl)
690{
691 musb_dbg(musb, "SUSPEND (%s) devctl %02x",
692 usb_otg_state_string(musb->xceiv->otg->state), devctl);
693
694 switch (musb->xceiv->otg->state) {
695 case OTG_STATE_A_PERIPHERAL:
696 /* We also come here if the cable is removed, since
697 * this silicon doesn't report ID-no-longer-grounded.
698 *
699 * We depend on T(a_wait_bcon) to shut us down, and
700 * hope users don't do anything dicey during this
701 * undesired detour through A_WAIT_BCON.
702 */
703 musb_hnp_stop(musb);
704 musb_host_resume_root_hub(musb);
705 musb_root_disconnect(musb);
706 musb_platform_try_idle(musb, jiffies
707 + msecs_to_jiffies(musb->a_wait_bcon
708 ? : OTG_TIME_A_WAIT_BCON));
709
710 break;
711 case OTG_STATE_B_IDLE:
712 if (!musb->is_active)
713 break;
714 /* fall through */
715 case OTG_STATE_B_PERIPHERAL:
716 musb_g_suspend(musb);
717 musb->is_active = musb->g.b_hnp_enable;
718 if (musb->is_active) {
719 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
720 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
721 mod_timer(&musb->otg_timer, jiffies
722 + msecs_to_jiffies(
723 OTG_TIME_B_ASE0_BRST));
724 }
725 break;
726 case OTG_STATE_A_WAIT_BCON:
727 if (musb->a_wait_bcon != 0)
728 musb_platform_try_idle(musb, jiffies
729 + msecs_to_jiffies(musb->a_wait_bcon));
730 break;
731 case OTG_STATE_A_HOST:
732 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
733 musb->is_active = musb->hcd->self.b_hnp_enable;
734 break;
735 case OTG_STATE_B_HOST:
736 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
737 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
738 break;
739 default:
740 /* "should not happen" */
741 musb->is_active = 0;
742 break;
743 }
744}
745
746static void musb_handle_intr_connect(struct musb *musb, u8 devctl, u8 int_usb)
747{
748 struct usb_hcd *hcd = musb->hcd;
749
750 musb->is_active = 1;
751 musb->ep0_stage = MUSB_EP0_START;
752
753 musb->intrtxe = musb->epmask;
754 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
755 musb->intrrxe = musb->epmask & 0xfffe;
756 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
757 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
758 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
759 |USB_PORT_STAT_HIGH_SPEED
760 |USB_PORT_STAT_ENABLE
761 );
762 musb->port1_status |= USB_PORT_STAT_CONNECTION
763 |(USB_PORT_STAT_C_CONNECTION << 16);
764
765 /* high vs full speed is just a guess until after reset */
766 if (devctl & MUSB_DEVCTL_LSDEV)
767 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
768
769 /* indicate new connection to OTG machine */
770 switch (musb->xceiv->otg->state) {
771 case OTG_STATE_B_PERIPHERAL:
772 if (int_usb & MUSB_INTR_SUSPEND) {
773 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
774 int_usb &= ~MUSB_INTR_SUSPEND;
775 goto b_host;
776 } else
777 musb_dbg(musb, "CONNECT as b_peripheral???");
778 break;
779 case OTG_STATE_B_WAIT_ACON:
780 musb_dbg(musb, "HNP: CONNECT, now b_host");
781b_host:
782 musb->xceiv->otg->state = OTG_STATE_B_HOST;
783 if (musb->hcd)
784 musb->hcd->self.is_b_host = 1;
785 del_timer(&musb->otg_timer);
786 break;
787 default:
788 if ((devctl & MUSB_DEVCTL_VBUS)
789 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
790 musb->xceiv->otg->state = OTG_STATE_A_HOST;
791 if (hcd)
792 hcd->self.is_b_host = 0;
793 }
794 break;
795 }
796
797 musb_host_poke_root_hub(musb);
798
799 musb_dbg(musb, "CONNECT (%s) devctl %02x",
800 usb_otg_state_string(musb->xceiv->otg->state), devctl);
801}
802
803static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl)
804{
805 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
806 usb_otg_state_string(musb->xceiv->otg->state),
807 MUSB_MODE(musb), devctl);
808
809 switch (musb->xceiv->otg->state) {
810 case OTG_STATE_A_HOST:
811 case OTG_STATE_A_SUSPEND:
812 musb_host_resume_root_hub(musb);
813 musb_root_disconnect(musb);
814 if (musb->a_wait_bcon != 0)
815 musb_platform_try_idle(musb, jiffies
816 + msecs_to_jiffies(musb->a_wait_bcon));
817 break;
818 case OTG_STATE_B_HOST:
819 /* REVISIT this behaves for "real disconnect"
820 * cases; make sure the other transitions from
821 * from B_HOST act right too. The B_HOST code
822 * in hnp_stop() is currently not used...
823 */
824 musb_root_disconnect(musb);
825 if (musb->hcd)
826 musb->hcd->self.is_b_host = 0;
827 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
828 MUSB_DEV_MODE(musb);
829 musb_g_disconnect(musb);
830 break;
831 case OTG_STATE_A_PERIPHERAL:
832 musb_hnp_stop(musb);
833 musb_root_disconnect(musb);
834 /* FALLTHROUGH */
835 case OTG_STATE_B_WAIT_ACON:
836 /* FALLTHROUGH */
837 case OTG_STATE_B_PERIPHERAL:
838 case OTG_STATE_B_IDLE:
839 musb_g_disconnect(musb);
840 break;
841 default:
842 WARNING("unhandled DISCONNECT transition (%s)\n",
843 usb_otg_state_string(musb->xceiv->otg->state));
844 break;
845 }
846}
847
848/*
849 * mentor saves a bit: bus reset and babble share the same irq.
850 * only host sees babble; only peripheral sees bus reset.
851 */
852static void musb_handle_intr_reset(struct musb *musb)
853{
854 if (is_host_active(musb)) {
855 /*
856 * When BABBLE happens what we can depends on which
857 * platform MUSB is running, because some platforms
858 * implemented proprietary means for 'recovering' from
859 * Babble conditions. One such platform is AM335x. In
860 * most cases, however, the only thing we can do is
861 * drop the session.
862 */
863 dev_err(musb->controller, "Babble\n");
864 musb_recover_from_babble(musb);
865 } else {
866 musb_dbg(musb, "BUS RESET as %s",
867 usb_otg_state_string(musb->xceiv->otg->state));
868 switch (musb->xceiv->otg->state) {
869 case OTG_STATE_A_SUSPEND:
870 musb_g_reset(musb);
871 /* FALLTHROUGH */
872 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
873 /* never use invalid T(a_wait_bcon) */
874 musb_dbg(musb, "HNP: in %s, %d msec timeout",
875 usb_otg_state_string(musb->xceiv->otg->state),
876 TA_WAIT_BCON(musb));
877 mod_timer(&musb->otg_timer, jiffies
878 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
879 break;
880 case OTG_STATE_A_PERIPHERAL:
881 del_timer(&musb->otg_timer);
882 musb_g_reset(musb);
883 break;
884 case OTG_STATE_B_WAIT_ACON:
885 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
886 usb_otg_state_string(musb->xceiv->otg->state));
887 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
888 musb_g_reset(musb);
889 break;
890 case OTG_STATE_B_IDLE:
891 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
892 /* FALLTHROUGH */
893 case OTG_STATE_B_PERIPHERAL:
894 musb_g_reset(musb);
895 break;
896 default:
897 musb_dbg(musb, "Unhandled BUS RESET as %s",
898 usb_otg_state_string(musb->xceiv->otg->state));
899 }
900 }
901}
902
550a7375
FB		 903/*
904 * Interrupt Service Routine to record USB "global" interrupts.
905 * Since these do not happen often and signify things of
906 * paramount importance, it seems OK to check them individually;
907 * the order of the tests is specified in the manual
908 *
909 * @param musb instance pointer
910 * @param int_usb register contents
911 * @param devctl
912 * @param power
913 */
914
550a7375 915static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
b11e94d0 916 u8 devctl)
550a7375
FB		 917{
918 irqreturn_t handled = IRQ_NONE;
550a7375 919
b99d3659 920 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
550a7375
FB		 921
922 /* in host mode, the peripheral may issue remote wakeup.
923 * in peripheral mode, the host may resume the link.
924 * spurious RESUME irqs happen too, paired with SUSPEND.
925 */
926 if (int_usb & MUSB_INTR_RESUME) {
bcb8fd3a 927 musb_handle_intr_resume(musb, devctl);
550a7375 928 handled = IRQ_HANDLED;
550a7375
FB		 929 }
930
550a7375
FB		 931 /* see manual for the order of the tests */
932 if (int_usb & MUSB_INTR_SESSREQ) {
bcb8fd3a 933 if (musb_handle_intr_sessreq(musb, devctl))
a6038ee7 934 return IRQ_HANDLED;
550a7375
FB		 935 handled = IRQ_HANDLED;
936 }
937
938 if (int_usb & MUSB_INTR_VBUSERROR) {
bcb8fd3a 939 musb_handle_intr_vbuserr(musb, devctl);
550a7375
FB		 940 handled = IRQ_HANDLED;
941 }
942
1c25fda4 943 if (int_usb & MUSB_INTR_SUSPEND) {
bcb8fd3a 944 musb_handle_intr_suspend(musb, devctl);
1c25fda4 945 handled = IRQ_HANDLED;
1c25fda4
AM		 946 }
947
550a7375 948 if (int_usb & MUSB_INTR_CONNECT) {
bcb8fd3a 949 musb_handle_intr_connect(musb, devctl, int_usb);
550a7375 950 handled = IRQ_HANDLED;
550a7375 951 }
550a7375 952
6d349671 953 if (int_usb & MUSB_INTR_DISCONNECT) {
bcb8fd3a 954 musb_handle_intr_disconnect(musb, devctl);
1c25fda4 955 handled = IRQ_HANDLED;
1c25fda4
AM		 956 }
957
550a7375 958 if (int_usb & MUSB_INTR_RESET) {
bcb8fd3a 959 musb_handle_intr_reset(musb);
1c25fda4 960 handled = IRQ_HANDLED;
550a7375 961 }
550a7375
FB		 962
963#if 0
964/* REVISIT ... this would be for multiplexing periodic endpoints, or
965 * supporting transfer phasing to prevent exceeding ISO bandwidth
966 * limits of a given frame or microframe.
967 *
968 * It's not needed for peripheral side, which dedicates endpoints;
969 * though it _might_ use SOF irqs for other purposes.
970 *
971 * And it's not currently needed for host side, which also dedicates
972 * endpoints, relies on TX/RX interval registers, and isn't claimed
973 * to support ISO transfers yet.
974 */
975 if (int_usb & MUSB_INTR_SOF) {
976 void __iomem *mbase = musb->mregs;
977 struct musb_hw_ep *ep;
978 u8 epnum;
979 u16 frame;
980
5c8a86e1 981 dev_dbg(musb->controller, "START_OF_FRAME\n");
550a7375
FB		 982 handled = IRQ_HANDLED;
983
984 /* start any periodic Tx transfers waiting for current frame */
985 frame = musb_readw(mbase, MUSB_FRAME);
986 ep = musb->endpoints;
987 for (epnum = 1; (epnum < musb->nr_endpoints)
988 && (musb->epmask >= (1 << epnum));
989 epnum++, ep++) {
990 /*
991 * FIXME handle framecounter wraps (12 bits)
992 * eliminate duplicated StartUrb logic
993 */
994 if (ep->dwWaitFrame >= frame) {
995 ep->dwWaitFrame = 0;
996 pr_debug("SOF --> periodic TX%s on %d\n",
997 ep->tx_channel ? " DMA" : "",
998 epnum);
999 if (!ep->tx_channel)
1000 musb_h_tx_start(musb, epnum);
1001 else
1002 cppi_hostdma_start(musb, epnum);
1003 }
1004 } /* end of for loop */
1005 }
1006#endif
1007
2bff3916 1008 schedule_delayed_work(&musb->irq_work, 0);
550a7375
FB		 1009
1010 return handled;
1011}
1012
1013/*-------------------------------------------------------------------------*/
1014
e1eb3eb8 1015static void musb_disable_interrupts(struct musb *musb)
550a7375
FB		 1016{
1017 void __iomem *mbase = musb->mregs;
1018 u16 temp;
1019
1020 /* disable interrupts */
1021 musb_writeb(mbase, MUSB_INTRUSBE, 0);
b18d26f6 1022 musb->intrtxe = 0;
550a7375 1023 musb_writew(mbase, MUSB_INTRTXE, 0);
af5ec14d 1024 musb->intrrxe = 0;
550a7375
FB		 1025 musb_writew(mbase, MUSB_INTRRXE, 0);
1026
550a7375
FB		 1027 /* flush pending interrupts */
1028 temp = musb_readb(mbase, MUSB_INTRUSB);
1029 temp = musb_readw(mbase, MUSB_INTRTX);
1030 temp = musb_readw(mbase, MUSB_INTRRX);
e1eb3eb8
FB		 1031}
1032
1033static void musb_enable_interrupts(struct musb *musb)
1034{
1035 void __iomem *regs = musb->mregs;
1036
1037 /* Set INT enable registers, enable interrupts */
1038 musb->intrtxe = musb->epmask;
1039 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1040 musb->intrrxe = musb->epmask & 0xfffe;
1041 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1042 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
550a7375
FB		 1043
1044}
1045
001dd84a
SAS		 1046/*
1047 * Program the HDRC to start (enable interrupts, dma, etc.).
1048 */
1049void musb_start(struct musb *musb)
1050{
1051 void __iomem *regs = musb->mregs;
1052 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
9b753764 1053 u8 power;
001dd84a 1054
b99d3659 1055 musb_dbg(musb, "<== devctl %02x", devctl);
001dd84a 1056
e1eb3eb8 1057 musb_enable_interrupts(musb);
001dd84a
SAS		 1058 musb_writeb(regs, MUSB_TESTMODE, 0);
1059
9b753764
BL		 1060 power = MUSB_POWER_ISOUPDATE;
1061 /*
1062 * treating UNKNOWN as unspecified maximum speed, in which case
1063 * we will default to high-speed.
1064 */
1065 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1066 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1067 power |= MUSB_POWER_HSENAB;
1068 musb_writeb(regs, MUSB_POWER, power);
001dd84a
SAS		 1069
1070 musb->is_active = 0;
1071 devctl = musb_readb(regs, MUSB_DEVCTL);
1072 devctl &= ~MUSB_DEVCTL_SESSION;
1073
1074 /* session started after:
1075 * (a) ID-grounded irq, host mode;
1076 * (b) vbus present/connect IRQ, peripheral mode;
1077 * (c) peripheral initiates, using SRP
1078 */
7ad76955 1079 if (musb->port_mode != MUSB_HOST &&
40af177e 1080 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
001dd84a
SAS		 1081 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1082 musb->is_active = 1;
1083 } else {
1084 devctl |= MUSB_DEVCTL_SESSION;
1085 }
1086
1087 musb_platform_enable(musb);
1088 musb_writeb(regs, MUSB_DEVCTL, devctl);
1089}
1090
550a7375
FB		 1091/*
1092 * Make the HDRC stop (disable interrupts, etc.);
1093 * reversible by musb_start
1094 * called on gadget driver unregister
1095 * with controller locked, irqs blocked
1096 * acts as a NOP unless some role activated the hardware
1097 */
1098void musb_stop(struct musb *musb)
1099{
1100 /* stop IRQs, timers, ... */
1101 musb_platform_disable(musb);
e945953d
BL		 1102 musb_disable_interrupts(musb);
1103 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
550a7375
FB		 1104
1105 /* FIXME
1106 * - mark host and/or peripheral drivers unusable/inactive
1107 * - disable DMA (and enable it in HdrcStart)
1108 * - make sure we can musb_start() after musb_stop(); with
1109 * OTG mode, gadget driver module rmmod/modprobe cycles that
1110 * - ...
1111 */
1112 musb_platform_try_idle(musb, 0);
1113}
1114
550a7375
FB		 1115/*-------------------------------------------------------------------------*/
1116
1117/*
1118 * The silicon either has hard-wired endpoint configurations, or else
1119 * "dynamic fifo" sizing. The driver has support for both, though at this
c767c1c6
DB		 1120 * writing only the dynamic sizing is very well tested. Since we switched
1121 * away from compile-time hardware parameters, we can no longer rely on
1122 * dead code elimination to leave only the relevant one in the object file.
550a7375
FB		 1123 *
1124 * We don't currently use dynamic fifo setup capability to do anything
1125 * more than selecting one of a bunch of predefined configurations.
1126 */
8a77f05a 1127static ushort fifo_mode;
550a7375
FB		 1128
1129/* "modprobe ... fifo_mode=1" etc */
1130module_param(fifo_mode, ushort, 0);
1131MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1132
550a7375
FB		 1133/*
1134 * tables defining fifo_mode values. define more if you like.
1135 * for host side, make sure both halves of ep1 are set up.
1136 */
1137
1138/* mode 0 - fits in 2KB */
d3608b6d 1139static struct musb_fifo_cfg mode_0_cfg[] = {
550a7375
FB		 1140{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1141{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1142{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1143{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1144{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1145};
1146
1147/* mode 1 - fits in 4KB */
d3608b6d 1148static struct musb_fifo_cfg mode_1_cfg[] = {
550a7375
FB		 1149{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1150{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1151{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1152{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1153{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1154};
1155
1156/* mode 2 - fits in 4KB */
d3608b6d 1157static struct musb_fifo_cfg mode_2_cfg[] = {
550a7375
FB		 1158{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1159{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1160{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1161{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
55aad53f
BL		 1162{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, },
1163{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, },
550a7375
FB		 1164};
1165
1166/* mode 3 - fits in 4KB */
d3608b6d 1167static struct musb_fifo_cfg mode_3_cfg[] = {
550a7375
FB		 1168{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1169{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1170{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1171{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1172{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1173{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1174};
1175
1176/* mode 4 - fits in 16KB */
d3608b6d 1177static struct musb_fifo_cfg mode_4_cfg[] = {
550a7375
FB		 1178{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1179{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1180{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1181{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1182{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1183{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1184{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1185{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1186{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1187{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1188{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1189{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1190{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1191{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1192{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1193{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1194{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1195{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
a483d706
AKG		 1196{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1197{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1198{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1199{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1200{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1201{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1202{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
550a7375
FB		 1203{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1204{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1205};
1206
3b151526 1207/* mode 5 - fits in 8KB */
d3608b6d 1208static struct musb_fifo_cfg mode_5_cfg[] = {
3b151526
AKG		 1209{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1210{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1211{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1212{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1213{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1214{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1215{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1216{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1217{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1218{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1219{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1220{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1221{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1222{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1223{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1224{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1225{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1226{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1227{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1228{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1229{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1230{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1231{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1232{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1233{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1234{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1235{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1236};
550a7375
FB		 1237
1238/*
1239 * configure a fifo; for non-shared endpoints, this may be called
1240 * once for a tx fifo and once for an rx fifo.
1241 *
1242 * returns negative errno or offset for next fifo.
1243 */
41ac7b3a 1244static int
550a7375 1245fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
e6c213b2 1246 const struct musb_fifo_cfg *cfg, u16 offset)
550a7375
FB		 1247{
1248 void __iomem *mbase = musb->mregs;
1249 int size = 0;
1250 u16 maxpacket = cfg->maxpacket;
1251 u16 c_off = offset >> 3;
1252 u8 c_size;
1253
1254 /* expect hw_ep has already been zero-initialized */
1255
1256 size = ffs(max(maxpacket, (u16) 8)) - 1;
1257 maxpacket = 1 << size;
1258
1259 c_size = size - 3;
1260 if (cfg->mode == BUF_DOUBLE) {
ca6d1b13
FB		 1261 if ((offset + (maxpacket << 1)) >
1262 (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1263 return -EMSGSIZE;
1264 c_size |= MUSB_FIFOSZ_DPB;
1265 } else {
ca6d1b13 1266 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
550a7375
FB		 1267 return -EMSGSIZE;
1268 }
1269
1270 /* configure the FIFO */
1271 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1272
550a7375 1273 /* EP0 reserved endpoint for control, bidirectional;
5ae477b0 1274 * EP1 reserved for bulk, two unidirectional halves.
550a7375
FB		 1275 */
1276 if (hw_ep->epnum == 1)
1277 musb->bulk_ep = hw_ep;
1278 /* REVISIT error check: be sure ep0 can both rx and tx ... */
550a7375
FB		 1279 switch (cfg->style) {
1280 case FIFO_TX:
113ad151
BL		 1281 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1282 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
550a7375
FB		 1283 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1284 hw_ep->max_packet_sz_tx = maxpacket;
1285 break;
1286 case FIFO_RX:
113ad151
BL		 1287 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1288 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
550a7375
FB		 1289 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1290 hw_ep->max_packet_sz_rx = maxpacket;
1291 break;
1292 case FIFO_RXTX:
113ad151
BL		 1293 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1294 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
550a7375
FB		 1295 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1296 hw_ep->max_packet_sz_rx = maxpacket;
1297
113ad151
BL		 1298 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1299 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
550a7375
FB		 1300 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1301 hw_ep->max_packet_sz_tx = maxpacket;
1302
1303 hw_ep->is_shared_fifo = true;
1304 break;
1305 }
1306
1307 /* NOTE rx and tx endpoint irqs aren't managed separately,
1308 * which happens to be ok
1309 */
1310 musb->epmask |= (1 << hw_ep->epnum);
1311
1312 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1313}
1314
d3608b6d 1315static struct musb_fifo_cfg ep0_cfg = {
550a7375
FB		 1316 .style = FIFO_RXTX, .maxpacket = 64,
1317};
1318
41ac7b3a 1319static int ep_config_from_table(struct musb *musb)
550a7375 1320{
e6c213b2 1321 const struct musb_fifo_cfg *cfg;
550a7375
FB		 1322 unsigned i, n;
1323 int offset;
1324 struct musb_hw_ep *hw_ep = musb->endpoints;
1325
e6c213b2
FB		 1326 if (musb->config->fifo_cfg) {
1327 cfg = musb->config->fifo_cfg;
1328 n = musb->config->fifo_cfg_size;
1329 goto done;
1330 }
1331
550a7375
FB		 1332 switch (fifo_mode) {
1333 default:
1334 fifo_mode = 0;
1335 /* FALLTHROUGH */
1336 case 0:
1337 cfg = mode_0_cfg;
1338 n = ARRAY_SIZE(mode_0_cfg);
1339 break;
1340 case 1:
1341 cfg = mode_1_cfg;
1342 n = ARRAY_SIZE(mode_1_cfg);
1343 break;
1344 case 2:
1345 cfg = mode_2_cfg;
1346 n = ARRAY_SIZE(mode_2_cfg);
1347 break;
1348 case 3:
1349 cfg = mode_3_cfg;
1350 n = ARRAY_SIZE(mode_3_cfg);
1351 break;
1352 case 4:
1353 cfg = mode_4_cfg;
1354 n = ARRAY_SIZE(mode_4_cfg);
1355 break;
3b151526
AKG		 1356 case 5:
1357 cfg = mode_5_cfg;
1358 n = ARRAY_SIZE(mode_5_cfg);
1359 break;
550a7375
FB		 1360 }
1361
3ff4b573 1362 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
550a7375
FB		 1363
1364
e6c213b2 1365done:
550a7375
FB		 1366 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1367 /* assert(offset > 0) */
1368
1369 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
ca6d1b13 1370 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
550a7375
FB		 1371 */
1372
1373 for (i = 0; i < n; i++) {
1374 u8 epn = cfg->hw_ep_num;
1375
ca6d1b13 1376 if (epn >= musb->config->num_eps) {
550a7375
FB		 1377 pr_debug("%s: invalid ep %d\n",
1378 musb_driver_name, epn);
bb1c9ef1 1379 return -EINVAL;
550a7375
FB		 1380 }
1381 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1382 if (offset < 0) {
1383 pr_debug("%s: mem overrun, ep %d\n",
1384 musb_driver_name, epn);
f69dfa1f 1385 return offset;
550a7375
FB		 1386 }
1387 epn++;
1388 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1389 }
1390
3ff4b573 1391 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
550a7375 1392 musb_driver_name,
ca6d1b13
FB		 1393 n + 1, musb->config->num_eps * 2 - 1,
1394 offset, (1 << (musb->config->ram_bits + 2)));
550a7375 1395
550a7375
FB		 1396 if (!musb->bulk_ep) {
1397 pr_debug("%s: missing bulk\n", musb_driver_name);
1398 return -EINVAL;
1399 }
550a7375
FB		 1400
1401 return 0;
1402}
1403
1404
1405/*
1406 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1407 * @param musb the controller
1408 */
41ac7b3a 1409static int ep_config_from_hw(struct musb *musb)
550a7375 1410{
c6cf8b00 1411 u8 epnum = 0;
550a7375 1412 struct musb_hw_ep *hw_ep;
a156544b 1413 void __iomem *mbase = musb->mregs;
c6cf8b00 1414 int ret = 0;
550a7375 1415
b99d3659 1416 musb_dbg(musb, "<== static silicon ep config");
550a7375
FB		 1417
1418 /* FIXME pick up ep0 maxpacket size */
1419
ca6d1b13 1420 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
550a7375
FB		 1421 musb_ep_select(mbase, epnum);
1422 hw_ep = musb->endpoints + epnum;
1423
c6cf8b00
BW		 1424 ret = musb_read_fifosize(musb, hw_ep, epnum);
1425 if (ret < 0)
550a7375 1426 break;
550a7375
FB		 1427
1428 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1429
550a7375
FB		 1430 /* pick an RX/TX endpoint for bulk */
1431 if (hw_ep->max_packet_sz_tx < 512
1432 || hw_ep->max_packet_sz_rx < 512)
1433 continue;
1434
1435 /* REVISIT: this algorithm is lazy, we should at least
1436 * try to pick a double buffered endpoint.
1437 */
1438 if (musb->bulk_ep)
1439 continue;
1440 musb->bulk_ep = hw_ep;
550a7375
FB		 1441 }
1442
550a7375
FB		 1443 if (!musb->bulk_ep) {
1444 pr_debug("%s: missing bulk\n", musb_driver_name);
1445 return -EINVAL;
1446 }
550a7375
FB		 1447
1448 return 0;
1449}
1450
1451enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1452
1453/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1454 * configure endpoints, or take their config from silicon
1455 */
41ac7b3a 1456static int musb_core_init(u16 musb_type, struct musb *musb)
550a7375 1457{
550a7375
FB		 1458 u8 reg;
1459 char *type;
21b031fb 1460 char aInfo[90];
550a7375
FB		 1461 void __iomem *mbase = musb->mregs;
1462 int status = 0;
1463 int i;
1464
1465 /* log core options (read using indexed model) */
c6cf8b00 1466 reg = musb_read_configdata(mbase);
550a7375
FB		 1467
1468 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
51bf0d0e 1469 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
550a7375 1470 strcat(aInfo, ", dyn FIFOs");
51bf0d0e
AKG		 1471 musb->dyn_fifo = true;
1472 }
550a7375
FB		 1473 if (reg & MUSB_CONFIGDATA_MPRXE) {
1474 strcat(aInfo, ", bulk combine");
550a7375 1475 musb->bulk_combine = true;
550a7375
FB		 1476 }
1477 if (reg & MUSB_CONFIGDATA_MPTXE) {
1478 strcat(aInfo, ", bulk split");
550a7375 1479 musb->bulk_split = true;
550a7375
FB		 1480 }
1481 if (reg & MUSB_CONFIGDATA_HBRXE) {
1482 strcat(aInfo, ", HB-ISO Rx");
a483d706 1483 musb->hb_iso_rx = true;
550a7375
FB		 1484 }
1485 if (reg & MUSB_CONFIGDATA_HBTXE) {
1486 strcat(aInfo, ", HB-ISO Tx");
a483d706 1487 musb->hb_iso_tx = true;
550a7375
FB		 1488 }
1489 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1490 strcat(aInfo, ", SoftConn");
1491
3ff4b573 1492 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
550a7375 1493
550a7375
FB		 1494 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1495 musb->is_multipoint = 1;
1496 type = "M";
1497 } else {
1498 musb->is_multipoint = 0;
1499 type = "";
41386bc8
PC		 1500 if (IS_ENABLED(CONFIG_USB) &&
1501 !IS_ENABLED(CONFIG_USB_OTG_BLACKLIST_HUB)) {
1502 pr_err("%s: kernel must blacklist external hubs\n",
1503 musb_driver_name);
1504 }
550a7375
FB		 1505 }
1506
1507 /* log release info */
113ad151 1508 musb->hwvers = musb_readw(mbase, MUSB_HWVERS);
21b031fb
RV		 1509 pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1510 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1511 MUSB_HWVERS_MINOR(musb->hwvers),
1512 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
550a7375
FB		 1513
1514 /* configure ep0 */
c6cf8b00 1515 musb_configure_ep0(musb);
550a7375
FB		 1516
1517 /* discover endpoint configuration */
1518 musb->nr_endpoints = 1;
1519 musb->epmask = 1;
1520
ad517e9e
FB		 1521 if (musb->dyn_fifo)
1522 status = ep_config_from_table(musb);
1523 else
1524 status = ep_config_from_hw(musb);
550a7375
FB		 1525
1526 if (status < 0)
1527 return status;
1528
1529 /* finish init, and print endpoint config */
1530 for (i = 0; i < musb->nr_endpoints; i++) {
1531 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1532
1b40fc57 1533 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
ebf39920 1534#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
dc8fca6c 1535 if (musb->ops->quirks & MUSB_IN_TUSB) {
1b40fc57
TL		 1536 hw_ep->fifo_async = musb->async + 0x400 +
1537 musb->io.fifo_offset(i);
1538 hw_ep->fifo_sync = musb->sync + 0x400 +
1539 musb->io.fifo_offset(i);
1540 hw_ep->fifo_sync_va =
1541 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1542
1543 if (i == 0)
1544 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1545 else
1546 hw_ep->conf = mbase + 0x400 +
1547 (((i - 1) & 0xf) << 2);
1548 }
550a7375
FB		 1549#endif
1550
d026e9c7 1551 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
550a7375
FB		 1552 hw_ep->rx_reinit = 1;
1553 hw_ep->tx_reinit = 1;
550a7375
FB		 1554
1555 if (hw_ep->max_packet_sz_tx) {
b99d3659 1556 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
550a7375
FB		 1557 musb_driver_name, i,
1558 hw_ep->is_shared_fifo ? "shared" : "tx",
1559 hw_ep->tx_double_buffered
1560 ? "doublebuffer, " : "",
1561 hw_ep->max_packet_sz_tx);
1562 }
1563 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
b99d3659 1564 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
550a7375
FB		 1565 musb_driver_name, i,
1566 "rx",
1567 hw_ep->rx_double_buffered
1568 ? "doublebuffer, " : "",
1569 hw_ep->max_packet_sz_rx);
1570 }
1571 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
b99d3659 1572 musb_dbg(musb, "hw_ep %d not configured", i);
550a7375
FB		 1573 }
1574
1575 return 0;
1576}
1577
1578/*-------------------------------------------------------------------------*/
1579
550a7375
FB		 1580/*
1581 * handle all the irqs defined by the HDRC core. for now we expect: other
1582 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1583 * will be assigned, and the irq will already have been acked.
1584 *
1585 * called in irq context with spinlock held, irqs blocked
1586 */
1587irqreturn_t musb_interrupt(struct musb *musb)
1588{
1589 irqreturn_t retval = IRQ_NONE;
31a0ede0
FB		 1590 unsigned long status;
1591 unsigned long epnum;
b11e94d0 1592 u8 devctl;
31a0ede0
FB		 1593
1594 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1595 return IRQ_NONE;
550a7375
FB		 1596
1597 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
550a7375 1598
cfb9a1bc 1599 trace_musb_isr(musb);
550a7375 1600
e3c93e1a
FB		 1601 /**
1602 * According to Mentor Graphics' documentation, flowchart on page 98,
1603 * IRQ should be handled as follows:
1604 *
1605 * . Resume IRQ
1606 * . Session Request IRQ
1607 * . VBUS Error IRQ
1608 * . Suspend IRQ
1609 * . Connect IRQ
1610 * . Disconnect IRQ
1611 * . Reset/Babble IRQ
1612 * . SOF IRQ (we're not using this one)
1613 * . Endpoint 0 IRQ
1614 * . TX Endpoints
1615 * . RX Endpoints
1616 *
1617 * We will be following that flowchart in order to avoid any problems
1618 * that might arise with internal Finite State Machine.
550a7375 1619 */
e3c93e1a 1620
7d9645fd 1621 if (musb->int_usb)
31a0ede0 1622 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
550a7375 1623
550a7375 1624 if (musb->int_tx & 1) {
c03da38d 1625 if (is_host_active(musb))
550a7375
FB		 1626 retval |= musb_h_ep0_irq(musb);
1627 else
1628 retval |= musb_g_ep0_irq(musb);
31a0ede0
FB		 1629
1630 /* we have just handled endpoint 0 IRQ, clear it */
1631 musb->int_tx &= ~BIT(0);
550a7375
FB		 1632 }
1633
31a0ede0
FB		 1634 status = musb->int_tx;
1635
1636 for_each_set_bit(epnum, &status, 16) {
1637 retval = IRQ_HANDLED;
1638 if (is_host_active(musb))
1639 musb_host_tx(musb, epnum);
1640 else
1641 musb_g_tx(musb, epnum);
550a7375
FB		 1642 }
1643
31a0ede0 1644 status = musb->int_rx;
e3c93e1a 1645
31a0ede0
FB		 1646 for_each_set_bit(epnum, &status, 16) {
1647 retval = IRQ_HANDLED;
1648 if (is_host_active(musb))
1649 musb_host_rx(musb, epnum);
1650 else
1651 musb_g_rx(musb, epnum);
550a7375
FB		 1652 }
1653
550a7375
FB		 1654 return retval;
1655}
981430a1 1656EXPORT_SYMBOL_GPL(musb_interrupt);
550a7375
FB		 1657
1658#ifndef CONFIG_MUSB_PIO_ONLY
d3608b6d 1659static bool use_dma = 1;
550a7375
FB		 1660
1661/* "modprobe ... use_dma=0" etc */
51676c8d 1662module_param(use_dma, bool, 0644);
550a7375
FB		 1663MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1664
1665void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1666{
550a7375
FB		 1667 /* called with controller lock already held */
1668
1669 if (!epnum) {
f8e9f34f 1670 if (!is_cppi_enabled(musb)) {
550a7375 1671 /* endpoint 0 */
c03da38d 1672 if (is_host_active(musb))
550a7375
FB		 1673 musb_h_ep0_irq(musb);
1674 else
1675 musb_g_ep0_irq(musb);
1676 }
550a7375
FB		 1677 } else {
1678 /* endpoints 1..15 */
1679 if (transmit) {
c03da38d 1680 if (is_host_active(musb))
a04d46d0
FB		 1681 musb_host_tx(musb, epnum);
1682 else
1683 musb_g_tx(musb, epnum);
550a7375
FB		 1684 } else {
1685 /* receive */
c03da38d 1686 if (is_host_active(musb))
a04d46d0
FB		 1687 musb_host_rx(musb, epnum);
1688 else
1689 musb_g_rx(musb, epnum);
550a7375
FB		 1690 }
1691 }
1692}
9a35f876 1693EXPORT_SYMBOL_GPL(musb_dma_completion);
550a7375
FB		 1694
1695#else
1696#define use_dma 0
1697#endif
1698
12b7db2b 1699static int (*musb_phy_callback)(enum musb_vbus_id_status status);
8055555f
TL		 1700
1701/*
1702 * musb_mailbox - optional phy notifier function
1703 * @status phy state change
1704 *
1705 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1706 * disabled at the point the phy_callback is registered or unregistered.
1707 */
12b7db2b 1708int musb_mailbox(enum musb_vbus_id_status status)
8055555f
TL		 1709{
1710 if (musb_phy_callback)
12b7db2b 1711 return musb_phy_callback(status);
8055555f 1712
12b7db2b 1713 return -ENODEV;
8055555f
TL		 1714};
1715EXPORT_SYMBOL_GPL(musb_mailbox);
1716
550a7375
FB		 1717/*-------------------------------------------------------------------------*/
1718
550a7375 1719static ssize_t
ed5bd7a4 1720mode_show(struct device *dev, struct device_attribute *attr, char *buf)
550a7375
FB		 1721{
1722 struct musb *musb = dev_to_musb(dev);
1723 unsigned long flags;
82e17a09 1724 int ret;
550a7375
FB		 1725
1726 spin_lock_irqsave(&musb->lock, flags);
e47d9254 1727 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
550a7375
FB		 1728 spin_unlock_irqrestore(&musb->lock, flags);
1729
1730 return ret;
1731}
1732
1733static ssize_t
ed5bd7a4 1734mode_store(struct device *dev, struct device_attribute *attr,
550a7375
FB		 1735 const char *buf, size_t n)
1736{
1737 struct musb *musb = dev_to_musb(dev);
1738 unsigned long flags;
96a274d1 1739 int status;
550a7375
FB		 1740
1741 spin_lock_irqsave(&musb->lock, flags);
96a274d1
DB		 1742 if (sysfs_streq(buf, "host"))
1743 status = musb_platform_set_mode(musb, MUSB_HOST);
1744 else if (sysfs_streq(buf, "peripheral"))
1745 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1746 else if (sysfs_streq(buf, "otg"))
1747 status = musb_platform_set_mode(musb, MUSB_OTG);
1748 else
1749 status = -EINVAL;
550a7375
FB		 1750 spin_unlock_irqrestore(&musb->lock, flags);
1751
96a274d1 1752 return (status == 0) ? n : status;
550a7375 1753}
ed5bd7a4 1754static DEVICE_ATTR_RW(mode);
550a7375
FB		 1755
1756static ssize_t
ed5bd7a4 1757vbus_store(struct device *dev, struct device_attribute *attr,
550a7375
FB		 1758 const char *buf, size_t n)
1759{
1760 struct musb *musb = dev_to_musb(dev);
1761 unsigned long flags;
1762 unsigned long val;
1763
1764 if (sscanf(buf, "%lu", &val) < 1) {
b3b1cc3b 1765 dev_err(dev, "Invalid VBUS timeout ms value\n");
550a7375
FB		 1766 return -EINVAL;
1767 }
1768
1769 spin_lock_irqsave(&musb->lock, flags);
f7f9d63e
DB		 1770 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1771 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
e47d9254 1772 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
550a7375
FB		 1773 musb->is_active = 0;
1774 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1775 spin_unlock_irqrestore(&musb->lock, flags);
1776
1777 return n;
1778}
1779
1780static ssize_t
ed5bd7a4 1781vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
550a7375
FB		 1782{
1783 struct musb *musb = dev_to_musb(dev);
1784 unsigned long flags;
1785 unsigned long val;
1786 int vbus;
3bbafac8 1787 u8 devctl;
550a7375 1788
df6b074d 1789 pm_runtime_get_sync(dev);
550a7375
FB		 1790 spin_lock_irqsave(&musb->lock, flags);
1791 val = musb->a_wait_bcon;
1792 vbus = musb_platform_get_vbus_status(musb);
3bbafac8
RA		 1793 if (vbus < 0) {
1794 /* Use default MUSB method by means of DEVCTL register */
1795 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1796 if ((devctl & MUSB_DEVCTL_VBUS)
1797 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1798 vbus = 1;
1799 else
1800 vbus = 0;
1801 }
550a7375 1802 spin_unlock_irqrestore(&musb->lock, flags);
df6b074d 1803 pm_runtime_put_sync(dev);
550a7375 1804
f7f9d63e 1805 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
550a7375
FB		 1806 vbus ? "on" : "off", val);
1807}
ed5bd7a4 1808static DEVICE_ATTR_RW(vbus);
550a7375 1809
550a7375
FB		 1810/* Gadget drivers can't know that a host is connected so they might want
1811 * to start SRP, but users can. This allows userspace to trigger SRP.
1812 */
6e4294d0 1813static ssize_t srp_store(struct device *dev, struct device_attribute *attr,
550a7375
FB		 1814 const char *buf, size_t n)
1815{
1816 struct musb *musb = dev_to_musb(dev);
1817 unsigned short srp;
1818
1819 if (sscanf(buf, "%hu", &srp) != 1
1820 || (srp != 1)) {
b3b1cc3b 1821 dev_err(dev, "SRP: Value must be 1\n");
550a7375
FB		 1822 return -EINVAL;
1823 }
1824
1825 if (srp == 1)
1826 musb_g_wakeup(musb);
1827
1828 return n;
1829}
6e4294d0 1830static DEVICE_ATTR_WO(srp);
550a7375 1831
d3b5e319 1832static struct attribute *musb_attrs[] = {
94375751
FB		 1833 &dev_attr_mode.attr,
1834 &dev_attr_vbus.attr,
94375751 1835 &dev_attr_srp.attr,
94375751
FB		 1836 NULL
1837};
d3b5e319 1838ATTRIBUTE_GROUPS(musb);
94375751 1839
467d5c98
TL		 1840#define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
1841 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1842 MUSB_DEVCTL_SESSION)
0a8deda5
TL		 1843#define MUSB_QUIRK_B_DISCONNECT_99 (MUSB_DEVCTL_BDEVICE | \
1844 (3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1845 MUSB_DEVCTL_SESSION)
467d5c98
TL		 1846#define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1847 MUSB_DEVCTL_SESSION)
1848
1849/*
1850 * Check the musb devctl session bit to determine if we want to
1851 * allow PM runtime for the device. In general, we want to keep things
1852 * active when the session bit is set except after host disconnect.
1853 *
1854 * Only called from musb_irq_work. If this ever needs to get called
1855 * elsewhere, proper locking must be implemented for musb->session.
1856 */
1857static void musb_pm_runtime_check_session(struct musb *musb)
1858{
1859 u8 devctl, s;
1860 int error;
1861
1862 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1863
1864 /* Handle session status quirks first */
1865 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
1866 MUSB_DEVCTL_HR;
1867 switch (devctl & ~s) {
0a8deda5 1868 case MUSB_QUIRK_B_DISCONNECT_99:
2a46ade6
TL		 1869 if (musb->quirk_retries && !musb->flush_irq_work) {
1870 musb_dbg(musb, "Poll devctl in case of suspend after disconnect\n");
1871 schedule_delayed_work(&musb->irq_work,
1872 msecs_to_jiffies(1000));
1873 musb->quirk_retries--;
2a46ade6 1874 }
de6e0544 1875 break;
467d5c98 1876 case MUSB_QUIRK_B_INVALID_VBUS_91:
0c3aae9b 1877 if (musb->quirk_retries && !musb->flush_irq_work) {
2b9a8c40 1878 musb_dbg(musb,
2bff3916
TL		 1879 "Poll devctl on invalid vbus, assume no session");
1880 schedule_delayed_work(&musb->irq_work,
1881 msecs_to_jiffies(1000));
4f190e0b 1882 musb->quirk_retries--;
2b9a8c40
TL		 1883 return;
1884 }
eff0b85e 1885 /* fall through */
467d5c98 1886 case MUSB_QUIRK_A_DISCONNECT_19:
0c3aae9b 1887 if (musb->quirk_retries && !musb->flush_irq_work) {
2bff3916
TL		 1888 musb_dbg(musb,
1889 "Poll devctl on possible host mode disconnect");
1890 schedule_delayed_work(&musb->irq_work,
1891 msecs_to_jiffies(1000));
4f190e0b 1892 musb->quirk_retries--;
2bff3916
TL		 1893 return;
1894 }
467d5c98
TL		 1895 if (!musb->session)
1896 break;
1897 musb_dbg(musb, "Allow PM on possible host mode disconnect");
1898 pm_runtime_mark_last_busy(musb->controller);
1899 pm_runtime_put_autosuspend(musb->controller);
1900 musb->session = false;
1901 return;
1902 default:
1903 break;
1904 }
1905
1906 /* No need to do anything if session has not changed */
1907 s = devctl & MUSB_DEVCTL_SESSION;
1908 if (s == musb->session)
1909 return;
1910
1911 /* Block PM or allow PM? */
1912 if (s) {
1913 musb_dbg(musb, "Block PM on active session: %02x", devctl);
1914 error = pm_runtime_get_sync(musb->controller);
1915 if (error < 0)
1916 dev_err(musb->controller, "Could not enable: %i\n",
1917 error);
2bff3916 1918 musb->quirk_retries = 3;
467d5c98
TL		 1919 } else {
1920 musb_dbg(musb, "Allow PM with no session: %02x", devctl);
1921 pm_runtime_mark_last_busy(musb->controller);
1922 pm_runtime_put_autosuspend(musb->controller);
1923 }
1924
1925 musb->session = s;
1926}
1927
550a7375
FB		 1928/* Only used to provide driver mode change events */
1929static void musb_irq_work(struct work_struct *data)
1930{
2bff3916 1931 struct musb *musb = container_of(data, struct musb, irq_work.work);
3ba7b779
TL		 1932 int error;
1933
b8ad1151 1934 error = pm_runtime_resume_and_get(musb->controller);
3ba7b779
TL		 1935 if (error < 0) {
1936 dev_err(musb->controller, "Could not enable: %i\n", error);
1937
1938 return;
1939 }
550a7375 1940
467d5c98
TL		 1941 musb_pm_runtime_check_session(musb);
1942
e47d9254
AT		 1943 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1944 musb->xceiv_old_state = musb->xceiv->otg->state;
550a7375
FB		 1945 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1946 }
3ba7b779
TL		 1947
1948 pm_runtime_mark_last_busy(musb->controller);
1949 pm_runtime_put_autosuspend(musb->controller);
550a7375
FB		 1950}
1951
83b8f5b8 1952static void musb_recover_from_babble(struct musb *musb)
ca88fc2e 1953{
b4dc38fd
FB		 1954 int ret;
1955 u8 devctl;
ca88fc2e 1956
0244336f
FB		 1957 musb_disable_interrupts(musb);
1958
83b8f5b8
FB		 1959 /*
1960 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1961 * it some slack and wait for 10us.
1962 */
1963 udelay(10);
1964
b28a6432 1965 ret = musb_platform_recover(musb);
ba7ee8bb
FB		 1966 if (ret) {
1967 musb_enable_interrupts(musb);
d871c622 1968 return;
ba7ee8bb 1969 }
ca88fc2e 1970
b4dc38fd
FB		 1971 /* drop session bit */
1972 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1973 devctl &= ~MUSB_DEVCTL_SESSION;
1974 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
ca88fc2e 1975
b4dc38fd
FB		 1976 /* tell usbcore about it */
1977 musb_root_disconnect(musb);
ca88fc2e
DM		 1978
1979 /*
d871c622
GC		 1980 * When a babble condition occurs, the musb controller
1981 * removes the session bit and the endpoint config is lost.
ca88fc2e
DM		 1982 */
1983 if (musb->dyn_fifo)
b4dc38fd 1984 ret = ep_config_from_table(musb);
ca88fc2e 1985 else
b4dc38fd 1986 ret = ep_config_from_hw(musb);
ca88fc2e 1987
b4dc38fd
FB		 1988 /* restart session */
1989 if (ret == 0)
ca88fc2e
DM		 1990 musb_start(musb);
1991}
1992
550a7375
FB		 1993/* --------------------------------------------------------------------------
1994 * Init support
1995 */
1996
41ac7b3a 1997static struct musb *allocate_instance(struct device *dev,
ead22caf 1998 const struct musb_hdrc_config *config, void __iomem *mbase)
550a7375
FB		 1999{
2000 struct musb *musb;
2001 struct musb_hw_ep *ep;
2002 int epnum;
74c2e936 2003 int ret;
550a7375 2004
74c2e936
DM		 2005 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
2006 if (!musb)
550a7375 2007 return NULL;
550a7375 2008
550a7375
FB		 2009 INIT_LIST_HEAD(&musb->control);
2010 INIT_LIST_HEAD(&musb->in_bulk);
2011 INIT_LIST_HEAD(&musb->out_bulk);
ea2f35c0 2012 INIT_LIST_HEAD(&musb->pending_list);
550a7375 2013
550a7375 2014 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
f7f9d63e 2015 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
550a7375
FB		 2016 musb->mregs = mbase;
2017 musb->ctrl_base = mbase;
2018 musb->nIrq = -ENODEV;
ca6d1b13 2019 musb->config = config;
02582b92 2020 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
550a7375 2021 for (epnum = 0, ep = musb->endpoints;
ca6d1b13 2022 epnum < musb->config->num_eps;
550a7375 2023 epnum++, ep++) {
550a7375
FB		 2024 ep->musb = musb;
2025 ep->epnum = epnum;
2026 }
2027
2028 musb->controller = dev;
743411b3 2029
74c2e936
DM		 2030 ret = musb_host_alloc(musb);
2031 if (ret < 0)
2032 goto err_free;
2033
2034 dev_set_drvdata(dev, musb);
2035
550a7375 2036 return musb;
74c2e936
DM		 2037
2038err_free:
2039 return NULL;
550a7375
FB		 2040}
2041
2042static void musb_free(struct musb *musb)
2043{
2044 /* this has multiple entry modes. it handles fault cleanup after
2045 * probe(), where things may be partially set up, as well as rmmod
2046 * cleanup after everything's been de-activated.
2047 */
2048
97a39896
AKG		 2049 if (musb->nIrq >= 0) {
2050 if (musb->irq_wake)
2051 disable_irq_wake(musb->nIrq);
550a7375
FB		 2052 free_irq(musb->nIrq, musb);
2053 }
550a7375 2054
74c2e936 2055 musb_host_free(musb);
550a7375
FB		 2056}
2057
ea2f35c0
TL		 2058struct musb_pending_work {
2059 int (*callback)(struct musb *musb, void *data);
2060 void *data;
2061 struct list_head node;
2062};
2063
c8bd2ac3 2064#ifdef CONFIG_PM
ea2f35c0
TL		 2065/*
2066 * Called from musb_runtime_resume(), musb_resume(), and
2067 * musb_queue_resume_work(). Callers must take musb->lock.
2068 */
2069static int musb_run_resume_work(struct musb *musb)
2070{
2071 struct musb_pending_work *w, *_w;
2072 unsigned long flags;
2073 int error = 0;
2074
2075 spin_lock_irqsave(&musb->list_lock, flags);
2076 list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
2077 if (w->callback) {
2078 error = w->callback(musb, w->data);
2079 if (error < 0) {
2080 dev_err(musb->controller,
2081 "resume callback %p failed: %i\n",
2082 w->callback, error);
2083 }
2084 }
2085 list_del(&w->node);
2086 devm_kfree(musb->controller, w);
2087 }
2088 spin_unlock_irqrestore(&musb->list_lock, flags);
2089
2090 return error;
2091}
c8bd2ac3 2092#endif
ea2f35c0
TL		 2093
2094/*
2095 * Called to run work if device is active or else queue the work to happen
2096 * on resume. Caller must take musb->lock and must hold an RPM reference.
2097 *
2098 * Note that we cowardly refuse queuing work after musb PM runtime
2099 * resume is done calling musb_run_resume_work() and return -EINPROGRESS
2100 * instead.
2101 */
2102int musb_queue_resume_work(struct musb *musb,
2103 int (*callback)(struct musb *musb, void *data),
2104 void *data)
2105{
2106 struct musb_pending_work *w;
2107 unsigned long flags;
2f25bec1 2108 bool is_suspended;
ea2f35c0
TL		 2109 int error;
2110
2111 if (WARN_ON(!callback))
2112 return -EINVAL;
2113
2f25bec1
PC		 2114 spin_lock_irqsave(&musb->list_lock, flags);
2115 is_suspended = musb->is_runtime_suspended;
2116
2117 if (is_suspended) {
2118 w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
2119 if (!w) {
2120 error = -ENOMEM;
2121 goto out_unlock;
2122 }
ea2f35c0 2123
2f25bec1
PC		 2124 w->callback = callback;
2125 w->data = data;
ea2f35c0 2126
ea2f35c0
TL		 2127 list_add_tail(&w->node, &musb->pending_list);
2128 error = 0;
ea2f35c0 2129 }
2f25bec1
PC		 2130
2131out_unlock:
ea2f35c0
TL		 2132 spin_unlock_irqrestore(&musb->list_lock, flags);
2133
2f25bec1
PC		 2134 if (!is_suspended)
2135 error = callback(musb, data);
2136
ea2f35c0
TL		 2137 return error;
2138}
2139EXPORT_SYMBOL_GPL(musb_queue_resume_work);
2140
8ed1fb79
DM		 2141static void musb_deassert_reset(struct work_struct *work)
2142{
2143 struct musb *musb;
2144 unsigned long flags;
2145
2146 musb = container_of(work, struct musb, deassert_reset_work.work);
2147
2148 spin_lock_irqsave(&musb->lock, flags);
2149
2150 if (musb->port1_status & USB_PORT_STAT_RESET)
2151 musb_port_reset(musb, false);
2152
2153 spin_unlock_irqrestore(&musb->lock, flags);
2154}
2155
550a7375
FB		 2156/*
2157 * Perform generic per-controller initialization.
2158 *
28dd924a
SS		 2159 * @dev: the controller (already clocked, etc)
2160 * @nIrq: IRQ number
2161 * @ctrl: virtual address of controller registers,
550a7375
FB		 2162 * not yet corrected for platform-specific offsets
2163 */
41ac7b3a 2164static int
550a7375
FB		 2165musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2166{
2167 int status;
2168 struct musb *musb;
c1a7d67c 2169 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
550a7375
FB		 2170
2171 /* The driver might handle more features than the board; OK.
2172 * Fail when the board needs a feature that's not enabled.
2173 */
2174 if (!plat) {
b99d3659 2175 dev_err(dev, "no platform_data?\n");
34e2beb2
SS		 2176 status = -ENODEV;
2177 goto fail0;
550a7375 2178 }
34e2beb2 2179
550a7375 2180 /* allocate */
ca6d1b13 2181 musb = allocate_instance(dev, plat->config, ctrl);
34e2beb2
SS		 2182 if (!musb) {
2183 status = -ENOMEM;
2184 goto fail0;
2185 }
550a7375
FB		 2186
2187 spin_lock_init(&musb->lock);
ea2f35c0 2188 spin_lock_init(&musb->list_lock);
550a7375 2189 musb->board_set_power = plat->set_power;
550a7375 2190 musb->min_power = plat->min_power;
f7ec9437 2191 musb->ops = plat->platform_ops;
9ad96e69 2192 musb->port_mode = plat->mode;
550a7375 2193
1b40fc57
TL		 2194 /*
2195 * Initialize the default IO functions. At least omap2430 needs
2196 * these early. We initialize the platform specific IO functions
2197 * later on.
2198 */
2199 musb_readb = musb_default_readb;
2200 musb_writeb = musb_default_writeb;
2201 musb_readw = musb_default_readw;
2202 musb_writew = musb_default_writew;
1b40fc57 2203
84e250ff 2204 /* The musb_platform_init() call:
baef653a
PDS		 2205 * - adjusts musb->mregs
2206 * - sets the musb->isr
5ae477b0 2207 * - may initialize an integrated transceiver
721002ec 2208 * - initializes musb->xceiv, usually by otg_get_phy()
84e250ff 2209 * - stops powering VBUS
84e250ff 2210 *
a9762b70 2211 * There are various transceiver configurations.
84e250ff
DB		 2212 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2213 * external/discrete ones in various flavors (twl4030 family,
2214 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
550a7375 2215 */
ea65df57 2216 status = musb_platform_init(musb);
550a7375 2217 if (status < 0)
03491761 2218 goto fail1;
34e2beb2 2219
550a7375
FB		 2220 if (!musb->isr) {
2221 status = -ENODEV;
c04352a5 2222 goto fail2;
550a7375
FB		 2223 }
2224
1b40fc57 2225
da96cfc1 2226 /* Most devices use indexed offset or flat offset */
dc8fca6c 2227 if (musb->ops->quirks & MUSB_INDEXED_EP) {
d026e9c7
TL		 2228 musb->io.ep_offset = musb_indexed_ep_offset;
2229 musb->io.ep_select = musb_indexed_ep_select;
2230 } else {
2231 musb->io.ep_offset = musb_flat_ep_offset;
2232 musb->io.ep_select = musb_flat_ep_select;
2233 }
2234
dc8fca6c 2235 if (musb->ops->quirks & MUSB_G_NO_SKB_RESERVE)
1fa07c37
PU		 2236 musb->g.quirk_avoids_skb_reserve = 1;
2237
da96cfc1
BH		 2238 /* At least tusb6010 has its own offsets */
2239 if (musb->ops->ep_offset)
2240 musb->io.ep_offset = musb->ops->ep_offset;
2241 if (musb->ops->ep_select)
2242 musb->io.ep_select = musb->ops->ep_select;
2243
8a77f05a
TL		 2244 if (musb->ops->fifo_mode)
2245 fifo_mode = musb->ops->fifo_mode;
2246 else
2247 fifo_mode = 4;
2248
1b40fc57
TL		 2249 if (musb->ops->fifo_offset)
2250 musb->io.fifo_offset = musb->ops->fifo_offset;
2251 else
2252 musb->io.fifo_offset = musb_default_fifo_offset;
2253
6cc2af6d
HG		 2254 if (musb->ops->busctl_offset)
2255 musb->io.busctl_offset = musb->ops->busctl_offset;
2256 else
2257 musb->io.busctl_offset = musb_default_busctl_offset;
2258
1b40fc57
TL		 2259 if (musb->ops->readb)
2260 musb_readb = musb->ops->readb;
2261 if (musb->ops->writeb)
2262 musb_writeb = musb->ops->writeb;
2263 if (musb->ops->readw)
2264 musb_readw = musb->ops->readw;
2265 if (musb->ops->writew)
2266 musb_writew = musb->ops->writew;
1b40fc57 2267
7f6283ed
TL		 2268#ifndef CONFIG_MUSB_PIO_ONLY
2269 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2270 dev_err(dev, "DMA controller not set\n");
7d32cdef 2271 status = -ENODEV;
7f6283ed
TL		 2272 goto fail2;
2273 }
2274 musb_dma_controller_create = musb->ops->dma_init;
2275 musb_dma_controller_destroy = musb->ops->dma_exit;
2276#endif
2277
1b40fc57
TL		 2278 if (musb->ops->read_fifo)
2279 musb->io.read_fifo = musb->ops->read_fifo;
2280 else
2281 musb->io.read_fifo = musb_default_read_fifo;
2282
2283 if (musb->ops->write_fifo)
2284 musb->io.write_fifo = musb->ops->write_fifo;
2285 else
2286 musb->io.write_fifo = musb_default_write_fifo;
2287
ffb865b1 2288 if (!musb->xceiv->io_ops) {
bf070bc1 2289 musb->xceiv->io_dev = musb->controller;
ffb865b1
HK		 2290 musb->xceiv->io_priv = musb->mregs;
2291 musb->xceiv->io_ops = &musb_ulpi_access;
2292 }
2293
8055555f
TL		 2294 if (musb->ops->phy_callback)
2295 musb_phy_callback = musb->ops->phy_callback;
2296
f730f205
TL		 2297 /*
2298 * We need musb_read/write functions initialized for PM.
2299 * Note that at least 2430 glue needs autosuspend delay
2300 * somewhere above 300 ms for the hardware to idle properly
2301 * after disconnecting the cable in host mode. Let's use
2302 * 500 ms for some margin.
2303 */
2304 pm_runtime_use_autosuspend(musb->controller);
2305 pm_runtime_set_autosuspend_delay(musb->controller, 500);
2306 pm_runtime_enable(musb->controller);
c04352a5
GI		 2307 pm_runtime_get_sync(musb->controller);
2308
39cee200
UKK		 2309 status = usb_phy_init(musb->xceiv);
2310 if (status < 0)
2311 goto err_usb_phy_init;
2312
48054147 2313 if (use_dma && dev->dma_mask) {
7f6283ed
TL		 2314 musb->dma_controller =
2315 musb_dma_controller_create(musb, musb->mregs);
48054147
SAS		 2316 if (IS_ERR(musb->dma_controller)) {
2317 status = PTR_ERR(musb->dma_controller);
2318 goto fail2_5;
2319 }
2320 }
550a7375
FB		 2321
2322 /* be sure interrupts are disabled before connecting ISR */
2323 musb_platform_disable(musb);
e945953d
BL		 2324 musb_disable_interrupts(musb);
2325 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
550a7375 2326
85d37d50
PC		 2327 /* MUSB_POWER_SOFTCONN might be already set, JZ4740 does this. */
2328 musb_writeb(musb->mregs, MUSB_POWER, 0);
2329
66fadea5 2330 /* Init IRQ workqueue before request_irq */
2bff3916 2331 INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
8ed1fb79
DM		 2332 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2333 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
66fadea5 2334
550a7375 2335 /* setup musb parts of the core (especially endpoints) */
ca6d1b13 2336 status = musb_core_init(plat->config->multipoint
550a7375
FB		 2337 ? MUSB_CONTROLLER_MHDRC
2338 : MUSB_CONTROLLER_HDRC, musb);
2339 if (status < 0)
34e2beb2 2340 goto fail3;
550a7375 2341
05678497 2342 timer_setup(&musb->otg_timer, musb_otg_timer_func, 0);
f7f9d63e 2343
550a7375 2344 /* attach to the IRQ */
aa2fb886 2345 if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) {
550a7375
FB		 2346 dev_err(dev, "request_irq %d failed!\n", nIrq);
2347 status = -ENODEV;
34e2beb2 2348 goto fail3;
550a7375
FB		 2349 }
2350 musb->nIrq = nIrq;
032ec49f 2351 /* FIXME this handles wakeup irqs wrong */
c48a5155
FB		 2352 if (enable_irq_wake(nIrq) == 0) {
2353 musb->irq_wake = 1;
550a7375 2354 device_init_wakeup(dev, 1);
c48a5155
FB		 2355 } else {
2356 musb->irq_wake = 0;
2357 }
550a7375 2358
032ec49f
FB		 2359 /* program PHY to use external vBus if required */
2360 if (plat->extvbus) {
113ad151 2361 u8 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL);
032ec49f 2362 busctl |= MUSB_ULPI_USE_EXTVBUS;
113ad151 2363 musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl);
550a7375 2364 }
550a7375 2365
d2852f2d
BL		 2366 MUSB_DEV_MODE(musb);
2367 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
550a7375 2368
6c5f6a6f 2369 switch (musb->port_mode) {
7ad76955 2370 case MUSB_HOST:
6c5f6a6f 2371 status = musb_host_setup(musb, plat->power);
2df6761e
FB		 2372 if (status < 0)
2373 goto fail3;
2374 status = musb_platform_set_mode(musb, MUSB_HOST);
6c5f6a6f 2375 break;
7ad76955 2376 case MUSB_PERIPHERAL:
6c5f6a6f 2377 status = musb_gadget_setup(musb);
2df6761e
FB		 2378 if (status < 0)
2379 goto fail3;
2380 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
6c5f6a6f 2381 break;
7ad76955 2382 case MUSB_OTG:
6c5f6a6f
DM		 2383 status = musb_host_setup(musb, plat->power);
2384 if (status < 0)
2385 goto fail3;
2386 status = musb_gadget_setup(musb);
2df6761e 2387 if (status) {
0d2dd7ea 2388 musb_host_cleanup(musb);
2df6761e
FB		 2389 goto fail3;
2390 }
2391 status = musb_platform_set_mode(musb, MUSB_OTG);
6c5f6a6f
DM		 2392 break;
2393 default:
2394 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2395 break;
2396 }
550a7375 2397
461972d8 2398 if (status < 0)
34e2beb2 2399 goto fail3;
550a7375 2400
8a1ef171 2401 musb_init_debugfs(musb);
7f7f9e2a 2402
c723bd6e 2403 musb->is_initialized = 1;
7099dbc5
TL		 2404 pm_runtime_mark_last_busy(musb->controller);
2405 pm_runtime_put_autosuspend(musb->controller);
c04352a5 2406
28c2c51c 2407 return 0;
550a7375 2408
34e2beb2 2409fail3:
2bff3916 2410 cancel_delayed_work_sync(&musb->irq_work);
8ed1fb79
DM		 2411 cancel_delayed_work_sync(&musb->finish_resume_work);
2412 cancel_delayed_work_sync(&musb->deassert_reset_work);
f3ce4d5b 2413 if (musb->dma_controller)
7f6283ed 2414 musb_dma_controller_destroy(musb->dma_controller);
39cee200 2415
48054147 2416fail2_5:
39cee200
UKK		 2417 usb_phy_shutdown(musb->xceiv);
2418
2419err_usb_phy_init:
7099dbc5 2420 pm_runtime_dont_use_autosuspend(musb->controller);
c04352a5 2421 pm_runtime_put_sync(musb->controller);
f730f205 2422 pm_runtime_disable(musb->controller);
c04352a5
GI		 2423
2424fail2:
34e2beb2
SS		 2425 if (musb->irq_wake)
2426 device_init_wakeup(dev, 0);
550a7375 2427 musb_platform_exit(musb);
28c2c51c 2428
34e2beb2 2429fail1:
3df08dc7
LM		 2430 if (status != -EPROBE_DEFER)
2431 dev_err(musb->controller,
2432 "%s failed with status %d\n", __func__, status);
34e2beb2 2433
28c2c51c
FB		 2434 musb_free(musb);
2435
34e2beb2
SS		 2436fail0:
2437
28c2c51c
FB		 2438 return status;
2439
550a7375
FB		 2440}
2441
2442/*-------------------------------------------------------------------------*/
2443
2444/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2445 * bridge to a platform device; this driver then suffices.
2446 */
41ac7b3a 2447static int musb_probe(struct platform_device *pdev)
550a7375
FB		 2448{
2449 struct device *dev = &pdev->dev;
fcf173e4 2450 int irq = platform_get_irq_byname(pdev, "mc");
550a7375
FB		 2451 struct resource *iomem;
2452 void __iomem *base;
2453
1f79b26c 2454 if (irq <= 0)
550a7375
FB		 2455 return -ENODEV;
2456
1f79b26c 2457 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b42f7f30
FB		 2458 base = devm_ioremap_resource(dev, iomem);
2459 if (IS_ERR(base))
2460 return PTR_ERR(base);
550a7375 2461
b42f7f30 2462 return musb_init_controller(dev, irq, base);
550a7375
FB		 2463}
2464
fb4e98ab 2465static int musb_remove(struct platform_device *pdev)
550a7375 2466{
8d2421e6
AKG		 2467 struct device *dev = &pdev->dev;
2468 struct musb *musb = dev_to_musb(dev);
302f6802 2469 unsigned long flags;
550a7375
FB		 2470
2471 /* this gets called on rmmod.
2472 * - Host mode: host may still be active
2473 * - Peripheral mode: peripheral is deactivated (or never-activated)
2474 * - OTG mode: both roles are deactivated (or never-activated)
2475 */
7f7f9e2a 2476 musb_exit_debugfs(musb);
302f6802 2477
2bff3916 2478 cancel_delayed_work_sync(&musb->irq_work);
f730f205
TL		 2479 cancel_delayed_work_sync(&musb->finish_resume_work);
2480 cancel_delayed_work_sync(&musb->deassert_reset_work);
302f6802
TL		 2481 pm_runtime_get_sync(musb->controller);
2482 musb_host_cleanup(musb);
2483 musb_gadget_cleanup(musb);
e945953d 2484
302f6802 2485 musb_platform_disable(musb);
bc1e2154 2486 spin_lock_irqsave(&musb->lock, flags);
e945953d 2487 musb_disable_interrupts(musb);
302f6802 2488 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
e945953d 2489 spin_unlock_irqrestore(&musb->lock, flags);
94e46a4f 2490 musb_platform_exit(musb);
e945953d 2491
f730f205
TL		 2492 pm_runtime_dont_use_autosuspend(musb->controller);
2493 pm_runtime_put_sync(musb->controller);
2494 pm_runtime_disable(musb->controller);
8055555f 2495 musb_phy_callback = NULL;
8d1aad74 2496 if (musb->dma_controller)
7f6283ed 2497 musb_dma_controller_destroy(musb->dma_controller);
39cee200 2498 usb_phy_shutdown(musb->xceiv);
550a7375 2499 musb_free(musb);
8d2421e6 2500 device_init_wakeup(dev, 0);
550a7375
FB		 2501 return 0;
2502}
2503
2504#ifdef CONFIG_PM
2505
3c8a5fcc 2506static void musb_save_context(struct musb *musb)
4f712e01
AKG		 2507{
2508 int i;
2509 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2510 void __iomem *epio;
4f712e01 2511
032ec49f
FB		 2512 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2513 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
113ad151 2514 musb->context.busctl = musb_readb(musb_base, MUSB_ULPI_BUSCONTROL);
7421107b 2515 musb->context.power = musb_readb(musb_base, MUSB_POWER);
7421107b
FB		 2516 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2517 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2518 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
4f712e01 2519
ae9b2ad2 2520 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2521 struct musb_hw_ep *hw_ep;
2522
2523 hw_ep = &musb->endpoints[i];
2524 if (!hw_ep)
2525 continue;
2526
2527 epio = hw_ep->regs;
2528 if (!epio)
2529 continue;
2530
ea737554 2531 musb_writeb(musb_base, MUSB_INDEX, i);
7421107b 2532 musb->context.index_regs[i].txmaxp =
ae9b2ad2 2533 musb_readw(epio, MUSB_TXMAXP);
7421107b 2534 musb->context.index_regs[i].txcsr =
ae9b2ad2 2535 musb_readw(epio, MUSB_TXCSR);
7421107b 2536 musb->context.index_regs[i].rxmaxp =
ae9b2ad2 2537 musb_readw(epio, MUSB_RXMAXP);
7421107b 2538 musb->context.index_regs[i].rxcsr =
ae9b2ad2 2539 musb_readw(epio, MUSB_RXCSR);
4f712e01
AKG		 2540
2541 if (musb->dyn_fifo) {
7421107b 2542 musb->context.index_regs[i].txfifoadd =
113ad151 2543 musb_readw(musb_base, MUSB_TXFIFOADD);
7421107b 2544 musb->context.index_regs[i].rxfifoadd =
113ad151 2545 musb_readw(musb_base, MUSB_RXFIFOADD);
7421107b 2546 musb->context.index_regs[i].txfifosz =
113ad151 2547 musb_readb(musb_base, MUSB_TXFIFOSZ);
7421107b 2548 musb->context.index_regs[i].rxfifosz =
113ad151 2549 musb_readb(musb_base, MUSB_RXFIFOSZ);
4f712e01 2550 }
032ec49f
FB		 2551
2552 musb->context.index_regs[i].txtype =
2553 musb_readb(epio, MUSB_TXTYPE);
2554 musb->context.index_regs[i].txinterval =
2555 musb_readb(epio, MUSB_TXINTERVAL);
2556 musb->context.index_regs[i].rxtype =
2557 musb_readb(epio, MUSB_RXTYPE);
2558 musb->context.index_regs[i].rxinterval =
2559 musb_readb(epio, MUSB_RXINTERVAL);
2560
2561 musb->context.index_regs[i].txfunaddr =
6cc2af6d 2562 musb_read_txfunaddr(musb, i);
032ec49f 2563 musb->context.index_regs[i].txhubaddr =
6cc2af6d 2564 musb_read_txhubaddr(musb, i);
032ec49f 2565 musb->context.index_regs[i].txhubport =
6cc2af6d 2566 musb_read_txhubport(musb, i);
032ec49f
FB		 2567
2568 musb->context.index_regs[i].rxfunaddr =
6cc2af6d 2569 musb_read_rxfunaddr(musb, i);
032ec49f 2570 musb->context.index_regs[i].rxhubaddr =
6cc2af6d 2571 musb_read_rxhubaddr(musb, i);
032ec49f 2572 musb->context.index_regs[i].rxhubport =
6cc2af6d 2573 musb_read_rxhubport(musb, i);
4f712e01 2574 }
4f712e01
AKG		 2575}
2576
3c8a5fcc 2577static void musb_restore_context(struct musb *musb)
4f712e01
AKG		 2578{
2579 int i;
2580 void __iomem *musb_base = musb->mregs;
ae9b2ad2 2581 void __iomem *epio;
33f8d75f 2582 u8 power;
4f712e01 2583
032ec49f
FB		 2584 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2585 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
113ad151 2586 musb_writeb(musb_base, MUSB_ULPI_BUSCONTROL, musb->context.busctl);
33f8d75f
RQ		 2587
2588 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2589 power = musb_readb(musb_base, MUSB_POWER);
2590 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2591 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2592 power |= musb->context.power;
2593 musb_writeb(musb_base, MUSB_POWER, power);
2594
b18d26f6 2595 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
af5ec14d 2596 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
7421107b 2597 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
84ac5d11
BL		 2598 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2599 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
4f712e01 2600
ae9b2ad2 2601 for (i = 0; i < musb->config->num_eps; ++i) {
e4e5b136
FB		 2602 struct musb_hw_ep *hw_ep;
2603
2604 hw_ep = &musb->endpoints[i];
2605 if (!hw_ep)
2606 continue;
2607
2608 epio = hw_ep->regs;
2609 if (!epio)
2610 continue;
2611
ea737554 2612 musb_writeb(musb_base, MUSB_INDEX, i);
ae9b2ad2 2613 musb_writew(epio, MUSB_TXMAXP,
7421107b 2614 musb->context.index_regs[i].txmaxp);
ae9b2ad2 2615 musb_writew(epio, MUSB_TXCSR,
7421107b 2616 musb->context.index_regs[i].txcsr);
ae9b2ad2 2617 musb_writew(epio, MUSB_RXMAXP,
7421107b 2618 musb->context.index_regs[i].rxmaxp);
ae9b2ad2 2619 musb_writew(epio, MUSB_RXCSR,
7421107b 2620 musb->context.index_regs[i].rxcsr);
4f712e01
AKG		 2621
2622 if (musb->dyn_fifo) {
113ad151 2623 musb_writeb(musb_base, MUSB_TXFIFOSZ,
7421107b 2624 musb->context.index_regs[i].txfifosz);
113ad151 2625 musb_writeb(musb_base, MUSB_RXFIFOSZ,
7421107b 2626 musb->context.index_regs[i].rxfifosz);
113ad151 2627 musb_writew(musb_base, MUSB_TXFIFOADD,
7421107b 2628 musb->context.index_regs[i].txfifoadd);
113ad151 2629 musb_writew(musb_base, MUSB_RXFIFOADD,
7421107b 2630 musb->context.index_regs[i].rxfifoadd);
4f712e01
AKG		 2631 }
2632
032ec49f 2633 musb_writeb(epio, MUSB_TXTYPE,
7421107b 2634 musb->context.index_regs[i].txtype);
032ec49f 2635 musb_writeb(epio, MUSB_TXINTERVAL,
7421107b 2636 musb->context.index_regs[i].txinterval);
032ec49f 2637 musb_writeb(epio, MUSB_RXTYPE,
7421107b 2638 musb->context.index_regs[i].rxtype);
032ec49f 2639 musb_writeb(epio, MUSB_RXINTERVAL,
4f712e01 2640
032ec49f 2641 musb->context.index_regs[i].rxinterval);
6cc2af6d 2642 musb_write_txfunaddr(musb, i,
7421107b 2643 musb->context.index_regs[i].txfunaddr);
6cc2af6d 2644 musb_write_txhubaddr(musb, i,
7421107b 2645 musb->context.index_regs[i].txhubaddr);
6cc2af6d 2646 musb_write_txhubport(musb, i,
7421107b 2647 musb->context.index_regs[i].txhubport);
4f712e01 2648
6cc2af6d 2649 musb_write_rxfunaddr(musb, i,
7421107b 2650 musb->context.index_regs[i].rxfunaddr);
6cc2af6d 2651 musb_write_rxhubaddr(musb, i,
7421107b 2652 musb->context.index_regs[i].rxhubaddr);
6cc2af6d 2653 musb_write_rxhubport(musb, i,
7421107b 2654 musb->context.index_regs[i].rxhubport);
4f712e01 2655 }
3c5fec75 2656 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
4f712e01
AKG		 2657}
2658
48fea965 2659static int musb_suspend(struct device *dev)
550a7375 2660{
8220796d 2661 struct musb *musb = dev_to_musb(dev);
550a7375 2662 unsigned long flags;
082df8be
JH		 2663 int ret;
2664
2665 ret = pm_runtime_get_sync(dev);
2666 if (ret < 0) {
2667 pm_runtime_put_noidle(dev);
2668 return ret;
2669 }
550a7375 2670
6fc6f4b8 2671 musb_platform_disable(musb);
e945953d 2672 musb_disable_interrupts(musb);
0c3aae9b
JH		 2673
2674 musb->flush_irq_work = true;
2675 while (flush_delayed_work(&musb->irq_work))
2676 ;
2677 musb->flush_irq_work = false;
2678
dc8fca6c 2679 if (!(musb->ops->quirks & MUSB_PRESERVE_SESSION))
a926ed11 2680 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
0c3aae9b 2681
ea2f35c0 2682 WARN_ON(!list_empty(&musb->pending_list));
6fc6f4b8 2683
550a7375
FB		 2684 spin_lock_irqsave(&musb->lock, flags);
2685
2686 if (is_peripheral_active(musb)) {
2687 /* FIXME force disconnect unless we know USB will wake
2688 * the system up quickly enough to respond ...
2689 */
2690 } else if (is_host_active(musb)) {
2691 /* we know all the children are suspended; sometimes
2692 * they will even be wakeup-enabled.
2693 */
2694 }
2695
c338412b
DM		 2696 musb_save_context(musb);
2697
550a7375
FB		 2698 spin_unlock_irqrestore(&musb->lock, flags);
2699 return 0;
2700}
2701
3e87d9a3 2702static int musb_resume(struct device *dev)
550a7375 2703{
ea2f35c0
TL		 2704 struct musb *musb = dev_to_musb(dev);
2705 unsigned long flags;
2706 int error;
2707 u8 devctl;
2708 u8 mask;
c338412b
DM		 2709
2710 /*
2711 * For static cmos like DaVinci, register values were preserved
0ec8fd70
KK		 2712 * unless for some reason the whole soc powered down or the USB
2713 * module got reset through the PSC (vs just being disabled).
c338412b
DM		 2714 *
2715 * For the DSPS glue layer though, a full register restore has to
2716 * be done. As it shouldn't harm other platforms, we do it
2717 * unconditionally.
550a7375 2718 */
c338412b
DM		 2719
2720 musb_restore_context(musb);
2721
b87fd2f7
SAS		 2722 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2723 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2724 if ((devctl & mask) != (musb->context.devctl & mask))
2725 musb->port1_status = 0;
a1fc1920 2726
17539f2f
AK		 2727 musb_enable_interrupts(musb);
2728 musb_platform_enable(musb);
6fc6f4b8 2729
a18545e2
BL		 2730 /* session might be disabled in suspend */
2731 if (musb->port_mode == MUSB_HOST &&
2732 !(musb->ops->quirks & MUSB_PRESERVE_SESSION)) {
2733 devctl |= MUSB_DEVCTL_SESSION;
2734 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
2735 }
2736
ea2f35c0
TL		 2737 spin_lock_irqsave(&musb->lock, flags);
2738 error = musb_run_resume_work(musb);
2739 if (error)
2740 dev_err(musb->controller, "resume work failed with %i\n",
2741 error);
2742 spin_unlock_irqrestore(&musb->lock, flags);
2743
082df8be
JH		 2744 pm_runtime_mark_last_busy(dev);
2745 pm_runtime_put_autosuspend(dev);
2746
550a7375
FB		 2747 return 0;
2748}
2749
7acc6197
HH		 2750static int musb_runtime_suspend(struct device *dev)
2751{
2752 struct musb *musb = dev_to_musb(dev);
2753
2754 musb_save_context(musb);
ea2f35c0 2755 musb->is_runtime_suspended = 1;
7acc6197
HH		 2756
2757 return 0;
2758}
2759
2760static int musb_runtime_resume(struct device *dev)
2761{
ea2f35c0
TL		 2762 struct musb *musb = dev_to_musb(dev);
2763 unsigned long flags;
2764 int error;
7acc6197
HH		 2765
2766 /*
2767 * When pm_runtime_get_sync called for the first time in driver
2768 * init, some of the structure is still not initialized which is
2769 * used in restore function. But clock needs to be
2770 * enabled before any register access, so
2771 * pm_runtime_get_sync has to be called.
2772 * Also context restore without save does not make
2773 * any sense
2774 */
c723bd6e
TL		 2775 if (!musb->is_initialized)
2776 return 0;
2777
2778 musb_restore_context(musb);
7acc6197 2779
ea2f35c0
TL		 2780 spin_lock_irqsave(&musb->lock, flags);
2781 error = musb_run_resume_work(musb);
2782 if (error)
2783 dev_err(musb->controller, "resume work failed with %i\n",
2784 error);
2785 musb->is_runtime_suspended = 0;
2786 spin_unlock_irqrestore(&musb->lock, flags);
2787
7acc6197
HH		 2788 return 0;
2789}
2790
47145210 2791static const struct dev_pm_ops musb_dev_pm_ops = {
48fea965 2792 .suspend = musb_suspend,
3e87d9a3 2793 .resume = musb_resume,
7acc6197
HH		 2794 .runtime_suspend = musb_runtime_suspend,
2795 .runtime_resume = musb_runtime_resume,
48fea965
MD		 2796};
2797
2798#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
550a7375 2799#else
48fea965 2800#define MUSB_DEV_PM_OPS NULL
550a7375
FB		 2801#endif
2802
2803static struct platform_driver musb_driver = {
2804 .driver = {
2805 .name = (char *)musb_driver_name,
2806 .bus = &platform_bus_type,
48fea965 2807 .pm = MUSB_DEV_PM_OPS,
d3b5e319 2808 .dev_groups = musb_groups,
550a7375 2809 },
e9e8c85e 2810 .probe = musb_probe,
7690417d 2811 .remove = musb_remove,
550a7375
FB		 2812};
2813
89f836a8 2814module_platform_driver(musb_driver);
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