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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver peripheral support | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
cea83241 | 7 | * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> |
550a7375 FB |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
24 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
26 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/list.h> | |
38 | #include <linux/timer.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/smp.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/moduleparam.h> | |
44 | #include <linux/stat.h> | |
45 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 46 | #include <linux/slab.h> |
550a7375 FB |
47 | |
48 | #include "musb_core.h" | |
49 | ||
50 | ||
51 | /* MUSB PERIPHERAL status 3-mar-2006: | |
52 | * | |
53 | * - EP0 seems solid. It passes both USBCV and usbtest control cases. | |
54 | * Minor glitches: | |
55 | * | |
56 | * + remote wakeup to Linux hosts work, but saw USBCV failures; | |
57 | * in one test run (operator error?) | |
58 | * + endpoint halt tests -- in both usbtest and usbcv -- seem | |
59 | * to break when dma is enabled ... is something wrongly | |
60 | * clearing SENDSTALL? | |
61 | * | |
62 | * - Mass storage behaved ok when last tested. Network traffic patterns | |
63 | * (with lots of short transfers etc) need retesting; they turn up the | |
64 | * worst cases of the DMA, since short packets are typical but are not | |
65 | * required. | |
66 | * | |
67 | * - TX/IN | |
68 | * + both pio and dma behave in with network and g_zero tests | |
69 | * + no cppi throughput issues other than no-hw-queueing | |
70 | * + failed with FLAT_REG (DaVinci) | |
71 | * + seems to behave with double buffering, PIO -and- CPPI | |
72 | * + with gadgetfs + AIO, requests got lost? | |
73 | * | |
74 | * - RX/OUT | |
75 | * + both pio and dma behave in with network and g_zero tests | |
76 | * + dma is slow in typical case (short_not_ok is clear) | |
77 | * + double buffering ok with PIO | |
78 | * + double buffering *FAILS* with CPPI, wrong data bytes sometimes | |
79 | * + request lossage observed with gadgetfs | |
80 | * | |
81 | * - ISO not tested ... might work, but only weakly isochronous | |
82 | * | |
83 | * - Gadget driver disabling of softconnect during bind() is ignored; so | |
84 | * drivers can't hold off host requests until userspace is ready. | |
85 | * (Workaround: they can turn it off later.) | |
86 | * | |
87 | * - PORTABILITY (assumes PIO works): | |
88 | * + DaVinci, basically works with cppi dma | |
89 | * + OMAP 2430, ditto with mentor dma | |
90 | * + TUSB 6010, platform-specific dma in the works | |
91 | */ | |
92 | ||
93 | /* ----------------------------------------------------------------------- */ | |
94 | ||
c65bfa62 MYK |
95 | #define is_buffer_mapped(req) (is_dma_capable() && \ |
96 | (req->map_state != UN_MAPPED)) | |
97 | ||
92d2711f HK |
98 | /* Maps the buffer to dma */ |
99 | ||
100 | static inline void map_dma_buffer(struct musb_request *request, | |
c65bfa62 | 101 | struct musb *musb, struct musb_ep *musb_ep) |
92d2711f | 102 | { |
5f5761cb MYK |
103 | int compatible = true; |
104 | struct dma_controller *dma = musb->dma_controller; | |
105 | ||
c65bfa62 MYK |
106 | request->map_state = UN_MAPPED; |
107 | ||
108 | if (!is_dma_capable() || !musb_ep->dma) | |
109 | return; | |
110 | ||
5f5761cb MYK |
111 | /* Check if DMA engine can handle this request. |
112 | * DMA code must reject the USB request explicitly. | |
113 | * Default behaviour is to map the request. | |
114 | */ | |
115 | if (dma->is_compatible) | |
116 | compatible = dma->is_compatible(musb_ep->dma, | |
117 | musb_ep->packet_sz, request->request.buf, | |
118 | request->request.length); | |
119 | if (!compatible) | |
120 | return; | |
121 | ||
92d2711f HK |
122 | if (request->request.dma == DMA_ADDR_INVALID) { |
123 | request->request.dma = dma_map_single( | |
124 | musb->controller, | |
125 | request->request.buf, | |
126 | request->request.length, | |
127 | request->tx | |
128 | ? DMA_TO_DEVICE | |
129 | : DMA_FROM_DEVICE); | |
c65bfa62 | 130 | request->map_state = MUSB_MAPPED; |
92d2711f HK |
131 | } else { |
132 | dma_sync_single_for_device(musb->controller, | |
133 | request->request.dma, | |
134 | request->request.length, | |
135 | request->tx | |
136 | ? DMA_TO_DEVICE | |
137 | : DMA_FROM_DEVICE); | |
c65bfa62 | 138 | request->map_state = PRE_MAPPED; |
92d2711f HK |
139 | } |
140 | } | |
141 | ||
142 | /* Unmap the buffer from dma and maps it back to cpu */ | |
143 | static inline void unmap_dma_buffer(struct musb_request *request, | |
144 | struct musb *musb) | |
145 | { | |
c65bfa62 MYK |
146 | if (!is_buffer_mapped(request)) |
147 | return; | |
148 | ||
92d2711f | 149 | if (request->request.dma == DMA_ADDR_INVALID) { |
5c8a86e1 FB |
150 | dev_vdbg(musb->controller, |
151 | "not unmapping a never mapped buffer\n"); | |
92d2711f HK |
152 | return; |
153 | } | |
c65bfa62 | 154 | if (request->map_state == MUSB_MAPPED) { |
92d2711f HK |
155 | dma_unmap_single(musb->controller, |
156 | request->request.dma, | |
157 | request->request.length, | |
158 | request->tx | |
159 | ? DMA_TO_DEVICE | |
160 | : DMA_FROM_DEVICE); | |
161 | request->request.dma = DMA_ADDR_INVALID; | |
c65bfa62 | 162 | } else { /* PRE_MAPPED */ |
92d2711f HK |
163 | dma_sync_single_for_cpu(musb->controller, |
164 | request->request.dma, | |
165 | request->request.length, | |
166 | request->tx | |
167 | ? DMA_TO_DEVICE | |
168 | : DMA_FROM_DEVICE); | |
92d2711f | 169 | } |
c65bfa62 | 170 | request->map_state = UN_MAPPED; |
92d2711f HK |
171 | } |
172 | ||
550a7375 FB |
173 | /* |
174 | * Immediately complete a request. | |
175 | * | |
176 | * @param request the request to complete | |
177 | * @param status the status to complete the request with | |
178 | * Context: controller locked, IRQs blocked. | |
179 | */ | |
180 | void musb_g_giveback( | |
181 | struct musb_ep *ep, | |
182 | struct usb_request *request, | |
183 | int status) | |
184 | __releases(ep->musb->lock) | |
185 | __acquires(ep->musb->lock) | |
186 | { | |
187 | struct musb_request *req; | |
188 | struct musb *musb; | |
189 | int busy = ep->busy; | |
190 | ||
191 | req = to_musb_request(request); | |
192 | ||
ad1adb89 | 193 | list_del(&req->list); |
550a7375 FB |
194 | if (req->request.status == -EINPROGRESS) |
195 | req->request.status = status; | |
196 | musb = req->musb; | |
197 | ||
198 | ep->busy = 1; | |
199 | spin_unlock(&musb->lock); | |
c65bfa62 | 200 | unmap_dma_buffer(req, musb); |
550a7375 | 201 | if (request->status == 0) |
5c8a86e1 | 202 | dev_dbg(musb->controller, "%s done request %p, %d/%d\n", |
550a7375 FB |
203 | ep->end_point.name, request, |
204 | req->request.actual, req->request.length); | |
205 | else | |
5c8a86e1 | 206 | dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n", |
550a7375 FB |
207 | ep->end_point.name, request, |
208 | req->request.actual, req->request.length, | |
209 | request->status); | |
210 | req->request.complete(&req->ep->end_point, &req->request); | |
211 | spin_lock(&musb->lock); | |
212 | ep->busy = busy; | |
213 | } | |
214 | ||
215 | /* ----------------------------------------------------------------------- */ | |
216 | ||
217 | /* | |
218 | * Abort requests queued to an endpoint using the status. Synchronous. | |
219 | * caller locked controller and blocked irqs, and selected this ep. | |
220 | */ | |
221 | static void nuke(struct musb_ep *ep, const int status) | |
222 | { | |
5c8a86e1 | 223 | struct musb *musb = ep->musb; |
550a7375 FB |
224 | struct musb_request *req = NULL; |
225 | void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; | |
226 | ||
227 | ep->busy = 1; | |
228 | ||
229 | if (is_dma_capable() && ep->dma) { | |
230 | struct dma_controller *c = ep->musb->dma_controller; | |
231 | int value; | |
b6e434a5 | 232 | |
550a7375 | 233 | if (ep->is_in) { |
b6e434a5 SS |
234 | /* |
235 | * The programming guide says that we must not clear | |
236 | * the DMAMODE bit before DMAENAB, so we only | |
237 | * clear it in the second write... | |
238 | */ | |
550a7375 | 239 | musb_writew(epio, MUSB_TXCSR, |
b6e434a5 | 240 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); |
550a7375 FB |
241 | musb_writew(epio, MUSB_TXCSR, |
242 | 0 | MUSB_TXCSR_FLUSHFIFO); | |
243 | } else { | |
244 | musb_writew(epio, MUSB_RXCSR, | |
245 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
246 | musb_writew(epio, MUSB_RXCSR, | |
247 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
248 | } | |
249 | ||
250 | value = c->channel_abort(ep->dma); | |
5c8a86e1 FB |
251 | dev_dbg(musb->controller, "%s: abort DMA --> %d\n", |
252 | ep->name, value); | |
550a7375 FB |
253 | c->channel_release(ep->dma); |
254 | ep->dma = NULL; | |
255 | } | |
256 | ||
ad1adb89 FB |
257 | while (!list_empty(&ep->req_list)) { |
258 | req = list_first_entry(&ep->req_list, struct musb_request, list); | |
550a7375 FB |
259 | musb_g_giveback(ep, &req->request, status); |
260 | } | |
261 | } | |
262 | ||
263 | /* ----------------------------------------------------------------------- */ | |
264 | ||
265 | /* Data transfers - pure PIO, pure DMA, or mixed mode */ | |
266 | ||
267 | /* | |
268 | * This assumes the separate CPPI engine is responding to DMA requests | |
269 | * from the usb core ... sequenced a bit differently from mentor dma. | |
270 | */ | |
271 | ||
272 | static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) | |
273 | { | |
274 | if (can_bulk_split(musb, ep->type)) | |
275 | return ep->hw_ep->max_packet_sz_tx; | |
276 | else | |
277 | return ep->packet_sz; | |
278 | } | |
279 | ||
280 | ||
281 | #ifdef CONFIG_USB_INVENTRA_DMA | |
282 | ||
283 | /* Peripheral tx (IN) using Mentor DMA works as follows: | |
284 | Only mode 0 is used for transfers <= wPktSize, | |
285 | mode 1 is used for larger transfers, | |
286 | ||
287 | One of the following happens: | |
288 | - Host sends IN token which causes an endpoint interrupt | |
289 | -> TxAvail | |
290 | -> if DMA is currently busy, exit. | |
291 | -> if queue is non-empty, txstate(). | |
292 | ||
293 | - Request is queued by the gadget driver. | |
294 | -> if queue was previously empty, txstate() | |
295 | ||
296 | txstate() | |
297 | -> start | |
298 | /\ -> setup DMA | |
299 | | (data is transferred to the FIFO, then sent out when | |
300 | | IN token(s) are recd from Host. | |
301 | | -> DMA interrupt on completion | |
302 | | calls TxAvail. | |
b6e434a5 | 303 | | -> stop DMA, ~DMAENAB, |
550a7375 FB |
304 | | -> set TxPktRdy for last short pkt or zlp |
305 | | -> Complete Request | |
306 | | -> Continue next request (call txstate) | |
307 | |___________________________________| | |
308 | ||
309 | * Non-Mentor DMA engines can of course work differently, such as by | |
310 | * upleveling from irq-per-packet to irq-per-buffer. | |
311 | */ | |
312 | ||
313 | #endif | |
314 | ||
315 | /* | |
316 | * An endpoint is transmitting data. This can be called either from | |
317 | * the IRQ routine or from ep.queue() to kickstart a request on an | |
318 | * endpoint. | |
319 | * | |
320 | * Context: controller locked, IRQs blocked, endpoint selected | |
321 | */ | |
322 | static void txstate(struct musb *musb, struct musb_request *req) | |
323 | { | |
324 | u8 epnum = req->epnum; | |
325 | struct musb_ep *musb_ep; | |
326 | void __iomem *epio = musb->endpoints[epnum].regs; | |
327 | struct usb_request *request; | |
328 | u16 fifo_count = 0, csr; | |
329 | int use_dma = 0; | |
330 | ||
331 | musb_ep = req->ep; | |
332 | ||
333 | /* we shouldn't get here while DMA is active ... but we do ... */ | |
334 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { | |
5c8a86e1 | 335 | dev_dbg(musb->controller, "dma pending...\n"); |
550a7375 FB |
336 | return; |
337 | } | |
338 | ||
339 | /* read TXCSR before */ | |
340 | csr = musb_readw(epio, MUSB_TXCSR); | |
341 | ||
342 | request = &req->request; | |
343 | fifo_count = min(max_ep_writesize(musb, musb_ep), | |
344 | (int)(request->length - request->actual)); | |
345 | ||
346 | if (csr & MUSB_TXCSR_TXPKTRDY) { | |
5c8a86e1 | 347 | dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n", |
550a7375 FB |
348 | musb_ep->end_point.name, csr); |
349 | return; | |
350 | } | |
351 | ||
352 | if (csr & MUSB_TXCSR_P_SENDSTALL) { | |
5c8a86e1 | 353 | dev_dbg(musb->controller, "%s stalling, txcsr %03x\n", |
550a7375 FB |
354 | musb_ep->end_point.name, csr); |
355 | return; | |
356 | } | |
357 | ||
5c8a86e1 | 358 | dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", |
550a7375 FB |
359 | epnum, musb_ep->packet_sz, fifo_count, |
360 | csr); | |
361 | ||
362 | #ifndef CONFIG_MUSB_PIO_ONLY | |
c65bfa62 | 363 | if (is_buffer_mapped(req)) { |
550a7375 | 364 | struct dma_controller *c = musb->dma_controller; |
66af83dd ML |
365 | size_t request_size; |
366 | ||
367 | /* setup DMA, then program endpoint CSR */ | |
368 | request_size = min_t(size_t, request->length - request->actual, | |
369 | musb_ep->dma->max_len); | |
550a7375 FB |
370 | |
371 | use_dma = (request->dma != DMA_ADDR_INVALID); | |
372 | ||
373 | /* MUSB_TXCSR_P_ISO is still set correctly */ | |
374 | ||
a48ff906 | 375 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) |
550a7375 | 376 | { |
d1043a26 | 377 | if (request_size < musb_ep->packet_sz) |
550a7375 FB |
378 | musb_ep->dma->desired_mode = 0; |
379 | else | |
380 | musb_ep->dma->desired_mode = 1; | |
381 | ||
382 | use_dma = use_dma && c->channel_program( | |
383 | musb_ep->dma, musb_ep->packet_sz, | |
384 | musb_ep->dma->desired_mode, | |
796a83fa | 385 | request->dma + request->actual, request_size); |
550a7375 FB |
386 | if (use_dma) { |
387 | if (musb_ep->dma->desired_mode == 0) { | |
b6e434a5 SS |
388 | /* |
389 | * We must not clear the DMAMODE bit | |
390 | * before the DMAENAB bit -- and the | |
391 | * latter doesn't always get cleared | |
392 | * before we get here... | |
393 | */ | |
394 | csr &= ~(MUSB_TXCSR_AUTOSET | |
395 | | MUSB_TXCSR_DMAENAB); | |
396 | musb_writew(epio, MUSB_TXCSR, csr | |
397 | | MUSB_TXCSR_P_WZC_BITS); | |
398 | csr &= ~MUSB_TXCSR_DMAMODE; | |
550a7375 FB |
399 | csr |= (MUSB_TXCSR_DMAENAB | |
400 | MUSB_TXCSR_MODE); | |
401 | /* against programming guide */ | |
f11d893d ML |
402 | } else { |
403 | csr |= (MUSB_TXCSR_DMAENAB | |
550a7375 FB |
404 | | MUSB_TXCSR_DMAMODE |
405 | | MUSB_TXCSR_MODE); | |
f11d893d ML |
406 | if (!musb_ep->hb_mult) |
407 | csr |= MUSB_TXCSR_AUTOSET; | |
408 | } | |
550a7375 | 409 | csr &= ~MUSB_TXCSR_P_UNDERRUN; |
f11d893d | 410 | |
550a7375 FB |
411 | musb_writew(epio, MUSB_TXCSR, csr); |
412 | } | |
413 | } | |
414 | ||
415 | #elif defined(CONFIG_USB_TI_CPPI_DMA) | |
416 | /* program endpoint CSR first, then setup DMA */ | |
b6e434a5 | 417 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); |
37e3ee99 SS |
418 | csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | |
419 | MUSB_TXCSR_MODE; | |
550a7375 FB |
420 | musb_writew(epio, MUSB_TXCSR, |
421 | (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN) | |
422 | | csr); | |
423 | ||
424 | /* ensure writebuffer is empty */ | |
425 | csr = musb_readw(epio, MUSB_TXCSR); | |
426 | ||
427 | /* NOTE host side sets DMAENAB later than this; both are | |
428 | * OK since the transfer dma glue (between CPPI and Mentor | |
429 | * fifos) just tells CPPI it could start. Data only moves | |
430 | * to the USB TX fifo when both fifos are ready. | |
431 | */ | |
432 | ||
433 | /* "mode" is irrelevant here; handle terminating ZLPs like | |
434 | * PIO does, since the hardware RNDIS mode seems unreliable | |
435 | * except for the last-packet-is-already-short case. | |
436 | */ | |
437 | use_dma = use_dma && c->channel_program( | |
438 | musb_ep->dma, musb_ep->packet_sz, | |
439 | 0, | |
66af83dd ML |
440 | request->dma + request->actual, |
441 | request_size); | |
550a7375 FB |
442 | if (!use_dma) { |
443 | c->channel_release(musb_ep->dma); | |
444 | musb_ep->dma = NULL; | |
b6e434a5 SS |
445 | csr &= ~MUSB_TXCSR_DMAENAB; |
446 | musb_writew(epio, MUSB_TXCSR, csr); | |
550a7375 FB |
447 | /* invariant: prequest->buf is non-null */ |
448 | } | |
449 | #elif defined(CONFIG_USB_TUSB_OMAP_DMA) | |
450 | use_dma = use_dma && c->channel_program( | |
451 | musb_ep->dma, musb_ep->packet_sz, | |
452 | request->zero, | |
66af83dd ML |
453 | request->dma + request->actual, |
454 | request_size); | |
550a7375 FB |
455 | #endif |
456 | } | |
457 | #endif | |
458 | ||
459 | if (!use_dma) { | |
92d2711f HK |
460 | /* |
461 | * Unmap the dma buffer back to cpu if dma channel | |
462 | * programming fails | |
463 | */ | |
c65bfa62 | 464 | unmap_dma_buffer(req, musb); |
92d2711f | 465 | |
550a7375 FB |
466 | musb_write_fifo(musb_ep->hw_ep, fifo_count, |
467 | (u8 *) (request->buf + request->actual)); | |
468 | request->actual += fifo_count; | |
469 | csr |= MUSB_TXCSR_TXPKTRDY; | |
470 | csr &= ~MUSB_TXCSR_P_UNDERRUN; | |
471 | musb_writew(epio, MUSB_TXCSR, csr); | |
472 | } | |
473 | ||
474 | /* host may already have the data when this message shows... */ | |
5c8a86e1 | 475 | dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", |
550a7375 FB |
476 | musb_ep->end_point.name, use_dma ? "dma" : "pio", |
477 | request->actual, request->length, | |
478 | musb_readw(epio, MUSB_TXCSR), | |
479 | fifo_count, | |
480 | musb_readw(epio, MUSB_TXMAXP)); | |
481 | } | |
482 | ||
483 | /* | |
484 | * FIFO state update (e.g. data ready). | |
485 | * Called from IRQ, with controller locked. | |
486 | */ | |
487 | void musb_g_tx(struct musb *musb, u8 epnum) | |
488 | { | |
489 | u16 csr; | |
ad1adb89 | 490 | struct musb_request *req; |
550a7375 FB |
491 | struct usb_request *request; |
492 | u8 __iomem *mbase = musb->mregs; | |
493 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; | |
494 | void __iomem *epio = musb->endpoints[epnum].regs; | |
495 | struct dma_channel *dma; | |
496 | ||
497 | musb_ep_select(mbase, epnum); | |
ad1adb89 FB |
498 | req = next_request(musb_ep); |
499 | request = &req->request; | |
550a7375 FB |
500 | |
501 | csr = musb_readw(epio, MUSB_TXCSR); | |
5c8a86e1 | 502 | dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); |
550a7375 FB |
503 | |
504 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
7723de7e SS |
505 | |
506 | /* | |
507 | * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX | |
508 | * probably rates reporting as a host error. | |
509 | */ | |
510 | if (csr & MUSB_TXCSR_P_SENTSTALL) { | |
511 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
512 | csr &= ~MUSB_TXCSR_P_SENTSTALL; | |
513 | musb_writew(epio, MUSB_TXCSR, csr); | |
514 | return; | |
515 | } | |
516 | ||
517 | if (csr & MUSB_TXCSR_P_UNDERRUN) { | |
518 | /* We NAKed, no big deal... little reason to care. */ | |
519 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
520 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); | |
521 | musb_writew(epio, MUSB_TXCSR, csr); | |
5c8a86e1 FB |
522 | dev_vdbg(musb->controller, "underrun on ep%d, req %p\n", |
523 | epnum, request); | |
7723de7e SS |
524 | } |
525 | ||
526 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
527 | /* | |
528 | * SHOULD NOT HAPPEN... has with CPPI though, after | |
529 | * changing SENDSTALL (and other cases); harmless? | |
550a7375 | 530 | */ |
5c8a86e1 | 531 | dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name); |
7723de7e SS |
532 | return; |
533 | } | |
550a7375 | 534 | |
7723de7e SS |
535 | if (request) { |
536 | u8 is_dma = 0; | |
537 | ||
538 | if (dma && (csr & MUSB_TXCSR_DMAENAB)) { | |
539 | is_dma = 1; | |
550a7375 | 540 | csr |= MUSB_TXCSR_P_WZC_BITS; |
7723de7e | 541 | csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | |
100d4a9d | 542 | MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET); |
550a7375 | 543 | musb_writew(epio, MUSB_TXCSR, csr); |
7723de7e SS |
544 | /* Ensure writebuffer is empty. */ |
545 | csr = musb_readw(epio, MUSB_TXCSR); | |
546 | request->actual += musb_ep->dma->actual_len; | |
5c8a86e1 | 547 | dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n", |
7723de7e | 548 | epnum, csr, musb_ep->dma->actual_len, request); |
550a7375 FB |
549 | } |
550 | ||
e7379aaa ML |
551 | /* |
552 | * First, maybe a terminating short packet. Some DMA | |
553 | * engines might handle this by themselves. | |
554 | */ | |
555 | if ((request->zero && request->length | |
556 | && (request->length % musb_ep->packet_sz == 0) | |
557 | && (request->actual == request->length)) | |
a48ff906 | 558 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) |
e7379aaa ML |
559 | || (is_dma && (!dma->desired_mode || |
560 | (request->actual & | |
561 | (musb_ep->packet_sz - 1)))) | |
550a7375 | 562 | #endif |
e7379aaa ML |
563 | ) { |
564 | /* | |
565 | * On DMA completion, FIFO may not be | |
566 | * available yet... | |
567 | */ | |
568 | if (csr & MUSB_TXCSR_TXPKTRDY) | |
569 | return; | |
550a7375 | 570 | |
5c8a86e1 | 571 | dev_dbg(musb->controller, "sending zero pkt\n"); |
e7379aaa ML |
572 | musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE |
573 | | MUSB_TXCSR_TXPKTRDY); | |
574 | request->zero = 0; | |
575 | } | |
576 | ||
577 | if (request->actual == request->length) { | |
578 | musb_g_giveback(musb_ep, request, 0); | |
ad1adb89 FB |
579 | req = musb_ep->desc ? next_request(musb_ep) : NULL; |
580 | if (!req) { | |
5c8a86e1 | 581 | dev_dbg(musb->controller, "%s idle now\n", |
e7379aaa ML |
582 | musb_ep->end_point.name); |
583 | return; | |
95962a77 | 584 | } |
550a7375 FB |
585 | } |
586 | ||
ad1adb89 | 587 | txstate(musb, req); |
7723de7e | 588 | } |
550a7375 FB |
589 | } |
590 | ||
591 | /* ------------------------------------------------------------ */ | |
592 | ||
593 | #ifdef CONFIG_USB_INVENTRA_DMA | |
594 | ||
595 | /* Peripheral rx (OUT) using Mentor DMA works as follows: | |
596 | - Only mode 0 is used. | |
597 | ||
598 | - Request is queued by the gadget class driver. | |
599 | -> if queue was previously empty, rxstate() | |
600 | ||
601 | - Host sends OUT token which causes an endpoint interrupt | |
602 | /\ -> RxReady | |
603 | | -> if request queued, call rxstate | |
604 | | /\ -> setup DMA | |
605 | | | -> DMA interrupt on completion | |
606 | | | -> RxReady | |
607 | | | -> stop DMA | |
608 | | | -> ack the read | |
609 | | | -> if data recd = max expected | |
610 | | | by the request, or host | |
611 | | | sent a short packet, | |
612 | | | complete the request, | |
613 | | | and start the next one. | |
614 | | |_____________________________________| | |
615 | | else just wait for the host | |
616 | | to send the next OUT token. | |
617 | |__________________________________________________| | |
618 | ||
619 | * Non-Mentor DMA engines can of course work differently. | |
620 | */ | |
621 | ||
622 | #endif | |
623 | ||
624 | /* | |
625 | * Context: controller locked, IRQs blocked, endpoint selected | |
626 | */ | |
627 | static void rxstate(struct musb *musb, struct musb_request *req) | |
628 | { | |
550a7375 FB |
629 | const u8 epnum = req->epnum; |
630 | struct usb_request *request = &req->request; | |
bd2e74d6 | 631 | struct musb_ep *musb_ep; |
550a7375 | 632 | void __iomem *epio = musb->endpoints[epnum].regs; |
c2c96321 | 633 | unsigned fifo_count = 0; |
bd2e74d6 | 634 | u16 len; |
cea83241 | 635 | u16 csr = musb_readw(epio, MUSB_RXCSR); |
bd2e74d6 ML |
636 | struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; |
637 | ||
638 | if (hw_ep->is_shared_fifo) | |
639 | musb_ep = &hw_ep->ep_in; | |
640 | else | |
641 | musb_ep = &hw_ep->ep_out; | |
642 | ||
643 | len = musb_ep->packet_sz; | |
550a7375 | 644 | |
cea83241 SS |
645 | /* We shouldn't get here while DMA is active, but we do... */ |
646 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { | |
5c8a86e1 | 647 | dev_dbg(musb->controller, "DMA pending...\n"); |
cea83241 SS |
648 | return; |
649 | } | |
650 | ||
651 | if (csr & MUSB_RXCSR_P_SENDSTALL) { | |
5c8a86e1 | 652 | dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n", |
cea83241 SS |
653 | musb_ep->end_point.name, csr); |
654 | return; | |
655 | } | |
550a7375 | 656 | |
c65bfa62 | 657 | if (is_cppi_enabled() && is_buffer_mapped(req)) { |
550a7375 FB |
658 | struct dma_controller *c = musb->dma_controller; |
659 | struct dma_channel *channel = musb_ep->dma; | |
660 | ||
661 | /* NOTE: CPPI won't actually stop advancing the DMA | |
662 | * queue after short packet transfers, so this is almost | |
663 | * always going to run as IRQ-per-packet DMA so that | |
664 | * faults will be handled correctly. | |
665 | */ | |
666 | if (c->channel_program(channel, | |
667 | musb_ep->packet_sz, | |
668 | !request->short_not_ok, | |
669 | request->dma + request->actual, | |
670 | request->length - request->actual)) { | |
671 | ||
672 | /* make sure that if an rxpkt arrived after the irq, | |
673 | * the cppi engine will be ready to take it as soon | |
674 | * as DMA is enabled | |
675 | */ | |
676 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
677 | | MUSB_RXCSR_DMAMODE); | |
678 | csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; | |
679 | musb_writew(epio, MUSB_RXCSR, csr); | |
680 | return; | |
681 | } | |
682 | } | |
683 | ||
684 | if (csr & MUSB_RXCSR_RXPKTRDY) { | |
685 | len = musb_readw(epio, MUSB_RXCOUNT); | |
686 | if (request->actual < request->length) { | |
687 | #ifdef CONFIG_USB_INVENTRA_DMA | |
c65bfa62 | 688 | if (is_buffer_mapped(req)) { |
550a7375 FB |
689 | struct dma_controller *c; |
690 | struct dma_channel *channel; | |
691 | int use_dma = 0; | |
692 | ||
693 | c = musb->dma_controller; | |
694 | channel = musb_ep->dma; | |
695 | ||
696 | /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in | |
697 | * mode 0 only. So we do not get endpoint interrupts due to DMA | |
698 | * completion. We only get interrupts from DMA controller. | |
699 | * | |
700 | * We could operate in DMA mode 1 if we knew the size of the tranfer | |
701 | * in advance. For mass storage class, request->length = what the host | |
702 | * sends, so that'd work. But for pretty much everything else, | |
703 | * request->length is routinely more than what the host sends. For | |
704 | * most these gadgets, end of is signified either by a short packet, | |
705 | * or filling the last byte of the buffer. (Sending extra data in | |
706 | * that last pckate should trigger an overflow fault.) But in mode 1, | |
707 | * we don't get DMA completion interrrupt for short packets. | |
708 | * | |
709 | * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), | |
710 | * to get endpoint interrupt on every DMA req, but that didn't seem | |
711 | * to work reliably. | |
712 | * | |
713 | * REVISIT an updated g_file_storage can set req->short_not_ok, which | |
714 | * then becomes usable as a runtime "use mode 1" hint... | |
715 | */ | |
716 | ||
717 | csr |= MUSB_RXCSR_DMAENAB; | |
490e5fbe | 718 | #ifdef USE_MODE1 |
9001d80d | 719 | csr |= MUSB_RXCSR_AUTOCLEAR; |
550a7375 FB |
720 | /* csr |= MUSB_RXCSR_DMAMODE; */ |
721 | ||
722 | /* this special sequence (enabling and then | |
723 | * disabling MUSB_RXCSR_DMAMODE) is required | |
724 | * to get DMAReq to activate | |
725 | */ | |
726 | musb_writew(epio, MUSB_RXCSR, | |
727 | csr | MUSB_RXCSR_DMAMODE); | |
9001d80d ML |
728 | #else |
729 | if (!musb_ep->hb_mult && | |
730 | musb_ep->hw_ep->rx_double_buffered) | |
731 | csr |= MUSB_RXCSR_AUTOCLEAR; | |
550a7375 FB |
732 | #endif |
733 | musb_writew(epio, MUSB_RXCSR, csr); | |
734 | ||
735 | if (request->actual < request->length) { | |
736 | int transfer_size = 0; | |
737 | #ifdef USE_MODE1 | |
1018b4e4 | 738 | transfer_size = min(request->length - request->actual, |
550a7375 FB |
739 | channel->max_len); |
740 | #else | |
1018b4e4 ML |
741 | transfer_size = min(request->length - request->actual, |
742 | (unsigned)len); | |
550a7375 FB |
743 | #endif |
744 | if (transfer_size <= musb_ep->packet_sz) | |
745 | musb_ep->dma->desired_mode = 0; | |
746 | else | |
747 | musb_ep->dma->desired_mode = 1; | |
748 | ||
749 | use_dma = c->channel_program( | |
750 | channel, | |
751 | musb_ep->packet_sz, | |
752 | channel->desired_mode, | |
753 | request->dma | |
754 | + request->actual, | |
755 | transfer_size); | |
756 | } | |
757 | ||
758 | if (use_dma) | |
a48ff906 MYK |
759 | return; |
760 | } | |
761 | #elif defined(CONFIG_USB_UX500_DMA) | |
762 | if ((is_buffer_mapped(req)) && | |
763 | (request->actual < request->length)) { | |
764 | ||
765 | struct dma_controller *c; | |
766 | struct dma_channel *channel; | |
767 | int transfer_size = 0; | |
768 | ||
769 | c = musb->dma_controller; | |
770 | channel = musb_ep->dma; | |
771 | ||
772 | /* In case first packet is short */ | |
773 | if (len < musb_ep->packet_sz) | |
774 | transfer_size = len; | |
775 | else if (request->short_not_ok) | |
776 | transfer_size = min(request->length - | |
777 | request->actual, | |
778 | channel->max_len); | |
779 | else | |
780 | transfer_size = min(request->length - | |
781 | request->actual, | |
782 | (unsigned)len); | |
783 | ||
784 | csr &= ~MUSB_RXCSR_DMAMODE; | |
785 | csr |= (MUSB_RXCSR_DMAENAB | | |
786 | MUSB_RXCSR_AUTOCLEAR); | |
787 | ||
788 | musb_writew(epio, MUSB_RXCSR, csr); | |
789 | ||
790 | if (transfer_size <= musb_ep->packet_sz) { | |
791 | musb_ep->dma->desired_mode = 0; | |
792 | } else { | |
793 | musb_ep->dma->desired_mode = 1; | |
794 | /* Mode must be set after DMAENAB */ | |
795 | csr |= MUSB_RXCSR_DMAMODE; | |
796 | musb_writew(epio, MUSB_RXCSR, csr); | |
797 | } | |
798 | ||
799 | if (c->channel_program(channel, | |
800 | musb_ep->packet_sz, | |
801 | channel->desired_mode, | |
802 | request->dma | |
803 | + request->actual, | |
804 | transfer_size)) | |
805 | ||
550a7375 FB |
806 | return; |
807 | } | |
808 | #endif /* Mentor's DMA */ | |
809 | ||
810 | fifo_count = request->length - request->actual; | |
5c8a86e1 | 811 | dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", |
550a7375 FB |
812 | musb_ep->end_point.name, |
813 | len, fifo_count, | |
814 | musb_ep->packet_sz); | |
815 | ||
c2c96321 | 816 | fifo_count = min_t(unsigned, len, fifo_count); |
550a7375 FB |
817 | |
818 | #ifdef CONFIG_USB_TUSB_OMAP_DMA | |
c65bfa62 | 819 | if (tusb_dma_omap() && is_buffer_mapped(req)) { |
550a7375 FB |
820 | struct dma_controller *c = musb->dma_controller; |
821 | struct dma_channel *channel = musb_ep->dma; | |
822 | u32 dma_addr = request->dma + request->actual; | |
823 | int ret; | |
824 | ||
825 | ret = c->channel_program(channel, | |
826 | musb_ep->packet_sz, | |
827 | channel->desired_mode, | |
828 | dma_addr, | |
829 | fifo_count); | |
830 | if (ret) | |
831 | return; | |
832 | } | |
833 | #endif | |
92d2711f HK |
834 | /* |
835 | * Unmap the dma buffer back to cpu if dma channel | |
836 | * programming fails. This buffer is mapped if the | |
837 | * channel allocation is successful | |
838 | */ | |
c65bfa62 | 839 | if (is_buffer_mapped(req)) { |
92d2711f HK |
840 | unmap_dma_buffer(req, musb); |
841 | ||
e75df371 ML |
842 | /* |
843 | * Clear DMAENAB and AUTOCLEAR for the | |
92d2711f HK |
844 | * PIO mode transfer |
845 | */ | |
e75df371 | 846 | csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR); |
92d2711f HK |
847 | musb_writew(epio, MUSB_RXCSR, csr); |
848 | } | |
550a7375 FB |
849 | |
850 | musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) | |
851 | (request->buf + request->actual)); | |
852 | request->actual += fifo_count; | |
853 | ||
854 | /* REVISIT if we left anything in the fifo, flush | |
855 | * it and report -EOVERFLOW | |
856 | */ | |
857 | ||
858 | /* ack the read! */ | |
859 | csr |= MUSB_RXCSR_P_WZC_BITS; | |
860 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
861 | musb_writew(epio, MUSB_RXCSR, csr); | |
862 | } | |
863 | } | |
864 | ||
865 | /* reach the end or short packet detected */ | |
866 | if (request->actual == request->length || len < musb_ep->packet_sz) | |
867 | musb_g_giveback(musb_ep, request, 0); | |
868 | } | |
869 | ||
870 | /* | |
871 | * Data ready for a request; called from IRQ | |
872 | */ | |
873 | void musb_g_rx(struct musb *musb, u8 epnum) | |
874 | { | |
875 | u16 csr; | |
ad1adb89 | 876 | struct musb_request *req; |
550a7375 FB |
877 | struct usb_request *request; |
878 | void __iomem *mbase = musb->mregs; | |
bd2e74d6 | 879 | struct musb_ep *musb_ep; |
550a7375 FB |
880 | void __iomem *epio = musb->endpoints[epnum].regs; |
881 | struct dma_channel *dma; | |
bd2e74d6 ML |
882 | struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; |
883 | ||
884 | if (hw_ep->is_shared_fifo) | |
885 | musb_ep = &hw_ep->ep_in; | |
886 | else | |
887 | musb_ep = &hw_ep->ep_out; | |
550a7375 FB |
888 | |
889 | musb_ep_select(mbase, epnum); | |
890 | ||
ad1adb89 FB |
891 | req = next_request(musb_ep); |
892 | if (!req) | |
0abdc36f | 893 | return; |
550a7375 | 894 | |
ad1adb89 FB |
895 | request = &req->request; |
896 | ||
550a7375 FB |
897 | csr = musb_readw(epio, MUSB_RXCSR); |
898 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
899 | ||
5c8a86e1 | 900 | dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, |
550a7375 FB |
901 | csr, dma ? " (dma)" : "", request); |
902 | ||
903 | if (csr & MUSB_RXCSR_P_SENTSTALL) { | |
550a7375 FB |
904 | csr |= MUSB_RXCSR_P_WZC_BITS; |
905 | csr &= ~MUSB_RXCSR_P_SENTSTALL; | |
906 | musb_writew(epio, MUSB_RXCSR, csr); | |
cea83241 | 907 | return; |
550a7375 FB |
908 | } |
909 | ||
910 | if (csr & MUSB_RXCSR_P_OVERRUN) { | |
911 | /* csr |= MUSB_RXCSR_P_WZC_BITS; */ | |
912 | csr &= ~MUSB_RXCSR_P_OVERRUN; | |
913 | musb_writew(epio, MUSB_RXCSR, csr); | |
914 | ||
5c8a86e1 | 915 | dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request); |
43467868 | 916 | if (request->status == -EINPROGRESS) |
550a7375 FB |
917 | request->status = -EOVERFLOW; |
918 | } | |
919 | if (csr & MUSB_RXCSR_INCOMPRX) { | |
920 | /* REVISIT not necessarily an error */ | |
5c8a86e1 | 921 | dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name); |
550a7375 FB |
922 | } |
923 | ||
924 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
925 | /* "should not happen"; likely RXPKTRDY pending for DMA */ | |
5c8a86e1 | 926 | dev_dbg(musb->controller, "%s busy, csr %04x\n", |
550a7375 | 927 | musb_ep->end_point.name, csr); |
cea83241 | 928 | return; |
550a7375 FB |
929 | } |
930 | ||
931 | if (dma && (csr & MUSB_RXCSR_DMAENAB)) { | |
932 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
933 | | MUSB_RXCSR_DMAENAB | |
934 | | MUSB_RXCSR_DMAMODE); | |
935 | musb_writew(epio, MUSB_RXCSR, | |
936 | MUSB_RXCSR_P_WZC_BITS | csr); | |
937 | ||
938 | request->actual += musb_ep->dma->actual_len; | |
939 | ||
5c8a86e1 | 940 | dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", |
550a7375 FB |
941 | epnum, csr, |
942 | musb_readw(epio, MUSB_RXCSR), | |
943 | musb_ep->dma->actual_len, request); | |
944 | ||
a48ff906 MYK |
945 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ |
946 | defined(CONFIG_USB_UX500_DMA) | |
550a7375 | 947 | /* Autoclear doesn't clear RxPktRdy for short packets */ |
9001d80d | 948 | if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered) |
550a7375 FB |
949 | || (dma->actual_len |
950 | & (musb_ep->packet_sz - 1))) { | |
951 | /* ack the read! */ | |
952 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
953 | musb_writew(epio, MUSB_RXCSR, csr); | |
954 | } | |
955 | ||
956 | /* incomplete, and not short? wait for next IN packet */ | |
957 | if ((request->actual < request->length) | |
958 | && (musb_ep->dma->actual_len | |
9001d80d ML |
959 | == musb_ep->packet_sz)) { |
960 | /* In double buffer case, continue to unload fifo if | |
961 | * there is Rx packet in FIFO. | |
962 | **/ | |
963 | csr = musb_readw(epio, MUSB_RXCSR); | |
964 | if ((csr & MUSB_RXCSR_RXPKTRDY) && | |
965 | hw_ep->rx_double_buffered) | |
966 | goto exit; | |
cea83241 | 967 | return; |
9001d80d | 968 | } |
550a7375 FB |
969 | #endif |
970 | musb_g_giveback(musb_ep, request, 0); | |
971 | ||
ad1adb89 FB |
972 | req = next_request(musb_ep); |
973 | if (!req) | |
cea83241 | 974 | return; |
550a7375 | 975 | } |
a48ff906 MYK |
976 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ |
977 | defined(CONFIG_USB_UX500_DMA) | |
9001d80d | 978 | exit: |
bb324b08 | 979 | #endif |
43467868 | 980 | /* Analyze request */ |
ad1adb89 | 981 | rxstate(musb, req); |
550a7375 FB |
982 | } |
983 | ||
984 | /* ------------------------------------------------------------ */ | |
985 | ||
986 | static int musb_gadget_enable(struct usb_ep *ep, | |
987 | const struct usb_endpoint_descriptor *desc) | |
988 | { | |
989 | unsigned long flags; | |
990 | struct musb_ep *musb_ep; | |
991 | struct musb_hw_ep *hw_ep; | |
992 | void __iomem *regs; | |
993 | struct musb *musb; | |
994 | void __iomem *mbase; | |
995 | u8 epnum; | |
996 | u16 csr; | |
997 | unsigned tmp; | |
998 | int status = -EINVAL; | |
999 | ||
1000 | if (!ep || !desc) | |
1001 | return -EINVAL; | |
1002 | ||
1003 | musb_ep = to_musb_ep(ep); | |
1004 | hw_ep = musb_ep->hw_ep; | |
1005 | regs = hw_ep->regs; | |
1006 | musb = musb_ep->musb; | |
1007 | mbase = musb->mregs; | |
1008 | epnum = musb_ep->current_epnum; | |
1009 | ||
1010 | spin_lock_irqsave(&musb->lock, flags); | |
1011 | ||
1012 | if (musb_ep->desc) { | |
1013 | status = -EBUSY; | |
1014 | goto fail; | |
1015 | } | |
96bcd090 | 1016 | musb_ep->type = usb_endpoint_type(desc); |
550a7375 FB |
1017 | |
1018 | /* check direction and (later) maxpacket size against endpoint */ | |
96bcd090 | 1019 | if (usb_endpoint_num(desc) != epnum) |
550a7375 FB |
1020 | goto fail; |
1021 | ||
1022 | /* REVISIT this rules out high bandwidth periodic transfers */ | |
1023 | tmp = le16_to_cpu(desc->wMaxPacketSize); | |
f11d893d ML |
1024 | if (tmp & ~0x07ff) { |
1025 | int ok; | |
1026 | ||
1027 | if (usb_endpoint_dir_in(desc)) | |
1028 | ok = musb->hb_iso_tx; | |
1029 | else | |
1030 | ok = musb->hb_iso_rx; | |
1031 | ||
1032 | if (!ok) { | |
5c8a86e1 | 1033 | dev_dbg(musb->controller, "no support for high bandwidth ISO\n"); |
f11d893d ML |
1034 | goto fail; |
1035 | } | |
1036 | musb_ep->hb_mult = (tmp >> 11) & 3; | |
1037 | } else { | |
1038 | musb_ep->hb_mult = 0; | |
1039 | } | |
1040 | ||
1041 | musb_ep->packet_sz = tmp & 0x7ff; | |
1042 | tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1); | |
550a7375 FB |
1043 | |
1044 | /* enable the interrupts for the endpoint, set the endpoint | |
1045 | * packet size (or fail), set the mode, clear the fifo | |
1046 | */ | |
1047 | musb_ep_select(mbase, epnum); | |
96bcd090 | 1048 | if (usb_endpoint_dir_in(desc)) { |
550a7375 FB |
1049 | u16 int_txe = musb_readw(mbase, MUSB_INTRTXE); |
1050 | ||
1051 | if (hw_ep->is_shared_fifo) | |
1052 | musb_ep->is_in = 1; | |
1053 | if (!musb_ep->is_in) | |
1054 | goto fail; | |
f11d893d ML |
1055 | |
1056 | if (tmp > hw_ep->max_packet_sz_tx) { | |
5c8a86e1 | 1057 | dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n"); |
550a7375 | 1058 | goto fail; |
f11d893d | 1059 | } |
550a7375 FB |
1060 | |
1061 | int_txe |= (1 << epnum); | |
1062 | musb_writew(mbase, MUSB_INTRTXE, int_txe); | |
1063 | ||
1064 | /* REVISIT if can_bulk_split(), use by updating "tmp"; | |
1065 | * likewise high bandwidth periodic tx | |
1066 | */ | |
9f445cb2 | 1067 | /* Set TXMAXP with the FIFO size of the endpoint |
31c9909b | 1068 | * to disable double buffering mode. |
9f445cb2 | 1069 | */ |
06624818 FB |
1070 | if (musb->double_buffer_not_ok) |
1071 | musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx); | |
1072 | else | |
1073 | musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz | |
1074 | | (musb_ep->hb_mult << 11)); | |
550a7375 FB |
1075 | |
1076 | csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; | |
1077 | if (musb_readw(regs, MUSB_TXCSR) | |
1078 | & MUSB_TXCSR_FIFONOTEMPTY) | |
1079 | csr |= MUSB_TXCSR_FLUSHFIFO; | |
1080 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
1081 | csr |= MUSB_TXCSR_P_ISO; | |
1082 | ||
1083 | /* set twice in case of double buffering */ | |
1084 | musb_writew(regs, MUSB_TXCSR, csr); | |
1085 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
1086 | musb_writew(regs, MUSB_TXCSR, csr); | |
1087 | ||
1088 | } else { | |
1089 | u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE); | |
1090 | ||
1091 | if (hw_ep->is_shared_fifo) | |
1092 | musb_ep->is_in = 0; | |
1093 | if (musb_ep->is_in) | |
1094 | goto fail; | |
f11d893d ML |
1095 | |
1096 | if (tmp > hw_ep->max_packet_sz_rx) { | |
5c8a86e1 | 1097 | dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n"); |
550a7375 | 1098 | goto fail; |
f11d893d | 1099 | } |
550a7375 FB |
1100 | |
1101 | int_rxe |= (1 << epnum); | |
1102 | musb_writew(mbase, MUSB_INTRRXE, int_rxe); | |
1103 | ||
1104 | /* REVISIT if can_bulk_combine() use by updating "tmp" | |
1105 | * likewise high bandwidth periodic rx | |
1106 | */ | |
9f445cb2 CC |
1107 | /* Set RXMAXP with the FIFO size of the endpoint |
1108 | * to disable double buffering mode. | |
1109 | */ | |
06624818 FB |
1110 | if (musb->double_buffer_not_ok) |
1111 | musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx); | |
1112 | else | |
1113 | musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz | |
1114 | | (musb_ep->hb_mult << 11)); | |
550a7375 FB |
1115 | |
1116 | /* force shared fifo to OUT-only mode */ | |
1117 | if (hw_ep->is_shared_fifo) { | |
1118 | csr = musb_readw(regs, MUSB_TXCSR); | |
1119 | csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); | |
1120 | musb_writew(regs, MUSB_TXCSR, csr); | |
1121 | } | |
1122 | ||
1123 | csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; | |
1124 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
1125 | csr |= MUSB_RXCSR_P_ISO; | |
1126 | else if (musb_ep->type == USB_ENDPOINT_XFER_INT) | |
1127 | csr |= MUSB_RXCSR_DISNYET; | |
1128 | ||
1129 | /* set twice in case of double buffering */ | |
1130 | musb_writew(regs, MUSB_RXCSR, csr); | |
1131 | musb_writew(regs, MUSB_RXCSR, csr); | |
1132 | } | |
1133 | ||
1134 | /* NOTE: all the I/O code _should_ work fine without DMA, in case | |
1135 | * for some reason you run out of channels here. | |
1136 | */ | |
1137 | if (is_dma_capable() && musb->dma_controller) { | |
1138 | struct dma_controller *c = musb->dma_controller; | |
1139 | ||
1140 | musb_ep->dma = c->channel_alloc(c, hw_ep, | |
1141 | (desc->bEndpointAddress & USB_DIR_IN)); | |
1142 | } else | |
1143 | musb_ep->dma = NULL; | |
1144 | ||
1145 | musb_ep->desc = desc; | |
1146 | musb_ep->busy = 0; | |
47e97605 | 1147 | musb_ep->wedged = 0; |
550a7375 FB |
1148 | status = 0; |
1149 | ||
1150 | pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", | |
1151 | musb_driver_name, musb_ep->end_point.name, | |
1152 | ({ char *s; switch (musb_ep->type) { | |
1153 | case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; | |
1154 | case USB_ENDPOINT_XFER_INT: s = "int"; break; | |
1155 | default: s = "iso"; break; | |
1156 | }; s; }), | |
1157 | musb_ep->is_in ? "IN" : "OUT", | |
1158 | musb_ep->dma ? "dma, " : "", | |
1159 | musb_ep->packet_sz); | |
1160 | ||
1161 | schedule_work(&musb->irq_work); | |
1162 | ||
1163 | fail: | |
1164 | spin_unlock_irqrestore(&musb->lock, flags); | |
1165 | return status; | |
1166 | } | |
1167 | ||
1168 | /* | |
1169 | * Disable an endpoint flushing all requests queued. | |
1170 | */ | |
1171 | static int musb_gadget_disable(struct usb_ep *ep) | |
1172 | { | |
1173 | unsigned long flags; | |
1174 | struct musb *musb; | |
1175 | u8 epnum; | |
1176 | struct musb_ep *musb_ep; | |
1177 | void __iomem *epio; | |
1178 | int status = 0; | |
1179 | ||
1180 | musb_ep = to_musb_ep(ep); | |
1181 | musb = musb_ep->musb; | |
1182 | epnum = musb_ep->current_epnum; | |
1183 | epio = musb->endpoints[epnum].regs; | |
1184 | ||
1185 | spin_lock_irqsave(&musb->lock, flags); | |
1186 | musb_ep_select(musb->mregs, epnum); | |
1187 | ||
1188 | /* zero the endpoint sizes */ | |
1189 | if (musb_ep->is_in) { | |
1190 | u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE); | |
1191 | int_txe &= ~(1 << epnum); | |
1192 | musb_writew(musb->mregs, MUSB_INTRTXE, int_txe); | |
1193 | musb_writew(epio, MUSB_TXMAXP, 0); | |
1194 | } else { | |
1195 | u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE); | |
1196 | int_rxe &= ~(1 << epnum); | |
1197 | musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe); | |
1198 | musb_writew(epio, MUSB_RXMAXP, 0); | |
1199 | } | |
1200 | ||
1201 | musb_ep->desc = NULL; | |
1202 | ||
1203 | /* abort all pending DMA and requests */ | |
1204 | nuke(musb_ep, -ESHUTDOWN); | |
1205 | ||
1206 | schedule_work(&musb->irq_work); | |
1207 | ||
1208 | spin_unlock_irqrestore(&(musb->lock), flags); | |
1209 | ||
5c8a86e1 | 1210 | dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name); |
550a7375 FB |
1211 | |
1212 | return status; | |
1213 | } | |
1214 | ||
1215 | /* | |
1216 | * Allocate a request for an endpoint. | |
1217 | * Reused by ep0 code. | |
1218 | */ | |
1219 | struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) | |
1220 | { | |
1221 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
5c8a86e1 | 1222 | struct musb *musb = musb_ep->musb; |
550a7375 FB |
1223 | struct musb_request *request = NULL; |
1224 | ||
1225 | request = kzalloc(sizeof *request, gfp_flags); | |
0607f862 | 1226 | if (!request) { |
5c8a86e1 | 1227 | dev_dbg(musb->controller, "not enough memory\n"); |
0607f862 | 1228 | return NULL; |
550a7375 FB |
1229 | } |
1230 | ||
0607f862 FB |
1231 | request->request.dma = DMA_ADDR_INVALID; |
1232 | request->epnum = musb_ep->current_epnum; | |
1233 | request->ep = musb_ep; | |
1234 | ||
550a7375 FB |
1235 | return &request->request; |
1236 | } | |
1237 | ||
1238 | /* | |
1239 | * Free a request | |
1240 | * Reused by ep0 code. | |
1241 | */ | |
1242 | void musb_free_request(struct usb_ep *ep, struct usb_request *req) | |
1243 | { | |
1244 | kfree(to_musb_request(req)); | |
1245 | } | |
1246 | ||
1247 | static LIST_HEAD(buffers); | |
1248 | ||
1249 | struct free_record { | |
1250 | struct list_head list; | |
1251 | struct device *dev; | |
1252 | unsigned bytes; | |
1253 | dma_addr_t dma; | |
1254 | }; | |
1255 | ||
1256 | /* | |
1257 | * Context: controller locked, IRQs blocked. | |
1258 | */ | |
a666e3e6 | 1259 | void musb_ep_restart(struct musb *musb, struct musb_request *req) |
550a7375 | 1260 | { |
5c8a86e1 | 1261 | dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n", |
550a7375 FB |
1262 | req->tx ? "TX/IN" : "RX/OUT", |
1263 | &req->request, req->request.length, req->epnum); | |
1264 | ||
1265 | musb_ep_select(musb->mregs, req->epnum); | |
1266 | if (req->tx) | |
1267 | txstate(musb, req); | |
1268 | else | |
1269 | rxstate(musb, req); | |
1270 | } | |
1271 | ||
1272 | static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, | |
1273 | gfp_t gfp_flags) | |
1274 | { | |
1275 | struct musb_ep *musb_ep; | |
1276 | struct musb_request *request; | |
1277 | struct musb *musb; | |
1278 | int status = 0; | |
1279 | unsigned long lockflags; | |
1280 | ||
1281 | if (!ep || !req) | |
1282 | return -EINVAL; | |
1283 | if (!req->buf) | |
1284 | return -ENODATA; | |
1285 | ||
1286 | musb_ep = to_musb_ep(ep); | |
1287 | musb = musb_ep->musb; | |
1288 | ||
1289 | request = to_musb_request(req); | |
1290 | request->musb = musb; | |
1291 | ||
1292 | if (request->ep != musb_ep) | |
1293 | return -EINVAL; | |
1294 | ||
5c8a86e1 | 1295 | dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req); |
550a7375 FB |
1296 | |
1297 | /* request is mine now... */ | |
1298 | request->request.actual = 0; | |
1299 | request->request.status = -EINPROGRESS; | |
1300 | request->epnum = musb_ep->current_epnum; | |
1301 | request->tx = musb_ep->is_in; | |
1302 | ||
c65bfa62 | 1303 | map_dma_buffer(request, musb, musb_ep); |
550a7375 FB |
1304 | |
1305 | spin_lock_irqsave(&musb->lock, lockflags); | |
1306 | ||
1307 | /* don't queue if the ep is down */ | |
1308 | if (!musb_ep->desc) { | |
5c8a86e1 | 1309 | dev_dbg(musb->controller, "req %p queued to %s while ep %s\n", |
550a7375 FB |
1310 | req, ep->name, "disabled"); |
1311 | status = -ESHUTDOWN; | |
1312 | goto cleanup; | |
1313 | } | |
1314 | ||
1315 | /* add request to the list */ | |
ad1adb89 | 1316 | list_add_tail(&request->list, &musb_ep->req_list); |
550a7375 FB |
1317 | |
1318 | /* it this is the head of the queue, start i/o ... */ | |
ad1adb89 | 1319 | if (!musb_ep->busy && &request->list == musb_ep->req_list.next) |
550a7375 FB |
1320 | musb_ep_restart(musb, request); |
1321 | ||
1322 | cleanup: | |
1323 | spin_unlock_irqrestore(&musb->lock, lockflags); | |
1324 | return status; | |
1325 | } | |
1326 | ||
1327 | static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) | |
1328 | { | |
1329 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
4cbbf084 FB |
1330 | struct musb_request *req = to_musb_request(request); |
1331 | struct musb_request *r; | |
550a7375 FB |
1332 | unsigned long flags; |
1333 | int status = 0; | |
1334 | struct musb *musb = musb_ep->musb; | |
1335 | ||
1336 | if (!ep || !request || to_musb_request(request)->ep != musb_ep) | |
1337 | return -EINVAL; | |
1338 | ||
1339 | spin_lock_irqsave(&musb->lock, flags); | |
1340 | ||
1341 | list_for_each_entry(r, &musb_ep->req_list, list) { | |
4cbbf084 | 1342 | if (r == req) |
550a7375 FB |
1343 | break; |
1344 | } | |
4cbbf084 | 1345 | if (r != req) { |
5c8a86e1 | 1346 | dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name); |
550a7375 FB |
1347 | status = -EINVAL; |
1348 | goto done; | |
1349 | } | |
1350 | ||
1351 | /* if the hardware doesn't have the request, easy ... */ | |
3d5ad13e | 1352 | if (musb_ep->req_list.next != &req->list || musb_ep->busy) |
550a7375 FB |
1353 | musb_g_giveback(musb_ep, request, -ECONNRESET); |
1354 | ||
1355 | /* ... else abort the dma transfer ... */ | |
1356 | else if (is_dma_capable() && musb_ep->dma) { | |
1357 | struct dma_controller *c = musb->dma_controller; | |
1358 | ||
1359 | musb_ep_select(musb->mregs, musb_ep->current_epnum); | |
1360 | if (c->channel_abort) | |
1361 | status = c->channel_abort(musb_ep->dma); | |
1362 | else | |
1363 | status = -EBUSY; | |
1364 | if (status == 0) | |
1365 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1366 | } else { | |
1367 | /* NOTE: by sticking to easily tested hardware/driver states, | |
1368 | * we leave counting of in-flight packets imprecise. | |
1369 | */ | |
1370 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1371 | } | |
1372 | ||
1373 | done: | |
1374 | spin_unlock_irqrestore(&musb->lock, flags); | |
1375 | return status; | |
1376 | } | |
1377 | ||
1378 | /* | |
1379 | * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any | |
1380 | * data but will queue requests. | |
1381 | * | |
1382 | * exported to ep0 code | |
1383 | */ | |
1b6c3b0f | 1384 | static int musb_gadget_set_halt(struct usb_ep *ep, int value) |
550a7375 FB |
1385 | { |
1386 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1387 | u8 epnum = musb_ep->current_epnum; | |
1388 | struct musb *musb = musb_ep->musb; | |
1389 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1390 | void __iomem *mbase; | |
1391 | unsigned long flags; | |
1392 | u16 csr; | |
cea83241 | 1393 | struct musb_request *request; |
550a7375 FB |
1394 | int status = 0; |
1395 | ||
1396 | if (!ep) | |
1397 | return -EINVAL; | |
1398 | mbase = musb->mregs; | |
1399 | ||
1400 | spin_lock_irqsave(&musb->lock, flags); | |
1401 | ||
1402 | if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { | |
1403 | status = -EINVAL; | |
1404 | goto done; | |
1405 | } | |
1406 | ||
1407 | musb_ep_select(mbase, epnum); | |
1408 | ||
ad1adb89 | 1409 | request = next_request(musb_ep); |
cea83241 SS |
1410 | if (value) { |
1411 | if (request) { | |
5c8a86e1 | 1412 | dev_dbg(musb->controller, "request in progress, cannot halt %s\n", |
cea83241 SS |
1413 | ep->name); |
1414 | status = -EAGAIN; | |
1415 | goto done; | |
1416 | } | |
1417 | /* Cannot portably stall with non-empty FIFO */ | |
1418 | if (musb_ep->is_in) { | |
1419 | csr = musb_readw(epio, MUSB_TXCSR); | |
1420 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
5c8a86e1 | 1421 | dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name); |
cea83241 SS |
1422 | status = -EAGAIN; |
1423 | goto done; | |
1424 | } | |
550a7375 | 1425 | } |
47e97605 SS |
1426 | } else |
1427 | musb_ep->wedged = 0; | |
550a7375 FB |
1428 | |
1429 | /* set/clear the stall and toggle bits */ | |
5c8a86e1 | 1430 | dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear"); |
550a7375 FB |
1431 | if (musb_ep->is_in) { |
1432 | csr = musb_readw(epio, MUSB_TXCSR); | |
550a7375 FB |
1433 | csr |= MUSB_TXCSR_P_WZC_BITS |
1434 | | MUSB_TXCSR_CLRDATATOG; | |
1435 | if (value) | |
1436 | csr |= MUSB_TXCSR_P_SENDSTALL; | |
1437 | else | |
1438 | csr &= ~(MUSB_TXCSR_P_SENDSTALL | |
1439 | | MUSB_TXCSR_P_SENTSTALL); | |
1440 | csr &= ~MUSB_TXCSR_TXPKTRDY; | |
1441 | musb_writew(epio, MUSB_TXCSR, csr); | |
1442 | } else { | |
1443 | csr = musb_readw(epio, MUSB_RXCSR); | |
1444 | csr |= MUSB_RXCSR_P_WZC_BITS | |
1445 | | MUSB_RXCSR_FLUSHFIFO | |
1446 | | MUSB_RXCSR_CLRDATATOG; | |
1447 | if (value) | |
1448 | csr |= MUSB_RXCSR_P_SENDSTALL; | |
1449 | else | |
1450 | csr &= ~(MUSB_RXCSR_P_SENDSTALL | |
1451 | | MUSB_RXCSR_P_SENTSTALL); | |
1452 | musb_writew(epio, MUSB_RXCSR, csr); | |
1453 | } | |
1454 | ||
550a7375 FB |
1455 | /* maybe start the first request in the queue */ |
1456 | if (!musb_ep->busy && !value && request) { | |
5c8a86e1 | 1457 | dev_dbg(musb->controller, "restarting the request\n"); |
550a7375 FB |
1458 | musb_ep_restart(musb, request); |
1459 | } | |
1460 | ||
cea83241 | 1461 | done: |
550a7375 FB |
1462 | spin_unlock_irqrestore(&musb->lock, flags); |
1463 | return status; | |
1464 | } | |
1465 | ||
47e97605 SS |
1466 | /* |
1467 | * Sets the halt feature with the clear requests ignored | |
1468 | */ | |
1b6c3b0f | 1469 | static int musb_gadget_set_wedge(struct usb_ep *ep) |
47e97605 SS |
1470 | { |
1471 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1472 | ||
1473 | if (!ep) | |
1474 | return -EINVAL; | |
1475 | ||
1476 | musb_ep->wedged = 1; | |
1477 | ||
1478 | return usb_ep_set_halt(ep); | |
1479 | } | |
1480 | ||
550a7375 FB |
1481 | static int musb_gadget_fifo_status(struct usb_ep *ep) |
1482 | { | |
1483 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1484 | void __iomem *epio = musb_ep->hw_ep->regs; | |
1485 | int retval = -EINVAL; | |
1486 | ||
1487 | if (musb_ep->desc && !musb_ep->is_in) { | |
1488 | struct musb *musb = musb_ep->musb; | |
1489 | int epnum = musb_ep->current_epnum; | |
1490 | void __iomem *mbase = musb->mregs; | |
1491 | unsigned long flags; | |
1492 | ||
1493 | spin_lock_irqsave(&musb->lock, flags); | |
1494 | ||
1495 | musb_ep_select(mbase, epnum); | |
1496 | /* FIXME return zero unless RXPKTRDY is set */ | |
1497 | retval = musb_readw(epio, MUSB_RXCOUNT); | |
1498 | ||
1499 | spin_unlock_irqrestore(&musb->lock, flags); | |
1500 | } | |
1501 | return retval; | |
1502 | } | |
1503 | ||
1504 | static void musb_gadget_fifo_flush(struct usb_ep *ep) | |
1505 | { | |
1506 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1507 | struct musb *musb = musb_ep->musb; | |
1508 | u8 epnum = musb_ep->current_epnum; | |
1509 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1510 | void __iomem *mbase; | |
1511 | unsigned long flags; | |
1512 | u16 csr, int_txe; | |
1513 | ||
1514 | mbase = musb->mregs; | |
1515 | ||
1516 | spin_lock_irqsave(&musb->lock, flags); | |
1517 | musb_ep_select(mbase, (u8) epnum); | |
1518 | ||
1519 | /* disable interrupts */ | |
1520 | int_txe = musb_readw(mbase, MUSB_INTRTXE); | |
1521 | musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); | |
1522 | ||
1523 | if (musb_ep->is_in) { | |
1524 | csr = musb_readw(epio, MUSB_TXCSR); | |
1525 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
1526 | csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; | |
1527 | musb_writew(epio, MUSB_TXCSR, csr); | |
1528 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
1529 | musb_writew(epio, MUSB_TXCSR, csr); | |
1530 | } | |
1531 | } else { | |
1532 | csr = musb_readw(epio, MUSB_RXCSR); | |
1533 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; | |
1534 | musb_writew(epio, MUSB_RXCSR, csr); | |
1535 | musb_writew(epio, MUSB_RXCSR, csr); | |
1536 | } | |
1537 | ||
1538 | /* re-enable interrupt */ | |
1539 | musb_writew(mbase, MUSB_INTRTXE, int_txe); | |
1540 | spin_unlock_irqrestore(&musb->lock, flags); | |
1541 | } | |
1542 | ||
1543 | static const struct usb_ep_ops musb_ep_ops = { | |
1544 | .enable = musb_gadget_enable, | |
1545 | .disable = musb_gadget_disable, | |
1546 | .alloc_request = musb_alloc_request, | |
1547 | .free_request = musb_free_request, | |
1548 | .queue = musb_gadget_queue, | |
1549 | .dequeue = musb_gadget_dequeue, | |
1550 | .set_halt = musb_gadget_set_halt, | |
47e97605 | 1551 | .set_wedge = musb_gadget_set_wedge, |
550a7375 FB |
1552 | .fifo_status = musb_gadget_fifo_status, |
1553 | .fifo_flush = musb_gadget_fifo_flush | |
1554 | }; | |
1555 | ||
1556 | /* ----------------------------------------------------------------------- */ | |
1557 | ||
1558 | static int musb_gadget_get_frame(struct usb_gadget *gadget) | |
1559 | { | |
1560 | struct musb *musb = gadget_to_musb(gadget); | |
1561 | ||
1562 | return (int)musb_readw(musb->mregs, MUSB_FRAME); | |
1563 | } | |
1564 | ||
1565 | static int musb_gadget_wakeup(struct usb_gadget *gadget) | |
1566 | { | |
1567 | struct musb *musb = gadget_to_musb(gadget); | |
1568 | void __iomem *mregs = musb->mregs; | |
1569 | unsigned long flags; | |
1570 | int status = -EINVAL; | |
1571 | u8 power, devctl; | |
1572 | int retries; | |
1573 | ||
1574 | spin_lock_irqsave(&musb->lock, flags); | |
1575 | ||
84e250ff | 1576 | switch (musb->xceiv->state) { |
550a7375 FB |
1577 | case OTG_STATE_B_PERIPHERAL: |
1578 | /* NOTE: OTG state machine doesn't include B_SUSPENDED; | |
1579 | * that's part of the standard usb 1.1 state machine, and | |
1580 | * doesn't affect OTG transitions. | |
1581 | */ | |
1582 | if (musb->may_wakeup && musb->is_suspended) | |
1583 | break; | |
1584 | goto done; | |
1585 | case OTG_STATE_B_IDLE: | |
1586 | /* Start SRP ... OTG not required. */ | |
1587 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
5c8a86e1 | 1588 | dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl); |
550a7375 FB |
1589 | devctl |= MUSB_DEVCTL_SESSION; |
1590 | musb_writeb(mregs, MUSB_DEVCTL, devctl); | |
1591 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1592 | retries = 100; | |
1593 | while (!(devctl & MUSB_DEVCTL_SESSION)) { | |
1594 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1595 | if (retries-- < 1) | |
1596 | break; | |
1597 | } | |
1598 | retries = 10000; | |
1599 | while (devctl & MUSB_DEVCTL_SESSION) { | |
1600 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1601 | if (retries-- < 1) | |
1602 | break; | |
1603 | } | |
1604 | ||
8620543e HH |
1605 | spin_unlock_irqrestore(&musb->lock, flags); |
1606 | otg_start_srp(musb->xceiv); | |
1607 | spin_lock_irqsave(&musb->lock, flags); | |
1608 | ||
550a7375 FB |
1609 | /* Block idling for at least 1s */ |
1610 | musb_platform_try_idle(musb, | |
1611 | jiffies + msecs_to_jiffies(1 * HZ)); | |
1612 | ||
1613 | status = 0; | |
1614 | goto done; | |
1615 | default: | |
5c8a86e1 | 1616 | dev_dbg(musb->controller, "Unhandled wake: %s\n", |
3df00453 | 1617 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
1618 | goto done; |
1619 | } | |
1620 | ||
1621 | status = 0; | |
1622 | ||
1623 | power = musb_readb(mregs, MUSB_POWER); | |
1624 | power |= MUSB_POWER_RESUME; | |
1625 | musb_writeb(mregs, MUSB_POWER, power); | |
5c8a86e1 | 1626 | dev_dbg(musb->controller, "issue wakeup\n"); |
550a7375 FB |
1627 | |
1628 | /* FIXME do this next chunk in a timer callback, no udelay */ | |
1629 | mdelay(2); | |
1630 | ||
1631 | power = musb_readb(mregs, MUSB_POWER); | |
1632 | power &= ~MUSB_POWER_RESUME; | |
1633 | musb_writeb(mregs, MUSB_POWER, power); | |
1634 | done: | |
1635 | spin_unlock_irqrestore(&musb->lock, flags); | |
1636 | return status; | |
1637 | } | |
1638 | ||
1639 | static int | |
1640 | musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) | |
1641 | { | |
1642 | struct musb *musb = gadget_to_musb(gadget); | |
1643 | ||
1644 | musb->is_self_powered = !!is_selfpowered; | |
1645 | return 0; | |
1646 | } | |
1647 | ||
1648 | static void musb_pullup(struct musb *musb, int is_on) | |
1649 | { | |
1650 | u8 power; | |
1651 | ||
1652 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1653 | if (is_on) | |
1654 | power |= MUSB_POWER_SOFTCONN; | |
1655 | else | |
1656 | power &= ~MUSB_POWER_SOFTCONN; | |
1657 | ||
1658 | /* FIXME if on, HdrcStart; if off, HdrcStop */ | |
1659 | ||
5c8a86e1 | 1660 | dev_dbg(musb->controller, "gadget %s D+ pullup %s\n", |
550a7375 FB |
1661 | musb->gadget_driver->function, is_on ? "on" : "off"); |
1662 | musb_writeb(musb->mregs, MUSB_POWER, power); | |
1663 | } | |
1664 | ||
1665 | #if 0 | |
1666 | static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) | |
1667 | { | |
5c8a86e1 | 1668 | dev_dbg(musb->controller, "<= %s =>\n", __func__); |
550a7375 FB |
1669 | |
1670 | /* | |
1671 | * FIXME iff driver's softconnect flag is set (as it is during probe, | |
1672 | * though that can clear it), just musb_pullup(). | |
1673 | */ | |
1674 | ||
1675 | return -EINVAL; | |
1676 | } | |
1677 | #endif | |
1678 | ||
1679 | static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1680 | { | |
1681 | struct musb *musb = gadget_to_musb(gadget); | |
1682 | ||
84e250ff | 1683 | if (!musb->xceiv->set_power) |
550a7375 | 1684 | return -EOPNOTSUPP; |
84e250ff | 1685 | return otg_set_power(musb->xceiv, mA); |
550a7375 FB |
1686 | } |
1687 | ||
1688 | static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) | |
1689 | { | |
1690 | struct musb *musb = gadget_to_musb(gadget); | |
1691 | unsigned long flags; | |
1692 | ||
1693 | is_on = !!is_on; | |
1694 | ||
1695 | /* NOTE: this assumes we are sensing vbus; we'd rather | |
1696 | * not pullup unless the B-session is active. | |
1697 | */ | |
1698 | spin_lock_irqsave(&musb->lock, flags); | |
1699 | if (is_on != musb->softconnect) { | |
1700 | musb->softconnect = is_on; | |
1701 | musb_pullup(musb, is_on); | |
1702 | } | |
1703 | spin_unlock_irqrestore(&musb->lock, flags); | |
1704 | return 0; | |
1705 | } | |
1706 | ||
0f91349b SAS |
1707 | static int musb_gadget_start(struct usb_gadget_driver *driver, |
1708 | int (*bind)(struct usb_gadget *)); | |
1709 | static int musb_gadget_stop(struct usb_gadget_driver *driver); | |
1710 | ||
550a7375 FB |
1711 | static const struct usb_gadget_ops musb_gadget_operations = { |
1712 | .get_frame = musb_gadget_get_frame, | |
1713 | .wakeup = musb_gadget_wakeup, | |
1714 | .set_selfpowered = musb_gadget_set_self_powered, | |
1715 | /* .vbus_session = musb_gadget_vbus_session, */ | |
1716 | .vbus_draw = musb_gadget_vbus_draw, | |
1717 | .pullup = musb_gadget_pullup, | |
0f91349b SAS |
1718 | .start = musb_gadget_start, |
1719 | .stop = musb_gadget_stop, | |
550a7375 FB |
1720 | }; |
1721 | ||
1722 | /* ----------------------------------------------------------------------- */ | |
1723 | ||
1724 | /* Registration */ | |
1725 | ||
1726 | /* Only this registration code "knows" the rule (from USB standards) | |
1727 | * about there being only one external upstream port. It assumes | |
1728 | * all peripheral ports are external... | |
1729 | */ | |
1730 | static struct musb *the_gadget; | |
1731 | ||
1732 | static void musb_gadget_release(struct device *dev) | |
1733 | { | |
1734 | /* kref_put(WHAT) */ | |
1735 | dev_dbg(dev, "%s\n", __func__); | |
1736 | } | |
1737 | ||
1738 | ||
1739 | static void __init | |
1740 | init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) | |
1741 | { | |
1742 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
1743 | ||
1744 | memset(ep, 0, sizeof *ep); | |
1745 | ||
1746 | ep->current_epnum = epnum; | |
1747 | ep->musb = musb; | |
1748 | ep->hw_ep = hw_ep; | |
1749 | ep->is_in = is_in; | |
1750 | ||
1751 | INIT_LIST_HEAD(&ep->req_list); | |
1752 | ||
1753 | sprintf(ep->name, "ep%d%s", epnum, | |
1754 | (!epnum || hw_ep->is_shared_fifo) ? "" : ( | |
1755 | is_in ? "in" : "out")); | |
1756 | ep->end_point.name = ep->name; | |
1757 | INIT_LIST_HEAD(&ep->end_point.ep_list); | |
1758 | if (!epnum) { | |
1759 | ep->end_point.maxpacket = 64; | |
1760 | ep->end_point.ops = &musb_g_ep0_ops; | |
1761 | musb->g.ep0 = &ep->end_point; | |
1762 | } else { | |
1763 | if (is_in) | |
1764 | ep->end_point.maxpacket = hw_ep->max_packet_sz_tx; | |
1765 | else | |
1766 | ep->end_point.maxpacket = hw_ep->max_packet_sz_rx; | |
1767 | ep->end_point.ops = &musb_ep_ops; | |
1768 | list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); | |
1769 | } | |
1770 | } | |
1771 | ||
1772 | /* | |
1773 | * Initialize the endpoints exposed to peripheral drivers, with backlinks | |
1774 | * to the rest of the driver state. | |
1775 | */ | |
1776 | static inline void __init musb_g_init_endpoints(struct musb *musb) | |
1777 | { | |
1778 | u8 epnum; | |
1779 | struct musb_hw_ep *hw_ep; | |
1780 | unsigned count = 0; | |
1781 | ||
b595076a | 1782 | /* initialize endpoint list just once */ |
550a7375 FB |
1783 | INIT_LIST_HEAD(&(musb->g.ep_list)); |
1784 | ||
1785 | for (epnum = 0, hw_ep = musb->endpoints; | |
1786 | epnum < musb->nr_endpoints; | |
1787 | epnum++, hw_ep++) { | |
1788 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1789 | init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); | |
1790 | count++; | |
1791 | } else { | |
1792 | if (hw_ep->max_packet_sz_tx) { | |
1793 | init_peripheral_ep(musb, &hw_ep->ep_in, | |
1794 | epnum, 1); | |
1795 | count++; | |
1796 | } | |
1797 | if (hw_ep->max_packet_sz_rx) { | |
1798 | init_peripheral_ep(musb, &hw_ep->ep_out, | |
1799 | epnum, 0); | |
1800 | count++; | |
1801 | } | |
1802 | } | |
1803 | } | |
1804 | } | |
1805 | ||
1806 | /* called once during driver setup to initialize and link into | |
1807 | * the driver model; memory is zeroed. | |
1808 | */ | |
1809 | int __init musb_gadget_setup(struct musb *musb) | |
1810 | { | |
1811 | int status; | |
1812 | ||
1813 | /* REVISIT minor race: if (erroneously) setting up two | |
1814 | * musb peripherals at the same time, only the bus lock | |
1815 | * is probably held. | |
1816 | */ | |
1817 | if (the_gadget) | |
1818 | return -EBUSY; | |
1819 | the_gadget = musb; | |
1820 | ||
1821 | musb->g.ops = &musb_gadget_operations; | |
1822 | musb->g.is_dualspeed = 1; | |
1823 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1824 | ||
1825 | /* this "gadget" abstracts/virtualizes the controller */ | |
427c4f33 | 1826 | dev_set_name(&musb->g.dev, "gadget"); |
550a7375 FB |
1827 | musb->g.dev.parent = musb->controller; |
1828 | musb->g.dev.dma_mask = musb->controller->dma_mask; | |
1829 | musb->g.dev.release = musb_gadget_release; | |
1830 | musb->g.name = musb_driver_name; | |
1831 | ||
1832 | if (is_otg_enabled(musb)) | |
1833 | musb->g.is_otg = 1; | |
1834 | ||
1835 | musb_g_init_endpoints(musb); | |
1836 | ||
1837 | musb->is_active = 0; | |
1838 | musb_platform_try_idle(musb, 0); | |
1839 | ||
1840 | status = device_register(&musb->g.dev); | |
e2c34045 RR |
1841 | if (status != 0) { |
1842 | put_device(&musb->g.dev); | |
550a7375 | 1843 | the_gadget = NULL; |
0f91349b | 1844 | return status; |
e2c34045 | 1845 | } |
0f91349b SAS |
1846 | status = usb_add_gadget_udc(musb->controller, &musb->g); |
1847 | if (status) | |
1848 | goto err; | |
1849 | ||
1850 | return 0; | |
1851 | err: | |
1852 | device_unregister(&musb->g.dev); | |
1853 | the_gadget = NULL; | |
550a7375 FB |
1854 | return status; |
1855 | } | |
1856 | ||
1857 | void musb_gadget_cleanup(struct musb *musb) | |
1858 | { | |
1859 | if (musb != the_gadget) | |
1860 | return; | |
1861 | ||
0f91349b | 1862 | usb_del_gadget_udc(&musb->g); |
550a7375 FB |
1863 | device_unregister(&musb->g.dev); |
1864 | the_gadget = NULL; | |
1865 | } | |
1866 | ||
1867 | /* | |
1868 | * Register the gadget driver. Used by gadget drivers when | |
1869 | * registering themselves with the controller. | |
1870 | * | |
1871 | * -EINVAL something went wrong (not driver) | |
1872 | * -EBUSY another gadget is already using the controller | |
b595076a | 1873 | * -ENOMEM no memory to perform the operation |
550a7375 FB |
1874 | * |
1875 | * @param driver the gadget driver | |
b0fca50f | 1876 | * @param bind the driver's bind function |
550a7375 FB |
1877 | * @return <0 if error, 0 if everything is fine |
1878 | */ | |
0f91349b | 1879 | static int musb_gadget_start(struct usb_gadget_driver *driver, |
b0fca50f | 1880 | int (*bind)(struct usb_gadget *)) |
550a7375 | 1881 | { |
63eed2b5 FB |
1882 | struct musb *musb = the_gadget; |
1883 | unsigned long flags; | |
1884 | int retval = -EINVAL; | |
550a7375 FB |
1885 | |
1886 | if (!driver | |
1887 | || driver->speed != USB_SPEED_HIGH | |
b0fca50f | 1888 | || !bind || !driver->setup) |
63eed2b5 | 1889 | goto err0; |
550a7375 FB |
1890 | |
1891 | /* driver must be initialized to support peripheral mode */ | |
08e6c972 | 1892 | if (!musb) { |
5c8a86e1 | 1893 | dev_dbg(musb->controller, "no dev??\n"); |
63eed2b5 FB |
1894 | retval = -ENODEV; |
1895 | goto err0; | |
550a7375 FB |
1896 | } |
1897 | ||
7acc6197 HH |
1898 | pm_runtime_get_sync(musb->controller); |
1899 | ||
5c8a86e1 | 1900 | dev_dbg(musb->controller, "registering driver %s\n", driver->function); |
550a7375 FB |
1901 | |
1902 | if (musb->gadget_driver) { | |
5c8a86e1 | 1903 | dev_dbg(musb->controller, "%s is already bound to %s\n", |
550a7375 FB |
1904 | musb_driver_name, |
1905 | musb->gadget_driver->driver.name); | |
1906 | retval = -EBUSY; | |
63eed2b5 | 1907 | goto err0; |
550a7375 FB |
1908 | } |
1909 | ||
63eed2b5 FB |
1910 | spin_lock_irqsave(&musb->lock, flags); |
1911 | musb->gadget_driver = driver; | |
1912 | musb->g.dev.driver = &driver->driver; | |
1913 | driver->driver.bus = NULL; | |
1914 | musb->softconnect = 1; | |
550a7375 FB |
1915 | spin_unlock_irqrestore(&musb->lock, flags); |
1916 | ||
63eed2b5 FB |
1917 | retval = bind(&musb->g); |
1918 | if (retval) { | |
5c8a86e1 | 1919 | dev_dbg(musb->controller, "bind to driver %s failed --> %d\n", |
63eed2b5 FB |
1920 | driver->driver.name, retval); |
1921 | goto err1; | |
1922 | } | |
550a7375 | 1923 | |
63eed2b5 | 1924 | spin_lock_irqsave(&musb->lock, flags); |
550a7375 | 1925 | |
63eed2b5 FB |
1926 | otg_set_peripheral(musb->xceiv, &musb->g); |
1927 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
1928 | musb->is_active = 1; | |
550a7375 | 1929 | |
63eed2b5 FB |
1930 | /* |
1931 | * FIXME this ignores the softconnect flag. Drivers are | |
1932 | * allowed hold the peripheral inactive until for example | |
1933 | * userspace hooks up printer hardware or DSP codecs, so | |
1934 | * hosts only see fully functional devices. | |
1935 | */ | |
550a7375 | 1936 | |
63eed2b5 FB |
1937 | if (!is_otg_enabled(musb)) |
1938 | musb_start(musb); | |
550a7375 | 1939 | |
63eed2b5 | 1940 | otg_set_peripheral(musb->xceiv, &musb->g); |
84e250ff | 1941 | |
63eed2b5 | 1942 | spin_unlock_irqrestore(&musb->lock, flags); |
550a7375 | 1943 | |
63eed2b5 FB |
1944 | if (is_otg_enabled(musb)) { |
1945 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
07a8cdd2 | 1946 | |
5c8a86e1 | 1947 | dev_dbg(musb->controller, "OTG startup...\n"); |
550a7375 | 1948 | |
63eed2b5 FB |
1949 | /* REVISIT: funcall to other code, which also |
1950 | * handles power budgeting ... this way also | |
1951 | * ensures HdrcStart is indirectly called. | |
1952 | */ | |
1953 | retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); | |
1954 | if (retval < 0) { | |
5c8a86e1 | 1955 | dev_dbg(musb->controller, "add_hcd failed, %d\n", retval); |
63eed2b5 | 1956 | goto err2; |
550a7375 | 1957 | } |
63eed2b5 | 1958 | |
5f1e8ce7 HH |
1959 | if ((musb->xceiv->last_event == USB_EVENT_ID) |
1960 | && musb->xceiv->set_vbus) | |
1961 | otg_set_vbus(musb->xceiv, 1); | |
1962 | ||
63eed2b5 | 1963 | hcd->self.uses_pio_for_control = 1; |
550a7375 | 1964 | } |
cdefce16 JN |
1965 | if (musb->xceiv->last_event == USB_EVENT_NONE) |
1966 | pm_runtime_put(musb->controller); | |
550a7375 | 1967 | |
63eed2b5 FB |
1968 | return 0; |
1969 | ||
1970 | err2: | |
1971 | if (!is_otg_enabled(musb)) | |
1972 | musb_stop(musb); | |
1973 | ||
1974 | err1: | |
1975 | musb->gadget_driver = NULL; | |
1976 | musb->g.dev.driver = NULL; | |
1977 | ||
1978 | err0: | |
550a7375 FB |
1979 | return retval; |
1980 | } | |
550a7375 FB |
1981 | |
1982 | static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver) | |
1983 | { | |
1984 | int i; | |
1985 | struct musb_hw_ep *hw_ep; | |
1986 | ||
1987 | /* don't disconnect if it's not connected */ | |
1988 | if (musb->g.speed == USB_SPEED_UNKNOWN) | |
1989 | driver = NULL; | |
1990 | else | |
1991 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1992 | ||
1993 | /* deactivate the hardware */ | |
1994 | if (musb->softconnect) { | |
1995 | musb->softconnect = 0; | |
1996 | musb_pullup(musb, 0); | |
1997 | } | |
1998 | musb_stop(musb); | |
1999 | ||
2000 | /* killing any outstanding requests will quiesce the driver; | |
2001 | * then report disconnect | |
2002 | */ | |
2003 | if (driver) { | |
2004 | for (i = 0, hw_ep = musb->endpoints; | |
2005 | i < musb->nr_endpoints; | |
2006 | i++, hw_ep++) { | |
2007 | musb_ep_select(musb->mregs, i); | |
2008 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
2009 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
2010 | } else { | |
2011 | if (hw_ep->max_packet_sz_tx) | |
2012 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
2013 | if (hw_ep->max_packet_sz_rx) | |
2014 | nuke(&hw_ep->ep_out, -ESHUTDOWN); | |
2015 | } | |
2016 | } | |
2017 | ||
2018 | spin_unlock(&musb->lock); | |
2019 | driver->disconnect(&musb->g); | |
2020 | spin_lock(&musb->lock); | |
2021 | } | |
2022 | } | |
2023 | ||
2024 | /* | |
2025 | * Unregister the gadget driver. Used by gadget drivers when | |
2026 | * unregistering themselves from the controller. | |
2027 | * | |
2028 | * @param driver the gadget driver to unregister | |
2029 | */ | |
0f91349b | 2030 | static int musb_gadget_stop(struct usb_gadget_driver *driver) |
550a7375 | 2031 | { |
550a7375 | 2032 | struct musb *musb = the_gadget; |
63eed2b5 | 2033 | unsigned long flags; |
550a7375 FB |
2034 | |
2035 | if (!driver || !driver->unbind || !musb) | |
2036 | return -EINVAL; | |
2037 | ||
63eed2b5 FB |
2038 | if (!musb->gadget_driver) |
2039 | return -EINVAL; | |
2040 | ||
7acc6197 HH |
2041 | if (musb->xceiv->last_event == USB_EVENT_NONE) |
2042 | pm_runtime_get_sync(musb->controller); | |
2043 | ||
63eed2b5 FB |
2044 | /* |
2045 | * REVISIT always use otg_set_peripheral() here too; | |
550a7375 FB |
2046 | * this needs to shut down the OTG engine. |
2047 | */ | |
2048 | ||
2049 | spin_lock_irqsave(&musb->lock, flags); | |
2050 | ||
2051 | #ifdef CONFIG_USB_MUSB_OTG | |
2052 | musb_hnp_stop(musb); | |
2053 | #endif | |
2054 | ||
63eed2b5 | 2055 | (void) musb_gadget_vbus_draw(&musb->g, 0); |
550a7375 | 2056 | |
63eed2b5 FB |
2057 | musb->xceiv->state = OTG_STATE_UNDEFINED; |
2058 | stop_activity(musb, driver); | |
2059 | otg_set_peripheral(musb->xceiv, NULL); | |
550a7375 | 2060 | |
5c8a86e1 | 2061 | dev_dbg(musb->controller, "unregistering driver %s\n", driver->function); |
550a7375 | 2062 | |
63eed2b5 FB |
2063 | spin_unlock_irqrestore(&musb->lock, flags); |
2064 | driver->unbind(&musb->g); | |
2065 | spin_lock_irqsave(&musb->lock, flags); | |
550a7375 | 2066 | |
63eed2b5 FB |
2067 | musb->gadget_driver = NULL; |
2068 | musb->g.dev.driver = NULL; | |
550a7375 | 2069 | |
63eed2b5 FB |
2070 | musb->is_active = 0; |
2071 | musb_platform_try_idle(musb, 0); | |
550a7375 FB |
2072 | spin_unlock_irqrestore(&musb->lock, flags); |
2073 | ||
63eed2b5 | 2074 | if (is_otg_enabled(musb)) { |
550a7375 FB |
2075 | usb_remove_hcd(musb_to_hcd(musb)); |
2076 | /* FIXME we need to be able to register another | |
2077 | * gadget driver here and have everything work; | |
2078 | * that currently misbehaves. | |
2079 | */ | |
2080 | } | |
2081 | ||
63eed2b5 FB |
2082 | if (!is_otg_enabled(musb)) |
2083 | musb_stop(musb); | |
2084 | ||
7acc6197 HH |
2085 | pm_runtime_put(musb->controller); |
2086 | ||
63eed2b5 | 2087 | return 0; |
550a7375 | 2088 | } |
550a7375 FB |
2089 | |
2090 | /* ----------------------------------------------------------------------- */ | |
2091 | ||
2092 | /* lifecycle operations called through plat_uds.c */ | |
2093 | ||
2094 | void musb_g_resume(struct musb *musb) | |
2095 | { | |
2096 | musb->is_suspended = 0; | |
84e250ff | 2097 | switch (musb->xceiv->state) { |
550a7375 FB |
2098 | case OTG_STATE_B_IDLE: |
2099 | break; | |
2100 | case OTG_STATE_B_WAIT_ACON: | |
2101 | case OTG_STATE_B_PERIPHERAL: | |
2102 | musb->is_active = 1; | |
2103 | if (musb->gadget_driver && musb->gadget_driver->resume) { | |
2104 | spin_unlock(&musb->lock); | |
2105 | musb->gadget_driver->resume(&musb->g); | |
2106 | spin_lock(&musb->lock); | |
2107 | } | |
2108 | break; | |
2109 | default: | |
2110 | WARNING("unhandled RESUME transition (%s)\n", | |
3df00453 | 2111 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
2112 | } |
2113 | } | |
2114 | ||
2115 | /* called when SOF packets stop for 3+ msec */ | |
2116 | void musb_g_suspend(struct musb *musb) | |
2117 | { | |
2118 | u8 devctl; | |
2119 | ||
2120 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
5c8a86e1 | 2121 | dev_dbg(musb->controller, "devctl %02x\n", devctl); |
550a7375 | 2122 | |
84e250ff | 2123 | switch (musb->xceiv->state) { |
550a7375 FB |
2124 | case OTG_STATE_B_IDLE: |
2125 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
84e250ff | 2126 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
2127 | break; |
2128 | case OTG_STATE_B_PERIPHERAL: | |
2129 | musb->is_suspended = 1; | |
2130 | if (musb->gadget_driver && musb->gadget_driver->suspend) { | |
2131 | spin_unlock(&musb->lock); | |
2132 | musb->gadget_driver->suspend(&musb->g); | |
2133 | spin_lock(&musb->lock); | |
2134 | } | |
2135 | break; | |
2136 | default: | |
2137 | /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; | |
2138 | * A_PERIPHERAL may need care too | |
2139 | */ | |
2140 | WARNING("unhandled SUSPEND transition (%s)\n", | |
3df00453 | 2141 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
2142 | } |
2143 | } | |
2144 | ||
2145 | /* Called during SRP */ | |
2146 | void musb_g_wakeup(struct musb *musb) | |
2147 | { | |
2148 | musb_gadget_wakeup(&musb->g); | |
2149 | } | |
2150 | ||
2151 | /* called when VBUS drops below session threshold, and in other cases */ | |
2152 | void musb_g_disconnect(struct musb *musb) | |
2153 | { | |
2154 | void __iomem *mregs = musb->mregs; | |
2155 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
2156 | ||
5c8a86e1 | 2157 | dev_dbg(musb->controller, "devctl %02x\n", devctl); |
550a7375 FB |
2158 | |
2159 | /* clear HR */ | |
2160 | musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); | |
2161 | ||
2162 | /* don't draw vbus until new b-default session */ | |
2163 | (void) musb_gadget_vbus_draw(&musb->g, 0); | |
2164 | ||
2165 | musb->g.speed = USB_SPEED_UNKNOWN; | |
2166 | if (musb->gadget_driver && musb->gadget_driver->disconnect) { | |
2167 | spin_unlock(&musb->lock); | |
2168 | musb->gadget_driver->disconnect(&musb->g); | |
2169 | spin_lock(&musb->lock); | |
2170 | } | |
2171 | ||
84e250ff | 2172 | switch (musb->xceiv->state) { |
550a7375 FB |
2173 | default: |
2174 | #ifdef CONFIG_USB_MUSB_OTG | |
5c8a86e1 | 2175 | dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n", |
3df00453 | 2176 | otg_state_string(musb->xceiv->state)); |
84e250ff | 2177 | musb->xceiv->state = OTG_STATE_A_IDLE; |
ab983f2a | 2178 | MUSB_HST_MODE(musb); |
550a7375 FB |
2179 | break; |
2180 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae | 2181 | musb->xceiv->state = OTG_STATE_A_WAIT_BCON; |
ab983f2a | 2182 | MUSB_HST_MODE(musb); |
550a7375 FB |
2183 | break; |
2184 | case OTG_STATE_B_WAIT_ACON: | |
2185 | case OTG_STATE_B_HOST: | |
2186 | #endif | |
2187 | case OTG_STATE_B_PERIPHERAL: | |
2188 | case OTG_STATE_B_IDLE: | |
84e250ff | 2189 | musb->xceiv->state = OTG_STATE_B_IDLE; |
550a7375 FB |
2190 | break; |
2191 | case OTG_STATE_B_SRP_INIT: | |
2192 | break; | |
2193 | } | |
2194 | ||
2195 | musb->is_active = 0; | |
2196 | } | |
2197 | ||
2198 | void musb_g_reset(struct musb *musb) | |
2199 | __releases(musb->lock) | |
2200 | __acquires(musb->lock) | |
2201 | { | |
2202 | void __iomem *mbase = musb->mregs; | |
2203 | u8 devctl = musb_readb(mbase, MUSB_DEVCTL); | |
2204 | u8 power; | |
2205 | ||
5c8a86e1 | 2206 | dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n", |
550a7375 FB |
2207 | (devctl & MUSB_DEVCTL_BDEVICE) |
2208 | ? "B-Device" : "A-Device", | |
2209 | musb_readb(mbase, MUSB_FADDR), | |
2210 | musb->gadget_driver | |
2211 | ? musb->gadget_driver->driver.name | |
2212 | : NULL | |
2213 | ); | |
2214 | ||
2215 | /* report disconnect, if we didn't already (flushing EP state) */ | |
2216 | if (musb->g.speed != USB_SPEED_UNKNOWN) | |
2217 | musb_g_disconnect(musb); | |
2218 | ||
2219 | /* clear HR */ | |
2220 | else if (devctl & MUSB_DEVCTL_HR) | |
2221 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
2222 | ||
2223 | ||
2224 | /* what speed did we negotiate? */ | |
2225 | power = musb_readb(mbase, MUSB_POWER); | |
2226 | musb->g.speed = (power & MUSB_POWER_HSMODE) | |
2227 | ? USB_SPEED_HIGH : USB_SPEED_FULL; | |
2228 | ||
2229 | /* start in USB_STATE_DEFAULT */ | |
2230 | musb->is_active = 1; | |
2231 | musb->is_suspended = 0; | |
2232 | MUSB_DEV_MODE(musb); | |
2233 | musb->address = 0; | |
2234 | musb->ep0_state = MUSB_EP0_STAGE_SETUP; | |
2235 | ||
2236 | musb->may_wakeup = 0; | |
2237 | musb->g.b_hnp_enable = 0; | |
2238 | musb->g.a_alt_hnp_support = 0; | |
2239 | musb->g.a_hnp_support = 0; | |
2240 | ||
2241 | /* Normal reset, as B-Device; | |
2242 | * or else after HNP, as A-Device | |
2243 | */ | |
2244 | if (devctl & MUSB_DEVCTL_BDEVICE) { | |
84e250ff | 2245 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
2246 | musb->g.is_a_peripheral = 0; |
2247 | } else if (is_otg_enabled(musb)) { | |
84e250ff | 2248 | musb->xceiv->state = OTG_STATE_A_PERIPHERAL; |
550a7375 FB |
2249 | musb->g.is_a_peripheral = 1; |
2250 | } else | |
2251 | WARN_ON(1); | |
2252 | ||
2253 | /* start with default limits on VBUS power draw */ | |
2254 | (void) musb_gadget_vbus_draw(&musb->g, | |
2255 | is_otg_enabled(musb) ? 8 : 100); | |
2256 | } |