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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver peripheral support | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/list.h> | |
37 | #include <linux/timer.h> | |
38 | #include <linux/module.h> | |
39 | #include <linux/smp.h> | |
40 | #include <linux/spinlock.h> | |
41 | #include <linux/delay.h> | |
42 | #include <linux/moduleparam.h> | |
43 | #include <linux/stat.h> | |
44 | #include <linux/dma-mapping.h> | |
45 | ||
46 | #include "musb_core.h" | |
47 | ||
48 | ||
49 | /* MUSB PERIPHERAL status 3-mar-2006: | |
50 | * | |
51 | * - EP0 seems solid. It passes both USBCV and usbtest control cases. | |
52 | * Minor glitches: | |
53 | * | |
54 | * + remote wakeup to Linux hosts work, but saw USBCV failures; | |
55 | * in one test run (operator error?) | |
56 | * + endpoint halt tests -- in both usbtest and usbcv -- seem | |
57 | * to break when dma is enabled ... is something wrongly | |
58 | * clearing SENDSTALL? | |
59 | * | |
60 | * - Mass storage behaved ok when last tested. Network traffic patterns | |
61 | * (with lots of short transfers etc) need retesting; they turn up the | |
62 | * worst cases of the DMA, since short packets are typical but are not | |
63 | * required. | |
64 | * | |
65 | * - TX/IN | |
66 | * + both pio and dma behave in with network and g_zero tests | |
67 | * + no cppi throughput issues other than no-hw-queueing | |
68 | * + failed with FLAT_REG (DaVinci) | |
69 | * + seems to behave with double buffering, PIO -and- CPPI | |
70 | * + with gadgetfs + AIO, requests got lost? | |
71 | * | |
72 | * - RX/OUT | |
73 | * + both pio and dma behave in with network and g_zero tests | |
74 | * + dma is slow in typical case (short_not_ok is clear) | |
75 | * + double buffering ok with PIO | |
76 | * + double buffering *FAILS* with CPPI, wrong data bytes sometimes | |
77 | * + request lossage observed with gadgetfs | |
78 | * | |
79 | * - ISO not tested ... might work, but only weakly isochronous | |
80 | * | |
81 | * - Gadget driver disabling of softconnect during bind() is ignored; so | |
82 | * drivers can't hold off host requests until userspace is ready. | |
83 | * (Workaround: they can turn it off later.) | |
84 | * | |
85 | * - PORTABILITY (assumes PIO works): | |
86 | * + DaVinci, basically works with cppi dma | |
87 | * + OMAP 2430, ditto with mentor dma | |
88 | * + TUSB 6010, platform-specific dma in the works | |
89 | */ | |
90 | ||
91 | /* ----------------------------------------------------------------------- */ | |
92 | ||
93 | /* | |
94 | * Immediately complete a request. | |
95 | * | |
96 | * @param request the request to complete | |
97 | * @param status the status to complete the request with | |
98 | * Context: controller locked, IRQs blocked. | |
99 | */ | |
100 | void musb_g_giveback( | |
101 | struct musb_ep *ep, | |
102 | struct usb_request *request, | |
103 | int status) | |
104 | __releases(ep->musb->lock) | |
105 | __acquires(ep->musb->lock) | |
106 | { | |
107 | struct musb_request *req; | |
108 | struct musb *musb; | |
109 | int busy = ep->busy; | |
110 | ||
111 | req = to_musb_request(request); | |
112 | ||
113 | list_del(&request->list); | |
114 | if (req->request.status == -EINPROGRESS) | |
115 | req->request.status = status; | |
116 | musb = req->musb; | |
117 | ||
118 | ep->busy = 1; | |
119 | spin_unlock(&musb->lock); | |
120 | if (is_dma_capable()) { | |
121 | if (req->mapped) { | |
122 | dma_unmap_single(musb->controller, | |
123 | req->request.dma, | |
124 | req->request.length, | |
125 | req->tx | |
126 | ? DMA_TO_DEVICE | |
127 | : DMA_FROM_DEVICE); | |
128 | req->request.dma = DMA_ADDR_INVALID; | |
129 | req->mapped = 0; | |
130 | } else if (req->request.dma != DMA_ADDR_INVALID) | |
131 | dma_sync_single_for_cpu(musb->controller, | |
132 | req->request.dma, | |
133 | req->request.length, | |
134 | req->tx | |
135 | ? DMA_TO_DEVICE | |
136 | : DMA_FROM_DEVICE); | |
137 | } | |
138 | if (request->status == 0) | |
139 | DBG(5, "%s done request %p, %d/%d\n", | |
140 | ep->end_point.name, request, | |
141 | req->request.actual, req->request.length); | |
142 | else | |
143 | DBG(2, "%s request %p, %d/%d fault %d\n", | |
144 | ep->end_point.name, request, | |
145 | req->request.actual, req->request.length, | |
146 | request->status); | |
147 | req->request.complete(&req->ep->end_point, &req->request); | |
148 | spin_lock(&musb->lock); | |
149 | ep->busy = busy; | |
150 | } | |
151 | ||
152 | /* ----------------------------------------------------------------------- */ | |
153 | ||
154 | /* | |
155 | * Abort requests queued to an endpoint using the status. Synchronous. | |
156 | * caller locked controller and blocked irqs, and selected this ep. | |
157 | */ | |
158 | static void nuke(struct musb_ep *ep, const int status) | |
159 | { | |
160 | struct musb_request *req = NULL; | |
161 | void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; | |
162 | ||
163 | ep->busy = 1; | |
164 | ||
165 | if (is_dma_capable() && ep->dma) { | |
166 | struct dma_controller *c = ep->musb->dma_controller; | |
167 | int value; | |
b6e434a5 | 168 | |
550a7375 | 169 | if (ep->is_in) { |
b6e434a5 SS |
170 | /* |
171 | * The programming guide says that we must not clear | |
172 | * the DMAMODE bit before DMAENAB, so we only | |
173 | * clear it in the second write... | |
174 | */ | |
550a7375 | 175 | musb_writew(epio, MUSB_TXCSR, |
b6e434a5 | 176 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); |
550a7375 FB |
177 | musb_writew(epio, MUSB_TXCSR, |
178 | 0 | MUSB_TXCSR_FLUSHFIFO); | |
179 | } else { | |
180 | musb_writew(epio, MUSB_RXCSR, | |
181 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
182 | musb_writew(epio, MUSB_RXCSR, | |
183 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
184 | } | |
185 | ||
186 | value = c->channel_abort(ep->dma); | |
187 | DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value); | |
188 | c->channel_release(ep->dma); | |
189 | ep->dma = NULL; | |
190 | } | |
191 | ||
192 | while (!list_empty(&(ep->req_list))) { | |
193 | req = container_of(ep->req_list.next, struct musb_request, | |
194 | request.list); | |
195 | musb_g_giveback(ep, &req->request, status); | |
196 | } | |
197 | } | |
198 | ||
199 | /* ----------------------------------------------------------------------- */ | |
200 | ||
201 | /* Data transfers - pure PIO, pure DMA, or mixed mode */ | |
202 | ||
203 | /* | |
204 | * This assumes the separate CPPI engine is responding to DMA requests | |
205 | * from the usb core ... sequenced a bit differently from mentor dma. | |
206 | */ | |
207 | ||
208 | static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) | |
209 | { | |
210 | if (can_bulk_split(musb, ep->type)) | |
211 | return ep->hw_ep->max_packet_sz_tx; | |
212 | else | |
213 | return ep->packet_sz; | |
214 | } | |
215 | ||
216 | ||
217 | #ifdef CONFIG_USB_INVENTRA_DMA | |
218 | ||
219 | /* Peripheral tx (IN) using Mentor DMA works as follows: | |
220 | Only mode 0 is used for transfers <= wPktSize, | |
221 | mode 1 is used for larger transfers, | |
222 | ||
223 | One of the following happens: | |
224 | - Host sends IN token which causes an endpoint interrupt | |
225 | -> TxAvail | |
226 | -> if DMA is currently busy, exit. | |
227 | -> if queue is non-empty, txstate(). | |
228 | ||
229 | - Request is queued by the gadget driver. | |
230 | -> if queue was previously empty, txstate() | |
231 | ||
232 | txstate() | |
233 | -> start | |
234 | /\ -> setup DMA | |
235 | | (data is transferred to the FIFO, then sent out when | |
236 | | IN token(s) are recd from Host. | |
237 | | -> DMA interrupt on completion | |
238 | | calls TxAvail. | |
b6e434a5 | 239 | | -> stop DMA, ~DMAENAB, |
550a7375 FB |
240 | | -> set TxPktRdy for last short pkt or zlp |
241 | | -> Complete Request | |
242 | | -> Continue next request (call txstate) | |
243 | |___________________________________| | |
244 | ||
245 | * Non-Mentor DMA engines can of course work differently, such as by | |
246 | * upleveling from irq-per-packet to irq-per-buffer. | |
247 | */ | |
248 | ||
249 | #endif | |
250 | ||
251 | /* | |
252 | * An endpoint is transmitting data. This can be called either from | |
253 | * the IRQ routine or from ep.queue() to kickstart a request on an | |
254 | * endpoint. | |
255 | * | |
256 | * Context: controller locked, IRQs blocked, endpoint selected | |
257 | */ | |
258 | static void txstate(struct musb *musb, struct musb_request *req) | |
259 | { | |
260 | u8 epnum = req->epnum; | |
261 | struct musb_ep *musb_ep; | |
262 | void __iomem *epio = musb->endpoints[epnum].regs; | |
263 | struct usb_request *request; | |
264 | u16 fifo_count = 0, csr; | |
265 | int use_dma = 0; | |
266 | ||
267 | musb_ep = req->ep; | |
268 | ||
269 | /* we shouldn't get here while DMA is active ... but we do ... */ | |
270 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { | |
271 | DBG(4, "dma pending...\n"); | |
272 | return; | |
273 | } | |
274 | ||
275 | /* read TXCSR before */ | |
276 | csr = musb_readw(epio, MUSB_TXCSR); | |
277 | ||
278 | request = &req->request; | |
279 | fifo_count = min(max_ep_writesize(musb, musb_ep), | |
280 | (int)(request->length - request->actual)); | |
281 | ||
282 | if (csr & MUSB_TXCSR_TXPKTRDY) { | |
283 | DBG(5, "%s old packet still ready , txcsr %03x\n", | |
284 | musb_ep->end_point.name, csr); | |
285 | return; | |
286 | } | |
287 | ||
288 | if (csr & MUSB_TXCSR_P_SENDSTALL) { | |
289 | DBG(5, "%s stalling, txcsr %03x\n", | |
290 | musb_ep->end_point.name, csr); | |
291 | return; | |
292 | } | |
293 | ||
294 | DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", | |
295 | epnum, musb_ep->packet_sz, fifo_count, | |
296 | csr); | |
297 | ||
298 | #ifndef CONFIG_MUSB_PIO_ONLY | |
299 | if (is_dma_capable() && musb_ep->dma) { | |
300 | struct dma_controller *c = musb->dma_controller; | |
301 | ||
302 | use_dma = (request->dma != DMA_ADDR_INVALID); | |
303 | ||
304 | /* MUSB_TXCSR_P_ISO is still set correctly */ | |
305 | ||
306 | #ifdef CONFIG_USB_INVENTRA_DMA | |
307 | { | |
308 | size_t request_size; | |
309 | ||
310 | /* setup DMA, then program endpoint CSR */ | |
311 | request_size = min(request->length, | |
312 | musb_ep->dma->max_len); | |
313 | if (request_size <= musb_ep->packet_sz) | |
314 | musb_ep->dma->desired_mode = 0; | |
315 | else | |
316 | musb_ep->dma->desired_mode = 1; | |
317 | ||
318 | use_dma = use_dma && c->channel_program( | |
319 | musb_ep->dma, musb_ep->packet_sz, | |
320 | musb_ep->dma->desired_mode, | |
321 | request->dma, request_size); | |
322 | if (use_dma) { | |
323 | if (musb_ep->dma->desired_mode == 0) { | |
b6e434a5 SS |
324 | /* |
325 | * We must not clear the DMAMODE bit | |
326 | * before the DMAENAB bit -- and the | |
327 | * latter doesn't always get cleared | |
328 | * before we get here... | |
329 | */ | |
330 | csr &= ~(MUSB_TXCSR_AUTOSET | |
331 | | MUSB_TXCSR_DMAENAB); | |
332 | musb_writew(epio, MUSB_TXCSR, csr | |
333 | | MUSB_TXCSR_P_WZC_BITS); | |
334 | csr &= ~MUSB_TXCSR_DMAMODE; | |
550a7375 FB |
335 | csr |= (MUSB_TXCSR_DMAENAB | |
336 | MUSB_TXCSR_MODE); | |
337 | /* against programming guide */ | |
338 | } else | |
339 | csr |= (MUSB_TXCSR_AUTOSET | |
340 | | MUSB_TXCSR_DMAENAB | |
341 | | MUSB_TXCSR_DMAMODE | |
342 | | MUSB_TXCSR_MODE); | |
343 | ||
344 | csr &= ~MUSB_TXCSR_P_UNDERRUN; | |
345 | musb_writew(epio, MUSB_TXCSR, csr); | |
346 | } | |
347 | } | |
348 | ||
349 | #elif defined(CONFIG_USB_TI_CPPI_DMA) | |
350 | /* program endpoint CSR first, then setup DMA */ | |
b6e434a5 | 351 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); |
550a7375 FB |
352 | csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_DMAENAB; |
353 | musb_writew(epio, MUSB_TXCSR, | |
354 | (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN) | |
355 | | csr); | |
356 | ||
357 | /* ensure writebuffer is empty */ | |
358 | csr = musb_readw(epio, MUSB_TXCSR); | |
359 | ||
360 | /* NOTE host side sets DMAENAB later than this; both are | |
361 | * OK since the transfer dma glue (between CPPI and Mentor | |
362 | * fifos) just tells CPPI it could start. Data only moves | |
363 | * to the USB TX fifo when both fifos are ready. | |
364 | */ | |
365 | ||
366 | /* "mode" is irrelevant here; handle terminating ZLPs like | |
367 | * PIO does, since the hardware RNDIS mode seems unreliable | |
368 | * except for the last-packet-is-already-short case. | |
369 | */ | |
370 | use_dma = use_dma && c->channel_program( | |
371 | musb_ep->dma, musb_ep->packet_sz, | |
372 | 0, | |
373 | request->dma, | |
374 | request->length); | |
375 | if (!use_dma) { | |
376 | c->channel_release(musb_ep->dma); | |
377 | musb_ep->dma = NULL; | |
b6e434a5 SS |
378 | csr &= ~MUSB_TXCSR_DMAENAB; |
379 | musb_writew(epio, MUSB_TXCSR, csr); | |
550a7375 FB |
380 | /* invariant: prequest->buf is non-null */ |
381 | } | |
382 | #elif defined(CONFIG_USB_TUSB_OMAP_DMA) | |
383 | use_dma = use_dma && c->channel_program( | |
384 | musb_ep->dma, musb_ep->packet_sz, | |
385 | request->zero, | |
386 | request->dma, | |
387 | request->length); | |
388 | #endif | |
389 | } | |
390 | #endif | |
391 | ||
392 | if (!use_dma) { | |
393 | musb_write_fifo(musb_ep->hw_ep, fifo_count, | |
394 | (u8 *) (request->buf + request->actual)); | |
395 | request->actual += fifo_count; | |
396 | csr |= MUSB_TXCSR_TXPKTRDY; | |
397 | csr &= ~MUSB_TXCSR_P_UNDERRUN; | |
398 | musb_writew(epio, MUSB_TXCSR, csr); | |
399 | } | |
400 | ||
401 | /* host may already have the data when this message shows... */ | |
402 | DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", | |
403 | musb_ep->end_point.name, use_dma ? "dma" : "pio", | |
404 | request->actual, request->length, | |
405 | musb_readw(epio, MUSB_TXCSR), | |
406 | fifo_count, | |
407 | musb_readw(epio, MUSB_TXMAXP)); | |
408 | } | |
409 | ||
410 | /* | |
411 | * FIFO state update (e.g. data ready). | |
412 | * Called from IRQ, with controller locked. | |
413 | */ | |
414 | void musb_g_tx(struct musb *musb, u8 epnum) | |
415 | { | |
416 | u16 csr; | |
417 | struct usb_request *request; | |
418 | u8 __iomem *mbase = musb->mregs; | |
419 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; | |
420 | void __iomem *epio = musb->endpoints[epnum].regs; | |
421 | struct dma_channel *dma; | |
422 | ||
423 | musb_ep_select(mbase, epnum); | |
424 | request = next_request(musb_ep); | |
425 | ||
426 | csr = musb_readw(epio, MUSB_TXCSR); | |
427 | DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); | |
428 | ||
429 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
430 | do { | |
431 | /* REVISIT for high bandwidth, MUSB_TXCSR_P_INCOMPTX | |
432 | * probably rates reporting as a host error | |
433 | */ | |
434 | if (csr & MUSB_TXCSR_P_SENTSTALL) { | |
435 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
436 | csr &= ~MUSB_TXCSR_P_SENTSTALL; | |
437 | musb_writew(epio, MUSB_TXCSR, csr); | |
438 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
439 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; | |
440 | musb->dma_controller->channel_abort(dma); | |
441 | } | |
442 | ||
443 | if (request) | |
444 | musb_g_giveback(musb_ep, request, -EPIPE); | |
445 | ||
446 | break; | |
447 | } | |
448 | ||
449 | if (csr & MUSB_TXCSR_P_UNDERRUN) { | |
450 | /* we NAKed, no big deal ... little reason to care */ | |
451 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
452 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | |
453 | | MUSB_TXCSR_TXPKTRDY); | |
454 | musb_writew(epio, MUSB_TXCSR, csr); | |
455 | DBG(20, "underrun on ep%d, req %p\n", epnum, request); | |
456 | } | |
457 | ||
458 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
459 | /* SHOULD NOT HAPPEN ... has with cppi though, after | |
460 | * changing SENDSTALL (and other cases); harmless? | |
461 | */ | |
462 | DBG(5, "%s dma still busy?\n", musb_ep->end_point.name); | |
463 | break; | |
464 | } | |
465 | ||
466 | if (request) { | |
467 | u8 is_dma = 0; | |
468 | ||
469 | if (dma && (csr & MUSB_TXCSR_DMAENAB)) { | |
470 | is_dma = 1; | |
471 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
472 | csr &= ~(MUSB_TXCSR_DMAENAB | |
473 | | MUSB_TXCSR_P_UNDERRUN | |
474 | | MUSB_TXCSR_TXPKTRDY); | |
475 | musb_writew(epio, MUSB_TXCSR, csr); | |
476 | /* ensure writebuffer is empty */ | |
477 | csr = musb_readw(epio, MUSB_TXCSR); | |
478 | request->actual += musb_ep->dma->actual_len; | |
479 | DBG(4, "TXCSR%d %04x, dma off, " | |
480 | "len %zu, req %p\n", | |
481 | epnum, csr, | |
482 | musb_ep->dma->actual_len, | |
483 | request); | |
484 | } | |
485 | ||
486 | if (is_dma || request->actual == request->length) { | |
487 | ||
488 | /* First, maybe a terminating short packet. | |
489 | * Some DMA engines might handle this by | |
490 | * themselves. | |
491 | */ | |
492 | if ((request->zero | |
493 | && request->length | |
494 | && (request->length | |
495 | % musb_ep->packet_sz) | |
496 | == 0) | |
497 | #ifdef CONFIG_USB_INVENTRA_DMA | |
498 | || (is_dma && | |
499 | ((!dma->desired_mode) || | |
500 | (request->actual & | |
501 | (musb_ep->packet_sz - 1)))) | |
502 | #endif | |
503 | ) { | |
504 | /* on dma completion, fifo may not | |
505 | * be available yet ... | |
506 | */ | |
507 | if (csr & MUSB_TXCSR_TXPKTRDY) | |
508 | break; | |
509 | ||
510 | DBG(4, "sending zero pkt\n"); | |
511 | musb_writew(epio, MUSB_TXCSR, | |
512 | MUSB_TXCSR_MODE | |
513 | | MUSB_TXCSR_TXPKTRDY); | |
514 | request->zero = 0; | |
515 | } | |
516 | ||
517 | /* ... or if not, then complete it */ | |
518 | musb_g_giveback(musb_ep, request, 0); | |
519 | ||
520 | /* kickstart next transfer if appropriate; | |
521 | * the packet that just completed might not | |
522 | * be transmitted for hours or days. | |
523 | * REVISIT for double buffering... | |
524 | * FIXME revisit for stalls too... | |
525 | */ | |
526 | musb_ep_select(mbase, epnum); | |
527 | csr = musb_readw(epio, MUSB_TXCSR); | |
528 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) | |
529 | break; | |
530 | request = musb_ep->desc | |
531 | ? next_request(musb_ep) | |
532 | : NULL; | |
533 | if (!request) { | |
534 | DBG(4, "%s idle now\n", | |
535 | musb_ep->end_point.name); | |
536 | break; | |
537 | } | |
538 | } | |
539 | ||
540 | txstate(musb, to_musb_request(request)); | |
541 | } | |
542 | ||
543 | } while (0); | |
544 | } | |
545 | ||
546 | /* ------------------------------------------------------------ */ | |
547 | ||
548 | #ifdef CONFIG_USB_INVENTRA_DMA | |
549 | ||
550 | /* Peripheral rx (OUT) using Mentor DMA works as follows: | |
551 | - Only mode 0 is used. | |
552 | ||
553 | - Request is queued by the gadget class driver. | |
554 | -> if queue was previously empty, rxstate() | |
555 | ||
556 | - Host sends OUT token which causes an endpoint interrupt | |
557 | /\ -> RxReady | |
558 | | -> if request queued, call rxstate | |
559 | | /\ -> setup DMA | |
560 | | | -> DMA interrupt on completion | |
561 | | | -> RxReady | |
562 | | | -> stop DMA | |
563 | | | -> ack the read | |
564 | | | -> if data recd = max expected | |
565 | | | by the request, or host | |
566 | | | sent a short packet, | |
567 | | | complete the request, | |
568 | | | and start the next one. | |
569 | | |_____________________________________| | |
570 | | else just wait for the host | |
571 | | to send the next OUT token. | |
572 | |__________________________________________________| | |
573 | ||
574 | * Non-Mentor DMA engines can of course work differently. | |
575 | */ | |
576 | ||
577 | #endif | |
578 | ||
579 | /* | |
580 | * Context: controller locked, IRQs blocked, endpoint selected | |
581 | */ | |
582 | static void rxstate(struct musb *musb, struct musb_request *req) | |
583 | { | |
584 | u16 csr = 0; | |
585 | const u8 epnum = req->epnum; | |
586 | struct usb_request *request = &req->request; | |
587 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out; | |
588 | void __iomem *epio = musb->endpoints[epnum].regs; | |
c2c96321 | 589 | unsigned fifo_count = 0; |
550a7375 FB |
590 | u16 len = musb_ep->packet_sz; |
591 | ||
592 | csr = musb_readw(epio, MUSB_RXCSR); | |
593 | ||
594 | if (is_cppi_enabled() && musb_ep->dma) { | |
595 | struct dma_controller *c = musb->dma_controller; | |
596 | struct dma_channel *channel = musb_ep->dma; | |
597 | ||
598 | /* NOTE: CPPI won't actually stop advancing the DMA | |
599 | * queue after short packet transfers, so this is almost | |
600 | * always going to run as IRQ-per-packet DMA so that | |
601 | * faults will be handled correctly. | |
602 | */ | |
603 | if (c->channel_program(channel, | |
604 | musb_ep->packet_sz, | |
605 | !request->short_not_ok, | |
606 | request->dma + request->actual, | |
607 | request->length - request->actual)) { | |
608 | ||
609 | /* make sure that if an rxpkt arrived after the irq, | |
610 | * the cppi engine will be ready to take it as soon | |
611 | * as DMA is enabled | |
612 | */ | |
613 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
614 | | MUSB_RXCSR_DMAMODE); | |
615 | csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; | |
616 | musb_writew(epio, MUSB_RXCSR, csr); | |
617 | return; | |
618 | } | |
619 | } | |
620 | ||
621 | if (csr & MUSB_RXCSR_RXPKTRDY) { | |
622 | len = musb_readw(epio, MUSB_RXCOUNT); | |
623 | if (request->actual < request->length) { | |
624 | #ifdef CONFIG_USB_INVENTRA_DMA | |
625 | if (is_dma_capable() && musb_ep->dma) { | |
626 | struct dma_controller *c; | |
627 | struct dma_channel *channel; | |
628 | int use_dma = 0; | |
629 | ||
630 | c = musb->dma_controller; | |
631 | channel = musb_ep->dma; | |
632 | ||
633 | /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in | |
634 | * mode 0 only. So we do not get endpoint interrupts due to DMA | |
635 | * completion. We only get interrupts from DMA controller. | |
636 | * | |
637 | * We could operate in DMA mode 1 if we knew the size of the tranfer | |
638 | * in advance. For mass storage class, request->length = what the host | |
639 | * sends, so that'd work. But for pretty much everything else, | |
640 | * request->length is routinely more than what the host sends. For | |
641 | * most these gadgets, end of is signified either by a short packet, | |
642 | * or filling the last byte of the buffer. (Sending extra data in | |
643 | * that last pckate should trigger an overflow fault.) But in mode 1, | |
644 | * we don't get DMA completion interrrupt for short packets. | |
645 | * | |
646 | * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), | |
647 | * to get endpoint interrupt on every DMA req, but that didn't seem | |
648 | * to work reliably. | |
649 | * | |
650 | * REVISIT an updated g_file_storage can set req->short_not_ok, which | |
651 | * then becomes usable as a runtime "use mode 1" hint... | |
652 | */ | |
653 | ||
654 | csr |= MUSB_RXCSR_DMAENAB; | |
655 | #ifdef USE_MODE1 | |
656 | csr |= MUSB_RXCSR_AUTOCLEAR; | |
657 | /* csr |= MUSB_RXCSR_DMAMODE; */ | |
658 | ||
659 | /* this special sequence (enabling and then | |
660 | * disabling MUSB_RXCSR_DMAMODE) is required | |
661 | * to get DMAReq to activate | |
662 | */ | |
663 | musb_writew(epio, MUSB_RXCSR, | |
664 | csr | MUSB_RXCSR_DMAMODE); | |
665 | #endif | |
666 | musb_writew(epio, MUSB_RXCSR, csr); | |
667 | ||
668 | if (request->actual < request->length) { | |
669 | int transfer_size = 0; | |
670 | #ifdef USE_MODE1 | |
671 | transfer_size = min(request->length, | |
672 | channel->max_len); | |
673 | #else | |
674 | transfer_size = len; | |
675 | #endif | |
676 | if (transfer_size <= musb_ep->packet_sz) | |
677 | musb_ep->dma->desired_mode = 0; | |
678 | else | |
679 | musb_ep->dma->desired_mode = 1; | |
680 | ||
681 | use_dma = c->channel_program( | |
682 | channel, | |
683 | musb_ep->packet_sz, | |
684 | channel->desired_mode, | |
685 | request->dma | |
686 | + request->actual, | |
687 | transfer_size); | |
688 | } | |
689 | ||
690 | if (use_dma) | |
691 | return; | |
692 | } | |
693 | #endif /* Mentor's DMA */ | |
694 | ||
695 | fifo_count = request->length - request->actual; | |
696 | DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", | |
697 | musb_ep->end_point.name, | |
698 | len, fifo_count, | |
699 | musb_ep->packet_sz); | |
700 | ||
c2c96321 | 701 | fifo_count = min_t(unsigned, len, fifo_count); |
550a7375 FB |
702 | |
703 | #ifdef CONFIG_USB_TUSB_OMAP_DMA | |
704 | if (tusb_dma_omap() && musb_ep->dma) { | |
705 | struct dma_controller *c = musb->dma_controller; | |
706 | struct dma_channel *channel = musb_ep->dma; | |
707 | u32 dma_addr = request->dma + request->actual; | |
708 | int ret; | |
709 | ||
710 | ret = c->channel_program(channel, | |
711 | musb_ep->packet_sz, | |
712 | channel->desired_mode, | |
713 | dma_addr, | |
714 | fifo_count); | |
715 | if (ret) | |
716 | return; | |
717 | } | |
718 | #endif | |
719 | ||
720 | musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) | |
721 | (request->buf + request->actual)); | |
722 | request->actual += fifo_count; | |
723 | ||
724 | /* REVISIT if we left anything in the fifo, flush | |
725 | * it and report -EOVERFLOW | |
726 | */ | |
727 | ||
728 | /* ack the read! */ | |
729 | csr |= MUSB_RXCSR_P_WZC_BITS; | |
730 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
731 | musb_writew(epio, MUSB_RXCSR, csr); | |
732 | } | |
733 | } | |
734 | ||
735 | /* reach the end or short packet detected */ | |
736 | if (request->actual == request->length || len < musb_ep->packet_sz) | |
737 | musb_g_giveback(musb_ep, request, 0); | |
738 | } | |
739 | ||
740 | /* | |
741 | * Data ready for a request; called from IRQ | |
742 | */ | |
743 | void musb_g_rx(struct musb *musb, u8 epnum) | |
744 | { | |
745 | u16 csr; | |
746 | struct usb_request *request; | |
747 | void __iomem *mbase = musb->mregs; | |
748 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out; | |
749 | void __iomem *epio = musb->endpoints[epnum].regs; | |
750 | struct dma_channel *dma; | |
751 | ||
752 | musb_ep_select(mbase, epnum); | |
753 | ||
754 | request = next_request(musb_ep); | |
755 | ||
756 | csr = musb_readw(epio, MUSB_RXCSR); | |
757 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
758 | ||
759 | DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, | |
760 | csr, dma ? " (dma)" : "", request); | |
761 | ||
762 | if (csr & MUSB_RXCSR_P_SENTSTALL) { | |
763 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
764 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; | |
765 | (void) musb->dma_controller->channel_abort(dma); | |
766 | request->actual += musb_ep->dma->actual_len; | |
767 | } | |
768 | ||
769 | csr |= MUSB_RXCSR_P_WZC_BITS; | |
770 | csr &= ~MUSB_RXCSR_P_SENTSTALL; | |
771 | musb_writew(epio, MUSB_RXCSR, csr); | |
772 | ||
773 | if (request) | |
774 | musb_g_giveback(musb_ep, request, -EPIPE); | |
775 | goto done; | |
776 | } | |
777 | ||
778 | if (csr & MUSB_RXCSR_P_OVERRUN) { | |
779 | /* csr |= MUSB_RXCSR_P_WZC_BITS; */ | |
780 | csr &= ~MUSB_RXCSR_P_OVERRUN; | |
781 | musb_writew(epio, MUSB_RXCSR, csr); | |
782 | ||
783 | DBG(3, "%s iso overrun on %p\n", musb_ep->name, request); | |
784 | if (request && request->status == -EINPROGRESS) | |
785 | request->status = -EOVERFLOW; | |
786 | } | |
787 | if (csr & MUSB_RXCSR_INCOMPRX) { | |
788 | /* REVISIT not necessarily an error */ | |
789 | DBG(4, "%s, incomprx\n", musb_ep->end_point.name); | |
790 | } | |
791 | ||
792 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
793 | /* "should not happen"; likely RXPKTRDY pending for DMA */ | |
794 | DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1, | |
795 | "%s busy, csr %04x\n", | |
796 | musb_ep->end_point.name, csr); | |
797 | goto done; | |
798 | } | |
799 | ||
800 | if (dma && (csr & MUSB_RXCSR_DMAENAB)) { | |
801 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
802 | | MUSB_RXCSR_DMAENAB | |
803 | | MUSB_RXCSR_DMAMODE); | |
804 | musb_writew(epio, MUSB_RXCSR, | |
805 | MUSB_RXCSR_P_WZC_BITS | csr); | |
806 | ||
807 | request->actual += musb_ep->dma->actual_len; | |
808 | ||
809 | DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", | |
810 | epnum, csr, | |
811 | musb_readw(epio, MUSB_RXCSR), | |
812 | musb_ep->dma->actual_len, request); | |
813 | ||
814 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) | |
815 | /* Autoclear doesn't clear RxPktRdy for short packets */ | |
816 | if ((dma->desired_mode == 0) | |
817 | || (dma->actual_len | |
818 | & (musb_ep->packet_sz - 1))) { | |
819 | /* ack the read! */ | |
820 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
821 | musb_writew(epio, MUSB_RXCSR, csr); | |
822 | } | |
823 | ||
824 | /* incomplete, and not short? wait for next IN packet */ | |
825 | if ((request->actual < request->length) | |
826 | && (musb_ep->dma->actual_len | |
827 | == musb_ep->packet_sz)) | |
828 | goto done; | |
829 | #endif | |
830 | musb_g_giveback(musb_ep, request, 0); | |
831 | ||
832 | request = next_request(musb_ep); | |
833 | if (!request) | |
834 | goto done; | |
835 | ||
836 | /* don't start more i/o till the stall clears */ | |
837 | musb_ep_select(mbase, epnum); | |
838 | csr = musb_readw(epio, MUSB_RXCSR); | |
839 | if (csr & MUSB_RXCSR_P_SENDSTALL) | |
840 | goto done; | |
841 | } | |
842 | ||
843 | ||
844 | /* analyze request if the ep is hot */ | |
845 | if (request) | |
846 | rxstate(musb, to_musb_request(request)); | |
847 | else | |
848 | DBG(3, "packet waiting for %s%s request\n", | |
849 | musb_ep->desc ? "" : "inactive ", | |
850 | musb_ep->end_point.name); | |
851 | ||
852 | done: | |
853 | return; | |
854 | } | |
855 | ||
856 | /* ------------------------------------------------------------ */ | |
857 | ||
858 | static int musb_gadget_enable(struct usb_ep *ep, | |
859 | const struct usb_endpoint_descriptor *desc) | |
860 | { | |
861 | unsigned long flags; | |
862 | struct musb_ep *musb_ep; | |
863 | struct musb_hw_ep *hw_ep; | |
864 | void __iomem *regs; | |
865 | struct musb *musb; | |
866 | void __iomem *mbase; | |
867 | u8 epnum; | |
868 | u16 csr; | |
869 | unsigned tmp; | |
870 | int status = -EINVAL; | |
871 | ||
872 | if (!ep || !desc) | |
873 | return -EINVAL; | |
874 | ||
875 | musb_ep = to_musb_ep(ep); | |
876 | hw_ep = musb_ep->hw_ep; | |
877 | regs = hw_ep->regs; | |
878 | musb = musb_ep->musb; | |
879 | mbase = musb->mregs; | |
880 | epnum = musb_ep->current_epnum; | |
881 | ||
882 | spin_lock_irqsave(&musb->lock, flags); | |
883 | ||
884 | if (musb_ep->desc) { | |
885 | status = -EBUSY; | |
886 | goto fail; | |
887 | } | |
96bcd090 | 888 | musb_ep->type = usb_endpoint_type(desc); |
550a7375 FB |
889 | |
890 | /* check direction and (later) maxpacket size against endpoint */ | |
96bcd090 | 891 | if (usb_endpoint_num(desc) != epnum) |
550a7375 FB |
892 | goto fail; |
893 | ||
894 | /* REVISIT this rules out high bandwidth periodic transfers */ | |
895 | tmp = le16_to_cpu(desc->wMaxPacketSize); | |
896 | if (tmp & ~0x07ff) | |
897 | goto fail; | |
898 | musb_ep->packet_sz = tmp; | |
899 | ||
900 | /* enable the interrupts for the endpoint, set the endpoint | |
901 | * packet size (or fail), set the mode, clear the fifo | |
902 | */ | |
903 | musb_ep_select(mbase, epnum); | |
96bcd090 | 904 | if (usb_endpoint_dir_in(desc)) { |
550a7375 FB |
905 | u16 int_txe = musb_readw(mbase, MUSB_INTRTXE); |
906 | ||
907 | if (hw_ep->is_shared_fifo) | |
908 | musb_ep->is_in = 1; | |
909 | if (!musb_ep->is_in) | |
910 | goto fail; | |
911 | if (tmp > hw_ep->max_packet_sz_tx) | |
912 | goto fail; | |
913 | ||
914 | int_txe |= (1 << epnum); | |
915 | musb_writew(mbase, MUSB_INTRTXE, int_txe); | |
916 | ||
917 | /* REVISIT if can_bulk_split(), use by updating "tmp"; | |
918 | * likewise high bandwidth periodic tx | |
919 | */ | |
920 | musb_writew(regs, MUSB_TXMAXP, tmp); | |
921 | ||
922 | csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; | |
923 | if (musb_readw(regs, MUSB_TXCSR) | |
924 | & MUSB_TXCSR_FIFONOTEMPTY) | |
925 | csr |= MUSB_TXCSR_FLUSHFIFO; | |
926 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
927 | csr |= MUSB_TXCSR_P_ISO; | |
928 | ||
929 | /* set twice in case of double buffering */ | |
930 | musb_writew(regs, MUSB_TXCSR, csr); | |
931 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
932 | musb_writew(regs, MUSB_TXCSR, csr); | |
933 | ||
934 | } else { | |
935 | u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE); | |
936 | ||
937 | if (hw_ep->is_shared_fifo) | |
938 | musb_ep->is_in = 0; | |
939 | if (musb_ep->is_in) | |
940 | goto fail; | |
941 | if (tmp > hw_ep->max_packet_sz_rx) | |
942 | goto fail; | |
943 | ||
944 | int_rxe |= (1 << epnum); | |
945 | musb_writew(mbase, MUSB_INTRRXE, int_rxe); | |
946 | ||
947 | /* REVISIT if can_bulk_combine() use by updating "tmp" | |
948 | * likewise high bandwidth periodic rx | |
949 | */ | |
950 | musb_writew(regs, MUSB_RXMAXP, tmp); | |
951 | ||
952 | /* force shared fifo to OUT-only mode */ | |
953 | if (hw_ep->is_shared_fifo) { | |
954 | csr = musb_readw(regs, MUSB_TXCSR); | |
955 | csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); | |
956 | musb_writew(regs, MUSB_TXCSR, csr); | |
957 | } | |
958 | ||
959 | csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; | |
960 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
961 | csr |= MUSB_RXCSR_P_ISO; | |
962 | else if (musb_ep->type == USB_ENDPOINT_XFER_INT) | |
963 | csr |= MUSB_RXCSR_DISNYET; | |
964 | ||
965 | /* set twice in case of double buffering */ | |
966 | musb_writew(regs, MUSB_RXCSR, csr); | |
967 | musb_writew(regs, MUSB_RXCSR, csr); | |
968 | } | |
969 | ||
970 | /* NOTE: all the I/O code _should_ work fine without DMA, in case | |
971 | * for some reason you run out of channels here. | |
972 | */ | |
973 | if (is_dma_capable() && musb->dma_controller) { | |
974 | struct dma_controller *c = musb->dma_controller; | |
975 | ||
976 | musb_ep->dma = c->channel_alloc(c, hw_ep, | |
977 | (desc->bEndpointAddress & USB_DIR_IN)); | |
978 | } else | |
979 | musb_ep->dma = NULL; | |
980 | ||
981 | musb_ep->desc = desc; | |
982 | musb_ep->busy = 0; | |
983 | status = 0; | |
984 | ||
985 | pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", | |
986 | musb_driver_name, musb_ep->end_point.name, | |
987 | ({ char *s; switch (musb_ep->type) { | |
988 | case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; | |
989 | case USB_ENDPOINT_XFER_INT: s = "int"; break; | |
990 | default: s = "iso"; break; | |
991 | }; s; }), | |
992 | musb_ep->is_in ? "IN" : "OUT", | |
993 | musb_ep->dma ? "dma, " : "", | |
994 | musb_ep->packet_sz); | |
995 | ||
996 | schedule_work(&musb->irq_work); | |
997 | ||
998 | fail: | |
999 | spin_unlock_irqrestore(&musb->lock, flags); | |
1000 | return status; | |
1001 | } | |
1002 | ||
1003 | /* | |
1004 | * Disable an endpoint flushing all requests queued. | |
1005 | */ | |
1006 | static int musb_gadget_disable(struct usb_ep *ep) | |
1007 | { | |
1008 | unsigned long flags; | |
1009 | struct musb *musb; | |
1010 | u8 epnum; | |
1011 | struct musb_ep *musb_ep; | |
1012 | void __iomem *epio; | |
1013 | int status = 0; | |
1014 | ||
1015 | musb_ep = to_musb_ep(ep); | |
1016 | musb = musb_ep->musb; | |
1017 | epnum = musb_ep->current_epnum; | |
1018 | epio = musb->endpoints[epnum].regs; | |
1019 | ||
1020 | spin_lock_irqsave(&musb->lock, flags); | |
1021 | musb_ep_select(musb->mregs, epnum); | |
1022 | ||
1023 | /* zero the endpoint sizes */ | |
1024 | if (musb_ep->is_in) { | |
1025 | u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE); | |
1026 | int_txe &= ~(1 << epnum); | |
1027 | musb_writew(musb->mregs, MUSB_INTRTXE, int_txe); | |
1028 | musb_writew(epio, MUSB_TXMAXP, 0); | |
1029 | } else { | |
1030 | u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE); | |
1031 | int_rxe &= ~(1 << epnum); | |
1032 | musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe); | |
1033 | musb_writew(epio, MUSB_RXMAXP, 0); | |
1034 | } | |
1035 | ||
1036 | musb_ep->desc = NULL; | |
1037 | ||
1038 | /* abort all pending DMA and requests */ | |
1039 | nuke(musb_ep, -ESHUTDOWN); | |
1040 | ||
1041 | schedule_work(&musb->irq_work); | |
1042 | ||
1043 | spin_unlock_irqrestore(&(musb->lock), flags); | |
1044 | ||
1045 | DBG(2, "%s\n", musb_ep->end_point.name); | |
1046 | ||
1047 | return status; | |
1048 | } | |
1049 | ||
1050 | /* | |
1051 | * Allocate a request for an endpoint. | |
1052 | * Reused by ep0 code. | |
1053 | */ | |
1054 | struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) | |
1055 | { | |
1056 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1057 | struct musb_request *request = NULL; | |
1058 | ||
1059 | request = kzalloc(sizeof *request, gfp_flags); | |
1060 | if (request) { | |
1061 | INIT_LIST_HEAD(&request->request.list); | |
1062 | request->request.dma = DMA_ADDR_INVALID; | |
1063 | request->epnum = musb_ep->current_epnum; | |
1064 | request->ep = musb_ep; | |
1065 | } | |
1066 | ||
1067 | return &request->request; | |
1068 | } | |
1069 | ||
1070 | /* | |
1071 | * Free a request | |
1072 | * Reused by ep0 code. | |
1073 | */ | |
1074 | void musb_free_request(struct usb_ep *ep, struct usb_request *req) | |
1075 | { | |
1076 | kfree(to_musb_request(req)); | |
1077 | } | |
1078 | ||
1079 | static LIST_HEAD(buffers); | |
1080 | ||
1081 | struct free_record { | |
1082 | struct list_head list; | |
1083 | struct device *dev; | |
1084 | unsigned bytes; | |
1085 | dma_addr_t dma; | |
1086 | }; | |
1087 | ||
1088 | /* | |
1089 | * Context: controller locked, IRQs blocked. | |
1090 | */ | |
1091 | static void musb_ep_restart(struct musb *musb, struct musb_request *req) | |
1092 | { | |
1093 | DBG(3, "<== %s request %p len %u on hw_ep%d\n", | |
1094 | req->tx ? "TX/IN" : "RX/OUT", | |
1095 | &req->request, req->request.length, req->epnum); | |
1096 | ||
1097 | musb_ep_select(musb->mregs, req->epnum); | |
1098 | if (req->tx) | |
1099 | txstate(musb, req); | |
1100 | else | |
1101 | rxstate(musb, req); | |
1102 | } | |
1103 | ||
1104 | static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, | |
1105 | gfp_t gfp_flags) | |
1106 | { | |
1107 | struct musb_ep *musb_ep; | |
1108 | struct musb_request *request; | |
1109 | struct musb *musb; | |
1110 | int status = 0; | |
1111 | unsigned long lockflags; | |
1112 | ||
1113 | if (!ep || !req) | |
1114 | return -EINVAL; | |
1115 | if (!req->buf) | |
1116 | return -ENODATA; | |
1117 | ||
1118 | musb_ep = to_musb_ep(ep); | |
1119 | musb = musb_ep->musb; | |
1120 | ||
1121 | request = to_musb_request(req); | |
1122 | request->musb = musb; | |
1123 | ||
1124 | if (request->ep != musb_ep) | |
1125 | return -EINVAL; | |
1126 | ||
1127 | DBG(4, "<== to %s request=%p\n", ep->name, req); | |
1128 | ||
1129 | /* request is mine now... */ | |
1130 | request->request.actual = 0; | |
1131 | request->request.status = -EINPROGRESS; | |
1132 | request->epnum = musb_ep->current_epnum; | |
1133 | request->tx = musb_ep->is_in; | |
1134 | ||
1135 | if (is_dma_capable() && musb_ep->dma) { | |
1136 | if (request->request.dma == DMA_ADDR_INVALID) { | |
1137 | request->request.dma = dma_map_single( | |
1138 | musb->controller, | |
1139 | request->request.buf, | |
1140 | request->request.length, | |
1141 | request->tx | |
1142 | ? DMA_TO_DEVICE | |
1143 | : DMA_FROM_DEVICE); | |
1144 | request->mapped = 1; | |
1145 | } else { | |
1146 | dma_sync_single_for_device(musb->controller, | |
1147 | request->request.dma, | |
1148 | request->request.length, | |
1149 | request->tx | |
1150 | ? DMA_TO_DEVICE | |
1151 | : DMA_FROM_DEVICE); | |
1152 | request->mapped = 0; | |
1153 | } | |
1154 | } else if (!req->buf) { | |
1155 | return -ENODATA; | |
1156 | } else | |
1157 | request->mapped = 0; | |
1158 | ||
1159 | spin_lock_irqsave(&musb->lock, lockflags); | |
1160 | ||
1161 | /* don't queue if the ep is down */ | |
1162 | if (!musb_ep->desc) { | |
1163 | DBG(4, "req %p queued to %s while ep %s\n", | |
1164 | req, ep->name, "disabled"); | |
1165 | status = -ESHUTDOWN; | |
1166 | goto cleanup; | |
1167 | } | |
1168 | ||
1169 | /* add request to the list */ | |
1170 | list_add_tail(&(request->request.list), &(musb_ep->req_list)); | |
1171 | ||
1172 | /* it this is the head of the queue, start i/o ... */ | |
1173 | if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next) | |
1174 | musb_ep_restart(musb, request); | |
1175 | ||
1176 | cleanup: | |
1177 | spin_unlock_irqrestore(&musb->lock, lockflags); | |
1178 | return status; | |
1179 | } | |
1180 | ||
1181 | static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) | |
1182 | { | |
1183 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1184 | struct usb_request *r; | |
1185 | unsigned long flags; | |
1186 | int status = 0; | |
1187 | struct musb *musb = musb_ep->musb; | |
1188 | ||
1189 | if (!ep || !request || to_musb_request(request)->ep != musb_ep) | |
1190 | return -EINVAL; | |
1191 | ||
1192 | spin_lock_irqsave(&musb->lock, flags); | |
1193 | ||
1194 | list_for_each_entry(r, &musb_ep->req_list, list) { | |
1195 | if (r == request) | |
1196 | break; | |
1197 | } | |
1198 | if (r != request) { | |
1199 | DBG(3, "request %p not queued to %s\n", request, ep->name); | |
1200 | status = -EINVAL; | |
1201 | goto done; | |
1202 | } | |
1203 | ||
1204 | /* if the hardware doesn't have the request, easy ... */ | |
1205 | if (musb_ep->req_list.next != &request->list || musb_ep->busy) | |
1206 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1207 | ||
1208 | /* ... else abort the dma transfer ... */ | |
1209 | else if (is_dma_capable() && musb_ep->dma) { | |
1210 | struct dma_controller *c = musb->dma_controller; | |
1211 | ||
1212 | musb_ep_select(musb->mregs, musb_ep->current_epnum); | |
1213 | if (c->channel_abort) | |
1214 | status = c->channel_abort(musb_ep->dma); | |
1215 | else | |
1216 | status = -EBUSY; | |
1217 | if (status == 0) | |
1218 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1219 | } else { | |
1220 | /* NOTE: by sticking to easily tested hardware/driver states, | |
1221 | * we leave counting of in-flight packets imprecise. | |
1222 | */ | |
1223 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1224 | } | |
1225 | ||
1226 | done: | |
1227 | spin_unlock_irqrestore(&musb->lock, flags); | |
1228 | return status; | |
1229 | } | |
1230 | ||
1231 | /* | |
1232 | * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any | |
1233 | * data but will queue requests. | |
1234 | * | |
1235 | * exported to ep0 code | |
1236 | */ | |
1237 | int musb_gadget_set_halt(struct usb_ep *ep, int value) | |
1238 | { | |
1239 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1240 | u8 epnum = musb_ep->current_epnum; | |
1241 | struct musb *musb = musb_ep->musb; | |
1242 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1243 | void __iomem *mbase; | |
1244 | unsigned long flags; | |
1245 | u16 csr; | |
1246 | struct musb_request *request = NULL; | |
1247 | int status = 0; | |
1248 | ||
1249 | if (!ep) | |
1250 | return -EINVAL; | |
1251 | mbase = musb->mregs; | |
1252 | ||
1253 | spin_lock_irqsave(&musb->lock, flags); | |
1254 | ||
1255 | if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { | |
1256 | status = -EINVAL; | |
1257 | goto done; | |
1258 | } | |
1259 | ||
1260 | musb_ep_select(mbase, epnum); | |
1261 | ||
1262 | /* cannot portably stall with non-empty FIFO */ | |
1263 | request = to_musb_request(next_request(musb_ep)); | |
1264 | if (value && musb_ep->is_in) { | |
1265 | csr = musb_readw(epio, MUSB_TXCSR); | |
1266 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
1267 | DBG(3, "%s fifo busy, cannot halt\n", ep->name); | |
1268 | spin_unlock_irqrestore(&musb->lock, flags); | |
1269 | return -EAGAIN; | |
1270 | } | |
1271 | ||
1272 | } | |
1273 | ||
1274 | /* set/clear the stall and toggle bits */ | |
1275 | DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear"); | |
1276 | if (musb_ep->is_in) { | |
1277 | csr = musb_readw(epio, MUSB_TXCSR); | |
1278 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) | |
1279 | csr |= MUSB_TXCSR_FLUSHFIFO; | |
1280 | csr |= MUSB_TXCSR_P_WZC_BITS | |
1281 | | MUSB_TXCSR_CLRDATATOG; | |
1282 | if (value) | |
1283 | csr |= MUSB_TXCSR_P_SENDSTALL; | |
1284 | else | |
1285 | csr &= ~(MUSB_TXCSR_P_SENDSTALL | |
1286 | | MUSB_TXCSR_P_SENTSTALL); | |
1287 | csr &= ~MUSB_TXCSR_TXPKTRDY; | |
1288 | musb_writew(epio, MUSB_TXCSR, csr); | |
1289 | } else { | |
1290 | csr = musb_readw(epio, MUSB_RXCSR); | |
1291 | csr |= MUSB_RXCSR_P_WZC_BITS | |
1292 | | MUSB_RXCSR_FLUSHFIFO | |
1293 | | MUSB_RXCSR_CLRDATATOG; | |
1294 | if (value) | |
1295 | csr |= MUSB_RXCSR_P_SENDSTALL; | |
1296 | else | |
1297 | csr &= ~(MUSB_RXCSR_P_SENDSTALL | |
1298 | | MUSB_RXCSR_P_SENTSTALL); | |
1299 | musb_writew(epio, MUSB_RXCSR, csr); | |
1300 | } | |
1301 | ||
1302 | done: | |
1303 | ||
1304 | /* maybe start the first request in the queue */ | |
1305 | if (!musb_ep->busy && !value && request) { | |
1306 | DBG(3, "restarting the request\n"); | |
1307 | musb_ep_restart(musb, request); | |
1308 | } | |
1309 | ||
1310 | spin_unlock_irqrestore(&musb->lock, flags); | |
1311 | return status; | |
1312 | } | |
1313 | ||
1314 | static int musb_gadget_fifo_status(struct usb_ep *ep) | |
1315 | { | |
1316 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1317 | void __iomem *epio = musb_ep->hw_ep->regs; | |
1318 | int retval = -EINVAL; | |
1319 | ||
1320 | if (musb_ep->desc && !musb_ep->is_in) { | |
1321 | struct musb *musb = musb_ep->musb; | |
1322 | int epnum = musb_ep->current_epnum; | |
1323 | void __iomem *mbase = musb->mregs; | |
1324 | unsigned long flags; | |
1325 | ||
1326 | spin_lock_irqsave(&musb->lock, flags); | |
1327 | ||
1328 | musb_ep_select(mbase, epnum); | |
1329 | /* FIXME return zero unless RXPKTRDY is set */ | |
1330 | retval = musb_readw(epio, MUSB_RXCOUNT); | |
1331 | ||
1332 | spin_unlock_irqrestore(&musb->lock, flags); | |
1333 | } | |
1334 | return retval; | |
1335 | } | |
1336 | ||
1337 | static void musb_gadget_fifo_flush(struct usb_ep *ep) | |
1338 | { | |
1339 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1340 | struct musb *musb = musb_ep->musb; | |
1341 | u8 epnum = musb_ep->current_epnum; | |
1342 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1343 | void __iomem *mbase; | |
1344 | unsigned long flags; | |
1345 | u16 csr, int_txe; | |
1346 | ||
1347 | mbase = musb->mregs; | |
1348 | ||
1349 | spin_lock_irqsave(&musb->lock, flags); | |
1350 | musb_ep_select(mbase, (u8) epnum); | |
1351 | ||
1352 | /* disable interrupts */ | |
1353 | int_txe = musb_readw(mbase, MUSB_INTRTXE); | |
1354 | musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); | |
1355 | ||
1356 | if (musb_ep->is_in) { | |
1357 | csr = musb_readw(epio, MUSB_TXCSR); | |
1358 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
1359 | csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; | |
1360 | musb_writew(epio, MUSB_TXCSR, csr); | |
1361 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
1362 | musb_writew(epio, MUSB_TXCSR, csr); | |
1363 | } | |
1364 | } else { | |
1365 | csr = musb_readw(epio, MUSB_RXCSR); | |
1366 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; | |
1367 | musb_writew(epio, MUSB_RXCSR, csr); | |
1368 | musb_writew(epio, MUSB_RXCSR, csr); | |
1369 | } | |
1370 | ||
1371 | /* re-enable interrupt */ | |
1372 | musb_writew(mbase, MUSB_INTRTXE, int_txe); | |
1373 | spin_unlock_irqrestore(&musb->lock, flags); | |
1374 | } | |
1375 | ||
1376 | static const struct usb_ep_ops musb_ep_ops = { | |
1377 | .enable = musb_gadget_enable, | |
1378 | .disable = musb_gadget_disable, | |
1379 | .alloc_request = musb_alloc_request, | |
1380 | .free_request = musb_free_request, | |
1381 | .queue = musb_gadget_queue, | |
1382 | .dequeue = musb_gadget_dequeue, | |
1383 | .set_halt = musb_gadget_set_halt, | |
1384 | .fifo_status = musb_gadget_fifo_status, | |
1385 | .fifo_flush = musb_gadget_fifo_flush | |
1386 | }; | |
1387 | ||
1388 | /* ----------------------------------------------------------------------- */ | |
1389 | ||
1390 | static int musb_gadget_get_frame(struct usb_gadget *gadget) | |
1391 | { | |
1392 | struct musb *musb = gadget_to_musb(gadget); | |
1393 | ||
1394 | return (int)musb_readw(musb->mregs, MUSB_FRAME); | |
1395 | } | |
1396 | ||
1397 | static int musb_gadget_wakeup(struct usb_gadget *gadget) | |
1398 | { | |
1399 | struct musb *musb = gadget_to_musb(gadget); | |
1400 | void __iomem *mregs = musb->mregs; | |
1401 | unsigned long flags; | |
1402 | int status = -EINVAL; | |
1403 | u8 power, devctl; | |
1404 | int retries; | |
1405 | ||
1406 | spin_lock_irqsave(&musb->lock, flags); | |
1407 | ||
1408 | switch (musb->xceiv.state) { | |
1409 | case OTG_STATE_B_PERIPHERAL: | |
1410 | /* NOTE: OTG state machine doesn't include B_SUSPENDED; | |
1411 | * that's part of the standard usb 1.1 state machine, and | |
1412 | * doesn't affect OTG transitions. | |
1413 | */ | |
1414 | if (musb->may_wakeup && musb->is_suspended) | |
1415 | break; | |
1416 | goto done; | |
1417 | case OTG_STATE_B_IDLE: | |
1418 | /* Start SRP ... OTG not required. */ | |
1419 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1420 | DBG(2, "Sending SRP: devctl: %02x\n", devctl); | |
1421 | devctl |= MUSB_DEVCTL_SESSION; | |
1422 | musb_writeb(mregs, MUSB_DEVCTL, devctl); | |
1423 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1424 | retries = 100; | |
1425 | while (!(devctl & MUSB_DEVCTL_SESSION)) { | |
1426 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1427 | if (retries-- < 1) | |
1428 | break; | |
1429 | } | |
1430 | retries = 10000; | |
1431 | while (devctl & MUSB_DEVCTL_SESSION) { | |
1432 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1433 | if (retries-- < 1) | |
1434 | break; | |
1435 | } | |
1436 | ||
1437 | /* Block idling for at least 1s */ | |
1438 | musb_platform_try_idle(musb, | |
1439 | jiffies + msecs_to_jiffies(1 * HZ)); | |
1440 | ||
1441 | status = 0; | |
1442 | goto done; | |
1443 | default: | |
1444 | DBG(2, "Unhandled wake: %s\n", otg_state_string(musb)); | |
1445 | goto done; | |
1446 | } | |
1447 | ||
1448 | status = 0; | |
1449 | ||
1450 | power = musb_readb(mregs, MUSB_POWER); | |
1451 | power |= MUSB_POWER_RESUME; | |
1452 | musb_writeb(mregs, MUSB_POWER, power); | |
1453 | DBG(2, "issue wakeup\n"); | |
1454 | ||
1455 | /* FIXME do this next chunk in a timer callback, no udelay */ | |
1456 | mdelay(2); | |
1457 | ||
1458 | power = musb_readb(mregs, MUSB_POWER); | |
1459 | power &= ~MUSB_POWER_RESUME; | |
1460 | musb_writeb(mregs, MUSB_POWER, power); | |
1461 | done: | |
1462 | spin_unlock_irqrestore(&musb->lock, flags); | |
1463 | return status; | |
1464 | } | |
1465 | ||
1466 | static int | |
1467 | musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) | |
1468 | { | |
1469 | struct musb *musb = gadget_to_musb(gadget); | |
1470 | ||
1471 | musb->is_self_powered = !!is_selfpowered; | |
1472 | return 0; | |
1473 | } | |
1474 | ||
1475 | static void musb_pullup(struct musb *musb, int is_on) | |
1476 | { | |
1477 | u8 power; | |
1478 | ||
1479 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1480 | if (is_on) | |
1481 | power |= MUSB_POWER_SOFTCONN; | |
1482 | else | |
1483 | power &= ~MUSB_POWER_SOFTCONN; | |
1484 | ||
1485 | /* FIXME if on, HdrcStart; if off, HdrcStop */ | |
1486 | ||
1487 | DBG(3, "gadget %s D+ pullup %s\n", | |
1488 | musb->gadget_driver->function, is_on ? "on" : "off"); | |
1489 | musb_writeb(musb->mregs, MUSB_POWER, power); | |
1490 | } | |
1491 | ||
1492 | #if 0 | |
1493 | static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) | |
1494 | { | |
1495 | DBG(2, "<= %s =>\n", __func__); | |
1496 | ||
1497 | /* | |
1498 | * FIXME iff driver's softconnect flag is set (as it is during probe, | |
1499 | * though that can clear it), just musb_pullup(). | |
1500 | */ | |
1501 | ||
1502 | return -EINVAL; | |
1503 | } | |
1504 | #endif | |
1505 | ||
1506 | static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1507 | { | |
1508 | struct musb *musb = gadget_to_musb(gadget); | |
1509 | ||
1510 | if (!musb->xceiv.set_power) | |
1511 | return -EOPNOTSUPP; | |
1512 | return otg_set_power(&musb->xceiv, mA); | |
1513 | } | |
1514 | ||
1515 | static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) | |
1516 | { | |
1517 | struct musb *musb = gadget_to_musb(gadget); | |
1518 | unsigned long flags; | |
1519 | ||
1520 | is_on = !!is_on; | |
1521 | ||
1522 | /* NOTE: this assumes we are sensing vbus; we'd rather | |
1523 | * not pullup unless the B-session is active. | |
1524 | */ | |
1525 | spin_lock_irqsave(&musb->lock, flags); | |
1526 | if (is_on != musb->softconnect) { | |
1527 | musb->softconnect = is_on; | |
1528 | musb_pullup(musb, is_on); | |
1529 | } | |
1530 | spin_unlock_irqrestore(&musb->lock, flags); | |
1531 | return 0; | |
1532 | } | |
1533 | ||
1534 | static const struct usb_gadget_ops musb_gadget_operations = { | |
1535 | .get_frame = musb_gadget_get_frame, | |
1536 | .wakeup = musb_gadget_wakeup, | |
1537 | .set_selfpowered = musb_gadget_set_self_powered, | |
1538 | /* .vbus_session = musb_gadget_vbus_session, */ | |
1539 | .vbus_draw = musb_gadget_vbus_draw, | |
1540 | .pullup = musb_gadget_pullup, | |
1541 | }; | |
1542 | ||
1543 | /* ----------------------------------------------------------------------- */ | |
1544 | ||
1545 | /* Registration */ | |
1546 | ||
1547 | /* Only this registration code "knows" the rule (from USB standards) | |
1548 | * about there being only one external upstream port. It assumes | |
1549 | * all peripheral ports are external... | |
1550 | */ | |
1551 | static struct musb *the_gadget; | |
1552 | ||
1553 | static void musb_gadget_release(struct device *dev) | |
1554 | { | |
1555 | /* kref_put(WHAT) */ | |
1556 | dev_dbg(dev, "%s\n", __func__); | |
1557 | } | |
1558 | ||
1559 | ||
1560 | static void __init | |
1561 | init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) | |
1562 | { | |
1563 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
1564 | ||
1565 | memset(ep, 0, sizeof *ep); | |
1566 | ||
1567 | ep->current_epnum = epnum; | |
1568 | ep->musb = musb; | |
1569 | ep->hw_ep = hw_ep; | |
1570 | ep->is_in = is_in; | |
1571 | ||
1572 | INIT_LIST_HEAD(&ep->req_list); | |
1573 | ||
1574 | sprintf(ep->name, "ep%d%s", epnum, | |
1575 | (!epnum || hw_ep->is_shared_fifo) ? "" : ( | |
1576 | is_in ? "in" : "out")); | |
1577 | ep->end_point.name = ep->name; | |
1578 | INIT_LIST_HEAD(&ep->end_point.ep_list); | |
1579 | if (!epnum) { | |
1580 | ep->end_point.maxpacket = 64; | |
1581 | ep->end_point.ops = &musb_g_ep0_ops; | |
1582 | musb->g.ep0 = &ep->end_point; | |
1583 | } else { | |
1584 | if (is_in) | |
1585 | ep->end_point.maxpacket = hw_ep->max_packet_sz_tx; | |
1586 | else | |
1587 | ep->end_point.maxpacket = hw_ep->max_packet_sz_rx; | |
1588 | ep->end_point.ops = &musb_ep_ops; | |
1589 | list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); | |
1590 | } | |
1591 | } | |
1592 | ||
1593 | /* | |
1594 | * Initialize the endpoints exposed to peripheral drivers, with backlinks | |
1595 | * to the rest of the driver state. | |
1596 | */ | |
1597 | static inline void __init musb_g_init_endpoints(struct musb *musb) | |
1598 | { | |
1599 | u8 epnum; | |
1600 | struct musb_hw_ep *hw_ep; | |
1601 | unsigned count = 0; | |
1602 | ||
1603 | /* intialize endpoint list just once */ | |
1604 | INIT_LIST_HEAD(&(musb->g.ep_list)); | |
1605 | ||
1606 | for (epnum = 0, hw_ep = musb->endpoints; | |
1607 | epnum < musb->nr_endpoints; | |
1608 | epnum++, hw_ep++) { | |
1609 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1610 | init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); | |
1611 | count++; | |
1612 | } else { | |
1613 | if (hw_ep->max_packet_sz_tx) { | |
1614 | init_peripheral_ep(musb, &hw_ep->ep_in, | |
1615 | epnum, 1); | |
1616 | count++; | |
1617 | } | |
1618 | if (hw_ep->max_packet_sz_rx) { | |
1619 | init_peripheral_ep(musb, &hw_ep->ep_out, | |
1620 | epnum, 0); | |
1621 | count++; | |
1622 | } | |
1623 | } | |
1624 | } | |
1625 | } | |
1626 | ||
1627 | /* called once during driver setup to initialize and link into | |
1628 | * the driver model; memory is zeroed. | |
1629 | */ | |
1630 | int __init musb_gadget_setup(struct musb *musb) | |
1631 | { | |
1632 | int status; | |
1633 | ||
1634 | /* REVISIT minor race: if (erroneously) setting up two | |
1635 | * musb peripherals at the same time, only the bus lock | |
1636 | * is probably held. | |
1637 | */ | |
1638 | if (the_gadget) | |
1639 | return -EBUSY; | |
1640 | the_gadget = musb; | |
1641 | ||
1642 | musb->g.ops = &musb_gadget_operations; | |
1643 | musb->g.is_dualspeed = 1; | |
1644 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1645 | ||
1646 | /* this "gadget" abstracts/virtualizes the controller */ | |
427c4f33 | 1647 | dev_set_name(&musb->g.dev, "gadget"); |
550a7375 FB |
1648 | musb->g.dev.parent = musb->controller; |
1649 | musb->g.dev.dma_mask = musb->controller->dma_mask; | |
1650 | musb->g.dev.release = musb_gadget_release; | |
1651 | musb->g.name = musb_driver_name; | |
1652 | ||
1653 | if (is_otg_enabled(musb)) | |
1654 | musb->g.is_otg = 1; | |
1655 | ||
1656 | musb_g_init_endpoints(musb); | |
1657 | ||
1658 | musb->is_active = 0; | |
1659 | musb_platform_try_idle(musb, 0); | |
1660 | ||
1661 | status = device_register(&musb->g.dev); | |
1662 | if (status != 0) | |
1663 | the_gadget = NULL; | |
1664 | return status; | |
1665 | } | |
1666 | ||
1667 | void musb_gadget_cleanup(struct musb *musb) | |
1668 | { | |
1669 | if (musb != the_gadget) | |
1670 | return; | |
1671 | ||
1672 | device_unregister(&musb->g.dev); | |
1673 | the_gadget = NULL; | |
1674 | } | |
1675 | ||
1676 | /* | |
1677 | * Register the gadget driver. Used by gadget drivers when | |
1678 | * registering themselves with the controller. | |
1679 | * | |
1680 | * -EINVAL something went wrong (not driver) | |
1681 | * -EBUSY another gadget is already using the controller | |
1682 | * -ENOMEM no memeory to perform the operation | |
1683 | * | |
1684 | * @param driver the gadget driver | |
1685 | * @return <0 if error, 0 if everything is fine | |
1686 | */ | |
1687 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) | |
1688 | { | |
1689 | int retval; | |
1690 | unsigned long flags; | |
1691 | struct musb *musb = the_gadget; | |
1692 | ||
1693 | if (!driver | |
1694 | || driver->speed != USB_SPEED_HIGH | |
1695 | || !driver->bind | |
1696 | || !driver->setup) | |
1697 | return -EINVAL; | |
1698 | ||
1699 | /* driver must be initialized to support peripheral mode */ | |
1700 | if (!musb || !(musb->board_mode == MUSB_OTG | |
1701 | || musb->board_mode != MUSB_OTG)) { | |
1702 | DBG(1, "%s, no dev??\n", __func__); | |
1703 | return -ENODEV; | |
1704 | } | |
1705 | ||
1706 | DBG(3, "registering driver %s\n", driver->function); | |
1707 | spin_lock_irqsave(&musb->lock, flags); | |
1708 | ||
1709 | if (musb->gadget_driver) { | |
1710 | DBG(1, "%s is already bound to %s\n", | |
1711 | musb_driver_name, | |
1712 | musb->gadget_driver->driver.name); | |
1713 | retval = -EBUSY; | |
1714 | } else { | |
1715 | musb->gadget_driver = driver; | |
1716 | musb->g.dev.driver = &driver->driver; | |
1717 | driver->driver.bus = NULL; | |
1718 | musb->softconnect = 1; | |
1719 | retval = 0; | |
1720 | } | |
1721 | ||
1722 | spin_unlock_irqrestore(&musb->lock, flags); | |
1723 | ||
f362a475 | 1724 | if (retval == 0) { |
550a7375 | 1725 | retval = driver->bind(&musb->g); |
f362a475 FB |
1726 | if (retval != 0) { |
1727 | DBG(3, "bind to driver %s failed --> %d\n", | |
1728 | driver->driver.name, retval); | |
1729 | musb->gadget_driver = NULL; | |
1730 | musb->g.dev.driver = NULL; | |
1731 | } | |
550a7375 | 1732 | |
550a7375 FB |
1733 | spin_lock_irqsave(&musb->lock, flags); |
1734 | ||
1735 | /* REVISIT always use otg_set_peripheral(), handling | |
1736 | * issues including the root hub one below ... | |
1737 | */ | |
1738 | musb->xceiv.gadget = &musb->g; | |
1739 | musb->xceiv.state = OTG_STATE_B_IDLE; | |
1740 | musb->is_active = 1; | |
1741 | ||
1742 | /* FIXME this ignores the softconnect flag. Drivers are | |
1743 | * allowed hold the peripheral inactive until for example | |
1744 | * userspace hooks up printer hardware or DSP codecs, so | |
1745 | * hosts only see fully functional devices. | |
1746 | */ | |
1747 | ||
1748 | if (!is_otg_enabled(musb)) | |
1749 | musb_start(musb); | |
1750 | ||
1751 | spin_unlock_irqrestore(&musb->lock, flags); | |
1752 | ||
1753 | if (is_otg_enabled(musb)) { | |
1754 | DBG(3, "OTG startup...\n"); | |
1755 | ||
1756 | /* REVISIT: funcall to other code, which also | |
1757 | * handles power budgeting ... this way also | |
1758 | * ensures HdrcStart is indirectly called. | |
1759 | */ | |
1760 | retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); | |
1761 | if (retval < 0) { | |
1762 | DBG(1, "add_hcd failed, %d\n", retval); | |
1763 | spin_lock_irqsave(&musb->lock, flags); | |
1764 | musb->xceiv.gadget = NULL; | |
1765 | musb->xceiv.state = OTG_STATE_UNDEFINED; | |
1766 | musb->gadget_driver = NULL; | |
1767 | musb->g.dev.driver = NULL; | |
1768 | spin_unlock_irqrestore(&musb->lock, flags); | |
1769 | } | |
1770 | } | |
1771 | } | |
1772 | ||
1773 | return retval; | |
1774 | } | |
1775 | EXPORT_SYMBOL(usb_gadget_register_driver); | |
1776 | ||
1777 | static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver) | |
1778 | { | |
1779 | int i; | |
1780 | struct musb_hw_ep *hw_ep; | |
1781 | ||
1782 | /* don't disconnect if it's not connected */ | |
1783 | if (musb->g.speed == USB_SPEED_UNKNOWN) | |
1784 | driver = NULL; | |
1785 | else | |
1786 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1787 | ||
1788 | /* deactivate the hardware */ | |
1789 | if (musb->softconnect) { | |
1790 | musb->softconnect = 0; | |
1791 | musb_pullup(musb, 0); | |
1792 | } | |
1793 | musb_stop(musb); | |
1794 | ||
1795 | /* killing any outstanding requests will quiesce the driver; | |
1796 | * then report disconnect | |
1797 | */ | |
1798 | if (driver) { | |
1799 | for (i = 0, hw_ep = musb->endpoints; | |
1800 | i < musb->nr_endpoints; | |
1801 | i++, hw_ep++) { | |
1802 | musb_ep_select(musb->mregs, i); | |
1803 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1804 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
1805 | } else { | |
1806 | if (hw_ep->max_packet_sz_tx) | |
1807 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
1808 | if (hw_ep->max_packet_sz_rx) | |
1809 | nuke(&hw_ep->ep_out, -ESHUTDOWN); | |
1810 | } | |
1811 | } | |
1812 | ||
1813 | spin_unlock(&musb->lock); | |
1814 | driver->disconnect(&musb->g); | |
1815 | spin_lock(&musb->lock); | |
1816 | } | |
1817 | } | |
1818 | ||
1819 | /* | |
1820 | * Unregister the gadget driver. Used by gadget drivers when | |
1821 | * unregistering themselves from the controller. | |
1822 | * | |
1823 | * @param driver the gadget driver to unregister | |
1824 | */ | |
1825 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) | |
1826 | { | |
1827 | unsigned long flags; | |
1828 | int retval = 0; | |
1829 | struct musb *musb = the_gadget; | |
1830 | ||
1831 | if (!driver || !driver->unbind || !musb) | |
1832 | return -EINVAL; | |
1833 | ||
1834 | /* REVISIT always use otg_set_peripheral() here too; | |
1835 | * this needs to shut down the OTG engine. | |
1836 | */ | |
1837 | ||
1838 | spin_lock_irqsave(&musb->lock, flags); | |
1839 | ||
1840 | #ifdef CONFIG_USB_MUSB_OTG | |
1841 | musb_hnp_stop(musb); | |
1842 | #endif | |
1843 | ||
1844 | if (musb->gadget_driver == driver) { | |
1845 | ||
1846 | (void) musb_gadget_vbus_draw(&musb->g, 0); | |
1847 | ||
1848 | musb->xceiv.state = OTG_STATE_UNDEFINED; | |
1849 | stop_activity(musb, driver); | |
1850 | ||
1851 | DBG(3, "unregistering driver %s\n", driver->function); | |
1852 | spin_unlock_irqrestore(&musb->lock, flags); | |
1853 | driver->unbind(&musb->g); | |
1854 | spin_lock_irqsave(&musb->lock, flags); | |
1855 | ||
1856 | musb->gadget_driver = NULL; | |
1857 | musb->g.dev.driver = NULL; | |
1858 | ||
1859 | musb->is_active = 0; | |
1860 | musb_platform_try_idle(musb, 0); | |
1861 | } else | |
1862 | retval = -EINVAL; | |
1863 | spin_unlock_irqrestore(&musb->lock, flags); | |
1864 | ||
1865 | if (is_otg_enabled(musb) && retval == 0) { | |
1866 | usb_remove_hcd(musb_to_hcd(musb)); | |
1867 | /* FIXME we need to be able to register another | |
1868 | * gadget driver here and have everything work; | |
1869 | * that currently misbehaves. | |
1870 | */ | |
1871 | } | |
1872 | ||
1873 | return retval; | |
1874 | } | |
1875 | EXPORT_SYMBOL(usb_gadget_unregister_driver); | |
1876 | ||
1877 | ||
1878 | /* ----------------------------------------------------------------------- */ | |
1879 | ||
1880 | /* lifecycle operations called through plat_uds.c */ | |
1881 | ||
1882 | void musb_g_resume(struct musb *musb) | |
1883 | { | |
1884 | musb->is_suspended = 0; | |
1885 | switch (musb->xceiv.state) { | |
1886 | case OTG_STATE_B_IDLE: | |
1887 | break; | |
1888 | case OTG_STATE_B_WAIT_ACON: | |
1889 | case OTG_STATE_B_PERIPHERAL: | |
1890 | musb->is_active = 1; | |
1891 | if (musb->gadget_driver && musb->gadget_driver->resume) { | |
1892 | spin_unlock(&musb->lock); | |
1893 | musb->gadget_driver->resume(&musb->g); | |
1894 | spin_lock(&musb->lock); | |
1895 | } | |
1896 | break; | |
1897 | default: | |
1898 | WARNING("unhandled RESUME transition (%s)\n", | |
1899 | otg_state_string(musb)); | |
1900 | } | |
1901 | } | |
1902 | ||
1903 | /* called when SOF packets stop for 3+ msec */ | |
1904 | void musb_g_suspend(struct musb *musb) | |
1905 | { | |
1906 | u8 devctl; | |
1907 | ||
1908 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1909 | DBG(3, "devctl %02x\n", devctl); | |
1910 | ||
1911 | switch (musb->xceiv.state) { | |
1912 | case OTG_STATE_B_IDLE: | |
1913 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
1914 | musb->xceiv.state = OTG_STATE_B_PERIPHERAL; | |
1915 | break; | |
1916 | case OTG_STATE_B_PERIPHERAL: | |
1917 | musb->is_suspended = 1; | |
1918 | if (musb->gadget_driver && musb->gadget_driver->suspend) { | |
1919 | spin_unlock(&musb->lock); | |
1920 | musb->gadget_driver->suspend(&musb->g); | |
1921 | spin_lock(&musb->lock); | |
1922 | } | |
1923 | break; | |
1924 | default: | |
1925 | /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; | |
1926 | * A_PERIPHERAL may need care too | |
1927 | */ | |
1928 | WARNING("unhandled SUSPEND transition (%s)\n", | |
1929 | otg_state_string(musb)); | |
1930 | } | |
1931 | } | |
1932 | ||
1933 | /* Called during SRP */ | |
1934 | void musb_g_wakeup(struct musb *musb) | |
1935 | { | |
1936 | musb_gadget_wakeup(&musb->g); | |
1937 | } | |
1938 | ||
1939 | /* called when VBUS drops below session threshold, and in other cases */ | |
1940 | void musb_g_disconnect(struct musb *musb) | |
1941 | { | |
1942 | void __iomem *mregs = musb->mregs; | |
1943 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1944 | ||
1945 | DBG(3, "devctl %02x\n", devctl); | |
1946 | ||
1947 | /* clear HR */ | |
1948 | musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); | |
1949 | ||
1950 | /* don't draw vbus until new b-default session */ | |
1951 | (void) musb_gadget_vbus_draw(&musb->g, 0); | |
1952 | ||
1953 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1954 | if (musb->gadget_driver && musb->gadget_driver->disconnect) { | |
1955 | spin_unlock(&musb->lock); | |
1956 | musb->gadget_driver->disconnect(&musb->g); | |
1957 | spin_lock(&musb->lock); | |
1958 | } | |
1959 | ||
1960 | switch (musb->xceiv.state) { | |
1961 | default: | |
1962 | #ifdef CONFIG_USB_MUSB_OTG | |
1963 | DBG(2, "Unhandled disconnect %s, setting a_idle\n", | |
1964 | otg_state_string(musb)); | |
1965 | musb->xceiv.state = OTG_STATE_A_IDLE; | |
1966 | break; | |
1967 | case OTG_STATE_A_PERIPHERAL: | |
1968 | musb->xceiv.state = OTG_STATE_A_WAIT_VFALL; | |
1969 | break; | |
1970 | case OTG_STATE_B_WAIT_ACON: | |
1971 | case OTG_STATE_B_HOST: | |
1972 | #endif | |
1973 | case OTG_STATE_B_PERIPHERAL: | |
1974 | case OTG_STATE_B_IDLE: | |
1975 | musb->xceiv.state = OTG_STATE_B_IDLE; | |
1976 | break; | |
1977 | case OTG_STATE_B_SRP_INIT: | |
1978 | break; | |
1979 | } | |
1980 | ||
1981 | musb->is_active = 0; | |
1982 | } | |
1983 | ||
1984 | void musb_g_reset(struct musb *musb) | |
1985 | __releases(musb->lock) | |
1986 | __acquires(musb->lock) | |
1987 | { | |
1988 | void __iomem *mbase = musb->mregs; | |
1989 | u8 devctl = musb_readb(mbase, MUSB_DEVCTL); | |
1990 | u8 power; | |
1991 | ||
1992 | DBG(3, "<== %s addr=%x driver '%s'\n", | |
1993 | (devctl & MUSB_DEVCTL_BDEVICE) | |
1994 | ? "B-Device" : "A-Device", | |
1995 | musb_readb(mbase, MUSB_FADDR), | |
1996 | musb->gadget_driver | |
1997 | ? musb->gadget_driver->driver.name | |
1998 | : NULL | |
1999 | ); | |
2000 | ||
2001 | /* report disconnect, if we didn't already (flushing EP state) */ | |
2002 | if (musb->g.speed != USB_SPEED_UNKNOWN) | |
2003 | musb_g_disconnect(musb); | |
2004 | ||
2005 | /* clear HR */ | |
2006 | else if (devctl & MUSB_DEVCTL_HR) | |
2007 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
2008 | ||
2009 | ||
2010 | /* what speed did we negotiate? */ | |
2011 | power = musb_readb(mbase, MUSB_POWER); | |
2012 | musb->g.speed = (power & MUSB_POWER_HSMODE) | |
2013 | ? USB_SPEED_HIGH : USB_SPEED_FULL; | |
2014 | ||
2015 | /* start in USB_STATE_DEFAULT */ | |
2016 | musb->is_active = 1; | |
2017 | musb->is_suspended = 0; | |
2018 | MUSB_DEV_MODE(musb); | |
2019 | musb->address = 0; | |
2020 | musb->ep0_state = MUSB_EP0_STAGE_SETUP; | |
2021 | ||
2022 | musb->may_wakeup = 0; | |
2023 | musb->g.b_hnp_enable = 0; | |
2024 | musb->g.a_alt_hnp_support = 0; | |
2025 | musb->g.a_hnp_support = 0; | |
2026 | ||
2027 | /* Normal reset, as B-Device; | |
2028 | * or else after HNP, as A-Device | |
2029 | */ | |
2030 | if (devctl & MUSB_DEVCTL_BDEVICE) { | |
2031 | musb->xceiv.state = OTG_STATE_B_PERIPHERAL; | |
2032 | musb->g.is_a_peripheral = 0; | |
2033 | } else if (is_otg_enabled(musb)) { | |
2034 | musb->xceiv.state = OTG_STATE_A_PERIPHERAL; | |
2035 | musb->g.is_a_peripheral = 1; | |
2036 | } else | |
2037 | WARN_ON(1); | |
2038 | ||
2039 | /* start with default limits on VBUS power draw */ | |
2040 | (void) musb_gadget_vbus_draw(&musb->g, | |
2041 | is_otg_enabled(musb) ? 8 : 100); | |
2042 | } |