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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver host support | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | #include <linux/module.h> | |
36 | #include <linux/kernel.h> | |
37 | #include <linux/delay.h> | |
38 | #include <linux/sched.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/errno.h> | |
41 | #include <linux/init.h> | |
42 | #include <linux/list.h> | |
43 | ||
44 | #include "musb_core.h" | |
45 | #include "musb_host.h" | |
46 | ||
47 | ||
48 | /* MUSB HOST status 22-mar-2006 | |
49 | * | |
50 | * - There's still lots of partial code duplication for fault paths, so | |
51 | * they aren't handled as consistently as they need to be. | |
52 | * | |
53 | * - PIO mostly behaved when last tested. | |
54 | * + including ep0, with all usbtest cases 9, 10 | |
55 | * + usbtest 14 (ep0out) doesn't seem to run at all | |
56 | * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest | |
57 | * configurations, but otherwise double buffering passes basic tests. | |
58 | * + for 2.6.N, for N > ~10, needs API changes for hcd framework. | |
59 | * | |
60 | * - DMA (CPPI) ... partially behaves, not currently recommended | |
61 | * + about 1/15 the speed of typical EHCI implementations (PCI) | |
62 | * + RX, all too often reqpkt seems to misbehave after tx | |
63 | * + TX, no known issues (other than evident silicon issue) | |
64 | * | |
65 | * - DMA (Mentor/OMAP) ...has at least toggle update problems | |
66 | * | |
67 | * - Still no traffic scheduling code to make NAKing for bulk or control | |
68 | * transfers unable to starve other requests; or to make efficient use | |
69 | * of hardware with periodic transfers. (Note that network drivers | |
70 | * commonly post bulk reads that stay pending for a long time; these | |
71 | * would make very visible trouble.) | |
72 | * | |
73 | * - Not tested with HNP, but some SRP paths seem to behave. | |
74 | * | |
75 | * NOTE 24-August-2006: | |
76 | * | |
77 | * - Bulk traffic finally uses both sides of hardware ep1, freeing up an | |
78 | * extra endpoint for periodic use enabling hub + keybd + mouse. That | |
79 | * mostly works, except that with "usbnet" it's easy to trigger cases | |
80 | * with "ping" where RX loses. (a) ping to davinci, even "ping -f", | |
81 | * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses | |
82 | * although ARP RX wins. (That test was done with a full speed link.) | |
83 | */ | |
84 | ||
85 | ||
86 | /* | |
87 | * NOTE on endpoint usage: | |
88 | * | |
89 | * CONTROL transfers all go through ep0. BULK ones go through dedicated IN | |
90 | * and OUT endpoints ... hardware is dedicated for those "async" queue(s). | |
91 | * | |
92 | * (Yes, bulk _could_ use more of the endpoints than that, and would even | |
93 | * benefit from it ... one remote device may easily be NAKing while others | |
94 | * need to perform transfers in that same direction. The same thing could | |
95 | * be done in software though, assuming dma cooperates.) | |
96 | * | |
97 | * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. | |
98 | * So far that scheduling is both dumb and optimistic: the endpoint will be | |
99 | * "claimed" until its software queue is no longer refilled. No multiplexing | |
100 | * of transfers between endpoints, or anything clever. | |
101 | */ | |
102 | ||
103 | ||
104 | static void musb_ep_program(struct musb *musb, u8 epnum, | |
105 | struct urb *urb, unsigned int nOut, | |
106 | u8 *buf, u32 len); | |
107 | ||
108 | /* | |
109 | * Clear TX fifo. Needed to avoid BABBLE errors. | |
110 | */ | |
c767c1c6 | 111 | static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) |
550a7375 FB |
112 | { |
113 | void __iomem *epio = ep->regs; | |
114 | u16 csr; | |
bb1c9ef1 | 115 | u16 lastcsr = 0; |
550a7375 FB |
116 | int retries = 1000; |
117 | ||
118 | csr = musb_readw(epio, MUSB_TXCSR); | |
119 | while (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
bb1c9ef1 DB |
120 | if (csr != lastcsr) |
121 | DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr); | |
122 | lastcsr = csr; | |
550a7375 FB |
123 | csr |= MUSB_TXCSR_FLUSHFIFO; |
124 | musb_writew(epio, MUSB_TXCSR, csr); | |
125 | csr = musb_readw(epio, MUSB_TXCSR); | |
bb1c9ef1 DB |
126 | if (WARN(retries-- < 1, |
127 | "Could not flush host TX%d fifo: csr: %04x\n", | |
128 | ep->epnum, csr)) | |
550a7375 | 129 | return; |
550a7375 FB |
130 | mdelay(1); |
131 | } | |
132 | } | |
133 | ||
134 | /* | |
135 | * Start transmit. Caller is responsible for locking shared resources. | |
136 | * musb must be locked. | |
137 | */ | |
138 | static inline void musb_h_tx_start(struct musb_hw_ep *ep) | |
139 | { | |
140 | u16 txcsr; | |
141 | ||
142 | /* NOTE: no locks here; caller should lock and select EP */ | |
143 | if (ep->epnum) { | |
144 | txcsr = musb_readw(ep->regs, MUSB_TXCSR); | |
145 | txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; | |
146 | musb_writew(ep->regs, MUSB_TXCSR, txcsr); | |
147 | } else { | |
148 | txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; | |
149 | musb_writew(ep->regs, MUSB_CSR0, txcsr); | |
150 | } | |
151 | ||
152 | } | |
153 | ||
154 | static inline void cppi_host_txdma_start(struct musb_hw_ep *ep) | |
155 | { | |
156 | u16 txcsr; | |
157 | ||
158 | /* NOTE: no locks here; caller should lock and select EP */ | |
159 | txcsr = musb_readw(ep->regs, MUSB_TXCSR); | |
160 | txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; | |
161 | musb_writew(ep->regs, MUSB_TXCSR, txcsr); | |
162 | } | |
163 | ||
164 | /* | |
165 | * Start the URB at the front of an endpoint's queue | |
166 | * end must be claimed from the caller. | |
167 | * | |
168 | * Context: controller locked, irqs blocked | |
169 | */ | |
170 | static void | |
171 | musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) | |
172 | { | |
173 | u16 frame; | |
174 | u32 len; | |
175 | void *buf; | |
176 | void __iomem *mbase = musb->mregs; | |
177 | struct urb *urb = next_urb(qh); | |
178 | struct musb_hw_ep *hw_ep = qh->hw_ep; | |
179 | unsigned pipe = urb->pipe; | |
180 | u8 address = usb_pipedevice(pipe); | |
181 | int epnum = hw_ep->epnum; | |
182 | ||
183 | /* initialize software qh state */ | |
184 | qh->offset = 0; | |
185 | qh->segsize = 0; | |
186 | ||
187 | /* gather right source of data */ | |
188 | switch (qh->type) { | |
189 | case USB_ENDPOINT_XFER_CONTROL: | |
190 | /* control transfers always start with SETUP */ | |
191 | is_in = 0; | |
192 | hw_ep->out_qh = qh; | |
193 | musb->ep0_stage = MUSB_EP0_START; | |
194 | buf = urb->setup_packet; | |
195 | len = 8; | |
196 | break; | |
197 | case USB_ENDPOINT_XFER_ISOC: | |
198 | qh->iso_idx = 0; | |
199 | qh->frame = 0; | |
200 | buf = urb->transfer_buffer + urb->iso_frame_desc[0].offset; | |
201 | len = urb->iso_frame_desc[0].length; | |
202 | break; | |
203 | default: /* bulk, interrupt */ | |
204 | buf = urb->transfer_buffer; | |
205 | len = urb->transfer_buffer_length; | |
206 | } | |
207 | ||
208 | DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", | |
209 | qh, urb, address, qh->epnum, | |
210 | is_in ? "in" : "out", | |
211 | ({char *s; switch (qh->type) { | |
212 | case USB_ENDPOINT_XFER_CONTROL: s = ""; break; | |
213 | case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break; | |
214 | case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break; | |
215 | default: s = "-intr"; break; | |
216 | }; s; }), | |
217 | epnum, buf, len); | |
218 | ||
219 | /* Configure endpoint */ | |
220 | if (is_in || hw_ep->is_shared_fifo) | |
221 | hw_ep->in_qh = qh; | |
222 | else | |
223 | hw_ep->out_qh = qh; | |
224 | musb_ep_program(musb, epnum, urb, !is_in, buf, len); | |
225 | ||
226 | /* transmit may have more work: start it when it is time */ | |
227 | if (is_in) | |
228 | return; | |
229 | ||
230 | /* determine if the time is right for a periodic transfer */ | |
231 | switch (qh->type) { | |
232 | case USB_ENDPOINT_XFER_ISOC: | |
233 | case USB_ENDPOINT_XFER_INT: | |
234 | DBG(3, "check whether there's still time for periodic Tx\n"); | |
235 | qh->iso_idx = 0; | |
236 | frame = musb_readw(mbase, MUSB_FRAME); | |
237 | /* FIXME this doesn't implement that scheduling policy ... | |
238 | * or handle framecounter wrapping | |
239 | */ | |
240 | if ((urb->transfer_flags & URB_ISO_ASAP) | |
241 | || (frame >= urb->start_frame)) { | |
242 | /* REVISIT the SOF irq handler shouldn't duplicate | |
243 | * this code; and we don't init urb->start_frame... | |
244 | */ | |
245 | qh->frame = 0; | |
246 | goto start; | |
247 | } else { | |
248 | qh->frame = urb->start_frame; | |
249 | /* enable SOF interrupt so we can count down */ | |
250 | DBG(1, "SOF for %d\n", epnum); | |
251 | #if 1 /* ifndef CONFIG_ARCH_DAVINCI */ | |
252 | musb_writeb(mbase, MUSB_INTRUSBE, 0xff); | |
253 | #endif | |
254 | } | |
255 | break; | |
256 | default: | |
257 | start: | |
258 | DBG(4, "Start TX%d %s\n", epnum, | |
259 | hw_ep->tx_channel ? "dma" : "pio"); | |
260 | ||
261 | if (!hw_ep->tx_channel) | |
262 | musb_h_tx_start(hw_ep); | |
263 | else if (is_cppi_enabled() || tusb_dma_omap()) | |
264 | cppi_host_txdma_start(hw_ep); | |
265 | } | |
266 | } | |
267 | ||
268 | /* caller owns controller lock, irqs are blocked */ | |
269 | static void | |
270 | __musb_giveback(struct musb *musb, struct urb *urb, int status) | |
271 | __releases(musb->lock) | |
272 | __acquires(musb->lock) | |
273 | { | |
bb1c9ef1 | 274 | DBG(({ int level; switch (status) { |
550a7375 FB |
275 | case 0: |
276 | level = 4; | |
277 | break; | |
278 | /* common/boring faults */ | |
279 | case -EREMOTEIO: | |
280 | case -ESHUTDOWN: | |
281 | case -ECONNRESET: | |
282 | case -EPIPE: | |
283 | level = 3; | |
284 | break; | |
285 | default: | |
286 | level = 2; | |
287 | break; | |
288 | }; level; }), | |
bb1c9ef1 DB |
289 | "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n", |
290 | urb, urb->complete, status, | |
550a7375 FB |
291 | usb_pipedevice(urb->pipe), |
292 | usb_pipeendpoint(urb->pipe), | |
293 | usb_pipein(urb->pipe) ? "in" : "out", | |
294 | urb->actual_length, urb->transfer_buffer_length | |
295 | ); | |
296 | ||
2492e674 | 297 | usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb); |
550a7375 FB |
298 | spin_unlock(&musb->lock); |
299 | usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status); | |
300 | spin_lock(&musb->lock); | |
301 | } | |
302 | ||
303 | /* for bulk/interrupt endpoints only */ | |
304 | static inline void | |
305 | musb_save_toggle(struct musb_hw_ep *ep, int is_in, struct urb *urb) | |
306 | { | |
307 | struct usb_device *udev = urb->dev; | |
308 | u16 csr; | |
309 | void __iomem *epio = ep->regs; | |
310 | struct musb_qh *qh; | |
311 | ||
312 | /* FIXME: the current Mentor DMA code seems to have | |
313 | * problems getting toggle correct. | |
314 | */ | |
315 | ||
316 | if (is_in || ep->is_shared_fifo) | |
317 | qh = ep->in_qh; | |
318 | else | |
319 | qh = ep->out_qh; | |
320 | ||
321 | if (!is_in) { | |
322 | csr = musb_readw(epio, MUSB_TXCSR); | |
323 | usb_settoggle(udev, qh->epnum, 1, | |
324 | (csr & MUSB_TXCSR_H_DATATOGGLE) | |
325 | ? 1 : 0); | |
326 | } else { | |
327 | csr = musb_readw(epio, MUSB_RXCSR); | |
328 | usb_settoggle(udev, qh->epnum, 0, | |
329 | (csr & MUSB_RXCSR_H_DATATOGGLE) | |
330 | ? 1 : 0); | |
331 | } | |
332 | } | |
333 | ||
334 | /* caller owns controller lock, irqs are blocked */ | |
335 | static struct musb_qh * | |
336 | musb_giveback(struct musb_qh *qh, struct urb *urb, int status) | |
337 | { | |
338 | int is_in; | |
339 | struct musb_hw_ep *ep = qh->hw_ep; | |
340 | struct musb *musb = ep->musb; | |
341 | int ready = qh->is_ready; | |
342 | ||
343 | if (ep->is_shared_fifo) | |
344 | is_in = 1; | |
345 | else | |
346 | is_in = usb_pipein(urb->pipe); | |
347 | ||
348 | /* save toggle eagerly, for paranoia */ | |
349 | switch (qh->type) { | |
350 | case USB_ENDPOINT_XFER_BULK: | |
351 | case USB_ENDPOINT_XFER_INT: | |
352 | musb_save_toggle(ep, is_in, urb); | |
353 | break; | |
354 | case USB_ENDPOINT_XFER_ISOC: | |
355 | if (status == 0 && urb->error_count) | |
356 | status = -EXDEV; | |
357 | break; | |
358 | } | |
359 | ||
550a7375 FB |
360 | qh->is_ready = 0; |
361 | __musb_giveback(musb, urb, status); | |
362 | qh->is_ready = ready; | |
363 | ||
364 | /* reclaim resources (and bandwidth) ASAP; deschedule it, and | |
365 | * invalidate qh as soon as list_empty(&hep->urb_list) | |
366 | */ | |
367 | if (list_empty(&qh->hep->urb_list)) { | |
368 | struct list_head *head; | |
369 | ||
370 | if (is_in) | |
371 | ep->rx_reinit = 1; | |
372 | else | |
373 | ep->tx_reinit = 1; | |
374 | ||
375 | /* clobber old pointers to this qh */ | |
376 | if (is_in || ep->is_shared_fifo) | |
377 | ep->in_qh = NULL; | |
378 | else | |
379 | ep->out_qh = NULL; | |
380 | qh->hep->hcpriv = NULL; | |
381 | ||
382 | switch (qh->type) { | |
383 | ||
23d15e07 AKG |
384 | case USB_ENDPOINT_XFER_CONTROL: |
385 | case USB_ENDPOINT_XFER_BULK: | |
386 | /* fifo policy for these lists, except that NAKing | |
387 | * should rotate a qh to the end (for fairness). | |
388 | */ | |
389 | if (qh->mux == 1) { | |
390 | head = qh->ring.prev; | |
391 | list_del(&qh->ring); | |
392 | kfree(qh); | |
393 | qh = first_qh(head); | |
394 | break; | |
395 | } | |
396 | ||
550a7375 FB |
397 | case USB_ENDPOINT_XFER_ISOC: |
398 | case USB_ENDPOINT_XFER_INT: | |
399 | /* this is where periodic bandwidth should be | |
400 | * de-allocated if it's tracked and allocated; | |
401 | * and where we'd update the schedule tree... | |
402 | */ | |
403 | musb->periodic[ep->epnum] = NULL; | |
404 | kfree(qh); | |
405 | qh = NULL; | |
406 | break; | |
550a7375 FB |
407 | } |
408 | } | |
409 | return qh; | |
410 | } | |
411 | ||
412 | /* | |
413 | * Advance this hardware endpoint's queue, completing the specified urb and | |
414 | * advancing to either the next urb queued to that qh, or else invalidating | |
415 | * that qh and advancing to the next qh scheduled after the current one. | |
416 | * | |
417 | * Context: caller owns controller lock, irqs are blocked | |
418 | */ | |
419 | static void | |
420 | musb_advance_schedule(struct musb *musb, struct urb *urb, | |
421 | struct musb_hw_ep *hw_ep, int is_in) | |
422 | { | |
423 | struct musb_qh *qh; | |
424 | ||
425 | if (is_in || hw_ep->is_shared_fifo) | |
426 | qh = hw_ep->in_qh; | |
427 | else | |
428 | qh = hw_ep->out_qh; | |
429 | ||
430 | if (urb->status == -EINPROGRESS) | |
431 | qh = musb_giveback(qh, urb, 0); | |
432 | else | |
433 | qh = musb_giveback(qh, urb, urb->status); | |
434 | ||
435 | if (qh && qh->is_ready && !list_empty(&qh->hep->urb_list)) { | |
436 | DBG(4, "... next ep%d %cX urb %p\n", | |
437 | hw_ep->epnum, is_in ? 'R' : 'T', | |
438 | next_urb(qh)); | |
439 | musb_start_urb(musb, is_in, qh); | |
440 | } | |
441 | } | |
442 | ||
c767c1c6 | 443 | static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) |
550a7375 FB |
444 | { |
445 | /* we don't want fifo to fill itself again; | |
446 | * ignore dma (various models), | |
447 | * leave toggle alone (may not have been saved yet) | |
448 | */ | |
449 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; | |
450 | csr &= ~(MUSB_RXCSR_H_REQPKT | |
451 | | MUSB_RXCSR_H_AUTOREQ | |
452 | | MUSB_RXCSR_AUTOCLEAR); | |
453 | ||
454 | /* write 2x to allow double buffering */ | |
455 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); | |
456 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); | |
457 | ||
458 | /* flush writebuffer */ | |
459 | return musb_readw(hw_ep->regs, MUSB_RXCSR); | |
460 | } | |
461 | ||
462 | /* | |
463 | * PIO RX for a packet (or part of it). | |
464 | */ | |
465 | static bool | |
466 | musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) | |
467 | { | |
468 | u16 rx_count; | |
469 | u8 *buf; | |
470 | u16 csr; | |
471 | bool done = false; | |
472 | u32 length; | |
473 | int do_flush = 0; | |
474 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
475 | void __iomem *epio = hw_ep->regs; | |
476 | struct musb_qh *qh = hw_ep->in_qh; | |
477 | int pipe = urb->pipe; | |
478 | void *buffer = urb->transfer_buffer; | |
479 | ||
480 | /* musb_ep_select(mbase, epnum); */ | |
481 | rx_count = musb_readw(epio, MUSB_RXCOUNT); | |
482 | DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, | |
483 | urb->transfer_buffer, qh->offset, | |
484 | urb->transfer_buffer_length); | |
485 | ||
486 | /* unload FIFO */ | |
487 | if (usb_pipeisoc(pipe)) { | |
488 | int status = 0; | |
489 | struct usb_iso_packet_descriptor *d; | |
490 | ||
491 | if (iso_err) { | |
492 | status = -EILSEQ; | |
493 | urb->error_count++; | |
494 | } | |
495 | ||
496 | d = urb->iso_frame_desc + qh->iso_idx; | |
497 | buf = buffer + d->offset; | |
498 | length = d->length; | |
499 | if (rx_count > length) { | |
500 | if (status == 0) { | |
501 | status = -EOVERFLOW; | |
502 | urb->error_count++; | |
503 | } | |
504 | DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); | |
505 | do_flush = 1; | |
506 | } else | |
507 | length = rx_count; | |
508 | urb->actual_length += length; | |
509 | d->actual_length = length; | |
510 | ||
511 | d->status = status; | |
512 | ||
513 | /* see if we are done */ | |
514 | done = (++qh->iso_idx >= urb->number_of_packets); | |
515 | } else { | |
516 | /* non-isoch */ | |
517 | buf = buffer + qh->offset; | |
518 | length = urb->transfer_buffer_length - qh->offset; | |
519 | if (rx_count > length) { | |
520 | if (urb->status == -EINPROGRESS) | |
521 | urb->status = -EOVERFLOW; | |
522 | DBG(2, "** OVERFLOW %d into %d\n", rx_count, length); | |
523 | do_flush = 1; | |
524 | } else | |
525 | length = rx_count; | |
526 | urb->actual_length += length; | |
527 | qh->offset += length; | |
528 | ||
529 | /* see if we are done */ | |
530 | done = (urb->actual_length == urb->transfer_buffer_length) | |
531 | || (rx_count < qh->maxpacket) | |
532 | || (urb->status != -EINPROGRESS); | |
533 | if (done | |
534 | && (urb->status == -EINPROGRESS) | |
535 | && (urb->transfer_flags & URB_SHORT_NOT_OK) | |
536 | && (urb->actual_length | |
537 | < urb->transfer_buffer_length)) | |
538 | urb->status = -EREMOTEIO; | |
539 | } | |
540 | ||
541 | musb_read_fifo(hw_ep, length, buf); | |
542 | ||
543 | csr = musb_readw(epio, MUSB_RXCSR); | |
544 | csr |= MUSB_RXCSR_H_WZC_BITS; | |
545 | if (unlikely(do_flush)) | |
546 | musb_h_flush_rxfifo(hw_ep, csr); | |
547 | else { | |
548 | /* REVISIT this assumes AUTOCLEAR is never set */ | |
549 | csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); | |
550 | if (!done) | |
551 | csr |= MUSB_RXCSR_H_REQPKT; | |
552 | musb_writew(epio, MUSB_RXCSR, csr); | |
553 | } | |
554 | ||
555 | return done; | |
556 | } | |
557 | ||
558 | /* we don't always need to reinit a given side of an endpoint... | |
559 | * when we do, use tx/rx reinit routine and then construct a new CSR | |
560 | * to address data toggle, NYET, and DMA or PIO. | |
561 | * | |
562 | * it's possible that driver bugs (especially for DMA) or aborting a | |
563 | * transfer might have left the endpoint busier than it should be. | |
564 | * the busy/not-empty tests are basically paranoia. | |
565 | */ | |
566 | static void | |
567 | musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep) | |
568 | { | |
569 | u16 csr; | |
570 | ||
571 | /* NOTE: we know the "rx" fifo reinit never triggers for ep0. | |
572 | * That always uses tx_reinit since ep0 repurposes TX register | |
573 | * offsets; the initial SETUP packet is also a kind of OUT. | |
574 | */ | |
575 | ||
576 | /* if programmed for Tx, put it in RX mode */ | |
577 | if (ep->is_shared_fifo) { | |
578 | csr = musb_readw(ep->regs, MUSB_TXCSR); | |
579 | if (csr & MUSB_TXCSR_MODE) { | |
580 | musb_h_tx_flush_fifo(ep); | |
581 | musb_writew(ep->regs, MUSB_TXCSR, | |
582 | MUSB_TXCSR_FRCDATATOG); | |
583 | } | |
584 | /* clear mode (and everything else) to enable Rx */ | |
585 | musb_writew(ep->regs, MUSB_TXCSR, 0); | |
586 | ||
587 | /* scrub all previous state, clearing toggle */ | |
588 | } else { | |
589 | csr = musb_readw(ep->regs, MUSB_RXCSR); | |
590 | if (csr & MUSB_RXCSR_RXPKTRDY) | |
591 | WARNING("rx%d, packet/%d ready?\n", ep->epnum, | |
592 | musb_readw(ep->regs, MUSB_RXCOUNT)); | |
593 | ||
594 | musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); | |
595 | } | |
596 | ||
597 | /* target addr and (for multipoint) hub addr/port */ | |
598 | if (musb->is_multipoint) { | |
599 | musb_writeb(ep->target_regs, MUSB_RXFUNCADDR, | |
600 | qh->addr_reg); | |
601 | musb_writeb(ep->target_regs, MUSB_RXHUBADDR, | |
602 | qh->h_addr_reg); | |
603 | musb_writeb(ep->target_regs, MUSB_RXHUBPORT, | |
604 | qh->h_port_reg); | |
605 | } else | |
606 | musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); | |
607 | ||
608 | /* protocol/endpoint, interval/NAKlimit, i/o size */ | |
609 | musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); | |
610 | musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); | |
611 | /* NOTE: bulk combining rewrites high bits of maxpacket */ | |
612 | musb_writew(ep->regs, MUSB_RXMAXP, qh->maxpacket); | |
613 | ||
614 | ep->rx_reinit = 0; | |
615 | } | |
616 | ||
617 | ||
618 | /* | |
619 | * Program an HDRC endpoint as per the given URB | |
620 | * Context: irqs blocked, controller lock held | |
621 | */ | |
622 | static void musb_ep_program(struct musb *musb, u8 epnum, | |
623 | struct urb *urb, unsigned int is_out, | |
624 | u8 *buf, u32 len) | |
625 | { | |
626 | struct dma_controller *dma_controller; | |
627 | struct dma_channel *dma_channel; | |
628 | u8 dma_ok; | |
629 | void __iomem *mbase = musb->mregs; | |
630 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
631 | void __iomem *epio = hw_ep->regs; | |
632 | struct musb_qh *qh; | |
633 | u16 packet_sz; | |
634 | ||
635 | if (!is_out || hw_ep->is_shared_fifo) | |
636 | qh = hw_ep->in_qh; | |
637 | else | |
638 | qh = hw_ep->out_qh; | |
639 | ||
640 | packet_sz = qh->maxpacket; | |
641 | ||
642 | DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s " | |
643 | "h_addr%02x h_port%02x bytes %d\n", | |
644 | is_out ? "-->" : "<--", | |
645 | epnum, urb, urb->dev->speed, | |
646 | qh->addr_reg, qh->epnum, is_out ? "out" : "in", | |
647 | qh->h_addr_reg, qh->h_port_reg, | |
648 | len); | |
649 | ||
650 | musb_ep_select(mbase, epnum); | |
651 | ||
652 | /* candidate for DMA? */ | |
653 | dma_controller = musb->dma_controller; | |
654 | if (is_dma_capable() && epnum && dma_controller) { | |
655 | dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; | |
656 | if (!dma_channel) { | |
657 | dma_channel = dma_controller->channel_alloc( | |
658 | dma_controller, hw_ep, is_out); | |
659 | if (is_out) | |
660 | hw_ep->tx_channel = dma_channel; | |
661 | else | |
662 | hw_ep->rx_channel = dma_channel; | |
663 | } | |
664 | } else | |
665 | dma_channel = NULL; | |
666 | ||
667 | /* make sure we clear DMAEnab, autoSet bits from previous run */ | |
668 | ||
669 | /* OUT/transmit/EP0 or IN/receive? */ | |
670 | if (is_out) { | |
671 | u16 csr; | |
672 | u16 int_txe; | |
673 | u16 load_count; | |
674 | ||
675 | csr = musb_readw(epio, MUSB_TXCSR); | |
676 | ||
677 | /* disable interrupt in case we flush */ | |
678 | int_txe = musb_readw(mbase, MUSB_INTRTXE); | |
679 | musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); | |
680 | ||
681 | /* general endpoint setup */ | |
682 | if (epnum) { | |
683 | /* ASSERT: TXCSR_DMAENAB was already cleared */ | |
684 | ||
685 | /* flush all old state, set default */ | |
686 | musb_h_tx_flush_fifo(hw_ep); | |
687 | csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT | |
688 | | MUSB_TXCSR_DMAMODE | |
689 | | MUSB_TXCSR_FRCDATATOG | |
690 | | MUSB_TXCSR_H_RXSTALL | |
691 | | MUSB_TXCSR_H_ERROR | |
692 | | MUSB_TXCSR_TXPKTRDY | |
693 | ); | |
694 | csr |= MUSB_TXCSR_MODE; | |
695 | ||
696 | if (usb_gettoggle(urb->dev, | |
697 | qh->epnum, 1)) | |
698 | csr |= MUSB_TXCSR_H_WR_DATATOGGLE | |
699 | | MUSB_TXCSR_H_DATATOGGLE; | |
700 | else | |
701 | csr |= MUSB_TXCSR_CLRDATATOG; | |
702 | ||
703 | /* twice in case of double packet buffering */ | |
704 | musb_writew(epio, MUSB_TXCSR, csr); | |
705 | /* REVISIT may need to clear FLUSHFIFO ... */ | |
706 | musb_writew(epio, MUSB_TXCSR, csr); | |
707 | csr = musb_readw(epio, MUSB_TXCSR); | |
708 | } else { | |
709 | /* endpoint 0: just flush */ | |
710 | musb_writew(epio, MUSB_CSR0, | |
711 | csr | MUSB_CSR0_FLUSHFIFO); | |
712 | musb_writew(epio, MUSB_CSR0, | |
713 | csr | MUSB_CSR0_FLUSHFIFO); | |
714 | } | |
715 | ||
716 | /* target addr and (for multipoint) hub addr/port */ | |
717 | if (musb->is_multipoint) { | |
718 | musb_writeb(mbase, | |
719 | MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR), | |
720 | qh->addr_reg); | |
721 | musb_writeb(mbase, | |
722 | MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR), | |
723 | qh->h_addr_reg); | |
724 | musb_writeb(mbase, | |
725 | MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT), | |
726 | qh->h_port_reg); | |
727 | /* FIXME if !epnum, do the same for RX ... */ | |
728 | } else | |
729 | musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); | |
730 | ||
731 | /* protocol/endpoint/interval/NAKlimit */ | |
732 | if (epnum) { | |
733 | musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); | |
734 | if (can_bulk_split(musb, qh->type)) | |
735 | musb_writew(epio, MUSB_TXMAXP, | |
736 | packet_sz | |
737 | | ((hw_ep->max_packet_sz_tx / | |
738 | packet_sz) - 1) << 11); | |
739 | else | |
740 | musb_writew(epio, MUSB_TXMAXP, | |
741 | packet_sz); | |
742 | musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); | |
743 | } else { | |
744 | musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); | |
745 | if (musb->is_multipoint) | |
746 | musb_writeb(epio, MUSB_TYPE0, | |
747 | qh->type_reg); | |
748 | } | |
749 | ||
750 | if (can_bulk_split(musb, qh->type)) | |
751 | load_count = min((u32) hw_ep->max_packet_sz_tx, | |
752 | len); | |
753 | else | |
754 | load_count = min((u32) packet_sz, len); | |
755 | ||
756 | #ifdef CONFIG_USB_INVENTRA_DMA | |
757 | if (dma_channel) { | |
758 | ||
759 | /* clear previous state */ | |
760 | csr = musb_readw(epio, MUSB_TXCSR); | |
761 | csr &= ~(MUSB_TXCSR_AUTOSET | |
762 | | MUSB_TXCSR_DMAMODE | |
763 | | MUSB_TXCSR_DMAENAB); | |
764 | csr |= MUSB_TXCSR_MODE; | |
765 | musb_writew(epio, MUSB_TXCSR, | |
766 | csr | MUSB_TXCSR_MODE); | |
767 | ||
768 | qh->segsize = min(len, dma_channel->max_len); | |
769 | ||
770 | if (qh->segsize <= packet_sz) | |
771 | dma_channel->desired_mode = 0; | |
772 | else | |
773 | dma_channel->desired_mode = 1; | |
774 | ||
775 | ||
776 | if (dma_channel->desired_mode == 0) { | |
777 | csr &= ~(MUSB_TXCSR_AUTOSET | |
778 | | MUSB_TXCSR_DMAMODE); | |
779 | csr |= (MUSB_TXCSR_DMAENAB); | |
780 | /* against programming guide */ | |
781 | } else | |
782 | csr |= (MUSB_TXCSR_AUTOSET | |
783 | | MUSB_TXCSR_DMAENAB | |
784 | | MUSB_TXCSR_DMAMODE); | |
785 | ||
786 | musb_writew(epio, MUSB_TXCSR, csr); | |
787 | ||
788 | dma_ok = dma_controller->channel_program( | |
789 | dma_channel, packet_sz, | |
790 | dma_channel->desired_mode, | |
791 | urb->transfer_dma, | |
792 | qh->segsize); | |
793 | if (dma_ok) { | |
794 | load_count = 0; | |
795 | } else { | |
796 | dma_controller->channel_release(dma_channel); | |
797 | if (is_out) | |
798 | hw_ep->tx_channel = NULL; | |
799 | else | |
800 | hw_ep->rx_channel = NULL; | |
801 | dma_channel = NULL; | |
802 | } | |
803 | } | |
804 | #endif | |
805 | ||
806 | /* candidate for DMA */ | |
807 | if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { | |
808 | ||
809 | /* program endpoint CSRs first, then setup DMA. | |
810 | * assume CPPI setup succeeds. | |
811 | * defer enabling dma. | |
812 | */ | |
813 | csr = musb_readw(epio, MUSB_TXCSR); | |
814 | csr &= ~(MUSB_TXCSR_AUTOSET | |
815 | | MUSB_TXCSR_DMAMODE | |
816 | | MUSB_TXCSR_DMAENAB); | |
817 | csr |= MUSB_TXCSR_MODE; | |
818 | musb_writew(epio, MUSB_TXCSR, | |
819 | csr | MUSB_TXCSR_MODE); | |
820 | ||
821 | dma_channel->actual_len = 0L; | |
822 | qh->segsize = len; | |
823 | ||
824 | /* TX uses "rndis" mode automatically, but needs help | |
825 | * to identify the zero-length-final-packet case. | |
826 | */ | |
827 | dma_ok = dma_controller->channel_program( | |
828 | dma_channel, packet_sz, | |
829 | (urb->transfer_flags | |
830 | & URB_ZERO_PACKET) | |
831 | == URB_ZERO_PACKET, | |
832 | urb->transfer_dma, | |
833 | qh->segsize); | |
834 | if (dma_ok) { | |
835 | load_count = 0; | |
836 | } else { | |
837 | dma_controller->channel_release(dma_channel); | |
838 | hw_ep->tx_channel = NULL; | |
839 | dma_channel = NULL; | |
840 | ||
841 | /* REVISIT there's an error path here that | |
842 | * needs handling: can't do dma, but | |
843 | * there's no pio buffer address... | |
844 | */ | |
845 | } | |
846 | } | |
847 | ||
848 | if (load_count) { | |
849 | /* ASSERT: TXCSR_DMAENAB was already cleared */ | |
850 | ||
851 | /* PIO to load FIFO */ | |
852 | qh->segsize = load_count; | |
853 | musb_write_fifo(hw_ep, load_count, buf); | |
854 | csr = musb_readw(epio, MUSB_TXCSR); | |
855 | csr &= ~(MUSB_TXCSR_DMAENAB | |
856 | | MUSB_TXCSR_DMAMODE | |
857 | | MUSB_TXCSR_AUTOSET); | |
858 | /* write CSR */ | |
859 | csr |= MUSB_TXCSR_MODE; | |
860 | ||
861 | if (epnum) | |
862 | musb_writew(epio, MUSB_TXCSR, csr); | |
863 | } | |
864 | ||
865 | /* re-enable interrupt */ | |
866 | musb_writew(mbase, MUSB_INTRTXE, int_txe); | |
867 | ||
868 | /* IN/receive */ | |
869 | } else { | |
870 | u16 csr; | |
871 | ||
872 | if (hw_ep->rx_reinit) { | |
873 | musb_rx_reinit(musb, qh, hw_ep); | |
874 | ||
875 | /* init new state: toggle and NYET, maybe DMA later */ | |
876 | if (usb_gettoggle(urb->dev, qh->epnum, 0)) | |
877 | csr = MUSB_RXCSR_H_WR_DATATOGGLE | |
878 | | MUSB_RXCSR_H_DATATOGGLE; | |
879 | else | |
880 | csr = 0; | |
881 | if (qh->type == USB_ENDPOINT_XFER_INT) | |
882 | csr |= MUSB_RXCSR_DISNYET; | |
883 | ||
884 | } else { | |
885 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); | |
886 | ||
887 | if (csr & (MUSB_RXCSR_RXPKTRDY | |
888 | | MUSB_RXCSR_DMAENAB | |
889 | | MUSB_RXCSR_H_REQPKT)) | |
890 | ERR("broken !rx_reinit, ep%d csr %04x\n", | |
891 | hw_ep->epnum, csr); | |
892 | ||
893 | /* scrub any stale state, leaving toggle alone */ | |
894 | csr &= MUSB_RXCSR_DISNYET; | |
895 | } | |
896 | ||
897 | /* kick things off */ | |
898 | ||
899 | if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) { | |
900 | /* candidate for DMA */ | |
901 | if (dma_channel) { | |
902 | dma_channel->actual_len = 0L; | |
903 | qh->segsize = len; | |
904 | ||
905 | /* AUTOREQ is in a DMA register */ | |
906 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); | |
907 | csr = musb_readw(hw_ep->regs, | |
908 | MUSB_RXCSR); | |
909 | ||
910 | /* unless caller treats short rx transfers as | |
911 | * errors, we dare not queue multiple transfers. | |
912 | */ | |
913 | dma_ok = dma_controller->channel_program( | |
914 | dma_channel, packet_sz, | |
915 | !(urb->transfer_flags | |
916 | & URB_SHORT_NOT_OK), | |
917 | urb->transfer_dma, | |
918 | qh->segsize); | |
919 | if (!dma_ok) { | |
920 | dma_controller->channel_release( | |
921 | dma_channel); | |
922 | hw_ep->rx_channel = NULL; | |
923 | dma_channel = NULL; | |
924 | } else | |
925 | csr |= MUSB_RXCSR_DMAENAB; | |
926 | } | |
927 | } | |
928 | ||
929 | csr |= MUSB_RXCSR_H_REQPKT; | |
930 | DBG(7, "RXCSR%d := %04x\n", epnum, csr); | |
931 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); | |
932 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); | |
933 | } | |
934 | } | |
935 | ||
936 | ||
937 | /* | |
938 | * Service the default endpoint (ep0) as host. | |
939 | * Return true until it's time to start the status stage. | |
940 | */ | |
941 | static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) | |
942 | { | |
943 | bool more = false; | |
944 | u8 *fifo_dest = NULL; | |
945 | u16 fifo_count = 0; | |
946 | struct musb_hw_ep *hw_ep = musb->control_ep; | |
947 | struct musb_qh *qh = hw_ep->in_qh; | |
948 | struct usb_ctrlrequest *request; | |
949 | ||
950 | switch (musb->ep0_stage) { | |
951 | case MUSB_EP0_IN: | |
952 | fifo_dest = urb->transfer_buffer + urb->actual_length; | |
953 | fifo_count = min(len, ((u16) (urb->transfer_buffer_length | |
954 | - urb->actual_length))); | |
955 | if (fifo_count < len) | |
956 | urb->status = -EOVERFLOW; | |
957 | ||
958 | musb_read_fifo(hw_ep, fifo_count, fifo_dest); | |
959 | ||
960 | urb->actual_length += fifo_count; | |
961 | if (len < qh->maxpacket) { | |
962 | /* always terminate on short read; it's | |
963 | * rarely reported as an error. | |
964 | */ | |
965 | } else if (urb->actual_length < | |
966 | urb->transfer_buffer_length) | |
967 | more = true; | |
968 | break; | |
969 | case MUSB_EP0_START: | |
970 | request = (struct usb_ctrlrequest *) urb->setup_packet; | |
971 | ||
972 | if (!request->wLength) { | |
973 | DBG(4, "start no-DATA\n"); | |
974 | break; | |
975 | } else if (request->bRequestType & USB_DIR_IN) { | |
976 | DBG(4, "start IN-DATA\n"); | |
977 | musb->ep0_stage = MUSB_EP0_IN; | |
978 | more = true; | |
979 | break; | |
980 | } else { | |
981 | DBG(4, "start OUT-DATA\n"); | |
982 | musb->ep0_stage = MUSB_EP0_OUT; | |
983 | more = true; | |
984 | } | |
985 | /* FALLTHROUGH */ | |
986 | case MUSB_EP0_OUT: | |
987 | fifo_count = min(qh->maxpacket, ((u16) | |
988 | (urb->transfer_buffer_length | |
989 | - urb->actual_length))); | |
990 | ||
991 | if (fifo_count) { | |
992 | fifo_dest = (u8 *) (urb->transfer_buffer | |
993 | + urb->actual_length); | |
bb1c9ef1 DB |
994 | DBG(3, "Sending %d byte%s to ep0 fifo %p\n", |
995 | fifo_count, | |
996 | (fifo_count == 1) ? "" : "s", | |
997 | fifo_dest); | |
550a7375 FB |
998 | musb_write_fifo(hw_ep, fifo_count, fifo_dest); |
999 | ||
1000 | urb->actual_length += fifo_count; | |
1001 | more = true; | |
1002 | } | |
1003 | break; | |
1004 | default: | |
1005 | ERR("bogus ep0 stage %d\n", musb->ep0_stage); | |
1006 | break; | |
1007 | } | |
1008 | ||
1009 | return more; | |
1010 | } | |
1011 | ||
1012 | /* | |
1013 | * Handle default endpoint interrupt as host. Only called in IRQ time | |
c767c1c6 | 1014 | * from musb_interrupt(). |
550a7375 FB |
1015 | * |
1016 | * called with controller irqlocked | |
1017 | */ | |
1018 | irqreturn_t musb_h_ep0_irq(struct musb *musb) | |
1019 | { | |
1020 | struct urb *urb; | |
1021 | u16 csr, len; | |
1022 | int status = 0; | |
1023 | void __iomem *mbase = musb->mregs; | |
1024 | struct musb_hw_ep *hw_ep = musb->control_ep; | |
1025 | void __iomem *epio = hw_ep->regs; | |
1026 | struct musb_qh *qh = hw_ep->in_qh; | |
1027 | bool complete = false; | |
1028 | irqreturn_t retval = IRQ_NONE; | |
1029 | ||
1030 | /* ep0 only has one queue, "in" */ | |
1031 | urb = next_urb(qh); | |
1032 | ||
1033 | musb_ep_select(mbase, 0); | |
1034 | csr = musb_readw(epio, MUSB_CSR0); | |
1035 | len = (csr & MUSB_CSR0_RXPKTRDY) | |
1036 | ? musb_readb(epio, MUSB_COUNT0) | |
1037 | : 0; | |
1038 | ||
1039 | DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", | |
1040 | csr, qh, len, urb, musb->ep0_stage); | |
1041 | ||
1042 | /* if we just did status stage, we are done */ | |
1043 | if (MUSB_EP0_STATUS == musb->ep0_stage) { | |
1044 | retval = IRQ_HANDLED; | |
1045 | complete = true; | |
1046 | } | |
1047 | ||
1048 | /* prepare status */ | |
1049 | if (csr & MUSB_CSR0_H_RXSTALL) { | |
1050 | DBG(6, "STALLING ENDPOINT\n"); | |
1051 | status = -EPIPE; | |
1052 | ||
1053 | } else if (csr & MUSB_CSR0_H_ERROR) { | |
1054 | DBG(2, "no response, csr0 %04x\n", csr); | |
1055 | status = -EPROTO; | |
1056 | ||
1057 | } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { | |
1058 | DBG(2, "control NAK timeout\n"); | |
1059 | ||
1060 | /* NOTE: this code path would be a good place to PAUSE a | |
1061 | * control transfer, if another one is queued, so that | |
1062 | * ep0 is more likely to stay busy. | |
1063 | * | |
1064 | * if (qh->ring.next != &musb->control), then | |
1065 | * we have a candidate... NAKing is *NOT* an error | |
1066 | */ | |
1067 | musb_writew(epio, MUSB_CSR0, 0); | |
1068 | retval = IRQ_HANDLED; | |
1069 | } | |
1070 | ||
1071 | if (status) { | |
1072 | DBG(6, "aborting\n"); | |
1073 | retval = IRQ_HANDLED; | |
1074 | if (urb) | |
1075 | urb->status = status; | |
1076 | complete = true; | |
1077 | ||
1078 | /* use the proper sequence to abort the transfer */ | |
1079 | if (csr & MUSB_CSR0_H_REQPKT) { | |
1080 | csr &= ~MUSB_CSR0_H_REQPKT; | |
1081 | musb_writew(epio, MUSB_CSR0, csr); | |
1082 | csr &= ~MUSB_CSR0_H_NAKTIMEOUT; | |
1083 | musb_writew(epio, MUSB_CSR0, csr); | |
1084 | } else { | |
1085 | csr |= MUSB_CSR0_FLUSHFIFO; | |
1086 | musb_writew(epio, MUSB_CSR0, csr); | |
1087 | musb_writew(epio, MUSB_CSR0, csr); | |
1088 | csr &= ~MUSB_CSR0_H_NAKTIMEOUT; | |
1089 | musb_writew(epio, MUSB_CSR0, csr); | |
1090 | } | |
1091 | ||
1092 | musb_writeb(epio, MUSB_NAKLIMIT0, 0); | |
1093 | ||
1094 | /* clear it */ | |
1095 | musb_writew(epio, MUSB_CSR0, 0); | |
1096 | } | |
1097 | ||
1098 | if (unlikely(!urb)) { | |
1099 | /* stop endpoint since we have no place for its data, this | |
1100 | * SHOULD NEVER HAPPEN! */ | |
1101 | ERR("no URB for end 0\n"); | |
1102 | ||
1103 | musb_writew(epio, MUSB_CSR0, MUSB_CSR0_FLUSHFIFO); | |
1104 | musb_writew(epio, MUSB_CSR0, MUSB_CSR0_FLUSHFIFO); | |
1105 | musb_writew(epio, MUSB_CSR0, 0); | |
1106 | ||
1107 | goto done; | |
1108 | } | |
1109 | ||
1110 | if (!complete) { | |
1111 | /* call common logic and prepare response */ | |
1112 | if (musb_h_ep0_continue(musb, len, urb)) { | |
1113 | /* more packets required */ | |
1114 | csr = (MUSB_EP0_IN == musb->ep0_stage) | |
1115 | ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; | |
1116 | } else { | |
1117 | /* data transfer complete; perform status phase */ | |
1118 | if (usb_pipeout(urb->pipe) | |
1119 | || !urb->transfer_buffer_length) | |
1120 | csr = MUSB_CSR0_H_STATUSPKT | |
1121 | | MUSB_CSR0_H_REQPKT; | |
1122 | else | |
1123 | csr = MUSB_CSR0_H_STATUSPKT | |
1124 | | MUSB_CSR0_TXPKTRDY; | |
1125 | ||
1126 | /* flag status stage */ | |
1127 | musb->ep0_stage = MUSB_EP0_STATUS; | |
1128 | ||
1129 | DBG(5, "ep0 STATUS, csr %04x\n", csr); | |
1130 | ||
1131 | } | |
1132 | musb_writew(epio, MUSB_CSR0, csr); | |
1133 | retval = IRQ_HANDLED; | |
1134 | } else | |
1135 | musb->ep0_stage = MUSB_EP0_IDLE; | |
1136 | ||
1137 | /* call completion handler if done */ | |
1138 | if (complete) | |
1139 | musb_advance_schedule(musb, urb, hw_ep, 1); | |
1140 | done: | |
1141 | return retval; | |
1142 | } | |
1143 | ||
1144 | ||
1145 | #ifdef CONFIG_USB_INVENTRA_DMA | |
1146 | ||
1147 | /* Host side TX (OUT) using Mentor DMA works as follows: | |
1148 | submit_urb -> | |
1149 | - if queue was empty, Program Endpoint | |
1150 | - ... which starts DMA to fifo in mode 1 or 0 | |
1151 | ||
1152 | DMA Isr (transfer complete) -> TxAvail() | |
1153 | - Stop DMA (~DmaEnab) (<--- Alert ... currently happens | |
1154 | only in musb_cleanup_urb) | |
1155 | - TxPktRdy has to be set in mode 0 or for | |
1156 | short packets in mode 1. | |
1157 | */ | |
1158 | ||
1159 | #endif | |
1160 | ||
1161 | /* Service a Tx-Available or dma completion irq for the endpoint */ | |
1162 | void musb_host_tx(struct musb *musb, u8 epnum) | |
1163 | { | |
1164 | int pipe; | |
1165 | bool done = false; | |
1166 | u16 tx_csr; | |
1167 | size_t wLength = 0; | |
1168 | u8 *buf = NULL; | |
1169 | struct urb *urb; | |
1170 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
1171 | void __iomem *epio = hw_ep->regs; | |
1172 | struct musb_qh *qh = hw_ep->out_qh; | |
1173 | u32 status = 0; | |
1174 | void __iomem *mbase = musb->mregs; | |
1175 | struct dma_channel *dma; | |
1176 | ||
1177 | urb = next_urb(qh); | |
1178 | ||
1179 | musb_ep_select(mbase, epnum); | |
1180 | tx_csr = musb_readw(epio, MUSB_TXCSR); | |
1181 | ||
1182 | /* with CPPI, DMA sometimes triggers "extra" irqs */ | |
1183 | if (!urb) { | |
1184 | DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); | |
1185 | goto finish; | |
1186 | } | |
1187 | ||
1188 | pipe = urb->pipe; | |
1189 | dma = is_dma_capable() ? hw_ep->tx_channel : NULL; | |
1190 | DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, | |
1191 | dma ? ", dma" : ""); | |
1192 | ||
1193 | /* check for errors */ | |
1194 | if (tx_csr & MUSB_TXCSR_H_RXSTALL) { | |
1195 | /* dma was disabled, fifo flushed */ | |
1196 | DBG(3, "TX end %d stall\n", epnum); | |
1197 | ||
1198 | /* stall; record URB status */ | |
1199 | status = -EPIPE; | |
1200 | ||
1201 | } else if (tx_csr & MUSB_TXCSR_H_ERROR) { | |
1202 | /* (NON-ISO) dma was disabled, fifo flushed */ | |
1203 | DBG(3, "TX 3strikes on ep=%d\n", epnum); | |
1204 | ||
1205 | status = -ETIMEDOUT; | |
1206 | ||
1207 | } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { | |
1208 | DBG(6, "TX end=%d device not responding\n", epnum); | |
1209 | ||
1210 | /* NOTE: this code path would be a good place to PAUSE a | |
1211 | * transfer, if there's some other (nonperiodic) tx urb | |
1212 | * that could use this fifo. (dma complicates it...) | |
1213 | * | |
1214 | * if (bulk && qh->ring.next != &musb->out_bulk), then | |
1215 | * we have a candidate... NAKing is *NOT* an error | |
1216 | */ | |
1217 | musb_ep_select(mbase, epnum); | |
1218 | musb_writew(epio, MUSB_TXCSR, | |
1219 | MUSB_TXCSR_H_WZC_BITS | |
1220 | | MUSB_TXCSR_TXPKTRDY); | |
1221 | goto finish; | |
1222 | } | |
1223 | ||
1224 | if (status) { | |
1225 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
1226 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; | |
1227 | (void) musb->dma_controller->channel_abort(dma); | |
1228 | } | |
1229 | ||
1230 | /* do the proper sequence to abort the transfer in the | |
1231 | * usb core; the dma engine should already be stopped. | |
1232 | */ | |
1233 | musb_h_tx_flush_fifo(hw_ep); | |
1234 | tx_csr &= ~(MUSB_TXCSR_AUTOSET | |
1235 | | MUSB_TXCSR_DMAENAB | |
1236 | | MUSB_TXCSR_H_ERROR | |
1237 | | MUSB_TXCSR_H_RXSTALL | |
1238 | | MUSB_TXCSR_H_NAKTIMEOUT | |
1239 | ); | |
1240 | ||
1241 | musb_ep_select(mbase, epnum); | |
1242 | musb_writew(epio, MUSB_TXCSR, tx_csr); | |
1243 | /* REVISIT may need to clear FLUSHFIFO ... */ | |
1244 | musb_writew(epio, MUSB_TXCSR, tx_csr); | |
1245 | musb_writeb(epio, MUSB_TXINTERVAL, 0); | |
1246 | ||
1247 | done = true; | |
1248 | } | |
1249 | ||
1250 | /* second cppi case */ | |
1251 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
1252 | DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr); | |
1253 | goto finish; | |
1254 | ||
1255 | } | |
1256 | ||
1257 | /* REVISIT this looks wrong... */ | |
1258 | if (!status || dma || usb_pipeisoc(pipe)) { | |
1259 | if (dma) | |
1260 | wLength = dma->actual_len; | |
1261 | else | |
1262 | wLength = qh->segsize; | |
1263 | qh->offset += wLength; | |
1264 | ||
1265 | if (usb_pipeisoc(pipe)) { | |
1266 | struct usb_iso_packet_descriptor *d; | |
1267 | ||
1268 | d = urb->iso_frame_desc + qh->iso_idx; | |
1269 | d->actual_length = qh->segsize; | |
1270 | if (++qh->iso_idx >= urb->number_of_packets) { | |
1271 | done = true; | |
1272 | } else { | |
1273 | d++; | |
1274 | buf = urb->transfer_buffer + d->offset; | |
1275 | wLength = d->length; | |
1276 | } | |
1277 | } else if (dma) { | |
1278 | done = true; | |
1279 | } else { | |
1280 | /* see if we need to send more data, or ZLP */ | |
1281 | if (qh->segsize < qh->maxpacket) | |
1282 | done = true; | |
1283 | else if (qh->offset == urb->transfer_buffer_length | |
1284 | && !(urb->transfer_flags | |
1285 | & URB_ZERO_PACKET)) | |
1286 | done = true; | |
1287 | if (!done) { | |
1288 | buf = urb->transfer_buffer | |
1289 | + qh->offset; | |
1290 | wLength = urb->transfer_buffer_length | |
1291 | - qh->offset; | |
1292 | } | |
1293 | } | |
1294 | } | |
1295 | ||
1296 | /* urb->status != -EINPROGRESS means request has been faulted, | |
1297 | * so we must abort this transfer after cleanup | |
1298 | */ | |
1299 | if (urb->status != -EINPROGRESS) { | |
1300 | done = true; | |
1301 | if (status == 0) | |
1302 | status = urb->status; | |
1303 | } | |
1304 | ||
1305 | if (done) { | |
1306 | /* set status */ | |
1307 | urb->status = status; | |
1308 | urb->actual_length = qh->offset; | |
1309 | musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); | |
1310 | ||
1311 | } else if (!(tx_csr & MUSB_TXCSR_DMAENAB)) { | |
1312 | /* WARN_ON(!buf); */ | |
1313 | ||
1314 | /* REVISIT: some docs say that when hw_ep->tx_double_buffered, | |
1315 | * (and presumably, fifo is not half-full) we should write TWO | |
1316 | * packets before updating TXCSR ... other docs disagree ... | |
1317 | */ | |
1318 | /* PIO: start next packet in this URB */ | |
1319 | wLength = min(qh->maxpacket, (u16) wLength); | |
1320 | musb_write_fifo(hw_ep, wLength, buf); | |
1321 | qh->segsize = wLength; | |
1322 | ||
1323 | musb_ep_select(mbase, epnum); | |
1324 | musb_writew(epio, MUSB_TXCSR, | |
1325 | MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); | |
1326 | } else | |
1327 | DBG(1, "not complete, but dma enabled?\n"); | |
1328 | ||
1329 | finish: | |
1330 | return; | |
1331 | } | |
1332 | ||
1333 | ||
1334 | #ifdef CONFIG_USB_INVENTRA_DMA | |
1335 | ||
1336 | /* Host side RX (IN) using Mentor DMA works as follows: | |
1337 | submit_urb -> | |
1338 | - if queue was empty, ProgramEndpoint | |
1339 | - first IN token is sent out (by setting ReqPkt) | |
1340 | LinuxIsr -> RxReady() | |
1341 | /\ => first packet is received | |
1342 | | - Set in mode 0 (DmaEnab, ~ReqPkt) | |
1343 | | -> DMA Isr (transfer complete) -> RxReady() | |
1344 | | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) | |
1345 | | - if urb not complete, send next IN token (ReqPkt) | |
1346 | | | else complete urb. | |
1347 | | | | |
1348 | --------------------------- | |
1349 | * | |
1350 | * Nuances of mode 1: | |
1351 | * For short packets, no ack (+RxPktRdy) is sent automatically | |
1352 | * (even if AutoClear is ON) | |
1353 | * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent | |
1354 | * automatically => major problem, as collecting the next packet becomes | |
1355 | * difficult. Hence mode 1 is not used. | |
1356 | * | |
1357 | * REVISIT | |
1358 | * All we care about at this driver level is that | |
1359 | * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; | |
1360 | * (b) termination conditions are: short RX, or buffer full; | |
1361 | * (c) fault modes include | |
1362 | * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. | |
1363 | * (and that endpoint's dma queue stops immediately) | |
1364 | * - overflow (full, PLUS more bytes in the terminal packet) | |
1365 | * | |
1366 | * So for example, usb-storage sets URB_SHORT_NOT_OK, and would | |
1367 | * thus be a great candidate for using mode 1 ... for all but the | |
1368 | * last packet of one URB's transfer. | |
1369 | */ | |
1370 | ||
1371 | #endif | |
1372 | ||
1373 | /* | |
1374 | * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, | |
1375 | * and high-bandwidth IN transfer cases. | |
1376 | */ | |
1377 | void musb_host_rx(struct musb *musb, u8 epnum) | |
1378 | { | |
1379 | struct urb *urb; | |
1380 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
1381 | void __iomem *epio = hw_ep->regs; | |
1382 | struct musb_qh *qh = hw_ep->in_qh; | |
1383 | size_t xfer_len; | |
1384 | void __iomem *mbase = musb->mregs; | |
1385 | int pipe; | |
1386 | u16 rx_csr, val; | |
1387 | bool iso_err = false; | |
1388 | bool done = false; | |
1389 | u32 status; | |
1390 | struct dma_channel *dma; | |
1391 | ||
1392 | musb_ep_select(mbase, epnum); | |
1393 | ||
1394 | urb = next_urb(qh); | |
1395 | dma = is_dma_capable() ? hw_ep->rx_channel : NULL; | |
1396 | status = 0; | |
1397 | xfer_len = 0; | |
1398 | ||
1399 | rx_csr = musb_readw(epio, MUSB_RXCSR); | |
1400 | val = rx_csr; | |
1401 | ||
1402 | if (unlikely(!urb)) { | |
1403 | /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least | |
1404 | * usbtest #11 (unlinks) triggers it regularly, sometimes | |
1405 | * with fifo full. (Only with DMA??) | |
1406 | */ | |
1407 | DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, | |
1408 | musb_readw(epio, MUSB_RXCOUNT)); | |
1409 | musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); | |
1410 | return; | |
1411 | } | |
1412 | ||
1413 | pipe = urb->pipe; | |
1414 | ||
1415 | DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", | |
1416 | epnum, rx_csr, urb->actual_length, | |
1417 | dma ? dma->actual_len : 0); | |
1418 | ||
1419 | /* check for errors, concurrent stall & unlink is not really | |
1420 | * handled yet! */ | |
1421 | if (rx_csr & MUSB_RXCSR_H_RXSTALL) { | |
1422 | DBG(3, "RX end %d STALL\n", epnum); | |
1423 | ||
1424 | /* stall; record URB status */ | |
1425 | status = -EPIPE; | |
1426 | ||
1427 | } else if (rx_csr & MUSB_RXCSR_H_ERROR) { | |
1428 | DBG(3, "end %d RX proto error\n", epnum); | |
1429 | ||
1430 | status = -EPROTO; | |
1431 | musb_writeb(epio, MUSB_RXINTERVAL, 0); | |
1432 | ||
1433 | } else if (rx_csr & MUSB_RXCSR_DATAERROR) { | |
1434 | ||
1435 | if (USB_ENDPOINT_XFER_ISOC != qh->type) { | |
1436 | /* NOTE this code path would be a good place to PAUSE a | |
1437 | * transfer, if there's some other (nonperiodic) rx urb | |
1438 | * that could use this fifo. (dma complicates it...) | |
1439 | * | |
1440 | * if (bulk && qh->ring.next != &musb->in_bulk), then | |
1441 | * we have a candidate... NAKing is *NOT* an error | |
1442 | */ | |
1443 | DBG(6, "RX end %d NAK timeout\n", epnum); | |
1444 | musb_ep_select(mbase, epnum); | |
1445 | musb_writew(epio, MUSB_RXCSR, | |
1446 | MUSB_RXCSR_H_WZC_BITS | |
1447 | | MUSB_RXCSR_H_REQPKT); | |
1448 | ||
1449 | goto finish; | |
1450 | } else { | |
1451 | DBG(4, "RX end %d ISO data error\n", epnum); | |
1452 | /* packet error reported later */ | |
1453 | iso_err = true; | |
1454 | } | |
1455 | } | |
1456 | ||
1457 | /* faults abort the transfer */ | |
1458 | if (status) { | |
1459 | /* clean up dma and collect transfer count */ | |
1460 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
1461 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; | |
1462 | (void) musb->dma_controller->channel_abort(dma); | |
1463 | xfer_len = dma->actual_len; | |
1464 | } | |
1465 | musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); | |
1466 | musb_writeb(epio, MUSB_RXINTERVAL, 0); | |
1467 | done = true; | |
1468 | goto finish; | |
1469 | } | |
1470 | ||
1471 | if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { | |
1472 | /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ | |
1473 | ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); | |
1474 | goto finish; | |
1475 | } | |
1476 | ||
1477 | /* thorough shutdown for now ... given more precise fault handling | |
1478 | * and better queueing support, we might keep a DMA pipeline going | |
1479 | * while processing this irq for earlier completions. | |
1480 | */ | |
1481 | ||
1482 | /* FIXME this is _way_ too much in-line logic for Mentor DMA */ | |
1483 | ||
1484 | #ifndef CONFIG_USB_INVENTRA_DMA | |
1485 | if (rx_csr & MUSB_RXCSR_H_REQPKT) { | |
1486 | /* REVISIT this happened for a while on some short reads... | |
1487 | * the cleanup still needs investigation... looks bad... | |
1488 | * and also duplicates dma cleanup code above ... plus, | |
1489 | * shouldn't this be the "half full" double buffer case? | |
1490 | */ | |
1491 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
1492 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; | |
1493 | (void) musb->dma_controller->channel_abort(dma); | |
1494 | xfer_len = dma->actual_len; | |
1495 | done = true; | |
1496 | } | |
1497 | ||
1498 | DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, | |
1499 | xfer_len, dma ? ", dma" : ""); | |
1500 | rx_csr &= ~MUSB_RXCSR_H_REQPKT; | |
1501 | ||
1502 | musb_ep_select(mbase, epnum); | |
1503 | musb_writew(epio, MUSB_RXCSR, | |
1504 | MUSB_RXCSR_H_WZC_BITS | rx_csr); | |
1505 | } | |
1506 | #endif | |
1507 | if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { | |
1508 | xfer_len = dma->actual_len; | |
1509 | ||
1510 | val &= ~(MUSB_RXCSR_DMAENAB | |
1511 | | MUSB_RXCSR_H_AUTOREQ | |
1512 | | MUSB_RXCSR_AUTOCLEAR | |
1513 | | MUSB_RXCSR_RXPKTRDY); | |
1514 | musb_writew(hw_ep->regs, MUSB_RXCSR, val); | |
1515 | ||
1516 | #ifdef CONFIG_USB_INVENTRA_DMA | |
f82a689f AKG |
1517 | if (usb_pipeisoc(pipe)) { |
1518 | struct usb_iso_packet_descriptor *d; | |
1519 | ||
1520 | d = urb->iso_frame_desc + qh->iso_idx; | |
1521 | d->actual_length = xfer_len; | |
1522 | ||
1523 | /* even if there was an error, we did the dma | |
1524 | * for iso_frame_desc->length | |
1525 | */ | |
1526 | if (d->status != EILSEQ && d->status != -EOVERFLOW) | |
1527 | d->status = 0; | |
1528 | ||
1529 | if (++qh->iso_idx >= urb->number_of_packets) | |
1530 | done = true; | |
1531 | else | |
1532 | done = false; | |
1533 | ||
1534 | } else { | |
550a7375 FB |
1535 | /* done if urb buffer is full or short packet is recd */ |
1536 | done = (urb->actual_length + xfer_len >= | |
1537 | urb->transfer_buffer_length | |
1538 | || dma->actual_len < qh->maxpacket); | |
f82a689f | 1539 | } |
550a7375 FB |
1540 | |
1541 | /* send IN token for next packet, without AUTOREQ */ | |
1542 | if (!done) { | |
1543 | val |= MUSB_RXCSR_H_REQPKT; | |
1544 | musb_writew(epio, MUSB_RXCSR, | |
1545 | MUSB_RXCSR_H_WZC_BITS | val); | |
1546 | } | |
1547 | ||
1548 | DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, | |
1549 | done ? "off" : "reset", | |
1550 | musb_readw(epio, MUSB_RXCSR), | |
1551 | musb_readw(epio, MUSB_RXCOUNT)); | |
1552 | #else | |
1553 | done = true; | |
1554 | #endif | |
1555 | } else if (urb->status == -EINPROGRESS) { | |
1556 | /* if no errors, be sure a packet is ready for unloading */ | |
1557 | if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { | |
1558 | status = -EPROTO; | |
1559 | ERR("Rx interrupt with no errors or packet!\n"); | |
1560 | ||
1561 | /* FIXME this is another "SHOULD NEVER HAPPEN" */ | |
1562 | ||
1563 | /* SCRUB (RX) */ | |
1564 | /* do the proper sequence to abort the transfer */ | |
1565 | musb_ep_select(mbase, epnum); | |
1566 | val &= ~MUSB_RXCSR_H_REQPKT; | |
1567 | musb_writew(epio, MUSB_RXCSR, val); | |
1568 | goto finish; | |
1569 | } | |
1570 | ||
1571 | /* we are expecting IN packets */ | |
1572 | #ifdef CONFIG_USB_INVENTRA_DMA | |
1573 | if (dma) { | |
1574 | struct dma_controller *c; | |
1575 | u16 rx_count; | |
f82a689f AKG |
1576 | int ret, length; |
1577 | dma_addr_t buf; | |
550a7375 FB |
1578 | |
1579 | rx_count = musb_readw(epio, MUSB_RXCOUNT); | |
1580 | ||
1581 | DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n", | |
1582 | epnum, rx_count, | |
1583 | urb->transfer_dma | |
1584 | + urb->actual_length, | |
1585 | qh->offset, | |
1586 | urb->transfer_buffer_length); | |
1587 | ||
1588 | c = musb->dma_controller; | |
1589 | ||
f82a689f AKG |
1590 | if (usb_pipeisoc(pipe)) { |
1591 | int status = 0; | |
1592 | struct usb_iso_packet_descriptor *d; | |
1593 | ||
1594 | d = urb->iso_frame_desc + qh->iso_idx; | |
1595 | ||
1596 | if (iso_err) { | |
1597 | status = -EILSEQ; | |
1598 | urb->error_count++; | |
1599 | } | |
1600 | if (rx_count > d->length) { | |
1601 | if (status == 0) { | |
1602 | status = -EOVERFLOW; | |
1603 | urb->error_count++; | |
1604 | } | |
1605 | DBG(2, "** OVERFLOW %d into %d\n",\ | |
1606 | rx_count, d->length); | |
1607 | ||
1608 | length = d->length; | |
1609 | } else | |
1610 | length = rx_count; | |
1611 | d->status = status; | |
1612 | buf = urb->transfer_dma + d->offset; | |
1613 | } else { | |
1614 | length = rx_count; | |
1615 | buf = urb->transfer_dma + | |
1616 | urb->actual_length; | |
1617 | } | |
1618 | ||
550a7375 FB |
1619 | dma->desired_mode = 0; |
1620 | #ifdef USE_MODE1 | |
1621 | /* because of the issue below, mode 1 will | |
1622 | * only rarely behave with correct semantics. | |
1623 | */ | |
1624 | if ((urb->transfer_flags & | |
1625 | URB_SHORT_NOT_OK) | |
1626 | && (urb->transfer_buffer_length - | |
1627 | urb->actual_length) | |
1628 | > qh->maxpacket) | |
1629 | dma->desired_mode = 1; | |
f82a689f AKG |
1630 | if (rx_count < hw_ep->max_packet_sz_rx) { |
1631 | length = rx_count; | |
1632 | dma->bDesiredMode = 0; | |
1633 | } else { | |
1634 | length = urb->transfer_buffer_length; | |
1635 | } | |
550a7375 FB |
1636 | #endif |
1637 | ||
1638 | /* Disadvantage of using mode 1: | |
1639 | * It's basically usable only for mass storage class; essentially all | |
1640 | * other protocols also terminate transfers on short packets. | |
1641 | * | |
1642 | * Details: | |
1643 | * An extra IN token is sent at the end of the transfer (due to AUTOREQ) | |
1644 | * If you try to use mode 1 for (transfer_buffer_length - 512), and try | |
1645 | * to use the extra IN token to grab the last packet using mode 0, then | |
1646 | * the problem is that you cannot be sure when the device will send the | |
1647 | * last packet and RxPktRdy set. Sometimes the packet is recd too soon | |
1648 | * such that it gets lost when RxCSR is re-set at the end of the mode 1 | |
1649 | * transfer, while sometimes it is recd just a little late so that if you | |
1650 | * try to configure for mode 0 soon after the mode 1 transfer is | |
1651 | * completed, you will find rxcount 0. Okay, so you might think why not | |
1652 | * wait for an interrupt when the pkt is recd. Well, you won't get any! | |
1653 | */ | |
1654 | ||
1655 | val = musb_readw(epio, MUSB_RXCSR); | |
1656 | val &= ~MUSB_RXCSR_H_REQPKT; | |
1657 | ||
1658 | if (dma->desired_mode == 0) | |
1659 | val &= ~MUSB_RXCSR_H_AUTOREQ; | |
1660 | else | |
1661 | val |= MUSB_RXCSR_H_AUTOREQ; | |
1662 | val |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB; | |
1663 | ||
1664 | musb_writew(epio, MUSB_RXCSR, | |
1665 | MUSB_RXCSR_H_WZC_BITS | val); | |
1666 | ||
1667 | /* REVISIT if when actual_length != 0, | |
1668 | * transfer_buffer_length needs to be | |
1669 | * adjusted first... | |
1670 | */ | |
1671 | ret = c->channel_program( | |
1672 | dma, qh->maxpacket, | |
f82a689f | 1673 | dma->desired_mode, buf, length); |
550a7375 FB |
1674 | |
1675 | if (!ret) { | |
1676 | c->channel_release(dma); | |
1677 | hw_ep->rx_channel = NULL; | |
1678 | dma = NULL; | |
1679 | /* REVISIT reset CSR */ | |
1680 | } | |
1681 | } | |
1682 | #endif /* Mentor DMA */ | |
1683 | ||
1684 | if (!dma) { | |
1685 | done = musb_host_packet_rx(musb, urb, | |
1686 | epnum, iso_err); | |
1687 | DBG(6, "read %spacket\n", done ? "last " : ""); | |
1688 | } | |
1689 | } | |
1690 | ||
550a7375 FB |
1691 | finish: |
1692 | urb->actual_length += xfer_len; | |
1693 | qh->offset += xfer_len; | |
1694 | if (done) { | |
1695 | if (urb->status == -EINPROGRESS) | |
1696 | urb->status = status; | |
1697 | musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); | |
1698 | } | |
1699 | } | |
1700 | ||
1701 | /* schedule nodes correspond to peripheral endpoints, like an OHCI QH. | |
1702 | * the software schedule associates multiple such nodes with a given | |
1703 | * host side hardware endpoint + direction; scheduling may activate | |
1704 | * that hardware endpoint. | |
1705 | */ | |
1706 | static int musb_schedule( | |
1707 | struct musb *musb, | |
1708 | struct musb_qh *qh, | |
1709 | int is_in) | |
1710 | { | |
1711 | int idle; | |
1712 | int best_diff; | |
1713 | int best_end, epnum; | |
1714 | struct musb_hw_ep *hw_ep = NULL; | |
1715 | struct list_head *head = NULL; | |
1716 | ||
1717 | /* use fixed hardware for control and bulk */ | |
23d15e07 | 1718 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) { |
550a7375 FB |
1719 | head = &musb->control; |
1720 | hw_ep = musb->control_ep; | |
550a7375 FB |
1721 | goto success; |
1722 | } | |
1723 | ||
1724 | /* else, periodic transfers get muxed to other endpoints */ | |
1725 | ||
1726 | /* FIXME this doesn't consider direction, so it can only | |
1727 | * work for one half of the endpoint hardware, and assumes | |
1728 | * the previous cases handled all non-shared endpoints... | |
1729 | */ | |
1730 | ||
1731 | /* we know this qh hasn't been scheduled, so all we need to do | |
1732 | * is choose which hardware endpoint to put it on ... | |
1733 | * | |
1734 | * REVISIT what we really want here is a regular schedule tree | |
1735 | * like e.g. OHCI uses, but for now musb->periodic is just an | |
1736 | * array of the _single_ logical endpoint associated with a | |
1737 | * given physical one (identity mapping logical->physical). | |
1738 | * | |
1739 | * that simplistic approach makes TT scheduling a lot simpler; | |
1740 | * there is none, and thus none of its complexity... | |
1741 | */ | |
1742 | best_diff = 4096; | |
1743 | best_end = -1; | |
1744 | ||
1745 | for (epnum = 1; epnum < musb->nr_endpoints; epnum++) { | |
1746 | int diff; | |
1747 | ||
1748 | if (musb->periodic[epnum]) | |
1749 | continue; | |
1750 | hw_ep = &musb->endpoints[epnum]; | |
1751 | if (hw_ep == musb->bulk_ep) | |
1752 | continue; | |
1753 | ||
1754 | if (is_in) | |
1755 | diff = hw_ep->max_packet_sz_rx - qh->maxpacket; | |
1756 | else | |
1757 | diff = hw_ep->max_packet_sz_tx - qh->maxpacket; | |
1758 | ||
23d15e07 | 1759 | if (diff >= 0 && best_diff > diff) { |
550a7375 FB |
1760 | best_diff = diff; |
1761 | best_end = epnum; | |
1762 | } | |
1763 | } | |
23d15e07 | 1764 | /* use bulk reserved ep1 if no other ep is free */ |
aa5cbbec | 1765 | if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { |
23d15e07 AKG |
1766 | hw_ep = musb->bulk_ep; |
1767 | if (is_in) | |
1768 | head = &musb->in_bulk; | |
1769 | else | |
1770 | head = &musb->out_bulk; | |
1771 | goto success; | |
1772 | } else if (best_end < 0) { | |
550a7375 | 1773 | return -ENOSPC; |
23d15e07 | 1774 | } |
550a7375 FB |
1775 | |
1776 | idle = 1; | |
23d15e07 | 1777 | qh->mux = 0; |
550a7375 FB |
1778 | hw_ep = musb->endpoints + best_end; |
1779 | musb->periodic[best_end] = qh; | |
1780 | DBG(4, "qh %p periodic slot %d\n", qh, best_end); | |
1781 | success: | |
23d15e07 AKG |
1782 | if (head) { |
1783 | idle = list_empty(head); | |
1784 | list_add_tail(&qh->ring, head); | |
1785 | qh->mux = 1; | |
1786 | } | |
550a7375 FB |
1787 | qh->hw_ep = hw_ep; |
1788 | qh->hep->hcpriv = qh; | |
1789 | if (idle) | |
1790 | musb_start_urb(musb, is_in, qh); | |
1791 | return 0; | |
1792 | } | |
1793 | ||
1794 | static int musb_urb_enqueue( | |
1795 | struct usb_hcd *hcd, | |
1796 | struct urb *urb, | |
1797 | gfp_t mem_flags) | |
1798 | { | |
1799 | unsigned long flags; | |
1800 | struct musb *musb = hcd_to_musb(hcd); | |
1801 | struct usb_host_endpoint *hep = urb->ep; | |
1802 | struct musb_qh *qh = hep->hcpriv; | |
1803 | struct usb_endpoint_descriptor *epd = &hep->desc; | |
1804 | int ret; | |
1805 | unsigned type_reg; | |
1806 | unsigned interval; | |
1807 | ||
1808 | /* host role must be active */ | |
1809 | if (!is_host_active(musb) || !musb->is_active) | |
1810 | return -ENODEV; | |
1811 | ||
1812 | spin_lock_irqsave(&musb->lock, flags); | |
1813 | ret = usb_hcd_link_urb_to_ep(hcd, urb); | |
1814 | spin_unlock_irqrestore(&musb->lock, flags); | |
1815 | if (ret) | |
1816 | return ret; | |
1817 | ||
1818 | /* DMA mapping was already done, if needed, and this urb is on | |
1819 | * hep->urb_list ... so there's little to do unless hep wasn't | |
1820 | * yet scheduled onto a live qh. | |
1821 | * | |
1822 | * REVISIT best to keep hep->hcpriv valid until the endpoint gets | |
1823 | * disabled, testing for empty qh->ring and avoiding qh setup costs | |
1824 | * except for the first urb queued after a config change. | |
1825 | */ | |
1826 | if (qh) { | |
1827 | urb->hcpriv = qh; | |
1828 | return 0; | |
1829 | } | |
1830 | ||
1831 | /* Allocate and initialize qh, minimizing the work done each time | |
1832 | * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. | |
1833 | * | |
1834 | * REVISIT consider a dedicated qh kmem_cache, so it's harder | |
1835 | * for bugs in other kernel code to break this driver... | |
1836 | */ | |
1837 | qh = kzalloc(sizeof *qh, mem_flags); | |
1838 | if (!qh) { | |
2492e674 | 1839 | spin_lock_irqsave(&musb->lock, flags); |
550a7375 | 1840 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
2492e674 | 1841 | spin_unlock_irqrestore(&musb->lock, flags); |
550a7375 FB |
1842 | return -ENOMEM; |
1843 | } | |
1844 | ||
1845 | qh->hep = hep; | |
1846 | qh->dev = urb->dev; | |
1847 | INIT_LIST_HEAD(&qh->ring); | |
1848 | qh->is_ready = 1; | |
1849 | ||
1850 | qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize); | |
1851 | ||
1852 | /* no high bandwidth support yet */ | |
1853 | if (qh->maxpacket & ~0x7ff) { | |
1854 | ret = -EMSGSIZE; | |
1855 | goto done; | |
1856 | } | |
1857 | ||
1858 | qh->epnum = epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; | |
1859 | qh->type = epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; | |
1860 | ||
1861 | /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ | |
1862 | qh->addr_reg = (u8) usb_pipedevice(urb->pipe); | |
1863 | ||
1864 | /* precompute rxtype/txtype/type0 register */ | |
1865 | type_reg = (qh->type << 4) | qh->epnum; | |
1866 | switch (urb->dev->speed) { | |
1867 | case USB_SPEED_LOW: | |
1868 | type_reg |= 0xc0; | |
1869 | break; | |
1870 | case USB_SPEED_FULL: | |
1871 | type_reg |= 0x80; | |
1872 | break; | |
1873 | default: | |
1874 | type_reg |= 0x40; | |
1875 | } | |
1876 | qh->type_reg = type_reg; | |
1877 | ||
1878 | /* precompute rxinterval/txinterval register */ | |
1879 | interval = min((u8)16, epd->bInterval); /* log encoding */ | |
1880 | switch (qh->type) { | |
1881 | case USB_ENDPOINT_XFER_INT: | |
1882 | /* fullspeed uses linear encoding */ | |
1883 | if (USB_SPEED_FULL == urb->dev->speed) { | |
1884 | interval = epd->bInterval; | |
1885 | if (!interval) | |
1886 | interval = 1; | |
1887 | } | |
1888 | /* FALLTHROUGH */ | |
1889 | case USB_ENDPOINT_XFER_ISOC: | |
1890 | /* iso always uses log encoding */ | |
1891 | break; | |
1892 | default: | |
1893 | /* REVISIT we actually want to use NAK limits, hinting to the | |
1894 | * transfer scheduling logic to try some other qh, e.g. try | |
1895 | * for 2 msec first: | |
1896 | * | |
1897 | * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; | |
1898 | * | |
1899 | * The downside of disabling this is that transfer scheduling | |
1900 | * gets VERY unfair for nonperiodic transfers; a misbehaving | |
1901 | * peripheral could make that hurt. Or for reads, one that's | |
1902 | * perfectly normal: network and other drivers keep reads | |
1903 | * posted at all times, having one pending for a week should | |
1904 | * be perfectly safe. | |
1905 | * | |
1906 | * The upside of disabling it is avoidng transfer scheduling | |
1907 | * code to put this aside for while. | |
1908 | */ | |
1909 | interval = 0; | |
1910 | } | |
1911 | qh->intv_reg = interval; | |
1912 | ||
1913 | /* precompute addressing for external hub/tt ports */ | |
1914 | if (musb->is_multipoint) { | |
1915 | struct usb_device *parent = urb->dev->parent; | |
1916 | ||
1917 | if (parent != hcd->self.root_hub) { | |
1918 | qh->h_addr_reg = (u8) parent->devnum; | |
1919 | ||
1920 | /* set up tt info if needed */ | |
1921 | if (urb->dev->tt) { | |
1922 | qh->h_port_reg = (u8) urb->dev->ttport; | |
ae5ad296 AKG |
1923 | if (urb->dev->tt->hub) |
1924 | qh->h_addr_reg = | |
1925 | (u8) urb->dev->tt->hub->devnum; | |
1926 | if (urb->dev->tt->multi) | |
1927 | qh->h_addr_reg |= 0x80; | |
550a7375 FB |
1928 | } |
1929 | } | |
1930 | } | |
1931 | ||
1932 | /* invariant: hep->hcpriv is null OR the qh that's already scheduled. | |
1933 | * until we get real dma queues (with an entry for each urb/buffer), | |
1934 | * we only have work to do in the former case. | |
1935 | */ | |
1936 | spin_lock_irqsave(&musb->lock, flags); | |
1937 | if (hep->hcpriv) { | |
1938 | /* some concurrent activity submitted another urb to hep... | |
1939 | * odd, rare, error prone, but legal. | |
1940 | */ | |
1941 | kfree(qh); | |
1942 | ret = 0; | |
1943 | } else | |
1944 | ret = musb_schedule(musb, qh, | |
1945 | epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); | |
1946 | ||
1947 | if (ret == 0) { | |
1948 | urb->hcpriv = qh; | |
1949 | /* FIXME set urb->start_frame for iso/intr, it's tested in | |
1950 | * musb_start_urb(), but otherwise only konicawc cares ... | |
1951 | */ | |
1952 | } | |
1953 | spin_unlock_irqrestore(&musb->lock, flags); | |
1954 | ||
1955 | done: | |
1956 | if (ret != 0) { | |
2492e674 | 1957 | spin_lock_irqsave(&musb->lock, flags); |
550a7375 | 1958 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
2492e674 | 1959 | spin_unlock_irqrestore(&musb->lock, flags); |
550a7375 FB |
1960 | kfree(qh); |
1961 | } | |
1962 | return ret; | |
1963 | } | |
1964 | ||
1965 | ||
1966 | /* | |
1967 | * abort a transfer that's at the head of a hardware queue. | |
1968 | * called with controller locked, irqs blocked | |
1969 | * that hardware queue advances to the next transfer, unless prevented | |
1970 | */ | |
1971 | static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh, int is_in) | |
1972 | { | |
1973 | struct musb_hw_ep *ep = qh->hw_ep; | |
1974 | void __iomem *epio = ep->regs; | |
1975 | unsigned hw_end = ep->epnum; | |
1976 | void __iomem *regs = ep->musb->mregs; | |
1977 | u16 csr; | |
1978 | int status = 0; | |
1979 | ||
1980 | musb_ep_select(regs, hw_end); | |
1981 | ||
1982 | if (is_dma_capable()) { | |
1983 | struct dma_channel *dma; | |
1984 | ||
1985 | dma = is_in ? ep->rx_channel : ep->tx_channel; | |
1986 | if (dma) { | |
1987 | status = ep->musb->dma_controller->channel_abort(dma); | |
1988 | DBG(status ? 1 : 3, | |
1989 | "abort %cX%d DMA for urb %p --> %d\n", | |
1990 | is_in ? 'R' : 'T', ep->epnum, | |
1991 | urb, status); | |
1992 | urb->actual_length += dma->actual_len; | |
1993 | } | |
1994 | } | |
1995 | ||
1996 | /* turn off DMA requests, discard state, stop polling ... */ | |
1997 | if (is_in) { | |
1998 | /* giveback saves bulk toggle */ | |
1999 | csr = musb_h_flush_rxfifo(ep, 0); | |
2000 | ||
2001 | /* REVISIT we still get an irq; should likely clear the | |
2002 | * endpoint's irq status here to avoid bogus irqs. | |
2003 | * clearing that status is platform-specific... | |
2004 | */ | |
2005 | } else { | |
2006 | musb_h_tx_flush_fifo(ep); | |
2007 | csr = musb_readw(epio, MUSB_TXCSR); | |
2008 | csr &= ~(MUSB_TXCSR_AUTOSET | |
2009 | | MUSB_TXCSR_DMAENAB | |
2010 | | MUSB_TXCSR_H_RXSTALL | |
2011 | | MUSB_TXCSR_H_NAKTIMEOUT | |
2012 | | MUSB_TXCSR_H_ERROR | |
2013 | | MUSB_TXCSR_TXPKTRDY); | |
2014 | musb_writew(epio, MUSB_TXCSR, csr); | |
2015 | /* REVISIT may need to clear FLUSHFIFO ... */ | |
2016 | musb_writew(epio, MUSB_TXCSR, csr); | |
2017 | /* flush cpu writebuffer */ | |
2018 | csr = musb_readw(epio, MUSB_TXCSR); | |
2019 | } | |
2020 | if (status == 0) | |
2021 | musb_advance_schedule(ep->musb, urb, ep, is_in); | |
2022 | return status; | |
2023 | } | |
2024 | ||
2025 | static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) | |
2026 | { | |
2027 | struct musb *musb = hcd_to_musb(hcd); | |
2028 | struct musb_qh *qh; | |
2029 | struct list_head *sched; | |
2030 | unsigned long flags; | |
2031 | int ret; | |
2032 | ||
2033 | DBG(4, "urb=%p, dev%d ep%d%s\n", urb, | |
2034 | usb_pipedevice(urb->pipe), | |
2035 | usb_pipeendpoint(urb->pipe), | |
2036 | usb_pipein(urb->pipe) ? "in" : "out"); | |
2037 | ||
2038 | spin_lock_irqsave(&musb->lock, flags); | |
2039 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); | |
2040 | if (ret) | |
2041 | goto done; | |
2042 | ||
2043 | qh = urb->hcpriv; | |
2044 | if (!qh) | |
2045 | goto done; | |
2046 | ||
2047 | /* Any URB not actively programmed into endpoint hardware can be | |
2048 | * immediately given back. Such an URB must be at the head of its | |
2049 | * endpoint queue, unless someday we get real DMA queues. And even | |
2050 | * then, it might not be known to the hardware... | |
2051 | * | |
2052 | * Otherwise abort current transfer, pending dma, etc.; urb->status | |
2053 | * has already been updated. This is a synchronous abort; it'd be | |
2054 | * OK to hold off until after some IRQ, though. | |
2055 | */ | |
2056 | if (!qh->is_ready || urb->urb_list.prev != &qh->hep->urb_list) | |
2057 | ret = -EINPROGRESS; | |
2058 | else { | |
2059 | switch (qh->type) { | |
2060 | case USB_ENDPOINT_XFER_CONTROL: | |
2061 | sched = &musb->control; | |
2062 | break; | |
2063 | case USB_ENDPOINT_XFER_BULK: | |
23d15e07 AKG |
2064 | if (qh->mux == 1) { |
2065 | if (usb_pipein(urb->pipe)) | |
2066 | sched = &musb->in_bulk; | |
2067 | else | |
2068 | sched = &musb->out_bulk; | |
2069 | break; | |
2070 | } | |
550a7375 FB |
2071 | default: |
2072 | /* REVISIT when we get a schedule tree, periodic | |
2073 | * transfers won't always be at the head of a | |
2074 | * singleton queue... | |
2075 | */ | |
2076 | sched = NULL; | |
2077 | break; | |
2078 | } | |
2079 | } | |
2080 | ||
2081 | /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ | |
2082 | if (ret < 0 || (sched && qh != first_qh(sched))) { | |
2083 | int ready = qh->is_ready; | |
2084 | ||
2085 | ret = 0; | |
2086 | qh->is_ready = 0; | |
2087 | __musb_giveback(musb, urb, 0); | |
2088 | qh->is_ready = ready; | |
2089 | } else | |
2090 | ret = musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN); | |
2091 | done: | |
2092 | spin_unlock_irqrestore(&musb->lock, flags); | |
2093 | return ret; | |
2094 | } | |
2095 | ||
2096 | /* disable an endpoint */ | |
2097 | static void | |
2098 | musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) | |
2099 | { | |
2100 | u8 epnum = hep->desc.bEndpointAddress; | |
2101 | unsigned long flags; | |
2102 | struct musb *musb = hcd_to_musb(hcd); | |
2103 | u8 is_in = epnum & USB_DIR_IN; | |
2104 | struct musb_qh *qh = hep->hcpriv; | |
2105 | struct urb *urb, *tmp; | |
2106 | struct list_head *sched; | |
2107 | ||
2108 | if (!qh) | |
2109 | return; | |
2110 | ||
2111 | spin_lock_irqsave(&musb->lock, flags); | |
2112 | ||
2113 | switch (qh->type) { | |
2114 | case USB_ENDPOINT_XFER_CONTROL: | |
2115 | sched = &musb->control; | |
2116 | break; | |
2117 | case USB_ENDPOINT_XFER_BULK: | |
23d15e07 AKG |
2118 | if (qh->mux == 1) { |
2119 | if (is_in) | |
2120 | sched = &musb->in_bulk; | |
2121 | else | |
2122 | sched = &musb->out_bulk; | |
2123 | break; | |
2124 | } | |
550a7375 FB |
2125 | default: |
2126 | /* REVISIT when we get a schedule tree, periodic transfers | |
2127 | * won't always be at the head of a singleton queue... | |
2128 | */ | |
2129 | sched = NULL; | |
2130 | break; | |
2131 | } | |
2132 | ||
2133 | /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ | |
2134 | ||
2135 | /* kick first urb off the hardware, if needed */ | |
2136 | qh->is_ready = 0; | |
2137 | if (!sched || qh == first_qh(sched)) { | |
2138 | urb = next_urb(qh); | |
2139 | ||
2140 | /* make software (then hardware) stop ASAP */ | |
2141 | if (!urb->unlinked) | |
2142 | urb->status = -ESHUTDOWN; | |
2143 | ||
2144 | /* cleanup */ | |
2145 | musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN); | |
2146 | } else | |
2147 | urb = NULL; | |
2148 | ||
2149 | /* then just nuke all the others */ | |
2150 | list_for_each_entry_safe_from(urb, tmp, &hep->urb_list, urb_list) | |
2151 | musb_giveback(qh, urb, -ESHUTDOWN); | |
2152 | ||
2153 | spin_unlock_irqrestore(&musb->lock, flags); | |
2154 | } | |
2155 | ||
2156 | static int musb_h_get_frame_number(struct usb_hcd *hcd) | |
2157 | { | |
2158 | struct musb *musb = hcd_to_musb(hcd); | |
2159 | ||
2160 | return musb_readw(musb->mregs, MUSB_FRAME); | |
2161 | } | |
2162 | ||
2163 | static int musb_h_start(struct usb_hcd *hcd) | |
2164 | { | |
2165 | struct musb *musb = hcd_to_musb(hcd); | |
2166 | ||
2167 | /* NOTE: musb_start() is called when the hub driver turns | |
2168 | * on port power, or when (OTG) peripheral starts. | |
2169 | */ | |
2170 | hcd->state = HC_STATE_RUNNING; | |
2171 | musb->port1_status = 0; | |
2172 | return 0; | |
2173 | } | |
2174 | ||
2175 | static void musb_h_stop(struct usb_hcd *hcd) | |
2176 | { | |
2177 | musb_stop(hcd_to_musb(hcd)); | |
2178 | hcd->state = HC_STATE_HALT; | |
2179 | } | |
2180 | ||
2181 | static int musb_bus_suspend(struct usb_hcd *hcd) | |
2182 | { | |
2183 | struct musb *musb = hcd_to_musb(hcd); | |
2184 | ||
2185 | if (musb->xceiv.state == OTG_STATE_A_SUSPEND) | |
2186 | return 0; | |
2187 | ||
2188 | if (is_host_active(musb) && musb->is_active) { | |
2189 | WARNING("trying to suspend as %s is_active=%i\n", | |
2190 | otg_state_string(musb), musb->is_active); | |
2191 | return -EBUSY; | |
2192 | } else | |
2193 | return 0; | |
2194 | } | |
2195 | ||
2196 | static int musb_bus_resume(struct usb_hcd *hcd) | |
2197 | { | |
2198 | /* resuming child port does the work */ | |
2199 | return 0; | |
2200 | } | |
2201 | ||
2202 | const struct hc_driver musb_hc_driver = { | |
2203 | .description = "musb-hcd", | |
2204 | .product_desc = "MUSB HDRC host driver", | |
2205 | .hcd_priv_size = sizeof(struct musb), | |
2206 | .flags = HCD_USB2 | HCD_MEMORY, | |
2207 | ||
2208 | /* not using irq handler or reset hooks from usbcore, since | |
2209 | * those must be shared with peripheral code for OTG configs | |
2210 | */ | |
2211 | ||
2212 | .start = musb_h_start, | |
2213 | .stop = musb_h_stop, | |
2214 | ||
2215 | .get_frame_number = musb_h_get_frame_number, | |
2216 | ||
2217 | .urb_enqueue = musb_urb_enqueue, | |
2218 | .urb_dequeue = musb_urb_dequeue, | |
2219 | .endpoint_disable = musb_h_disable, | |
2220 | ||
2221 | .hub_status_data = musb_hub_status_data, | |
2222 | .hub_control = musb_hub_control, | |
2223 | .bus_suspend = musb_bus_suspend, | |
2224 | .bus_resume = musb_bus_resume, | |
2225 | /* .start_port_reset = NULL, */ | |
2226 | /* .hub_irq_enable = NULL, */ | |
2227 | }; |