[mirror_ubuntu-focal-kernel.git] / drivers / usb / musb / musbhsdma.c

// SPDX-License-Identifier: GPL-2.0
/*
 * MUSB OTG driver - support for Mentor's DMA controller
 *
 * Copyright 2005 Mentor Graphics Corporation
 * Copyright (C) 2005-2007 by Texas Instruments
 */
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "musb_core.h"

#define MUSB_HSDMA_BASE		0x200
#define MUSB_HSDMA_INTR		(MUSB_HSDMA_BASE + 0)
#define MUSB_HSDMA_CONTROL		0x4
#define MUSB_HSDMA_ADDRESS		0x8
#define MUSB_HSDMA_COUNT		0xc

#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)		\
		(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)

#define musb_read_hsdma_addr(mbase, bchannel)	\
	musb_readl(mbase,	\
		   MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))

#define musb_write_hsdma_addr(mbase, bchannel, addr) \
	musb_writel(mbase, \
		    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
		    addr)

#define musb_read_hsdma_count(mbase, bchannel)	\
	musb_readl(mbase,	\
		   MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))

#define musb_write_hsdma_count(mbase, bchannel, len) \
	musb_writel(mbase, \
		    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
		    len)
/* control register (16-bit): */
#define MUSB_HSDMA_ENABLE_SHIFT		0
#define MUSB_HSDMA_TRANSMIT_SHIFT	1
#define MUSB_HSDMA_MODE1_SHIFT		2
#define MUSB_HSDMA_IRQENABLE_SHIFT	3
#define MUSB_HSDMA_ENDPOINT_SHIFT	4
#define MUSB_HSDMA_BUSERROR_SHIFT	8
#define MUSB_HSDMA_BURSTMODE_SHIFT	9
#define MUSB_HSDMA_BURSTMODE		(3 << MUSB_HSDMA_BURSTMODE_SHIFT)
#define MUSB_HSDMA_BURSTMODE_UNSPEC	0
#define MUSB_HSDMA_BURSTMODE_INCR4	1
#define MUSB_HSDMA_BURSTMODE_INCR8	2
#define MUSB_HSDMA_BURSTMODE_INCR16	3

#define MUSB_HSDMA_CHANNELS		8

struct musb_dma_controller;

struct musb_dma_channel {
	struct dma_channel		channel;
	struct musb_dma_controller	*controller;
	u32				start_addr;
	u32				len;
	u16				max_packet_sz;
	u8				idx;
	u8				epnum;
	u8				transmit;
};

struct musb_dma_controller {
	struct dma_controller		controller;
	struct musb_dma_channel		channel[MUSB_HSDMA_CHANNELS];
	void				*private_data;
	void __iomem			*base;
	u8				channel_count;
	u8				used_channels;
	int				irq;
};

static void dma_channel_release(struct dma_channel *channel);

static void dma_controller_stop(struct musb_dma_controller *controller)
{
	struct musb *musb = controller->private_data;
	struct dma_channel *channel;
	u8 bit;

	if (controller->used_channels != 0) {
		dev_err(musb->controller,
			"Stopping DMA controller while channel active\n");

		for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
			if (controller->used_channels & (1 << bit)) {
				channel = &controller->channel[bit].channel;
				dma_channel_release(channel);

				if (!controller->used_channels)
					break;
			}
		}
	}
}

static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
				struct musb_hw_ep *hw_ep, u8 transmit)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);
	struct musb_dma_channel *musb_channel = NULL;
	struct dma_channel *channel = NULL;
	u8 bit;

	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
		if (!(controller->used_channels & (1 << bit))) {
			controller->used_channels |= (1 << bit);
			musb_channel = &(controller->channel[bit]);
			musb_channel->controller = controller;
			musb_channel->idx = bit;
			musb_channel->epnum = hw_ep->epnum;
			musb_channel->transmit = transmit;
			channel = &(musb_channel->channel);
			channel->private_data = musb_channel;
			channel->status = MUSB_DMA_STATUS_FREE;
			channel->max_len = 0x100000;
			/* Tx => mode 1; Rx => mode 0 */
			channel->desired_mode = transmit;
			channel->actual_len = 0;
			break;
		}
	}

	return channel;
}

static void dma_channel_release(struct dma_channel *channel)
{
	struct musb_dma_channel *musb_channel = channel->private_data;

	channel->actual_len = 0;
	musb_channel->start_addr = 0;
	musb_channel->len = 0;

	musb_channel->controller->used_channels &=
		~(1 << musb_channel->idx);

	channel->status = MUSB_DMA_STATUS_UNKNOWN;
}

static void configure_channel(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	struct musb_dma_controller *controller = musb_channel->controller;
	struct musb *musb = controller->private_data;
	void __iomem *mbase = controller->base;
	u8 bchannel = musb_channel->idx;
	u16 csr = 0;

	musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d",
			channel, packet_sz, &dma_addr, len, mode);

	if (mode) {
		csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
		BUG_ON(len < packet_sz);
	}
	csr |= MUSB_HSDMA_BURSTMODE_INCR16
				<< MUSB_HSDMA_BURSTMODE_SHIFT;

	csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
		| (1 << MUSB_HSDMA_ENABLE_SHIFT)
		| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
		| (musb_channel->transmit
				? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
				: 0);

	/* address/count */
	musb_write_hsdma_addr(mbase, bchannel, dma_addr);
	musb_write_hsdma_count(mbase, bchannel, len);

	/* control (this should start things) */
	musb_writew(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
		csr);
}

static int dma_channel_program(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	struct musb_dma_controller *controller = musb_channel->controller;
	struct musb *musb = controller->private_data;

	musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d",
		musb_channel->epnum,
		musb_channel->transmit ? "Tx" : "Rx",
		packet_sz, &dma_addr, len, mode);

	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
		channel->status == MUSB_DMA_STATUS_BUSY);

	/*
	 * The DMA engine in RTL1.8 and above cannot handle
	 * DMA addresses that are not aligned to a 4 byte boundary.
	 * It ends up masking the last two bits of the address
	 * programmed in DMA_ADDR.
	 *
	 * Fail such DMA transfers, so that the backup PIO mode
	 * can carry out the transfer
	 */
	if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
		return false;

	channel->actual_len = 0;
	musb_channel->start_addr = dma_addr;
	musb_channel->len = len;
	musb_channel->max_packet_sz = packet_sz;
	channel->status = MUSB_DMA_STATUS_BUSY;

	configure_channel(channel, packet_sz, mode, dma_addr, len);

	return true;
}

static int dma_channel_abort(struct dma_channel *channel)
{
	struct musb_dma_channel *musb_channel = channel->private_data;
	void __iomem *mbase = musb_channel->controller->base;
	struct musb *musb = musb_channel->controller->private_data;

	u8 bchannel = musb_channel->idx;
	int offset;
	u16 csr;

	if (channel->status == MUSB_DMA_STATUS_BUSY) {
		if (musb_channel->transmit) {
			offset = musb->io.ep_offset(musb_channel->epnum,
						MUSB_TXCSR);

			/*
			 * The programming guide says that we must clear
			 * the DMAENAB bit before the DMAMODE bit...
			 */
			csr = musb_readw(mbase, offset);
			csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
			musb_writew(mbase, offset, csr);
			csr &= ~MUSB_TXCSR_DMAMODE;
			musb_writew(mbase, offset, csr);
		} else {
			offset = musb->io.ep_offset(musb_channel->epnum,
						MUSB_RXCSR);

			csr = musb_readw(mbase, offset);
			csr &= ~(MUSB_RXCSR_AUTOCLEAR |
				 MUSB_RXCSR_DMAENAB |
				 MUSB_RXCSR_DMAMODE);
			musb_writew(mbase, offset, csr);
		}

		musb_writew(mbase,
			MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
			0);
		musb_write_hsdma_addr(mbase, bchannel, 0);
		musb_write_hsdma_count(mbase, bchannel, 0);
		channel->status = MUSB_DMA_STATUS_FREE;
	}

	return 0;
}

static irqreturn_t dma_controller_irq(int irq, void *private_data)
{
	struct musb_dma_controller *controller = private_data;
	struct musb *musb = controller->private_data;
	struct musb_dma_channel *musb_channel;
	struct dma_channel *channel;

	void __iomem *mbase = controller->base;

	irqreturn_t retval = IRQ_NONE;

	unsigned long flags;

	u8 bchannel;
	u8 int_hsdma;

	u32 addr, count;
	u16 csr;

	spin_lock_irqsave(&musb->lock, flags);

	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);

	if (!int_hsdma) {
		musb_dbg(musb, "spurious DMA irq");

		for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
			musb_channel = (struct musb_dma_channel *)
					&(controller->channel[bchannel]);
			channel = &musb_channel->channel;
			if (channel->status == MUSB_DMA_STATUS_BUSY) {
				count = musb_read_hsdma_count(mbase, bchannel);

				if (count == 0)
					int_hsdma |= (1 << bchannel);
			}
		}

		musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma);

		if (!int_hsdma)
			goto done;
	}

	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
		if (int_hsdma & (1 << bchannel)) {
			musb_channel = (struct musb_dma_channel *)
					&(controller->channel[bchannel]);
			channel = &musb_channel->channel;

			csr = musb_readw(mbase,
					MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
							MUSB_HSDMA_CONTROL));

			if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
				musb_channel->channel.status =
					MUSB_DMA_STATUS_BUS_ABORT;
			} else {
				u8 devctl;

				addr = musb_read_hsdma_addr(mbase,
						bchannel);
				channel->actual_len = addr
					- musb_channel->start_addr;

				musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s",
					channel, musb_channel->start_addr,
					addr, channel->actual_len,
					musb_channel->len,
					(channel->actual_len
						< musb_channel->len) ?
					"=> reconfig 0" : "=> complete");

				devctl = musb_readb(mbase, MUSB_DEVCTL);

				channel->status = MUSB_DMA_STATUS_FREE;

				/* completed */
				if (musb_channel->transmit &&
					(!channel->desired_mode ||
					(channel->actual_len %
					    musb_channel->max_packet_sz))) {
					u8  epnum  = musb_channel->epnum;
					int offset = musb->io.ep_offset(epnum,
								    MUSB_TXCSR);
					u16 txcsr;

					/*
					 * The programming guide says that we
					 * must clear DMAENAB before DMAMODE.
					 */
					musb_ep_select(mbase, epnum);
					txcsr = musb_readw(mbase, offset);
					if (channel->desired_mode == 1) {
						txcsr &= ~(MUSB_TXCSR_DMAENAB
							| MUSB_TXCSR_AUTOSET);
						musb_writew(mbase, offset, txcsr);
						/* Send out the packet */
						txcsr &= ~MUSB_TXCSR_DMAMODE;
						txcsr |= MUSB_TXCSR_DMAENAB;
					}
					txcsr |=  MUSB_TXCSR_TXPKTRDY;
					musb_writew(mbase, offset, txcsr);
				}
				musb_dma_completion(musb, musb_channel->epnum,
						    musb_channel->transmit);
			}
		}
	}

	retval = IRQ_HANDLED;
done:
	spin_unlock_irqrestore(&musb->lock, flags);
	return retval;
}

void musbhs_dma_controller_destroy(struct dma_controller *c)
{
	struct musb_dma_controller *controller = container_of(c,
			struct musb_dma_controller, controller);

	dma_controller_stop(controller);

	if (controller->irq)
		free_irq(controller->irq, c);

	kfree(controller);
}
EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy);

struct dma_controller *musbhs_dma_controller_create(struct musb *musb,
						    void __iomem *base)
{
	struct musb_dma_controller *controller;
	struct device *dev = musb->controller;
	struct platform_device *pdev = to_platform_device(dev);
	int irq = platform_get_irq_byname(pdev, "dma");

	if (irq <= 0) {
		dev_err(dev, "No DMA interrupt line!\n");
		return NULL;
	}

	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
	if (!controller)
		return NULL;

	controller->channel_count = MUSB_HSDMA_CHANNELS;
	controller->private_data = musb;
	controller->base = base;

	controller->controller.channel_alloc = dma_channel_allocate;
	controller->controller.channel_release = dma_channel_release;
	controller->controller.channel_program = dma_channel_program;
	controller->controller.channel_abort = dma_channel_abort;

	if (request_irq(irq, dma_controller_irq, 0,
			dev_name(musb->controller), &controller->controller)) {
		dev_err(dev, "request_irq %d failed!\n", irq);
		musb_dma_controller_destroy(&controller->controller);

		return NULL;
	}

	controller->irq = irq;

	return &controller->controller;
}
EXPORT_SYMBOL_GPL(musbhs_dma_controller_create);
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
550a7375 FB	2	/*
	3	* MUSB OTG driver - support for Mentor's DMA controller
	4	*
	5	* Copyright 2005 Mentor Graphics Corporation
	6	* Copyright (C) 2005-2007 by Texas Instruments
550a7375 FB	7	*/
	8	#include <linux/device.h>
	9	#include <linux/interrupt.h>
	10	#include <linux/platform_device.h>
5a0e3ad6	11	#include <linux/slab.h>
550a7375	12	#include "musb_core.h"
78fba982 BL	13
	14	#define MUSB_HSDMA_BASE 0x200
	15	#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
	16	#define MUSB_HSDMA_CONTROL 0x4
	17	#define MUSB_HSDMA_ADDRESS 0x8
	18	#define MUSB_HSDMA_COUNT 0xc
	19
	20	#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
	21	(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
	22
	23	#define musb_read_hsdma_addr(mbase, bchannel) \
	24	musb_readl(mbase, \
	25	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
	26
	27	#define musb_write_hsdma_addr(mbase, bchannel, addr) \
	28	musb_writel(mbase, \
	29	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
	30	addr)
	31
	32	#define musb_read_hsdma_count(mbase, bchannel) \
	33	musb_readl(mbase, \
	34	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
	35
	36	#define musb_write_hsdma_count(mbase, bchannel, len) \
	37	musb_writel(mbase, \
	38	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
	39	len)
	40	/* control register (16-bit): */
	41	#define MUSB_HSDMA_ENABLE_SHIFT 0
	42	#define MUSB_HSDMA_TRANSMIT_SHIFT 1
	43	#define MUSB_HSDMA_MODE1_SHIFT 2
	44	#define MUSB_HSDMA_IRQENABLE_SHIFT 3
	45	#define MUSB_HSDMA_ENDPOINT_SHIFT 4
	46	#define MUSB_HSDMA_BUSERROR_SHIFT 8
	47	#define MUSB_HSDMA_BURSTMODE_SHIFT 9
	48	#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
	49	#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
	50	#define MUSB_HSDMA_BURSTMODE_INCR4 1
	51	#define MUSB_HSDMA_BURSTMODE_INCR8 2
	52	#define MUSB_HSDMA_BURSTMODE_INCR16 3
	53
	54	#define MUSB_HSDMA_CHANNELS 8
	55
	56	struct musb_dma_controller;
	57
	58	struct musb_dma_channel {
	59	struct dma_channel channel;
	60	struct musb_dma_controller *controller;
	61	u32 start_addr;
	62	u32 len;
	63	u16 max_packet_sz;
	64	u8 idx;
	65	u8 epnum;
	66	u8 transmit;
	67	};
	68
	69	struct musb_dma_controller {
	70	struct dma_controller controller;
	71	struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
	72	void *private_data;
	73	void __iomem *base;
	74	u8 channel_count;
	75	u8 used_channels;
	76	int irq;
77	};
550a7375	78
458e6a51	79	static void dma_channel_release(struct dma_channel *channel);
550a7375	80
66c01883	81	static void dma_controller_stop(struct musb_dma_controller *controller)
550a7375	82	{
458e6a51 FB	83	struct musb *musb = controller->private_data;
	84	struct dma_channel *channel;
	85	u8 bit;
550a7375	86
458e6a51	87	if (controller->used_channels != 0) {
550a7375 FB	88	dev_err(musb->controller,
	89	"Stopping DMA controller while channel active\n");
	90
458e6a51 FB	91	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
	92	if (controller->used_channels & (1 << bit)) {
	93	channel = &controller->channel[bit].channel;
	94	dma_channel_release(channel);
550a7375	95
458e6a51	96	if (!controller->used_channels)
550a7375 FB	97	break;
	98	}
	99	}
	100	}
550a7375 FB	101	}
	102
	103	static struct dma_channel dma_channel_allocate(struct dma_controller c,
	104	struct musb_hw_ep *hw_ep, u8 transmit)
	105	{
458e6a51 FB	106	struct musb_dma_controller *controller = container_of(c,
	107	struct musb_dma_controller, controller);
	108	struct musb_dma_channel *musb_channel = NULL;
	109	struct dma_channel *channel = NULL;
	110	u8 bit;
	111
	112	for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
	113	if (!(controller->used_channels & (1 << bit))) {
	114	controller->used_channels \|= (1 << bit);
	115	musb_channel = &(controller->channel[bit]);
	116	musb_channel->controller = controller;
	117	musb_channel->idx = bit;
	118	musb_channel->epnum = hw_ep->epnum;
	119	musb_channel->transmit = transmit;
	120	channel = &(musb_channel->channel);
	121	channel->private_data = musb_channel;
	122	channel->status = MUSB_DMA_STATUS_FREE;
6587cc0f	123	channel->max_len = 0x100000;
550a7375	124	/* Tx => mode 1; Rx => mode 0 */
458e6a51 FB	125	channel->desired_mode = transmit;
458e6a51 FB	126	channel->actual_len = 0;
550a7375 FB	127	break;
	128	}
	129	}
458e6a51 FB	130
458e6a51 FB	131	return channel;
550a7375 FB	132	}
550a7375 FB	133
458e6a51	134	static void dma_channel_release(struct dma_channel *channel)
550a7375	135	{
458e6a51	136	struct musb_dma_channel *musb_channel = channel->private_data;
550a7375	137
458e6a51 FB	138	channel->actual_len = 0;
	139	musb_channel->start_addr = 0;
	140	musb_channel->len = 0;
550a7375	141
458e6a51 FB	142	musb_channel->controller->used_channels &=
458e6a51 FB	143	~(1 << musb_channel->idx);
550a7375	144
458e6a51	145	channel->status = MUSB_DMA_STATUS_UNKNOWN;
550a7375 FB	146	}
550a7375 FB	147
458e6a51	148	static void configure_channel(struct dma_channel *channel,
550a7375 FB	149	u16 packet_sz, u8 mode,
	150	dma_addr_t dma_addr, u32 len)
	151	{
458e6a51 FB	152	struct musb_dma_channel *musb_channel = channel->private_data;
458e6a51 FB	153	struct musb_dma_controller *controller = musb_channel->controller;
5c8a86e1	154	struct musb *musb = controller->private_data;
458e6a51 FB	155	void __iomem *mbase = controller->base;
458e6a51 FB	156	u8 bchannel = musb_channel->idx;
550a7375 FB	157	u16 csr = 0;
550a7375 FB	158
b99d3659	159	musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d",
3ec08ddf	160	channel, packet_sz, &dma_addr, len, mode);
550a7375 FB	161
	162	if (mode) {
	163	csr \|= 1 << MUSB_HSDMA_MODE1_SHIFT;
	164	BUG_ON(len < packet_sz);
550a7375	165	}
c0f1f8e3 HH	166	csr \|= MUSB_HSDMA_BURSTMODE_INCR16
c0f1f8e3 HH	167	<< MUSB_HSDMA_BURSTMODE_SHIFT;
550a7375	168
458e6a51	169	csr \|= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
550a7375 FB	170	\| (1 << MUSB_HSDMA_ENABLE_SHIFT)
550a7375 FB	171	\| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
458e6a51	172	\| (musb_channel->transmit
550a7375 FB	173	? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
	174	: 0);
	175
	176	/* address/count */
6995eb68 BW	177	musb_write_hsdma_addr(mbase, bchannel, dma_addr);
6995eb68 BW	178	musb_write_hsdma_count(mbase, bchannel, len);
550a7375 FB	179
	180	/* control (this should start things) */
	181	musb_writew(mbase,
458e6a51	182	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
550a7375 FB	183	csr);
	184	}
	185
458e6a51	186	static int dma_channel_program(struct dma_channel *channel,
550a7375 FB	187	u16 packet_sz, u8 mode,
	188	dma_addr_t dma_addr, u32 len)
	189	{
458e6a51	190	struct musb_dma_channel *musb_channel = channel->private_data;
6e16edfe AG	191	struct musb_dma_controller *controller = musb_channel->controller;
6e16edfe AG	192	struct musb *musb = controller->private_data;
550a7375	193
b99d3659	194	musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d",
458e6a51 FB	195	musb_channel->epnum,
458e6a51 FB	196	musb_channel->transmit ? "Tx" : "Rx",
3ec08ddf	197	packet_sz, &dma_addr, len, mode);
550a7375	198
458e6a51 FB	199	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN \|\|
458e6a51 FB	200	channel->status == MUSB_DMA_STATUS_BUSY);
550a7375	201
6e16edfe AG	202	/*
	203	* The DMA engine in RTL1.8 and above cannot handle
	204	* DMA addresses that are not aligned to a 4 byte boundary.
	205	* It ends up masking the last two bits of the address
	206	* programmed in DMA_ADDR.
	207	*
	208	* Fail such DMA transfers, so that the backup PIO mode
	209	* can carry out the transfer
	210	*/
	211	if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
	212	return false;
	213
458e6a51 FB	214	channel->actual_len = 0;
	215	musb_channel->start_addr = dma_addr;
	216	musb_channel->len = len;
	217	musb_channel->max_packet_sz = packet_sz;
	218	channel->status = MUSB_DMA_STATUS_BUSY;
550a7375	219
8ca47c8a	220	configure_channel(channel, packet_sz, mode, dma_addr, len);
550a7375 FB	221
	222	return true;
	223	}
	224
458e6a51	225	static int dma_channel_abort(struct dma_channel *channel)
550a7375	226	{
458e6a51 FB	227	struct musb_dma_channel *musb_channel = channel->private_data;
458e6a51 FB	228	void __iomem *mbase = musb_channel->controller->base;
d026e9c7	229	struct musb *musb = musb_channel->controller->private_data;
458e6a51 FB	230
458e6a51 FB	231	u8 bchannel = musb_channel->idx;
b6e434a5	232	int offset;
550a7375 FB	233	u16 csr;
550a7375 FB	234
458e6a51 FB	235	if (channel->status == MUSB_DMA_STATUS_BUSY) {
458e6a51 FB	236	if (musb_channel->transmit) {
d026e9c7	237	offset = musb->io.ep_offset(musb_channel->epnum,
b6e434a5 SS	238	MUSB_TXCSR);
	239
	240	/*
	241	* The programming guide says that we must clear
	242	* the DMAENAB bit before the DMAMODE bit...
	243	*/
	244	csr = musb_readw(mbase, offset);
	245	csr &= ~(MUSB_TXCSR_AUTOSET \| MUSB_TXCSR_DMAENAB);
	246	musb_writew(mbase, offset, csr);
	247	csr &= ~MUSB_TXCSR_DMAMODE;
	248	musb_writew(mbase, offset, csr);
550a7375	249	} else {
d026e9c7	250	offset = musb->io.ep_offset(musb_channel->epnum,
b6e434a5 SS	251	MUSB_RXCSR);
	252
	253	csr = musb_readw(mbase, offset);
550a7375 FB	254	csr &= ~(MUSB_RXCSR_AUTOCLEAR \|
	255	MUSB_RXCSR_DMAENAB \|
	256	MUSB_RXCSR_DMAMODE);
b6e434a5	257	musb_writew(mbase, offset, csr);
550a7375 FB	258	}
	259
	260	musb_writew(mbase,
458e6a51	261	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
550a7375	262	0);
6995eb68 BW	263	musb_write_hsdma_addr(mbase, bchannel, 0);
6995eb68 BW	264	musb_write_hsdma_count(mbase, bchannel, 0);
458e6a51	265	channel->status = MUSB_DMA_STATUS_FREE;
550a7375	266	}
458e6a51	267
550a7375 FB	268	return 0;
	269	}
	270
	271	static irqreturn_t dma_controller_irq(int irq, void *private_data)
	272	{
458e6a51 FB	273	struct musb_dma_controller *controller = private_data;
	274	struct musb *musb = controller->private_data;
	275	struct musb_dma_channel *musb_channel;
	276	struct dma_channel *channel;
	277
	278	void __iomem *mbase = controller->base;
	279
550a7375	280	irqreturn_t retval = IRQ_NONE;
458e6a51	281
550a7375 FB	282	unsigned long flags;
550a7375 FB	283
458e6a51 FB	284	u8 bchannel;
	285	u8 int_hsdma;
	286
f933a0c0	287	u32 addr, count;
458e6a51 FB	288	u16 csr;
458e6a51 FB	289
550a7375 FB	290	spin_lock_irqsave(&musb->lock, flags);
	291
	292	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
550a7375	293
f933a0c0	294	if (!int_hsdma) {
b99d3659	295	musb_dbg(musb, "spurious DMA irq");
f933a0c0 AG	296
	297	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
	298	musb_channel = (struct musb_dma_channel *)
	299	&(controller->channel[bchannel]);
	300	channel = &musb_channel->channel;
	301	if (channel->status == MUSB_DMA_STATUS_BUSY) {
	302	count = musb_read_hsdma_count(mbase, bchannel);
	303
	304	if (count == 0)
	305	int_hsdma \|= (1 << bchannel);
	306	}
	307	}
	308
b99d3659	309	musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma);
f933a0c0 AG	310
	311	if (!int_hsdma)
	312	goto done;
	313	}
	314
458e6a51 FB	315	for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
	316	if (int_hsdma & (1 << bchannel)) {
	317	musb_channel = (struct musb_dma_channel *)
	318	&(controller->channel[bchannel]);
	319	channel = &musb_channel->channel;
550a7375 FB	320
550a7375 FB	321	csr = musb_readw(mbase,
458e6a51	322	MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
550a7375 FB	323	MUSB_HSDMA_CONTROL));
550a7375 FB	324
458e6a51 FB	325	if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
458e6a51 FB	326	musb_channel->channel.status =
550a7375	327	MUSB_DMA_STATUS_BUS_ABORT;
458e6a51	328	} else {
550a7375 FB	329	u8 devctl;
550a7375 FB	330
6995eb68 BW	331	addr = musb_read_hsdma_addr(mbase,
6995eb68 BW	332	bchannel);
458e6a51 FB	333	channel->actual_len = addr
458e6a51 FB	334	- musb_channel->start_addr;
550a7375	335
b99d3659	336	musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s",
458e6a51 FB	337	channel, musb_channel->start_addr,
	338	addr, channel->actual_len,
	339	musb_channel->len,
	340	(channel->actual_len
	341	< musb_channel->len) ?
550a7375 FB	342	"=> reconfig 0" : "=> complete");
	343
	344	devctl = musb_readb(mbase, MUSB_DEVCTL);
	345
458e6a51	346	channel->status = MUSB_DMA_STATUS_FREE;
550a7375 FB	347
550a7375 FB	348	/* completed */
c418fd6c PE	349	if (musb_channel->transmit &&
	350	(!channel->desired_mode \|\|
	351	(channel->actual_len %
	352	musb_channel->max_packet_sz))) {
b6e434a5	353	u8 epnum = musb_channel->epnum;
d026e9c7	354	int offset = musb->io.ep_offset(epnum,
b6e434a5 SS	355	MUSB_TXCSR);
	356	u16 txcsr;
	357
	358	/*
	359	* The programming guide says that we
	360	* must clear DMAENAB before DMAMODE.
	361	*/
	362	musb_ep_select(mbase, epnum);
	363	txcsr = musb_readw(mbase, offset);
c418fd6c PE	364	if (channel->desired_mode == 1) {
c418fd6c PE	365	txcsr &= ~(MUSB_TXCSR_DMAENAB
b6e434a5	366	\| MUSB_TXCSR_AUTOSET);
c418fd6c PE	367	musb_writew(mbase, offset, txcsr);
	368	/* Send out the packet */
	369	txcsr &= ~MUSB_TXCSR_DMAMODE;
	370	txcsr \|= MUSB_TXCSR_DMAENAB;
	371	}
b6e434a5 SS	372	txcsr \|= MUSB_TXCSR_TXPKTRDY;
b6e434a5 SS	373	musb_writew(mbase, offset, txcsr);
458e6a51	374	}
c7bbc056 SS	375	musb_dma_completion(musb, musb_channel->epnum,
c7bbc056 SS	376	musb_channel->transmit);
550a7375 FB	377	}
	378	}
	379	}
6995eb68	380
550a7375 FB	381	retval = IRQ_HANDLED;
	382	done:
	383	spin_unlock_irqrestore(&musb->lock, flags);
	384	return retval;
	385	}
	386
7f6283ed	387	void musbhs_dma_controller_destroy(struct dma_controller *c)
550a7375	388	{
458e6a51 FB	389	struct musb_dma_controller *controller = container_of(c,
458e6a51 FB	390	struct musb_dma_controller, controller);
550a7375	391
66c01883 SAS	392	dma_controller_stop(controller);
66c01883 SAS	393
550a7375 FB	394	if (controller->irq)
	395	free_irq(controller->irq, c);
	396
	397	kfree(controller);
	398	}
7f6283ed	399	EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy);
550a7375	400
7f6283ed TL	401	struct dma_controller musbhs_dma_controller_create(struct musb musb,
7f6283ed TL	402	void __iomem *base)
550a7375 FB	403	{
	404	struct musb_dma_controller *controller;
	405	struct device *dev = musb->controller;
	406	struct platform_device *pdev = to_platform_device(dev);
fcf173e4	407	int irq = platform_get_irq_byname(pdev, "dma");
550a7375	408
7effdbd6	409	if (irq <= 0) {
550a7375 FB	410	dev_err(dev, "No DMA interrupt line!\n");
	411	return NULL;
	412	}
	413
458e6a51	414	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
550a7375 FB	415	if (!controller)
	416	return NULL;
	417
458e6a51 FB	418	controller->channel_count = MUSB_HSDMA_CHANNELS;
	419	controller->private_data = musb;
	420	controller->base = base;
550a7375	421
458e6a51 FB	422	controller->controller.channel_alloc = dma_channel_allocate;
	423	controller->controller.channel_release = dma_channel_release;
	424	controller->controller.channel_program = dma_channel_program;
	425	controller->controller.channel_abort = dma_channel_abort;
550a7375	426
b5dd18d8	427	if (request_irq(irq, dma_controller_irq, 0,
427c4f33	428	dev_name(musb->controller), &controller->controller)) {
550a7375	429	dev_err(dev, "request_irq %d failed!\n", irq);
7f6283ed	430	musb_dma_controller_destroy(&controller->controller);
458e6a51	431
550a7375 FB	432	return NULL;
	433	}
	434
	435	controller->irq = irq;
	436
458e6a51	437	return &controller->controller;
550a7375	438	}
7f6283ed	439	EXPORT_SYMBOL_GPL(musbhs_dma_controller_create);