[mirror_ubuntu-bionic-kernel.git] / drivers / usb / musb / musbhsdma.h

/*
 * MUSB OTG driver - support for Mentor's DMA controller
 *
 * Copyright 2005 Mentor Graphics Corporation
 * Copyright (C) 2005-2007 by Texas Instruments
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#ifndef CONFIG_BLACKFIN

#define MUSB_HSDMA_BASE		0x200
#define MUSB_HSDMA_INTR		(MUSB_HSDMA_BASE + 0)
#define MUSB_HSDMA_CONTROL		0x4
#define MUSB_HSDMA_ADDRESS		0x8
#define MUSB_HSDMA_COUNT		0xc

#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)		\
		(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)

#define musb_read_hsdma_addr(mbase, bchannel)	\
	musb_readl(mbase,	\
		   MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))

#define musb_write_hsdma_addr(mbase, bchannel, addr) \
	musb_writel(mbase, \
		    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
		    addr)

#define musb_read_hsdma_count(mbase, bchannel)	\
	musb_readl(mbase,	\
		   MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))

#define musb_write_hsdma_count(mbase, bchannel, len) \
	musb_writel(mbase, \
		    MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
		    len)
#else

#define MUSB_HSDMA_BASE		0x400
#define MUSB_HSDMA_INTR		(MUSB_HSDMA_BASE + 0)
#define MUSB_HSDMA_CONTROL		0x04
#define MUSB_HSDMA_ADDR_LOW		0x08
#define MUSB_HSDMA_ADDR_HIGH		0x0C
#define MUSB_HSDMA_COUNT_LOW		0x10
#define MUSB_HSDMA_COUNT_HIGH		0x14

#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset)		\
		(MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)

static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
{
	u32 addr = musb_readw(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));

	addr = addr << 16;

	addr |= musb_readw(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));

	return addr;
}

static inline void musb_write_hsdma_addr(void __iomem *mbase,
				u8 bchannel, dma_addr_t dma_addr)
{
	musb_writew(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
		dma_addr);
	musb_writew(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
		(dma_addr >> 16));
}

static inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel)
{
	u32 count = musb_readw(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH));

	count = count << 16;

	count |= musb_readw(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW));

	return count;
}

static inline void musb_write_hsdma_count(void __iomem *mbase,
				u8 bchannel, u32 len)
{
	musb_writew(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),len);
	musb_writew(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
		(len >> 16));
}

#endif /* CONFIG_BLACKFIN */

/* control register (16-bit): */
#define MUSB_HSDMA_ENABLE_SHIFT		0
#define MUSB_HSDMA_TRANSMIT_SHIFT	1
#define MUSB_HSDMA_MODE1_SHIFT		2
#define MUSB_HSDMA_IRQENABLE_SHIFT	3
#define MUSB_HSDMA_ENDPOINT_SHIFT	4
#define MUSB_HSDMA_BUSERROR_SHIFT	8
#define MUSB_HSDMA_BURSTMODE_SHIFT	9
#define MUSB_HSDMA_BURSTMODE		(3 << MUSB_HSDMA_BURSTMODE_SHIFT)
#define MUSB_HSDMA_BURSTMODE_UNSPEC	0
#define MUSB_HSDMA_BURSTMODE_INCR4	1
#define MUSB_HSDMA_BURSTMODE_INCR8	2
#define MUSB_HSDMA_BURSTMODE_INCR16	3

#define MUSB_HSDMA_CHANNELS		8

struct musb_dma_controller;

struct musb_dma_channel {
	struct dma_channel		channel;
	struct musb_dma_controller	*controller;
	u32				start_addr;
	u32				len;
	u16				max_packet_sz;
	u8				idx;
	u8				epnum;
	u8				transmit;
};

struct musb_dma_controller {
	struct dma_controller		controller;
	struct musb_dma_channel		channel[MUSB_HSDMA_CHANNELS];
	void				*private_data;
	void __iomem			*base;
	u8				channel_count;
	u8				used_channels;
	u8				irq;
};
Commit	Line	Data
6995eb68 BW	1	/*
	2	* MUSB OTG driver - support for Mentor's DMA controller
	3	*
	4	* Copyright 2005 Mentor Graphics Corporation
	5	* Copyright (C) 2005-2007 by Texas Instruments
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	19	* 02110-1301 USA
	20	*
	21	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
	22	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	23	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	24	* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	25	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	26	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	27	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	28	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	30	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*
	32	*/
	33
6995eb68 BW	34	#ifndef CONFIG_BLACKFIN
	35
	36	#define MUSB_HSDMA_BASE 0x200
	37	#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
	38	#define MUSB_HSDMA_CONTROL 0x4
	39	#define MUSB_HSDMA_ADDRESS 0x8
	40	#define MUSB_HSDMA_COUNT 0xc
	41
	42	#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
	43	(MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
	44
	45	#define musb_read_hsdma_addr(mbase, bchannel) \
	46	musb_readl(mbase, \
	47	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
	48
	49	#define musb_write_hsdma_addr(mbase, bchannel, addr) \
	50	musb_writel(mbase, \
	51	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
	52	addr)
	53
452f0394 AG	54	#define musb_read_hsdma_count(mbase, bchannel) \
	55	musb_readl(mbase, \
	56	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
	57
6995eb68 BW	58	#define musb_write_hsdma_count(mbase, bchannel, len) \
	59	musb_writel(mbase, \
	60	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
	61	len)
	62	#else
	63
	64	#define MUSB_HSDMA_BASE 0x400
	65	#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
	66	#define MUSB_HSDMA_CONTROL 0x04
	67	#define MUSB_HSDMA_ADDR_LOW 0x08
	68	#define MUSB_HSDMA_ADDR_HIGH 0x0C
	69	#define MUSB_HSDMA_COUNT_LOW 0x10
	70	#define MUSB_HSDMA_COUNT_HIGH 0x14
	71
	72	#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
	73	(MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)
	74
	75	static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
	76	{
	77	u32 addr = musb_readw(mbase,
	78	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));
	79
	80	addr = addr << 16;
	81
	82	addr \|= musb_readw(mbase,
	83	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));
	84
	85	return addr;
	86	}
	87
	88	static inline void musb_write_hsdma_addr(void __iomem *mbase,
	89	u8 bchannel, dma_addr_t dma_addr)
	90	{
	91	musb_writew(mbase,
	92	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
9c668079	93	dma_addr);
6995eb68 BW	94	musb_writew(mbase,
6995eb68 BW	95	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
9c668079	96	(dma_addr >> 16));
6995eb68 BW	97	}
6995eb68 BW	98
452f0394 AG	99	static inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel)
452f0394 AG	100	{
9c668079	101	u32 count = musb_readw(mbase,
452f0394	102	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH));
9c668079 BL	103
	104	count = count << 16;
	105
	106	count \|= musb_readw(mbase,
	107	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW));
	108
	109	return count;
452f0394 AG	110	}
452f0394 AG	111
6995eb68 BW	112	static inline void musb_write_hsdma_count(void __iomem *mbase,
	113	u8 bchannel, u32 len)
	114	{
9c668079 BL	115	musb_writew(mbase,
	116	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),len);
	117	musb_writew(mbase,
6995eb68	118	MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
9c668079	119	(len >> 16));
6995eb68 BW	120	}
	121
	122	#endif /* CONFIG_BLACKFIN */
	123
	124	/* control register (16-bit): */
	125	#define MUSB_HSDMA_ENABLE_SHIFT 0
	126	#define MUSB_HSDMA_TRANSMIT_SHIFT 1
	127	#define MUSB_HSDMA_MODE1_SHIFT 2
	128	#define MUSB_HSDMA_IRQENABLE_SHIFT 3
	129	#define MUSB_HSDMA_ENDPOINT_SHIFT 4
	130	#define MUSB_HSDMA_BUSERROR_SHIFT 8
	131	#define MUSB_HSDMA_BURSTMODE_SHIFT 9
	132	#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
	133	#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
	134	#define MUSB_HSDMA_BURSTMODE_INCR4 1
	135	#define MUSB_HSDMA_BURSTMODE_INCR8 2
	136	#define MUSB_HSDMA_BURSTMODE_INCR16 3
	137
	138	#define MUSB_HSDMA_CHANNELS 8
	139
	140	struct musb_dma_controller;
	141
	142	struct musb_dma_channel {
	143	struct dma_channel channel;
	144	struct musb_dma_controller *controller;
	145	u32 start_addr;
	146	u32 len;
	147	u16 max_packet_sz;
	148	u8 idx;
	149	u8 epnum;
	150	u8 transmit;
	151	};
	152
	153	struct musb_dma_controller {
	154	struct dma_controller controller;
	155	struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
	156	void *private_data;
	157	void __iomem *base;
	158	u8 channel_count;
	159	u8 used_channels;
	160	u8 irq;
	161	};