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usb: musb: sunxi: Add support for the Allwinner sunxi musb controller
[mirror_ubuntu-focal-kernel.git] / drivers / usb / musb / sunxi.c
CommitLineData
744543c5
HG		 1/*
2 * Allwinner sun4i MUSB Glue Layer
3 *
4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
5 *
6 * Based on code from
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/extcon.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/phy/phy-sun4i-usb.h>
28#include <linux/platform_device.h>
29#include <linux/soc/sunxi/sunxi_sram.h>
30#include <linux/usb/musb.h>
31#include <linux/usb/of.h>
32#include <linux/usb/usb_phy_generic.h>
33#include <linux/workqueue.h>
34#include "musb_core.h"
35
36/*
37 * Register offsets, note sunxi musb has a different layout then most
38 * musb implementations, we translate the layout in musb_readb & friends.
39 */
40#define SUNXI_MUSB_POWER 0x0040
41#define SUNXI_MUSB_DEVCTL 0x0041
42#define SUNXI_MUSB_INDEX 0x0042
43#define SUNXI_MUSB_VEND0 0x0043
44#define SUNXI_MUSB_INTRTX 0x0044
45#define SUNXI_MUSB_INTRRX 0x0046
46#define SUNXI_MUSB_INTRTXE 0x0048
47#define SUNXI_MUSB_INTRRXE 0x004a
48#define SUNXI_MUSB_INTRUSB 0x004c
49#define SUNXI_MUSB_INTRUSBE 0x0050
50#define SUNXI_MUSB_FRAME 0x0054
51#define SUNXI_MUSB_TXFIFOSZ 0x0090
52#define SUNXI_MUSB_TXFIFOADD 0x0092
53#define SUNXI_MUSB_RXFIFOSZ 0x0094
54#define SUNXI_MUSB_RXFIFOADD 0x0096
55#define SUNXI_MUSB_FADDR 0x0098
56#define SUNXI_MUSB_TXFUNCADDR 0x0098
57#define SUNXI_MUSB_TXHUBADDR 0x009a
58#define SUNXI_MUSB_TXHUBPORT 0x009b
59#define SUNXI_MUSB_RXFUNCADDR 0x009c
60#define SUNXI_MUSB_RXHUBADDR 0x009e
61#define SUNXI_MUSB_RXHUBPORT 0x009f
62#define SUNXI_MUSB_CONFIGDATA 0x00c0
63
64/* VEND0 bits */
65#define SUNXI_MUSB_VEND0_PIO_MODE 0
66
67/* flags */
68#define SUNXI_MUSB_FL_ENABLED 0
69#define SUNXI_MUSB_FL_HOSTMODE 1
70#define SUNXI_MUSB_FL_HOSTMODE_PEND 2
71#define SUNXI_MUSB_FL_VBUS_ON 3
72#define SUNXI_MUSB_FL_PHY_ON 4
73
74/* Our read/write methods need access and do not get passed in a musb ref :| */
75static struct musb *sunxi_musb;
76
77struct sunxi_glue {
78 struct device *dev;
79 struct platform_device *musb;
80 struct clk *clk;
81 struct phy *phy;
82 struct platform_device *usb_phy;
83 struct usb_phy *xceiv;
84 unsigned long flags;
85 struct work_struct work;
86 struct extcon_dev *extcon;
87 struct notifier_block host_nb;
88};
89
90/* phy_power_on / off may sleep, so we use a workqueue */
91static void sunxi_musb_work(struct work_struct *work)
92{
93 struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work);
94 bool vbus_on, phy_on;
95
96 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
97 return;
98
99 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) {
100 struct musb *musb = platform_get_drvdata(glue->musb);
101 unsigned long flags;
102 u8 devctl;
103
104 spin_lock_irqsave(&musb->lock, flags);
105
106 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL);
107 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) {
108 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
109 musb->xceiv->otg->default_a = 1;
110 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
111 MUSB_HST_MODE(musb);
112 devctl |= MUSB_DEVCTL_SESSION;
113 } else {
114 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
115 musb->xceiv->otg->default_a = 0;
116 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
117 MUSB_DEV_MODE(musb);
118 devctl &= ~MUSB_DEVCTL_SESSION;
119 }
120 writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL);
121
122 spin_unlock_irqrestore(&musb->lock, flags);
123 }
124
125 vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
126 phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
127
128 if (phy_on != vbus_on) {
129 if (vbus_on) {
130 phy_power_on(glue->phy);
131 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
132 } else {
133 phy_power_off(glue->phy);
134 clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
135 }
136 }
137}
138
139static void sunxi_musb_set_vbus(struct musb *musb, int is_on)
140{
141 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
142
143 if (is_on)
144 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
145 else
146 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
147
148 schedule_work(&glue->work);
149}
150
151static void sunxi_musb_pre_root_reset_end(struct musb *musb)
152{
153 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
154
155 sun4i_usb_phy_set_squelch_detect(glue->phy, false);
156}
157
158static void sunxi_musb_post_root_reset_end(struct musb *musb)
159{
160 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
161
162 sun4i_usb_phy_set_squelch_detect(glue->phy, true);
163}
164
165static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
166{
167 struct musb *musb = __hci;
168 unsigned long flags;
169
170 spin_lock_irqsave(&musb->lock, flags);
171
172 musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB);
173 if (musb->int_usb)
174 writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
175
176 /*
177 * sunxi musb often signals babble on low / full speed device
178 * disconnect, without ever raising MUSB_INTR_DISCONNECT, since
179 * normally babble never happens treat it as disconnect.
180 */
181 if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) {
182 musb->int_usb &= ~MUSB_INTR_BABBLE;
183 musb->int_usb |= MUSB_INTR_DISCONNECT;
184 }
185
186 if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
187 /* ep0 FADDR must be 0 when (re)entering peripheral mode */
188 musb_ep_select(musb->mregs, 0);
189 musb_writeb(musb->mregs, MUSB_FADDR, 0);
190 }
191
192 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX);
193 if (musb->int_tx)
194 writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX);
195
196 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX);
197 if (musb->int_rx)
198 writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX);
199
200 musb_interrupt(musb);
201
202 spin_unlock_irqrestore(&musb->lock, flags);
203
204 return IRQ_HANDLED;
205}
206
207static int sunxi_musb_host_notifier(struct notifier_block *nb,
208 unsigned long event, void *ptr)
209{
210 struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb);
211
212 if (event)
213 set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
214 else
215 clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
216
217 set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags);
218 schedule_work(&glue->work);
219
220 return NOTIFY_DONE;
221}
222
223static int sunxi_musb_init(struct musb *musb)
224{
225 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
226 int ret;
227
228 sunxi_musb = musb;
229 musb->phy = glue->phy;
230 musb->xceiv = glue->xceiv;
231
232 ret = sunxi_sram_claim(musb->controller->parent);
233 if (ret)
234 return ret;
235
236 ret = clk_prepare_enable(glue->clk);
237 if (ret)
238 goto error_sram_release;
239
240 writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0);
241
242 /* Register notifier before calling phy_init() */
243 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE) {
244 ret = extcon_register_notifier(glue->extcon, EXTCON_USB_HOST,
245 &glue->host_nb);
246 if (ret)
247 goto error_clk_disable;
248 }
249
250 ret = phy_init(glue->phy);
251 if (ret)
252 goto error_unregister_notifier;
253
254 if (musb->port_mode == MUSB_PORT_MODE_HOST) {
255 ret = phy_power_on(glue->phy);
256 if (ret)
257 goto error_phy_exit;
258 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
259 /* Stop musb work from turning vbus off again */
260 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
261 }
262
263 musb->isr = sunxi_musb_interrupt;
264
265 /* Stop the musb-core from doing runtime pm (not supported on sunxi) */
266 pm_runtime_get(musb->controller);
267
268 return 0;
269
270error_phy_exit:
271 phy_exit(glue->phy);
272error_unregister_notifier:
273 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
274 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST,
275 &glue->host_nb);
276error_clk_disable:
277 clk_disable_unprepare(glue->clk);
278error_sram_release:
279 sunxi_sram_release(musb->controller->parent);
280 return ret;
281}
282
283static int sunxi_musb_exit(struct musb *musb)
284{
285 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
286
287 pm_runtime_put(musb->controller);
288
289 cancel_work_sync(&glue->work);
290 if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags))
291 phy_power_off(glue->phy);
292
293 phy_exit(glue->phy);
294
295 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
296 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST,
297 &glue->host_nb);
298
299 clk_disable_unprepare(glue->clk);
300 sunxi_sram_release(musb->controller->parent);
301
302 return 0;
303}
304
305static void sunxi_musb_enable(struct musb *musb)
306{
307 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
308
309 /* musb_core does not call us in a balanced manner */
310 if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
311 return;
312
313 schedule_work(&glue->work);
314}
315
316static void sunxi_musb_disable(struct musb *musb)
317{
318 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
319
320 clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags);
321}
322
323/*
324 * sunxi musb register layout
325 * 0x00 - 0x17 fifo regs, 1 long per fifo
326 * 0x40 - 0x57 generic control regs (power - frame)
327 * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed)
328 * 0x90 - 0x97 fifo control regs (indexed)
329 * 0x98 - 0x9f multipoint / busctl regs (indexed)
330 * 0xc0 configdata reg
331 */
332
333static u32 sunxi_musb_fifo_offset(u8 epnum)
334{
335 return (epnum * 4);
336}
337
338static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset)
339{
340 WARN_ONCE(offset != 0,
341 "sunxi_musb_ep_offset called with non 0 offset\n");
342
343 return 0x80; /* indexed, so ignore epnum */
344}
345
346static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset)
347{
348 return SUNXI_MUSB_TXFUNCADDR + offset;
349}
350
351static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset)
352{
353 if (addr == sunxi_musb->mregs) {
354 /* generic control or fifo control reg access */
355 switch (offset) {
356 case MUSB_FADDR:
357 return readb(addr + SUNXI_MUSB_FADDR);
358 case MUSB_POWER:
359 return readb(addr + SUNXI_MUSB_POWER);
360 case MUSB_INTRUSB:
361 return readb(addr + SUNXI_MUSB_INTRUSB);
362 case MUSB_INTRUSBE:
363 return readb(addr + SUNXI_MUSB_INTRUSBE);
364 case MUSB_INDEX:
365 return readb(addr + SUNXI_MUSB_INDEX);
366 case MUSB_TESTMODE:
367 return 0; /* No testmode on sunxi */
368 case MUSB_DEVCTL:
369 return readb(addr + SUNXI_MUSB_DEVCTL);
370 case MUSB_TXFIFOSZ:
371 return readb(addr + SUNXI_MUSB_TXFIFOSZ);
372 case MUSB_RXFIFOSZ:
373 return readb(addr + SUNXI_MUSB_RXFIFOSZ);
374 case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */
375 return readb(addr + SUNXI_MUSB_CONFIGDATA);
376 /* Offset for these is fixed by sunxi_musb_busctl_offset() */
377 case SUNXI_MUSB_TXFUNCADDR:
378 case SUNXI_MUSB_TXHUBADDR:
379 case SUNXI_MUSB_TXHUBPORT:
380 case SUNXI_MUSB_RXFUNCADDR:
381 case SUNXI_MUSB_RXHUBADDR:
382 case SUNXI_MUSB_RXHUBPORT:
383 /* multipoint / busctl reg access */
384 return readb(addr + offset);
385 default:
386 dev_err(sunxi_musb->controller->parent,
387 "Error unknown readb offset %u\n", offset);
388 return 0;
389 }
390 } else if (addr == (sunxi_musb->mregs + 0x80)) {
391 /* ep control reg access */
392 /* sunxi has a 2 byte hole before the txtype register */
393 if (offset >= MUSB_TXTYPE)
394 offset += 2;
395 return readb(addr + offset);
396 }
397
398 dev_err(sunxi_musb->controller->parent,
399 "Error unknown readb at 0x%x bytes offset\n",
400 (int)(addr - sunxi_musb->mregs));
401 return 0;
402}
403
404static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
405{
406 if (addr == sunxi_musb->mregs) {
407 /* generic control or fifo control reg access */
408 switch (offset) {
409 case MUSB_FADDR:
410 return writeb(data, addr + SUNXI_MUSB_FADDR);
411 case MUSB_POWER:
412 return writeb(data, addr + SUNXI_MUSB_POWER);
413 case MUSB_INTRUSB:
414 return writeb(data, addr + SUNXI_MUSB_INTRUSB);
415 case MUSB_INTRUSBE:
416 return writeb(data, addr + SUNXI_MUSB_INTRUSBE);
417 case MUSB_INDEX:
418 return writeb(data, addr + SUNXI_MUSB_INDEX);
419 case MUSB_TESTMODE:
420 if (data)
421 dev_warn(sunxi_musb->controller->parent,
422 "sunxi-musb does not have testmode\n");
423 return;
424 case MUSB_DEVCTL:
425 return writeb(data, addr + SUNXI_MUSB_DEVCTL);
426 case MUSB_TXFIFOSZ:
427 return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ);
428 case MUSB_RXFIFOSZ:
429 return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ);
430 /* Offset for these is fixed by sunxi_musb_busctl_offset() */
431 case SUNXI_MUSB_TXFUNCADDR:
432 case SUNXI_MUSB_TXHUBADDR:
433 case SUNXI_MUSB_TXHUBPORT:
434 case SUNXI_MUSB_RXFUNCADDR:
435 case SUNXI_MUSB_RXHUBADDR:
436 case SUNXI_MUSB_RXHUBPORT:
437 /* multipoint / busctl reg access */
438 return writeb(data, addr + offset);
439 default:
440 dev_err(sunxi_musb->controller->parent,
441 "Error unknown writeb offset %u\n", offset);
442 return;
443 }
444 } else if (addr == (sunxi_musb->mregs + 0x80)) {
445 /* ep control reg access */
446 if (offset >= MUSB_TXTYPE)
447 offset += 2;
448 return writeb(data, addr + offset);
449 }
450
451 dev_err(sunxi_musb->controller->parent,
452 "Error unknown writeb at 0x%x bytes offset\n",
453 (int)(addr - sunxi_musb->mregs));
454}
455
456static u16 sunxi_musb_readw(const void __iomem *addr, unsigned offset)
457{
458 if (addr == sunxi_musb->mregs) {
459 /* generic control or fifo control reg access */
460 switch (offset) {
461 case MUSB_INTRTX:
462 return readw(addr + SUNXI_MUSB_INTRTX);
463 case MUSB_INTRRX:
464 return readw(addr + SUNXI_MUSB_INTRRX);
465 case MUSB_INTRTXE:
466 return readw(addr + SUNXI_MUSB_INTRTXE);
467 case MUSB_INTRRXE:
468 return readw(addr + SUNXI_MUSB_INTRRXE);
469 case MUSB_FRAME:
470 return readw(addr + SUNXI_MUSB_FRAME);
471 case MUSB_TXFIFOADD:
472 return readw(addr + SUNXI_MUSB_TXFIFOADD);
473 case MUSB_RXFIFOADD:
474 return readw(addr + SUNXI_MUSB_RXFIFOADD);
475 case MUSB_HWVERS:
476 return 0; /* sunxi musb version is not known */
477 default:
478 dev_err(sunxi_musb->controller->parent,
479 "Error unknown readw offset %u\n", offset);
480 return 0;
481 }
482 } else if (addr == (sunxi_musb->mregs + 0x80)) {
483 /* ep control reg access */
484 return readw(addr + offset);
485 }
486
487 dev_err(sunxi_musb->controller->parent,
488 "Error unknown readw at 0x%x bytes offset\n",
489 (int)(addr - sunxi_musb->mregs));
490 return 0;
491}
492
493static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data)
494{
495 if (addr == sunxi_musb->mregs) {
496 /* generic control or fifo control reg access */
497 switch (offset) {
498 case MUSB_INTRTX:
499 return writew(data, addr + SUNXI_MUSB_INTRTX);
500 case MUSB_INTRRX:
501 return writew(data, addr + SUNXI_MUSB_INTRRX);
502 case MUSB_INTRTXE:
503 return writew(data, addr + SUNXI_MUSB_INTRTXE);
504 case MUSB_INTRRXE:
505 return writew(data, addr + SUNXI_MUSB_INTRRXE);
506 case MUSB_FRAME:
507 return writew(data, addr + SUNXI_MUSB_FRAME);
508 case MUSB_TXFIFOADD:
509 return writew(data, addr + SUNXI_MUSB_TXFIFOADD);
510 case MUSB_RXFIFOADD:
511 return writew(data, addr + SUNXI_MUSB_RXFIFOADD);
512 default:
513 dev_err(sunxi_musb->controller->parent,
514 "Error unknown writew offset %u\n", offset);
515 return;
516 }
517 } else if (addr == (sunxi_musb->mregs + 0x80)) {
518 /* ep control reg access */
519 return writew(data, addr + offset);
520 }
521
522 dev_err(sunxi_musb->controller->parent,
523 "Error unknown writew at 0x%x bytes offset\n",
524 (int)(addr - sunxi_musb->mregs));
525}
526
527static const struct musb_platform_ops sunxi_musb_ops = {
528 .quirks = MUSB_INDEXED_EP,
529 .init = sunxi_musb_init,
530 .exit = sunxi_musb_exit,
531 .enable = sunxi_musb_enable,
532 .disable = sunxi_musb_disable,
533 .fifo_offset = sunxi_musb_fifo_offset,
534 .ep_offset = sunxi_musb_ep_offset,
535 .busctl_offset = sunxi_musb_busctl_offset,
536 .readb = sunxi_musb_readb,
537 .writeb = sunxi_musb_writeb,
538 .readw = sunxi_musb_readw,
539 .writew = sunxi_musb_writew,
540 .set_vbus = sunxi_musb_set_vbus,
541 .pre_root_reset_end = sunxi_musb_pre_root_reset_end,
542 .post_root_reset_end = sunxi_musb_post_root_reset_end,
543};
544
545/* Allwinner OTG supports up to 5 endpoints */
546#define SUNXI_MUSB_MAX_EP_NUM 6
547#define SUNXI_MUSB_RAM_BITS 11
548
549static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
550 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
551 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
552 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
553 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
554 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
555 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
556 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
557 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
558 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
559 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
560};
561
562static struct musb_hdrc_config sunxi_musb_hdrc_config = {
563 .fifo_cfg = sunxi_musb_mode_cfg,
564 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
565 .multipoint = true,
566 .dyn_fifo = true,
567 .soft_con = true,
568 .num_eps = SUNXI_MUSB_MAX_EP_NUM,
569 .ram_bits = SUNXI_MUSB_RAM_BITS,
570 .dma = 0,
571};
572
573static int sunxi_musb_probe(struct platform_device *pdev)
574{
575 struct musb_hdrc_platform_data pdata;
576 struct platform_device_info pinfo;
577 struct sunxi_glue *glue;
578 struct device_node *np = pdev->dev.of_node;
579 int ret;
580
581 if (!np) {
582 dev_err(&pdev->dev, "Error no device tree node found\n");
583 return -EINVAL;
584 }
585
586 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
587 if (!glue)
588 return -ENOMEM;
589
590 memset(&pdata, 0, sizeof(pdata));
591 switch (of_usb_get_dr_mode(np)) {
592#if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST
593 case USB_DR_MODE_HOST:
594 pdata.mode = MUSB_PORT_MODE_HOST;
595 break;
596#endif
597#ifdef CONFIG_USB_MUSB_DUAL_ROLE
598 case USB_DR_MODE_OTG:
599 glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0);
600 if (IS_ERR(glue->extcon)) {
601 if (PTR_ERR(glue->extcon) == -EPROBE_DEFER)
602 return -EPROBE_DEFER;
603 dev_err(&pdev->dev, "Invalid or missing extcon\n");
604 return PTR_ERR(glue->extcon);
605 }
606 pdata.mode = MUSB_PORT_MODE_DUAL_ROLE;
607 break;
608#endif
609 default:
610 dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n");
611 return -EINVAL;
612 }
613 pdata.platform_ops = &sunxi_musb_ops;
614 pdata.config = &sunxi_musb_hdrc_config;
615
616 glue->dev = &pdev->dev;
617 INIT_WORK(&glue->work, sunxi_musb_work);
618 glue->host_nb.notifier_call = sunxi_musb_host_notifier;
619
620 glue->clk = devm_clk_get(&pdev->dev, NULL);
621 if (IS_ERR(glue->clk)) {
622 dev_err(&pdev->dev, "Error getting clock: %ld\n",
623 PTR_ERR(glue->clk));
624 return PTR_ERR(glue->clk);
625 }
626
627 glue->phy = devm_phy_get(&pdev->dev, "usb");
628 if (IS_ERR(glue->phy)) {
629 if (PTR_ERR(glue->phy) == -EPROBE_DEFER)
630 return -EPROBE_DEFER;
631 dev_err(&pdev->dev, "Error getting phy %ld\n",
632 PTR_ERR(glue->phy));
633 return PTR_ERR(glue->phy);
634 }
635
636 glue->usb_phy = usb_phy_generic_register();
637 if (IS_ERR(glue->usb_phy)) {
638 dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
639 PTR_ERR(glue->usb_phy));
640 return PTR_ERR(glue->usb_phy);
641 }
642
643 glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
644 if (IS_ERR(glue->xceiv)) {
645 ret = PTR_ERR(glue->xceiv);
646 dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret);
647 goto err_unregister_usb_phy;
648 }
649
650 platform_set_drvdata(pdev, glue);
651
652 memset(&pinfo, 0, sizeof(pinfo));
653 pinfo.name = "musb-hdrc";
654 pinfo.id = PLATFORM_DEVID_AUTO;
655 pinfo.parent = &pdev->dev;
656 pinfo.res = pdev->resource;
657 pinfo.num_res = pdev->num_resources;
658 pinfo.data = &pdata;
659 pinfo.size_data = sizeof(pdata);
660
661 glue->musb = platform_device_register_full(&pinfo);
662 if (IS_ERR(glue->musb)) {
663 ret = PTR_ERR(glue->musb);
664 dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret);
665 goto err_unregister_usb_phy;
666 }
667
668 return 0;
669
670err_unregister_usb_phy:
671 usb_phy_generic_unregister(glue->usb_phy);
672 return ret;
673}
674
675static int sunxi_musb_remove(struct platform_device *pdev)
676{
677 struct sunxi_glue *glue = platform_get_drvdata(pdev);
678 struct platform_device *usb_phy = glue->usb_phy;
679
680 platform_device_unregister(glue->musb); /* Frees glue ! */
681 usb_phy_generic_unregister(usb_phy);
682
683 return 0;
684}
685
686static const struct of_device_id sunxi_musb_match[] = {
687 { .compatible = "allwinner,sun4i-a10-musb", },
688 {}
689};
690
691static struct platform_driver sunxi_musb_driver = {
692 .probe = sunxi_musb_probe,
693 .remove = sunxi_musb_remove,
694 .driver = {
695 .name = "musb-sunxi",
696 .of_match_table = sunxi_musb_match,
697 },
698};
699module_platform_driver(sunxi_musb_driver);
700
701MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer");
702MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
703MODULE_LICENSE("GPL v2");
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