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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
550a7375 FB |
2 | /* |
3 | * TUSB6010 USB 2.0 OTG Dual Role controller | |
4 | * | |
5 | * Copyright (C) 2006 Nokia Corporation | |
550a7375 | 6 | * Tony Lindgren <tony@atomide.com> |
550a7375 FB |
7 | * |
8 | * Notes: | |
9 | * - Driver assumes that interface to external host (main CPU) is | |
10 | * configured for NOR FLASH interface instead of VLYNQ serial | |
11 | * interface. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/errno.h> | |
ded017ee | 17 | #include <linux/err.h> |
240a16e2 | 18 | #include <linux/prefetch.h> |
550a7375 FB |
19 | #include <linux/usb.h> |
20 | #include <linux/irq.h> | |
56c82cdc | 21 | #include <linux/io.h> |
cdfe35fb | 22 | #include <linux/device.h> |
550a7375 | 23 | #include <linux/platform_device.h> |
18688fbe | 24 | #include <linux/dma-mapping.h> |
d7078df6 | 25 | #include <linux/usb/usb_phy_generic.h> |
550a7375 FB |
26 | |
27 | #include "musb_core.h" | |
28 | ||
1add75d2 FB |
29 | struct tusb6010_glue { |
30 | struct device *dev; | |
31 | struct platform_device *musb; | |
2f36ff69 | 32 | struct platform_device *phy; |
1add75d2 FB |
33 | }; |
34 | ||
743411b3 | 35 | static void tusb_musb_set_vbus(struct musb *musb, int is_on); |
550a7375 FB |
36 | |
37 | #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) | |
38 | #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) | |
39 | ||
40 | /* | |
41 | * Checks the revision. We need to use the DMA register as 3.0 does not | |
42 | * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. | |
43 | */ | |
7751b6fb | 44 | static u8 tusb_get_revision(struct musb *musb) |
550a7375 FB |
45 | { |
46 | void __iomem *tbase = musb->ctrl_base; | |
47 | u32 die_id; | |
48 | u8 rev; | |
49 | ||
50 | rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff; | |
51 | if (TUSB_REV_MAJOR(rev) == 3) { | |
52 | die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, | |
53 | TUSB_DIDR1_HI)); | |
54 | if (die_id >= TUSB_DIDR1_HI_REV_31) | |
55 | rev |= 1; | |
56 | } | |
57 | ||
58 | return rev; | |
59 | } | |
60 | ||
7751b6fb | 61 | static void tusb_print_revision(struct musb *musb) |
550a7375 FB |
62 | { |
63 | void __iomem *tbase = musb->ctrl_base; | |
64 | u8 rev; | |
65 | ||
7751b6fb | 66 | rev = musb->tusb_revision; |
550a7375 FB |
67 | |
68 | pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n", | |
69 | "prcm", | |
70 | TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)), | |
71 | TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)), | |
72 | "int", | |
73 | TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), | |
74 | TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), | |
75 | "gpio", | |
76 | TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)), | |
77 | TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)), | |
78 | "dma", | |
79 | TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), | |
80 | TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), | |
81 | "dieid", | |
82 | TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)), | |
83 | "rev", | |
84 | TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev)); | |
550a7375 FB |
85 | } |
86 | ||
87 | #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \ | |
88 | | TUSB_PHY_OTG_CTRL_TESTM0) | |
89 | ||
90 | /* | |
91 | * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0. | |
92 | * Disables power detection in PHY for the duration of idle. | |
93 | */ | |
94 | static void tusb_wbus_quirk(struct musb *musb, int enabled) | |
95 | { | |
96 | void __iomem *tbase = musb->ctrl_base; | |
97 | static u32 phy_otg_ctrl, phy_otg_ena; | |
98 | u32 tmp; | |
99 | ||
100 | if (enabled) { | |
101 | phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); | |
102 | phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); | |
103 | tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | |
104 | | phy_otg_ena | WBUS_QUIRK_MASK; | |
105 | musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); | |
106 | tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; | |
107 | tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; | |
108 | musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); | |
5c8a86e1 | 109 | dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", |
550a7375 FB |
110 | musb_readl(tbase, TUSB_PHY_OTG_CTRL), |
111 | musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); | |
112 | } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) | |
113 | & TUSB_PHY_OTG_CTRL_TESTM2) { | |
114 | tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl; | |
115 | musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); | |
116 | tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; | |
117 | musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); | |
5c8a86e1 | 118 | dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", |
550a7375 FB |
119 | musb_readl(tbase, TUSB_PHY_OTG_CTRL), |
120 | musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); | |
121 | phy_otg_ctrl = 0; | |
122 | phy_otg_ena = 0; | |
123 | } | |
124 | } | |
125 | ||
9d506fc6 TL |
126 | static u32 tusb_fifo_offset(u8 epnum) |
127 | { | |
128 | return 0x200 + (epnum * 0x20); | |
129 | } | |
130 | ||
d026e9c7 TL |
131 | static u32 tusb_ep_offset(u8 epnum, u16 offset) |
132 | { | |
133 | return 0x10 + offset; | |
134 | } | |
135 | ||
136 | /* TUSB mapping: "flat" plus ep0 special cases */ | |
137 | static void tusb_ep_select(void __iomem *mbase, u8 epnum) | |
138 | { | |
139 | musb_writeb(mbase, MUSB_INDEX, epnum); | |
140 | } | |
141 | ||
9d506fc6 TL |
142 | /* |
143 | * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum. | |
144 | */ | |
145 | static u8 tusb_readb(const void __iomem *addr, unsigned offset) | |
146 | { | |
147 | u16 tmp; | |
148 | u8 val; | |
149 | ||
150 | tmp = __raw_readw(addr + (offset & ~1)); | |
151 | if (offset & 1) | |
152 | val = (tmp >> 8); | |
153 | else | |
154 | val = tmp & 0xff; | |
155 | ||
156 | return val; | |
157 | } | |
158 | ||
159 | static void tusb_writeb(void __iomem *addr, unsigned offset, u8 data) | |
160 | { | |
161 | u16 tmp; | |
162 | ||
163 | tmp = __raw_readw(addr + (offset & ~1)); | |
164 | if (offset & 1) | |
165 | tmp = (data << 8) | (tmp & 0xff); | |
166 | else | |
167 | tmp = (tmp & 0xff00) | data; | |
168 | ||
169 | __raw_writew(tmp, addr + (offset & ~1)); | |
170 | } | |
171 | ||
550a7375 FB |
172 | /* |
173 | * TUSB 6010 may use a parallel bus that doesn't support byte ops; | |
174 | * so both loading and unloading FIFOs need explicit byte counts. | |
175 | */ | |
176 | ||
177 | static inline void | |
178 | tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len) | |
179 | { | |
180 | u32 val; | |
181 | int i; | |
182 | ||
183 | if (len > 4) { | |
184 | for (i = 0; i < (len >> 2); i++) { | |
185 | memcpy(&val, buf, 4); | |
186 | musb_writel(fifo, 0, val); | |
187 | buf += 4; | |
188 | } | |
189 | len %= 4; | |
190 | } | |
191 | if (len > 0) { | |
192 | /* Write the rest 1 - 3 bytes to FIFO */ | |
193 | memcpy(&val, buf, len); | |
194 | musb_writel(fifo, 0, val); | |
195 | } | |
196 | } | |
197 | ||
198 | static inline void tusb_fifo_read_unaligned(void __iomem *fifo, | |
a156544b | 199 | void *buf, u16 len) |
550a7375 FB |
200 | { |
201 | u32 val; | |
202 | int i; | |
203 | ||
204 | if (len > 4) { | |
205 | for (i = 0; i < (len >> 2); i++) { | |
206 | val = musb_readl(fifo, 0); | |
207 | memcpy(buf, &val, 4); | |
208 | buf += 4; | |
209 | } | |
210 | len %= 4; | |
211 | } | |
212 | if (len > 0) { | |
213 | /* Read the rest 1 - 3 bytes from FIFO */ | |
214 | val = musb_readl(fifo, 0); | |
215 | memcpy(buf, &val, len); | |
216 | } | |
217 | } | |
218 | ||
1b40fc57 | 219 | static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) |
550a7375 | 220 | { |
28e49705 | 221 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
222 | void __iomem *ep_conf = hw_ep->conf; |
223 | void __iomem *fifo = hw_ep->fifo; | |
224 | u8 epnum = hw_ep->epnum; | |
225 | ||
226 | prefetch(buf); | |
227 | ||
5c8a86e1 | 228 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
229 | 'T', epnum, fifo, len, buf); |
230 | ||
231 | if (epnum) | |
232 | musb_writel(ep_conf, TUSB_EP_TX_OFFSET, | |
233 | TUSB_EP_CONFIG_XFR_SIZE(len)); | |
234 | else | |
235 | musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX | | |
236 | TUSB_EP0_CONFIG_XFR_SIZE(len)); | |
237 | ||
238 | if (likely((0x01 & (unsigned long) buf) == 0)) { | |
239 | ||
240 | /* Best case is 32bit-aligned destination address */ | |
241 | if ((0x02 & (unsigned long) buf) == 0) { | |
242 | if (len >= 4) { | |
56c82cdc | 243 | iowrite32_rep(fifo, buf, len >> 2); |
550a7375 FB |
244 | buf += (len & ~0x03); |
245 | len &= 0x03; | |
246 | } | |
247 | } else { | |
248 | if (len >= 2) { | |
249 | u32 val; | |
250 | int i; | |
251 | ||
252 | /* Cannot use writesw, fifo is 32-bit */ | |
253 | for (i = 0; i < (len >> 2); i++) { | |
254 | val = (u32)(*(u16 *)buf); | |
255 | buf += 2; | |
256 | val |= (*(u16 *)buf) << 16; | |
257 | buf += 2; | |
258 | musb_writel(fifo, 0, val); | |
259 | } | |
260 | len &= 0x03; | |
261 | } | |
262 | } | |
263 | } | |
264 | ||
265 | if (len > 0) | |
266 | tusb_fifo_write_unaligned(fifo, buf, len); | |
267 | } | |
268 | ||
1b40fc57 | 269 | static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) |
550a7375 | 270 | { |
28e49705 | 271 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
272 | void __iomem *ep_conf = hw_ep->conf; |
273 | void __iomem *fifo = hw_ep->fifo; | |
274 | u8 epnum = hw_ep->epnum; | |
275 | ||
5c8a86e1 | 276 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
277 | 'R', epnum, fifo, len, buf); |
278 | ||
279 | if (epnum) | |
280 | musb_writel(ep_conf, TUSB_EP_RX_OFFSET, | |
281 | TUSB_EP_CONFIG_XFR_SIZE(len)); | |
282 | else | |
283 | musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len)); | |
284 | ||
285 | if (likely((0x01 & (unsigned long) buf) == 0)) { | |
286 | ||
287 | /* Best case is 32bit-aligned destination address */ | |
288 | if ((0x02 & (unsigned long) buf) == 0) { | |
289 | if (len >= 4) { | |
56c82cdc | 290 | ioread32_rep(fifo, buf, len >> 2); |
550a7375 FB |
291 | buf += (len & ~0x03); |
292 | len &= 0x03; | |
293 | } | |
294 | } else { | |
295 | if (len >= 2) { | |
296 | u32 val; | |
297 | int i; | |
298 | ||
299 | /* Cannot use readsw, fifo is 32-bit */ | |
300 | for (i = 0; i < (len >> 2); i++) { | |
301 | val = musb_readl(fifo, 0); | |
302 | *(u16 *)buf = (u16)(val & 0xffff); | |
303 | buf += 2; | |
304 | *(u16 *)buf = (u16)(val >> 16); | |
305 | buf += 2; | |
306 | } | |
307 | len &= 0x03; | |
308 | } | |
309 | } | |
310 | } | |
311 | ||
312 | if (len > 0) | |
313 | tusb_fifo_read_unaligned(fifo, buf, len); | |
314 | } | |
315 | ||
84e250ff DB |
316 | static struct musb *the_musb; |
317 | ||
550a7375 FB |
318 | /* This is used by gadget drivers, and OTG transceiver logic, allowing |
319 | * at most mA current to be drawn from VBUS during a Default-B session | |
320 | * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host | |
321 | * mode), or low power Default-B sessions, something else supplies power. | |
322 | * Caller must take care of locking. | |
323 | */ | |
86753811 | 324 | static int tusb_draw_power(struct usb_phy *x, unsigned mA) |
550a7375 | 325 | { |
84e250ff | 326 | struct musb *musb = the_musb; |
550a7375 FB |
327 | void __iomem *tbase = musb->ctrl_base; |
328 | u32 reg; | |
329 | ||
550a7375 FB |
330 | /* tps65030 seems to consume max 100mA, with maybe 60mA available |
331 | * (measured on one board) for things other than tps and tusb. | |
332 | * | |
333 | * Boards sharing the CPU clock with CLKIN will need to prevent | |
334 | * certain idle sleep states while the USB link is active. | |
335 | * | |
336 | * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }. | |
337 | * The actual current usage would be very board-specific. For now, | |
338 | * it's simpler to just use an aggregate (also board-specific). | |
339 | */ | |
d445b6da | 340 | if (x->otg->default_a || mA < (musb->min_power << 1)) |
550a7375 FB |
341 | mA = 0; |
342 | ||
343 | reg = musb_readl(tbase, TUSB_PRCM_MNGMT); | |
344 | if (mA) { | |
345 | musb->is_bus_powered = 1; | |
346 | reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; | |
347 | } else { | |
348 | musb->is_bus_powered = 0; | |
349 | reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); | |
350 | } | |
351 | musb_writel(tbase, TUSB_PRCM_MNGMT, reg); | |
352 | ||
5c8a86e1 | 353 | dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA); |
550a7375 FB |
354 | return 0; |
355 | } | |
356 | ||
550a7375 FB |
357 | /* workaround for issue 13: change clock during chip idle |
358 | * (to be fixed in rev3 silicon) ... symptoms include disconnect | |
359 | * or looping suspend/resume cycles | |
360 | */ | |
361 | static void tusb_set_clock_source(struct musb *musb, unsigned mode) | |
362 | { | |
363 | void __iomem *tbase = musb->ctrl_base; | |
364 | u32 reg; | |
365 | ||
366 | reg = musb_readl(tbase, TUSB_PRCM_CONF); | |
367 | reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); | |
368 | ||
369 | /* 0 = refclk (clkin, XI) | |
370 | * 1 = PHY 60 MHz (internal PLL) | |
371 | * 2 = not supported | |
372 | * 3 = what? | |
373 | */ | |
374 | if (mode > 0) | |
375 | reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); | |
376 | ||
377 | musb_writel(tbase, TUSB_PRCM_CONF, reg); | |
378 | ||
379 | /* FIXME tusb6010_platform_retime(mode == 0); */ | |
380 | } | |
381 | ||
382 | /* | |
383 | * Idle TUSB6010 until next wake-up event; NOR access always wakes. | |
384 | * Other code ensures that we idle unless we're connected _and_ the | |
385 | * USB link is not suspended ... and tells us the relevant wakeup | |
386 | * events. SW_EN for voltage is handled separately. | |
387 | */ | |
743411b3 | 388 | static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables) |
550a7375 FB |
389 | { |
390 | void __iomem *tbase = musb->ctrl_base; | |
391 | u32 reg; | |
392 | ||
393 | if ((wakeup_enables & TUSB_PRCM_WBUS) | |
7751b6fb | 394 | && (musb->tusb_revision == TUSB_REV_30)) |
550a7375 FB |
395 | tusb_wbus_quirk(musb, 1); |
396 | ||
397 | tusb_set_clock_source(musb, 0); | |
398 | ||
399 | wakeup_enables |= TUSB_PRCM_WNORCS; | |
400 | musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables); | |
401 | ||
402 | /* REVISIT writeup of WID implies that if WID set and ID is grounded, | |
403 | * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared. | |
404 | * Presumably that's mostly to save power, hence WID is immaterial ... | |
405 | */ | |
406 | ||
407 | reg = musb_readl(tbase, TUSB_PRCM_MNGMT); | |
408 | /* issue 4: when driving vbus, use hipower (vbus_det) comparator */ | |
409 | if (is_host_active(musb)) { | |
410 | reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; | |
411 | reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; | |
412 | } else { | |
413 | reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; | |
414 | reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; | |
415 | } | |
416 | reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; | |
417 | musb_writel(tbase, TUSB_PRCM_MNGMT, reg); | |
418 | ||
5c8a86e1 | 419 | dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables); |
550a7375 FB |
420 | } |
421 | ||
422 | /* | |
423 | * Updates cable VBUS status. Caller must take care of locking. | |
424 | */ | |
743411b3 | 425 | static int tusb_musb_vbus_status(struct musb *musb) |
550a7375 FB |
426 | { |
427 | void __iomem *tbase = musb->ctrl_base; | |
428 | u32 otg_stat, prcm_mngmt; | |
429 | int ret = 0; | |
430 | ||
431 | otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); | |
432 | prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT); | |
433 | ||
434 | /* Temporarily enable VBUS detection if it was disabled for | |
435 | * suspend mode. Unless it's enabled otg_stat and devctl will | |
436 | * not show correct VBUS state. | |
437 | */ | |
438 | if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) { | |
439 | u32 tmp = prcm_mngmt; | |
440 | tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; | |
441 | musb_writel(tbase, TUSB_PRCM_MNGMT, tmp); | |
442 | otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); | |
443 | musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt); | |
444 | } | |
445 | ||
446 | if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) | |
447 | ret = 1; | |
448 | ||
449 | return ret; | |
450 | } | |
451 | ||
05678497 | 452 | static void musb_do_idle(struct timer_list *t) |
550a7375 | 453 | { |
05678497 | 454 | struct musb *musb = from_timer(musb, t, dev_timer); |
550a7375 FB |
455 | unsigned long flags; |
456 | ||
457 | spin_lock_irqsave(&musb->lock, flags); | |
458 | ||
e47d9254 | 459 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
460 | case OTG_STATE_A_WAIT_BCON: |
461 | if ((musb->a_wait_bcon != 0) | |
462 | && (musb->idle_timeout == 0 | |
463 | || time_after(jiffies, musb->idle_timeout))) { | |
5c8a86e1 | 464 | dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n", |
e47d9254 | 465 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
466 | } |
467 | /* FALLTHROUGH */ | |
468 | case OTG_STATE_A_IDLE: | |
743411b3 | 469 | tusb_musb_set_vbus(musb, 0); |
550a7375 FB |
470 | default: |
471 | break; | |
472 | } | |
473 | ||
474 | if (!musb->is_active) { | |
475 | u32 wakeups; | |
476 | ||
37ebb549 | 477 | /* wait until hub_wq handles port change status */ |
550a7375 FB |
478 | if (is_host_active(musb) && (musb->port1_status >> 16)) |
479 | goto done; | |
480 | ||
032ec49f | 481 | if (!musb->gadget_driver) { |
550a7375 | 482 | wakeups = 0; |
62285963 | 483 | } else { |
550a7375 | 484 | wakeups = TUSB_PRCM_WHOSTDISCON |
62285963 | 485 | | TUSB_PRCM_WBUS |
550a7375 | 486 | | TUSB_PRCM_WVBUS; |
032ec49f | 487 | wakeups |= TUSB_PRCM_WID; |
550a7375 | 488 | } |
550a7375 FB |
489 | tusb_allow_idle(musb, wakeups); |
490 | } | |
491 | done: | |
492 | spin_unlock_irqrestore(&musb->lock, flags); | |
493 | } | |
494 | ||
495 | /* | |
496 | * Maybe put TUSB6010 into idle mode mode depending on USB link status, | |
497 | * like "disconnected" or "suspended". We'll be woken out of it by | |
498 | * connect, resume, or disconnect. | |
499 | * | |
500 | * Needs to be called as the last function everywhere where there is | |
501 | * register access to TUSB6010 because of NOR flash wake-up. | |
502 | * Caller should own controller spinlock. | |
503 | * | |
504 | * Delay because peripheral enables D+ pullup 3msec after SE0, and | |
505 | * we don't want to treat that full speed J as a wakeup event. | |
506 | * ... peripherals must draw only suspend current after 10 msec. | |
507 | */ | |
743411b3 | 508 | static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout) |
550a7375 FB |
509 | { |
510 | unsigned long default_timeout = jiffies + msecs_to_jiffies(3); | |
511 | static unsigned long last_timer; | |
512 | ||
513 | if (timeout == 0) | |
514 | timeout = default_timeout; | |
515 | ||
516 | /* Never idle if active, or when VBUS timeout is not set as host */ | |
517 | if (musb->is_active || ((musb->a_wait_bcon == 0) | |
e47d9254 | 518 | && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) { |
5c8a86e1 | 519 | dev_dbg(musb->controller, "%s active, deleting timer\n", |
e47d9254 | 520 | usb_otg_state_string(musb->xceiv->otg->state)); |
05678497 | 521 | del_timer(&musb->dev_timer); |
550a7375 FB |
522 | last_timer = jiffies; |
523 | return; | |
524 | } | |
525 | ||
526 | if (time_after(last_timer, timeout)) { | |
05678497 | 527 | if (!timer_pending(&musb->dev_timer)) |
550a7375 FB |
528 | last_timer = timeout; |
529 | else { | |
5c8a86e1 | 530 | dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n"); |
550a7375 FB |
531 | return; |
532 | } | |
533 | } | |
534 | last_timer = timeout; | |
535 | ||
5c8a86e1 | 536 | dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n", |
e47d9254 | 537 | usb_otg_state_string(musb->xceiv->otg->state), |
550a7375 | 538 | (unsigned long)jiffies_to_msecs(timeout - jiffies)); |
05678497 | 539 | mod_timer(&musb->dev_timer, timeout); |
550a7375 FB |
540 | } |
541 | ||
542 | /* ticks of 60 MHz clock */ | |
543 | #define DEVCLOCK 60000000 | |
544 | #define OTG_TIMER_MS(msecs) ((msecs) \ | |
545 | ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \ | |
546 | | TUSB_DEV_OTG_TIMER_ENABLE) \ | |
547 | : 0) | |
548 | ||
743411b3 | 549 | static void tusb_musb_set_vbus(struct musb *musb, int is_on) |
550a7375 FB |
550 | { |
551 | void __iomem *tbase = musb->ctrl_base; | |
552 | u32 conf, prcm, timer; | |
553 | u8 devctl; | |
d445b6da | 554 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 FB |
555 | |
556 | /* HDRC controls CPEN, but beware current surges during device | |
557 | * connect. They can trigger transient overcurrent conditions | |
558 | * that must be ignored. | |
559 | */ | |
560 | ||
561 | prcm = musb_readl(tbase, TUSB_PRCM_MNGMT); | |
562 | conf = musb_readl(tbase, TUSB_DEV_CONF); | |
563 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
564 | ||
565 | if (is_on) { | |
550a7375 | 566 | timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); |
d445b6da | 567 | otg->default_a = 1; |
e47d9254 | 568 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; |
550a7375 FB |
569 | devctl |= MUSB_DEVCTL_SESSION; |
570 | ||
571 | conf |= TUSB_DEV_CONF_USB_HOST_MODE; | |
572 | MUSB_HST_MODE(musb); | |
573 | } else { | |
574 | u32 otg_stat; | |
575 | ||
576 | timer = 0; | |
577 | ||
578 | /* If ID pin is grounded, we want to be a_idle */ | |
579 | otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); | |
580 | if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { | |
e47d9254 | 581 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
582 | case OTG_STATE_A_WAIT_VRISE: |
583 | case OTG_STATE_A_WAIT_BCON: | |
e47d9254 | 584 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
585 | break; |
586 | case OTG_STATE_A_WAIT_VFALL: | |
e47d9254 | 587 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
550a7375 FB |
588 | break; |
589 | default: | |
e47d9254 | 590 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
550a7375 FB |
591 | } |
592 | musb->is_active = 0; | |
d445b6da | 593 | otg->default_a = 1; |
550a7375 FB |
594 | MUSB_HST_MODE(musb); |
595 | } else { | |
596 | musb->is_active = 0; | |
d445b6da | 597 | otg->default_a = 0; |
e47d9254 | 598 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
550a7375 FB |
599 | MUSB_DEV_MODE(musb); |
600 | } | |
601 | ||
602 | devctl &= ~MUSB_DEVCTL_SESSION; | |
603 | conf &= ~TUSB_DEV_CONF_USB_HOST_MODE; | |
550a7375 FB |
604 | } |
605 | prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); | |
606 | ||
607 | musb_writel(tbase, TUSB_PRCM_MNGMT, prcm); | |
608 | musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer); | |
609 | musb_writel(tbase, TUSB_DEV_CONF, conf); | |
610 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); | |
611 | ||
5c8a86e1 | 612 | dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", |
e47d9254 | 613 | usb_otg_state_string(musb->xceiv->otg->state), |
550a7375 FB |
614 | musb_readb(musb->mregs, MUSB_DEVCTL), |
615 | musb_readl(tbase, TUSB_DEV_OTG_STAT), | |
616 | conf, prcm); | |
617 | } | |
618 | ||
619 | /* | |
620 | * Sets the mode to OTG, peripheral or host by changing the ID detection. | |
621 | * Caller must take care of locking. | |
622 | * | |
623 | * Note that if a mini-A cable is plugged in the ID line will stay down as | |
624 | * the weak ID pull-up is not able to pull the ID up. | |
550a7375 | 625 | */ |
743411b3 | 626 | static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode) |
550a7375 FB |
627 | { |
628 | void __iomem *tbase = musb->ctrl_base; | |
629 | u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf; | |
630 | ||
550a7375 FB |
631 | otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); |
632 | phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); | |
633 | phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); | |
634 | dev_conf = musb_readl(tbase, TUSB_DEV_CONF); | |
635 | ||
636 | switch (musb_mode) { | |
637 | ||
550a7375 FB |
638 | case MUSB_HOST: /* Disable PHY ID detect, ground ID */ |
639 | phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
640 | phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
641 | dev_conf |= TUSB_DEV_CONF_ID_SEL; | |
642 | dev_conf &= ~TUSB_DEV_CONF_SOFT_ID; | |
643 | break; | |
550a7375 FB |
644 | case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */ |
645 | phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
646 | phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
647 | dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); | |
648 | break; | |
550a7375 FB |
649 | case MUSB_OTG: /* Use PHY ID detection */ |
650 | phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
651 | phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
652 | dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); | |
653 | break; | |
550a7375 FB |
654 | |
655 | default: | |
5c8a86e1 | 656 | dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode); |
96a274d1 | 657 | return -EINVAL; |
550a7375 FB |
658 | } |
659 | ||
660 | musb_writel(tbase, TUSB_PHY_OTG_CTRL, | |
661 | TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl); | |
662 | musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, | |
663 | TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena); | |
664 | musb_writel(tbase, TUSB_DEV_CONF, dev_conf); | |
665 | ||
666 | otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); | |
667 | if ((musb_mode == MUSB_PERIPHERAL) && | |
668 | !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) | |
669 | INFO("Cannot be peripheral with mini-A cable " | |
670 | "otg_stat: %08x\n", otg_stat); | |
96a274d1 DB |
671 | |
672 | return 0; | |
550a7375 FB |
673 | } |
674 | ||
675 | static inline unsigned long | |
676 | tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) | |
677 | { | |
678 | u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); | |
679 | unsigned long idle_timeout = 0; | |
d445b6da | 680 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 FB |
681 | |
682 | /* ID pin */ | |
683 | if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) { | |
684 | int default_a; | |
685 | ||
032ec49f | 686 | default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); |
5c8a86e1 | 687 | dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B'); |
d445b6da | 688 | otg->default_a = default_a; |
743411b3 | 689 | tusb_musb_set_vbus(musb, default_a); |
550a7375 FB |
690 | |
691 | /* Don't allow idling immediately */ | |
692 | if (default_a) | |
693 | idle_timeout = jiffies + (HZ * 3); | |
694 | } | |
695 | ||
696 | /* VBUS state change */ | |
697 | if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { | |
698 | ||
699 | /* B-dev state machine: no vbus ~= disconnect */ | |
032ec49f | 700 | if (!otg->default_a) { |
550a7375 FB |
701 | /* ? musb_root_disconnect(musb); */ |
702 | musb->port1_status &= | |
703 | ~(USB_PORT_STAT_CONNECTION | |
704 | | USB_PORT_STAT_ENABLE | |
705 | | USB_PORT_STAT_LOW_SPEED | |
706 | | USB_PORT_STAT_HIGH_SPEED | |
707 | | USB_PORT_STAT_TEST | |
708 | ); | |
550a7375 FB |
709 | |
710 | if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { | |
5c8a86e1 | 711 | dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n"); |
e47d9254 | 712 | if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) { |
550a7375 | 713 | /* INTR_DISCONNECT can hide... */ |
e47d9254 | 714 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
550a7375 FB |
715 | musb->int_usb |= MUSB_INTR_DISCONNECT; |
716 | } | |
717 | musb->is_active = 0; | |
718 | } | |
5c8a86e1 | 719 | dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", |
e47d9254 | 720 | usb_otg_state_string(musb->xceiv->otg->state), otg_stat); |
550a7375 | 721 | idle_timeout = jiffies + (1 * HZ); |
2bff3916 | 722 | schedule_delayed_work(&musb->irq_work, 0); |
550a7375 FB |
723 | |
724 | } else /* A-dev state machine */ { | |
5c8a86e1 | 725 | dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", |
e47d9254 | 726 | usb_otg_state_string(musb->xceiv->otg->state), otg_stat); |
550a7375 | 727 | |
e47d9254 | 728 | switch (musb->xceiv->otg->state) { |
550a7375 | 729 | case OTG_STATE_A_IDLE: |
5c8a86e1 | 730 | dev_dbg(musb->controller, "Got SRP, turning on VBUS\n"); |
743411b3 | 731 | musb_platform_set_vbus(musb, 1); |
550a7375 FB |
732 | |
733 | /* CONNECT can wake if a_wait_bcon is set */ | |
734 | if (musb->a_wait_bcon != 0) | |
735 | musb->is_active = 0; | |
736 | else | |
737 | musb->is_active = 1; | |
738 | ||
739 | /* | |
740 | * OPT FS A TD.4.6 needs few seconds for | |
741 | * A_WAIT_VRISE | |
742 | */ | |
743 | idle_timeout = jiffies + (2 * HZ); | |
744 | ||
745 | break; | |
746 | case OTG_STATE_A_WAIT_VRISE: | |
747 | /* ignore; A-session-valid < VBUS_VALID/2, | |
748 | * we monitor this with the timer | |
749 | */ | |
750 | break; | |
751 | case OTG_STATE_A_WAIT_VFALL: | |
752 | /* REVISIT this irq triggers during short | |
753 | * spikes caused by enumeration ... | |
754 | */ | |
755 | if (musb->vbuserr_retry) { | |
756 | musb->vbuserr_retry--; | |
743411b3 | 757 | tusb_musb_set_vbus(musb, 1); |
550a7375 FB |
758 | } else { |
759 | musb->vbuserr_retry | |
760 | = VBUSERR_RETRY_COUNT; | |
743411b3 | 761 | tusb_musb_set_vbus(musb, 0); |
550a7375 FB |
762 | } |
763 | break; | |
764 | default: | |
765 | break; | |
766 | } | |
767 | } | |
768 | } | |
769 | ||
770 | /* OTG timer expiration */ | |
771 | if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { | |
772 | u8 devctl; | |
773 | ||
5c8a86e1 | 774 | dev_dbg(musb->controller, "%s timer, %03x\n", |
e47d9254 | 775 | usb_otg_state_string(musb->xceiv->otg->state), otg_stat); |
550a7375 | 776 | |
e47d9254 | 777 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
778 | case OTG_STATE_A_WAIT_VRISE: |
779 | /* VBUS has probably been valid for a while now, | |
780 | * but may well have bounced out of range a bit | |
781 | */ | |
782 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
783 | if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { | |
784 | if ((devctl & MUSB_DEVCTL_VBUS) | |
785 | != MUSB_DEVCTL_VBUS) { | |
5c8a86e1 | 786 | dev_dbg(musb->controller, "devctl %02x\n", devctl); |
550a7375 FB |
787 | break; |
788 | } | |
e47d9254 | 789 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; |
550a7375 FB |
790 | musb->is_active = 0; |
791 | idle_timeout = jiffies | |
792 | + msecs_to_jiffies(musb->a_wait_bcon); | |
793 | } else { | |
794 | /* REVISIT report overcurrent to hub? */ | |
795 | ERR("vbus too slow, devctl %02x\n", devctl); | |
743411b3 | 796 | tusb_musb_set_vbus(musb, 0); |
550a7375 FB |
797 | } |
798 | break; | |
799 | case OTG_STATE_A_WAIT_BCON: | |
800 | if (musb->a_wait_bcon != 0) | |
801 | idle_timeout = jiffies | |
802 | + msecs_to_jiffies(musb->a_wait_bcon); | |
803 | break; | |
804 | case OTG_STATE_A_SUSPEND: | |
805 | break; | |
806 | case OTG_STATE_B_WAIT_ACON: | |
807 | break; | |
808 | default: | |
809 | break; | |
810 | } | |
811 | } | |
2bff3916 | 812 | schedule_delayed_work(&musb->irq_work, 0); |
550a7375 FB |
813 | |
814 | return idle_timeout; | |
815 | } | |
816 | ||
743411b3 | 817 | static irqreturn_t tusb_musb_interrupt(int irq, void *__hci) |
550a7375 FB |
818 | { |
819 | struct musb *musb = __hci; | |
820 | void __iomem *tbase = musb->ctrl_base; | |
821 | unsigned long flags, idle_timeout = 0; | |
822 | u32 int_mask, int_src; | |
823 | ||
824 | spin_lock_irqsave(&musb->lock, flags); | |
825 | ||
826 | /* Mask all interrupts to allow using both edge and level GPIO irq */ | |
827 | int_mask = musb_readl(tbase, TUSB_INT_MASK); | |
828 | musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); | |
829 | ||
830 | int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; | |
5c8a86e1 | 831 | dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src); |
550a7375 FB |
832 | |
833 | musb->int_usb = (u8) int_src; | |
834 | ||
835 | /* Acknowledge wake-up source interrupts */ | |
836 | if (int_src & TUSB_INT_SRC_DEV_WAKEUP) { | |
837 | u32 reg; | |
838 | u32 i; | |
839 | ||
7751b6fb | 840 | if (musb->tusb_revision == TUSB_REV_30) |
550a7375 FB |
841 | tusb_wbus_quirk(musb, 0); |
842 | ||
843 | /* there are issues re-locking the PLL on wakeup ... */ | |
844 | ||
845 | /* work around issue 8 */ | |
846 | for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) { | |
847 | musb_writel(tbase, TUSB_SCRATCH_PAD, 0); | |
848 | musb_writel(tbase, TUSB_SCRATCH_PAD, i); | |
849 | reg = musb_readl(tbase, TUSB_SCRATCH_PAD); | |
850 | if (reg == i) | |
851 | break; | |
5c8a86e1 | 852 | dev_dbg(musb->controller, "TUSB NOR not ready\n"); |
550a7375 FB |
853 | } |
854 | ||
855 | /* work around issue 13 (2nd half) */ | |
856 | tusb_set_clock_source(musb, 1); | |
857 | ||
858 | reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE); | |
859 | musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); | |
860 | if (reg & ~TUSB_PRCM_WNORCS) { | |
861 | musb->is_active = 1; | |
2bff3916 | 862 | schedule_delayed_work(&musb->irq_work, 0); |
550a7375 | 863 | } |
5c8a86e1 | 864 | dev_dbg(musb->controller, "wake %sactive %02x\n", |
550a7375 FB |
865 | musb->is_active ? "" : "in", reg); |
866 | ||
867 | /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ | |
868 | } | |
869 | ||
870 | if (int_src & TUSB_INT_SRC_USB_IP_CONN) | |
05678497 | 871 | del_timer(&musb->dev_timer); |
550a7375 FB |
872 | |
873 | /* OTG state change reports (annoyingly) not issued by Mentor core */ | |
874 | if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG | |
875 | | TUSB_INT_SRC_OTG_TIMEOUT | |
876 | | TUSB_INT_SRC_ID_STATUS_CHNG)) | |
877 | idle_timeout = tusb_otg_ints(musb, int_src, tbase); | |
878 | ||
47699b0a PU |
879 | /* |
880 | * Just clear the DMA interrupt if it comes as the completion for both | |
881 | * TX and RX is handled by the DMA callback in tusb6010_omap | |
550a7375 FB |
882 | */ |
883 | if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) { | |
884 | u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); | |
550a7375 | 885 | |
5c8a86e1 | 886 | dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src); |
550a7375 FB |
887 | musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src); |
888 | } | |
889 | ||
890 | /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */ | |
891 | if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) { | |
892 | u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC); | |
893 | ||
894 | musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src); | |
895 | musb->int_rx = (((musb_src >> 16) & 0xffff) << 1); | |
896 | musb->int_tx = (musb_src & 0xffff); | |
897 | } else { | |
898 | musb->int_rx = 0; | |
899 | musb->int_tx = 0; | |
900 | } | |
901 | ||
902 | if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff)) | |
903 | musb_interrupt(musb); | |
904 | ||
905 | /* Acknowledge TUSB interrupts. Clear only non-reserved bits */ | |
906 | musb_writel(tbase, TUSB_INT_SRC_CLEAR, | |
907 | int_src & ~TUSB_INT_MASK_RESERVED_BITS); | |
908 | ||
743411b3 | 909 | tusb_musb_try_idle(musb, idle_timeout); |
550a7375 FB |
910 | |
911 | musb_writel(tbase, TUSB_INT_MASK, int_mask); | |
912 | spin_unlock_irqrestore(&musb->lock, flags); | |
913 | ||
914 | return IRQ_HANDLED; | |
915 | } | |
916 | ||
917 | static int dma_off; | |
918 | ||
919 | /* | |
920 | * Enables TUSB6010. Caller must take care of locking. | |
921 | * REVISIT: | |
922 | * - Check what is unnecessary in MGC_HdrcStart() | |
923 | */ | |
743411b3 | 924 | static void tusb_musb_enable(struct musb *musb) |
550a7375 FB |
925 | { |
926 | void __iomem *tbase = musb->ctrl_base; | |
927 | ||
928 | /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF. | |
929 | * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */ | |
930 | musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF); | |
931 | ||
932 | /* Setup TUSB interrupt, disable DMA and GPIO interrupts */ | |
933 | musb_writel(tbase, TUSB_USBIP_INT_MASK, 0); | |
934 | musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); | |
935 | musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); | |
936 | ||
937 | /* Clear all subsystem interrups */ | |
938 | musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff); | |
939 | musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff); | |
940 | musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff); | |
941 | ||
942 | /* Acknowledge pending interrupt(s) */ | |
943 | musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS); | |
944 | ||
945 | /* Only 0 clock cycles for minimum interrupt de-assertion time and | |
946 | * interrupt polarity active low seems to work reliably here */ | |
947 | musb_writel(tbase, TUSB_INT_CTRL_CONF, | |
948 | TUSB_INT_CTRL_CONF_INT_RELCYC(0)); | |
949 | ||
dced35ae | 950 | irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW); |
550a7375 FB |
951 | |
952 | /* maybe force into the Default-A OTG state machine */ | |
953 | if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT) | |
954 | & TUSB_DEV_OTG_STAT_ID_STATUS)) | |
955 | musb_writel(tbase, TUSB_INT_SRC_SET, | |
956 | TUSB_INT_SRC_ID_STATUS_CHNG); | |
957 | ||
958 | if (is_dma_capable() && dma_off) | |
959 | printk(KERN_WARNING "%s %s: dma not reactivated\n", | |
960 | __FILE__, __func__); | |
961 | else | |
962 | dma_off = 1; | |
963 | } | |
964 | ||
965 | /* | |
966 | * Disables TUSB6010. Caller must take care of locking. | |
967 | */ | |
743411b3 | 968 | static void tusb_musb_disable(struct musb *musb) |
550a7375 FB |
969 | { |
970 | void __iomem *tbase = musb->ctrl_base; | |
971 | ||
972 | /* FIXME stop DMA, IRQs, timers, ... */ | |
973 | ||
974 | /* disable all IRQs */ | |
975 | musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); | |
976 | musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff); | |
977 | musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); | |
978 | musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); | |
979 | ||
05678497 | 980 | del_timer(&musb->dev_timer); |
550a7375 FB |
981 | |
982 | if (is_dma_capable() && !dma_off) { | |
983 | printk(KERN_WARNING "%s %s: dma still active\n", | |
984 | __FILE__, __func__); | |
985 | dma_off = 1; | |
986 | } | |
987 | } | |
988 | ||
989 | /* | |
990 | * Sets up TUSB6010 CPU interface specific signals and registers | |
991 | * Note: Settings optimized for OMAP24xx | |
992 | */ | |
743411b3 | 993 | static void tusb_setup_cpu_interface(struct musb *musb) |
550a7375 FB |
994 | { |
995 | void __iomem *tbase = musb->ctrl_base; | |
996 | ||
997 | /* | |
998 | * Disable GPIO[5:0] pullups (used as output DMA requests) | |
999 | * Don't disable GPIO[7:6] as they are needed for wake-up. | |
1000 | */ | |
1001 | musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F); | |
1002 | ||
1003 | /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */ | |
1004 | musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF); | |
1005 | ||
1006 | /* Turn GPIO[5:0] to DMAREQ[5:0] signals */ | |
1007 | musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f)); | |
1008 | ||
1009 | /* Burst size 16x16 bits, all six DMA requests enabled, DMA request | |
1010 | * de-assertion time 2 system clocks p 62 */ | |
1011 | musb_writel(tbase, TUSB_DMA_REQ_CONF, | |
1012 | TUSB_DMA_REQ_CONF_BURST_SIZE(2) | | |
1013 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | | |
1014 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); | |
1015 | ||
1016 | /* Set 0 wait count for synchronous burst access */ | |
1017 | musb_writel(tbase, TUSB_WAIT_COUNT, 1); | |
1018 | } | |
1019 | ||
743411b3 | 1020 | static int tusb_musb_start(struct musb *musb) |
550a7375 FB |
1021 | { |
1022 | void __iomem *tbase = musb->ctrl_base; | |
1023 | int ret = 0; | |
1024 | unsigned long flags; | |
1025 | u32 reg; | |
1026 | ||
1027 | if (musb->board_set_power) | |
1028 | ret = musb->board_set_power(1); | |
1029 | if (ret != 0) { | |
1030 | printk(KERN_ERR "tusb: Cannot enable TUSB6010\n"); | |
1031 | return ret; | |
1032 | } | |
1033 | ||
1034 | spin_lock_irqsave(&musb->lock, flags); | |
1035 | ||
1036 | if (musb_readl(tbase, TUSB_PROD_TEST_RESET) != | |
1037 | TUSB_PROD_TEST_RESET_VAL) { | |
1038 | printk(KERN_ERR "tusb: Unable to detect TUSB6010\n"); | |
1039 | goto err; | |
1040 | } | |
1041 | ||
8c240dc1 | 1042 | musb->tusb_revision = tusb_get_revision(musb); |
7751b6fb MK |
1043 | tusb_print_revision(musb); |
1044 | if (musb->tusb_revision < 2) { | |
550a7375 | 1045 | printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n", |
7751b6fb | 1046 | musb->tusb_revision); |
550a7375 FB |
1047 | goto err; |
1048 | } | |
1049 | ||
1050 | /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when | |
1051 | * NOR FLASH interface is used */ | |
1052 | musb_writel(tbase, TUSB_VLYNQ_CTRL, 8); | |
1053 | ||
1054 | /* Select PHY free running 60MHz as a system clock */ | |
1055 | tusb_set_clock_source(musb, 1); | |
1056 | ||
1057 | /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for | |
1058 | * power saving, enable VBus detect and session end comparators, | |
1059 | * enable IDpullup, enable VBus charging */ | |
1060 | musb_writel(tbase, TUSB_PRCM_MNGMT, | |
1061 | TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) | | |
1062 | TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN | | |
1063 | TUSB_PRCM_MNGMT_OTG_SESS_END_EN | | |
1064 | TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN | | |
1065 | TUSB_PRCM_MNGMT_OTG_ID_PULLUP); | |
1066 | tusb_setup_cpu_interface(musb); | |
1067 | ||
1068 | /* simplify: always sense/pullup ID pins, as if in OTG mode */ | |
1069 | reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); | |
1070 | reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
1071 | musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg); | |
1072 | ||
1073 | reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL); | |
1074 | reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
1075 | musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg); | |
1076 | ||
1077 | spin_unlock_irqrestore(&musb->lock, flags); | |
1078 | ||
1079 | return 0; | |
1080 | ||
1081 | err: | |
1082 | spin_unlock_irqrestore(&musb->lock, flags); | |
1083 | ||
1084 | if (musb->board_set_power) | |
1085 | musb->board_set_power(0); | |
1086 | ||
1087 | return -ENODEV; | |
1088 | } | |
1089 | ||
743411b3 | 1090 | static int tusb_musb_init(struct musb *musb) |
550a7375 FB |
1091 | { |
1092 | struct platform_device *pdev; | |
1093 | struct resource *mem; | |
84e250ff | 1094 | void __iomem *sync = NULL; |
550a7375 FB |
1095 | int ret; |
1096 | ||
662dca54 | 1097 | musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); |
ded017ee | 1098 | if (IS_ERR_OR_NULL(musb->xceiv)) |
25736e0c | 1099 | return -EPROBE_DEFER; |
84e250ff | 1100 | |
550a7375 FB |
1101 | pdev = to_platform_device(musb->controller); |
1102 | ||
1103 | /* dma address for async dma */ | |
1104 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1105 | musb->async = mem->start; | |
1106 | ||
1107 | /* dma address for sync dma */ | |
1108 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1109 | if (!mem) { | |
1110 | pr_debug("no sync dma resource?\n"); | |
84e250ff DB |
1111 | ret = -ENODEV; |
1112 | goto done; | |
550a7375 FB |
1113 | } |
1114 | musb->sync = mem->start; | |
1115 | ||
3d268645 | 1116 | sync = ioremap(mem->start, resource_size(mem)); |
550a7375 FB |
1117 | if (!sync) { |
1118 | pr_debug("ioremap for sync failed\n"); | |
84e250ff DB |
1119 | ret = -ENOMEM; |
1120 | goto done; | |
550a7375 FB |
1121 | } |
1122 | musb->sync_va = sync; | |
1123 | ||
1124 | /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400, | |
1125 | * FIFOs at 0x600, TUSB at 0x800 | |
1126 | */ | |
1127 | musb->mregs += TUSB_BASE_OFFSET; | |
1128 | ||
743411b3 | 1129 | ret = tusb_musb_start(musb); |
550a7375 FB |
1130 | if (ret) { |
1131 | printk(KERN_ERR "Could not start tusb6010 (%d)\n", | |
1132 | ret); | |
84e250ff | 1133 | goto done; |
550a7375 | 1134 | } |
743411b3 | 1135 | musb->isr = tusb_musb_interrupt; |
550a7375 | 1136 | |
032ec49f FB |
1137 | musb->xceiv->set_power = tusb_draw_power; |
1138 | the_musb = musb; | |
550a7375 | 1139 | |
05678497 | 1140 | timer_setup(&musb->dev_timer, musb_do_idle, 0); |
550a7375 | 1141 | |
84e250ff DB |
1142 | done: |
1143 | if (ret < 0) { | |
1144 | if (sync) | |
1145 | iounmap(sync); | |
f4053874 | 1146 | |
721002ec | 1147 | usb_put_phy(musb->xceiv); |
84e250ff | 1148 | } |
550a7375 FB |
1149 | return ret; |
1150 | } | |
1151 | ||
743411b3 | 1152 | static int tusb_musb_exit(struct musb *musb) |
550a7375 | 1153 | { |
05678497 | 1154 | del_timer_sync(&musb->dev_timer); |
84e250ff | 1155 | the_musb = NULL; |
550a7375 FB |
1156 | |
1157 | if (musb->board_set_power) | |
1158 | musb->board_set_power(0); | |
1159 | ||
1160 | iounmap(musb->sync_va); | |
f4053874 | 1161 | |
721002ec | 1162 | usb_put_phy(musb->xceiv); |
550a7375 FB |
1163 | return 0; |
1164 | } | |
743411b3 | 1165 | |
f7ec9437 | 1166 | static const struct musb_platform_ops tusb_ops = { |
0efc1356 PU |
1167 | .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB | |
1168 | MUSB_G_NO_SKB_RESERVE, | |
743411b3 FB |
1169 | .init = tusb_musb_init, |
1170 | .exit = tusb_musb_exit, | |
1171 | ||
d026e9c7 TL |
1172 | .ep_offset = tusb_ep_offset, |
1173 | .ep_select = tusb_ep_select, | |
9d506fc6 TL |
1174 | .fifo_offset = tusb_fifo_offset, |
1175 | .readb = tusb_readb, | |
1176 | .writeb = tusb_writeb, | |
1b40fc57 TL |
1177 | .read_fifo = tusb_read_fifo, |
1178 | .write_fifo = tusb_write_fifo, | |
7f6283ed TL |
1179 | #ifdef CONFIG_USB_TUSB_OMAP_DMA |
1180 | .dma_init = tusb_dma_controller_create, | |
1181 | .dma_exit = tusb_dma_controller_destroy, | |
1182 | #endif | |
743411b3 FB |
1183 | .enable = tusb_musb_enable, |
1184 | .disable = tusb_musb_disable, | |
1185 | ||
1186 | .set_mode = tusb_musb_set_mode, | |
1187 | .try_idle = tusb_musb_try_idle, | |
1188 | ||
1189 | .vbus_status = tusb_musb_vbus_status, | |
1190 | .set_vbus = tusb_musb_set_vbus, | |
1191 | }; | |
18688fbe | 1192 | |
af384875 RK |
1193 | static const struct platform_device_info tusb_dev_info = { |
1194 | .name = "musb-hdrc", | |
1195 | .id = PLATFORM_DEVID_AUTO, | |
1196 | .dma_mask = DMA_BIT_MASK(32), | |
1197 | }; | |
18688fbe | 1198 | |
41ac7b3a | 1199 | static int tusb_probe(struct platform_device *pdev) |
18688fbe | 1200 | { |
c1f01be4 | 1201 | struct resource musb_resources[3]; |
c1a7d67c | 1202 | struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
18688fbe | 1203 | struct platform_device *musb; |
1add75d2 | 1204 | struct tusb6010_glue *glue; |
af384875 | 1205 | struct platform_device_info pinfo; |
cdfe35fb | 1206 | int ret; |
18688fbe | 1207 | |
cdfe35fb | 1208 | glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); |
6a58856f | 1209 | if (!glue) |
cdfe35fb | 1210 | return -ENOMEM; |
1add75d2 | 1211 | |
1add75d2 | 1212 | glue->dev = &pdev->dev; |
1add75d2 | 1213 | |
f7ec9437 FB |
1214 | pdata->platform_ops = &tusb_ops; |
1215 | ||
e741e637 | 1216 | usb_phy_generic_register(); |
1add75d2 | 1217 | platform_set_drvdata(pdev, glue); |
18688fbe | 1218 | |
09fc7d22 FB |
1219 | memset(musb_resources, 0x00, sizeof(*musb_resources) * |
1220 | ARRAY_SIZE(musb_resources)); | |
1221 | ||
1222 | musb_resources[0].name = pdev->resource[0].name; | |
1223 | musb_resources[0].start = pdev->resource[0].start; | |
1224 | musb_resources[0].end = pdev->resource[0].end; | |
1225 | musb_resources[0].flags = pdev->resource[0].flags; | |
1226 | ||
1227 | musb_resources[1].name = pdev->resource[1].name; | |
1228 | musb_resources[1].start = pdev->resource[1].start; | |
1229 | musb_resources[1].end = pdev->resource[1].end; | |
1230 | musb_resources[1].flags = pdev->resource[1].flags; | |
1231 | ||
c1f01be4 KVA |
1232 | musb_resources[2].name = pdev->resource[2].name; |
1233 | musb_resources[2].start = pdev->resource[2].start; | |
1234 | musb_resources[2].end = pdev->resource[2].end; | |
1235 | musb_resources[2].flags = pdev->resource[2].flags; | |
1236 | ||
af384875 RK |
1237 | pinfo = tusb_dev_info; |
1238 | pinfo.parent = &pdev->dev; | |
1239 | pinfo.res = musb_resources; | |
1240 | pinfo.num_res = ARRAY_SIZE(musb_resources); | |
1241 | pinfo.data = pdata; | |
1242 | pinfo.size_data = sizeof(*pdata); | |
1243 | ||
1244 | glue->musb = musb = platform_device_register_full(&pinfo); | |
1245 | if (IS_ERR(musb)) { | |
1246 | ret = PTR_ERR(musb); | |
1247 | dev_err(&pdev->dev, "failed to register musb device: %d\n", ret); | |
cdfe35fb | 1248 | return ret; |
18688fbe FB |
1249 | } |
1250 | ||
1251 | return 0; | |
18688fbe FB |
1252 | } |
1253 | ||
fb4e98ab | 1254 | static int tusb_remove(struct platform_device *pdev) |
18688fbe | 1255 | { |
1add75d2 | 1256 | struct tusb6010_glue *glue = platform_get_drvdata(pdev); |
18688fbe | 1257 | |
a81a01f9 | 1258 | platform_device_unregister(glue->musb); |
2f36ff69 | 1259 | usb_phy_generic_unregister(glue->phy); |
18688fbe FB |
1260 | |
1261 | return 0; | |
1262 | } | |
1263 | ||
1264 | static struct platform_driver tusb_driver = { | |
e9e8c85e | 1265 | .probe = tusb_probe, |
7690417d | 1266 | .remove = tusb_remove, |
18688fbe FB |
1267 | .driver = { |
1268 | .name = "musb-tusb", | |
1269 | }, | |
1270 | }; | |
1271 | ||
1272 | MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer"); | |
1273 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); | |
1274 | MODULE_LICENSE("GPL v2"); | |
01380c08 | 1275 | module_platform_driver(tusb_driver); |