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Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface | |
3 | * | |
4 | * Copyright (C) 2006 Nokia Corporation | |
5 | * Tony Lindgren <tony@atomide.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/errno.h> | |
550a7375 FB |
14 | #include <linux/usb.h> |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 17 | #include <linux/slab.h> |
45c3eb7d | 18 | #include <linux/omap-dma.h> |
550a7375 FB |
19 | |
20 | #include "musb_core.h" | |
240a16e2 | 21 | #include "tusb6010.h" |
550a7375 FB |
22 | |
23 | #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data) | |
24 | ||
25 | #define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */ | |
26 | ||
d5e7c864 LV |
27 | #define OMAP24XX_DMA_EXT_DMAREQ0 2 |
28 | #define OMAP24XX_DMA_EXT_DMAREQ1 3 | |
29 | #define OMAP242X_DMA_EXT_DMAREQ2 14 | |
30 | #define OMAP242X_DMA_EXT_DMAREQ3 15 | |
31 | #define OMAP242X_DMA_EXT_DMAREQ4 16 | |
32 | #define OMAP242X_DMA_EXT_DMAREQ5 64 | |
33 | ||
550a7375 FB |
34 | struct tusb_omap_dma_ch { |
35 | struct musb *musb; | |
36 | void __iomem *tbase; | |
37 | unsigned long phys_offset; | |
38 | int epnum; | |
39 | u8 tx; | |
40 | struct musb_hw_ep *hw_ep; | |
41 | ||
42 | int ch; | |
43 | s8 dmareq; | |
44 | s8 sync_dev; | |
45 | ||
46 | struct tusb_omap_dma *tusb_dma; | |
47 | ||
1d0f11b3 | 48 | dma_addr_t dma_addr; |
550a7375 FB |
49 | |
50 | u32 len; | |
51 | u16 packet_sz; | |
52 | u16 transfer_packet_sz; | |
53 | u32 transfer_len; | |
54 | u32 completed_len; | |
55 | }; | |
56 | ||
57 | struct tusb_omap_dma { | |
58 | struct dma_controller controller; | |
550a7375 FB |
59 | void __iomem *tbase; |
60 | ||
61 | int ch; | |
62 | s8 dmareq; | |
63 | s8 sync_dev; | |
64 | unsigned multichannel:1; | |
65 | }; | |
66 | ||
550a7375 FB |
67 | /* |
68 | * Allocate dmareq0 to the current channel unless it's already taken | |
69 | */ | |
70 | static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat) | |
71 | { | |
72 | u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); | |
73 | ||
74 | if (reg != 0) { | |
74c6f3a4 | 75 | dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n", |
550a7375 FB |
76 | chdat->epnum, reg & 0xf); |
77 | return -EAGAIN; | |
78 | } | |
79 | ||
80 | if (chdat->tx) | |
81 | reg = (1 << 4) | chdat->epnum; | |
82 | else | |
83 | reg = chdat->epnum; | |
84 | ||
85 | musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
90 | static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat) | |
91 | { | |
92 | u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); | |
93 | ||
94 | if ((reg & 0xf) != chdat->epnum) { | |
95 | printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n", | |
96 | chdat->epnum, reg & 0xf); | |
97 | return; | |
98 | } | |
99 | musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0); | |
100 | } | |
101 | ||
102 | /* | |
103 | * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in | |
104 | * musb_gadget.c. | |
105 | */ | |
106 | static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data) | |
107 | { | |
108 | struct dma_channel *channel = (struct dma_channel *)data; | |
109 | struct tusb_omap_dma_ch *chdat = to_chdat(channel); | |
110 | struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; | |
111 | struct musb *musb = chdat->musb; | |
1d0f11b3 | 112 | struct device *dev = musb->controller; |
550a7375 FB |
113 | struct musb_hw_ep *hw_ep = chdat->hw_ep; |
114 | void __iomem *ep_conf = hw_ep->conf; | |
115 | void __iomem *mbase = musb->mregs; | |
116 | unsigned long remaining, flags, pio; | |
117 | int ch; | |
118 | ||
119 | spin_lock_irqsave(&musb->lock, flags); | |
120 | ||
121 | if (tusb_dma->multichannel) | |
122 | ch = chdat->ch; | |
123 | else | |
124 | ch = tusb_dma->ch; | |
125 | ||
126 | if (ch_status != OMAP_DMA_BLOCK_IRQ) | |
127 | printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status); | |
128 | ||
5c8a86e1 | 129 | dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n", |
550a7375 FB |
130 | chdat->epnum, chdat->tx ? "tx" : "rx", |
131 | ch, ch_status); | |
132 | ||
133 | if (chdat->tx) | |
134 | remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); | |
135 | else | |
136 | remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); | |
137 | ||
138 | remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining); | |
139 | ||
140 | /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */ | |
141 | if (unlikely(remaining > chdat->transfer_len)) { | |
5c8a86e1 | 142 | dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n", |
550a7375 FB |
143 | chdat->tx ? "tx" : "rx", chdat->ch, |
144 | remaining); | |
145 | remaining = 0; | |
146 | } | |
147 | ||
148 | channel->actual_len = chdat->transfer_len - remaining; | |
149 | pio = chdat->len - channel->actual_len; | |
150 | ||
5c8a86e1 | 151 | dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len); |
550a7375 FB |
152 | |
153 | /* Transfer remaining 1 - 31 bytes */ | |
154 | if (pio > 0 && pio < 32) { | |
155 | u8 *buf; | |
156 | ||
5c8a86e1 | 157 | dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio); |
550a7375 FB |
158 | buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len; |
159 | if (chdat->tx) { | |
1d0f11b3 TL |
160 | dma_unmap_single(dev, chdat->dma_addr, |
161 | chdat->transfer_len, | |
162 | DMA_TO_DEVICE); | |
550a7375 FB |
163 | musb_write_fifo(hw_ep, pio, buf); |
164 | } else { | |
1d0f11b3 TL |
165 | dma_unmap_single(dev, chdat->dma_addr, |
166 | chdat->transfer_len, | |
167 | DMA_FROM_DEVICE); | |
550a7375 | 168 | musb_read_fifo(hw_ep, pio, buf); |
550a7375 FB |
169 | } |
170 | channel->actual_len += pio; | |
171 | } | |
172 | ||
173 | if (!tusb_dma->multichannel) | |
174 | tusb_omap_free_shared_dmareq(chdat); | |
175 | ||
176 | channel->status = MUSB_DMA_STATUS_FREE; | |
177 | ||
178 | /* Handle only RX callbacks here. TX callbacks must be handled based | |
179 | * on the TUSB DMA status interrupt. | |
180 | * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback | |
181 | * interrupt for RX and TX. | |
182 | */ | |
183 | if (!chdat->tx) | |
184 | musb_dma_completion(musb, chdat->epnum, chdat->tx); | |
185 | ||
186 | /* We must terminate short tx transfers manually by setting TXPKTRDY. | |
187 | * REVISIT: This same problem may occur with other MUSB dma as well. | |
188 | * Easy to test with g_ether by pinging the MUSB board with ping -s54. | |
189 | */ | |
190 | if ((chdat->transfer_len < chdat->packet_sz) | |
191 | || (chdat->transfer_len % chdat->packet_sz != 0)) { | |
192 | u16 csr; | |
193 | ||
194 | if (chdat->tx) { | |
5c8a86e1 | 195 | dev_dbg(musb->controller, "terminating short tx packet\n"); |
550a7375 FB |
196 | musb_ep_select(mbase, chdat->epnum); |
197 | csr = musb_readw(hw_ep->regs, MUSB_TXCSR); | |
198 | csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY | |
199 | | MUSB_TXCSR_P_WZC_BITS; | |
200 | musb_writew(hw_ep->regs, MUSB_TXCSR, csr); | |
201 | } | |
202 | } | |
203 | ||
204 | spin_unlock_irqrestore(&musb->lock, flags); | |
205 | } | |
206 | ||
207 | static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz, | |
208 | u8 rndis_mode, dma_addr_t dma_addr, u32 len) | |
209 | { | |
210 | struct tusb_omap_dma_ch *chdat = to_chdat(channel); | |
211 | struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; | |
212 | struct musb *musb = chdat->musb; | |
1d0f11b3 | 213 | struct device *dev = musb->controller; |
550a7375 FB |
214 | struct musb_hw_ep *hw_ep = chdat->hw_ep; |
215 | void __iomem *mbase = musb->mregs; | |
216 | void __iomem *ep_conf = hw_ep->conf; | |
217 | dma_addr_t fifo = hw_ep->fifo_sync; | |
218 | struct omap_dma_channel_params dma_params; | |
219 | u32 dma_remaining; | |
220 | int src_burst, dst_burst; | |
221 | u16 csr; | |
6df2b42f | 222 | u32 psize; |
550a7375 FB |
223 | int ch; |
224 | s8 dmareq; | |
225 | s8 sync_dev; | |
226 | ||
227 | if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz)) | |
228 | return false; | |
229 | ||
230 | /* | |
231 | * HW issue #10: Async dma will eventually corrupt the XFR_SIZE | |
232 | * register which will cause missed DMA interrupt. We could try to | |
233 | * use a timer for the callback, but it is unsafe as the XFR_SIZE | |
234 | * register is corrupt, and we won't know if the DMA worked. | |
235 | */ | |
236 | if (dma_addr & 0x2) | |
237 | return false; | |
238 | ||
239 | /* | |
240 | * Because of HW issue #10, it seems like mixing sync DMA and async | |
241 | * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before | |
242 | * using the channel for DMA. | |
243 | */ | |
244 | if (chdat->tx) | |
245 | dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); | |
246 | else | |
247 | dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); | |
248 | ||
249 | dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining); | |
250 | if (dma_remaining) { | |
5c8a86e1 | 251 | dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n", |
550a7375 FB |
252 | chdat->tx ? "tx" : "rx", chdat->ch, |
253 | dma_remaining); | |
254 | return false; | |
255 | } | |
256 | ||
257 | chdat->transfer_len = len & ~0x1f; | |
258 | ||
259 | if (len < packet_sz) | |
260 | chdat->transfer_packet_sz = chdat->transfer_len; | |
261 | else | |
262 | chdat->transfer_packet_sz = packet_sz; | |
263 | ||
264 | if (tusb_dma->multichannel) { | |
265 | ch = chdat->ch; | |
266 | dmareq = chdat->dmareq; | |
267 | sync_dev = chdat->sync_dev; | |
268 | } else { | |
269 | if (tusb_omap_use_shared_dmareq(chdat) != 0) { | |
5c8a86e1 | 270 | dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum); |
550a7375 FB |
271 | return false; |
272 | } | |
273 | if (tusb_dma->ch < 0) { | |
274 | /* REVISIT: This should get blocked earlier, happens | |
275 | * with MSC ErrorRecoveryTest | |
276 | */ | |
277 | WARN_ON(1); | |
278 | return false; | |
279 | } | |
280 | ||
281 | ch = tusb_dma->ch; | |
282 | dmareq = tusb_dma->dmareq; | |
283 | sync_dev = tusb_dma->sync_dev; | |
284 | omap_set_dma_callback(ch, tusb_omap_dma_cb, channel); | |
285 | } | |
286 | ||
287 | chdat->packet_sz = packet_sz; | |
288 | chdat->len = len; | |
289 | channel->actual_len = 0; | |
1d0f11b3 | 290 | chdat->dma_addr = dma_addr; |
550a7375 FB |
291 | channel->status = MUSB_DMA_STATUS_BUSY; |
292 | ||
293 | /* Since we're recycling dma areas, we need to clean or invalidate */ | |
294 | if (chdat->tx) | |
1d0f11b3 TL |
295 | dma_map_single(dev, phys_to_virt(dma_addr), len, |
296 | DMA_TO_DEVICE); | |
550a7375 | 297 | else |
1d0f11b3 TL |
298 | dma_map_single(dev, phys_to_virt(dma_addr), len, |
299 | DMA_FROM_DEVICE); | |
550a7375 FB |
300 | |
301 | /* Use 16-bit transfer if dma_addr is not 32-bit aligned */ | |
302 | if ((dma_addr & 0x3) == 0) { | |
303 | dma_params.data_type = OMAP_DMA_DATA_TYPE_S32; | |
304 | dma_params.elem_count = 8; /* Elements in frame */ | |
305 | } else { | |
306 | dma_params.data_type = OMAP_DMA_DATA_TYPE_S16; | |
307 | dma_params.elem_count = 16; /* Elements in frame */ | |
308 | fifo = hw_ep->fifo_async; | |
309 | } | |
310 | ||
311 | dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */ | |
312 | ||
3ec08ddf | 313 | dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %pad len: %u(%u) packet_sz: %i(%i)\n", |
550a7375 | 314 | chdat->epnum, chdat->tx ? "tx" : "rx", |
3ec08ddf | 315 | ch, &dma_addr, chdat->transfer_len, len, |
550a7375 FB |
316 | chdat->transfer_packet_sz, packet_sz); |
317 | ||
318 | /* | |
319 | * Prepare omap DMA for transfer | |
320 | */ | |
321 | if (chdat->tx) { | |
322 | dma_params.src_amode = OMAP_DMA_AMODE_POST_INC; | |
323 | dma_params.src_start = (unsigned long)dma_addr; | |
324 | dma_params.src_ei = 0; | |
325 | dma_params.src_fi = 0; | |
326 | ||
327 | dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX; | |
328 | dma_params.dst_start = (unsigned long)fifo; | |
329 | dma_params.dst_ei = 1; | |
330 | dma_params.dst_fi = -31; /* Loop 32 byte window */ | |
331 | ||
332 | dma_params.trigger = sync_dev; | |
333 | dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; | |
334 | dma_params.src_or_dst_synch = 0; /* Dest sync */ | |
335 | ||
336 | src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */ | |
337 | dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */ | |
338 | } else { | |
339 | dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX; | |
340 | dma_params.src_start = (unsigned long)fifo; | |
341 | dma_params.src_ei = 1; | |
342 | dma_params.src_fi = -31; /* Loop 32 byte window */ | |
343 | ||
344 | dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC; | |
345 | dma_params.dst_start = (unsigned long)dma_addr; | |
346 | dma_params.dst_ei = 0; | |
347 | dma_params.dst_fi = 0; | |
348 | ||
349 | dma_params.trigger = sync_dev; | |
350 | dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; | |
351 | dma_params.src_or_dst_synch = 1; /* Source sync */ | |
352 | ||
353 | src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */ | |
354 | dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */ | |
355 | } | |
356 | ||
5c8a86e1 | 357 | dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n", |
550a7375 FB |
358 | chdat->epnum, chdat->tx ? "tx" : "rx", |
359 | (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16, | |
360 | ((dma_addr & 0x3) == 0) ? "sync" : "async", | |
361 | dma_params.src_start, dma_params.dst_start); | |
362 | ||
363 | omap_set_dma_params(ch, &dma_params); | |
364 | omap_set_dma_src_burst_mode(ch, src_burst); | |
365 | omap_set_dma_dest_burst_mode(ch, dst_burst); | |
366 | omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED); | |
367 | ||
368 | /* | |
369 | * Prepare MUSB for DMA transfer | |
370 | */ | |
371 | if (chdat->tx) { | |
372 | musb_ep_select(mbase, chdat->epnum); | |
373 | csr = musb_readw(hw_ep->regs, MUSB_TXCSR); | |
374 | csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB | |
375 | | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE); | |
376 | csr &= ~MUSB_TXCSR_P_UNDERRUN; | |
377 | musb_writew(hw_ep->regs, MUSB_TXCSR, csr); | |
378 | } else { | |
379 | musb_ep_select(mbase, chdat->epnum); | |
380 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); | |
381 | csr |= MUSB_RXCSR_DMAENAB; | |
382 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE); | |
383 | musb_writew(hw_ep->regs, MUSB_RXCSR, | |
384 | csr | MUSB_RXCSR_P_WZC_BITS); | |
385 | } | |
386 | ||
387 | /* | |
388 | * Start DMA transfer | |
389 | */ | |
390 | omap_start_dma(ch); | |
391 | ||
392 | if (chdat->tx) { | |
393 | /* Send transfer_packet_sz packets at a time */ | |
6df2b42f PU |
394 | psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET); |
395 | psize &= ~0x7ff; | |
396 | psize |= chdat->transfer_packet_sz; | |
397 | musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize); | |
550a7375 FB |
398 | |
399 | musb_writel(ep_conf, TUSB_EP_TX_OFFSET, | |
400 | TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); | |
401 | } else { | |
402 | /* Receive transfer_packet_sz packets at a time */ | |
6df2b42f PU |
403 | psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET); |
404 | psize &= ~(0x7ff << 16); | |
405 | psize |= (chdat->transfer_packet_sz << 16); | |
406 | musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize); | |
550a7375 FB |
407 | |
408 | musb_writel(ep_conf, TUSB_EP_RX_OFFSET, | |
409 | TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); | |
410 | } | |
411 | ||
412 | return true; | |
413 | } | |
414 | ||
415 | static int tusb_omap_dma_abort(struct dma_channel *channel) | |
416 | { | |
417 | struct tusb_omap_dma_ch *chdat = to_chdat(channel); | |
418 | struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; | |
419 | ||
420 | if (!tusb_dma->multichannel) { | |
421 | if (tusb_dma->ch >= 0) { | |
422 | omap_stop_dma(tusb_dma->ch); | |
423 | omap_free_dma(tusb_dma->ch); | |
424 | tusb_dma->ch = -1; | |
425 | } | |
426 | ||
427 | tusb_dma->dmareq = -1; | |
428 | tusb_dma->sync_dev = -1; | |
429 | } | |
430 | ||
431 | channel->status = MUSB_DMA_STATUS_FREE; | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
436 | static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat) | |
437 | { | |
438 | u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); | |
439 | int i, dmareq_nr = -1; | |
440 | ||
441 | const int sync_dev[6] = { | |
442 | OMAP24XX_DMA_EXT_DMAREQ0, | |
443 | OMAP24XX_DMA_EXT_DMAREQ1, | |
444 | OMAP242X_DMA_EXT_DMAREQ2, | |
445 | OMAP242X_DMA_EXT_DMAREQ3, | |
446 | OMAP242X_DMA_EXT_DMAREQ4, | |
447 | OMAP242X_DMA_EXT_DMAREQ5, | |
448 | }; | |
449 | ||
450 | for (i = 0; i < MAX_DMAREQ; i++) { | |
451 | int cur = (reg & (0xf << (i * 5))) >> (i * 5); | |
452 | if (cur == 0) { | |
453 | dmareq_nr = i; | |
454 | break; | |
455 | } | |
456 | } | |
457 | ||
458 | if (dmareq_nr == -1) | |
459 | return -EAGAIN; | |
460 | ||
461 | reg |= (chdat->epnum << (dmareq_nr * 5)); | |
462 | if (chdat->tx) | |
463 | reg |= ((1 << 4) << (dmareq_nr * 5)); | |
464 | musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); | |
465 | ||
466 | chdat->dmareq = dmareq_nr; | |
467 | chdat->sync_dev = sync_dev[chdat->dmareq]; | |
468 | ||
469 | return 0; | |
470 | } | |
471 | ||
472 | static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat) | |
473 | { | |
474 | u32 reg; | |
475 | ||
476 | if (!chdat || chdat->dmareq < 0) | |
477 | return; | |
478 | ||
479 | reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); | |
480 | reg &= ~(0x1f << (chdat->dmareq * 5)); | |
481 | musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); | |
482 | ||
483 | chdat->dmareq = -1; | |
484 | chdat->sync_dev = -1; | |
485 | } | |
486 | ||
487 | static struct dma_channel *dma_channel_pool[MAX_DMAREQ]; | |
488 | ||
489 | static struct dma_channel * | |
490 | tusb_omap_dma_allocate(struct dma_controller *c, | |
491 | struct musb_hw_ep *hw_ep, | |
492 | u8 tx) | |
493 | { | |
494 | int ret, i; | |
495 | const char *dev_name; | |
496 | struct tusb_omap_dma *tusb_dma; | |
497 | struct musb *musb; | |
498 | void __iomem *tbase; | |
499 | struct dma_channel *channel = NULL; | |
500 | struct tusb_omap_dma_ch *chdat = NULL; | |
501 | u32 reg; | |
502 | ||
503 | tusb_dma = container_of(c, struct tusb_omap_dma, controller); | |
a96ca0d2 | 504 | musb = tusb_dma->controller.musb; |
550a7375 FB |
505 | tbase = musb->ctrl_base; |
506 | ||
507 | reg = musb_readl(tbase, TUSB_DMA_INT_MASK); | |
508 | if (tx) | |
509 | reg &= ~(1 << hw_ep->epnum); | |
510 | else | |
511 | reg &= ~(1 << (hw_ep->epnum + 15)); | |
512 | musb_writel(tbase, TUSB_DMA_INT_MASK, reg); | |
513 | ||
514 | /* REVISIT: Why does dmareq5 not work? */ | |
515 | if (hw_ep->epnum == 0) { | |
5c8a86e1 | 516 | dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx"); |
550a7375 FB |
517 | return NULL; |
518 | } | |
519 | ||
520 | for (i = 0; i < MAX_DMAREQ; i++) { | |
521 | struct dma_channel *ch = dma_channel_pool[i]; | |
522 | if (ch->status == MUSB_DMA_STATUS_UNKNOWN) { | |
523 | ch->status = MUSB_DMA_STATUS_FREE; | |
524 | channel = ch; | |
525 | chdat = ch->private_data; | |
526 | break; | |
527 | } | |
528 | } | |
529 | ||
530 | if (!channel) | |
531 | return NULL; | |
532 | ||
533 | if (tx) { | |
534 | chdat->tx = 1; | |
535 | dev_name = "TUSB transmit"; | |
536 | } else { | |
537 | chdat->tx = 0; | |
538 | dev_name = "TUSB receive"; | |
539 | } | |
540 | ||
a96ca0d2 | 541 | chdat->musb = tusb_dma->controller.musb; |
550a7375 FB |
542 | chdat->tbase = tusb_dma->tbase; |
543 | chdat->hw_ep = hw_ep; | |
544 | chdat->epnum = hw_ep->epnum; | |
545 | chdat->dmareq = -1; | |
546 | chdat->completed_len = 0; | |
547 | chdat->tusb_dma = tusb_dma; | |
548 | ||
549 | channel->max_len = 0x7fffffff; | |
550 | channel->desired_mode = 0; | |
551 | channel->actual_len = 0; | |
552 | ||
553 | if (tusb_dma->multichannel) { | |
554 | ret = tusb_omap_dma_allocate_dmareq(chdat); | |
555 | if (ret != 0) | |
556 | goto free_dmareq; | |
557 | ||
558 | ret = omap_request_dma(chdat->sync_dev, dev_name, | |
559 | tusb_omap_dma_cb, channel, &chdat->ch); | |
560 | if (ret != 0) | |
561 | goto free_dmareq; | |
562 | } else if (tusb_dma->ch == -1) { | |
563 | tusb_dma->dmareq = 0; | |
564 | tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0; | |
565 | ||
566 | /* Callback data gets set later in the shared dmareq case */ | |
567 | ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared", | |
568 | tusb_omap_dma_cb, NULL, &tusb_dma->ch); | |
569 | if (ret != 0) | |
570 | goto free_dmareq; | |
571 | ||
572 | chdat->dmareq = -1; | |
573 | chdat->ch = -1; | |
574 | } | |
575 | ||
5c8a86e1 | 576 | dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n", |
550a7375 FB |
577 | chdat->epnum, |
578 | chdat->tx ? "tx" : "rx", | |
579 | chdat->ch >= 0 ? "dedicated" : "shared", | |
580 | chdat->ch >= 0 ? chdat->ch : tusb_dma->ch, | |
581 | chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq, | |
582 | chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev); | |
583 | ||
584 | return channel; | |
585 | ||
586 | free_dmareq: | |
587 | tusb_omap_dma_free_dmareq(chdat); | |
588 | ||
5c8a86e1 | 589 | dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum); |
550a7375 FB |
590 | channel->status = MUSB_DMA_STATUS_UNKNOWN; |
591 | ||
592 | return NULL; | |
593 | } | |
594 | ||
595 | static void tusb_omap_dma_release(struct dma_channel *channel) | |
596 | { | |
597 | struct tusb_omap_dma_ch *chdat = to_chdat(channel); | |
598 | struct musb *musb = chdat->musb; | |
599 | void __iomem *tbase = musb->ctrl_base; | |
600 | u32 reg; | |
601 | ||
5c8a86e1 | 602 | dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch); |
550a7375 FB |
603 | |
604 | reg = musb_readl(tbase, TUSB_DMA_INT_MASK); | |
605 | if (chdat->tx) | |
606 | reg |= (1 << chdat->epnum); | |
607 | else | |
608 | reg |= (1 << (chdat->epnum + 15)); | |
609 | musb_writel(tbase, TUSB_DMA_INT_MASK, reg); | |
610 | ||
611 | reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR); | |
612 | if (chdat->tx) | |
613 | reg |= (1 << chdat->epnum); | |
614 | else | |
615 | reg |= (1 << (chdat->epnum + 15)); | |
616 | musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg); | |
617 | ||
618 | channel->status = MUSB_DMA_STATUS_UNKNOWN; | |
619 | ||
620 | if (chdat->ch >= 0) { | |
621 | omap_stop_dma(chdat->ch); | |
622 | omap_free_dma(chdat->ch); | |
623 | chdat->ch = -1; | |
624 | } | |
625 | ||
626 | if (chdat->dmareq >= 0) | |
627 | tusb_omap_dma_free_dmareq(chdat); | |
628 | ||
629 | channel = NULL; | |
630 | } | |
631 | ||
7f6283ed | 632 | void tusb_dma_controller_destroy(struct dma_controller *c) |
550a7375 FB |
633 | { |
634 | struct tusb_omap_dma *tusb_dma; | |
635 | int i; | |
636 | ||
637 | tusb_dma = container_of(c, struct tusb_omap_dma, controller); | |
638 | for (i = 0; i < MAX_DMAREQ; i++) { | |
639 | struct dma_channel *ch = dma_channel_pool[i]; | |
640 | if (ch) { | |
641 | kfree(ch->private_data); | |
642 | kfree(ch); | |
643 | } | |
644 | } | |
645 | ||
94089d56 | 646 | if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0) |
550a7375 FB |
647 | omap_free_dma(tusb_dma->ch); |
648 | ||
649 | kfree(tusb_dma); | |
650 | } | |
7f6283ed | 651 | EXPORT_SYMBOL_GPL(tusb_dma_controller_destroy); |
550a7375 | 652 | |
7f6283ed TL |
653 | struct dma_controller * |
654 | tusb_dma_controller_create(struct musb *musb, void __iomem *base) | |
550a7375 FB |
655 | { |
656 | void __iomem *tbase = musb->ctrl_base; | |
657 | struct tusb_omap_dma *tusb_dma; | |
658 | int i; | |
659 | ||
660 | /* REVISIT: Get dmareq lines used from board-*.c */ | |
661 | ||
662 | musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff); | |
663 | musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0); | |
664 | ||
665 | musb_writel(tbase, TUSB_DMA_REQ_CONF, | |
666 | TUSB_DMA_REQ_CONF_BURST_SIZE(2) | |
667 | | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | |
668 | | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); | |
669 | ||
670 | tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL); | |
671 | if (!tusb_dma) | |
c88ba39c | 672 | goto out; |
550a7375 | 673 | |
a96ca0d2 | 674 | tusb_dma->controller.musb = musb; |
550a7375 FB |
675 | tusb_dma->tbase = musb->ctrl_base; |
676 | ||
677 | tusb_dma->ch = -1; | |
678 | tusb_dma->dmareq = -1; | |
679 | tusb_dma->sync_dev = -1; | |
680 | ||
550a7375 FB |
681 | tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate; |
682 | tusb_dma->controller.channel_release = tusb_omap_dma_release; | |
683 | tusb_dma->controller.channel_program = tusb_omap_dma_program; | |
684 | tusb_dma->controller.channel_abort = tusb_omap_dma_abort; | |
685 | ||
7751b6fb | 686 | if (musb->tusb_revision >= TUSB_REV_30) |
550a7375 FB |
687 | tusb_dma->multichannel = 1; |
688 | ||
689 | for (i = 0; i < MAX_DMAREQ; i++) { | |
690 | struct dma_channel *ch; | |
691 | struct tusb_omap_dma_ch *chdat; | |
692 | ||
693 | ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL); | |
694 | if (!ch) | |
695 | goto cleanup; | |
696 | ||
697 | dma_channel_pool[i] = ch; | |
698 | ||
699 | chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL); | |
700 | if (!chdat) | |
701 | goto cleanup; | |
702 | ||
703 | ch->status = MUSB_DMA_STATUS_UNKNOWN; | |
704 | ch->private_data = chdat; | |
705 | } | |
706 | ||
707 | return &tusb_dma->controller; | |
708 | ||
709 | cleanup: | |
7f6283ed | 710 | musb_dma_controller_destroy(&tusb_dma->controller); |
c88ba39c | 711 | out: |
550a7375 FB |
712 | return NULL; |
713 | } | |
7f6283ed | 714 | EXPORT_SYMBOL_GPL(tusb_dma_controller_create); |