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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0+ |
fb3967b9 | 2 | /* Copyright (C) 2007,2008 Freescale Semiconductor, Inc. */ |
0807c500 | 3 | |
5653668c | 4 | #include <linux/usb/otg-fsm.h> |
0807c500 LY |
5 | #include <linux/usb/otg.h> |
6 | #include <linux/ioctl.h> | |
7 | ||
8 | /* USB Command Register Bit Masks */ | |
9 | #define USB_CMD_RUN_STOP (0x1<<0) | |
10 | #define USB_CMD_CTRL_RESET (0x1<<1) | |
11 | #define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4) | |
12 | #define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5) | |
13 | #define USB_CMD_INT_AA_DOORBELL (0x1<<6) | |
14 | #define USB_CMD_ASP (0x3<<8) | |
15 | #define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11) | |
16 | #define USB_CMD_SUTW (0x1<<13) | |
17 | #define USB_CMD_ATDTW (0x1<<14) | |
18 | #define USB_CMD_ITC (0xFF<<16) | |
19 | ||
20 | /* bit 15,3,2 are frame list size */ | |
21 | #define USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2) | |
22 | #define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2) | |
23 | #define USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2) | |
24 | #define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2) | |
25 | #define USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2) | |
26 | #define USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2) | |
27 | #define USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2) | |
28 | #define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2) | |
29 | ||
30 | /* bit 9-8 are async schedule park mode count */ | |
31 | #define USB_CMD_ASP_00 (0x0<<8) | |
32 | #define USB_CMD_ASP_01 (0x1<<8) | |
33 | #define USB_CMD_ASP_10 (0x2<<8) | |
34 | #define USB_CMD_ASP_11 (0x3<<8) | |
35 | #define USB_CMD_ASP_BIT_POS (8) | |
36 | ||
37 | /* bit 23-16 are interrupt threshold control */ | |
38 | #define USB_CMD_ITC_NO_THRESHOLD (0x00<<16) | |
39 | #define USB_CMD_ITC_1_MICRO_FRM (0x01<<16) | |
40 | #define USB_CMD_ITC_2_MICRO_FRM (0x02<<16) | |
41 | #define USB_CMD_ITC_4_MICRO_FRM (0x04<<16) | |
42 | #define USB_CMD_ITC_8_MICRO_FRM (0x08<<16) | |
43 | #define USB_CMD_ITC_16_MICRO_FRM (0x10<<16) | |
44 | #define USB_CMD_ITC_32_MICRO_FRM (0x20<<16) | |
45 | #define USB_CMD_ITC_64_MICRO_FRM (0x40<<16) | |
46 | #define USB_CMD_ITC_BIT_POS (16) | |
47 | ||
48 | /* USB Status Register Bit Masks */ | |
49 | #define USB_STS_INT (0x1<<0) | |
50 | #define USB_STS_ERR (0x1<<1) | |
51 | #define USB_STS_PORT_CHANGE (0x1<<2) | |
52 | #define USB_STS_FRM_LST_ROLL (0x1<<3) | |
53 | #define USB_STS_SYS_ERR (0x1<<4) | |
54 | #define USB_STS_IAA (0x1<<5) | |
55 | #define USB_STS_RESET_RECEIVED (0x1<<6) | |
56 | #define USB_STS_SOF (0x1<<7) | |
57 | #define USB_STS_DCSUSPEND (0x1<<8) | |
58 | #define USB_STS_HC_HALTED (0x1<<12) | |
59 | #define USB_STS_RCL (0x1<<13) | |
60 | #define USB_STS_PERIODIC_SCHEDULE (0x1<<14) | |
61 | #define USB_STS_ASYNC_SCHEDULE (0x1<<15) | |
62 | ||
63 | /* USB Interrupt Enable Register Bit Masks */ | |
64 | #define USB_INTR_INT_EN (0x1<<0) | |
65 | #define USB_INTR_ERR_INT_EN (0x1<<1) | |
66 | #define USB_INTR_PC_DETECT_EN (0x1<<2) | |
67 | #define USB_INTR_FRM_LST_ROLL_EN (0x1<<3) | |
68 | #define USB_INTR_SYS_ERR_EN (0x1<<4) | |
69 | #define USB_INTR_ASYN_ADV_EN (0x1<<5) | |
70 | #define USB_INTR_RESET_EN (0x1<<6) | |
71 | #define USB_INTR_SOF_EN (0x1<<7) | |
72 | #define USB_INTR_DEVICE_SUSPEND (0x1<<8) | |
73 | ||
74 | /* Device Address bit masks */ | |
75 | #define USB_DEVICE_ADDRESS_MASK (0x7F<<25) | |
76 | #define USB_DEVICE_ADDRESS_BIT_POS (25) | |
77 | /* PORTSC Register Bit Masks,Only one PORT in OTG mode*/ | |
78 | #define PORTSC_CURRENT_CONNECT_STATUS (0x1<<0) | |
79 | #define PORTSC_CONNECT_STATUS_CHANGE (0x1<<1) | |
80 | #define PORTSC_PORT_ENABLE (0x1<<2) | |
81 | #define PORTSC_PORT_EN_DIS_CHANGE (0x1<<3) | |
82 | #define PORTSC_OVER_CURRENT_ACT (0x1<<4) | |
83 | #define PORTSC_OVER_CUURENT_CHG (0x1<<5) | |
84 | #define PORTSC_PORT_FORCE_RESUME (0x1<<6) | |
85 | #define PORTSC_PORT_SUSPEND (0x1<<7) | |
86 | #define PORTSC_PORT_RESET (0x1<<8) | |
87 | #define PORTSC_LINE_STATUS_BITS (0x3<<10) | |
88 | #define PORTSC_PORT_POWER (0x1<<12) | |
89 | #define PORTSC_PORT_INDICTOR_CTRL (0x3<<14) | |
90 | #define PORTSC_PORT_TEST_CTRL (0xF<<16) | |
91 | #define PORTSC_WAKE_ON_CONNECT_EN (0x1<<20) | |
92 | #define PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21) | |
93 | #define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22) | |
94 | #define PORTSC_PHY_LOW_POWER_SPD (0x1<<23) | |
95 | #define PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24) | |
96 | #define PORTSC_PORT_SPEED_MASK (0x3<<26) | |
97 | #define PORTSC_TRANSCEIVER_WIDTH (0x1<<28) | |
98 | #define PORTSC_PHY_TYPE_SEL (0x3<<30) | |
99 | /* bit 11-10 are line status */ | |
100 | #define PORTSC_LINE_STATUS_SE0 (0x0<<10) | |
101 | #define PORTSC_LINE_STATUS_JSTATE (0x1<<10) | |
102 | #define PORTSC_LINE_STATUS_KSTATE (0x2<<10) | |
103 | #define PORTSC_LINE_STATUS_UNDEF (0x3<<10) | |
104 | #define PORTSC_LINE_STATUS_BIT_POS (10) | |
105 | ||
106 | /* bit 15-14 are port indicator control */ | |
107 | #define PORTSC_PIC_OFF (0x0<<14) | |
108 | #define PORTSC_PIC_AMBER (0x1<<14) | |
109 | #define PORTSC_PIC_GREEN (0x2<<14) | |
110 | #define PORTSC_PIC_UNDEF (0x3<<14) | |
111 | #define PORTSC_PIC_BIT_POS (14) | |
112 | ||
113 | /* bit 19-16 are port test control */ | |
114 | #define PORTSC_PTC_DISABLE (0x0<<16) | |
115 | #define PORTSC_PTC_JSTATE (0x1<<16) | |
116 | #define PORTSC_PTC_KSTATE (0x2<<16) | |
117 | #define PORTSC_PTC_SEQNAK (0x3<<16) | |
118 | #define PORTSC_PTC_PACKET (0x4<<16) | |
119 | #define PORTSC_PTC_FORCE_EN (0x5<<16) | |
120 | #define PORTSC_PTC_BIT_POS (16) | |
121 | ||
122 | /* bit 27-26 are port speed */ | |
123 | #define PORTSC_PORT_SPEED_FULL (0x0<<26) | |
124 | #define PORTSC_PORT_SPEED_LOW (0x1<<26) | |
125 | #define PORTSC_PORT_SPEED_HIGH (0x2<<26) | |
126 | #define PORTSC_PORT_SPEED_UNDEF (0x3<<26) | |
127 | #define PORTSC_SPEED_BIT_POS (26) | |
128 | ||
129 | /* bit 28 is parallel transceiver width for UTMI interface */ | |
130 | #define PORTSC_PTW (0x1<<28) | |
131 | #define PORTSC_PTW_8BIT (0x0<<28) | |
132 | #define PORTSC_PTW_16BIT (0x1<<28) | |
133 | ||
134 | /* bit 31-30 are port transceiver select */ | |
135 | #define PORTSC_PTS_UTMI (0x0<<30) | |
136 | #define PORTSC_PTS_ULPI (0x2<<30) | |
137 | #define PORTSC_PTS_FSLS_SERIAL (0x3<<30) | |
138 | #define PORTSC_PTS_BIT_POS (30) | |
139 | ||
140 | #define PORTSC_W1C_BITS \ | |
141 | (PORTSC_CONNECT_STATUS_CHANGE | \ | |
142 | PORTSC_PORT_EN_DIS_CHANGE | \ | |
143 | PORTSC_OVER_CUURENT_CHG) | |
144 | ||
145 | /* OTG Status Control Register Bit Masks */ | |
146 | #define OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0) | |
147 | #define OTGSC_CTRL_VBUS_CHARGE (0x1<<1) | |
148 | #define OTGSC_CTRL_OTG_TERMINATION (0x1<<3) | |
149 | #define OTGSC_CTRL_DATA_PULSING (0x1<<4) | |
150 | #define OTGSC_CTRL_ID_PULL_EN (0x1<<5) | |
151 | #define OTGSC_HA_DATA_PULSE (0x1<<6) | |
152 | #define OTGSC_HA_BA (0x1<<7) | |
153 | #define OTGSC_STS_USB_ID (0x1<<8) | |
154 | #define OTGSC_STS_A_VBUS_VALID (0x1<<9) | |
155 | #define OTGSC_STS_A_SESSION_VALID (0x1<<10) | |
156 | #define OTGSC_STS_B_SESSION_VALID (0x1<<11) | |
157 | #define OTGSC_STS_B_SESSION_END (0x1<<12) | |
158 | #define OTGSC_STS_1MS_TOGGLE (0x1<<13) | |
159 | #define OTGSC_STS_DATA_PULSING (0x1<<14) | |
160 | #define OTGSC_INTSTS_USB_ID (0x1<<16) | |
161 | #define OTGSC_INTSTS_A_VBUS_VALID (0x1<<17) | |
162 | #define OTGSC_INTSTS_A_SESSION_VALID (0x1<<18) | |
163 | #define OTGSC_INTSTS_B_SESSION_VALID (0x1<<19) | |
164 | #define OTGSC_INTSTS_B_SESSION_END (0x1<<20) | |
165 | #define OTGSC_INTSTS_1MS (0x1<<21) | |
166 | #define OTGSC_INTSTS_DATA_PULSING (0x1<<22) | |
167 | #define OTGSC_INTR_USB_ID_EN (0x1<<24) | |
168 | #define OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25) | |
169 | #define OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26) | |
170 | #define OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27) | |
171 | #define OTGSC_INTR_B_SESSION_END_EN (0x1<<28) | |
172 | #define OTGSC_INTR_1MS_TIMER_EN (0x1<<29) | |
173 | #define OTGSC_INTR_DATA_PULSING_EN (0x1<<30) | |
174 | #define OTGSC_INTSTS_MASK (0x00ff0000) | |
175 | ||
176 | /* USB MODE Register Bit Masks */ | |
177 | #define USB_MODE_CTRL_MODE_IDLE (0x0<<0) | |
178 | #define USB_MODE_CTRL_MODE_DEVICE (0x2<<0) | |
179 | #define USB_MODE_CTRL_MODE_HOST (0x3<<0) | |
180 | #define USB_MODE_CTRL_MODE_RSV (0x1<<0) | |
181 | #define USB_MODE_SETUP_LOCK_OFF (0x1<<3) | |
182 | #define USB_MODE_STREAM_DISABLE (0x1<<4) | |
183 | #define USB_MODE_ES (0x1<<2) /* Endian Select */ | |
184 | ||
185 | /* control Register Bit Masks */ | |
186 | #define USB_CTRL_IOENB (0x1<<2) | |
187 | #define USB_CTRL_ULPI_INT0EN (0x1<<0) | |
188 | ||
189 | /* BCSR5 */ | |
190 | #define BCSR5_INT_USB (0x02) | |
191 | ||
192 | /* USB module clk cfg */ | |
193 | #define SCCR_OFFS (0xA08) | |
194 | #define SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */ | |
195 | #define SCCR_USB_MPHCM_11 (0x00c00000) | |
196 | #define SCCR_USB_MPHCM_01 (0x00400000) | |
197 | #define SCCR_USB_MPHCM_10 (0x00800000) | |
198 | #define SCCR_USB_DRCM_11 (0x00300000) | |
199 | #define SCCR_USB_DRCM_01 (0x00100000) | |
200 | #define SCCR_USB_DRCM_10 (0x00200000) | |
201 | ||
202 | #define SICRL_OFFS (0x114) | |
203 | #define SICRL_USB0 (0x40000000) | |
204 | #define SICRL_USB1 (0x20000000) | |
205 | ||
206 | #define SICRH_OFFS (0x118) | |
207 | #define SICRH_USB_UTMI (0x00020000) | |
208 | ||
209 | /* OTG interrupt enable bit masks */ | |
210 | #define OTGSC_INTERRUPT_ENABLE_BITS_MASK \ | |
211 | (OTGSC_INTR_USB_ID_EN | \ | |
212 | OTGSC_INTR_1MS_TIMER_EN | \ | |
213 | OTGSC_INTR_A_VBUS_VALID_EN | \ | |
214 | OTGSC_INTR_A_SESSION_VALID_EN | \ | |
215 | OTGSC_INTR_B_SESSION_VALID_EN | \ | |
216 | OTGSC_INTR_B_SESSION_END_EN | \ | |
217 | OTGSC_INTR_DATA_PULSING_EN) | |
218 | ||
219 | /* OTG interrupt status bit masks */ | |
220 | #define OTGSC_INTERRUPT_STATUS_BITS_MASK \ | |
221 | (OTGSC_INTSTS_USB_ID | \ | |
222 | OTGSC_INTR_1MS_TIMER_EN | \ | |
223 | OTGSC_INTSTS_A_VBUS_VALID | \ | |
224 | OTGSC_INTSTS_A_SESSION_VALID | \ | |
225 | OTGSC_INTSTS_B_SESSION_VALID | \ | |
226 | OTGSC_INTSTS_B_SESSION_END | \ | |
227 | OTGSC_INTSTS_DATA_PULSING) | |
228 | ||
229 | /* | |
230 | * A-DEVICE timing constants | |
231 | */ | |
232 | ||
233 | /* Wait for VBUS Rise */ | |
234 | #define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */ | |
235 | ||
236 | /* Wait for B-Connect */ | |
237 | #define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2 | |
238 | * This is only used to get out of | |
239 | * OTG_STATE_A_WAIT_BCON state if there was | |
240 | * no connection for these many milliseconds | |
241 | */ | |
242 | ||
243 | /* A-Idle to B-Disconnect */ | |
244 | /* It is necessary for this timer to be more than 750 ms because of a bug in OPT | |
245 | * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated | |
246 | * in the test description | |
247 | */ | |
248 | #define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */ | |
249 | ||
250 | /* B-Idle to A-Disconnect */ | |
251 | #define TA_BIDL_ADIS (12) /* 3 to 200 ms */ | |
252 | ||
253 | /* B-device timing constants */ | |
254 | ||
255 | ||
256 | /* Data-Line Pulse Time*/ | |
257 | #define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */ | |
258 | #define TB_DATA_PLS_MIN (5) /* minimum 5 ms */ | |
259 | #define TB_DATA_PLS_MAX (10) /* maximum 10 ms */ | |
260 | ||
261 | /* SRP Initiate Time */ | |
262 | #define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */ | |
263 | ||
264 | /* SRP Fail Time */ | |
265 | #define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/ | |
266 | ||
267 | /* SRP result wait time */ | |
268 | #define TB_SRP_WAIT (60) | |
269 | ||
270 | /* VBus time */ | |
271 | #define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */ | |
272 | ||
273 | /* Discharge time */ | |
274 | /* This time should be less than 10ms. It varies from system to system. */ | |
275 | #define TB_VBUS_DSCHRG (8) | |
276 | ||
277 | /* A-SE0 to B-Reset */ | |
278 | #define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */ | |
279 | ||
280 | /* A bus suspend timer before we can switch to b_wait_aconn */ | |
281 | #define TB_A_SUSPEND (7) | |
282 | #define TB_BUS_RESUME (12) | |
283 | ||
284 | /* SE0 Time Before SRP */ | |
285 | #define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */ | |
286 | ||
e5ba1c02 | 287 | #define SET_OTG_STATE(phy, newstate) ((phy)->otg->state = newstate) |
0807c500 LY |
288 | |
289 | struct usb_dr_mmap { | |
290 | /* Capability register */ | |
291 | u8 res1[256]; | |
292 | u16 caplength; /* Capability Register Length */ | |
293 | u16 hciversion; /* Host Controller Interface Version */ | |
294 | u32 hcsparams; /* Host Controller Structual Parameters */ | |
295 | u32 hccparams; /* Host Controller Capability Parameters */ | |
296 | u8 res2[20]; | |
297 | u32 dciversion; /* Device Controller Interface Version */ | |
298 | u32 dccparams; /* Device Controller Capability Parameters */ | |
299 | u8 res3[24]; | |
300 | /* Operation register */ | |
301 | u32 usbcmd; /* USB Command Register */ | |
302 | u32 usbsts; /* USB Status Register */ | |
303 | u32 usbintr; /* USB Interrupt Enable Register */ | |
304 | u32 frindex; /* Frame Index Register */ | |
305 | u8 res4[4]; | |
306 | u32 deviceaddr; /* Device Address */ | |
307 | u32 endpointlistaddr; /* Endpoint List Address Register */ | |
308 | u8 res5[4]; | |
309 | u32 burstsize; /* Master Interface Data Burst Size Register */ | |
310 | u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */ | |
311 | u8 res6[8]; | |
312 | u32 ulpiview; /* ULPI register access */ | |
313 | u8 res7[12]; | |
314 | u32 configflag; /* Configure Flag Register */ | |
315 | u32 portsc; /* Port 1 Status and Control Register */ | |
316 | u8 res8[28]; | |
317 | u32 otgsc; /* On-The-Go Status and Control */ | |
318 | u32 usbmode; /* USB Mode Register */ | |
319 | u32 endptsetupstat; /* Endpoint Setup Status Register */ | |
320 | u32 endpointprime; /* Endpoint Initialization Register */ | |
321 | u32 endptflush; /* Endpoint Flush Register */ | |
322 | u32 endptstatus; /* Endpoint Status Register */ | |
323 | u32 endptcomplete; /* Endpoint Complete Register */ | |
324 | u32 endptctrl[6]; /* Endpoint Control Registers */ | |
325 | u8 res9[552]; | |
326 | u32 snoop1; | |
327 | u32 snoop2; | |
328 | u32 age_cnt_thresh; /* Age Count Threshold Register */ | |
329 | u32 pri_ctrl; /* Priority Control Register */ | |
330 | u32 si_ctrl; /* System Interface Control Register */ | |
331 | u8 res10[236]; | |
332 | u32 control; /* General Purpose Control Register */ | |
333 | }; | |
334 | ||
335 | struct fsl_otg_timer { | |
336 | unsigned long expires; /* Number of count increase to timeout */ | |
337 | unsigned long count; /* Tick counter */ | |
338 | void (*function)(unsigned long); /* Timeout function */ | |
339 | unsigned long data; /* Data passed to function */ | |
340 | struct list_head list; | |
341 | }; | |
342 | ||
343 | inline struct fsl_otg_timer *otg_timer_initializer | |
344 | (void (*function)(unsigned long), unsigned long expires, unsigned long data) | |
345 | { | |
346 | struct fsl_otg_timer *timer; | |
347 | ||
348 | timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL); | |
349 | if (!timer) | |
350 | return NULL; | |
351 | timer->function = function; | |
352 | timer->expires = expires; | |
353 | timer->data = data; | |
354 | return timer; | |
355 | } | |
356 | ||
357 | struct fsl_otg { | |
7e062c0f | 358 | struct usb_phy phy; |
0807c500 LY |
359 | struct otg_fsm fsm; |
360 | struct usb_dr_mmap *dr_mem_map; | |
361 | struct delayed_work otg_event; | |
362 | ||
363 | /* used for usb host */ | |
364 | struct work_struct work_wq; | |
365 | u8 host_working; | |
366 | ||
367 | int irq; | |
368 | }; | |
369 | ||
370 | struct fsl_otg_config { | |
371 | u8 otg_port; | |
372 | }; | |
373 | ||
374 | /* For SRP and HNP handle */ | |
375 | #define FSL_OTG_MAJOR 240 | |
376 | #define FSL_OTG_NAME "fsl-usb2-otg" | |
377 | /* Command to OTG driver ioctl */ | |
378 | #define OTG_IOCTL_MAGIC FSL_OTG_MAJOR | |
379 | /* if otg work as host, it should return 1, otherwise return 0 */ | |
380 | #define GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int) | |
381 | #define SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int) | |
382 | #define SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int) | |
383 | #define SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int) | |
384 | #define SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int) | |
385 | #define GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int) | |
386 | #define GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int) | |
387 | #define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int) | |
388 | #define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int) | |
389 | ||
da8cc167 AT |
390 | void fsl_otg_add_timer(struct otg_fsm *fsm, void *timer); |
391 | void fsl_otg_del_timer(struct otg_fsm *fsm, void *timer); | |
0807c500 | 392 | void fsl_otg_pulse_vbus(void); |