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d860852e | 1 | /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. |
e0c201f3 PK |
2 | * |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
15 | * 02110-1301, USA. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/uaccess.h> | |
30 | #include <linux/debugfs.h> | |
31 | #include <linux/seq_file.h> | |
87c0104a | 32 | #include <linux/pm_runtime.h> |
8364f9af II |
33 | #include <linux/of.h> |
34 | #include <linux/of_device.h> | |
a2734543 | 35 | #include <linux/reset.h> |
e0c201f3 PK |
36 | |
37 | #include <linux/usb.h> | |
38 | #include <linux/usb/otg.h> | |
8364f9af | 39 | #include <linux/usb/of.h> |
e0c201f3 PK |
40 | #include <linux/usb/ulpi.h> |
41 | #include <linux/usb/gadget.h> | |
42 | #include <linux/usb/hcd.h> | |
43 | #include <linux/usb/msm_hsusb.h> | |
44 | #include <linux/usb/msm_hsusb_hw.h> | |
11aa5c47 | 45 | #include <linux/regulator/consumer.h> |
e0c201f3 | 46 | |
e0c201f3 PK |
47 | #define MSM_USB_BASE (motg->regs) |
48 | #define DRIVER_NAME "msm_otg" | |
49 | ||
50 | #define ULPI_IO_TIMEOUT_USEC (10 * 1000) | |
d69c6f5d | 51 | #define LINK_RESET_TIMEOUT_USEC (250 * 1000) |
11aa5c47 A |
52 | |
53 | #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */ | |
54 | #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */ | |
55 | #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */ | |
56 | #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */ | |
57 | ||
58 | #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */ | |
59 | #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */ | |
60 | #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */ | |
61 | #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */ | |
62 | ||
63 | #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */ | |
64 | #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */ | |
65 | ||
11aa5c47 A |
66 | static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init) |
67 | { | |
68 | int ret = 0; | |
69 | ||
70 | if (init) { | |
37cfdaf7 | 71 | ret = regulator_set_voltage(motg->vddcx, |
11aa5c47 A |
72 | USB_PHY_VDD_DIG_VOL_MIN, |
73 | USB_PHY_VDD_DIG_VOL_MAX); | |
74 | if (ret) { | |
3aca0fa9 | 75 | dev_err(motg->phy.dev, "Cannot set vddcx voltage\n"); |
11aa5c47 A |
76 | return ret; |
77 | } | |
78 | ||
37cfdaf7 | 79 | ret = regulator_enable(motg->vddcx); |
6b99c68e | 80 | if (ret) |
1d4c9293 | 81 | dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n"); |
11aa5c47 | 82 | } else { |
37cfdaf7 | 83 | ret = regulator_set_voltage(motg->vddcx, 0, |
7b521fcb | 84 | USB_PHY_VDD_DIG_VOL_MAX); |
e99c4309 | 85 | if (ret) |
3aca0fa9 | 86 | dev_err(motg->phy.dev, "Cannot set vddcx voltage\n"); |
37cfdaf7 | 87 | ret = regulator_disable(motg->vddcx); |
11aa5c47 | 88 | if (ret) |
1d4c9293 | 89 | dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n"); |
11aa5c47 A |
90 | } |
91 | ||
92 | return ret; | |
93 | } | |
94 | ||
95 | static int msm_hsusb_ldo_init(struct msm_otg *motg, int init) | |
96 | { | |
97 | int rc = 0; | |
98 | ||
99 | if (init) { | |
37cfdaf7 | 100 | rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN, |
11aa5c47 A |
101 | USB_PHY_3P3_VOL_MAX); |
102 | if (rc) { | |
3aca0fa9 | 103 | dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n"); |
6b99c68e | 104 | goto exit; |
11aa5c47 | 105 | } |
37cfdaf7 | 106 | rc = regulator_enable(motg->v3p3); |
11aa5c47 | 107 | if (rc) { |
1d4c9293 | 108 | dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n"); |
6b99c68e | 109 | goto exit; |
11aa5c47 | 110 | } |
37cfdaf7 | 111 | rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN, |
11aa5c47 A |
112 | USB_PHY_1P8_VOL_MAX); |
113 | if (rc) { | |
3aca0fa9 | 114 | dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n"); |
6b99c68e | 115 | goto disable_3p3; |
11aa5c47 | 116 | } |
37cfdaf7 | 117 | rc = regulator_enable(motg->v1p8); |
11aa5c47 | 118 | if (rc) { |
1d4c9293 | 119 | dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n"); |
6b99c68e | 120 | goto disable_3p3; |
11aa5c47 A |
121 | } |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
37cfdaf7 | 126 | regulator_disable(motg->v1p8); |
11aa5c47 | 127 | disable_3p3: |
37cfdaf7 | 128 | regulator_disable(motg->v3p3); |
6b99c68e | 129 | exit: |
11aa5c47 A |
130 | return rc; |
131 | } | |
132 | ||
37cfdaf7 | 133 | static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on) |
11aa5c47 A |
134 | { |
135 | int ret = 0; | |
136 | ||
11aa5c47 | 137 | if (on) { |
37cfdaf7 | 138 | ret = regulator_set_optimum_mode(motg->v1p8, |
11aa5c47 A |
139 | USB_PHY_1P8_HPM_LOAD); |
140 | if (ret < 0) { | |
3aca0fa9 | 141 | pr_err("Could not set HPM for v1p8\n"); |
11aa5c47 A |
142 | return ret; |
143 | } | |
37cfdaf7 | 144 | ret = regulator_set_optimum_mode(motg->v3p3, |
11aa5c47 A |
145 | USB_PHY_3P3_HPM_LOAD); |
146 | if (ret < 0) { | |
3aca0fa9 | 147 | pr_err("Could not set HPM for v3p3\n"); |
37cfdaf7 | 148 | regulator_set_optimum_mode(motg->v1p8, |
11aa5c47 A |
149 | USB_PHY_1P8_LPM_LOAD); |
150 | return ret; | |
151 | } | |
152 | } else { | |
37cfdaf7 | 153 | ret = regulator_set_optimum_mode(motg->v1p8, |
11aa5c47 A |
154 | USB_PHY_1P8_LPM_LOAD); |
155 | if (ret < 0) | |
3aca0fa9 | 156 | pr_err("Could not set LPM for v1p8\n"); |
37cfdaf7 | 157 | ret = regulator_set_optimum_mode(motg->v3p3, |
11aa5c47 A |
158 | USB_PHY_3P3_LPM_LOAD); |
159 | if (ret < 0) | |
3aca0fa9 | 160 | pr_err("Could not set LPM for v3p3\n"); |
11aa5c47 A |
161 | } |
162 | ||
163 | pr_debug("reg (%s)\n", on ? "HPM" : "LPM"); | |
164 | return ret < 0 ? ret : 0; | |
165 | } | |
166 | ||
1d4c9293 | 167 | static int ulpi_read(struct usb_phy *phy, u32 reg) |
e0c201f3 | 168 | { |
1d4c9293 | 169 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
170 | int cnt = 0; |
171 | ||
172 | /* initiate read operation */ | |
173 | writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg), | |
174 | USB_ULPI_VIEWPORT); | |
175 | ||
176 | /* wait for completion */ | |
177 | while (cnt < ULPI_IO_TIMEOUT_USEC) { | |
178 | if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN)) | |
179 | break; | |
180 | udelay(1); | |
181 | cnt++; | |
182 | } | |
183 | ||
184 | if (cnt >= ULPI_IO_TIMEOUT_USEC) { | |
1d4c9293 | 185 | dev_err(phy->dev, "ulpi_read: timeout %08x\n", |
e0c201f3 PK |
186 | readl(USB_ULPI_VIEWPORT)); |
187 | return -ETIMEDOUT; | |
188 | } | |
189 | return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT)); | |
190 | } | |
191 | ||
1d4c9293 | 192 | static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg) |
e0c201f3 | 193 | { |
1d4c9293 | 194 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
195 | int cnt = 0; |
196 | ||
197 | /* initiate write operation */ | |
198 | writel(ULPI_RUN | ULPI_WRITE | | |
199 | ULPI_ADDR(reg) | ULPI_DATA(val), | |
200 | USB_ULPI_VIEWPORT); | |
201 | ||
202 | /* wait for completion */ | |
203 | while (cnt < ULPI_IO_TIMEOUT_USEC) { | |
204 | if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN)) | |
205 | break; | |
206 | udelay(1); | |
207 | cnt++; | |
208 | } | |
209 | ||
210 | if (cnt >= ULPI_IO_TIMEOUT_USEC) { | |
1d4c9293 | 211 | dev_err(phy->dev, "ulpi_write: timeout\n"); |
e0c201f3 PK |
212 | return -ETIMEDOUT; |
213 | } | |
214 | return 0; | |
215 | } | |
216 | ||
1d4c9293 | 217 | static struct usb_phy_io_ops msm_otg_io_ops = { |
e0c201f3 PK |
218 | .read = ulpi_read, |
219 | .write = ulpi_write, | |
220 | }; | |
221 | ||
222 | static void ulpi_init(struct msm_otg *motg) | |
223 | { | |
224 | struct msm_otg_platform_data *pdata = motg->pdata; | |
8364f9af II |
225 | int *seq = pdata->phy_init_seq, idx; |
226 | u32 addr = ULPI_EXT_VENDOR_SPECIFIC; | |
e0c201f3 | 227 | |
8364f9af II |
228 | for (idx = 0; idx < pdata->phy_init_sz; idx++) { |
229 | if (seq[idx] == -1) | |
230 | continue; | |
e0c201f3 | 231 | |
1d4c9293 | 232 | dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n", |
8364f9af II |
233 | seq[idx], addr + idx); |
234 | ulpi_write(&motg->phy, seq[idx], addr + idx); | |
e0c201f3 PK |
235 | } |
236 | } | |
237 | ||
238 | static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert) | |
239 | { | |
a2734543 | 240 | int ret; |
5146d771 | 241 | |
a2734543 II |
242 | if (motg->pdata->link_clk_reset) |
243 | ret = motg->pdata->link_clk_reset(motg->clk, assert); | |
244 | else if (assert) | |
245 | ret = reset_control_assert(motg->link_rst); | |
246 | else | |
247 | ret = reset_control_deassert(motg->link_rst); | |
5146d771 | 248 | |
5146d771 II |
249 | if (ret) |
250 | dev_err(motg->phy.dev, "usb link clk reset %s failed\n", | |
251 | assert ? "assert" : "deassert"); | |
e0c201f3 | 252 | |
e0c201f3 PK |
253 | return ret; |
254 | } | |
255 | ||
256 | static int msm_otg_phy_clk_reset(struct msm_otg *motg) | |
257 | { | |
a2734543 | 258 | int ret; |
e0c201f3 | 259 | |
a2734543 II |
260 | if (motg->pdata->phy_clk_reset) |
261 | ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk); | |
262 | else | |
263 | ret = reset_control_reset(motg->phy_rst); | |
5146d771 | 264 | |
e0c201f3 | 265 | if (ret) |
5146d771 II |
266 | dev_err(motg->phy.dev, "usb phy clk reset failed\n"); |
267 | ||
e0c201f3 PK |
268 | return ret; |
269 | } | |
270 | ||
d69c6f5d | 271 | static int msm_link_reset(struct msm_otg *motg) |
e0c201f3 PK |
272 | { |
273 | u32 val; | |
274 | int ret; | |
e0c201f3 PK |
275 | |
276 | ret = msm_otg_link_clk_reset(motg, 1); | |
e0c201f3 PK |
277 | if (ret) |
278 | return ret; | |
279 | ||
d69c6f5d II |
280 | /* wait for 1ms delay as suggested in HPG. */ |
281 | usleep_range(1000, 1200); | |
e0c201f3 | 282 | |
d69c6f5d | 283 | ret = msm_otg_link_clk_reset(motg, 0); |
e0c201f3 PK |
284 | if (ret) |
285 | return ret; | |
286 | ||
cfa3ff5d II |
287 | if (motg->phy_number) |
288 | writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2); | |
289 | ||
9f27984b | 290 | /* put transceiver in serial mode as part of reset */ |
d69c6f5d | 291 | val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK; |
9f27984b | 292 | writel(val | PORTSC_PTS_SERIAL, USB_PORTSC); |
d69c6f5d | 293 | |
e0c201f3 PK |
294 | return 0; |
295 | } | |
296 | ||
1d4c9293 | 297 | static int msm_otg_reset(struct usb_phy *phy) |
e0c201f3 | 298 | { |
1d4c9293 | 299 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 | 300 | int cnt = 0; |
e0c201f3 PK |
301 | |
302 | writel(USBCMD_RESET, USB_USBCMD); | |
303 | while (cnt < LINK_RESET_TIMEOUT_USEC) { | |
304 | if (!(readl(USB_USBCMD) & USBCMD_RESET)) | |
305 | break; | |
306 | udelay(1); | |
307 | cnt++; | |
308 | } | |
309 | if (cnt >= LINK_RESET_TIMEOUT_USEC) | |
310 | return -ETIMEDOUT; | |
311 | ||
9f27984b TB |
312 | /* select ULPI phy and clear other status/control bits in PORTSC */ |
313 | writel(PORTSC_PTS_ULPI, USB_PORTSC); | |
314 | ||
d69c6f5d II |
315 | writel(0x0, USB_AHBBURST); |
316 | writel(0x08, USB_AHBMODE); | |
317 | ||
318 | if (motg->phy_number) | |
319 | writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2); | |
320 | return 0; | |
321 | } | |
322 | ||
323 | static void msm_phy_reset(struct msm_otg *motg) | |
324 | { | |
325 | void __iomem *addr; | |
326 | ||
327 | if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) { | |
328 | msm_otg_phy_clk_reset(motg); | |
329 | return; | |
330 | } | |
331 | ||
332 | addr = USB_PHY_CTRL; | |
333 | if (motg->phy_number) | |
334 | addr = USB_PHY_CTRL2; | |
335 | ||
336 | /* Assert USB PHY_POR */ | |
337 | writel(readl(addr) | PHY_POR_ASSERT, addr); | |
338 | ||
339 | /* | |
340 | * wait for minimum 10 microseconds as suggested in HPG. | |
341 | * Use a slightly larger value since the exact value didn't | |
342 | * work 100% of the time. | |
343 | */ | |
344 | udelay(12); | |
345 | ||
346 | /* Deassert USB PHY_POR */ | |
347 | writel(readl(addr) & ~PHY_POR_ASSERT, addr); | |
348 | } | |
349 | ||
350 | static int msm_usb_reset(struct usb_phy *phy) | |
351 | { | |
352 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); | |
353 | int ret; | |
354 | ||
355 | if (!IS_ERR(motg->core_clk)) | |
356 | clk_prepare_enable(motg->core_clk); | |
357 | ||
358 | ret = msm_link_reset(motg); | |
359 | if (ret) { | |
360 | dev_err(phy->dev, "phy_reset failed\n"); | |
361 | return ret; | |
362 | } | |
363 | ||
364 | ret = msm_otg_reset(&motg->phy); | |
365 | if (ret) { | |
366 | dev_err(phy->dev, "link reset failed\n"); | |
367 | return ret; | |
368 | } | |
e0c201f3 PK |
369 | |
370 | msleep(100); | |
371 | ||
d69c6f5d II |
372 | /* Reset USB PHY after performing USB Link RESET */ |
373 | msm_phy_reset(motg); | |
374 | ||
375 | if (!IS_ERR(motg->core_clk)) | |
376 | clk_disable_unprepare(motg->core_clk); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | static int msm_phy_init(struct usb_phy *phy) | |
382 | { | |
383 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); | |
384 | struct msm_otg_platform_data *pdata = motg->pdata; | |
385 | u32 val, ulpi_val = 0; | |
386 | ||
387 | /* Program USB PHY Override registers. */ | |
388 | ulpi_init(motg); | |
389 | ||
390 | /* | |
391 | * It is recommended in HPG to reset USB PHY after programming | |
392 | * USB PHY Override registers. | |
393 | */ | |
394 | msm_phy_reset(motg); | |
e0c201f3 PK |
395 | |
396 | if (pdata->otg_control == OTG_PHY_CONTROL) { | |
397 | val = readl(USB_OTGSC); | |
971232cf | 398 | if (pdata->mode == USB_DR_MODE_OTG) { |
e0c201f3 PK |
399 | ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID; |
400 | val |= OTGSC_IDIE | OTGSC_BSVIE; | |
971232cf | 401 | } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) { |
e0c201f3 PK |
402 | ulpi_val = ULPI_INT_SESS_VALID; |
403 | val |= OTGSC_BSVIE; | |
404 | } | |
405 | writel(val, USB_OTGSC); | |
1d4c9293 HK |
406 | ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE); |
407 | ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL); | |
e0c201f3 PK |
408 | } |
409 | ||
cfa3ff5d II |
410 | if (motg->phy_number) |
411 | writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2); | |
412 | ||
e0c201f3 PK |
413 | return 0; |
414 | } | |
415 | ||
87c0104a | 416 | #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000) |
7018773a PK |
417 | #define PHY_RESUME_TIMEOUT_USEC (100 * 1000) |
418 | ||
e7d613d1 JC |
419 | #ifdef CONFIG_PM |
420 | ||
421 | #define USB_PHY_SUSP_DIG_VOL 500000 | |
37cfdaf7 | 422 | static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high) |
e7d613d1 JC |
423 | { |
424 | int max_vol = USB_PHY_VDD_DIG_VOL_MAX; | |
425 | int min_vol; | |
426 | int ret; | |
427 | ||
428 | if (high) | |
429 | min_vol = USB_PHY_VDD_DIG_VOL_MIN; | |
430 | else | |
431 | min_vol = USB_PHY_SUSP_DIG_VOL; | |
432 | ||
37cfdaf7 | 433 | ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol); |
e7d613d1 | 434 | if (ret) { |
3aca0fa9 | 435 | pr_err("Cannot set vddcx voltage\n"); |
e7d613d1 JC |
436 | return ret; |
437 | } | |
438 | ||
439 | pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol); | |
440 | ||
441 | return ret; | |
442 | } | |
443 | ||
87c0104a PK |
444 | static int msm_otg_suspend(struct msm_otg *motg) |
445 | { | |
1d4c9293 HK |
446 | struct usb_phy *phy = &motg->phy; |
447 | struct usb_bus *bus = phy->otg->host; | |
87c0104a | 448 | struct msm_otg_platform_data *pdata = motg->pdata; |
cfa3ff5d | 449 | void __iomem *addr; |
87c0104a PK |
450 | int cnt = 0; |
451 | ||
452 | if (atomic_read(&motg->in_lpm)) | |
453 | return 0; | |
454 | ||
455 | disable_irq(motg->irq); | |
456 | /* | |
04aebcbb PK |
457 | * Chipidea 45-nm PHY suspend sequence: |
458 | * | |
87c0104a PK |
459 | * Interrupt Latch Register auto-clear feature is not present |
460 | * in all PHY versions. Latch register is clear on read type. | |
461 | * Clear latch register to avoid spurious wakeup from | |
462 | * low power mode (LPM). | |
04aebcbb | 463 | * |
87c0104a PK |
464 | * PHY comparators are disabled when PHY enters into low power |
465 | * mode (LPM). Keep PHY comparators ON in LPM only when we expect | |
466 | * VBUS/Id notifications from USB PHY. Otherwise turn off USB | |
467 | * PHY comparators. This save significant amount of power. | |
04aebcbb | 468 | * |
87c0104a PK |
469 | * PLL is not turned off when PHY enters into low power mode (LPM). |
470 | * Disable PLL for maximum power savings. | |
471 | */ | |
04aebcbb PK |
472 | |
473 | if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) { | |
1d4c9293 | 474 | ulpi_read(phy, 0x14); |
04aebcbb | 475 | if (pdata->otg_control == OTG_PHY_CONTROL) |
1d4c9293 HK |
476 | ulpi_write(phy, 0x01, 0x30); |
477 | ulpi_write(phy, 0x08, 0x09); | |
04aebcbb | 478 | } |
87c0104a PK |
479 | |
480 | /* | |
481 | * PHY may take some time or even fail to enter into low power | |
482 | * mode (LPM). Hence poll for 500 msec and reset the PHY and link | |
483 | * in failure case. | |
484 | */ | |
485 | writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC); | |
486 | while (cnt < PHY_SUSPEND_TIMEOUT_USEC) { | |
487 | if (readl(USB_PORTSC) & PORTSC_PHCD) | |
488 | break; | |
489 | udelay(1); | |
490 | cnt++; | |
491 | } | |
492 | ||
493 | if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) { | |
1d4c9293 HK |
494 | dev_err(phy->dev, "Unable to suspend PHY\n"); |
495 | msm_otg_reset(phy); | |
87c0104a PK |
496 | enable_irq(motg->irq); |
497 | return -ETIMEDOUT; | |
498 | } | |
499 | ||
500 | /* | |
501 | * PHY has capability to generate interrupt asynchronously in low | |
502 | * power mode (LPM). This interrupt is level triggered. So USB IRQ | |
503 | * line must be disabled till async interrupt enable bit is cleared | |
504 | * in USBCMD register. Assert STP (ULPI interface STOP signal) to | |
505 | * block data communication from PHY. | |
506 | */ | |
507 | writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD); | |
508 | ||
cfa3ff5d II |
509 | addr = USB_PHY_CTRL; |
510 | if (motg->phy_number) | |
511 | addr = USB_PHY_CTRL2; | |
512 | ||
04aebcbb PK |
513 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
514 | motg->pdata->otg_control == OTG_PMIC_CONTROL) | |
cfa3ff5d | 515 | writel(readl(addr) | PHY_RETEN, addr); |
04aebcbb | 516 | |
b99a8f62 SB |
517 | clk_disable_unprepare(motg->pclk); |
518 | clk_disable_unprepare(motg->clk); | |
6b99c68e | 519 | if (!IS_ERR(motg->core_clk)) |
b99a8f62 | 520 | clk_disable_unprepare(motg->core_clk); |
87c0104a | 521 | |
04aebcbb PK |
522 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
523 | motg->pdata->otg_control == OTG_PMIC_CONTROL) { | |
37cfdaf7 II |
524 | msm_hsusb_ldo_set_mode(motg, 0); |
525 | msm_hsusb_config_vddcx(motg, 0); | |
04aebcbb PK |
526 | } |
527 | ||
1d4c9293 | 528 | if (device_may_wakeup(phy->dev)) |
87c0104a PK |
529 | enable_irq_wake(motg->irq); |
530 | if (bus) | |
531 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags); | |
532 | ||
533 | atomic_set(&motg->in_lpm, 1); | |
534 | enable_irq(motg->irq); | |
535 | ||
1d4c9293 | 536 | dev_info(phy->dev, "USB in low power mode\n"); |
87c0104a PK |
537 | |
538 | return 0; | |
539 | } | |
540 | ||
87c0104a PK |
541 | static int msm_otg_resume(struct msm_otg *motg) |
542 | { | |
1d4c9293 HK |
543 | struct usb_phy *phy = &motg->phy; |
544 | struct usb_bus *bus = phy->otg->host; | |
cfa3ff5d | 545 | void __iomem *addr; |
87c0104a PK |
546 | int cnt = 0; |
547 | unsigned temp; | |
548 | ||
549 | if (!atomic_read(&motg->in_lpm)) | |
550 | return 0; | |
551 | ||
b99a8f62 SB |
552 | clk_prepare_enable(motg->pclk); |
553 | clk_prepare_enable(motg->clk); | |
6b99c68e | 554 | if (!IS_ERR(motg->core_clk)) |
b99a8f62 | 555 | clk_prepare_enable(motg->core_clk); |
87c0104a | 556 | |
04aebcbb PK |
557 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
558 | motg->pdata->otg_control == OTG_PMIC_CONTROL) { | |
cfa3ff5d II |
559 | |
560 | addr = USB_PHY_CTRL; | |
561 | if (motg->phy_number) | |
562 | addr = USB_PHY_CTRL2; | |
563 | ||
37cfdaf7 II |
564 | msm_hsusb_ldo_set_mode(motg, 1); |
565 | msm_hsusb_config_vddcx(motg, 1); | |
cfa3ff5d | 566 | writel(readl(addr) & ~PHY_RETEN, addr); |
04aebcbb PK |
567 | } |
568 | ||
87c0104a PK |
569 | temp = readl(USB_USBCMD); |
570 | temp &= ~ASYNC_INTR_CTRL; | |
571 | temp &= ~ULPI_STP_CTRL; | |
572 | writel(temp, USB_USBCMD); | |
573 | ||
574 | /* | |
575 | * PHY comes out of low power mode (LPM) in case of wakeup | |
576 | * from asynchronous interrupt. | |
577 | */ | |
578 | if (!(readl(USB_PORTSC) & PORTSC_PHCD)) | |
579 | goto skip_phy_resume; | |
580 | ||
581 | writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC); | |
582 | while (cnt < PHY_RESUME_TIMEOUT_USEC) { | |
583 | if (!(readl(USB_PORTSC) & PORTSC_PHCD)) | |
584 | break; | |
585 | udelay(1); | |
586 | cnt++; | |
587 | } | |
588 | ||
589 | if (cnt >= PHY_RESUME_TIMEOUT_USEC) { | |
590 | /* | |
591 | * This is a fatal error. Reset the link and | |
592 | * PHY. USB state can not be restored. Re-insertion | |
593 | * of USB cable is the only way to get USB working. | |
594 | */ | |
3aca0fa9 | 595 | dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n"); |
1d4c9293 | 596 | msm_otg_reset(phy); |
87c0104a PK |
597 | } |
598 | ||
599 | skip_phy_resume: | |
1d4c9293 | 600 | if (device_may_wakeup(phy->dev)) |
87c0104a PK |
601 | disable_irq_wake(motg->irq); |
602 | if (bus) | |
603 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags); | |
604 | ||
2ce2c3ac PK |
605 | atomic_set(&motg->in_lpm, 0); |
606 | ||
87c0104a PK |
607 | if (motg->async_int) { |
608 | motg->async_int = 0; | |
1d4c9293 | 609 | pm_runtime_put(phy->dev); |
87c0104a PK |
610 | enable_irq(motg->irq); |
611 | } | |
612 | ||
1d4c9293 | 613 | dev_info(phy->dev, "USB exited from low power mode\n"); |
87c0104a PK |
614 | |
615 | return 0; | |
616 | } | |
7018773a | 617 | #endif |
87c0104a | 618 | |
d860852e PK |
619 | static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA) |
620 | { | |
621 | if (motg->cur_power == mA) | |
622 | return; | |
623 | ||
624 | /* TODO: Notify PMIC about available current */ | |
1d4c9293 | 625 | dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA); |
d860852e PK |
626 | motg->cur_power = mA; |
627 | } | |
628 | ||
1d4c9293 | 629 | static int msm_otg_set_power(struct usb_phy *phy, unsigned mA) |
d860852e | 630 | { |
1d4c9293 | 631 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
d860852e PK |
632 | |
633 | /* | |
634 | * Gadget driver uses set_power method to notify about the | |
635 | * available current based on suspend/configured states. | |
636 | * | |
637 | * IDEV_CHG can be drawn irrespective of suspend/un-configured | |
638 | * states when CDP/ACA is connected. | |
639 | */ | |
640 | if (motg->chg_type == USB_SDP_CHARGER) | |
641 | msm_otg_notify_charger(motg, mA); | |
642 | ||
643 | return 0; | |
644 | } | |
645 | ||
1d4c9293 | 646 | static void msm_otg_start_host(struct usb_phy *phy, int on) |
e0c201f3 | 647 | { |
1d4c9293 | 648 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
649 | struct msm_otg_platform_data *pdata = motg->pdata; |
650 | struct usb_hcd *hcd; | |
651 | ||
1d4c9293 | 652 | if (!phy->otg->host) |
e0c201f3 PK |
653 | return; |
654 | ||
1d4c9293 | 655 | hcd = bus_to_hcd(phy->otg->host); |
e0c201f3 PK |
656 | |
657 | if (on) { | |
1d4c9293 | 658 | dev_dbg(phy->dev, "host on\n"); |
e0c201f3 PK |
659 | |
660 | if (pdata->vbus_power) | |
661 | pdata->vbus_power(1); | |
662 | /* | |
663 | * Some boards have a switch cotrolled by gpio | |
664 | * to enable/disable internal HUB. Enable internal | |
665 | * HUB before kicking the host. | |
666 | */ | |
667 | if (pdata->setup_gpio) | |
668 | pdata->setup_gpio(OTG_STATE_A_HOST); | |
669 | #ifdef CONFIG_USB | |
670 | usb_add_hcd(hcd, hcd->irq, IRQF_SHARED); | |
3c9740a1 | 671 | device_wakeup_enable(hcd->self.controller); |
e0c201f3 PK |
672 | #endif |
673 | } else { | |
1d4c9293 | 674 | dev_dbg(phy->dev, "host off\n"); |
e0c201f3 PK |
675 | |
676 | #ifdef CONFIG_USB | |
677 | usb_remove_hcd(hcd); | |
678 | #endif | |
679 | if (pdata->setup_gpio) | |
680 | pdata->setup_gpio(OTG_STATE_UNDEFINED); | |
681 | if (pdata->vbus_power) | |
682 | pdata->vbus_power(0); | |
683 | } | |
684 | } | |
685 | ||
1d4c9293 | 686 | static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host) |
e0c201f3 | 687 | { |
1d4c9293 | 688 | struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy); |
e0c201f3 PK |
689 | struct usb_hcd *hcd; |
690 | ||
691 | /* | |
692 | * Fail host registration if this board can support | |
693 | * only peripheral configuration. | |
694 | */ | |
971232cf | 695 | if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) { |
1d4c9293 | 696 | dev_info(otg->phy->dev, "Host mode is not supported\n"); |
e0c201f3 PK |
697 | return -ENODEV; |
698 | } | |
699 | ||
700 | if (!host) { | |
1d4c9293 HK |
701 | if (otg->phy->state == OTG_STATE_A_HOST) { |
702 | pm_runtime_get_sync(otg->phy->dev); | |
703 | msm_otg_start_host(otg->phy, 0); | |
e0c201f3 | 704 | otg->host = NULL; |
1d4c9293 | 705 | otg->phy->state = OTG_STATE_UNDEFINED; |
e0c201f3 PK |
706 | schedule_work(&motg->sm_work); |
707 | } else { | |
708 | otg->host = NULL; | |
709 | } | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
714 | hcd = bus_to_hcd(host); | |
715 | hcd->power_budget = motg->pdata->power_budget; | |
716 | ||
717 | otg->host = host; | |
1d4c9293 | 718 | dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n"); |
e0c201f3 PK |
719 | |
720 | /* | |
721 | * Kick the state machine work, if peripheral is not supported | |
722 | * or peripheral is already registered with us. | |
723 | */ | |
971232cf | 724 | if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) { |
1d4c9293 | 725 | pm_runtime_get_sync(otg->phy->dev); |
e0c201f3 | 726 | schedule_work(&motg->sm_work); |
87c0104a | 727 | } |
e0c201f3 PK |
728 | |
729 | return 0; | |
730 | } | |
731 | ||
1d4c9293 | 732 | static void msm_otg_start_peripheral(struct usb_phy *phy, int on) |
e0c201f3 | 733 | { |
1d4c9293 | 734 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
735 | struct msm_otg_platform_data *pdata = motg->pdata; |
736 | ||
1d4c9293 | 737 | if (!phy->otg->gadget) |
e0c201f3 PK |
738 | return; |
739 | ||
740 | if (on) { | |
1d4c9293 | 741 | dev_dbg(phy->dev, "gadget on\n"); |
e0c201f3 PK |
742 | /* |
743 | * Some boards have a switch cotrolled by gpio | |
744 | * to enable/disable internal HUB. Disable internal | |
745 | * HUB before kicking the gadget. | |
746 | */ | |
747 | if (pdata->setup_gpio) | |
748 | pdata->setup_gpio(OTG_STATE_B_PERIPHERAL); | |
1d4c9293 | 749 | usb_gadget_vbus_connect(phy->otg->gadget); |
e0c201f3 | 750 | } else { |
1d4c9293 HK |
751 | dev_dbg(phy->dev, "gadget off\n"); |
752 | usb_gadget_vbus_disconnect(phy->otg->gadget); | |
e0c201f3 PK |
753 | if (pdata->setup_gpio) |
754 | pdata->setup_gpio(OTG_STATE_UNDEFINED); | |
755 | } | |
756 | ||
757 | } | |
758 | ||
1d4c9293 HK |
759 | static int msm_otg_set_peripheral(struct usb_otg *otg, |
760 | struct usb_gadget *gadget) | |
e0c201f3 | 761 | { |
1d4c9293 | 762 | struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy); |
e0c201f3 PK |
763 | |
764 | /* | |
765 | * Fail peripheral registration if this board can support | |
766 | * only host configuration. | |
767 | */ | |
971232cf | 768 | if (motg->pdata->mode == USB_DR_MODE_HOST) { |
1d4c9293 | 769 | dev_info(otg->phy->dev, "Peripheral mode is not supported\n"); |
e0c201f3 PK |
770 | return -ENODEV; |
771 | } | |
772 | ||
773 | if (!gadget) { | |
1d4c9293 HK |
774 | if (otg->phy->state == OTG_STATE_B_PERIPHERAL) { |
775 | pm_runtime_get_sync(otg->phy->dev); | |
776 | msm_otg_start_peripheral(otg->phy, 0); | |
e0c201f3 | 777 | otg->gadget = NULL; |
1d4c9293 | 778 | otg->phy->state = OTG_STATE_UNDEFINED; |
e0c201f3 PK |
779 | schedule_work(&motg->sm_work); |
780 | } else { | |
781 | otg->gadget = NULL; | |
782 | } | |
783 | ||
784 | return 0; | |
785 | } | |
786 | otg->gadget = gadget; | |
1d4c9293 | 787 | dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n"); |
e0c201f3 PK |
788 | |
789 | /* | |
790 | * Kick the state machine work, if host is not supported | |
791 | * or host is already registered with us. | |
792 | */ | |
971232cf | 793 | if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) { |
1d4c9293 | 794 | pm_runtime_get_sync(otg->phy->dev); |
e0c201f3 | 795 | schedule_work(&motg->sm_work); |
87c0104a | 796 | } |
e0c201f3 PK |
797 | |
798 | return 0; | |
799 | } | |
800 | ||
d860852e PK |
801 | static bool msm_chg_check_secondary_det(struct msm_otg *motg) |
802 | { | |
1d4c9293 | 803 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
804 | u32 chg_det; |
805 | bool ret = false; | |
806 | ||
807 | switch (motg->pdata->phy_type) { | |
808 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 809 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
810 | ret = chg_det & (1 << 4); |
811 | break; | |
812 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 813 | chg_det = ulpi_read(phy, 0x87); |
d860852e PK |
814 | ret = chg_det & 1; |
815 | break; | |
816 | default: | |
817 | break; | |
818 | } | |
819 | return ret; | |
820 | } | |
821 | ||
822 | static void msm_chg_enable_secondary_det(struct msm_otg *motg) | |
823 | { | |
1d4c9293 | 824 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
825 | u32 chg_det; |
826 | ||
827 | switch (motg->pdata->phy_type) { | |
828 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 829 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
830 | /* Turn off charger block */ |
831 | chg_det |= ~(1 << 1); | |
1d4c9293 | 832 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
833 | udelay(20); |
834 | /* control chg block via ULPI */ | |
835 | chg_det &= ~(1 << 3); | |
1d4c9293 | 836 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
837 | /* put it in host mode for enabling D- source */ |
838 | chg_det &= ~(1 << 2); | |
1d4c9293 | 839 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
840 | /* Turn on chg detect block */ |
841 | chg_det &= ~(1 << 1); | |
1d4c9293 | 842 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
843 | udelay(20); |
844 | /* enable chg detection */ | |
845 | chg_det &= ~(1 << 0); | |
1d4c9293 | 846 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
847 | break; |
848 | case SNPS_28NM_INTEGRATED_PHY: | |
849 | /* | |
850 | * Configure DM as current source, DP as current sink | |
851 | * and enable battery charging comparators. | |
852 | */ | |
1d4c9293 HK |
853 | ulpi_write(phy, 0x8, 0x85); |
854 | ulpi_write(phy, 0x2, 0x85); | |
855 | ulpi_write(phy, 0x1, 0x85); | |
d860852e PK |
856 | break; |
857 | default: | |
858 | break; | |
859 | } | |
860 | } | |
861 | ||
862 | static bool msm_chg_check_primary_det(struct msm_otg *motg) | |
863 | { | |
1d4c9293 | 864 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
865 | u32 chg_det; |
866 | bool ret = false; | |
867 | ||
868 | switch (motg->pdata->phy_type) { | |
869 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 870 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
871 | ret = chg_det & (1 << 4); |
872 | break; | |
873 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 874 | chg_det = ulpi_read(phy, 0x87); |
d860852e PK |
875 | ret = chg_det & 1; |
876 | break; | |
877 | default: | |
878 | break; | |
879 | } | |
880 | return ret; | |
881 | } | |
882 | ||
883 | static void msm_chg_enable_primary_det(struct msm_otg *motg) | |
884 | { | |
1d4c9293 | 885 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
886 | u32 chg_det; |
887 | ||
888 | switch (motg->pdata->phy_type) { | |
889 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 890 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
891 | /* enable chg detection */ |
892 | chg_det &= ~(1 << 0); | |
1d4c9293 | 893 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
894 | break; |
895 | case SNPS_28NM_INTEGRATED_PHY: | |
896 | /* | |
897 | * Configure DP as current source, DM as current sink | |
898 | * and enable battery charging comparators. | |
899 | */ | |
1d4c9293 HK |
900 | ulpi_write(phy, 0x2, 0x85); |
901 | ulpi_write(phy, 0x1, 0x85); | |
d860852e PK |
902 | break; |
903 | default: | |
904 | break; | |
905 | } | |
906 | } | |
907 | ||
908 | static bool msm_chg_check_dcd(struct msm_otg *motg) | |
909 | { | |
1d4c9293 | 910 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
911 | u32 line_state; |
912 | bool ret = false; | |
913 | ||
914 | switch (motg->pdata->phy_type) { | |
915 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 916 | line_state = ulpi_read(phy, 0x15); |
d860852e PK |
917 | ret = !(line_state & 1); |
918 | break; | |
919 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 920 | line_state = ulpi_read(phy, 0x87); |
d860852e PK |
921 | ret = line_state & 2; |
922 | break; | |
923 | default: | |
924 | break; | |
925 | } | |
926 | return ret; | |
927 | } | |
928 | ||
929 | static void msm_chg_disable_dcd(struct msm_otg *motg) | |
930 | { | |
1d4c9293 | 931 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
932 | u32 chg_det; |
933 | ||
934 | switch (motg->pdata->phy_type) { | |
935 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 936 | chg_det = ulpi_read(phy, 0x34); |
d860852e | 937 | chg_det &= ~(1 << 5); |
1d4c9293 | 938 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
939 | break; |
940 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 941 | ulpi_write(phy, 0x10, 0x86); |
d860852e PK |
942 | break; |
943 | default: | |
944 | break; | |
945 | } | |
946 | } | |
947 | ||
948 | static void msm_chg_enable_dcd(struct msm_otg *motg) | |
949 | { | |
1d4c9293 | 950 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
951 | u32 chg_det; |
952 | ||
953 | switch (motg->pdata->phy_type) { | |
954 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 955 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
956 | /* Turn on D+ current source */ |
957 | chg_det |= (1 << 5); | |
1d4c9293 | 958 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
959 | break; |
960 | case SNPS_28NM_INTEGRATED_PHY: | |
961 | /* Data contact detection enable */ | |
1d4c9293 | 962 | ulpi_write(phy, 0x10, 0x85); |
d860852e PK |
963 | break; |
964 | default: | |
965 | break; | |
966 | } | |
967 | } | |
968 | ||
969 | static void msm_chg_block_on(struct msm_otg *motg) | |
970 | { | |
1d4c9293 | 971 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
972 | u32 func_ctrl, chg_det; |
973 | ||
974 | /* put the controller in non-driving mode */ | |
1d4c9293 | 975 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
d860852e PK |
976 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
977 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING; | |
1d4c9293 | 978 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
d860852e PK |
979 | |
980 | switch (motg->pdata->phy_type) { | |
981 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 982 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
983 | /* control chg block via ULPI */ |
984 | chg_det &= ~(1 << 3); | |
1d4c9293 | 985 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
986 | /* Turn on chg detect block */ |
987 | chg_det &= ~(1 << 1); | |
1d4c9293 | 988 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
989 | udelay(20); |
990 | break; | |
991 | case SNPS_28NM_INTEGRATED_PHY: | |
992 | /* Clear charger detecting control bits */ | |
1d4c9293 | 993 | ulpi_write(phy, 0x3F, 0x86); |
d860852e | 994 | /* Clear alt interrupt latch and enable bits */ |
1d4c9293 HK |
995 | ulpi_write(phy, 0x1F, 0x92); |
996 | ulpi_write(phy, 0x1F, 0x95); | |
d860852e PK |
997 | udelay(100); |
998 | break; | |
999 | default: | |
1000 | break; | |
1001 | } | |
1002 | } | |
1003 | ||
1004 | static void msm_chg_block_off(struct msm_otg *motg) | |
1005 | { | |
1d4c9293 | 1006 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1007 | u32 func_ctrl, chg_det; |
1008 | ||
1009 | switch (motg->pdata->phy_type) { | |
1010 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1011 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
1012 | /* Turn off charger block */ |
1013 | chg_det |= ~(1 << 1); | |
1d4c9293 | 1014 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1015 | break; |
1016 | case SNPS_28NM_INTEGRATED_PHY: | |
1017 | /* Clear charger detecting control bits */ | |
1d4c9293 | 1018 | ulpi_write(phy, 0x3F, 0x86); |
d860852e | 1019 | /* Clear alt interrupt latch and enable bits */ |
1d4c9293 HK |
1020 | ulpi_write(phy, 0x1F, 0x92); |
1021 | ulpi_write(phy, 0x1F, 0x95); | |
d860852e PK |
1022 | break; |
1023 | default: | |
1024 | break; | |
1025 | } | |
1026 | ||
1027 | /* put the controller in normal mode */ | |
1d4c9293 | 1028 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
d860852e PK |
1029 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
1030 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL; | |
1d4c9293 | 1031 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
d860852e PK |
1032 | } |
1033 | ||
1034 | #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */ | |
1035 | #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */ | |
1036 | #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */ | |
1037 | #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */ | |
1038 | static void msm_chg_detect_work(struct work_struct *w) | |
1039 | { | |
1040 | struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work); | |
1d4c9293 | 1041 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1042 | bool is_dcd, tmout, vout; |
1043 | unsigned long delay; | |
1044 | ||
1d4c9293 | 1045 | dev_dbg(phy->dev, "chg detection work\n"); |
d860852e PK |
1046 | switch (motg->chg_state) { |
1047 | case USB_CHG_STATE_UNDEFINED: | |
1d4c9293 | 1048 | pm_runtime_get_sync(phy->dev); |
d860852e PK |
1049 | msm_chg_block_on(motg); |
1050 | msm_chg_enable_dcd(motg); | |
1051 | motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; | |
1052 | motg->dcd_retries = 0; | |
1053 | delay = MSM_CHG_DCD_POLL_TIME; | |
1054 | break; | |
1055 | case USB_CHG_STATE_WAIT_FOR_DCD: | |
1056 | is_dcd = msm_chg_check_dcd(motg); | |
1057 | tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES; | |
1058 | if (is_dcd || tmout) { | |
1059 | msm_chg_disable_dcd(motg); | |
1060 | msm_chg_enable_primary_det(motg); | |
1061 | delay = MSM_CHG_PRIMARY_DET_TIME; | |
1062 | motg->chg_state = USB_CHG_STATE_DCD_DONE; | |
1063 | } else { | |
1064 | delay = MSM_CHG_DCD_POLL_TIME; | |
1065 | } | |
1066 | break; | |
1067 | case USB_CHG_STATE_DCD_DONE: | |
1068 | vout = msm_chg_check_primary_det(motg); | |
1069 | if (vout) { | |
1070 | msm_chg_enable_secondary_det(motg); | |
1071 | delay = MSM_CHG_SECONDARY_DET_TIME; | |
1072 | motg->chg_state = USB_CHG_STATE_PRIMARY_DONE; | |
1073 | } else { | |
1074 | motg->chg_type = USB_SDP_CHARGER; | |
1075 | motg->chg_state = USB_CHG_STATE_DETECTED; | |
1076 | delay = 0; | |
1077 | } | |
1078 | break; | |
1079 | case USB_CHG_STATE_PRIMARY_DONE: | |
1080 | vout = msm_chg_check_secondary_det(motg); | |
1081 | if (vout) | |
1082 | motg->chg_type = USB_DCP_CHARGER; | |
1083 | else | |
1084 | motg->chg_type = USB_CDP_CHARGER; | |
1085 | motg->chg_state = USB_CHG_STATE_SECONDARY_DONE; | |
1086 | /* fall through */ | |
1087 | case USB_CHG_STATE_SECONDARY_DONE: | |
1088 | motg->chg_state = USB_CHG_STATE_DETECTED; | |
1089 | case USB_CHG_STATE_DETECTED: | |
1090 | msm_chg_block_off(motg); | |
1d4c9293 | 1091 | dev_dbg(phy->dev, "charger = %d\n", motg->chg_type); |
d860852e PK |
1092 | schedule_work(&motg->sm_work); |
1093 | return; | |
1094 | default: | |
1095 | return; | |
1096 | } | |
1097 | ||
1098 | schedule_delayed_work(&motg->chg_work, delay); | |
1099 | } | |
1100 | ||
e0c201f3 PK |
1101 | /* |
1102 | * We support OTG, Peripheral only and Host only configurations. In case | |
1103 | * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen | |
1104 | * via Id pin status or user request (debugfs). Id/BSV interrupts are not | |
1105 | * enabled when switch is controlled by user and default mode is supplied | |
1106 | * by board file, which can be changed by userspace later. | |
1107 | */ | |
1108 | static void msm_otg_init_sm(struct msm_otg *motg) | |
1109 | { | |
1110 | struct msm_otg_platform_data *pdata = motg->pdata; | |
1111 | u32 otgsc = readl(USB_OTGSC); | |
1112 | ||
1113 | switch (pdata->mode) { | |
971232cf | 1114 | case USB_DR_MODE_OTG: |
e0c201f3 PK |
1115 | if (pdata->otg_control == OTG_PHY_CONTROL) { |
1116 | if (otgsc & OTGSC_ID) | |
1117 | set_bit(ID, &motg->inputs); | |
1118 | else | |
1119 | clear_bit(ID, &motg->inputs); | |
1120 | ||
1121 | if (otgsc & OTGSC_BSV) | |
1122 | set_bit(B_SESS_VLD, &motg->inputs); | |
1123 | else | |
1124 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1125 | } else if (pdata->otg_control == OTG_USER_CONTROL) { | |
e0c201f3 PK |
1126 | set_bit(ID, &motg->inputs); |
1127 | clear_bit(B_SESS_VLD, &motg->inputs); | |
e0c201f3 PK |
1128 | } |
1129 | break; | |
971232cf | 1130 | case USB_DR_MODE_HOST: |
e0c201f3 PK |
1131 | clear_bit(ID, &motg->inputs); |
1132 | break; | |
971232cf | 1133 | case USB_DR_MODE_PERIPHERAL: |
e0c201f3 PK |
1134 | set_bit(ID, &motg->inputs); |
1135 | if (otgsc & OTGSC_BSV) | |
1136 | set_bit(B_SESS_VLD, &motg->inputs); | |
1137 | else | |
1138 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1139 | break; | |
1140 | default: | |
1141 | break; | |
1142 | } | |
1143 | } | |
1144 | ||
1145 | static void msm_otg_sm_work(struct work_struct *w) | |
1146 | { | |
1147 | struct msm_otg *motg = container_of(w, struct msm_otg, sm_work); | |
1d4c9293 | 1148 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1149 | |
1d4c9293 | 1150 | switch (otg->phy->state) { |
e0c201f3 | 1151 | case OTG_STATE_UNDEFINED: |
1d4c9293 HK |
1152 | dev_dbg(otg->phy->dev, "OTG_STATE_UNDEFINED state\n"); |
1153 | msm_otg_reset(otg->phy); | |
e0c201f3 | 1154 | msm_otg_init_sm(motg); |
1d4c9293 | 1155 | otg->phy->state = OTG_STATE_B_IDLE; |
e0c201f3 PK |
1156 | /* FALL THROUGH */ |
1157 | case OTG_STATE_B_IDLE: | |
1d4c9293 | 1158 | dev_dbg(otg->phy->dev, "OTG_STATE_B_IDLE state\n"); |
e0c201f3 PK |
1159 | if (!test_bit(ID, &motg->inputs) && otg->host) { |
1160 | /* disable BSV bit */ | |
1161 | writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC); | |
1d4c9293 HK |
1162 | msm_otg_start_host(otg->phy, 1); |
1163 | otg->phy->state = OTG_STATE_A_HOST; | |
d860852e PK |
1164 | } else if (test_bit(B_SESS_VLD, &motg->inputs)) { |
1165 | switch (motg->chg_state) { | |
1166 | case USB_CHG_STATE_UNDEFINED: | |
1167 | msm_chg_detect_work(&motg->chg_work.work); | |
1168 | break; | |
1169 | case USB_CHG_STATE_DETECTED: | |
1170 | switch (motg->chg_type) { | |
1171 | case USB_DCP_CHARGER: | |
1172 | msm_otg_notify_charger(motg, | |
1173 | IDEV_CHG_MAX); | |
1174 | break; | |
1175 | case USB_CDP_CHARGER: | |
1176 | msm_otg_notify_charger(motg, | |
1177 | IDEV_CHG_MAX); | |
1d4c9293 HK |
1178 | msm_otg_start_peripheral(otg->phy, 1); |
1179 | otg->phy->state | |
1180 | = OTG_STATE_B_PERIPHERAL; | |
d860852e PK |
1181 | break; |
1182 | case USB_SDP_CHARGER: | |
1183 | msm_otg_notify_charger(motg, IUNIT); | |
1d4c9293 HK |
1184 | msm_otg_start_peripheral(otg->phy, 1); |
1185 | otg->phy->state | |
1186 | = OTG_STATE_B_PERIPHERAL; | |
d860852e PK |
1187 | break; |
1188 | default: | |
1189 | break; | |
1190 | } | |
1191 | break; | |
1192 | default: | |
1193 | break; | |
1194 | } | |
1195 | } else { | |
1196 | /* | |
1197 | * If charger detection work is pending, decrement | |
1198 | * the pm usage counter to balance with the one that | |
1199 | * is incremented in charger detection work. | |
1200 | */ | |
1201 | if (cancel_delayed_work_sync(&motg->chg_work)) { | |
1d4c9293 HK |
1202 | pm_runtime_put_sync(otg->phy->dev); |
1203 | msm_otg_reset(otg->phy); | |
d860852e PK |
1204 | } |
1205 | msm_otg_notify_charger(motg, 0); | |
1206 | motg->chg_state = USB_CHG_STATE_UNDEFINED; | |
1207 | motg->chg_type = USB_INVALID_CHARGER; | |
e0c201f3 | 1208 | } |
1d4c9293 | 1209 | pm_runtime_put_sync(otg->phy->dev); |
e0c201f3 PK |
1210 | break; |
1211 | case OTG_STATE_B_PERIPHERAL: | |
1d4c9293 | 1212 | dev_dbg(otg->phy->dev, "OTG_STATE_B_PERIPHERAL state\n"); |
e0c201f3 PK |
1213 | if (!test_bit(B_SESS_VLD, &motg->inputs) || |
1214 | !test_bit(ID, &motg->inputs)) { | |
d860852e | 1215 | msm_otg_notify_charger(motg, 0); |
1d4c9293 | 1216 | msm_otg_start_peripheral(otg->phy, 0); |
d860852e PK |
1217 | motg->chg_state = USB_CHG_STATE_UNDEFINED; |
1218 | motg->chg_type = USB_INVALID_CHARGER; | |
1d4c9293 HK |
1219 | otg->phy->state = OTG_STATE_B_IDLE; |
1220 | msm_otg_reset(otg->phy); | |
e0c201f3 PK |
1221 | schedule_work(w); |
1222 | } | |
1223 | break; | |
1224 | case OTG_STATE_A_HOST: | |
1d4c9293 | 1225 | dev_dbg(otg->phy->dev, "OTG_STATE_A_HOST state\n"); |
e0c201f3 | 1226 | if (test_bit(ID, &motg->inputs)) { |
1d4c9293 HK |
1227 | msm_otg_start_host(otg->phy, 0); |
1228 | otg->phy->state = OTG_STATE_B_IDLE; | |
1229 | msm_otg_reset(otg->phy); | |
e0c201f3 PK |
1230 | schedule_work(w); |
1231 | } | |
1232 | break; | |
1233 | default: | |
1234 | break; | |
1235 | } | |
1236 | } | |
1237 | ||
1238 | static irqreturn_t msm_otg_irq(int irq, void *data) | |
1239 | { | |
1240 | struct msm_otg *motg = data; | |
1d4c9293 | 1241 | struct usb_phy *phy = &motg->phy; |
e0c201f3 PK |
1242 | u32 otgsc = 0; |
1243 | ||
87c0104a PK |
1244 | if (atomic_read(&motg->in_lpm)) { |
1245 | disable_irq_nosync(irq); | |
1246 | motg->async_int = 1; | |
1d4c9293 | 1247 | pm_runtime_get(phy->dev); |
87c0104a PK |
1248 | return IRQ_HANDLED; |
1249 | } | |
1250 | ||
e0c201f3 PK |
1251 | otgsc = readl(USB_OTGSC); |
1252 | if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS))) | |
1253 | return IRQ_NONE; | |
1254 | ||
1255 | if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) { | |
1256 | if (otgsc & OTGSC_ID) | |
1257 | set_bit(ID, &motg->inputs); | |
1258 | else | |
1259 | clear_bit(ID, &motg->inputs); | |
1d4c9293 HK |
1260 | dev_dbg(phy->dev, "ID set/clear\n"); |
1261 | pm_runtime_get_noresume(phy->dev); | |
e0c201f3 PK |
1262 | } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) { |
1263 | if (otgsc & OTGSC_BSV) | |
1264 | set_bit(B_SESS_VLD, &motg->inputs); | |
1265 | else | |
1266 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1d4c9293 HK |
1267 | dev_dbg(phy->dev, "BSV set/clear\n"); |
1268 | pm_runtime_get_noresume(phy->dev); | |
e0c201f3 PK |
1269 | } |
1270 | ||
1271 | writel(otgsc, USB_OTGSC); | |
1272 | schedule_work(&motg->sm_work); | |
1273 | return IRQ_HANDLED; | |
1274 | } | |
1275 | ||
1276 | static int msm_otg_mode_show(struct seq_file *s, void *unused) | |
1277 | { | |
1278 | struct msm_otg *motg = s->private; | |
1d4c9293 | 1279 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1280 | |
1d4c9293 | 1281 | switch (otg->phy->state) { |
e0c201f3 | 1282 | case OTG_STATE_A_HOST: |
3aca0fa9 | 1283 | seq_puts(s, "host\n"); |
e0c201f3 PK |
1284 | break; |
1285 | case OTG_STATE_B_PERIPHERAL: | |
3aca0fa9 | 1286 | seq_puts(s, "peripheral\n"); |
e0c201f3 PK |
1287 | break; |
1288 | default: | |
3aca0fa9 | 1289 | seq_puts(s, "none\n"); |
e0c201f3 PK |
1290 | break; |
1291 | } | |
1292 | ||
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | static int msm_otg_mode_open(struct inode *inode, struct file *file) | |
1297 | { | |
1298 | return single_open(file, msm_otg_mode_show, inode->i_private); | |
1299 | } | |
1300 | ||
1301 | static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf, | |
1302 | size_t count, loff_t *ppos) | |
1303 | { | |
e2904ee4 PK |
1304 | struct seq_file *s = file->private_data; |
1305 | struct msm_otg *motg = s->private; | |
e0c201f3 | 1306 | char buf[16]; |
1d4c9293 | 1307 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1308 | int status = count; |
971232cf | 1309 | enum usb_dr_mode req_mode; |
e0c201f3 PK |
1310 | |
1311 | memset(buf, 0x00, sizeof(buf)); | |
1312 | ||
1313 | if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) { | |
1314 | status = -EFAULT; | |
1315 | goto out; | |
1316 | } | |
1317 | ||
1318 | if (!strncmp(buf, "host", 4)) { | |
971232cf | 1319 | req_mode = USB_DR_MODE_HOST; |
e0c201f3 | 1320 | } else if (!strncmp(buf, "peripheral", 10)) { |
971232cf | 1321 | req_mode = USB_DR_MODE_PERIPHERAL; |
e0c201f3 | 1322 | } else if (!strncmp(buf, "none", 4)) { |
971232cf | 1323 | req_mode = USB_DR_MODE_UNKNOWN; |
e0c201f3 PK |
1324 | } else { |
1325 | status = -EINVAL; | |
1326 | goto out; | |
1327 | } | |
1328 | ||
1329 | switch (req_mode) { | |
971232cf | 1330 | case USB_DR_MODE_UNKNOWN: |
1d4c9293 | 1331 | switch (otg->phy->state) { |
e0c201f3 PK |
1332 | case OTG_STATE_A_HOST: |
1333 | case OTG_STATE_B_PERIPHERAL: | |
1334 | set_bit(ID, &motg->inputs); | |
1335 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1336 | break; | |
1337 | default: | |
1338 | goto out; | |
1339 | } | |
1340 | break; | |
971232cf | 1341 | case USB_DR_MODE_PERIPHERAL: |
1d4c9293 | 1342 | switch (otg->phy->state) { |
e0c201f3 PK |
1343 | case OTG_STATE_B_IDLE: |
1344 | case OTG_STATE_A_HOST: | |
1345 | set_bit(ID, &motg->inputs); | |
1346 | set_bit(B_SESS_VLD, &motg->inputs); | |
1347 | break; | |
1348 | default: | |
1349 | goto out; | |
1350 | } | |
1351 | break; | |
971232cf | 1352 | case USB_DR_MODE_HOST: |
1d4c9293 | 1353 | switch (otg->phy->state) { |
e0c201f3 PK |
1354 | case OTG_STATE_B_IDLE: |
1355 | case OTG_STATE_B_PERIPHERAL: | |
1356 | clear_bit(ID, &motg->inputs); | |
1357 | break; | |
1358 | default: | |
1359 | goto out; | |
1360 | } | |
1361 | break; | |
1362 | default: | |
1363 | goto out; | |
1364 | } | |
1365 | ||
1d4c9293 | 1366 | pm_runtime_get_sync(otg->phy->dev); |
e0c201f3 PK |
1367 | schedule_work(&motg->sm_work); |
1368 | out: | |
1369 | return status; | |
1370 | } | |
1371 | ||
1372 | const struct file_operations msm_otg_mode_fops = { | |
1373 | .open = msm_otg_mode_open, | |
1374 | .read = seq_read, | |
1375 | .write = msm_otg_mode_write, | |
1376 | .llseek = seq_lseek, | |
1377 | .release = single_release, | |
1378 | }; | |
1379 | ||
1380 | static struct dentry *msm_otg_dbg_root; | |
1381 | static struct dentry *msm_otg_dbg_mode; | |
1382 | ||
1383 | static int msm_otg_debugfs_init(struct msm_otg *motg) | |
1384 | { | |
1385 | msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL); | |
1386 | ||
1387 | if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root)) | |
1388 | return -ENODEV; | |
1389 | ||
1390 | msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR, | |
1391 | msm_otg_dbg_root, motg, &msm_otg_mode_fops); | |
1392 | if (!msm_otg_dbg_mode) { | |
1393 | debugfs_remove(msm_otg_dbg_root); | |
1394 | msm_otg_dbg_root = NULL; | |
1395 | return -ENODEV; | |
1396 | } | |
1397 | ||
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | static void msm_otg_debugfs_cleanup(void) | |
1402 | { | |
1403 | debugfs_remove(msm_otg_dbg_mode); | |
1404 | debugfs_remove(msm_otg_dbg_root); | |
1405 | } | |
1406 | ||
8364f9af II |
1407 | static struct of_device_id msm_otg_dt_match[] = { |
1408 | { | |
1409 | .compatible = "qcom,usb-otg-ci", | |
1410 | .data = (void *) CI_45NM_INTEGRATED_PHY | |
1411 | }, | |
1412 | { | |
1413 | .compatible = "qcom,usb-otg-snps", | |
1414 | .data = (void *) SNPS_28NM_INTEGRATED_PHY | |
1415 | }, | |
1416 | { } | |
1417 | }; | |
1418 | MODULE_DEVICE_TABLE(of, msm_otg_dt_match); | |
1419 | ||
1420 | static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg) | |
1421 | { | |
1422 | struct msm_otg_platform_data *pdata; | |
1423 | const struct of_device_id *id; | |
1424 | struct device_node *node = pdev->dev.of_node; | |
1425 | struct property *prop; | |
1426 | int len, ret, words; | |
1427 | u32 val; | |
1428 | ||
1429 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1430 | if (!pdata) | |
1431 | return -ENOMEM; | |
1432 | ||
1433 | motg->pdata = pdata; | |
1434 | ||
1435 | id = of_match_device(msm_otg_dt_match, &pdev->dev); | |
1436 | pdata->phy_type = (int) id->data; | |
1437 | ||
a2734543 II |
1438 | motg->link_rst = devm_reset_control_get(&pdev->dev, "link"); |
1439 | if (IS_ERR(motg->link_rst)) | |
1440 | return PTR_ERR(motg->link_rst); | |
1441 | ||
1442 | motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy"); | |
1443 | if (IS_ERR(motg->phy_rst)) | |
1444 | return PTR_ERR(motg->phy_rst); | |
1445 | ||
8364f9af II |
1446 | pdata->mode = of_usb_get_dr_mode(node); |
1447 | if (pdata->mode == USB_DR_MODE_UNKNOWN) | |
1448 | pdata->mode = USB_DR_MODE_OTG; | |
1449 | ||
1450 | pdata->otg_control = OTG_PHY_CONTROL; | |
1451 | if (!of_property_read_u32(node, "qcom,otg-control", &val)) | |
1452 | if (val == OTG_PMIC_CONTROL) | |
1453 | pdata->otg_control = val; | |
1454 | ||
cfa3ff5d II |
1455 | if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2) |
1456 | motg->phy_number = val; | |
1457 | ||
8364f9af II |
1458 | prop = of_find_property(node, "qcom,phy-init-sequence", &len); |
1459 | if (!prop || !len) | |
1460 | return 0; | |
1461 | ||
1462 | words = len / sizeof(u32); | |
1463 | ||
1464 | if (words >= ULPI_EXT_VENDOR_SPECIFIC) { | |
1465 | dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words); | |
1466 | return 0; | |
1467 | } | |
1468 | ||
1469 | pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); | |
1470 | if (!pdata->phy_init_seq) { | |
1471 | dev_warn(&pdev->dev, "No space for PHY init sequence\n"); | |
1472 | return 0; | |
1473 | } | |
1474 | ||
1475 | ret = of_property_read_u32_array(node, "qcom,phy-init-sequence", | |
1476 | pdata->phy_init_seq, words); | |
1477 | if (!ret) | |
1478 | pdata->phy_init_sz = words; | |
1479 | ||
1480 | return 0; | |
1481 | } | |
1482 | ||
06a6ec44 | 1483 | static int msm_otg_probe(struct platform_device *pdev) |
e0c201f3 | 1484 | { |
6b99c68e | 1485 | struct regulator_bulk_data regs[3]; |
e0c201f3 | 1486 | int ret = 0; |
8364f9af II |
1487 | struct device_node *np = pdev->dev.of_node; |
1488 | struct msm_otg_platform_data *pdata; | |
e0c201f3 PK |
1489 | struct resource *res; |
1490 | struct msm_otg *motg; | |
1d4c9293 | 1491 | struct usb_phy *phy; |
e0c201f3 | 1492 | |
6b99c68e | 1493 | motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL); |
e0c201f3 PK |
1494 | if (!motg) { |
1495 | dev_err(&pdev->dev, "unable to allocate msm_otg\n"); | |
1496 | return -ENOMEM; | |
1497 | } | |
1498 | ||
8364f9af II |
1499 | pdata = dev_get_platdata(&pdev->dev); |
1500 | if (!pdata) { | |
1501 | if (!np) | |
1502 | return -ENXIO; | |
1503 | ret = msm_otg_read_dt(pdev, motg); | |
1504 | if (ret) | |
1505 | return ret; | |
1506 | } | |
1507 | ||
6b99c68e II |
1508 | motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg), |
1509 | GFP_KERNEL); | |
1d4c9293 HK |
1510 | if (!motg->phy.otg) { |
1511 | dev_err(&pdev->dev, "unable to allocate msm_otg\n"); | |
6b99c68e | 1512 | return -ENOMEM; |
1d4c9293 HK |
1513 | } |
1514 | ||
1d4c9293 HK |
1515 | phy = &motg->phy; |
1516 | phy->dev = &pdev->dev; | |
e0c201f3 | 1517 | |
8364f9af II |
1518 | motg->phy_reset_clk = devm_clk_get(&pdev->dev, |
1519 | np ? "phy" : "usb_phy_clk"); | |
e0c201f3 PK |
1520 | if (IS_ERR(motg->phy_reset_clk)) { |
1521 | dev_err(&pdev->dev, "failed to get usb_phy_clk\n"); | |
6b99c68e | 1522 | return PTR_ERR(motg->phy_reset_clk); |
e0c201f3 PK |
1523 | } |
1524 | ||
8364f9af | 1525 | motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk"); |
e0c201f3 PK |
1526 | if (IS_ERR(motg->clk)) { |
1527 | dev_err(&pdev->dev, "failed to get usb_hs_clk\n"); | |
6b99c68e | 1528 | return PTR_ERR(motg->clk); |
e0c201f3 | 1529 | } |
0f73cac8 A |
1530 | |
1531 | /* | |
1532 | * If USB Core is running its protocol engine based on CORE CLK, | |
1533 | * CORE CLK must be running at >55Mhz for correct HSUSB | |
1534 | * operation and USB core cannot tolerate frequency changes on | |
ff0e4a68 | 1535 | * CORE CLK. |
0f73cac8 | 1536 | */ |
8364f9af | 1537 | motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk"); |
e0c201f3 PK |
1538 | if (IS_ERR(motg->pclk)) { |
1539 | dev_err(&pdev->dev, "failed to get usb_hs_pclk\n"); | |
6b99c68e | 1540 | return PTR_ERR(motg->pclk); |
e0c201f3 PK |
1541 | } |
1542 | ||
1543 | /* | |
1544 | * USB core clock is not present on all MSM chips. This | |
1545 | * clock is introduced to remove the dependency on AXI | |
1546 | * bus frequency. | |
1547 | */ | |
8364f9af II |
1548 | motg->core_clk = devm_clk_get(&pdev->dev, |
1549 | np ? "alt_core" : "usb_hs_core_clk"); | |
e0c201f3 PK |
1550 | |
1551 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
6b99c68e II |
1552 | motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
1553 | if (IS_ERR(motg->regs)) | |
1554 | return PTR_ERR(motg->regs); | |
e0c201f3 | 1555 | |
e0c201f3 PK |
1556 | dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs); |
1557 | ||
1558 | motg->irq = platform_get_irq(pdev, 0); | |
f60c114a | 1559 | if (motg->irq < 0) { |
e0c201f3 | 1560 | dev_err(&pdev->dev, "platform_get_irq failed\n"); |
6b99c68e II |
1561 | return motg->irq; |
1562 | } | |
1563 | ||
f5ef2372 II |
1564 | regs[0].supply = "vddcx"; |
1565 | regs[1].supply = "v3p3"; | |
1566 | regs[2].supply = "v1p8"; | |
6b99c68e II |
1567 | |
1568 | ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs); | |
1569 | if (ret) | |
1570 | return ret; | |
1571 | ||
1572 | motg->vddcx = regs[0].consumer; | |
1573 | motg->v3p3 = regs[1].consumer; | |
1574 | motg->v1p8 = regs[2].consumer; | |
1575 | ||
1576 | clk_set_rate(motg->clk, 60000000); | |
e0c201f3 | 1577 | |
b99a8f62 SB |
1578 | clk_prepare_enable(motg->clk); |
1579 | clk_prepare_enable(motg->pclk); | |
11aa5c47 | 1580 | |
6b99c68e II |
1581 | if (!IS_ERR(motg->core_clk)) |
1582 | clk_prepare_enable(motg->core_clk); | |
1583 | ||
11aa5c47 A |
1584 | ret = msm_hsusb_init_vddcx(motg, 1); |
1585 | if (ret) { | |
1586 | dev_err(&pdev->dev, "hsusb vddcx configuration failed\n"); | |
6b99c68e | 1587 | goto disable_clks; |
11aa5c47 A |
1588 | } |
1589 | ||
1590 | ret = msm_hsusb_ldo_init(motg, 1); | |
1591 | if (ret) { | |
1592 | dev_err(&pdev->dev, "hsusb vreg configuration failed\n"); | |
6b99c68e | 1593 | goto disable_vddcx; |
11aa5c47 | 1594 | } |
37cfdaf7 | 1595 | ret = msm_hsusb_ldo_set_mode(motg, 1); |
11aa5c47 A |
1596 | if (ret) { |
1597 | dev_err(&pdev->dev, "hsusb vreg enable failed\n"); | |
6b99c68e | 1598 | goto disable_ldo; |
11aa5c47 A |
1599 | } |
1600 | ||
e0c201f3 PK |
1601 | writel(0, USB_USBINTR); |
1602 | writel(0, USB_OTGSC); | |
1603 | ||
1604 | INIT_WORK(&motg->sm_work, msm_otg_sm_work); | |
d860852e | 1605 | INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work); |
6b99c68e | 1606 | ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED, |
e0c201f3 PK |
1607 | "msm_otg", motg); |
1608 | if (ret) { | |
1609 | dev_err(&pdev->dev, "request irq failed\n"); | |
6b99c68e | 1610 | goto disable_ldo; |
e0c201f3 PK |
1611 | } |
1612 | ||
d69c6f5d | 1613 | phy->init = msm_phy_init; |
1d4c9293 HK |
1614 | phy->set_power = msm_otg_set_power; |
1615 | ||
1616 | phy->io_ops = &msm_otg_io_ops; | |
e0c201f3 | 1617 | |
1d4c9293 HK |
1618 | phy->otg->phy = &motg->phy; |
1619 | phy->otg->set_host = msm_otg_set_host; | |
1620 | phy->otg->set_peripheral = msm_otg_set_peripheral; | |
e0c201f3 | 1621 | |
d69c6f5d II |
1622 | msm_usb_reset(phy); |
1623 | ||
662dca54 | 1624 | ret = usb_add_phy(&motg->phy, USB_PHY_TYPE_USB2); |
e0c201f3 | 1625 | if (ret) { |
721002ec | 1626 | dev_err(&pdev->dev, "usb_add_phy failed\n"); |
6b99c68e | 1627 | goto disable_ldo; |
e0c201f3 PK |
1628 | } |
1629 | ||
1630 | platform_set_drvdata(pdev, motg); | |
1631 | device_init_wakeup(&pdev->dev, 1); | |
1632 | ||
971232cf | 1633 | if (motg->pdata->mode == USB_DR_MODE_OTG && |
8364f9af | 1634 | motg->pdata->otg_control == OTG_USER_CONTROL) { |
e0c201f3 PK |
1635 | ret = msm_otg_debugfs_init(motg); |
1636 | if (ret) | |
3aca0fa9 | 1637 | dev_dbg(&pdev->dev, "Can not create mode change file\n"); |
e0c201f3 PK |
1638 | } |
1639 | ||
87c0104a PK |
1640 | pm_runtime_set_active(&pdev->dev); |
1641 | pm_runtime_enable(&pdev->dev); | |
e0c201f3 | 1642 | |
87c0104a | 1643 | return 0; |
6b99c68e II |
1644 | |
1645 | disable_ldo: | |
1646 | msm_hsusb_ldo_init(motg, 0); | |
1647 | disable_vddcx: | |
1648 | msm_hsusb_init_vddcx(motg, 0); | |
e0c201f3 | 1649 | disable_clks: |
b99a8f62 SB |
1650 | clk_disable_unprepare(motg->pclk); |
1651 | clk_disable_unprepare(motg->clk); | |
6b99c68e II |
1652 | if (!IS_ERR(motg->core_clk)) |
1653 | clk_disable_unprepare(motg->core_clk); | |
e0c201f3 PK |
1654 | return ret; |
1655 | } | |
1656 | ||
fb4e98ab | 1657 | static int msm_otg_remove(struct platform_device *pdev) |
e0c201f3 PK |
1658 | { |
1659 | struct msm_otg *motg = platform_get_drvdata(pdev); | |
1d4c9293 | 1660 | struct usb_phy *phy = &motg->phy; |
87c0104a | 1661 | int cnt = 0; |
e0c201f3 | 1662 | |
1d4c9293 | 1663 | if (phy->otg->host || phy->otg->gadget) |
e0c201f3 PK |
1664 | return -EBUSY; |
1665 | ||
1666 | msm_otg_debugfs_cleanup(); | |
d860852e | 1667 | cancel_delayed_work_sync(&motg->chg_work); |
e0c201f3 | 1668 | cancel_work_sync(&motg->sm_work); |
87c0104a | 1669 | |
7018773a | 1670 | pm_runtime_resume(&pdev->dev); |
87c0104a | 1671 | |
e0c201f3 | 1672 | device_init_wakeup(&pdev->dev, 0); |
87c0104a | 1673 | pm_runtime_disable(&pdev->dev); |
e0c201f3 | 1674 | |
662dca54 | 1675 | usb_remove_phy(phy); |
6b99c68e | 1676 | disable_irq(motg->irq); |
e0c201f3 | 1677 | |
87c0104a PK |
1678 | /* |
1679 | * Put PHY in low power mode. | |
1680 | */ | |
1d4c9293 HK |
1681 | ulpi_read(phy, 0x14); |
1682 | ulpi_write(phy, 0x08, 0x09); | |
87c0104a PK |
1683 | |
1684 | writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC); | |
1685 | while (cnt < PHY_SUSPEND_TIMEOUT_USEC) { | |
1686 | if (readl(USB_PORTSC) & PORTSC_PHCD) | |
1687 | break; | |
1688 | udelay(1); | |
1689 | cnt++; | |
1690 | } | |
1691 | if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) | |
1d4c9293 | 1692 | dev_err(phy->dev, "Unable to suspend PHY\n"); |
87c0104a | 1693 | |
b99a8f62 SB |
1694 | clk_disable_unprepare(motg->pclk); |
1695 | clk_disable_unprepare(motg->clk); | |
6b99c68e | 1696 | if (!IS_ERR(motg->core_clk)) |
b99a8f62 | 1697 | clk_disable_unprepare(motg->core_clk); |
11aa5c47 | 1698 | msm_hsusb_ldo_init(motg, 0); |
e0c201f3 | 1699 | |
87c0104a | 1700 | pm_runtime_set_suspended(&pdev->dev); |
e0c201f3 | 1701 | |
e0c201f3 PK |
1702 | return 0; |
1703 | } | |
1704 | ||
87c0104a PK |
1705 | #ifdef CONFIG_PM_RUNTIME |
1706 | static int msm_otg_runtime_idle(struct device *dev) | |
1707 | { | |
1708 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1d4c9293 | 1709 | struct usb_otg *otg = motg->phy.otg; |
87c0104a PK |
1710 | |
1711 | dev_dbg(dev, "OTG runtime idle\n"); | |
1712 | ||
1713 | /* | |
1714 | * It is observed some times that a spurious interrupt | |
1715 | * comes when PHY is put into LPM immediately after PHY reset. | |
1716 | * This 1 sec delay also prevents entering into LPM immediately | |
1717 | * after asynchronous interrupt. | |
1718 | */ | |
1d4c9293 | 1719 | if (otg->phy->state != OTG_STATE_UNDEFINED) |
87c0104a PK |
1720 | pm_schedule_suspend(dev, 1000); |
1721 | ||
1722 | return -EAGAIN; | |
1723 | } | |
1724 | ||
1725 | static int msm_otg_runtime_suspend(struct device *dev) | |
1726 | { | |
1727 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1728 | ||
1729 | dev_dbg(dev, "OTG runtime suspend\n"); | |
1730 | return msm_otg_suspend(motg); | |
1731 | } | |
1732 | ||
1733 | static int msm_otg_runtime_resume(struct device *dev) | |
1734 | { | |
1735 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1736 | ||
1737 | dev_dbg(dev, "OTG runtime resume\n"); | |
1738 | return msm_otg_resume(motg); | |
1739 | } | |
87c0104a PK |
1740 | #endif |
1741 | ||
7018773a | 1742 | #ifdef CONFIG_PM_SLEEP |
87c0104a PK |
1743 | static int msm_otg_pm_suspend(struct device *dev) |
1744 | { | |
1745 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1746 | ||
1747 | dev_dbg(dev, "OTG PM suspend\n"); | |
1748 | return msm_otg_suspend(motg); | |
1749 | } | |
1750 | ||
1751 | static int msm_otg_pm_resume(struct device *dev) | |
1752 | { | |
1753 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1754 | int ret; | |
1755 | ||
1756 | dev_dbg(dev, "OTG PM resume\n"); | |
1757 | ||
1758 | ret = msm_otg_resume(motg); | |
1759 | if (ret) | |
1760 | return ret; | |
1761 | ||
1762 | /* | |
1763 | * Runtime PM Documentation recommends bringing the | |
1764 | * device to full powered state upon resume. | |
1765 | */ | |
1766 | pm_runtime_disable(dev); | |
1767 | pm_runtime_set_active(dev); | |
1768 | pm_runtime_enable(dev); | |
1769 | ||
1770 | return 0; | |
1771 | } | |
87c0104a PK |
1772 | #endif |
1773 | ||
1774 | static const struct dev_pm_ops msm_otg_dev_pm_ops = { | |
7018773a PK |
1775 | SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume) |
1776 | SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume, | |
1777 | msm_otg_runtime_idle) | |
87c0104a PK |
1778 | }; |
1779 | ||
e0c201f3 | 1780 | static struct platform_driver msm_otg_driver = { |
06a6ec44 | 1781 | .probe = msm_otg_probe, |
7690417d | 1782 | .remove = msm_otg_remove, |
e0c201f3 PK |
1783 | .driver = { |
1784 | .name = DRIVER_NAME, | |
1785 | .owner = THIS_MODULE, | |
87c0104a | 1786 | .pm = &msm_otg_dev_pm_ops, |
8364f9af | 1787 | .of_match_table = msm_otg_dt_match, |
e0c201f3 PK |
1788 | }, |
1789 | }; | |
1790 | ||
06a6ec44 | 1791 | module_platform_driver(msm_otg_driver); |
e0c201f3 PK |
1792 | |
1793 | MODULE_LICENSE("GPL v2"); | |
1794 | MODULE_DESCRIPTION("MSM USB transceiver driver"); |