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9ebd9616 DB |
1 | /* |
2 | * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller | |
3 | * | |
4 | * Copyright (C) 2004-2007 Texas Instruments | |
5 | * Copyright (C) 2008 Nokia Corporation | |
6 | * Contact: Felipe Balbi <felipe.balbi@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | * Current status: | |
23 | * - HS USB ULPI mode works. | |
24 | * - 3-pin mode support may be added in future. | |
25 | */ | |
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/workqueue.h> | |
33 | #include <linux/io.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/usb/otg.h> | |
c9721438 | 36 | #include <linux/usb/musb-omap.h> |
92a6e6b3 | 37 | #include <linux/usb/ulpi.h> |
b07682b6 | 38 | #include <linux/i2c/twl.h> |
66760169 JH |
39 | #include <linux/regulator/consumer.h> |
40 | #include <linux/err.h> | |
5a0e3ad6 | 41 | #include <linux/slab.h> |
9ebd9616 DB |
42 | |
43 | /* Register defines */ | |
44 | ||
9ebd9616 | 45 | #define MCPC_CTRL 0x30 |
9ebd9616 DB |
46 | #define MCPC_CTRL_RTSOL (1 << 7) |
47 | #define MCPC_CTRL_EXTSWR (1 << 6) | |
48 | #define MCPC_CTRL_EXTSWC (1 << 5) | |
49 | #define MCPC_CTRL_VOICESW (1 << 4) | |
50 | #define MCPC_CTRL_OUT64K (1 << 3) | |
51 | #define MCPC_CTRL_RTSCTSSW (1 << 2) | |
52 | #define MCPC_CTRL_HS_UART (1 << 0) | |
53 | ||
54 | #define MCPC_IO_CTRL 0x33 | |
9ebd9616 DB |
55 | #define MCPC_IO_CTRL_MICBIASEN (1 << 5) |
56 | #define MCPC_IO_CTRL_CTS_NPU (1 << 4) | |
57 | #define MCPC_IO_CTRL_RXD_PU (1 << 3) | |
58 | #define MCPC_IO_CTRL_TXDTYP (1 << 2) | |
59 | #define MCPC_IO_CTRL_CTSTYP (1 << 1) | |
60 | #define MCPC_IO_CTRL_RTSTYP (1 << 0) | |
61 | ||
62 | #define MCPC_CTRL2 0x36 | |
9ebd9616 DB |
63 | #define MCPC_CTRL2_MCPC_CK_EN (1 << 0) |
64 | ||
65 | #define OTHER_FUNC_CTRL 0x80 | |
9ebd9616 DB |
66 | #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4) |
67 | #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2) | |
68 | ||
69 | #define OTHER_IFC_CTRL 0x83 | |
9ebd9616 DB |
70 | #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6) |
71 | #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5) | |
72 | #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4) | |
73 | #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3) | |
74 | #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2) | |
75 | #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0) | |
76 | ||
77 | #define OTHER_INT_EN_RISE 0x86 | |
9ebd9616 | 78 | #define OTHER_INT_EN_FALL 0x89 |
9ebd9616 DB |
79 | #define OTHER_INT_STS 0x8C |
80 | #define OTHER_INT_LATCH 0x8D | |
81 | #define OTHER_INT_VB_SESS_VLD (1 << 7) | |
82 | #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */ | |
83 | #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */ | |
84 | #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */ | |
85 | #define OTHER_INT_MANU (1 << 1) | |
86 | #define OTHER_INT_ABNORMAL_STRESS (1 << 0) | |
87 | ||
88 | #define ID_STATUS 0x96 | |
89 | #define ID_RES_FLOAT (1 << 4) | |
90 | #define ID_RES_440K (1 << 3) | |
91 | #define ID_RES_200K (1 << 2) | |
92 | #define ID_RES_102K (1 << 1) | |
93 | #define ID_RES_GND (1 << 0) | |
94 | ||
95 | #define POWER_CTRL 0xAC | |
9ebd9616 DB |
96 | #define POWER_CTRL_OTG_ENAB (1 << 5) |
97 | ||
98 | #define OTHER_IFC_CTRL2 0xAF | |
9ebd9616 DB |
99 | #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4) |
100 | #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3) | |
101 | #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2) | |
102 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */ | |
103 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0) | |
104 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0) | |
105 | ||
106 | #define REG_CTRL_EN 0xB2 | |
9ebd9616 DB |
107 | #define REG_CTRL_ERROR 0xB5 |
108 | #define ULPI_I2C_CONFLICT_INTEN (1 << 0) | |
109 | ||
110 | #define OTHER_FUNC_CTRL2 0xB8 | |
9ebd9616 DB |
111 | #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0) |
112 | ||
113 | /* following registers do not have separate _clr and _set registers */ | |
114 | #define VBUS_DEBOUNCE 0xC0 | |
115 | #define ID_DEBOUNCE 0xC1 | |
116 | #define VBAT_TIMER 0xD3 | |
117 | #define PHY_PWR_CTRL 0xFD | |
118 | #define PHY_PWR_PHYPWD (1 << 0) | |
119 | #define PHY_CLK_CTRL 0xFE | |
120 | #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2) | |
121 | #define PHY_CLK_CTRL_CLK32K_EN (1 << 1) | |
122 | #define REQ_PHY_DPLL_CLK (1 << 0) | |
123 | #define PHY_CLK_CTRL_STS 0xFF | |
124 | #define PHY_DPLL_CLK (1 << 0) | |
125 | ||
9d94e16b | 126 | /* In module TWL_MODULE_PM_MASTER */ |
def6f8b9 | 127 | #define STS_HW_CONDITIONS 0x0F |
9ebd9616 | 128 | |
9d94e16b | 129 | /* In module TWL_MODULE_PM_RECEIVER */ |
9ebd9616 DB |
130 | #define VUSB_DEDICATED1 0x7D |
131 | #define VUSB_DEDICATED2 0x7E | |
132 | #define VUSB1V5_DEV_GRP 0x71 | |
133 | #define VUSB1V5_TYPE 0x72 | |
134 | #define VUSB1V5_REMAP 0x73 | |
135 | #define VUSB1V8_DEV_GRP 0x74 | |
136 | #define VUSB1V8_TYPE 0x75 | |
137 | #define VUSB1V8_REMAP 0x76 | |
138 | #define VUSB3V1_DEV_GRP 0x77 | |
139 | #define VUSB3V1_TYPE 0x78 | |
140 | #define VUSB3V1_REMAP 0x79 | |
141 | ||
142 | /* In module TWL4030_MODULE_INTBR */ | |
143 | #define PMBR1 0x0D | |
144 | #define GPIO_USB_4PIN_ULPI_2430C (3 << 0) | |
145 | ||
9ebd9616 | 146 | struct twl4030_usb { |
74d4aa44 | 147 | struct usb_phy phy; |
9ebd9616 DB |
148 | struct device *dev; |
149 | ||
66760169 JH |
150 | /* TWL4030 internal USB regulator supplies */ |
151 | struct regulator *usb1v5; | |
152 | struct regulator *usb1v8; | |
153 | struct regulator *usb3v1; | |
154 | ||
9ebd9616 DB |
155 | /* for vbus reporting with irqs disabled */ |
156 | spinlock_t lock; | |
157 | ||
158 | /* pin configuration */ | |
159 | enum twl4030_usb_mode usb_mode; | |
160 | ||
161 | int irq; | |
c9721438 | 162 | enum omap_musb_vbus_id_status linkstat; |
a87103a6 | 163 | bool vbus_supplied; |
9ebd9616 DB |
164 | u8 asleep; |
165 | bool irq_enabled; | |
249751f2 GI |
166 | |
167 | struct delayed_work id_workaround_work; | |
9ebd9616 DB |
168 | }; |
169 | ||
170 | /* internal define on top of container_of */ | |
74d4aa44 | 171 | #define phy_to_twl(x) container_of((x), struct twl4030_usb, phy) |
9ebd9616 DB |
172 | |
173 | /*-------------------------------------------------------------------------*/ | |
174 | ||
175 | static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl, | |
176 | u8 module, u8 data, u8 address) | |
177 | { | |
178 | u8 check; | |
179 | ||
fc7b92fc B |
180 | if ((twl_i2c_write_u8(module, data, address) >= 0) && |
181 | (twl_i2c_read_u8(module, &check, address) >= 0) && | |
9ebd9616 DB |
182 | (check == data)) |
183 | return 0; | |
184 | dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n", | |
185 | 1, module, address, check, data); | |
186 | ||
187 | /* Failed once: Try again */ | |
fc7b92fc B |
188 | if ((twl_i2c_write_u8(module, data, address) >= 0) && |
189 | (twl_i2c_read_u8(module, &check, address) >= 0) && | |
9ebd9616 DB |
190 | (check == data)) |
191 | return 0; | |
192 | dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n", | |
193 | 2, module, address, check, data); | |
194 | ||
195 | /* Failed again: Return error */ | |
196 | return -EBUSY; | |
197 | } | |
198 | ||
199 | #define twl4030_usb_write_verify(twl, address, data) \ | |
9d94e16b | 200 | twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address)) |
9ebd9616 DB |
201 | |
202 | static inline int twl4030_usb_write(struct twl4030_usb *twl, | |
203 | u8 address, u8 data) | |
204 | { | |
205 | int ret = 0; | |
206 | ||
9d94e16b | 207 | ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address); |
9ebd9616 DB |
208 | if (ret < 0) |
209 | dev_dbg(twl->dev, | |
210 | "TWL4030:USB:Write[0x%x] Error %d\n", address, ret); | |
211 | return ret; | |
212 | } | |
213 | ||
214 | static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address) | |
215 | { | |
216 | u8 data; | |
217 | int ret = 0; | |
218 | ||
fc7b92fc | 219 | ret = twl_i2c_read_u8(module, &data, address); |
9ebd9616 DB |
220 | if (ret >= 0) |
221 | ret = data; | |
222 | else | |
223 | dev_dbg(twl->dev, | |
224 | "TWL4030:readb[0x%x,0x%x] Error %d\n", | |
225 | module, address, ret); | |
226 | ||
227 | return ret; | |
228 | } | |
229 | ||
230 | static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address) | |
231 | { | |
9d94e16b | 232 | return twl4030_readb(twl, TWL_MODULE_USB, address); |
9ebd9616 DB |
233 | } |
234 | ||
235 | /*-------------------------------------------------------------------------*/ | |
236 | ||
237 | static inline int | |
238 | twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits) | |
239 | { | |
92a6e6b3 | 240 | return twl4030_usb_write(twl, ULPI_SET(reg), bits); |
9ebd9616 DB |
241 | } |
242 | ||
243 | static inline int | |
244 | twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits) | |
245 | { | |
92a6e6b3 | 246 | return twl4030_usb_write(twl, ULPI_CLR(reg), bits); |
9ebd9616 DB |
247 | } |
248 | ||
249 | /*-------------------------------------------------------------------------*/ | |
250 | ||
c9721438 KVA |
251 | static enum omap_musb_vbus_id_status |
252 | twl4030_usb_linkstat(struct twl4030_usb *twl) | |
9ebd9616 DB |
253 | { |
254 | int status; | |
c9721438 | 255 | enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN; |
9ebd9616 | 256 | |
a87103a6 MK |
257 | twl->vbus_supplied = false; |
258 | ||
def6f8b9 DB |
259 | /* |
260 | * For ID/VBUS sensing, see manual section 15.4.8 ... | |
261 | * except when using only battery backup power, two | |
262 | * comparators produce VBUS_PRES and ID_PRES signals, | |
263 | * which don't match docs elsewhere. But ... BIT(7) | |
264 | * and BIT(2) of STS_HW_CONDITIONS, respectively, do | |
265 | * seem to match up. If either is true the USB_PRES | |
266 | * signal is active, the OTG module is activated, and | |
267 | * its interrupt may be raised (may wake the system). | |
268 | */ | |
9d94e16b | 269 | status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS); |
9ebd9616 DB |
270 | if (status < 0) |
271 | dev_err(twl->dev, "USB link status err %d\n", status); | |
def6f8b9 | 272 | else if (status & (BIT(7) | BIT(2))) { |
a87103a6 MK |
273 | if (status & (BIT(7))) |
274 | twl->vbus_supplied = true; | |
275 | ||
def6f8b9 | 276 | if (status & BIT(2)) |
c9721438 | 277 | linkstat = OMAP_MUSB_ID_GROUND; |
def6f8b9 | 278 | else |
c9721438 KVA |
279 | linkstat = OMAP_MUSB_VBUS_VALID; |
280 | } else { | |
281 | if (twl->linkstat != OMAP_MUSB_UNKNOWN) | |
282 | linkstat = OMAP_MUSB_VBUS_OFF; | |
283 | } | |
9ebd9616 DB |
284 | |
285 | dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n", | |
286 | status, status, linkstat); | |
287 | ||
288 | /* REVISIT this assumes host and peripheral controllers | |
289 | * are registered, and that both are active... | |
290 | */ | |
291 | ||
9ebd9616 DB |
292 | return linkstat; |
293 | } | |
294 | ||
295 | static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode) | |
296 | { | |
297 | twl->usb_mode = mode; | |
298 | ||
299 | switch (mode) { | |
300 | case T2_USB_MODE_ULPI: | |
92a6e6b3 HK |
301 | twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL, |
302 | ULPI_IFC_CTRL_CARKITMODE); | |
9ebd9616 | 303 | twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB); |
92a6e6b3 HK |
304 | twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL, |
305 | ULPI_FUNC_CTRL_XCVRSEL_MASK | | |
306 | ULPI_FUNC_CTRL_OPMODE_MASK); | |
9ebd9616 DB |
307 | break; |
308 | case -1: | |
309 | /* FIXME: power on defaults */ | |
310 | break; | |
311 | default: | |
312 | dev_err(twl->dev, "unsupported T2 transceiver mode %d\n", | |
313 | mode); | |
314 | break; | |
315 | }; | |
316 | } | |
317 | ||
318 | static void twl4030_i2c_access(struct twl4030_usb *twl, int on) | |
319 | { | |
320 | unsigned long timeout; | |
321 | int val = twl4030_usb_read(twl, PHY_CLK_CTRL); | |
322 | ||
323 | if (val >= 0) { | |
324 | if (on) { | |
325 | /* enable DPLL to access PHY registers over I2C */ | |
326 | val |= REQ_PHY_DPLL_CLK; | |
327 | WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, | |
328 | (u8)val) < 0); | |
329 | ||
330 | timeout = jiffies + HZ; | |
331 | while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & | |
332 | PHY_DPLL_CLK) | |
333 | && time_before(jiffies, timeout)) | |
334 | udelay(10); | |
335 | if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & | |
336 | PHY_DPLL_CLK)) | |
337 | dev_err(twl->dev, "Timeout setting T2 HSUSB " | |
338 | "PHY DPLL clock\n"); | |
339 | } else { | |
340 | /* let ULPI control the DPLL clock */ | |
341 | val &= ~REQ_PHY_DPLL_CLK; | |
342 | WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, | |
343 | (u8)val) < 0); | |
344 | } | |
345 | } | |
346 | } | |
347 | ||
fc8f2a76 | 348 | static void __twl4030_phy_power(struct twl4030_usb *twl, int on) |
9ebd9616 | 349 | { |
fc8f2a76 ML |
350 | u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL); |
351 | ||
352 | if (on) | |
353 | pwr &= ~PHY_PWR_PHYPWD; | |
354 | else | |
355 | pwr |= PHY_PWR_PHYPWD; | |
9ebd9616 | 356 | |
fc8f2a76 ML |
357 | WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); |
358 | } | |
359 | ||
360 | static void twl4030_phy_power(struct twl4030_usb *twl, int on) | |
361 | { | |
9ebd9616 | 362 | if (on) { |
66760169 JH |
363 | regulator_enable(twl->usb3v1); |
364 | regulator_enable(twl->usb1v8); | |
365 | /* | |
366 | * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP | |
367 | * in twl4030) resets the VUSB_DEDICATED2 register. This reset | |
368 | * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to | |
369 | * SLEEP. We work around this by clearing the bit after usv3v1 | |
370 | * is re-activated. This ensures that VUSB3V1 is really active. | |
371 | */ | |
9d94e16b | 372 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2); |
66760169 | 373 | regulator_enable(twl->usb1v5); |
fc8f2a76 | 374 | __twl4030_phy_power(twl, 1); |
9ebd9616 DB |
375 | twl4030_usb_write(twl, PHY_CLK_CTRL, |
376 | twl4030_usb_read(twl, PHY_CLK_CTRL) | | |
377 | (PHY_CLK_CTRL_CLOCKGATING_EN | | |
378 | PHY_CLK_CTRL_CLK32K_EN)); | |
fc8f2a76 ML |
379 | } else { |
380 | __twl4030_phy_power(twl, 0); | |
66760169 JH |
381 | regulator_disable(twl->usb1v5); |
382 | regulator_disable(twl->usb1v8); | |
383 | regulator_disable(twl->usb3v1); | |
9ebd9616 DB |
384 | } |
385 | } | |
386 | ||
387 | static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off) | |
388 | { | |
389 | if (twl->asleep) | |
390 | return; | |
391 | ||
392 | twl4030_phy_power(twl, 0); | |
393 | twl->asleep = 1; | |
fc8f2a76 | 394 | dev_dbg(twl->dev, "%s\n", __func__); |
9ebd9616 DB |
395 | } |
396 | ||
fc8f2a76 | 397 | static void __twl4030_phy_resume(struct twl4030_usb *twl) |
9ebd9616 | 398 | { |
9ebd9616 DB |
399 | twl4030_phy_power(twl, 1); |
400 | twl4030_i2c_access(twl, 1); | |
401 | twl4030_usb_set_mode(twl, twl->usb_mode); | |
402 | if (twl->usb_mode == T2_USB_MODE_ULPI) | |
403 | twl4030_i2c_access(twl, 0); | |
fc8f2a76 ML |
404 | } |
405 | ||
406 | static void twl4030_phy_resume(struct twl4030_usb *twl) | |
407 | { | |
408 | if (!twl->asleep) | |
409 | return; | |
410 | __twl4030_phy_resume(twl); | |
9ebd9616 | 411 | twl->asleep = 0; |
fc8f2a76 | 412 | dev_dbg(twl->dev, "%s\n", __func__); |
249751f2 GI |
413 | |
414 | /* | |
415 | * XXX When VBUS gets driven after musb goes to A mode, | |
416 | * ID_PRES related interrupts no longer arrive, why? | |
417 | * Register itself is updated fine though, so we must poll. | |
418 | */ | |
419 | if (twl->linkstat == OMAP_MUSB_ID_GROUND) { | |
420 | cancel_delayed_work(&twl->id_workaround_work); | |
421 | schedule_delayed_work(&twl->id_workaround_work, HZ); | |
422 | } | |
9ebd9616 DB |
423 | } |
424 | ||
66760169 | 425 | static int twl4030_usb_ldo_init(struct twl4030_usb *twl) |
9ebd9616 DB |
426 | { |
427 | /* Enable writing to power configuration registers */ | |
9d94e16b PU |
428 | twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1, |
429 | TWL4030_PM_MASTER_PROTECT_KEY); | |
e7944d82 | 430 | |
9d94e16b PU |
431 | twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2, |
432 | TWL4030_PM_MASTER_PROTECT_KEY); | |
9ebd9616 | 433 | |
fc8f2a76 | 434 | /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/ |
9d94e16b | 435 | /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/ |
9ebd9616 DB |
436 | |
437 | /* input to VUSB3V1 LDO is from VBAT, not VBUS */ | |
9d94e16b | 438 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1); |
9ebd9616 | 439 | |
66760169 | 440 | /* Initialize 3.1V regulator */ |
9d94e16b | 441 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP); |
66760169 | 442 | |
9166902c | 443 | twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1"); |
66760169 JH |
444 | if (IS_ERR(twl->usb3v1)) |
445 | return -ENODEV; | |
446 | ||
9d94e16b | 447 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE); |
9ebd9616 | 448 | |
66760169 | 449 | /* Initialize 1.5V regulator */ |
9d94e16b | 450 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP); |
66760169 | 451 | |
9166902c | 452 | twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5"); |
66760169 | 453 | if (IS_ERR(twl->usb1v5)) |
9166902c | 454 | return -ENODEV; |
66760169 | 455 | |
9d94e16b | 456 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE); |
9ebd9616 | 457 | |
66760169 | 458 | /* Initialize 1.8V regulator */ |
9d94e16b | 459 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP); |
66760169 | 460 | |
9166902c | 461 | twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8"); |
66760169 | 462 | if (IS_ERR(twl->usb1v8)) |
9166902c | 463 | return -ENODEV; |
66760169 | 464 | |
9d94e16b | 465 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE); |
9ebd9616 DB |
466 | |
467 | /* disable access to power configuration registers */ | |
9d94e16b PU |
468 | twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0, |
469 | TWL4030_PM_MASTER_PROTECT_KEY); | |
66760169 JH |
470 | |
471 | return 0; | |
9ebd9616 DB |
472 | } |
473 | ||
474 | static ssize_t twl4030_usb_vbus_show(struct device *dev, | |
475 | struct device_attribute *attr, char *buf) | |
476 | { | |
477 | struct twl4030_usb *twl = dev_get_drvdata(dev); | |
478 | unsigned long flags; | |
479 | int ret = -EINVAL; | |
480 | ||
481 | spin_lock_irqsave(&twl->lock, flags); | |
482 | ret = sprintf(buf, "%s\n", | |
a87103a6 | 483 | twl->vbus_supplied ? "on" : "off"); |
9ebd9616 DB |
484 | spin_unlock_irqrestore(&twl->lock, flags); |
485 | ||
486 | return ret; | |
487 | } | |
488 | static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL); | |
489 | ||
490 | static irqreturn_t twl4030_usb_irq(int irq, void *_twl) | |
491 | { | |
492 | struct twl4030_usb *twl = _twl; | |
c9721438 | 493 | enum omap_musb_vbus_id_status status; |
249751f2 | 494 | bool status_changed = false; |
9ebd9616 | 495 | |
9ebd9616 | 496 | status = twl4030_usb_linkstat(twl); |
249751f2 GI |
497 | |
498 | spin_lock_irq(&twl->lock); | |
499 | if (status >= 0 && status != twl->linkstat) { | |
500 | twl->linkstat = status; | |
501 | status_changed = true; | |
502 | } | |
503 | spin_unlock_irq(&twl->lock); | |
504 | ||
505 | if (status_changed) { | |
9ebd9616 DB |
506 | /* FIXME add a set_power() method so that B-devices can |
507 | * configure the charger appropriately. It's not always | |
508 | * correct to consume VBUS power, and how much current to | |
509 | * consume is a function of the USB configuration chosen | |
510 | * by the host. | |
511 | * | |
512 | * REVISIT usb_gadget_vbus_connect(...) as needed, ditto | |
513 | * its disconnect() sibling, when changing to/from the | |
514 | * USB_LINK_VBUS state. musb_hdrc won't care until it | |
515 | * starts to handle softconnect right. | |
516 | */ | |
249751f2 | 517 | omap_musb_mailbox(status); |
9ebd9616 DB |
518 | } |
519 | sysfs_notify(&twl->dev->kobj, NULL, "vbus"); | |
520 | ||
521 | return IRQ_HANDLED; | |
522 | } | |
523 | ||
249751f2 GI |
524 | static void twl4030_id_workaround_work(struct work_struct *work) |
525 | { | |
526 | struct twl4030_usb *twl = container_of(work, struct twl4030_usb, | |
527 | id_workaround_work.work); | |
528 | enum omap_musb_vbus_id_status status; | |
529 | bool status_changed = false; | |
530 | ||
531 | status = twl4030_usb_linkstat(twl); | |
532 | ||
533 | spin_lock_irq(&twl->lock); | |
534 | if (status >= 0 && status != twl->linkstat) { | |
535 | twl->linkstat = status; | |
536 | status_changed = true; | |
537 | } | |
538 | spin_unlock_irq(&twl->lock); | |
539 | ||
540 | if (status_changed) { | |
541 | dev_dbg(twl->dev, "handle missing status change to %d\n", | |
542 | status); | |
543 | omap_musb_mailbox(status); | |
544 | } | |
545 | ||
546 | /* don't schedule during sleep - irq works right then */ | |
547 | if (status == OMAP_MUSB_ID_GROUND && !twl->asleep) { | |
548 | cancel_delayed_work(&twl->id_workaround_work); | |
549 | schedule_delayed_work(&twl->id_workaround_work, HZ); | |
550 | } | |
551 | } | |
552 | ||
817e5f33 | 553 | static int twl4030_usb_phy_init(struct usb_phy *phy) |
fc8f2a76 | 554 | { |
817e5f33 | 555 | struct twl4030_usb *twl = phy_to_twl(phy); |
c9721438 | 556 | enum omap_musb_vbus_id_status status; |
fc8f2a76 | 557 | |
44a50d08 GI |
558 | /* |
559 | * Start in sleep state, we'll get called through set_suspend() | |
560 | * callback when musb is runtime resumed and it's time to start. | |
561 | */ | |
562 | __twl4030_phy_power(twl, 0); | |
563 | twl->asleep = 1; | |
fc8f2a76 | 564 | |
44a50d08 | 565 | status = twl4030_usb_linkstat(twl); |
249751f2 GI |
566 | twl->linkstat = status; |
567 | ||
ca4f70ce | 568 | if (status == OMAP_MUSB_ID_GROUND || status == OMAP_MUSB_VBUS_VALID) |
c9721438 | 569 | omap_musb_mailbox(twl->linkstat); |
44a50d08 | 570 | |
fc8f2a76 | 571 | sysfs_notify(&twl->dev->kobj, NULL, "vbus"); |
817e5f33 | 572 | return 0; |
fc8f2a76 ML |
573 | } |
574 | ||
86753811 | 575 | static int twl4030_set_suspend(struct usb_phy *x, int suspend) |
9ebd9616 | 576 | { |
74d4aa44 | 577 | struct twl4030_usb *twl = phy_to_twl(x); |
9ebd9616 DB |
578 | |
579 | if (suspend) | |
580 | twl4030_phy_suspend(twl, 1); | |
581 | else | |
582 | twl4030_phy_resume(twl); | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
74d4aa44 HK |
587 | static int twl4030_set_peripheral(struct usb_otg *otg, |
588 | struct usb_gadget *gadget) | |
9ebd9616 | 589 | { |
74d4aa44 | 590 | if (!otg) |
9ebd9616 DB |
591 | return -ENODEV; |
592 | ||
74d4aa44 | 593 | otg->gadget = gadget; |
9ebd9616 | 594 | if (!gadget) |
74d4aa44 | 595 | otg->phy->state = OTG_STATE_UNDEFINED; |
9ebd9616 DB |
596 | |
597 | return 0; | |
598 | } | |
599 | ||
74d4aa44 | 600 | static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host) |
9ebd9616 | 601 | { |
74d4aa44 | 602 | if (!otg) |
9ebd9616 DB |
603 | return -ENODEV; |
604 | ||
74d4aa44 | 605 | otg->host = host; |
9ebd9616 | 606 | if (!host) |
74d4aa44 | 607 | otg->phy->state = OTG_STATE_UNDEFINED; |
9ebd9616 DB |
608 | |
609 | return 0; | |
610 | } | |
611 | ||
41ac7b3a | 612 | static int twl4030_usb_probe(struct platform_device *pdev) |
9ebd9616 DB |
613 | { |
614 | struct twl4030_usb_data *pdata = pdev->dev.platform_data; | |
615 | struct twl4030_usb *twl; | |
66760169 | 616 | int status, err; |
74d4aa44 | 617 | struct usb_otg *otg; |
f8515f06 | 618 | struct device_node *np = pdev->dev.of_node; |
9ebd9616 | 619 | |
b8a3efa3 | 620 | twl = devm_kzalloc(&pdev->dev, sizeof *twl, GFP_KERNEL); |
9ebd9616 DB |
621 | if (!twl) |
622 | return -ENOMEM; | |
623 | ||
f8515f06 KVA |
624 | if (np) |
625 | of_property_read_u32(np, "usb_mode", | |
626 | (enum twl4030_usb_mode *)&twl->usb_mode); | |
627 | else if (pdata) | |
628 | twl->usb_mode = pdata->usb_mode; | |
629 | else { | |
630 | dev_err(&pdev->dev, "twl4030 initialized without pdata\n"); | |
631 | return -EINVAL; | |
632 | } | |
633 | ||
b8a3efa3 KVA |
634 | otg = devm_kzalloc(&pdev->dev, sizeof *otg, GFP_KERNEL); |
635 | if (!otg) | |
74d4aa44 | 636 | return -ENOMEM; |
74d4aa44 | 637 | |
9ebd9616 DB |
638 | twl->dev = &pdev->dev; |
639 | twl->irq = platform_get_irq(pdev, 0); | |
a87103a6 | 640 | twl->vbus_supplied = false; |
74d4aa44 | 641 | twl->asleep = 1; |
c9721438 | 642 | twl->linkstat = OMAP_MUSB_UNKNOWN; |
74d4aa44 HK |
643 | |
644 | twl->phy.dev = twl->dev; | |
645 | twl->phy.label = "twl4030"; | |
646 | twl->phy.otg = otg; | |
c11747f6 | 647 | twl->phy.type = USB_PHY_TYPE_USB2; |
74d4aa44 | 648 | twl->phy.set_suspend = twl4030_set_suspend; |
817e5f33 | 649 | twl->phy.init = twl4030_usb_phy_init; |
74d4aa44 HK |
650 | |
651 | otg->phy = &twl->phy; | |
652 | otg->set_host = twl4030_set_host; | |
653 | otg->set_peripheral = twl4030_set_peripheral; | |
9ebd9616 DB |
654 | |
655 | /* init spinlock for workqueue */ | |
656 | spin_lock_init(&twl->lock); | |
657 | ||
249751f2 GI |
658 | INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work); |
659 | ||
66760169 JH |
660 | err = twl4030_usb_ldo_init(twl); |
661 | if (err) { | |
662 | dev_err(&pdev->dev, "ldo init failed\n"); | |
66760169 JH |
663 | return err; |
664 | } | |
c11747f6 | 665 | usb_add_phy_dev(&twl->phy); |
9ebd9616 DB |
666 | |
667 | platform_set_drvdata(pdev, twl); | |
668 | if (device_create_file(&pdev->dev, &dev_attr_vbus)) | |
669 | dev_warn(&pdev->dev, "could not create sysfs file\n"); | |
670 | ||
671 | /* Our job is to use irqs and status from the power module | |
672 | * to keep the transceiver disabled when nothing's connected. | |
673 | * | |
674 | * FIXME we actually shouldn't start enabling it until the | |
675 | * USB controller drivers have said they're ready, by calling | |
676 | * set_host() and/or set_peripheral() ... OTG_capable boards | |
677 | * need both handles, otherwise just one suffices. | |
678 | */ | |
679 | twl->irq_enabled = true; | |
9166902c KVA |
680 | status = devm_request_threaded_irq(twl->dev, twl->irq, NULL, |
681 | twl4030_usb_irq, IRQF_TRIGGER_FALLING | | |
682 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl); | |
9ebd9616 DB |
683 | if (status < 0) { |
684 | dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n", | |
685 | twl->irq, status); | |
9ebd9616 DB |
686 | return status; |
687 | } | |
688 | ||
9ebd9616 DB |
689 | dev_info(&pdev->dev, "Initialized TWL4030 USB module\n"); |
690 | return 0; | |
691 | } | |
692 | ||
693 | static int __exit twl4030_usb_remove(struct platform_device *pdev) | |
694 | { | |
695 | struct twl4030_usb *twl = platform_get_drvdata(pdev); | |
696 | int val; | |
697 | ||
249751f2 | 698 | cancel_delayed_work(&twl->id_workaround_work); |
9ebd9616 DB |
699 | device_remove_file(twl->dev, &dev_attr_vbus); |
700 | ||
701 | /* set transceiver mode to power on defaults */ | |
702 | twl4030_usb_set_mode(twl, -1); | |
703 | ||
704 | /* autogate 60MHz ULPI clock, | |
705 | * clear dpll clock request for i2c access, | |
706 | * disable 32KHz | |
707 | */ | |
708 | val = twl4030_usb_read(twl, PHY_CLK_CTRL); | |
709 | if (val >= 0) { | |
710 | val |= PHY_CLK_CTRL_CLOCKGATING_EN; | |
711 | val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK); | |
712 | twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val); | |
713 | } | |
714 | ||
715 | /* disable complete OTG block */ | |
716 | twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB); | |
717 | ||
c3d6450e JN |
718 | if (!twl->asleep) |
719 | twl4030_phy_power(twl, 0); | |
9ebd9616 | 720 | |
9ebd9616 DB |
721 | return 0; |
722 | } | |
723 | ||
f8515f06 KVA |
724 | #ifdef CONFIG_OF |
725 | static const struct of_device_id twl4030_usb_id_table[] = { | |
726 | { .compatible = "ti,twl4030-usb" }, | |
727 | {} | |
728 | }; | |
729 | MODULE_DEVICE_TABLE(of, twl4030_usb_id_table); | |
730 | #endif | |
731 | ||
9ebd9616 DB |
732 | static struct platform_driver twl4030_usb_driver = { |
733 | .probe = twl4030_usb_probe, | |
734 | .remove = __exit_p(twl4030_usb_remove), | |
735 | .driver = { | |
736 | .name = "twl4030_usb", | |
737 | .owner = THIS_MODULE, | |
f8515f06 | 738 | .of_match_table = of_match_ptr(twl4030_usb_id_table), |
9ebd9616 DB |
739 | }, |
740 | }; | |
741 | ||
742 | static int __init twl4030_usb_init(void) | |
743 | { | |
744 | return platform_driver_register(&twl4030_usb_driver); | |
745 | } | |
746 | subsys_initcall(twl4030_usb_init); | |
747 | ||
748 | static void __exit twl4030_usb_exit(void) | |
749 | { | |
750 | platform_driver_unregister(&twl4030_usb_driver); | |
751 | } | |
752 | module_exit(twl4030_usb_exit); | |
753 | ||
754 | MODULE_ALIAS("platform:twl4030_usb"); | |
755 | MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation"); | |
756 | MODULE_DESCRIPTION("TWL4030 USB transceiver driver"); | |
757 | MODULE_LICENSE("GPL"); |