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1da177e4 LT |
1 | /* vi: ts=8 sw=8 |
2 | * | |
3 | * TI 3410/5052 USB Serial Driver Header | |
4 | * | |
5 | * Copyright (C) 2004 Texas Instruments | |
6 | * | |
7 | * This driver is based on the Linux io_ti driver, which is | |
8 | * Copyright (C) 2000-2002 Inside Out Networks | |
9 | * Copyright (C) 2001-2002 Greg Kroah-Hartman | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * For questions or problems with this driver, contact Texas Instruments | |
17 | * technical support, or Al Borchers <alborchers@steinerpoint.com>, or | |
18 | * Peter Berger <pberger@brimson.com>. | |
19 | */ | |
20 | ||
21 | #ifndef _TI_3410_5052_H_ | |
22 | #define _TI_3410_5052_H_ | |
23 | ||
24 | /* Configuration ids */ | |
25 | #define TI_BOOT_CONFIG 1 | |
26 | #define TI_ACTIVE_CONFIG 2 | |
27 | ||
28 | /* Vendor and product ids */ | |
29 | #define TI_VENDOR_ID 0x0451 | |
1a1fab51 | 30 | #define IBM_VENDOR_ID 0x04b3 |
1da177e4 | 31 | #define TI_3410_PRODUCT_ID 0x3410 |
1a1fab51 | 32 | #define IBM_4543_PRODUCT_ID 0x4543 |
97dcf041 ON |
33 | #define IBM_454B_PRODUCT_ID 0x454b |
34 | #define IBM_454C_PRODUCT_ID 0x454c | |
1f54a6ae | 35 | #define TI_3410_EZ430_ID 0xF430 /* TI ez430 development tool */ |
1da177e4 LT |
36 | #define TI_5052_BOOT_PRODUCT_ID 0x5052 /* no EEPROM, no firmware */ |
37 | #define TI_5152_BOOT_PRODUCT_ID 0x5152 /* no EEPROM, no firmware */ | |
38 | #define TI_5052_EEPROM_PRODUCT_ID 0x505A /* EEPROM, no firmware */ | |
39 | #define TI_5052_FIRMWARE_PRODUCT_ID 0x505F /* firmware is running */ | |
975dc33b | 40 | #define FRI2_PRODUCT_ID 0x5053 /* Fish River Island II */ |
1da177e4 | 41 | |
cb7a7c6a CA |
42 | /* Multi-Tech vendor and product ids */ |
43 | #define MTS_VENDOR_ID 0x06E0 | |
44 | #define MTS_GSM_NO_FW_PRODUCT_ID 0xF108 | |
45 | #define MTS_CDMA_NO_FW_PRODUCT_ID 0xF109 | |
46 | #define MTS_CDMA_PRODUCT_ID 0xF110 | |
47 | #define MTS_GSM_PRODUCT_ID 0xF111 | |
48 | #define MTS_EDGE_PRODUCT_ID 0xF112 | |
cdc04834 AM |
49 | #define MTS_MT9234MU_PRODUCT_ID 0xF114 |
50 | #define MTS_MT9234ZBA_PRODUCT_ID 0xF115 | |
51 | #define MTS_MT9234ZBAOLD_PRODUCT_ID 0x0319 | |
cb7a7c6a | 52 | |
7fd25702 AL |
53 | /* Abbott Diabetics vendor and product ids */ |
54 | #define ABBOTT_VENDOR_ID 0x1a61 | |
55 | #define ABBOTT_PRODUCT_ID 0x3410 | |
56 | ||
1da177e4 LT |
57 | /* Commands */ |
58 | #define TI_GET_VERSION 0x01 | |
59 | #define TI_GET_PORT_STATUS 0x02 | |
60 | #define TI_GET_PORT_DEV_INFO 0x03 | |
61 | #define TI_GET_CONFIG 0x04 | |
62 | #define TI_SET_CONFIG 0x05 | |
63 | #define TI_OPEN_PORT 0x06 | |
64 | #define TI_CLOSE_PORT 0x07 | |
65 | #define TI_START_PORT 0x08 | |
66 | #define TI_STOP_PORT 0x09 | |
67 | #define TI_TEST_PORT 0x0A | |
68 | #define TI_PURGE_PORT 0x0B | |
69 | #define TI_RESET_EXT_DEVICE 0x0C | |
70 | #define TI_WRITE_DATA 0x80 | |
71 | #define TI_READ_DATA 0x81 | |
72 | #define TI_REQ_TYPE_CLASS 0x82 | |
73 | ||
74 | /* Module identifiers */ | |
75 | #define TI_I2C_PORT 0x01 | |
76 | #define TI_IEEE1284_PORT 0x02 | |
77 | #define TI_UART1_PORT 0x03 | |
78 | #define TI_UART2_PORT 0x04 | |
79 | #define TI_RAM_PORT 0x05 | |
80 | ||
81 | /* Modem status */ | |
82 | #define TI_MSR_DELTA_CTS 0x01 | |
83 | #define TI_MSR_DELTA_DSR 0x02 | |
84 | #define TI_MSR_DELTA_RI 0x04 | |
85 | #define TI_MSR_DELTA_CD 0x08 | |
86 | #define TI_MSR_CTS 0x10 | |
87 | #define TI_MSR_DSR 0x20 | |
88 | #define TI_MSR_RI 0x40 | |
89 | #define TI_MSR_CD 0x80 | |
90 | #define TI_MSR_DELTA_MASK 0x0F | |
91 | #define TI_MSR_MASK 0xF0 | |
92 | ||
93 | /* Line status */ | |
94 | #define TI_LSR_OVERRUN_ERROR 0x01 | |
95 | #define TI_LSR_PARITY_ERROR 0x02 | |
96 | #define TI_LSR_FRAMING_ERROR 0x04 | |
97 | #define TI_LSR_BREAK 0x08 | |
98 | #define TI_LSR_ERROR 0x0F | |
99 | #define TI_LSR_RX_FULL 0x10 | |
100 | #define TI_LSR_TX_EMPTY 0x20 | |
101 | ||
102 | /* Line control */ | |
103 | #define TI_LCR_BREAK 0x40 | |
104 | ||
105 | /* Modem control */ | |
106 | #define TI_MCR_LOOP 0x04 | |
107 | #define TI_MCR_DTR 0x10 | |
108 | #define TI_MCR_RTS 0x20 | |
109 | ||
110 | /* Mask settings */ | |
111 | #define TI_UART_ENABLE_RTS_IN 0x0001 | |
112 | #define TI_UART_DISABLE_RTS 0x0002 | |
113 | #define TI_UART_ENABLE_PARITY_CHECKING 0x0008 | |
114 | #define TI_UART_ENABLE_DSR_OUT 0x0010 | |
115 | #define TI_UART_ENABLE_CTS_OUT 0x0020 | |
116 | #define TI_UART_ENABLE_X_OUT 0x0040 | |
117 | #define TI_UART_ENABLE_XA_OUT 0x0080 | |
118 | #define TI_UART_ENABLE_X_IN 0x0100 | |
119 | #define TI_UART_ENABLE_DTR_IN 0x0800 | |
120 | #define TI_UART_DISABLE_DTR 0x1000 | |
121 | #define TI_UART_ENABLE_MS_INTS 0x2000 | |
122 | #define TI_UART_ENABLE_AUTO_START_DMA 0x4000 | |
123 | ||
124 | /* Parity */ | |
125 | #define TI_UART_NO_PARITY 0x00 | |
126 | #define TI_UART_ODD_PARITY 0x01 | |
127 | #define TI_UART_EVEN_PARITY 0x02 | |
128 | #define TI_UART_MARK_PARITY 0x03 | |
129 | #define TI_UART_SPACE_PARITY 0x04 | |
130 | ||
131 | /* Stop bits */ | |
132 | #define TI_UART_1_STOP_BITS 0x00 | |
133 | #define TI_UART_1_5_STOP_BITS 0x01 | |
134 | #define TI_UART_2_STOP_BITS 0x02 | |
135 | ||
136 | /* Bits per character */ | |
137 | #define TI_UART_5_DATA_BITS 0x00 | |
138 | #define TI_UART_6_DATA_BITS 0x01 | |
139 | #define TI_UART_7_DATA_BITS 0x02 | |
140 | #define TI_UART_8_DATA_BITS 0x03 | |
141 | ||
142 | /* 232/485 modes */ | |
143 | #define TI_UART_232 0x00 | |
144 | #define TI_UART_485_RECEIVER_DISABLED 0x01 | |
145 | #define TI_UART_485_RECEIVER_ENABLED 0x02 | |
146 | ||
147 | /* Pipe transfer mode and timeout */ | |
148 | #define TI_PIPE_MODE_CONTINOUS 0x01 | |
149 | #define TI_PIPE_MODE_MASK 0x03 | |
150 | #define TI_PIPE_TIMEOUT_MASK 0x7C | |
151 | #define TI_PIPE_TIMEOUT_ENABLE 0x80 | |
152 | ||
153 | /* Config struct */ | |
154 | struct ti_uart_config { | |
155 | __u16 wBaudRate; | |
156 | __u16 wFlags; | |
157 | __u8 bDataBits; | |
158 | __u8 bParity; | |
159 | __u8 bStopBits; | |
160 | char cXon; | |
161 | char cXoff; | |
162 | __u8 bUartMode; | |
163 | } __attribute__((packed)); | |
164 | ||
165 | /* Get port status */ | |
166 | struct ti_port_status { | |
167 | __u8 bCmdCode; | |
168 | __u8 bModuleId; | |
169 | __u8 bErrorCode; | |
170 | __u8 bMSR; | |
171 | __u8 bLSR; | |
172 | } __attribute__((packed)); | |
173 | ||
174 | /* Purge modes */ | |
175 | #define TI_PURGE_OUTPUT 0x00 | |
176 | #define TI_PURGE_INPUT 0x80 | |
177 | ||
178 | /* Read/Write data */ | |
179 | #define TI_RW_DATA_ADDR_SFR 0x10 | |
180 | #define TI_RW_DATA_ADDR_IDATA 0x20 | |
181 | #define TI_RW_DATA_ADDR_XDATA 0x30 | |
182 | #define TI_RW_DATA_ADDR_CODE 0x40 | |
183 | #define TI_RW_DATA_ADDR_GPIO 0x50 | |
184 | #define TI_RW_DATA_ADDR_I2C 0x60 | |
185 | #define TI_RW_DATA_ADDR_FLASH 0x70 | |
186 | #define TI_RW_DATA_ADDR_DSP 0x80 | |
187 | ||
188 | #define TI_RW_DATA_UNSPECIFIED 0x00 | |
189 | #define TI_RW_DATA_BYTE 0x01 | |
190 | #define TI_RW_DATA_WORD 0x02 | |
191 | #define TI_RW_DATA_DOUBLE_WORD 0x04 | |
192 | ||
193 | struct ti_write_data_bytes { | |
194 | __u8 bAddrType; | |
195 | __u8 bDataType; | |
196 | __u8 bDataCounter; | |
197 | __be16 wBaseAddrHi; | |
198 | __be16 wBaseAddrLo; | |
199 | __u8 bData[0]; | |
200 | } __attribute__((packed)); | |
201 | ||
202 | struct ti_read_data_request { | |
203 | __u8 bAddrType; | |
204 | __u8 bDataType; | |
205 | __u8 bDataCounter; | |
206 | __be16 wBaseAddrHi; | |
207 | __be16 wBaseAddrLo; | |
208 | } __attribute__((packed)); | |
209 | ||
210 | struct ti_read_data_bytes { | |
211 | __u8 bCmdCode; | |
212 | __u8 bModuleId; | |
213 | __u8 bErrorCode; | |
214 | __u8 bData[0]; | |
215 | } __attribute__((packed)); | |
216 | ||
217 | /* Interrupt struct */ | |
218 | struct ti_interrupt { | |
219 | __u8 bICode; | |
220 | __u8 bIInfo; | |
221 | } __attribute__((packed)); | |
222 | ||
223 | /* Interrupt codes */ | |
224 | #define TI_GET_PORT_FROM_CODE(c) (((c) >> 4) - 3) | |
225 | #define TI_GET_FUNC_FROM_CODE(c) ((c) & 0x0f) | |
226 | #define TI_CODE_HARDWARE_ERROR 0xFF | |
227 | #define TI_CODE_DATA_ERROR 0x03 | |
228 | #define TI_CODE_MODEM_STATUS 0x04 | |
229 | ||
230 | /* Download firmware max packet size */ | |
231 | #define TI_DOWNLOAD_MAX_PACKET_SIZE 64 | |
232 | ||
233 | /* Firmware image header */ | |
234 | struct ti_firmware_header { | |
235 | __le16 wLength; | |
236 | __u8 bCheckSum; | |
237 | } __attribute__((packed)); | |
238 | ||
239 | /* UART addresses */ | |
240 | #define TI_UART1_BASE_ADDR 0xFFA0 /* UART 1 base address */ | |
241 | #define TI_UART2_BASE_ADDR 0xFFB0 /* UART 2 base address */ | |
242 | #define TI_UART_OFFSET_LCR 0x0002 /* UART MCR register offset */ | |
243 | #define TI_UART_OFFSET_MCR 0x0004 /* UART MCR register offset */ | |
244 | ||
245 | #endif /* _TI_3410_5052_H_ */ |