]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/amba-clcd.c | |
3 | * | |
4 | * Copyright (C) 2001 ARM Limited, by David A Rusling | |
5 | * Updated to 2.5, Deep Blue Solutions Ltd. | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file COPYING in the main directory of this archive | |
9 | * for more details. | |
10 | * | |
11 | * ARM PrimeCell PL110 Color LCD Controller | |
12 | */ | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/string.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/fb.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/list.h> | |
24 | ||
25 | #include <asm/hardware/amba.h> | |
26 | #include <asm/hardware/clock.h> | |
27 | ||
28 | #include <asm/hardware/amba_clcd.h> | |
29 | ||
30 | #define to_clcd(info) container_of(info, struct clcd_fb, fb) | |
31 | ||
32 | /* This is limited to 16 characters when displayed by X startup */ | |
33 | static const char *clcd_name = "CLCD FB"; | |
34 | ||
35 | /* | |
36 | * Unfortunately, the enable/disable functions may be called either from | |
37 | * process or IRQ context, and we _need_ to delay. This is _not_ good. | |
38 | */ | |
39 | static inline void clcdfb_sleep(unsigned int ms) | |
40 | { | |
41 | if (in_atomic()) { | |
42 | mdelay(ms); | |
43 | } else { | |
44 | msleep(ms); | |
45 | } | |
46 | } | |
47 | ||
48 | static inline void clcdfb_set_start(struct clcd_fb *fb) | |
49 | { | |
50 | unsigned long ustart = fb->fb.fix.smem_start; | |
51 | unsigned long lstart; | |
52 | ||
53 | ustart += fb->fb.var.yoffset * fb->fb.fix.line_length; | |
54 | lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2; | |
55 | ||
56 | writel(ustart, fb->regs + CLCD_UBAS); | |
57 | writel(lstart, fb->regs + CLCD_LBAS); | |
58 | } | |
59 | ||
60 | static void clcdfb_disable(struct clcd_fb *fb) | |
61 | { | |
62 | u32 val; | |
63 | ||
64 | if (fb->board->disable) | |
65 | fb->board->disable(fb); | |
66 | ||
67 | val = readl(fb->regs + CLCD_CNTL); | |
68 | if (val & CNTL_LCDPWR) { | |
69 | val &= ~CNTL_LCDPWR; | |
70 | writel(val, fb->regs + CLCD_CNTL); | |
71 | ||
72 | clcdfb_sleep(20); | |
73 | } | |
74 | if (val & CNTL_LCDEN) { | |
75 | val &= ~CNTL_LCDEN; | |
76 | writel(val, fb->regs + CLCD_CNTL); | |
77 | } | |
78 | ||
79 | /* | |
80 | * Disable CLCD clock source. | |
81 | */ | |
82 | clk_disable(fb->clk); | |
83 | } | |
84 | ||
85 | static void clcdfb_enable(struct clcd_fb *fb, u32 cntl) | |
86 | { | |
87 | /* | |
88 | * Enable the CLCD clock source. | |
89 | */ | |
90 | clk_enable(fb->clk); | |
91 | ||
92 | /* | |
93 | * Bring up by first enabling.. | |
94 | */ | |
95 | cntl |= CNTL_LCDEN; | |
96 | writel(cntl, fb->regs + CLCD_CNTL); | |
97 | ||
98 | clcdfb_sleep(20); | |
99 | ||
100 | /* | |
101 | * and now apply power. | |
102 | */ | |
103 | cntl |= CNTL_LCDPWR; | |
104 | writel(cntl, fb->regs + CLCD_CNTL); | |
105 | ||
106 | /* | |
107 | * finally, enable the interface. | |
108 | */ | |
109 | if (fb->board->enable) | |
110 | fb->board->enable(fb); | |
111 | } | |
112 | ||
113 | static int | |
114 | clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var) | |
115 | { | |
116 | int ret = 0; | |
117 | ||
118 | memset(&var->transp, 0, sizeof(var->transp)); | |
119 | memset(&var->red, 0, sizeof(var->red)); | |
120 | memset(&var->green, 0, sizeof(var->green)); | |
121 | memset(&var->blue, 0, sizeof(var->blue)); | |
122 | ||
123 | switch (var->bits_per_pixel) { | |
124 | case 1: | |
125 | case 2: | |
126 | case 4: | |
127 | case 8: | |
c4d12b98 | 128 | var->red.length = var->bits_per_pixel; |
1da177e4 | 129 | var->red.offset = 0; |
c4d12b98 | 130 | var->green.length = var->bits_per_pixel; |
1da177e4 | 131 | var->green.offset = 0; |
c4d12b98 | 132 | var->blue.length = var->bits_per_pixel; |
1da177e4 LT |
133 | var->blue.offset = 0; |
134 | break; | |
135 | case 16: | |
136 | var->red.length = 5; | |
ed562ab1 | 137 | var->green.length = 6; |
1da177e4 LT |
138 | var->blue.length = 5; |
139 | if (fb->panel->cntl & CNTL_BGR) { | |
ed562ab1 | 140 | var->red.offset = 11; |
1da177e4 LT |
141 | var->green.offset = 5; |
142 | var->blue.offset = 0; | |
143 | } else { | |
144 | var->red.offset = 0; | |
145 | var->green.offset = 5; | |
ed562ab1 | 146 | var->blue.offset = 11; |
1da177e4 LT |
147 | } |
148 | break; | |
82235e91 | 149 | case 32: |
1da177e4 LT |
150 | if (fb->panel->cntl & CNTL_LCDTFT) { |
151 | var->red.length = 8; | |
152 | var->green.length = 8; | |
153 | var->blue.length = 8; | |
154 | ||
155 | if (fb->panel->cntl & CNTL_BGR) { | |
156 | var->red.offset = 16; | |
157 | var->green.offset = 8; | |
158 | var->blue.offset = 0; | |
159 | } else { | |
160 | var->red.offset = 0; | |
161 | var->green.offset = 8; | |
162 | var->blue.offset = 16; | |
163 | } | |
164 | break; | |
165 | } | |
166 | default: | |
167 | ret = -EINVAL; | |
168 | break; | |
169 | } | |
170 | ||
171 | return ret; | |
172 | } | |
173 | ||
174 | static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
175 | { | |
176 | struct clcd_fb *fb = to_clcd(info); | |
177 | int ret = -EINVAL; | |
178 | ||
179 | if (fb->board->check) | |
180 | ret = fb->board->check(fb, var); | |
82235e91 RK |
181 | |
182 | if (ret == 0 && | |
183 | var->xres_virtual * var->bits_per_pixel / 8 * | |
184 | var->yres_virtual > fb->fb.fix.smem_len) | |
185 | ret = -EINVAL; | |
186 | ||
1da177e4 LT |
187 | if (ret == 0) |
188 | ret = clcdfb_set_bitfields(fb, var); | |
189 | ||
190 | return ret; | |
191 | } | |
192 | ||
193 | static int clcdfb_set_par(struct fb_info *info) | |
194 | { | |
195 | struct clcd_fb *fb = to_clcd(info); | |
196 | struct clcd_regs regs; | |
197 | ||
198 | fb->fb.fix.line_length = fb->fb.var.xres_virtual * | |
199 | fb->fb.var.bits_per_pixel / 8; | |
200 | ||
201 | if (fb->fb.var.bits_per_pixel <= 8) | |
202 | fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
203 | else | |
204 | fb->fb.fix.visual = FB_VISUAL_TRUECOLOR; | |
205 | ||
206 | fb->board->decode(fb, ®s); | |
207 | ||
208 | clcdfb_disable(fb); | |
209 | ||
210 | writel(regs.tim0, fb->regs + CLCD_TIM0); | |
211 | writel(regs.tim1, fb->regs + CLCD_TIM1); | |
212 | writel(regs.tim2, fb->regs + CLCD_TIM2); | |
213 | writel(regs.tim3, fb->regs + CLCD_TIM3); | |
214 | ||
215 | clcdfb_set_start(fb); | |
216 | ||
217 | clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000); | |
218 | ||
219 | fb->clcd_cntl = regs.cntl; | |
220 | ||
221 | clcdfb_enable(fb, regs.cntl); | |
222 | ||
223 | #ifdef DEBUG | |
224 | printk(KERN_INFO "CLCD: Registers set to\n" | |
225 | KERN_INFO " %08x %08x %08x %08x\n" | |
226 | KERN_INFO " %08x %08x %08x %08x\n", | |
227 | readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1), | |
228 | readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3), | |
229 | readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS), | |
230 | readl(fb->regs + CLCD_IENB), readl(fb->regs + CLCD_CNTL)); | |
231 | #endif | |
232 | ||
233 | return 0; | |
234 | } | |
235 | ||
236 | static inline u32 convert_bitfield(int val, struct fb_bitfield *bf) | |
237 | { | |
238 | unsigned int mask = (1 << bf->length) - 1; | |
239 | ||
240 | return (val >> (16 - bf->length) & mask) << bf->offset; | |
241 | } | |
242 | ||
243 | /* | |
244 | * Set a single color register. The values supplied have a 16 bit | |
245 | * magnitude. Return != 0 for invalid regno. | |
246 | */ | |
247 | static int | |
248 | clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, | |
249 | unsigned int blue, unsigned int transp, struct fb_info *info) | |
250 | { | |
251 | struct clcd_fb *fb = to_clcd(info); | |
252 | ||
253 | if (regno < 16) | |
254 | fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) | | |
255 | convert_bitfield(blue, &fb->fb.var.blue) | | |
256 | convert_bitfield(green, &fb->fb.var.green) | | |
257 | convert_bitfield(red, &fb->fb.var.red); | |
258 | ||
1ddb8a16 | 259 | if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) { |
1da177e4 LT |
260 | int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3); |
261 | u32 val, mask, newval; | |
262 | ||
263 | newval = (red >> 11) & 0x001f; | |
264 | newval |= (green >> 6) & 0x03e0; | |
265 | newval |= (blue >> 1) & 0x7c00; | |
266 | ||
267 | /* | |
268 | * 3.2.11: if we're configured for big endian | |
269 | * byte order, the palette entries are swapped. | |
270 | */ | |
271 | if (fb->clcd_cntl & CNTL_BEBO) | |
272 | regno ^= 1; | |
273 | ||
274 | if (regno & 1) { | |
275 | newval <<= 16; | |
276 | mask = 0x0000ffff; | |
277 | } else { | |
278 | mask = 0xffff0000; | |
279 | } | |
280 | ||
281 | val = readl(fb->regs + hw_reg) & mask; | |
282 | writel(val | newval, fb->regs + hw_reg); | |
283 | } | |
284 | ||
285 | return regno > 255; | |
286 | } | |
287 | ||
288 | /* | |
289 | * Blank the screen if blank_mode != 0, else unblank. If blank == NULL | |
290 | * then the caller blanks by setting the CLUT (Color Look Up Table) to all | |
291 | * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due | |
292 | * to e.g. a video mode which doesn't support it. Implements VESA suspend | |
293 | * and powerdown modes on hardware that supports disabling hsync/vsync: | |
294 | * blank_mode == 2: suspend vsync | |
295 | * blank_mode == 3: suspend hsync | |
296 | * blank_mode == 4: powerdown | |
297 | */ | |
298 | static int clcdfb_blank(int blank_mode, struct fb_info *info) | |
299 | { | |
300 | struct clcd_fb *fb = to_clcd(info); | |
301 | ||
302 | if (blank_mode != 0) { | |
303 | clcdfb_disable(fb); | |
304 | } else { | |
305 | clcdfb_enable(fb, fb->clcd_cntl); | |
306 | } | |
307 | return 0; | |
308 | } | |
309 | ||
310 | static int clcdfb_mmap(struct fb_info *info, struct file *file, | |
311 | struct vm_area_struct *vma) | |
312 | { | |
313 | struct clcd_fb *fb = to_clcd(info); | |
314 | unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT; | |
315 | int ret = -EINVAL; | |
316 | ||
317 | len = info->fix.smem_len; | |
318 | ||
319 | if (off <= len && vma->vm_end - vma->vm_start <= len - off && | |
320 | fb->board->mmap) | |
321 | ret = fb->board->mmap(fb, vma); | |
322 | ||
323 | return ret; | |
324 | } | |
325 | ||
326 | static struct fb_ops clcdfb_ops = { | |
327 | .owner = THIS_MODULE, | |
328 | .fb_check_var = clcdfb_check_var, | |
329 | .fb_set_par = clcdfb_set_par, | |
330 | .fb_setcolreg = clcdfb_setcolreg, | |
331 | .fb_blank = clcdfb_blank, | |
332 | .fb_fillrect = cfb_fillrect, | |
333 | .fb_copyarea = cfb_copyarea, | |
334 | .fb_imageblit = cfb_imageblit, | |
335 | .fb_cursor = soft_cursor, | |
336 | .fb_mmap = clcdfb_mmap, | |
337 | }; | |
338 | ||
339 | static int clcdfb_register(struct clcd_fb *fb) | |
340 | { | |
341 | int ret; | |
342 | ||
343 | fb->clk = clk_get(&fb->dev->dev, "CLCDCLK"); | |
344 | if (IS_ERR(fb->clk)) { | |
345 | ret = PTR_ERR(fb->clk); | |
346 | goto out; | |
347 | } | |
348 | ||
349 | ret = clk_use(fb->clk); | |
350 | if (ret) | |
351 | goto free_clk; | |
352 | ||
353 | fb->fb.fix.mmio_start = fb->dev->res.start; | |
354 | fb->fb.fix.mmio_len = SZ_4K; | |
355 | ||
356 | fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len); | |
357 | if (!fb->regs) { | |
358 | printk(KERN_ERR "CLCD: unable to remap registers\n"); | |
359 | ret = -ENOMEM; | |
360 | goto unuse_clk; | |
361 | } | |
362 | ||
363 | fb->fb.fbops = &clcdfb_ops; | |
364 | fb->fb.flags = FBINFO_FLAG_DEFAULT; | |
365 | fb->fb.pseudo_palette = fb->cmap; | |
366 | ||
367 | strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id)); | |
368 | fb->fb.fix.type = FB_TYPE_PACKED_PIXELS; | |
369 | fb->fb.fix.type_aux = 0; | |
370 | fb->fb.fix.xpanstep = 0; | |
371 | fb->fb.fix.ypanstep = 0; | |
372 | fb->fb.fix.ywrapstep = 0; | |
373 | fb->fb.fix.accel = FB_ACCEL_NONE; | |
374 | ||
375 | fb->fb.var.xres = fb->panel->mode.xres; | |
376 | fb->fb.var.yres = fb->panel->mode.yres; | |
377 | fb->fb.var.xres_virtual = fb->panel->mode.xres; | |
378 | fb->fb.var.yres_virtual = fb->panel->mode.yres; | |
379 | fb->fb.var.bits_per_pixel = fb->panel->bpp; | |
380 | fb->fb.var.grayscale = fb->panel->grayscale; | |
381 | fb->fb.var.pixclock = fb->panel->mode.pixclock; | |
382 | fb->fb.var.left_margin = fb->panel->mode.left_margin; | |
383 | fb->fb.var.right_margin = fb->panel->mode.right_margin; | |
384 | fb->fb.var.upper_margin = fb->panel->mode.upper_margin; | |
385 | fb->fb.var.lower_margin = fb->panel->mode.lower_margin; | |
386 | fb->fb.var.hsync_len = fb->panel->mode.hsync_len; | |
387 | fb->fb.var.vsync_len = fb->panel->mode.vsync_len; | |
388 | fb->fb.var.sync = fb->panel->mode.sync; | |
389 | fb->fb.var.vmode = fb->panel->mode.vmode; | |
390 | fb->fb.var.activate = FB_ACTIVATE_NOW; | |
391 | fb->fb.var.nonstd = 0; | |
392 | fb->fb.var.height = fb->panel->height; | |
393 | fb->fb.var.width = fb->panel->width; | |
394 | fb->fb.var.accel_flags = 0; | |
395 | ||
396 | fb->fb.monspecs.hfmin = 0; | |
397 | fb->fb.monspecs.hfmax = 100000; | |
398 | fb->fb.monspecs.vfmin = 0; | |
399 | fb->fb.monspecs.vfmax = 400; | |
400 | fb->fb.monspecs.dclkmin = 1000000; | |
401 | fb->fb.monspecs.dclkmax = 100000000; | |
402 | ||
403 | /* | |
404 | * Make sure that the bitfields are set appropriately. | |
405 | */ | |
406 | clcdfb_set_bitfields(fb, &fb->fb.var); | |
407 | ||
408 | /* | |
409 | * Allocate colourmap. | |
410 | */ | |
411 | fb_alloc_cmap(&fb->fb.cmap, 256, 0); | |
412 | ||
413 | /* | |
414 | * Ensure interrupts are disabled. | |
415 | */ | |
416 | writel(0, fb->regs + CLCD_IENB); | |
417 | ||
418 | fb_set_var(&fb->fb, &fb->fb.var); | |
419 | ||
420 | printk(KERN_INFO "CLCD: %s hardware, %s display\n", | |
421 | fb->board->name, fb->panel->mode.name); | |
422 | ||
423 | ret = register_framebuffer(&fb->fb); | |
424 | if (ret == 0) | |
425 | goto out; | |
426 | ||
427 | printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret); | |
428 | ||
429 | iounmap(fb->regs); | |
430 | unuse_clk: | |
431 | clk_unuse(fb->clk); | |
432 | free_clk: | |
433 | clk_put(fb->clk); | |
434 | out: | |
435 | return ret; | |
436 | } | |
437 | ||
438 | static int clcdfb_probe(struct amba_device *dev, void *id) | |
439 | { | |
440 | struct clcd_board *board = dev->dev.platform_data; | |
441 | struct clcd_fb *fb; | |
442 | int ret; | |
443 | ||
444 | if (!board) | |
445 | return -EINVAL; | |
446 | ||
447 | ret = amba_request_regions(dev, NULL); | |
448 | if (ret) { | |
449 | printk(KERN_ERR "CLCD: unable to reserve regs region\n"); | |
450 | goto out; | |
451 | } | |
452 | ||
453 | fb = (struct clcd_fb *) kmalloc(sizeof(struct clcd_fb), GFP_KERNEL); | |
454 | if (!fb) { | |
455 | printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n"); | |
456 | ret = -ENOMEM; | |
457 | goto free_region; | |
458 | } | |
459 | memset(fb, 0, sizeof(struct clcd_fb)); | |
460 | ||
461 | fb->dev = dev; | |
462 | fb->board = board; | |
463 | ||
464 | ret = fb->board->setup(fb); | |
465 | if (ret) | |
466 | goto free_fb; | |
467 | ||
468 | ret = clcdfb_register(fb); | |
469 | if (ret == 0) { | |
470 | amba_set_drvdata(dev, fb); | |
471 | goto out; | |
472 | } | |
473 | ||
474 | fb->board->remove(fb); | |
475 | free_fb: | |
476 | kfree(fb); | |
477 | free_region: | |
478 | amba_release_regions(dev); | |
479 | out: | |
480 | return ret; | |
481 | } | |
482 | ||
483 | static int clcdfb_remove(struct amba_device *dev) | |
484 | { | |
485 | struct clcd_fb *fb = amba_get_drvdata(dev); | |
486 | ||
487 | amba_set_drvdata(dev, NULL); | |
488 | ||
489 | clcdfb_disable(fb); | |
490 | unregister_framebuffer(&fb->fb); | |
491 | iounmap(fb->regs); | |
492 | clk_unuse(fb->clk); | |
493 | clk_put(fb->clk); | |
494 | ||
495 | fb->board->remove(fb); | |
496 | ||
497 | kfree(fb); | |
498 | ||
499 | amba_release_regions(dev); | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
504 | static struct amba_id clcdfb_id_table[] = { | |
505 | { | |
506 | .id = 0x00041110, | |
507 | .mask = 0x000fffff, | |
508 | }, | |
509 | { 0, 0 }, | |
510 | }; | |
511 | ||
512 | static struct amba_driver clcd_driver = { | |
513 | .drv = { | |
514 | .name = "clcd-pl110", | |
515 | }, | |
516 | .probe = clcdfb_probe, | |
517 | .remove = clcdfb_remove, | |
518 | .id_table = clcdfb_id_table, | |
519 | }; | |
520 | ||
521 | int __init amba_clcdfb_init(void) | |
522 | { | |
523 | if (fb_get_options("ambafb", NULL)) | |
524 | return -ENODEV; | |
525 | ||
526 | return amba_driver_register(&clcd_driver); | |
527 | } | |
528 | ||
529 | module_init(amba_clcdfb_init); | |
530 | ||
531 | static void __exit amba_clcdfb_exit(void) | |
532 | { | |
533 | amba_driver_unregister(&clcd_driver); | |
534 | } | |
535 | ||
536 | module_exit(amba_clcdfb_exit); | |
537 | ||
538 | MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver"); | |
539 | MODULE_LICENSE("GPL"); |