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14340586 NF |
1 | /* |
2 | * Driver for AT91/AT32 LCD Controller | |
3 | * | |
4 | * Copyright (C) 2007 Atmel Corporation | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file COPYING in the main directory of this archive for | |
8 | * more details. | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/dma-mapping.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/fb.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/delay.h> | |
a9a84c37 | 19 | #include <linux/backlight.h> |
14340586 | 20 | |
a09e64fb RK |
21 | #include <mach/board.h> |
22 | #include <mach/cpu.h> | |
23 | #include <mach/gpio.h> | |
14340586 NF |
24 | |
25 | #include <video/atmel_lcdc.h> | |
26 | ||
27 | #define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg)) | |
28 | #define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg)) | |
29 | ||
30 | /* configurable parameters */ | |
31 | #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 | |
53b7479b NF |
32 | #define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */ |
33 | #define ATMEL_LCDC_FIFO_SIZE 512 /* words */ | |
14340586 NF |
34 | |
35 | #if defined(CONFIG_ARCH_AT91) | |
e730d8b0 HS |
36 | #define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \ |
37 | | FBINFO_PARTIAL_PAN_OK \ | |
38 | | FBINFO_HWACCEL_YPAN) | |
14340586 NF |
39 | |
40 | static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo, | |
41 | struct fb_var_screeninfo *var) | |
42 | { | |
43 | ||
44 | } | |
45 | #elif defined(CONFIG_AVR32) | |
46 | #define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \ | |
47 | | FBINFO_PARTIAL_PAN_OK \ | |
48 | | FBINFO_HWACCEL_XPAN \ | |
49 | | FBINFO_HWACCEL_YPAN) | |
50 | ||
51 | static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo, | |
52 | struct fb_var_screeninfo *var) | |
53 | { | |
54 | u32 dma2dcfg; | |
55 | u32 pixeloff; | |
56 | ||
57 | pixeloff = (var->xoffset * var->bits_per_pixel) & 0x1f; | |
58 | ||
59 | dma2dcfg = ((var->xres_virtual - var->xres) * var->bits_per_pixel) / 8; | |
60 | dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET; | |
61 | lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg); | |
62 | ||
63 | /* Update configuration */ | |
64 | lcdc_writel(sinfo, ATMEL_LCDC_DMACON, | |
65 | lcdc_readl(sinfo, ATMEL_LCDC_DMACON) | |
66 | | ATMEL_LCDC_DMAUPDT); | |
67 | } | |
68 | #endif | |
69 | ||
a9a84c37 DB |
70 | static const u32 contrast_ctr = ATMEL_LCDC_PS_DIV8 |
71 | | ATMEL_LCDC_POL_POSITIVE | |
72 | | ATMEL_LCDC_ENA_PWMENABLE; | |
73 | ||
74 | #ifdef CONFIG_BACKLIGHT_ATMEL_LCDC | |
75 | ||
76 | /* some bl->props field just changed */ | |
77 | static int atmel_bl_update_status(struct backlight_device *bl) | |
78 | { | |
79 | struct atmel_lcdfb_info *sinfo = bl_get_data(bl); | |
80 | int power = sinfo->bl_power; | |
81 | int brightness = bl->props.brightness; | |
82 | ||
83 | /* REVISIT there may be a meaningful difference between | |
84 | * fb_blank and power ... there seem to be some cases | |
85 | * this doesn't handle correctly. | |
86 | */ | |
87 | if (bl->props.fb_blank != sinfo->bl_power) | |
88 | power = bl->props.fb_blank; | |
89 | else if (bl->props.power != sinfo->bl_power) | |
90 | power = bl->props.power; | |
91 | ||
92 | if (brightness < 0 && power == FB_BLANK_UNBLANK) | |
93 | brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL); | |
94 | else if (power != FB_BLANK_UNBLANK) | |
95 | brightness = 0; | |
96 | ||
97 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness); | |
98 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, | |
99 | brightness ? contrast_ctr : 0); | |
100 | ||
101 | bl->props.fb_blank = bl->props.power = sinfo->bl_power = power; | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
106 | static int atmel_bl_get_brightness(struct backlight_device *bl) | |
107 | { | |
108 | struct atmel_lcdfb_info *sinfo = bl_get_data(bl); | |
109 | ||
110 | return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL); | |
111 | } | |
112 | ||
113 | static struct backlight_ops atmel_lcdc_bl_ops = { | |
114 | .update_status = atmel_bl_update_status, | |
115 | .get_brightness = atmel_bl_get_brightness, | |
116 | }; | |
117 | ||
118 | static void init_backlight(struct atmel_lcdfb_info *sinfo) | |
119 | { | |
120 | struct backlight_device *bl; | |
121 | ||
122 | sinfo->bl_power = FB_BLANK_UNBLANK; | |
123 | ||
124 | if (sinfo->backlight) | |
125 | return; | |
126 | ||
127 | bl = backlight_device_register("backlight", &sinfo->pdev->dev, | |
128 | sinfo, &atmel_lcdc_bl_ops); | |
cf7b9a1e | 129 | if (IS_ERR(bl)) { |
a9a84c37 DB |
130 | dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n", |
131 | PTR_ERR(bl)); | |
132 | return; | |
133 | } | |
134 | sinfo->backlight = bl; | |
135 | ||
136 | bl->props.power = FB_BLANK_UNBLANK; | |
137 | bl->props.fb_blank = FB_BLANK_UNBLANK; | |
138 | bl->props.max_brightness = 0xff; | |
139 | bl->props.brightness = atmel_bl_get_brightness(bl); | |
140 | } | |
141 | ||
142 | static void exit_backlight(struct atmel_lcdfb_info *sinfo) | |
143 | { | |
144 | if (sinfo->backlight) | |
145 | backlight_device_unregister(sinfo->backlight); | |
146 | } | |
147 | ||
148 | #else | |
149 | ||
150 | static void init_backlight(struct atmel_lcdfb_info *sinfo) | |
151 | { | |
152 | dev_warn(&sinfo->pdev->dev, "backlight control is not available\n"); | |
153 | } | |
154 | ||
155 | static void exit_backlight(struct atmel_lcdfb_info *sinfo) | |
156 | { | |
157 | } | |
158 | ||
159 | #endif | |
160 | ||
161 | static void init_contrast(struct atmel_lcdfb_info *sinfo) | |
162 | { | |
163 | /* have some default contrast/backlight settings */ | |
164 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr); | |
165 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); | |
166 | ||
167 | if (sinfo->lcdcon_is_backlight) | |
168 | init_backlight(sinfo); | |
169 | } | |
170 | ||
14340586 NF |
171 | |
172 | static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = { | |
173 | .type = FB_TYPE_PACKED_PIXELS, | |
174 | .visual = FB_VISUAL_TRUECOLOR, | |
175 | .xpanstep = 0, | |
e730d8b0 | 176 | .ypanstep = 1, |
14340586 NF |
177 | .ywrapstep = 0, |
178 | .accel = FB_ACCEL_NONE, | |
179 | }; | |
180 | ||
250a269d NF |
181 | static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2) |
182 | { | |
183 | unsigned long value; | |
184 | ||
185 | if (!(cpu_is_at91sam9261() || cpu_is_at32ap7000())) | |
186 | return xres; | |
187 | ||
188 | value = xres; | |
189 | if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) { | |
190 | /* STN display */ | |
191 | if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) { | |
192 | value *= 3; | |
193 | } | |
194 | if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4 | |
195 | || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8 | |
196 | && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL )) | |
197 | value = DIV_ROUND_UP(value, 4); | |
198 | else | |
199 | value = DIV_ROUND_UP(value, 8); | |
200 | } | |
201 | ||
202 | return value; | |
203 | } | |
14340586 | 204 | |
3aa04f1b HS |
205 | static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo) |
206 | { | |
207 | /* Turn off the LCD controller and the DMA controller */ | |
208 | lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, | |
209 | sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET); | |
210 | ||
211 | /* Wait for the LCDC core to become idle */ | |
212 | while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY) | |
213 | msleep(10); | |
214 | ||
215 | lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0); | |
216 | } | |
217 | ||
218 | static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo) | |
219 | { | |
220 | atmel_lcdfb_stop_nowait(sinfo); | |
221 | ||
222 | /* Wait for DMA engine to become idle... */ | |
223 | while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY) | |
224 | msleep(10); | |
225 | } | |
226 | ||
227 | static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo) | |
228 | { | |
229 | lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon); | |
230 | lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, | |
231 | (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET) | |
232 | | ATMEL_LCDC_PWR); | |
233 | } | |
234 | ||
14340586 NF |
235 | static void atmel_lcdfb_update_dma(struct fb_info *info, |
236 | struct fb_var_screeninfo *var) | |
237 | { | |
238 | struct atmel_lcdfb_info *sinfo = info->par; | |
239 | struct fb_fix_screeninfo *fix = &info->fix; | |
240 | unsigned long dma_addr; | |
241 | ||
242 | dma_addr = (fix->smem_start + var->yoffset * fix->line_length | |
243 | + var->xoffset * var->bits_per_pixel / 8); | |
244 | ||
245 | dma_addr &= ~3UL; | |
246 | ||
247 | /* Set framebuffer DMA base address and pixel offset */ | |
248 | lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr); | |
249 | ||
250 | atmel_lcdfb_update_dma2d(sinfo, var); | |
251 | } | |
252 | ||
253 | static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo) | |
254 | { | |
255 | struct fb_info *info = sinfo->info; | |
256 | ||
257 | dma_free_writecombine(info->device, info->fix.smem_len, | |
258 | info->screen_base, info->fix.smem_start); | |
259 | } | |
260 | ||
261 | /** | |
262 | * atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory | |
263 | * @sinfo: the frame buffer to allocate memory for | |
264 | */ | |
265 | static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo) | |
266 | { | |
267 | struct fb_info *info = sinfo->info; | |
268 | struct fb_var_screeninfo *var = &info->var; | |
ea757aca | 269 | unsigned int smem_len; |
14340586 | 270 | |
ea757aca HS |
271 | smem_len = (var->xres_virtual * var->yres_virtual |
272 | * ((var->bits_per_pixel + 7) / 8)); | |
273 | info->fix.smem_len = max(smem_len, sinfo->smem_len); | |
14340586 NF |
274 | |
275 | info->screen_base = dma_alloc_writecombine(info->device, info->fix.smem_len, | |
276 | (dma_addr_t *)&info->fix.smem_start, GFP_KERNEL); | |
277 | ||
278 | if (!info->screen_base) { | |
279 | return -ENOMEM; | |
280 | } | |
281 | ||
01d3a5e7 HS |
282 | memset(info->screen_base, 0, info->fix.smem_len); |
283 | ||
14340586 NF |
284 | return 0; |
285 | } | |
286 | ||
968910bd NF |
287 | static const struct fb_videomode *atmel_lcdfb_choose_mode(struct fb_var_screeninfo *var, |
288 | struct fb_info *info) | |
289 | { | |
290 | struct fb_videomode varfbmode; | |
291 | const struct fb_videomode *fbmode = NULL; | |
292 | ||
293 | fb_var_to_videomode(&varfbmode, var); | |
294 | fbmode = fb_find_nearest_mode(&varfbmode, &info->modelist); | |
295 | if (fbmode) | |
296 | fb_videomode_to_var(var, fbmode); | |
297 | return fbmode; | |
298 | } | |
299 | ||
300 | ||
14340586 NF |
301 | /** |
302 | * atmel_lcdfb_check_var - Validates a var passed in. | |
303 | * @var: frame buffer variable screen structure | |
304 | * @info: frame buffer structure that represents a single frame buffer | |
305 | * | |
306 | * Checks to see if the hardware supports the state requested by | |
307 | * var passed in. This function does not alter the hardware | |
308 | * state!!! This means the data stored in struct fb_info and | |
309 | * struct atmel_lcdfb_info do not change. This includes the var | |
310 | * inside of struct fb_info. Do NOT change these. This function | |
311 | * can be called on its own if we intent to only test a mode and | |
312 | * not actually set it. The stuff in modedb.c is a example of | |
313 | * this. If the var passed in is slightly off by what the | |
314 | * hardware can support then we alter the var PASSED in to what | |
315 | * we can do. If the hardware doesn't support mode change a | |
316 | * -EINVAL will be returned by the upper layers. You don't need | |
317 | * to implement this function then. If you hardware doesn't | |
318 | * support changing the resolution then this function is not | |
319 | * needed. In this case the driver would just provide a var that | |
320 | * represents the static state the screen is in. | |
321 | * | |
322 | * Returns negative errno on error, or zero on success. | |
323 | */ | |
324 | static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var, | |
325 | struct fb_info *info) | |
326 | { | |
327 | struct device *dev = info->device; | |
328 | struct atmel_lcdfb_info *sinfo = info->par; | |
329 | unsigned long clk_value_khz; | |
330 | ||
331 | clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000; | |
332 | ||
333 | dev_dbg(dev, "%s:\n", __func__); | |
968910bd NF |
334 | |
335 | if (!(var->pixclock && var->bits_per_pixel)) { | |
336 | /* choose a suitable mode if possible */ | |
337 | if (!atmel_lcdfb_choose_mode(var, info)) { | |
338 | dev_err(dev, "needed value not specified\n"); | |
339 | return -EINVAL; | |
340 | } | |
341 | } | |
342 | ||
14340586 NF |
343 | dev_dbg(dev, " resolution: %ux%u\n", var->xres, var->yres); |
344 | dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(var->pixclock)); | |
345 | dev_dbg(dev, " bpp: %u\n", var->bits_per_pixel); | |
346 | dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz); | |
347 | ||
97b9a5a2 | 348 | if (PICOS2KHZ(var->pixclock) > clk_value_khz) { |
14340586 NF |
349 | dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock)); |
350 | return -EINVAL; | |
351 | } | |
352 | ||
968910bd NF |
353 | /* Do not allow to have real resoulution larger than virtual */ |
354 | if (var->xres > var->xres_virtual) | |
355 | var->xres_virtual = var->xres; | |
356 | ||
357 | if (var->yres > var->yres_virtual) | |
358 | var->yres_virtual = var->yres; | |
359 | ||
14340586 NF |
360 | /* Force same alignment for each line */ |
361 | var->xres = (var->xres + 3) & ~3UL; | |
362 | var->xres_virtual = (var->xres_virtual + 3) & ~3UL; | |
363 | ||
364 | var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0; | |
365 | var->transp.msb_right = 0; | |
366 | var->transp.offset = var->transp.length = 0; | |
367 | var->xoffset = var->yoffset = 0; | |
368 | ||
f928ac0a SG |
369 | if (info->fix.smem_len) { |
370 | unsigned int smem_len = (var->xres_virtual * var->yres_virtual | |
371 | * ((var->bits_per_pixel + 7) / 8)); | |
372 | if (smem_len > info->fix.smem_len) | |
373 | return -EINVAL; | |
374 | } | |
375 | ||
162b3a08 HS |
376 | /* Saturate vertical and horizontal timings at maximum values */ |
377 | var->vsync_len = min_t(u32, var->vsync_len, | |
378 | (ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1); | |
379 | var->upper_margin = min_t(u32, var->upper_margin, | |
380 | ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET); | |
381 | var->lower_margin = min_t(u32, var->lower_margin, | |
382 | ATMEL_LCDC_VFP); | |
383 | var->right_margin = min_t(u32, var->right_margin, | |
384 | (ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1); | |
385 | var->hsync_len = min_t(u32, var->hsync_len, | |
386 | (ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1); | |
387 | var->left_margin = min_t(u32, var->left_margin, | |
388 | ATMEL_LCDC_HBP + 1); | |
389 | ||
390 | /* Some parameters can't be zero */ | |
391 | var->vsync_len = max_t(u32, var->vsync_len, 1); | |
392 | var->right_margin = max_t(u32, var->right_margin, 1); | |
393 | var->hsync_len = max_t(u32, var->hsync_len, 1); | |
394 | var->left_margin = max_t(u32, var->left_margin, 1); | |
395 | ||
14340586 | 396 | switch (var->bits_per_pixel) { |
250a269d | 397 | case 1: |
14340586 NF |
398 | case 2: |
399 | case 4: | |
400 | case 8: | |
401 | var->red.offset = var->green.offset = var->blue.offset = 0; | |
402 | var->red.length = var->green.length = var->blue.length | |
403 | = var->bits_per_pixel; | |
404 | break; | |
405 | case 15: | |
406 | case 16: | |
fd085801 NF |
407 | if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { |
408 | /* RGB:565 mode */ | |
409 | var->red.offset = 11; | |
410 | var->blue.offset = 0; | |
411 | var->green.length = 6; | |
fbd03a1c GG |
412 | } else if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB555) { |
413 | var->red.offset = 10; | |
414 | var->blue.offset = 0; | |
415 | var->green.length = 5; | |
fd085801 NF |
416 | } else { |
417 | /* BGR:555 mode */ | |
418 | var->red.offset = 0; | |
419 | var->blue.offset = 10; | |
420 | var->green.length = 5; | |
421 | } | |
14340586 | 422 | var->green.offset = 5; |
fd085801 | 423 | var->red.length = var->blue.length = 5; |
14340586 | 424 | break; |
14340586 | 425 | case 32: |
4440e0e1 HS |
426 | var->transp.offset = 24; |
427 | var->transp.length = 8; | |
428 | /* fall through */ | |
429 | case 24: | |
fd085801 NF |
430 | if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) { |
431 | /* RGB:888 mode */ | |
432 | var->red.offset = 16; | |
433 | var->blue.offset = 0; | |
434 | } else { | |
435 | /* BGR:888 mode */ | |
436 | var->red.offset = 0; | |
437 | var->blue.offset = 16; | |
438 | } | |
14340586 | 439 | var->green.offset = 8; |
14340586 NF |
440 | var->red.length = var->green.length = var->blue.length = 8; |
441 | break; | |
442 | default: | |
443 | dev_err(dev, "color depth %d not supported\n", | |
444 | var->bits_per_pixel); | |
445 | return -EINVAL; | |
446 | } | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
d22579b8 NF |
451 | /* |
452 | * LCD reset sequence | |
453 | */ | |
454 | static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo) | |
455 | { | |
456 | might_sleep(); | |
457 | ||
3aa04f1b HS |
458 | atmel_lcdfb_stop(sinfo); |
459 | atmel_lcdfb_start(sinfo); | |
d22579b8 NF |
460 | } |
461 | ||
14340586 NF |
462 | /** |
463 | * atmel_lcdfb_set_par - Alters the hardware state. | |
464 | * @info: frame buffer structure that represents a single frame buffer | |
465 | * | |
466 | * Using the fb_var_screeninfo in fb_info we set the resolution | |
467 | * of the this particular framebuffer. This function alters the | |
468 | * par AND the fb_fix_screeninfo stored in fb_info. It doesn't | |
469 | * not alter var in fb_info since we are using that data. This | |
470 | * means we depend on the data in var inside fb_info to be | |
471 | * supported by the hardware. atmel_lcdfb_check_var is always called | |
472 | * before atmel_lcdfb_set_par to ensure this. Again if you can't | |
473 | * change the resolution you don't need this function. | |
474 | * | |
475 | */ | |
476 | static int atmel_lcdfb_set_par(struct fb_info *info) | |
477 | { | |
478 | struct atmel_lcdfb_info *sinfo = info->par; | |
250a269d | 479 | unsigned long hozval_linesz; |
14340586 NF |
480 | unsigned long value; |
481 | unsigned long clk_value_khz; | |
250a269d | 482 | unsigned long bits_per_line; |
14340586 | 483 | |
d22579b8 NF |
484 | might_sleep(); |
485 | ||
14340586 NF |
486 | dev_dbg(info->device, "%s:\n", __func__); |
487 | dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n", | |
488 | info->var.xres, info->var.yres, | |
489 | info->var.xres_virtual, info->var.yres_virtual); | |
490 | ||
3aa04f1b | 491 | atmel_lcdfb_stop_nowait(sinfo); |
14340586 | 492 | |
250a269d NF |
493 | if (info->var.bits_per_pixel == 1) |
494 | info->fix.visual = FB_VISUAL_MONO01; | |
495 | else if (info->var.bits_per_pixel <= 8) | |
14340586 NF |
496 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
497 | else | |
498 | info->fix.visual = FB_VISUAL_TRUECOLOR; | |
499 | ||
250a269d NF |
500 | bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel; |
501 | info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8); | |
14340586 NF |
502 | |
503 | /* Re-initialize the DMA engine... */ | |
504 | dev_dbg(info->device, " * update DMA engine\n"); | |
505 | atmel_lcdfb_update_dma(info, &info->var); | |
506 | ||
507 | /* ...set frame size and burst length = 8 words (?) */ | |
508 | value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32; | |
509 | value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET); | |
510 | lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value); | |
511 | ||
512 | /* Now, the LCDC core... */ | |
513 | ||
514 | /* Set pixel clock */ | |
515 | clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000; | |
516 | ||
250a269d | 517 | value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock)); |
14340586 | 518 | |
baf6332a | 519 | if (value < 2) { |
14340586 NF |
520 | dev_notice(info->device, "Bypassing pixel clock divider\n"); |
521 | lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); | |
250a269d | 522 | } else { |
baf6332a NF |
523 | value = (value / 2) - 1; |
524 | dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", | |
525 | value); | |
526 | lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, | |
527 | value << ATMEL_LCDC_CLKVAL_OFFSET); | |
250a269d NF |
528 | info->var.pixclock = KHZ2PICOS(clk_value_khz / (2 * (value + 1))); |
529 | dev_dbg(info->device, " updated pixclk: %lu KHz\n", | |
530 | PICOS2KHZ(info->var.pixclock)); | |
531 | } | |
532 | ||
14340586 NF |
533 | |
534 | /* Initialize control register 2 */ | |
535 | value = sinfo->default_lcdcon2; | |
536 | ||
537 | if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) | |
538 | value |= ATMEL_LCDC_INVLINE_INVERTED; | |
539 | if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) | |
540 | value |= ATMEL_LCDC_INVFRAME_INVERTED; | |
541 | ||
542 | switch (info->var.bits_per_pixel) { | |
543 | case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break; | |
544 | case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break; | |
545 | case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break; | |
546 | case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break; | |
547 | case 15: /* fall through */ | |
548 | case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break; | |
549 | case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break; | |
550 | case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break; | |
551 | default: BUG(); break; | |
552 | } | |
553 | dev_dbg(info->device, " * LCDCON2 = %08lx\n", value); | |
554 | lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value); | |
555 | ||
556 | /* Vertical timing */ | |
557 | value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET; | |
558 | value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET; | |
559 | value |= info->var.lower_margin; | |
560 | dev_dbg(info->device, " * LCDTIM1 = %08lx\n", value); | |
561 | lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value); | |
562 | ||
563 | /* Horizontal timing */ | |
564 | value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET; | |
565 | value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET; | |
566 | value |= (info->var.left_margin - 1); | |
567 | dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value); | |
568 | lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value); | |
569 | ||
250a269d NF |
570 | /* Horizontal value (aka line size) */ |
571 | hozval_linesz = compute_hozval(info->var.xres, | |
572 | lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2)); | |
573 | ||
14340586 | 574 | /* Display size */ |
250a269d | 575 | value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET; |
14340586 | 576 | value |= info->var.yres - 1; |
250a269d | 577 | dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value); |
14340586 NF |
578 | lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value); |
579 | ||
580 | /* FIFO Threshold: Use formula from data sheet */ | |
581 | value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3); | |
582 | lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value); | |
583 | ||
584 | /* Toggle LCD_MODE every frame */ | |
585 | lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0); | |
586 | ||
587 | /* Disable all interrupts */ | |
588 | lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL); | |
d22579b8 NF |
589 | /* Enable FIFO & DMA errors */ |
590 | lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI); | |
14340586 | 591 | |
14340586 NF |
592 | /* ...wait for DMA engine to become idle... */ |
593 | while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY) | |
594 | msleep(10); | |
595 | ||
3aa04f1b | 596 | atmel_lcdfb_start(sinfo); |
14340586 NF |
597 | |
598 | dev_dbg(info->device, " * DONE\n"); | |
599 | ||
600 | return 0; | |
601 | } | |
602 | ||
603 | static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf) | |
604 | { | |
605 | chan &= 0xffff; | |
606 | chan >>= 16 - bf->length; | |
607 | return chan << bf->offset; | |
608 | } | |
609 | ||
610 | /** | |
611 | * atmel_lcdfb_setcolreg - Optional function. Sets a color register. | |
612 | * @regno: Which register in the CLUT we are programming | |
613 | * @red: The red value which can be up to 16 bits wide | |
614 | * @green: The green value which can be up to 16 bits wide | |
615 | * @blue: The blue value which can be up to 16 bits wide. | |
616 | * @transp: If supported the alpha value which can be up to 16 bits wide. | |
617 | * @info: frame buffer info structure | |
618 | * | |
619 | * Set a single color register. The values supplied have a 16 bit | |
620 | * magnitude which needs to be scaled in this function for the hardware. | |
621 | * Things to take into consideration are how many color registers, if | |
622 | * any, are supported with the current color visual. With truecolor mode | |
623 | * no color palettes are supported. Here a psuedo palette is created | |
624 | * which we store the value in pseudo_palette in struct fb_info. For | |
625 | * pseudocolor mode we have a limited color palette. To deal with this | |
626 | * we can program what color is displayed for a particular pixel value. | |
627 | * DirectColor is similar in that we can program each color field. If | |
628 | * we have a static colormap we don't need to implement this function. | |
629 | * | |
630 | * Returns negative errno on error, or zero on success. In an | |
631 | * ideal world, this would have been the case, but as it turns | |
632 | * out, the other drivers return 1 on failure, so that's what | |
633 | * we're going to do. | |
634 | */ | |
635 | static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red, | |
636 | unsigned int green, unsigned int blue, | |
637 | unsigned int transp, struct fb_info *info) | |
638 | { | |
639 | struct atmel_lcdfb_info *sinfo = info->par; | |
640 | unsigned int val; | |
641 | u32 *pal; | |
642 | int ret = 1; | |
643 | ||
644 | if (info->var.grayscale) | |
645 | red = green = blue = (19595 * red + 38470 * green | |
646 | + 7471 * blue) >> 16; | |
647 | ||
648 | switch (info->fix.visual) { | |
649 | case FB_VISUAL_TRUECOLOR: | |
650 | if (regno < 16) { | |
651 | pal = info->pseudo_palette; | |
652 | ||
653 | val = chan_to_field(red, &info->var.red); | |
654 | val |= chan_to_field(green, &info->var.green); | |
655 | val |= chan_to_field(blue, &info->var.blue); | |
656 | ||
657 | pal[regno] = val; | |
658 | ret = 0; | |
659 | } | |
660 | break; | |
661 | ||
662 | case FB_VISUAL_PSEUDOCOLOR: | |
663 | if (regno < 256) { | |
664 | val = ((red >> 11) & 0x001f); | |
665 | val |= ((green >> 6) & 0x03e0); | |
666 | val |= ((blue >> 1) & 0x7c00); | |
667 | ||
668 | /* | |
669 | * TODO: intensity bit. Maybe something like | |
670 | * ~(red[10] ^ green[10] ^ blue[10]) & 1 | |
671 | */ | |
672 | ||
673 | lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val); | |
674 | ret = 0; | |
675 | } | |
676 | break; | |
250a269d NF |
677 | |
678 | case FB_VISUAL_MONO01: | |
679 | if (regno < 2) { | |
680 | val = (regno == 0) ? 0x00 : 0x1F; | |
681 | lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val); | |
682 | ret = 0; | |
683 | } | |
684 | break; | |
685 | ||
14340586 NF |
686 | } |
687 | ||
688 | return ret; | |
689 | } | |
690 | ||
691 | static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var, | |
692 | struct fb_info *info) | |
693 | { | |
694 | dev_dbg(info->device, "%s\n", __func__); | |
695 | ||
696 | atmel_lcdfb_update_dma(info, var); | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
701 | static struct fb_ops atmel_lcdfb_ops = { | |
702 | .owner = THIS_MODULE, | |
703 | .fb_check_var = atmel_lcdfb_check_var, | |
704 | .fb_set_par = atmel_lcdfb_set_par, | |
705 | .fb_setcolreg = atmel_lcdfb_setcolreg, | |
706 | .fb_pan_display = atmel_lcdfb_pan_display, | |
707 | .fb_fillrect = cfb_fillrect, | |
708 | .fb_copyarea = cfb_copyarea, | |
709 | .fb_imageblit = cfb_imageblit, | |
710 | }; | |
711 | ||
712 | static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id) | |
713 | { | |
714 | struct fb_info *info = dev_id; | |
715 | struct atmel_lcdfb_info *sinfo = info->par; | |
716 | u32 status; | |
717 | ||
718 | status = lcdc_readl(sinfo, ATMEL_LCDC_ISR); | |
d22579b8 NF |
719 | if (status & ATMEL_LCDC_UFLWI) { |
720 | dev_warn(info->device, "FIFO underflow %#x\n", status); | |
721 | /* reset DMA and FIFO to avoid screen shifting */ | |
722 | schedule_work(&sinfo->task); | |
723 | } | |
724 | lcdc_writel(sinfo, ATMEL_LCDC_ICR, status); | |
14340586 NF |
725 | return IRQ_HANDLED; |
726 | } | |
727 | ||
d22579b8 NF |
728 | /* |
729 | * LCD controller task (to reset the LCD) | |
730 | */ | |
731 | static void atmel_lcdfb_task(struct work_struct *work) | |
732 | { | |
733 | struct atmel_lcdfb_info *sinfo = | |
734 | container_of(work, struct atmel_lcdfb_info, task); | |
735 | ||
736 | atmel_lcdfb_reset(sinfo); | |
737 | } | |
738 | ||
14340586 NF |
739 | static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo) |
740 | { | |
741 | struct fb_info *info = sinfo->info; | |
742 | int ret = 0; | |
743 | ||
14340586 NF |
744 | info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW; |
745 | ||
746 | dev_info(info->device, | |
747 | "%luKiB frame buffer at %08lx (mapped at %p)\n", | |
748 | (unsigned long)info->fix.smem_len / 1024, | |
749 | (unsigned long)info->fix.smem_start, | |
750 | info->screen_base); | |
751 | ||
752 | /* Allocate colormap */ | |
753 | ret = fb_alloc_cmap(&info->cmap, 256, 0); | |
754 | if (ret < 0) | |
755 | dev_err(info->device, "Alloc color map failed\n"); | |
756 | ||
757 | return ret; | |
758 | } | |
759 | ||
760 | static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo) | |
761 | { | |
762 | if (sinfo->bus_clk) | |
763 | clk_enable(sinfo->bus_clk); | |
764 | clk_enable(sinfo->lcdc_clk); | |
765 | } | |
766 | ||
767 | static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo) | |
768 | { | |
769 | if (sinfo->bus_clk) | |
770 | clk_disable(sinfo->bus_clk); | |
771 | clk_disable(sinfo->lcdc_clk); | |
772 | } | |
773 | ||
774 | ||
775 | static int __init atmel_lcdfb_probe(struct platform_device *pdev) | |
776 | { | |
777 | struct device *dev = &pdev->dev; | |
778 | struct fb_info *info; | |
779 | struct atmel_lcdfb_info *sinfo; | |
780 | struct atmel_lcdfb_info *pdata_sinfo; | |
968910bd | 781 | struct fb_videomode fbmode; |
14340586 NF |
782 | struct resource *regs = NULL; |
783 | struct resource *map = NULL; | |
784 | int ret; | |
785 | ||
786 | dev_dbg(dev, "%s BEGIN\n", __func__); | |
787 | ||
788 | ret = -ENOMEM; | |
789 | info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev); | |
790 | if (!info) { | |
791 | dev_err(dev, "cannot allocate memory\n"); | |
792 | goto out; | |
793 | } | |
794 | ||
795 | sinfo = info->par; | |
796 | ||
797 | if (dev->platform_data) { | |
798 | pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data; | |
799 | sinfo->default_bpp = pdata_sinfo->default_bpp; | |
800 | sinfo->default_dmacon = pdata_sinfo->default_dmacon; | |
801 | sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2; | |
802 | sinfo->default_monspecs = pdata_sinfo->default_monspecs; | |
803 | sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control; | |
804 | sinfo->guard_time = pdata_sinfo->guard_time; | |
ea757aca | 805 | sinfo->smem_len = pdata_sinfo->smem_len; |
a9a84c37 | 806 | sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight; |
fd085801 | 807 | sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode; |
14340586 NF |
808 | } else { |
809 | dev_err(dev, "cannot get default configuration\n"); | |
810 | goto free_info; | |
811 | } | |
812 | sinfo->info = info; | |
813 | sinfo->pdev = pdev; | |
814 | ||
815 | strcpy(info->fix.id, sinfo->pdev->name); | |
816 | info->flags = ATMEL_LCDFB_FBINFO_DEFAULT; | |
817 | info->pseudo_palette = sinfo->pseudo_palette; | |
818 | info->fbops = &atmel_lcdfb_ops; | |
819 | ||
820 | memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs)); | |
821 | info->fix = atmel_lcdfb_fix; | |
822 | ||
823 | /* Enable LCDC Clocks */ | |
824 | if (cpu_is_at91sam9261() || cpu_is_at32ap7000()) { | |
825 | sinfo->bus_clk = clk_get(dev, "hck1"); | |
826 | if (IS_ERR(sinfo->bus_clk)) { | |
827 | ret = PTR_ERR(sinfo->bus_clk); | |
828 | goto free_info; | |
829 | } | |
830 | } | |
831 | sinfo->lcdc_clk = clk_get(dev, "lcdc_clk"); | |
832 | if (IS_ERR(sinfo->lcdc_clk)) { | |
833 | ret = PTR_ERR(sinfo->lcdc_clk); | |
834 | goto put_bus_clk; | |
835 | } | |
836 | atmel_lcdfb_start_clock(sinfo); | |
837 | ||
838 | ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb, | |
839 | info->monspecs.modedb_len, info->monspecs.modedb, | |
840 | sinfo->default_bpp); | |
841 | if (!ret) { | |
842 | dev_err(dev, "no suitable video mode found\n"); | |
843 | goto stop_clk; | |
844 | } | |
845 | ||
846 | ||
847 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
848 | if (!regs) { | |
849 | dev_err(dev, "resources unusable\n"); | |
850 | ret = -ENXIO; | |
851 | goto stop_clk; | |
852 | } | |
853 | ||
854 | sinfo->irq_base = platform_get_irq(pdev, 0); | |
855 | if (sinfo->irq_base < 0) { | |
856 | dev_err(dev, "unable to get irq\n"); | |
857 | ret = sinfo->irq_base; | |
858 | goto stop_clk; | |
859 | } | |
860 | ||
861 | /* Initialize video memory */ | |
862 | map = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
863 | if (map) { | |
864 | /* use a pre-allocated memory buffer */ | |
865 | info->fix.smem_start = map->start; | |
866 | info->fix.smem_len = map->end - map->start + 1; | |
867 | if (!request_mem_region(info->fix.smem_start, | |
868 | info->fix.smem_len, pdev->name)) { | |
869 | ret = -EBUSY; | |
870 | goto stop_clk; | |
871 | } | |
872 | ||
873 | info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len); | |
874 | if (!info->screen_base) | |
875 | goto release_intmem; | |
01d3a5e7 HS |
876 | |
877 | /* | |
878 | * Don't clear the framebuffer -- someone may have set | |
879 | * up a splash image. | |
880 | */ | |
14340586 NF |
881 | } else { |
882 | /* alocate memory buffer */ | |
883 | ret = atmel_lcdfb_alloc_video_memory(sinfo); | |
884 | if (ret < 0) { | |
885 | dev_err(dev, "cannot allocate framebuffer: %d\n", ret); | |
886 | goto stop_clk; | |
887 | } | |
888 | } | |
889 | ||
890 | /* LCDC registers */ | |
891 | info->fix.mmio_start = regs->start; | |
892 | info->fix.mmio_len = regs->end - regs->start + 1; | |
893 | ||
894 | if (!request_mem_region(info->fix.mmio_start, | |
895 | info->fix.mmio_len, pdev->name)) { | |
896 | ret = -EBUSY; | |
897 | goto free_fb; | |
898 | } | |
899 | ||
900 | sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len); | |
901 | if (!sinfo->mmio) { | |
902 | dev_err(dev, "cannot map LCDC registers\n"); | |
903 | goto release_mem; | |
904 | } | |
905 | ||
a9a84c37 DB |
906 | /* Initialize PWM for contrast or backlight ("off") */ |
907 | init_contrast(sinfo); | |
908 | ||
14340586 NF |
909 | /* interrupt */ |
910 | ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info); | |
911 | if (ret) { | |
912 | dev_err(dev, "request_irq failed: %d\n", ret); | |
913 | goto unmap_mmio; | |
914 | } | |
915 | ||
d22579b8 NF |
916 | /* Some operations on the LCDC might sleep and |
917 | * require a preemptible task context */ | |
918 | INIT_WORK(&sinfo->task, atmel_lcdfb_task); | |
919 | ||
14340586 NF |
920 | ret = atmel_lcdfb_init_fbinfo(sinfo); |
921 | if (ret < 0) { | |
922 | dev_err(dev, "init fbinfo failed: %d\n", ret); | |
923 | goto unregister_irqs; | |
924 | } | |
925 | ||
926 | /* | |
927 | * This makes sure that our colour bitfield | |
928 | * descriptors are correctly initialised. | |
929 | */ | |
930 | atmel_lcdfb_check_var(&info->var, info); | |
931 | ||
932 | ret = fb_set_var(info, &info->var); | |
933 | if (ret) { | |
934 | dev_warn(dev, "unable to set display parameters\n"); | |
935 | goto free_cmap; | |
936 | } | |
937 | ||
938 | dev_set_drvdata(dev, info); | |
939 | ||
940 | /* | |
941 | * Tell the world that we're ready to go | |
942 | */ | |
943 | ret = register_framebuffer(info); | |
944 | if (ret < 0) { | |
945 | dev_err(dev, "failed to register framebuffer device: %d\n", ret); | |
34a35bdd | 946 | goto reset_drvdata; |
14340586 NF |
947 | } |
948 | ||
968910bd NF |
949 | /* add selected videomode to modelist */ |
950 | fb_var_to_videomode(&fbmode, &info->var); | |
951 | fb_add_videomode(&fbmode, &info->modelist); | |
952 | ||
14340586 NF |
953 | /* Power up the LCDC screen */ |
954 | if (sinfo->atmel_lcdfb_power_control) | |
955 | sinfo->atmel_lcdfb_power_control(1); | |
956 | ||
957 | dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %lu\n", | |
958 | info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base); | |
959 | ||
960 | return 0; | |
961 | ||
34a35bdd SG |
962 | reset_drvdata: |
963 | dev_set_drvdata(dev, NULL); | |
14340586 NF |
964 | free_cmap: |
965 | fb_dealloc_cmap(&info->cmap); | |
966 | unregister_irqs: | |
d22579b8 | 967 | cancel_work_sync(&sinfo->task); |
14340586 NF |
968 | free_irq(sinfo->irq_base, info); |
969 | unmap_mmio: | |
a9a84c37 | 970 | exit_backlight(sinfo); |
14340586 NF |
971 | iounmap(sinfo->mmio); |
972 | release_mem: | |
973 | release_mem_region(info->fix.mmio_start, info->fix.mmio_len); | |
974 | free_fb: | |
975 | if (map) | |
976 | iounmap(info->screen_base); | |
977 | else | |
978 | atmel_lcdfb_free_video_memory(sinfo); | |
979 | ||
980 | release_intmem: | |
981 | if (map) | |
982 | release_mem_region(info->fix.smem_start, info->fix.smem_len); | |
983 | stop_clk: | |
984 | atmel_lcdfb_stop_clock(sinfo); | |
985 | clk_put(sinfo->lcdc_clk); | |
986 | put_bus_clk: | |
987 | if (sinfo->bus_clk) | |
988 | clk_put(sinfo->bus_clk); | |
989 | free_info: | |
990 | framebuffer_release(info); | |
991 | out: | |
992 | dev_dbg(dev, "%s FAILED\n", __func__); | |
993 | return ret; | |
994 | } | |
995 | ||
996 | static int __exit atmel_lcdfb_remove(struct platform_device *pdev) | |
997 | { | |
998 | struct device *dev = &pdev->dev; | |
999 | struct fb_info *info = dev_get_drvdata(dev); | |
34a35bdd | 1000 | struct atmel_lcdfb_info *sinfo; |
14340586 | 1001 | |
34a35bdd | 1002 | if (!info || !info->par) |
14340586 | 1003 | return 0; |
34a35bdd | 1004 | sinfo = info->par; |
14340586 | 1005 | |
d22579b8 | 1006 | cancel_work_sync(&sinfo->task); |
a9a84c37 | 1007 | exit_backlight(sinfo); |
14340586 NF |
1008 | if (sinfo->atmel_lcdfb_power_control) |
1009 | sinfo->atmel_lcdfb_power_control(0); | |
1010 | unregister_framebuffer(info); | |
1011 | atmel_lcdfb_stop_clock(sinfo); | |
1012 | clk_put(sinfo->lcdc_clk); | |
1013 | if (sinfo->bus_clk) | |
1014 | clk_put(sinfo->bus_clk); | |
1015 | fb_dealloc_cmap(&info->cmap); | |
1016 | free_irq(sinfo->irq_base, info); | |
1017 | iounmap(sinfo->mmio); | |
1018 | release_mem_region(info->fix.mmio_start, info->fix.mmio_len); | |
1019 | if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) { | |
1020 | iounmap(info->screen_base); | |
1021 | release_mem_region(info->fix.smem_start, info->fix.smem_len); | |
1022 | } else { | |
1023 | atmel_lcdfb_free_video_memory(sinfo); | |
1024 | } | |
1025 | ||
1026 | dev_set_drvdata(dev, NULL); | |
1027 | framebuffer_release(info); | |
1028 | ||
1029 | return 0; | |
1030 | } | |
1031 | ||
cf19a37e DB |
1032 | #ifdef CONFIG_PM |
1033 | ||
1034 | static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg) | |
1035 | { | |
1036 | struct fb_info *info = platform_get_drvdata(pdev); | |
1037 | struct atmel_lcdfb_info *sinfo = info->par; | |
1038 | ||
3aa04f1b HS |
1039 | /* |
1040 | * We don't want to handle interrupts while the clock is | |
1041 | * stopped. It may take forever. | |
1042 | */ | |
1043 | lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL); | |
1044 | ||
cf19a37e DB |
1045 | sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL); |
1046 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0); | |
1047 | if (sinfo->atmel_lcdfb_power_control) | |
1048 | sinfo->atmel_lcdfb_power_control(0); | |
3aa04f1b HS |
1049 | |
1050 | atmel_lcdfb_stop(sinfo); | |
cf19a37e | 1051 | atmel_lcdfb_stop_clock(sinfo); |
3aa04f1b | 1052 | |
cf19a37e DB |
1053 | return 0; |
1054 | } | |
1055 | ||
1056 | static int atmel_lcdfb_resume(struct platform_device *pdev) | |
1057 | { | |
1058 | struct fb_info *info = platform_get_drvdata(pdev); | |
1059 | struct atmel_lcdfb_info *sinfo = info->par; | |
1060 | ||
1061 | atmel_lcdfb_start_clock(sinfo); | |
3aa04f1b | 1062 | atmel_lcdfb_start(sinfo); |
cf19a37e DB |
1063 | if (sinfo->atmel_lcdfb_power_control) |
1064 | sinfo->atmel_lcdfb_power_control(1); | |
1065 | lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon); | |
3aa04f1b HS |
1066 | |
1067 | /* Enable FIFO & DMA errors */ | |
1068 | lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | |
1069 | | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI); | |
1070 | ||
cf19a37e DB |
1071 | return 0; |
1072 | } | |
1073 | ||
1074 | #else | |
1075 | #define atmel_lcdfb_suspend NULL | |
1076 | #define atmel_lcdfb_resume NULL | |
1077 | #endif | |
1078 | ||
14340586 NF |
1079 | static struct platform_driver atmel_lcdfb_driver = { |
1080 | .remove = __exit_p(atmel_lcdfb_remove), | |
cf19a37e DB |
1081 | .suspend = atmel_lcdfb_suspend, |
1082 | .resume = atmel_lcdfb_resume, | |
a9a84c37 | 1083 | |
14340586 NF |
1084 | .driver = { |
1085 | .name = "atmel_lcdfb", | |
1086 | .owner = THIS_MODULE, | |
1087 | }, | |
1088 | }; | |
1089 | ||
1090 | static int __init atmel_lcdfb_init(void) | |
1091 | { | |
1092 | return platform_driver_probe(&atmel_lcdfb_driver, atmel_lcdfb_probe); | |
1093 | } | |
1094 | ||
1095 | static void __exit atmel_lcdfb_exit(void) | |
1096 | { | |
1097 | platform_driver_unregister(&atmel_lcdfb_driver); | |
1098 | } | |
1099 | ||
1100 | module_init(atmel_lcdfb_init); | |
1101 | module_exit(atmel_lcdfb_exit); | |
1102 | ||
1103 | MODULE_DESCRIPTION("AT91/AT32 LCD Controller framebuffer driver"); | |
8f4c79ce | 1104 | MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); |
14340586 | 1105 | MODULE_LICENSE("GPL"); |