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Drivers: video: remove __dev* attributes.
[mirror_ubuntu-zesty-kernel.git] / drivers / video / aty / aty128fb.c
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1da177e4
LT		 1/* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Michel Danzer <michdaen@iiic.ethz.ch>
11 * - 15/16 bit cleanup
12 * - fix panning
13 *
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
17 *
18 * Andreas Hundt <andi@convergence.de>
19 * - FB_ACTIVATE fixes
20 *
21 * Paul Mackerras <paulus@samba.org>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
24 *
25 * Paul Mundt
26 * - PCI hotplug
27 *
28 * Jon Smirl <jonsmirl@yahoo.com>
29 * - PCI ID update
30 * - replace ROM BIOS search
31 *
32 * Based off of Geert's atyfb.c and vfb.c.
33 *
34 * TODO:
35 * - monitor sensing (DDC)
36 * - virtual display
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
39 *
40 * Please cc: your patches to brad@neruo.com.
41 */
42
43/*
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
46 */
47
48
1da177e4
LT		 49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/kernel.h>
52#include <linux/errno.h>
53#include <linux/string.h>
54#include <linux/mm.h>
1da177e4
LT		 55#include <linux/vmalloc.h>
56#include <linux/delay.h>
57#include <linux/interrupt.h>
84902b7a 58#include <linux/uaccess.h>
1da177e4
LT		 59#include <linux/fb.h>
60#include <linux/init.h>
61#include <linux/pci.h>
62#include <linux/ioport.h>
63#include <linux/console.h>
5474c120 64#include <linux/backlight.h>
1da177e4
LT		 65#include <asm/io.h>
66
67#ifdef CONFIG_PPC_PMAC
e8222502 68#include <asm/machdep.h>
1da177e4
LT		 69#include <asm/pmac_feature.h>
70#include <asm/prom.h>
71#include <asm/pci-bridge.h>
72#include "../macmodes.h"
73#endif
74
75#ifdef CONFIG_PMAC_BACKLIGHT
76#include <asm/backlight.h>
77#endif
78
79#ifdef CONFIG_BOOTX_TEXT
80#include <asm/btext.h>
81#endif /* CONFIG_BOOTX_TEXT */
82
83#ifdef CONFIG_MTRR
84#include <asm/mtrr.h>
85#endif
86
87#include <video/aty128.h>
88
89/* Debug flag */
90#undef DEBUG
91
92#ifdef DEBUG
659f675e
EG		 93#define DBG(fmt, args...) \
94 printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args);
1da177e4
LT		 95#else
96#define DBG(fmt, args...)
97#endif
98
99#ifndef CONFIG_PPC_PMAC
100/* default mode */
48c68c4f 101static struct fb_var_screeninfo default_var = {
1da177e4
LT		 102 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
103 640, 480, 640, 480, 0, 0, 8, 0,
104 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
105 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
106 0, FB_VMODE_NONINTERLACED
107};
108
109#else /* CONFIG_PPC_PMAC */
110/* default to 1024x768 at 75Hz on PPC - this will work
111 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
112static struct fb_var_screeninfo default_var = {
113 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
114 1024, 768, 1024, 768, 0, 0, 8, 0,
115 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
116 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
117 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
118 FB_VMODE_NONINTERLACED
119};
120#endif /* CONFIG_PPC_PMAC */
121
122/* default modedb mode */
123/* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
48c68c4f 124static struct fb_videomode defaultmode = {
1da177e4
LT		 125 .refresh = 60,
126 .xres = 640,
127 .yres = 480,
128 .pixclock = 39722,
129 .left_margin = 48,
130 .right_margin = 16,
131 .upper_margin = 33,
132 .lower_margin = 10,
133 .hsync_len = 96,
134 .vsync_len = 2,
135 .sync = 0,
136 .vmode = FB_VMODE_NONINTERLACED
137};
138
139/* Chip generations */
140enum {
141 rage_128,
142 rage_128_pci,
143 rage_128_pro,
144 rage_128_pro_pci,
145 rage_M3,
146 rage_M3_pci,
147 rage_M4,
148 rage_128_ultra,
149};
150
151/* Must match above enum */
48c68c4f 152static char * const r128_family[] = {
1da177e4
LT		 153 "AGP",
154 "PCI",
155 "PRO AGP",
156 "PRO PCI",
157 "M3 AGP",
158 "M3 PCI",
159 "M4 AGP",
160 "Ultra AGP",
161};
162
163/*
164 * PCI driver prototypes
165 */
166static int aty128_probe(struct pci_dev *pdev,
167 const struct pci_device_id *ent);
168static void aty128_remove(struct pci_dev *pdev);
169static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
170static int aty128_pci_resume(struct pci_dev *pdev);
171static int aty128_do_resume(struct pci_dev *pdev);
172
173/* supported Rage128 chipsets */
174static struct pci_device_id aty128_pci_tbl[] = {
175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
269 { 0, }
270};
271
272MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
273
274static struct pci_driver aty128fb_driver = {
275 .name = "aty128fb",
276 .id_table = aty128_pci_tbl,
277 .probe = aty128_probe,
48c68c4f 278 .remove = aty128_remove,
1da177e4
LT		 279 .suspend = aty128_pci_suspend,
280 .resume = aty128_pci_resume,
281};
282
283/* packed BIOS settings */
284#ifndef CONFIG_PPC
285typedef struct {
286 u8 clock_chip_type;
287 u8 struct_size;
288 u8 accelerator_entry;
289 u8 VGA_entry;
290 u16 VGA_table_offset;
291 u16 POST_table_offset;
292 u16 XCLK;
293 u16 MCLK;
294 u8 num_PLL_blocks;
295 u8 size_PLL_blocks;
296 u16 PCLK_ref_freq;
297 u16 PCLK_ref_divider;
298 u32 PCLK_min_freq;
299 u32 PCLK_max_freq;
300 u16 MCLK_ref_freq;
301 u16 MCLK_ref_divider;
302 u32 MCLK_min_freq;
303 u32 MCLK_max_freq;
304 u16 XCLK_ref_freq;
305 u16 XCLK_ref_divider;
306 u32 XCLK_min_freq;
307 u32 XCLK_max_freq;
308} __attribute__ ((packed)) PLL_BLOCK;
309#endif /* !CONFIG_PPC */
310
311/* onboard memory information */
312struct aty128_meminfo {
313 u8 ML;
314 u8 MB;
315 u8 Trcd;
316 u8 Trp;
317 u8 Twr;
318 u8 CL;
319 u8 Tr2w;
320 u8 LoopLatency;
321 u8 DspOn;
322 u8 Rloop;
323 const char *name;
324};
325
326/* various memory configurations */
327static const struct aty128_meminfo sdr_128 =
328 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
329static const struct aty128_meminfo sdr_64 =
330 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
331static const struct aty128_meminfo sdr_sgram =
332 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
333static const struct aty128_meminfo ddr_sgram =
334 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
335
48c68c4f 336static struct fb_fix_screeninfo aty128fb_fix = {
1da177e4
LT		 337 .id = "ATY Rage128",
338 .type = FB_TYPE_PACKED_PIXELS,
339 .visual = FB_VISUAL_PSEUDOCOLOR,
340 .xpanstep = 8,
341 .ypanstep = 1,
342 .mmio_len = 0x2000,
343 .accel = FB_ACCEL_ATI_RAGE128,
344};
345
48c68c4f 346static char *mode_option = NULL;
1da177e4
LT		 347
348#ifdef CONFIG_PPC_PMAC
48c68c4f
GKH		 349static int default_vmode = VMODE_1024_768_60;
350static int default_cmode = CMODE_8;
1da177e4
LT		 351#endif
352
48c68c4f
GKH		 353static int default_crt_on = 0;
354static int default_lcd_on = 1;
1da177e4
LT		 355
356#ifdef CONFIG_MTRR
9a71af2c 357static bool mtrr = true;
1da177e4
LT		 358#endif
359
202d4e60 360#ifdef CONFIG_PMAC_BACKLIGHT
48c68c4f 361static int backlight = 1;
202d4e60 362#else
48c68c4f 363static int backlight = 0;
202d4e60
RP		 364#endif
365
1da177e4
LT		 366/* PLL constants */
367struct aty128_constants {
368 u32 ref_clk;
369 u32 ppll_min;
370 u32 ppll_max;
371 u32 ref_divider;
372 u32 xclk;
373 u32 fifo_width;
374 u32 fifo_depth;
375};
376
377struct aty128_crtc {
378 u32 gen_cntl;
379 u32 h_total, h_sync_strt_wid;
380 u32 v_total, v_sync_strt_wid;
381 u32 pitch;
382 u32 offset, offset_cntl;
383 u32 xoffset, yoffset;
384 u32 vxres, vyres;
385 u32 depth, bpp;
386};
387
388struct aty128_pll {
389 u32 post_divider;
390 u32 feedback_divider;
391 u32 vclk;
392};
393
394struct aty128_ddafifo {
395 u32 dda_config;
396 u32 dda_on_off;
397};
398
399/* register values for a specific mode */
400struct aty128fb_par {
401 struct aty128_crtc crtc;
402 struct aty128_pll pll;
403 struct aty128_ddafifo fifo_reg;
404 u32 accel_flags;
405 struct aty128_constants constants; /* PLL and others */
406 void __iomem *regbase; /* remapped mmio */
407 u32 vram_size; /* onboard video ram */
408 int chip_gen;
409 const struct aty128_meminfo *mem; /* onboard mem info */
410#ifdef CONFIG_MTRR
411 struct { int vram; int vram_valid; } mtrr;
412#endif
413 int blitter_may_be_busy;
414 int fifo_slots; /* free slots in FIFO (64 max) */
415
416 int pm_reg;
417 int crt_on, lcd_on;
418 struct pci_dev *pdev;
419 struct fb_info *next;
420 int asleep;
421 int lock_blank;
422
423 u8 red[32]; /* see aty128fb_setcolreg */
424 u8 green[64];
425 u8 blue[32];
426 u32 pseudo_palette[16]; /* used for TRUECOLOR */
427};
428
429
430#define round_div(n, d) ((n+(d/2))/d)
431
432static int aty128fb_check_var(struct fb_var_screeninfo *var,
433 struct fb_info *info);
434static int aty128fb_set_par(struct fb_info *info);
435static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
436 u_int transp, struct fb_info *info);
437static int aty128fb_pan_display(struct fb_var_screeninfo *var,
438 struct fb_info *fb);
439static int aty128fb_blank(int blank, struct fb_info *fb);
67a6680d 440static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
1da177e4
LT		 441static int aty128fb_sync(struct fb_info *info);
442
443 /*
444 * Internal routines
445 */
446
447static int aty128_encode_var(struct fb_var_screeninfo *var,
448 const struct aty128fb_par *par);
449static int aty128_decode_var(struct fb_var_screeninfo *var,
450 struct aty128fb_par *par);
451#if 0
48c68c4f
GKH		 452static void aty128_get_pllinfo(struct aty128fb_par *par, void __iomem *bios);
453static void __iomem *aty128_map_ROM(struct pci_dev *pdev,
454 const struct aty128fb_par *par);
1da177e4
LT		 455#endif
456static void aty128_timings(struct aty128fb_par *par);
457static void aty128_init_engine(struct aty128fb_par *par);
458static void aty128_reset_engine(const struct aty128fb_par *par);
459static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
460static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
461static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
462static void wait_for_idle(struct aty128fb_par *par);
463static u32 depth_to_dst(u32 depth);
4b755999
MH		 464
465#ifdef CONFIG_FB_ATY128_BACKLIGHT
e01af038 466static void aty128_bl_set_power(struct fb_info *info, int power);
4b755999 467#endif
1da177e4
LT		 468
469#define BIOS_IN8(v) (readb(bios + (v)))
470#define BIOS_IN16(v) (readb(bios + (v)) | \
471 (readb(bios + (v) + 1) << 8))
472#define BIOS_IN32(v) (readb(bios + (v)) | \
473 (readb(bios + (v) + 1) << 8) | \
474 (readb(bios + (v) + 2) << 16) | \
475 (readb(bios + (v) + 3) << 24))
476
477
478static struct fb_ops aty128fb_ops = {
479 .owner = THIS_MODULE,
480 .fb_check_var = aty128fb_check_var,
481 .fb_set_par = aty128fb_set_par,
482 .fb_setcolreg = aty128fb_setcolreg,
483 .fb_pan_display = aty128fb_pan_display,
484 .fb_blank = aty128fb_blank,
485 .fb_ioctl = aty128fb_ioctl,
486 .fb_sync = aty128fb_sync,
487 .fb_fillrect = cfb_fillrect,
488 .fb_copyarea = cfb_copyarea,
489 .fb_imageblit = cfb_imageblit,
1da177e4
LT		 490};
491
1da177e4
LT		 492 /*
493 * Functions to read from/write to the mmio registers
494 * - endian conversions may possibly be avoided by
495 * using the other register aperture. TODO.
496 */
497static inline u32 _aty_ld_le32(volatile unsigned int regindex,
498 const struct aty128fb_par *par)
499{
500 return readl (par->regbase + regindex);
501}
502
503static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
504 const struct aty128fb_par *par)
505{
506 writel (val, par->regbase + regindex);
507}
508
509static inline u8 _aty_ld_8(unsigned int regindex,
510 const struct aty128fb_par *par)
511{
512 return readb (par->regbase + regindex);
513}
514
515static inline void _aty_st_8(unsigned int regindex, u8 val,
516 const struct aty128fb_par *par)
517{
518 writeb (val, par->regbase + regindex);
519}
520
521#define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
522#define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
523#define aty_ld_8(regindex) _aty_ld_8(regindex, par)
524#define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
525
526 /*
527 * Functions to read from/write to the pll registers
528 */
529
530#define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
531#define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
532
533
534static u32 _aty_ld_pll(unsigned int pll_index,
535 const struct aty128fb_par *par)
536{
537 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
538 return aty_ld_le32(CLOCK_CNTL_DATA);
539}
540
541
542static void _aty_st_pll(unsigned int pll_index, u32 val,
543 const struct aty128fb_par *par)
544{
545 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
546 aty_st_le32(CLOCK_CNTL_DATA, val);
547}
548
549
550/* return true when the PLL has completed an atomic update */
551static int aty_pll_readupdate(const struct aty128fb_par *par)
552{
553 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
554}
555
556
557static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
558{
559 unsigned long timeout = jiffies + HZ/100; // should be more than enough
560 int reset = 1;
561
562 while (time_before(jiffies, timeout))
563 if (aty_pll_readupdate(par)) {
564 reset = 0;
565 break;
566 }
567
568 if (reset) /* reset engine?? */
569 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
570}
571
572
573/* tell PLL to update */
574static void aty_pll_writeupdate(const struct aty128fb_par *par)
575{
576 aty_pll_wait_readupdate(par);
577
578 aty_st_pll(PPLL_REF_DIV,
579 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
580}
581
582
583/* write to the scratch register to test r/w functionality */
48c68c4f 584static int register_test(const struct aty128fb_par *par)
1da177e4
LT		 585{
586 u32 val;
587 int flag = 0;
588
589 val = aty_ld_le32(BIOS_0_SCRATCH);
590
591 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
592 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
593 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
594
595 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
596 flag = 1;
597 }
598
599 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
600 return flag;
601}
602
603
604/*
605 * Accelerator engine functions
606 */
607static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
608{
609 int i;
610
611 for (;;) {
612 for (i = 0; i < 2000000; i++) {
613 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
614 if (par->fifo_slots >= entries)
615 return;
616 }
617 aty128_reset_engine(par);
618 }
619}
620
621
622static void wait_for_idle(struct aty128fb_par *par)
623{
624 int i;
625
626 do_wait_for_fifo(64, par);
627
628 for (;;) {
629 for (i = 0; i < 2000000; i++) {
630 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
631 aty128_flush_pixel_cache(par);
632 par->blitter_may_be_busy = 0;
633 return;
634 }
635 }
636 aty128_reset_engine(par);
637 }
638}
639
640
641static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
642{
643 if (par->fifo_slots < entries)
644 do_wait_for_fifo(64, par);
645 par->fifo_slots -= entries;
646}
647
648
649static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
650{
651 int i;
652 u32 tmp;
653
654 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
655 tmp &= ~(0x00ff);
656 tmp |= 0x00ff;
657 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
658
659 for (i = 0; i < 2000000; i++)
660 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
661 break;
662}
663
664
665static void aty128_reset_engine(const struct aty128fb_par *par)
666{
667 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
668
669 aty128_flush_pixel_cache(par);
670
671 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
672 mclk_cntl = aty_ld_pll(MCLK_CNTL);
673
674 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
675
676 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
677 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
678 aty_ld_le32(GEN_RESET_CNTL);
679 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
680 aty_ld_le32(GEN_RESET_CNTL);
681
682 aty_st_pll(MCLK_CNTL, mclk_cntl);
683 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
684 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
685
686 /* use old pio mode */
687 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
688
689 DBG("engine reset");
690}
691
692
693static void aty128_init_engine(struct aty128fb_par *par)
694{
695 u32 pitch_value;
696
697 wait_for_idle(par);
698
699 /* 3D scaler not spoken here */
700 wait_for_fifo(1, par);
701 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
702
703 aty128_reset_engine(par);
704
705 pitch_value = par->crtc.pitch;
706 if (par->crtc.bpp == 24) {
707 pitch_value = pitch_value * 3;
708 }
709
710 wait_for_fifo(4, par);
711 /* setup engine offset registers */
712 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
713
714 /* setup engine pitch registers */
715 aty_st_le32(DEFAULT_PITCH, pitch_value);
716
717 /* set the default scissor register to max dimensions */
718 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
719
720 /* set the drawing controls registers */
721 aty_st_le32(DP_GUI_MASTER_CNTL,
722 GMC_SRC_PITCH_OFFSET_DEFAULT |
723 GMC_DST_PITCH_OFFSET_DEFAULT |
724 GMC_SRC_CLIP_DEFAULT |
725 GMC_DST_CLIP_DEFAULT |
726 GMC_BRUSH_SOLIDCOLOR |
727 (depth_to_dst(par->crtc.depth) << 8) |
728 GMC_SRC_DSTCOLOR |
729 GMC_BYTE_ORDER_MSB_TO_LSB |
730 GMC_DP_CONVERSION_TEMP_6500 |
731 ROP3_PATCOPY |
732 GMC_DP_SRC_RECT |
733 GMC_3D_FCN_EN_CLR |
734 GMC_DST_CLR_CMP_FCN_CLEAR |
735 GMC_AUX_CLIP_CLEAR |
736 GMC_WRITE_MASK_SET);
737
738 wait_for_fifo(8, par);
739 /* clear the line drawing registers */
740 aty_st_le32(DST_BRES_ERR, 0);
741 aty_st_le32(DST_BRES_INC, 0);
742 aty_st_le32(DST_BRES_DEC, 0);
743
744 /* set brush color registers */
745 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
746 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
747
748 /* set source color registers */
749 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
750 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
751
752 /* default write mask */
753 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
754
755 /* Wait for all the writes to be completed before returning */
756 wait_for_idle(par);
757}
758
759
760/* convert depth values to their register representation */
761static u32 depth_to_dst(u32 depth)
762{
763 if (depth <= 8)
764 return DST_8BPP;
765 else if (depth <= 15)
766 return DST_15BPP;
767 else if (depth == 16)
768 return DST_16BPP;
769 else if (depth <= 24)
770 return DST_24BPP;
771 else if (depth <= 32)
772 return DST_32BPP;
773
774 return -EINVAL;
775}
776
777/*
778 * PLL informations retreival
779 */
780
781
782#ifndef __sparc__
48c68c4f
GKH		 783static void __iomem *aty128_map_ROM(const struct aty128fb_par *par,
784 struct pci_dev *dev)
1da177e4
LT		 785{
786 u16 dptr;
787 u8 rom_type;
788 void __iomem *bios;
789 size_t rom_size;
790
791 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
792 unsigned int temp;
793 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
794 temp &= 0x00ffffffu;
795 temp |= 0x04 << 24;
796 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
797 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
798
799 bios = pci_map_rom(dev, &rom_size);
800
801 if (!bios) {
802 printk(KERN_ERR "aty128fb: ROM failed to map\n");
803 return NULL;
804 }
805
806 /* Very simple test to make sure it appeared */
807 if (BIOS_IN16(0) != 0xaa55) {
3b4abffb
OH		 808 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
809 " be 0xaa55\n", BIOS_IN16(0));
1da177e4
LT		 810 goto failed;
811 }
812
813 /* Look for the PCI data to check the ROM type */
814 dptr = BIOS_IN16(0x18);
815
659f675e
EG		 816 /* Check the PCI data signature. If it's wrong, we still assume a normal
817 * x86 ROM for now, until I've verified this works everywhere.
818 * The goal here is more to phase out Open Firmware images.
1da177e4 819 *
659f675e
EG		 820 * Currently, we only look at the first PCI data, we could iteratre and
821 * deal with them all, and we should use fb_bios_start relative to start
822 * of image and not relative start of ROM, but so far, I never found a
823 * dual-image ATI card.
1da177e4
LT		 824 *
825 * typedef struct {
826 * u32 signature; + 0x00
827 * u16 vendor; + 0x04
828 * u16 device; + 0x06
829 * u16 reserved_1; + 0x08
830 * u16 dlen; + 0x0a
831 * u8 drevision; + 0x0c
832 * u8 class_hi; + 0x0d
833 * u16 class_lo; + 0x0e
834 * u16 ilen; + 0x10
835 * u16 irevision; + 0x12
836 * u8 type; + 0x14
837 * u8 indicator; + 0x15
838 * u16 reserved_2; + 0x16
839 * } pci_data_t;
840 */
841 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
842 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
843 BIOS_IN32(dptr));
844 goto anyway;
845 }
846 rom_type = BIOS_IN8(dptr + 0x14);
847 switch(rom_type) {
848 case 0:
849 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
850 break;
851 case 1:
852 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
853 goto failed;
854 case 2:
855 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
856 goto failed;
857 default:
659f675e
EG		 858 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n",
859 rom_type);
1da177e4
LT		 860 goto failed;
861 }
862 anyway:
863 return bios;
864
865 failed:
866 pci_unmap_rom(dev, bios);
867 return NULL;
868}
869
48c68c4f
GKH		 870static void aty128_get_pllinfo(struct aty128fb_par *par,
871 unsigned char __iomem *bios)
1da177e4
LT		 872{
873 unsigned int bios_hdr;
874 unsigned int bios_pll;
875
876 bios_hdr = BIOS_IN16(0x48);
877 bios_pll = BIOS_IN16(bios_hdr + 0x30);
878
879 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
880 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
881 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
882 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
883 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
884
885 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
886 par->constants.ppll_max, par->constants.ppll_min,
887 par->constants.xclk, par->constants.ref_divider,
888 par->constants.ref_clk);
889
890}
891
892#ifdef CONFIG_X86
48c68c4f 893static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par)
1da177e4
LT		 894{
895 /* I simplified this code as we used to miss the signatures in
896 * a lot of case. It's now closer to XFree, we just don't check
897 * for signatures at all... Something better will have to be done
898 * if we end up having conflicts
899 */
900 u32 segstart;
901 unsigned char __iomem *rom_base = NULL;
902
903 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
904 rom_base = ioremap(segstart, 0x10000);
905 if (rom_base == NULL)
906 return NULL;
907 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
908 break;
909 iounmap(rom_base);
910 rom_base = NULL;
911 }
912 return rom_base;
913}
914#endif
915#endif /* ndef(__sparc__) */
916
917/* fill in known card constants if pll_block is not available */
48c68c4f 918static void aty128_timings(struct aty128fb_par *par)
1da177e4
LT		 919{
920#ifdef CONFIG_PPC_OF
921 /* instead of a table lookup, assume OF has properly
922 * setup the PLL registers and use their values
923 * to set the XCLK values and reference divider values */
924
925 u32 x_mpll_ref_fb_div;
926 u32 xclk_cntl;
927 u32 Nx, M;
928 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
929#endif
930
931 if (!par->constants.ref_clk)
932 par->constants.ref_clk = 2950;
933
934#ifdef CONFIG_PPC_OF
935 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
936 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
937 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
938 M = x_mpll_ref_fb_div & 0x0000ff;
939
940 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
941 (M * PostDivSet[xclk_cntl]));
942
943 par->constants.ref_divider =
944 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
945#endif
946
947 if (!par->constants.ref_divider) {
948 par->constants.ref_divider = 0x3b;
949
950 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
951 aty_pll_writeupdate(par);
952 }
953 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
954 aty_pll_writeupdate(par);
955
956 /* from documentation */
957 if (!par->constants.ppll_min)
958 par->constants.ppll_min = 12500;
959 if (!par->constants.ppll_max)
960 par->constants.ppll_max = 25000; /* 23000 on some cards? */
961 if (!par->constants.xclk)
962 par->constants.xclk = 0x1d4d; /* same as mclk */
963
964 par->constants.fifo_width = 128;
965 par->constants.fifo_depth = 32;
966
967 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
968 case 0:
969 par->mem = &sdr_128;
970 break;
971 case 1:
972 par->mem = &sdr_sgram;
973 break;
974 case 2:
975 par->mem = &ddr_sgram;
976 break;
977 default:
978 par->mem = &sdr_sgram;
979 }
980}
981
982
983
984/*
985 * CRTC programming
986 */
987
988/* Program the CRTC registers */
989static void aty128_set_crtc(const struct aty128_crtc *crtc,
990 const struct aty128fb_par *par)
991{
992 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
993 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
994 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
995 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
996 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
997 aty_st_le32(CRTC_PITCH, crtc->pitch);
998 aty_st_le32(CRTC_OFFSET, crtc->offset);
999 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
1000 /* Disable ATOMIC updating. Is this the right place? */
1001 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
1002}
1003
1004
1005static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1006 struct aty128_crtc *crtc,
1007 const struct aty128fb_par *par)
1008{
1009 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1010 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1011 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1012 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1013 u32 depth, bytpp;
1014 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1015
1016 /* input */
1017 xres = var->xres;
1018 yres = var->yres;
1019 vxres = var->xres_virtual;
1020 vyres = var->yres_virtual;
1021 xoffset = var->xoffset;
1022 yoffset = var->yoffset;
1023 bpp = var->bits_per_pixel;
1024 left = var->left_margin;
1025 right = var->right_margin;
1026 upper = var->upper_margin;
1027 lower = var->lower_margin;
1028 hslen = var->hsync_len;
1029 vslen = var->vsync_len;
1030 sync = var->sync;
1031 vmode = var->vmode;
1032
1033 if (bpp != 16)
1034 depth = bpp;
1035 else
1036 depth = (var->green.length == 6) ? 16 : 15;
1037
1038 /* check for mode eligibility
1039 * accept only non interlaced modes */
1040 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1041 return -EINVAL;
1042
1043 /* convert (and round up) and validate */
1044 xres = (xres + 7) & ~7;
1045 xoffset = (xoffset + 7) & ~7;
1046
1047 if (vxres < xres + xoffset)
1048 vxres = xres + xoffset;
1049
1050 if (vyres < yres + yoffset)
1051 vyres = yres + yoffset;
1052
1053 /* convert depth into ATI register depth */
1054 dst = depth_to_dst(depth);
1055
1056 if (dst == -EINVAL) {
1057 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1058 return -EINVAL;
1059 }
1060
1061 /* convert register depth to bytes per pixel */
1062 bytpp = mode_bytpp[dst];
1063
1064 /* make sure there is enough video ram for the mode */
1065 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1066 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1067 return -EINVAL;
1068 }
1069
1070 h_disp = (xres >> 3) - 1;
1071 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1072
1073 v_disp = yres - 1;
1074 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1075
1076 /* check to make sure h_total and v_total are in range */
1077 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1078 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1079 return -EINVAL;
1080 }
1081
1082 h_sync_wid = (hslen + 7) >> 3;
1083 if (h_sync_wid == 0)
1084 h_sync_wid = 1;
1085 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1086 h_sync_wid = 0x3f;
1087
1088 h_sync_strt = (h_disp << 3) + right;
1089
1090 v_sync_wid = vslen;
1091 if (v_sync_wid == 0)
1092 v_sync_wid = 1;
1093 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1094 v_sync_wid = 0x1f;
1095
1096 v_sync_strt = v_disp + lower;
1097
1098 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1099 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1100
1101 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1102
1103 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1104
1105 crtc->h_total = h_total | (h_disp << 16);
1106 crtc->v_total = v_total | (v_disp << 16);
1107
1108 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1109 (h_sync_pol << 23);
1110 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1111 (v_sync_pol << 23);
1112
1113 crtc->pitch = vxres >> 3;
1114
1115 crtc->offset = 0;
1116
1117 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1118 crtc->offset_cntl = 0x00010000;
1119 else
1120 crtc->offset_cntl = 0;
1121
1122 crtc->vxres = vxres;
1123 crtc->vyres = vyres;
1124 crtc->xoffset = xoffset;
1125 crtc->yoffset = yoffset;
1126 crtc->depth = depth;
1127 crtc->bpp = bpp;
1128
1129 return 0;
1130}
1131
1132
1133static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1134{
1135
1136 /* fill in pixel info */
1137 var->red.msb_right = 0;
1138 var->green.msb_right = 0;
1139 var->blue.offset = 0;
1140 var->blue.msb_right = 0;
1141 var->transp.offset = 0;
1142 var->transp.length = 0;
1143 var->transp.msb_right = 0;
1144 switch (pix_width) {
1145 case CRTC_PIX_WIDTH_8BPP:
1146 var->bits_per_pixel = 8;
1147 var->red.offset = 0;
1148 var->red.length = 8;
1149 var->green.offset = 0;
1150 var->green.length = 8;
1151 var->blue.length = 8;
1152 break;
1153 case CRTC_PIX_WIDTH_15BPP:
1154 var->bits_per_pixel = 16;
1155 var->red.offset = 10;
1156 var->red.length = 5;
1157 var->green.offset = 5;
1158 var->green.length = 5;
1159 var->blue.length = 5;
1160 break;
1161 case CRTC_PIX_WIDTH_16BPP:
1162 var->bits_per_pixel = 16;
1163 var->red.offset = 11;
1164 var->red.length = 5;
1165 var->green.offset = 5;
1166 var->green.length = 6;
1167 var->blue.length = 5;
1168 break;
1169 case CRTC_PIX_WIDTH_24BPP:
1170 var->bits_per_pixel = 24;
1171 var->red.offset = 16;
1172 var->red.length = 8;
1173 var->green.offset = 8;
1174 var->green.length = 8;
1175 var->blue.length = 8;
1176 break;
1177 case CRTC_PIX_WIDTH_32BPP:
1178 var->bits_per_pixel = 32;
1179 var->red.offset = 16;
1180 var->red.length = 8;
1181 var->green.offset = 8;
1182 var->green.length = 8;
1183 var->blue.length = 8;
1184 var->transp.offset = 24;
1185 var->transp.length = 8;
1186 break;
1187 default:
1188 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1189 return -EINVAL;
1190 }
1191
1192 return 0;
1193}
1194
1195
1196static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1197 struct fb_var_screeninfo *var)
1198{
1199 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1200 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1201 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1202 u32 pix_width;
1203
1204 /* fun with masking */
1205 h_total = crtc->h_total & 0x1ff;
1206 h_disp = (crtc->h_total >> 16) & 0xff;
1207 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1208 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1209 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1210 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1211 v_total = crtc->v_total & 0x7ff;
1212 v_disp = (crtc->v_total >> 16) & 0x7ff;
1213 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1214 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1215 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1216 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1217 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1218
1219 /* do conversions */
1220 xres = (h_disp + 1) << 3;
1221 yres = v_disp + 1;
1222 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1223 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1224 hslen = h_sync_wid << 3;
1225 upper = v_total - v_sync_strt - v_sync_wid;
1226 lower = v_sync_strt - v_disp;
1227 vslen = v_sync_wid;
1228 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1229 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1230 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1231
1232 aty128_pix_width_to_var(pix_width, var);
1233
1234 var->xres = xres;
1235 var->yres = yres;
1236 var->xres_virtual = crtc->vxres;
1237 var->yres_virtual = crtc->vyres;
1238 var->xoffset = crtc->xoffset;
1239 var->yoffset = crtc->yoffset;
1240 var->left_margin = left;
1241 var->right_margin = right;
1242 var->upper_margin = upper;
1243 var->lower_margin = lower;
1244 var->hsync_len = hslen;
1245 var->vsync_len = vslen;
1246 var->sync = sync;
1247 var->vmode = FB_VMODE_NONINTERLACED;
1248
1249 return 0;
1250}
1251
1da177e4
LT		 1252static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1253{
1254 if (on) {
659f675e
EG		 1255 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) |
1256 CRT_CRTC_ON);
1257 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) |
1258 DAC_PALETTE2_SNOOP_EN));
1da177e4 1259 } else
659f675e
EG		 1260 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) &
1261 ~CRT_CRTC_ON);
1da177e4
LT		 1262}
1263
1264static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1265{
1266 u32 reg;
5474c120
MH		 1267#ifdef CONFIG_FB_ATY128_BACKLIGHT
1268 struct fb_info *info = pci_get_drvdata(par->pdev);
1269#endif
1da177e4
LT		 1270
1271 if (on) {
1272 reg = aty_ld_le32(LVDS_GEN_CNTL);
1273 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1274 reg &= ~LVDS_DISPLAY_DIS;
1275 aty_st_le32(LVDS_GEN_CNTL, reg);
5474c120 1276#ifdef CONFIG_FB_ATY128_BACKLIGHT
e01af038 1277 aty128_bl_set_power(info, FB_BLANK_UNBLANK);
1da177e4
LT		 1278#endif
1279 } else {
5474c120 1280#ifdef CONFIG_FB_ATY128_BACKLIGHT
e01af038 1281 aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
1da177e4
LT		 1282#endif
1283 reg = aty_ld_le32(LVDS_GEN_CNTL);
1284 reg |= LVDS_DISPLAY_DIS;
1285 aty_st_le32(LVDS_GEN_CNTL, reg);
1286 mdelay(100);
1287 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1288 aty_st_le32(LVDS_GEN_CNTL, reg);
1289 }
1290}
1da177e4 1291
659f675e
EG		 1292static void aty128_set_pll(struct aty128_pll *pll,
1293 const struct aty128fb_par *par)
1da177e4
LT		 1294{
1295 u32 div3;
1296
1297 unsigned char post_conv[] = /* register values for post dividers */
1298 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1299
1300 /* select PPLL_DIV_3 */
1301 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1302
1303 /* reset PLL */
1304 aty_st_pll(PPLL_CNTL,
1305 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1306
1307 /* write the reference divider */
1308 aty_pll_wait_readupdate(par);
1309 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1310 aty_pll_writeupdate(par);
1311
1312 div3 = aty_ld_pll(PPLL_DIV_3);
1313 div3 &= ~PPLL_FB3_DIV_MASK;
1314 div3 |= pll->feedback_divider;
1315 div3 &= ~PPLL_POST3_DIV_MASK;
1316 div3 |= post_conv[pll->post_divider] << 16;
1317
1318 /* write feedback and post dividers */
1319 aty_pll_wait_readupdate(par);
1320 aty_st_pll(PPLL_DIV_3, div3);
1321 aty_pll_writeupdate(par);
1322
1323 aty_pll_wait_readupdate(par);
1324 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1325 aty_pll_writeupdate(par);
1326
1327 /* clear the reset, just in case */
1328 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1329}
1330
1331
1332static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1333 const struct aty128fb_par *par)
1334{
1335 const struct aty128_constants c = par->constants;
1336 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1337 u32 output_freq;
1338 u32 vclk; /* in .01 MHz */
8e650987 1339 int i = 0;
1da177e4
LT		 1340 u32 n, d;
1341
1342 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1343
1344 /* adjust pixel clock if necessary */
1345 if (vclk > c.ppll_max)
1346 vclk = c.ppll_max;
1347 if (vclk * 12 < c.ppll_min)
1348 vclk = c.ppll_min/12;
1349
1350 /* now, find an acceptable divider */
816664f8 1351 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) {
1da177e4 1352 output_freq = post_dividers[i] * vclk;
8e650987
AD		 1353 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1354 pll->post_divider = post_dividers[i];
1da177e4 1355 break;
8e650987 1356 }
1da177e4
LT		 1357 }
1358
816664f8 1359 if (i == ARRAY_SIZE(post_dividers))
fd717689
JG		 1360 return -EINVAL;
1361
1da177e4
LT		 1362 /* calculate feedback divider */
1363 n = c.ref_divider * output_freq;
1364 d = c.ref_clk;
1365
1da177e4
LT		 1366 pll->feedback_divider = round_div(n, d);
1367 pll->vclk = vclk;
1368
1369 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1370 "vclk_per: %d\n", pll->post_divider,
1371 pll->feedback_divider, vclk, output_freq,
1372 c.ref_divider, period_in_ps);
1373
1374 return 0;
1375}
1376
1377
659f675e
EG		 1378static int aty128_pll_to_var(const struct aty128_pll *pll,
1379 struct fb_var_screeninfo *var)
1da177e4
LT		 1380{
1381 var->pixclock = 100000000 / pll->vclk;
1382
1383 return 0;
1384}
1385
1386
1387static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1388 const struct aty128fb_par *par)
1389{
1390 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1391 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1392}
1393
1394
1395static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1396 const struct aty128_pll *pll,
1397 u32 depth,
1398 const struct aty128fb_par *par)
1399{
1400 const struct aty128_meminfo *m = par->mem;
1401 u32 xclk = par->constants.xclk;
1402 u32 fifo_width = par->constants.fifo_width;
1403 u32 fifo_depth = par->constants.fifo_depth;
1404 s32 x, b, p, ron, roff;
1405 u32 n, d, bpp;
1406
1407 /* round up to multiple of 8 */
1408 bpp = (depth+7) & ~7;
1409
1410 n = xclk * fifo_width;
1411 d = pll->vclk * bpp;
1412 x = round_div(n, d);
1413
1414 ron = 4 * m->MB +
1415 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1416 2 * m->Trp +
1417 m->Twr +
1418 m->CL +
1419 m->Tr2w +
1420 x;
1421
1422 DBG("x %x\n", x);
1423
1424 b = 0;
1425 while (x) {
1426 x >>= 1;
1427 b++;
1428 }
1429 p = b + 1;
1430
1431 ron <<= (11 - p);
1432
1433 n <<= (11 - p);
1434 x = round_div(n, d);
1435 roff = x * (fifo_depth - 4);
1436
1437 if ((ron + m->Rloop) >= roff) {
1438 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1439 return -EINVAL;
1440 }
1441
1442 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1443 p, m->Rloop, x, ron, roff);
1444
1445 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1446 dsp->dda_on_off = ron << 16 | roff;
1447
1448 return 0;
1449}
1450
1451
1452/*
1453 * This actually sets the video mode.
1454 */
1455static int aty128fb_set_par(struct fb_info *info)
1456{
1457 struct aty128fb_par *par = info->par;
1458 u32 config;
1459 int err;
1460
1461 if ((err = aty128_decode_var(&info->var, par)) != 0)
1462 return err;
1463
1464 if (par->blitter_may_be_busy)
1465 wait_for_idle(par);
1466
1467 /* clear all registers that may interfere with mode setting */
1468 aty_st_le32(OVR_CLR, 0);
1469 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1470 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1471 aty_st_le32(OV0_SCALE_CNTL, 0);
1472 aty_st_le32(MPP_TB_CONFIG, 0);
1473 aty_st_le32(MPP_GP_CONFIG, 0);
1474 aty_st_le32(SUBPIC_CNTL, 0);
1475 aty_st_le32(VIPH_CONTROL, 0);
1476 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1477 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1478 aty_st_le32(CAP0_TRIG_CNTL, 0);
1479 aty_st_le32(CAP1_TRIG_CNTL, 0);
1480
1481 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1482
1483 aty128_set_crtc(&par->crtc, par);
1484 aty128_set_pll(&par->pll, par);
1485 aty128_set_fifo(&par->fifo_reg, par);
1486
fe86175b 1487 config = aty_ld_le32(CNFG_CNTL) & ~3;
1da177e4
LT		 1488
1489#if defined(__BIG_ENDIAN)
1490 if (par->crtc.bpp == 32)
1491 config |= 2; /* make aperture do 32 bit swapping */
1492 else if (par->crtc.bpp == 16)
1493 config |= 1; /* make aperture do 16 bit swapping */
1494#endif
1495
fe86175b 1496 aty_st_le32(CNFG_CNTL, config);
1da177e4
LT		 1497 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1498
1499 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1500 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1501 : FB_VISUAL_DIRECTCOLOR;
1502
1da177e4
LT		 1503 if (par->chip_gen == rage_M3) {
1504 aty128_set_crt_enable(par, par->crt_on);
1505 aty128_set_lcd_enable(par, par->lcd_on);
1506 }
1da177e4
LT		 1507 if (par->accel_flags & FB_ACCELF_TEXT)
1508 aty128_init_engine(par);
1509
1510#ifdef CONFIG_BOOTX_TEXT
1511 btext_update_display(info->fix.smem_start,
1512 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1513 ((par->crtc.v_total>>16) & 0x7ff)+1,
1514 par->crtc.bpp,
1515 par->crtc.vxres*par->crtc.bpp/8);
1516#endif /* CONFIG_BOOTX_TEXT */
1517
1518 return 0;
1519}
1520
1521/*
1522 * encode/decode the User Defined Part of the Display
1523 */
1524
659f675e
EG		 1525static int aty128_decode_var(struct fb_var_screeninfo *var,
1526 struct aty128fb_par *par)
1da177e4
LT		 1527{
1528 int err;
1529 struct aty128_crtc crtc;
1530 struct aty128_pll pll;
1531 struct aty128_ddafifo fifo_reg;
1532
1533 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1534 return err;
1535
1536 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1537 return err;
1538
1539 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1540 return err;
1541
1542 par->crtc = crtc;
1543 par->pll = pll;
1544 par->fifo_reg = fifo_reg;
1545 par->accel_flags = var->accel_flags;
1546
1547 return 0;
1548}
1549
1550
1551static int aty128_encode_var(struct fb_var_screeninfo *var,
1552 const struct aty128fb_par *par)
1553{
1554 int err;
1555
1556 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1557 return err;
1558
1559 if ((err = aty128_pll_to_var(&par->pll, var)))
1560 return err;
1561
1562 var->nonstd = 0;
1563 var->activate = 0;
1564
1565 var->height = -1;
1566 var->width = -1;
1567 var->accel_flags = par->accel_flags;
1568
1569 return 0;
1570}
1571
1572
659f675e
EG		 1573static int aty128fb_check_var(struct fb_var_screeninfo *var,
1574 struct fb_info *info)
1da177e4
LT		 1575{
1576 struct aty128fb_par par;
1577 int err;
1578
1579 par = *(struct aty128fb_par *)info->par;
1580 if ((err = aty128_decode_var(var, &par)) != 0)
1581 return err;
1582 aty128_encode_var(var, &par);
1583 return 0;
1584}
1585
1586
1587/*
1588 * Pan or Wrap the Display
1589 */
659f675e
EG		 1590static int aty128fb_pan_display(struct fb_var_screeninfo *var,
1591 struct fb_info *fb)
1da177e4
LT		 1592{
1593 struct aty128fb_par *par = fb->par;
1594 u32 xoffset, yoffset;
1595 u32 offset;
1596 u32 xres, yres;
1597
1598 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1599 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1600
1601 xoffset = (var->xoffset +7) & ~7;
1602 yoffset = var->yoffset;
1603
1604 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1605 return -EINVAL;
1606
1607 par->crtc.xoffset = xoffset;
1608 par->crtc.yoffset = yoffset;
1609
659f675e
EG		 1610 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3))
1611 & ~7;
1da177e4
LT		 1612
1613 if (par->crtc.bpp == 24)
1614 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1615
1616 aty_st_le32(CRTC_OFFSET, offset);
1617
1618 return 0;
1619}
1620
1621
1622/*
1623 * Helper function to store a single palette register
1624 */
1625static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1626 struct aty128fb_par *par)
1627{
1628 if (par->chip_gen == rage_M3) {
1629#if 0
1630 /* Note: For now, on M3, we set palette on both heads, which may
1631 * be useless. Can someone with a M3 check this ?
1632 *
1633 * This code would still be useful if using the second CRTC to
1634 * do mirroring
1635 */
1636
659f675e
EG		 1637 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) |
1638 DAC_PALETTE_ACCESS_CNTL);
1da177e4
LT		 1639 aty_st_8(PALETTE_INDEX, regno);
1640 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1641#endif
659f675e
EG		 1642 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &
1643 ~DAC_PALETTE_ACCESS_CNTL);
1da177e4
LT		 1644 }
1645
1646 aty_st_8(PALETTE_INDEX, regno);
1647 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1648}
1649
1650static int aty128fb_sync(struct fb_info *info)
1651{
1652 struct aty128fb_par *par = info->par;
1653
1654 if (par->blitter_may_be_busy)
1655 wait_for_idle(par);
1656 return 0;
1657}
1658
1659#ifndef MODULE
48c68c4f 1660static int aty128fb_setup(char *options)
1da177e4
LT		 1661{
1662 char *this_opt;
1663
1664 if (!options || !*options)
1665 return 0;
1666
1667 while ((this_opt = strsep(&options, ",")) != NULL) {
1da177e4
LT		 1668 if (!strncmp(this_opt, "lcd:", 4)) {
1669 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1670 continue;
1671 } else if (!strncmp(this_opt, "crt:", 4)) {
1672 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1673 continue;
202d4e60
RP		 1674 } else if (!strncmp(this_opt, "backlight:", 10)) {
1675 backlight = simple_strtoul(this_opt+10, NULL, 0);
1676 continue;
1da177e4 1677 }
1da177e4
LT		 1678#ifdef CONFIG_MTRR
1679 if(!strncmp(this_opt, "nomtrr", 6)) {
1680 mtrr = 0;
1681 continue;
1682 }
1683#endif
1684#ifdef CONFIG_PPC_PMAC
1685 /* vmode and cmode deprecated */
1686 if (!strncmp(this_opt, "vmode:", 6)) {
1687 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1688 if (vmode > 0 && vmode <= VMODE_MAX)
1689 default_vmode = vmode;
1690 continue;
1691 } else if (!strncmp(this_opt, "cmode:", 6)) {
1692 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1693 switch (cmode) {
1694 case 0:
1695 case 8:
1696 default_cmode = CMODE_8;
1697 break;
1698 case 15:
1699 case 16:
1700 default_cmode = CMODE_16;
1701 break;
1702 case 24:
1703 case 32:
1704 default_cmode = CMODE_32;
1705 break;
1706 }
1707 continue;
1708 }
1709#endif /* CONFIG_PPC_PMAC */
1710 mode_option = this_opt;
1711 }
1712 return 0;
1713}
1714#endif /* MODULE */
1715
5474c120
MH		 1716/* Backlight */
1717#ifdef CONFIG_FB_ATY128_BACKLIGHT
1718#define MAX_LEVEL 0xFF
1719
5474c120
MH		 1720static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1721 int level)
1722{
1723 struct fb_info *info = pci_get_drvdata(par->pdev);
1724 int atylevel;
1725
1726 /* Get and convert the value */
37ce69a5 1727 /* No locking of bl_curve since we read a single value */
5474c120
MH		 1728 atylevel = MAX_LEVEL -
1729 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
5474c120
MH		 1730
1731 if (atylevel < 0)
1732 atylevel = 0;
1733 else if (atylevel > MAX_LEVEL)
1734 atylevel = MAX_LEVEL;
1735
1736 return atylevel;
1737}
1738
1739/* We turn off the LCD completely instead of just dimming the backlight.
1740 * This provides greater power saving and the display is useless without
1741 * backlight anyway
1742 */
1743#define BACKLIGHT_LVDS_OFF
1744/* That one prevents proper CRT output with LCD off */
1745#undef BACKLIGHT_DAC_OFF
1746
37ce69a5 1747static int aty128_bl_update_status(struct backlight_device *bd)
5474c120 1748{
655bfd7a 1749 struct aty128fb_par *par = bl_get_data(bd);
5474c120
MH		 1750 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1751 int level;
1752
599a52d1
RP		 1753 if (bd->props.power != FB_BLANK_UNBLANK ||
1754 bd->props.fb_blank != FB_BLANK_UNBLANK ||
5474c120
MH		 1755 !par->lcd_on)
1756 level = 0;
1757 else
599a52d1 1758 level = bd->props.brightness;
5474c120
MH		 1759
1760 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
1761 if (level > 0) {
1762 reg |= LVDS_DIGION;
1763 if (!(reg & LVDS_ON)) {
1764 reg &= ~LVDS_BLON;
1765 aty_st_le32(LVDS_GEN_CNTL, reg);
1766 aty_ld_le32(LVDS_GEN_CNTL);
1767 mdelay(10);
1768 reg |= LVDS_BLON;
1769 aty_st_le32(LVDS_GEN_CNTL, reg);
1770 }
1771 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
659f675e
EG		 1772 reg |= (aty128_bl_get_level_brightness(par, level) <<
1773 LVDS_BL_MOD_LEVEL_SHIFT);
5474c120
MH		 1774#ifdef BACKLIGHT_LVDS_OFF
1775 reg |= LVDS_ON | LVDS_EN;
1776 reg &= ~LVDS_DISPLAY_DIS;
1777#endif
1778 aty_st_le32(LVDS_GEN_CNTL, reg);
1779#ifdef BACKLIGHT_DAC_OFF
1780 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1781#endif
1782 } else {
1783 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
659f675e
EG		 1784 reg |= (aty128_bl_get_level_brightness(par, 0) <<
1785 LVDS_BL_MOD_LEVEL_SHIFT);
5474c120
MH		 1786#ifdef BACKLIGHT_LVDS_OFF
1787 reg |= LVDS_DISPLAY_DIS;
1788 aty_st_le32(LVDS_GEN_CNTL, reg);
1789 aty_ld_le32(LVDS_GEN_CNTL);
1790 udelay(10);
1791 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
1792#endif
1793 aty_st_le32(LVDS_GEN_CNTL, reg);
1794#ifdef BACKLIGHT_DAC_OFF
1795 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1796#endif
1797 }
1798
1799 return 0;
1800}
1801
1802static int aty128_bl_get_brightness(struct backlight_device *bd)
1803{
599a52d1 1804 return bd->props.brightness;
5474c120
MH		 1805}
1806
acc2472e 1807static const struct backlight_ops aty128_bl_data = {
5474c120
MH		 1808 .get_brightness = aty128_bl_get_brightness,
1809 .update_status = aty128_bl_update_status,
5474c120
MH		 1810};
1811
e01af038
MH		 1812static void aty128_bl_set_power(struct fb_info *info, int power)
1813{
a9303638 1814 if (info->bl_dev) {
599a52d1 1815 info->bl_dev->props.power = power;
37ce69a5 1816 backlight_update_status(info->bl_dev);
a9303638 1817 }
e01af038
MH		 1818}
1819
5474c120
MH		 1820static void aty128_bl_init(struct aty128fb_par *par)
1821{
a19a6ee6 1822 struct backlight_properties props;
5474c120
MH		 1823 struct fb_info *info = pci_get_drvdata(par->pdev);
1824 struct backlight_device *bd;
1825 char name[12];
1826
1827 /* Could be extended to Rage128Pro LVDS output too */
1828 if (par->chip_gen != rage_M3)
1829 return;
1830
1831#ifdef CONFIG_PMAC_BACKLIGHT
1832 if (!pmac_has_backlight_type("ati"))
1833 return;
1834#endif
1835
1836 snprintf(name, sizeof(name), "aty128bl%d", info->node);
1837
a19a6ee6 1838 memset(&props, 0, sizeof(struct backlight_properties));
bb7ca747 1839 props.type = BACKLIGHT_RAW;
a19a6ee6
MG		 1840 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
1841 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data,
1842 &props);
5474c120
MH		 1843 if (IS_ERR(bd)) {
1844 info->bl_dev = NULL;
98a3c781 1845 printk(KERN_WARNING "aty128: Backlight registration failed\n");
5474c120
MH		 1846 goto error;
1847 }
1848
5474c120
MH		 1849 info->bl_dev = bd;
1850 fb_bl_default_curve(info, 0,
1851 63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
1852 219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
5474c120 1853
599a52d1
RP		 1854 bd->props.brightness = bd->props.max_brightness;
1855 bd->props.power = FB_BLANK_UNBLANK;
28ee086d 1856 backlight_update_status(bd);
5474c120 1857
5474c120
MH		 1858 printk("aty128: Backlight initialized (%s)\n", name);
1859
1860 return;
1861
1862error:
1863 return;
1864}
1865
37ce69a5 1866static void aty128_bl_exit(struct backlight_device *bd)
5474c120 1867{
321709c5
RP		 1868 backlight_device_unregister(bd);
1869 printk("aty128: Backlight unloaded\n");
5474c120
MH		 1870}
1871#endif /* CONFIG_FB_ATY128_BACKLIGHT */
1da177e4
LT		 1872
1873/*
1874 * Initialisation
1875 */
1876
d801cec7 1877#ifdef CONFIG_PPC_PMAC__disabled
1da177e4
LT		 1878static void aty128_early_resume(void *data)
1879{
1880 struct aty128fb_par *par = data;
1881
ac751efa 1882 if (!console_trylock())
1da177e4 1883 return;
d801cec7 1884 pci_restore_state(par->pdev);
1da177e4 1885 aty128_do_resume(par->pdev);
ac751efa 1886 console_unlock();
1da177e4
LT		 1887}
1888#endif /* CONFIG_PPC_PMAC */
1889
48c68c4f 1890static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1891{
1892 struct fb_info *info = pci_get_drvdata(pdev);
1893 struct aty128fb_par *par = info->par;
1894 struct fb_var_screeninfo var;
ca52a498 1895 char video_card[50];
1da177e4
LT		 1896 u8 chip_rev;
1897 u32 dac;
1898
1da177e4 1899 /* Get the chip revision */
fe86175b 1900 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
1da177e4
LT		 1901
1902 strcpy(video_card, "Rage128 XX ");
1903 video_card[8] = ent->device >> 8;
1904 video_card[9] = ent->device & 0xFF;
d1ae418e 1905
1da177e4 1906 /* range check to make sure */
d1ae418e 1907 if (ent->driver_data < ARRAY_SIZE(r128_family))
659f675e
EG		 1908 strlcat(video_card, r128_family[ent->driver_data],
1909 sizeof(video_card));
1da177e4
LT		 1910
1911 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1912
1913 if (par->vram_size % (1024 * 1024) == 0)
1914 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1915 else
1916 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1917
1918 par->chip_gen = ent->driver_data;
1919
1920 /* fill in info */
1921 info->fbops = &aty128fb_ops;
1922 info->flags = FBINFO_FLAG_DEFAULT;
1923
1da177e4
LT		 1924 par->lcd_on = default_lcd_on;
1925 par->crt_on = default_crt_on;
1da177e4
LT		 1926
1927 var = default_var;
1928#ifdef CONFIG_PPC_PMAC
e8222502 1929 if (machine_is(powermac)) {
1da177e4
LT		 1930 /* Indicate sleep capability */
1931 if (par->chip_gen == rage_M3) {
1932 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
659f675e
EG		 1933#if 0 /* Disable the early video resume hack for now as it's causing problems,
1934 * among others we now rely on the PCI core restoring the config space
1935 * for us, which isn't the case with that hack, and that code path causes
1936 * various things to be called with interrupts off while they shouldn't.
1937 * I'm leaving the code in as it can be useful for debugging purposes
d801cec7 1938 */
1da177e4 1939 pmac_set_early_video_resume(aty128_early_resume, par);
d801cec7 1940#endif
1da177e4
LT		 1941 }
1942
1943 /* Find default mode */
1944 if (mode_option) {
1945 if (!mac_find_mode(&var, info, mode_option, 8))
1946 var = default_var;
1947 } else {
1948 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1949 default_vmode = VMODE_1024_768_60;
1950
1951 /* iMacs need that resolution
1952 * PowerMac2,1 first r128 iMacs
1953 * PowerMac2,2 summer 2000 iMacs
1954 * PowerMac4,1 january 2001 iMacs "flower power"
1955 */
71a157e8
GL		 1956 if (of_machine_is_compatible("PowerMac2,1") ||
1957 of_machine_is_compatible("PowerMac2,2") ||
1958 of_machine_is_compatible("PowerMac4,1"))
1da177e4
LT		 1959 default_vmode = VMODE_1024_768_75;
1960
1961 /* iBook SE */
71a157e8 1962 if (of_machine_is_compatible("PowerBook2,2"))
1da177e4
LT		 1963 default_vmode = VMODE_800_600_60;
1964
1965 /* PowerBook Firewire (Pismo), iBook Dual USB */
71a157e8
GL		 1966 if (of_machine_is_compatible("PowerBook3,1") ||
1967 of_machine_is_compatible("PowerBook4,1"))
1da177e4
LT		 1968 default_vmode = VMODE_1024_768_60;
1969
1970 /* PowerBook Titanium */
71a157e8 1971 if (of_machine_is_compatible("PowerBook3,2"))
1da177e4
LT		 1972 default_vmode = VMODE_1152_768_60;
1973
1974 if (default_cmode > 16)
659f675e 1975 default_cmode = CMODE_32;
1da177e4 1976 else if (default_cmode > 8)
659f675e 1977 default_cmode = CMODE_16;
1da177e4 1978 else
659f675e 1979 default_cmode = CMODE_8;
1da177e4
LT		 1980
1981 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1982 var = default_var;
1983 }
1984 } else
1985#endif /* CONFIG_PPC_PMAC */
1986 {
1987 if (mode_option)
1988 if (fb_find_mode(&var, info, mode_option, NULL,
1989 0, &defaultmode, 8) == 0)
1990 var = default_var;
1991 }
1992
1993 var.accel_flags &= ~FB_ACCELF_TEXT;
1994// var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
1995
1996 if (aty128fb_check_var(&var, info)) {
1997 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1998 return 0;
1999 }
2000
2001 /* setup the DAC the way we like it */
2002 dac = aty_ld_le32(DAC_CNTL);
2003 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
2004 dac |= DAC_MASK;
2005 if (par->chip_gen == rage_M3)
2006 dac |= DAC_PALETTE2_SNOOP_EN;
2007 aty_st_le32(DAC_CNTL, dac);
2008
2009 /* turn off bus mastering, just in case */
2010 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
2011
2012 info->var = var;
2013 fb_alloc_cmap(&info->cmap, 256, 0);
2014
2015 var.activate = FB_ACTIVATE_NOW;
2016
2017 aty128_init_engine(par);
2018
1da177e4
LT		 2019 par->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
2020 par->pdev = pdev;
2021 par->asleep = 0;
2022 par->lock_blank = 0;
5474c120
MH		 2023
2024#ifdef CONFIG_FB_ATY128_BACKLIGHT
202d4e60
RP		 2025 if (backlight)
2026 aty128_bl_init(par);
5474c120
MH		 2027#endif
2028
c3760ae1
OH		 2029 if (register_framebuffer(info) < 0)
2030 return 0;
2031
1da177e4
LT		 2032 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
2033 info->node, info->fix.id, video_card);
2034
2035 return 1; /* success! */
2036}
2037
2038#ifdef CONFIG_PCI
2039/* register a card ++ajoshi */
48c68c4f 2040static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 2041{
2042 unsigned long fb_addr, reg_addr;
2043 struct aty128fb_par *par;
2044 struct fb_info *info;
2045 int err;
2046#ifndef __sparc__
2047 void __iomem *bios = NULL;
2048#endif
2049
2050 /* Enable device in PCI config */
2051 if ((err = pci_enable_device(pdev))) {
2052 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2053 err);
2054 return -ENODEV;
2055 }
2056
2057 fb_addr = pci_resource_start(pdev, 0);
2058 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2059 "aty128fb FB")) {
2060 printk(KERN_ERR "aty128fb: cannot reserve frame "
2061 "buffer memory\n");
2062 return -ENODEV;
2063 }
2064
2065 reg_addr = pci_resource_start(pdev, 2);
2066 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2067 "aty128fb MMIO")) {
2068 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2069 goto err_free_fb;
2070 }
2071
2072 /* We have the resources. Now virtualize them */
2073 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
2074 if (info == NULL) {
2075 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
2076 goto err_free_mmio;
2077 }
2078 par = info->par;
2079
2080 info->pseudo_palette = par->pseudo_palette;
1da177e4
LT		 2081
2082 /* Virtualize mmio region */
2083 info->fix.mmio_start = reg_addr;
3c36aa5c 2084 par->regbase = pci_ioremap_bar(pdev, 2);
1da177e4
LT		 2085 if (!par->regbase)
2086 goto err_free_info;
2087
2088 /* Grab memory size from the card */
2089 // How does this relate to the resource length from the PCI hardware?
fe86175b 2090 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
1da177e4
LT		 2091
2092 /* Virtualize the framebuffer */
2093 info->screen_base = ioremap(fb_addr, par->vram_size);
2094 if (!info->screen_base)
2095 goto err_unmap_out;
2096
2097 /* Set up info->fix */
2098 info->fix = aty128fb_fix;
2099 info->fix.smem_start = fb_addr;
2100 info->fix.smem_len = par->vram_size;
2101 info->fix.mmio_start = reg_addr;
2102
2103 /* If we can't test scratch registers, something is seriously wrong */
2104 if (!register_test(par)) {
2105 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2106 goto err_out;
2107 }
2108
2109#ifndef __sparc__
2110 bios = aty128_map_ROM(par, pdev);
2111#ifdef CONFIG_X86
2112 if (bios == NULL)
2113 bios = aty128_find_mem_vbios(par);
2114#endif
2115 if (bios == NULL)
2116 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
2117 else {
2118 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
2119 aty128_get_pllinfo(par, bios);
2120 pci_unmap_rom(pdev, bios);
2121 }
2122#endif /* __sparc__ */
2123
2124 aty128_timings(par);
2125 pci_set_drvdata(pdev, info);
2126
2127 if (!aty128_init(pdev, ent))
2128 goto err_out;
2129
2130#ifdef CONFIG_MTRR
2131 if (mtrr) {
2132 par->mtrr.vram = mtrr_add(info->fix.smem_start,
2133 par->vram_size, MTRR_TYPE_WRCOMB, 1);
2134 par->mtrr.vram_valid = 1;
2135 /* let there be speed */
2136 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
2137 }
2138#endif /* CONFIG_MTRR */
2139 return 0;
2140
2141err_out:
2142 iounmap(info->screen_base);
2143err_unmap_out:
2144 iounmap(par->regbase);
2145err_free_info:
2146 framebuffer_release(info);
2147err_free_mmio:
2148 release_mem_region(pci_resource_start(pdev, 2),
2149 pci_resource_len(pdev, 2));
2150err_free_fb:
2151 release_mem_region(pci_resource_start(pdev, 0),
2152 pci_resource_len(pdev, 0));
2153 return -ENODEV;
2154}
2155
48c68c4f 2156static void aty128_remove(struct pci_dev *pdev)
1da177e4
LT		 2157{
2158 struct fb_info *info = pci_get_drvdata(pdev);
2159 struct aty128fb_par *par;
2160
2161 if (!info)
2162 return;
2163
2164 par = info->par;
2165
37ce69a5
RP		 2166 unregister_framebuffer(info);
2167
5474c120 2168#ifdef CONFIG_FB_ATY128_BACKLIGHT
37ce69a5 2169 aty128_bl_exit(info->bl_dev);
5474c120
MH		 2170#endif
2171
1da177e4
LT		 2172#ifdef CONFIG_MTRR
2173 if (par->mtrr.vram_valid)
2174 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2175 par->vram_size);
2176#endif /* CONFIG_MTRR */
2177 iounmap(par->regbase);
2178 iounmap(info->screen_base);
2179
2180 release_mem_region(pci_resource_start(pdev, 0),
2181 pci_resource_len(pdev, 0));
2182 release_mem_region(pci_resource_start(pdev, 2),
2183 pci_resource_len(pdev, 2));
2184 framebuffer_release(info);
2185}
2186#endif /* CONFIG_PCI */
2187
2188
2189
2190 /*
2191 * Blank the display.
2192 */
2193static int aty128fb_blank(int blank, struct fb_info *fb)
2194{
2195 struct aty128fb_par *par = fb->par;
125e1137 2196 u8 state;
1da177e4
LT		 2197
2198 if (par->lock_blank || par->asleep)
2199 return 0;
2200
125e1137
WF		 2201 switch (blank) {
2202 case FB_BLANK_NORMAL:
2203 state = 4;
2204 break;
2205 case FB_BLANK_VSYNC_SUSPEND:
2206 state = 6;
2207 break;
2208 case FB_BLANK_HSYNC_SUSPEND:
2209 state = 5;
2210 break;
2211 case FB_BLANK_POWERDOWN:
2212 state = 7;
2213 break;
2214 case FB_BLANK_UNBLANK:
2215 default:
2216 state = 0;
2217 break;
2218 }
1da177e4
LT		 2219 aty_st_8(CRTC_EXT_CNTL+1, state);
2220
1da177e4
LT		 2221 if (par->chip_gen == rage_M3) {
2222 aty128_set_crt_enable(par, par->crt_on && !blank);
2223 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2224 }
e01af038 2225
1da177e4
LT		 2226 return 0;
2227}
2228
2229/*
2230 * Set a single color register. The values supplied are already
2231 * rounded down to the hardware's capabilities (according to the
2232 * entries in the var structure). Return != 0 for invalid regno.
2233 */
2234static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2235 u_int transp, struct fb_info *info)
2236{
2237 struct aty128fb_par *par = info->par;
2238
2239 if (regno > 255
2240 || (par->crtc.depth == 16 && regno > 63)
2241 || (par->crtc.depth == 15 && regno > 31))
2242 return 1;
2243
2244 red >>= 8;
2245 green >>= 8;
2246 blue >>= 8;
2247
2248 if (regno < 16) {
2249 int i;
2250 u32 *pal = info->pseudo_palette;
2251
2252 switch (par->crtc.depth) {
2253 case 15:
2254 pal[regno] = (regno << 10) | (regno << 5) | regno;
2255 break;
2256 case 16:
2257 pal[regno] = (regno << 11) | (regno << 6) | regno;
2258 break;
2259 case 24:
2260 pal[regno] = (regno << 16) | (regno << 8) | regno;
2261 break;
2262 case 32:
2263 i = (regno << 8) | regno;
2264 pal[regno] = (i << 16) | i;
2265 break;
2266 }
2267 }
2268
2269 if (par->crtc.depth == 16 && regno > 0) {
2270 /*
2271 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2272 * have 32 slots for R and B values but 64 slots for G values.
2273 * Thus the R and B values go in one slot but the G value
2274 * goes in a different slot, and we have to avoid disturbing
2275 * the other fields in the slots we touch.
2276 */
2277 par->green[regno] = green;
2278 if (regno < 32) {
2279 par->red[regno] = red;
2280 par->blue[regno] = blue;
2281 aty128_st_pal(regno * 8, red, par->green[regno*2],
2282 blue, par);
2283 }
2284 red = par->red[regno/2];
2285 blue = par->blue[regno/2];
2286 regno <<= 2;
2287 } else if (par->crtc.bpp == 16)
2288 regno <<= 3;
2289 aty128_st_pal(regno, red, green, blue, par);
2290
2291 return 0;
2292}
2293
2294#define ATY_MIRROR_LCD_ON 0x00000001
2295#define ATY_MIRROR_CRT_ON 0x00000002
2296
2297/* out param: u32* backlight value: 0 to 15 */
2298#define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2299/* in param: u32* backlight value: 0 to 15 */
2300#define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2301
67a6680d 2302static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1da177e4 2303{
1da177e4
LT		 2304 struct aty128fb_par *par = info->par;
2305 u32 value;
2306 int rc;
2307
2308 switch (cmd) {
2309 case FBIO_ATY128_SET_MIRROR:
2310 if (par->chip_gen != rage_M3)
2311 return -EINVAL;
2312 rc = get_user(value, (__u32 __user *)arg);
2313 if (rc)
2314 return rc;
2315 par->lcd_on = (value & 0x01) != 0;
2316 par->crt_on = (value & 0x02) != 0;
2317 if (!par->crt_on && !par->lcd_on)
2318 par->lcd_on = 1;
2319 aty128_set_crt_enable(par, par->crt_on);
2320 aty128_set_lcd_enable(par, par->lcd_on);
2321 return 0;
2322 case FBIO_ATY128_GET_MIRROR:
2323 if (par->chip_gen != rage_M3)
2324 return -EINVAL;
2325 value = (par->crt_on << 1) | par->lcd_on;
2326 return put_user(value, (__u32 __user *)arg);
2327 }
1da177e4
LT		 2328 return -EINVAL;
2329}
2330
1da177e4
LT		 2331#if 0
2332 /*
2333 * Accelerated functions
2334 */
2335
2336static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2337 u_int width, u_int height,
2338 struct fb_info_aty128 *par)
2339{
659f675e
EG		 2340 u32 save_dp_datatype, save_dp_cntl, dstval;
2341
2342 if (!width || !height)
2343 return;
2344
2345 dstval = depth_to_dst(par->current_par.crtc.depth);
2346 if (dstval == DST_24BPP) {
2347 srcx *= 3;
2348 dstx *= 3;
2349 width *= 3;
2350 } else if (dstval == -EINVAL) {
2351 printk("aty128fb: invalid depth or RGBA\n");
2352 return;
2353 }
2354
2355 wait_for_fifo(2, par);
2356 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2357 save_dp_cntl = aty_ld_le32(DP_CNTL);
2358
2359 wait_for_fifo(6, par);
2360 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2361 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2362 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2363 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2364
2365 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2366 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2367
2368 par->blitter_may_be_busy = 1;
2369
2370 wait_for_fifo(2, par);
2371 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2372 aty_st_le32(DP_CNTL, save_dp_cntl);
1da177e4
LT		 2373}
2374
2375
2376 /*
2377 * Text mode accelerated functions
2378 */
2379
659f675e
EG		 2380static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy,
2381 int dx, int height, int width)
1da177e4 2382{
659f675e
EG		 2383 sx *= fontwidth(p);
2384 sy *= fontheight(p);
2385 dx *= fontwidth(p);
2386 dy *= fontheight(p);
2387 width *= fontwidth(p);
2388 height *= fontheight(p);
2389
2390 aty128_rectcopy(sx, sy, dx, dy, width, height,
1da177e4
LT		 2391 (struct fb_info_aty128 *)p->fb_info);
2392}
2393#endif /* 0 */
2394
2395static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2396{
2397 u32 pmgt;
1da177e4
LT		 2398 struct pci_dev *pdev = par->pdev;
2399
2400 if (!par->pm_reg)
2401 return;
2402
2403 /* Set the chip into the appropriate suspend mode (we use D2,
2404 * D3 would require a complete re-initialisation of the chip,
2405 * including PCI config registers, clocks, AGP configuration, ...)
b746bb77
BH		 2406 *
2407 * For resume, the core will have already brought us back to D0
1da177e4
LT		 2408 */
2409 if (suspend) {
2410 /* Make sure CRTC2 is reset. Remove that the day we decide to
2411 * actually use CRTC2 and replace it with real code for disabling
2412 * the CRTC2 output during sleep
2413 */
2414 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2415 ~(CRTC2_EN));
2416
2417 /* Set the power management mode to be PCI based */
2418 /* Use this magic value for now */
2419 pmgt = 0x0c005407;
2420 aty_st_pll(POWER_MANAGEMENT, pmgt);
2421 (void)aty_ld_pll(POWER_MANAGEMENT);
2422 aty_st_le32(BUS_CNTL1, 0x00000010);
2423 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2424 mdelay(100);
b746bb77 2425
1da177e4 2426 /* Switch PCI power management to D2 */
b746bb77 2427 pci_set_power_state(pdev, PCI_D2);
1da177e4
LT		 2428 }
2429}
2430
2431static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2432{
2433 struct fb_info *info = pci_get_drvdata(pdev);
2434 struct aty128fb_par *par = info->par;
1da177e4 2435
b746bb77
BH		 2436 /* Because we may change PCI D state ourselves, we need to
2437 * first save the config space content so the core can
2438 * restore it properly on resume.
2439 */
2440 pci_save_state(pdev);
2441
1da177e4
LT		 2442 /* We don't do anything but D2, for now we return 0, but
2443 * we may want to change that. How do we know if the BIOS
2444 * can properly take care of D3 ? Also, with swsusp, we
2445 * know we'll be rebooted, ...
2446 */
ca078bae 2447#ifndef CONFIG_PPC_PMAC
1da177e4
LT		 2448 /* HACK ALERT ! Once I find a proper way to say to each driver
2449 * individually what will happen with it's PCI slot, I'll change
2450 * that. On laptops, the AGP slot is just unclocked, so D2 is
2451 * expected, while on desktops, the card is powered off
2452 */
ca078bae 2453 return 0;
1da177e4
LT		 2454#endif /* CONFIG_PPC_PMAC */
2455
ca078bae 2456 if (state.event == pdev->dev.power.power_state.event)
1da177e4
LT		 2457 return 0;
2458
2459 printk(KERN_DEBUG "aty128fb: suspending...\n");
2460
ac751efa 2461 console_lock();
1da177e4
LT		 2462
2463 fb_set_suspend(info, 1);
2464
2465 /* Make sure engine is reset */
2466 wait_for_idle(par);
2467 aty128_reset_engine(par);
2468 wait_for_idle(par);
2469
2470 /* Blank display and LCD */
125e1137 2471 aty128fb_blank(FB_BLANK_POWERDOWN, info);
1da177e4
LT		 2472
2473 /* Sleep */
2474 par->asleep = 1;
2475 par->lock_blank = 1;
2476
0c541b44
BH		 2477#ifdef CONFIG_PPC_PMAC
2478 /* On powermac, we have hooks to properly suspend/resume AGP now,
2479 * use them here. We'll ultimately need some generic support here,
2480 * but the generic code isn't quite ready for that yet
1da177e4 2481 */
0c541b44
BH		 2482 pmac_suspend_agp_for_card(pdev);
2483#endif /* CONFIG_PPC_PMAC */
1da177e4
LT		 2484
2485 /* We need a way to make sure the fbdev layer will _not_ touch the
2486 * framebuffer before we put the chip to suspend state. On 2.4, I
2487 * used dummy fb ops, 2.5 need proper support for this at the
2488 * fbdev level
2489 */
ca078bae 2490 if (state.event != PM_EVENT_ON)
1da177e4
LT		 2491 aty128_set_suspend(par, 1);
2492
ac751efa 2493 console_unlock();
1da177e4
LT		 2494
2495 pdev->dev.power.power_state = state;
2496
2497 return 0;
2498}
2499
2500static int aty128_do_resume(struct pci_dev *pdev)
2501{
2502 struct fb_info *info = pci_get_drvdata(pdev);
2503 struct aty128fb_par *par = info->par;
2504
ca078bae 2505 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
1da177e4
LT		 2506 return 0;
2507
b746bb77
BH		 2508 /* PCI state will have been restored by the core, so
2509 * we should be in D0 now with our config space fully
2510 * restored
2511 */
2512
1da177e4 2513 /* Wakeup chip */
ca078bae 2514 aty128_set_suspend(par, 0);
1da177e4
LT		 2515 par->asleep = 0;
2516
2517 /* Restore display & engine */
2518 aty128_reset_engine(par);
2519 wait_for_idle(par);
2520 aty128fb_set_par(info);
2521 fb_pan_display(info, &info->var);
2522 fb_set_cmap(&info->cmap, info);
2523
2524 /* Refresh */
2525 fb_set_suspend(info, 0);
2526
2527 /* Unblank */
2528 par->lock_blank = 0;
2529 aty128fb_blank(0, info);
2530
0c541b44
BH		 2531#ifdef CONFIG_PPC_PMAC
2532 /* On powermac, we have hooks to properly suspend/resume AGP now,
2533 * use them here. We'll ultimately need some generic support here,
2534 * but the generic code isn't quite ready for that yet
2535 */
2536 pmac_resume_agp_for_card(pdev);
2537#endif /* CONFIG_PPC_PMAC */
2538
1da177e4
LT		 2539 pdev->dev.power.power_state = PMSG_ON;
2540
2541 printk(KERN_DEBUG "aty128fb: resumed !\n");
2542
2543 return 0;
2544}
2545
2546static int aty128_pci_resume(struct pci_dev *pdev)
2547{
2548 int rc;
2549
ac751efa 2550 console_lock();
1da177e4 2551 rc = aty128_do_resume(pdev);
ac751efa 2552 console_unlock();
1da177e4
LT		 2553
2554 return rc;
2555}
2556
2557
48c68c4f 2558static int aty128fb_init(void)
1da177e4
LT		 2559{
2560#ifndef MODULE
2561 char *option = NULL;
2562
2563 if (fb_get_options("aty128fb", &option))
2564 return -ENODEV;
2565 aty128fb_setup(option);
2566#endif
2567
2568 return pci_register_driver(&aty128fb_driver);
2569}
2570
2571static void __exit aty128fb_exit(void)
2572{
2573 pci_unregister_driver(&aty128fb_driver);
2574}
2575
2576module_init(aty128fb_init);
2577
2578module_exit(aty128fb_exit);
2579
2580MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2581MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2582MODULE_LICENSE("GPL");
2583module_param(mode_option, charp, 0);
2584MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2585#ifdef CONFIG_MTRR
2586module_param_named(nomtrr, mtrr, invbool, 0);
2587MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
2588#endif
2589
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