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[POWERPC] Rename get_property to of_get_property: drivers
[mirror_ubuntu-jammy-kernel.git] / drivers / video / aty / radeon_base.c
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1da177e4
LT		 1/*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53#define RADEON_VERSION "0.2.0"
54
1da177e4
LT		 55#include <linux/module.h>
56#include <linux/moduleparam.h>
57#include <linux/kernel.h>
58#include <linux/errno.h>
59#include <linux/string.h>
60#include <linux/mm.h>
1da177e4
LT		 61#include <linux/slab.h>
62#include <linux/delay.h>
63#include <linux/time.h>
64#include <linux/fb.h>
65#include <linux/ioport.h>
66#include <linux/init.h>
67#include <linux/pci.h>
68#include <linux/vmalloc.h>
69#include <linux/device.h>
1da177e4
LT		 70
71#include <asm/io.h>
72#include <asm/uaccess.h>
73
74#ifdef CONFIG_PPC_OF
75
76#include <asm/pci-bridge.h>
77#include "../macmodes.h"
78
1da177e4
LT		 79#ifdef CONFIG_BOOTX_TEXT
80#include <asm/btext.h>
81#endif
82
83#endif /* CONFIG_PPC_OF */
84
85#ifdef CONFIG_MTRR
86#include <asm/mtrr.h>
87#endif
88
89#include <video/radeon.h>
90#include <linux/radeonfb.h>
91
92#include "../edid.h" // MOVE THAT TO include/video
93#include "ati_ids.h"
94#include "radeonfb.h"
95
96#define MAX_MAPPED_VRAM (2048*2048*4)
97#define MIN_MAPPED_VRAM (1024*768*1)
98
99#define CHIP_DEF(id, family, flags) \
100 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
101
102static struct pci_device_id radeonfb_pci_table[] = {
103 /* Mobility M6 */
104 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
105 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
106 /* Radeon VE/7000 */
107 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
108 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
183dee0f 109 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
1da177e4
LT		 110 /* Radeon IGP320M (U1) */
111 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
112 /* Radeon IGP320 (A3) */
113 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
114 /* IGP330M/340M/350M (U2) */
115 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
116 /* IGP330/340/350 (A4) */
117 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
118 /* Mobility 7000 IGP */
119 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
120 /* 7000 IGP (A4+) */
121 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
122 /* 8500 AIW */
123 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
124 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
125 /* 8700/8800 */
126 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
127 /* 8500 */
128 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
129 /* 9100 */
130 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
131 /* Mobility M7 */
132 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
133 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
134 /* 7500 */
135 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
136 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
137 /* Mobility M9 */
138 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
141 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
142 /* 9000/Pro */
143 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
144 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
145 /* Mobility 9100 IGP (U3) */
146 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
147 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
148 /* 9100 IGP (A5) */
149 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
150 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
151 /* Mobility 9200 (M9+) */
152 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
153 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
154 /* 9200 */
155 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
156 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
157 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
158 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
159 /* 9500 */
160 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
161 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
162 /* 9600TX / FireGL Z1 */
163 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
165 /* 9700/9500/Pro/FireGL X1 */
166 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
167 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
168 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
169 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
170 /* Mobility M10/M11 */
171 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
172 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
173 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
174 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
175 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
176 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
177 /* 9600/FireGL T2 */
178 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
179 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
180 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
181 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
182 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
183 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
184 /* 9800/Pro/FileGL X2 */
185 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
191 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
193 /* Newer stuff */
194 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
197 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
198 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
199 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
200 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
203 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
211 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
220 /* Original Radeon/7200 */
221 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
222 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
223 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
224 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
225 { 0, }
226};
227MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
228
229
230typedef struct {
231 u16 reg;
232 u32 val;
233} reg_val;
234
235
236/* these common regs are cleared before mode setting so they do not
237 * interfere with anything
238 */
239static reg_val common_regs[] = {
240 { OVR_CLR, 0 },
241 { OVR_WID_LEFT_RIGHT, 0 },
242 { OVR_WID_TOP_BOTTOM, 0 },
243 { OV0_SCALE_CNTL, 0 },
244 { SUBPIC_CNTL, 0 },
245 { VIPH_CONTROL, 0 },
246 { I2C_CNTL_1, 0 },
247 { GEN_INT_CNTL, 0 },
248 { CAP0_TRIG_CNTL, 0 },
249 { CAP1_TRIG_CNTL, 0 },
250};
251
252/*
253 * globals
254 */
255
256static char *mode_option;
257static char *monitor_layout;
258static int noaccel = 0;
259static int default_dynclk = -2;
260static int nomodeset = 0;
261static int ignore_edid = 0;
262static int mirror = 0;
263static int panel_yres = 0;
264static int force_dfp = 0;
265static int force_measure_pll = 0;
266#ifdef CONFIG_MTRR
267static int nomtrr = 0;
268#endif
994aad25
VB		 269static int force_sleep;
270static int ignore_devlist;
202d4e60
RP		 271#ifdef CONFIG_PMAC_BACKLIGHT
272static int backlight = 1;
273#else
274static int backlight = 0;
275#endif
1da177e4
LT		 276
277/*
278 * prototypes
279 */
280
1da177e4
LT		 281static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
282{
283 if (!rinfo->bios_seg)
284 return;
285 pci_unmap_rom(dev, rinfo->bios_seg);
286}
287
288static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
289{
290 void __iomem *rom;
291 u16 dptr;
292 u8 rom_type;
293 size_t rom_size;
294
295 /* If this is a primary card, there is a shadow copy of the
296 * ROM somewhere in the first meg. We will just ignore the copy
297 * and use the ROM directly.
298 */
299
300 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
301 unsigned int temp;
302 temp = INREG(MPP_TB_CONFIG);
303 temp &= 0x00ffffffu;
304 temp |= 0x04 << 24;
305 OUTREG(MPP_TB_CONFIG, temp);
306 temp = INREG(MPP_TB_CONFIG);
307
308 rom = pci_map_rom(dev, &rom_size);
309 if (!rom) {
310 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
311 pci_name(rinfo->pdev));
312 return -ENOMEM;
313 }
314
315 rinfo->bios_seg = rom;
316
317 /* Very simple test to make sure it appeared */
318 if (BIOS_IN16(0) != 0xaa55) {
3b4abffb
OH		 319 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
320 "should be 0xaa55\n",
321 pci_name(rinfo->pdev), BIOS_IN16(0));
1da177e4
LT		 322 goto failed;
323 }
324 /* Look for the PCI data to check the ROM type */
325 dptr = BIOS_IN16(0x18);
326
327 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
328 * for now, until I've verified this works everywhere. The goal here is more
329 * to phase out Open Firmware images.
330 *
331 * Currently, we only look at the first PCI data, we could iteratre and deal with
332 * them all, and we should use fb_bios_start relative to start of image and not
333 * relative start of ROM, but so far, I never found a dual-image ATI card
334 *
335 * typedef struct {
336 * u32 signature; + 0x00
337 * u16 vendor; + 0x04
338 * u16 device; + 0x06
339 * u16 reserved_1; + 0x08
340 * u16 dlen; + 0x0a
341 * u8 drevision; + 0x0c
342 * u8 class_hi; + 0x0d
343 * u16 class_lo; + 0x0e
344 * u16 ilen; + 0x10
345 * u16 irevision; + 0x12
346 * u8 type; + 0x14
347 * u8 indicator; + 0x15
348 * u16 reserved_2; + 0x16
349 * } pci_data_t;
350 */
351 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
352 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
353 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
354 goto anyway;
355 }
356 rom_type = BIOS_IN8(dptr + 0x14);
357 switch(rom_type) {
358 case 0:
359 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
360 break;
361 case 1:
362 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
363 goto failed;
364 case 2:
365 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
366 goto failed;
367 default:
368 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
369 goto failed;
370 }
371 anyway:
372 /* Locate the flat panel infos, do some sanity checking !!! */
373 rinfo->fp_bios_start = BIOS_IN16(0x48);
374 return 0;
375
376 failed:
377 rinfo->bios_seg = NULL;
378 radeon_unmap_ROM(rinfo, dev);
379 return -ENXIO;
380}
381
382#ifdef CONFIG_X86
383static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
384{
385 /* I simplified this code as we used to miss the signatures in
386 * a lot of case. It's now closer to XFree, we just don't check
387 * for signatures at all... Something better will have to be done
388 * if we end up having conflicts
389 */
390 u32 segstart;
391 void __iomem *rom_base = NULL;
392
393 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
394 rom_base = ioremap(segstart, 0x10000);
395 if (rom_base == NULL)
396 return -ENOMEM;
397 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
398 break;
399 iounmap(rom_base);
400 rom_base = NULL;
401 }
402 if (rom_base == NULL)
403 return -ENXIO;
404
405 /* Locate the flat panel infos, do some sanity checking !!! */
406 rinfo->bios_seg = rom_base;
407 rinfo->fp_bios_start = BIOS_IN16(0x48);
408
409 return 0;
410}
411#endif
412
9f47df26 413#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
1da177e4
LT		 414/*
415 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
416 * tree. Hopefully, ATI OF driver is kind enough to fill these
417 */
418static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
419{
420 struct device_node *dp = rinfo->of_node;
b04e3dd4 421 const u32 *val;
1da177e4
LT		 422
423 if (dp == NULL)
424 return -ENODEV;
40cd3a45 425 val = of_get_property(dp, "ATY,RefCLK", NULL);
1da177e4
LT		 426 if (!val || !*val) {
427 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
428 return -EINVAL;
429 }
430
431 rinfo->pll.ref_clk = (*val) / 10;
432
40cd3a45 433 val = of_get_property(dp, "ATY,SCLK", NULL);
1da177e4
LT		 434 if (val && *val)
435 rinfo->pll.sclk = (*val) / 10;
436
40cd3a45 437 val = of_get_property(dp, "ATY,MCLK", NULL);
1da177e4
LT		 438 if (val && *val)
439 rinfo->pll.mclk = (*val) / 10;
440
441 return 0;
442}
9f47df26 443#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
1da177e4
LT		 444
445/*
446 * Read PLL infos from chip registers
447 */
448static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
449{
450 unsigned char ppll_div_sel;
451 unsigned Ns, Nm, M;
452 unsigned sclk, mclk, tmp, ref_div;
453 int hTotal, vTotal, num, denom, m, n;
454 unsigned long long hz, vclk;
455 long xtal;
456 struct timeval start_tv, stop_tv;
457 long total_secs, total_usecs;
458 int i;
459
460 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
461 * here, so... --BenH
462 */
463
464 /* Flush PCI buffers ? */
017fb98e 465 tmp = INREG16(DEVICE_ID);
1da177e4
LT		 466
467 local_irq_disable();
468
469 for(i=0; i<1000000; i++)
470 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
471 break;
472
473 do_gettimeofday(&start_tv);
474
475 for(i=0; i<1000000; i++)
476 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
477 break;
478
479 for(i=0; i<1000000; i++)
480 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
481 break;
482
483 do_gettimeofday(&stop_tv);
484
485 local_irq_enable();
486
487 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
488 if (total_secs > 10)
489 return -1;
490 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
491 total_usecs += total_secs * 1000000;
492 if (total_usecs < 0)
493 total_usecs = -total_usecs;
494 hz = 1000000/total_usecs;
495
496 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
497 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
498 vclk = (long long)hTotal * (long long)vTotal * hz;
499
500 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
501 case 0:
502 default:
503 num = 1;
504 denom = 1;
505 break;
506 case 1:
507 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
508 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
509 num = 2*n;
510 denom = 2*m;
511 break;
512 case 2:
513 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
514 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
515 num = 2*n;
516 denom = 2*m;
517 break;
518 }
519
520 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
521 radeon_pll_errata_after_index(rinfo);
522
523 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
524 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
525
526 num *= n;
527 denom *= m;
528
529 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
530 case 1:
531 denom *= 2;
532 break;
533 case 2:
534 denom *= 4;
535 break;
536 case 3:
537 denom *= 8;
538 break;
539 case 4:
540 denom *= 3;
541 break;
542 case 6:
543 denom *= 6;
544 break;
545 case 7:
546 denom *= 12;
547 break;
548 }
549
550 vclk *= denom;
551 do_div(vclk, 1000 * num);
552 xtal = vclk;
553
554 if ((xtal > 26900) && (xtal < 27100))
555 xtal = 2700;
556 else if ((xtal > 14200) && (xtal < 14400))
557 xtal = 1432;
558 else if ((xtal > 29400) && (xtal < 29600))
559 xtal = 2950;
560 else {
561 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
562 return -1;
563 }
564
565 tmp = INPLL(M_SPLL_REF_FB_DIV);
566 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
567
568 Ns = (tmp & 0xff0000) >> 16;
569 Nm = (tmp & 0xff00) >> 8;
570 M = (tmp & 0xff);
571 sclk = round_div((2 * Ns * xtal), (2 * M));
572 mclk = round_div((2 * Nm * xtal), (2 * M));
573
574 /* we're done, hopefully these are sane values */
575 rinfo->pll.ref_clk = xtal;
576 rinfo->pll.ref_div = ref_div;
577 rinfo->pll.sclk = sclk;
578 rinfo->pll.mclk = mclk;
579
580 return 0;
581}
582
583/*
4a4efbde 584 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
1da177e4
LT		 585 */
586static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
587{
588 /*
589 * In the case nothing works, these are defaults; they are mostly
590 * incomplete, however. It does provide ppll_max and _min values
591 * even for most other methods, however.
592 */
593 switch (rinfo->chipset) {
594 case PCI_DEVICE_ID_ATI_RADEON_QW:
595 case PCI_DEVICE_ID_ATI_RADEON_QX:
596 rinfo->pll.ppll_max = 35000;
597 rinfo->pll.ppll_min = 12000;
598 rinfo->pll.mclk = 23000;
599 rinfo->pll.sclk = 23000;
600 rinfo->pll.ref_clk = 2700;
601 break;
602 case PCI_DEVICE_ID_ATI_RADEON_QL:
603 case PCI_DEVICE_ID_ATI_RADEON_QN:
604 case PCI_DEVICE_ID_ATI_RADEON_QO:
605 case PCI_DEVICE_ID_ATI_RADEON_Ql:
606 case PCI_DEVICE_ID_ATI_RADEON_BB:
607 rinfo->pll.ppll_max = 35000;
608 rinfo->pll.ppll_min = 12000;
609 rinfo->pll.mclk = 27500;
610 rinfo->pll.sclk = 27500;
611 rinfo->pll.ref_clk = 2700;
612 break;
613 case PCI_DEVICE_ID_ATI_RADEON_Id:
614 case PCI_DEVICE_ID_ATI_RADEON_Ie:
615 case PCI_DEVICE_ID_ATI_RADEON_If:
616 case PCI_DEVICE_ID_ATI_RADEON_Ig:
617 rinfo->pll.ppll_max = 35000;
618 rinfo->pll.ppll_min = 12000;
619 rinfo->pll.mclk = 25000;
620 rinfo->pll.sclk = 25000;
621 rinfo->pll.ref_clk = 2700;
622 break;
623 case PCI_DEVICE_ID_ATI_RADEON_ND:
624 case PCI_DEVICE_ID_ATI_RADEON_NE:
625 case PCI_DEVICE_ID_ATI_RADEON_NF:
626 case PCI_DEVICE_ID_ATI_RADEON_NG:
627 rinfo->pll.ppll_max = 40000;
628 rinfo->pll.ppll_min = 20000;
629 rinfo->pll.mclk = 27000;
630 rinfo->pll.sclk = 27000;
631 rinfo->pll.ref_clk = 2700;
632 break;
633 case PCI_DEVICE_ID_ATI_RADEON_QD:
634 case PCI_DEVICE_ID_ATI_RADEON_QE:
635 case PCI_DEVICE_ID_ATI_RADEON_QF:
636 case PCI_DEVICE_ID_ATI_RADEON_QG:
637 default:
638 rinfo->pll.ppll_max = 35000;
639 rinfo->pll.ppll_min = 12000;
640 rinfo->pll.mclk = 16600;
641 rinfo->pll.sclk = 16600;
642 rinfo->pll.ref_clk = 2700;
643 break;
644 }
645 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
646
647
9f47df26 648#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
1da177e4 649 /*
4a4efbde 650 * Retrieve PLL infos from Open Firmware first
1da177e4
LT		 651 */
652 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
4a4efbde 653 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
1da177e4
LT		 654 goto found;
655 }
9f47df26 656#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
1da177e4
LT		 657
658 /*
659 * Check out if we have an X86 which gave us some PLL informations
4a4efbde 660 * and if yes, retrieve them
1da177e4
LT		 661 */
662 if (!force_measure_pll && rinfo->bios_seg) {
663 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
664
665 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
666 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
667 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
668 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
669 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
670 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
671
4a4efbde 672 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
1da177e4
LT		 673 goto found;
674 }
675
676 /*
677 * We didn't get PLL parameters from either OF or BIOS, we try to
678 * probe them
679 */
680 if (radeon_probe_pll_params(rinfo) == 0) {
4a4efbde 681 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
1da177e4
LT		 682 goto found;
683 }
684
685 /*
686 * Fall back to already-set defaults...
687 */
688 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
689
690found:
691 /*
4a4efbde 692 * Some methods fail to retrieve SCLK and MCLK values, we apply default
1da177e4
LT		 693 * settings in this case (200Mhz). If that really happne often, we could
694 * fetch from registers instead...
695 */
696 if (rinfo->pll.mclk == 0)
697 rinfo->pll.mclk = 20000;
698 if (rinfo->pll.sclk == 0)
699 rinfo->pll.sclk = 20000;
700
701 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
702 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
703 rinfo->pll.ref_div,
704 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
705 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
706 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
707}
708
709static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
710{
711 struct radeonfb_info *rinfo = info->par;
712 struct fb_var_screeninfo v;
713 int nom, den;
714 unsigned int pitch;
715
716 if (radeon_match_mode(rinfo, &v, var))
717 return -EINVAL;
718
719 switch (v.bits_per_pixel) {
720 case 0 ... 8:
721 v.bits_per_pixel = 8;
722 break;
723 case 9 ... 16:
724 v.bits_per_pixel = 16;
725 break;
726 case 17 ... 24:
727#if 0 /* Doesn't seem to work */
728 v.bits_per_pixel = 24;
729 break;
730#endif
731 return -EINVAL;
732 case 25 ... 32:
733 v.bits_per_pixel = 32;
734 break;
735 default:
736 return -EINVAL;
737 }
738
739 switch (var_to_depth(&v)) {
740 case 8:
741 nom = den = 1;
742 v.red.offset = v.green.offset = v.blue.offset = 0;
743 v.red.length = v.green.length = v.blue.length = 8;
744 v.transp.offset = v.transp.length = 0;
745 break;
746 case 15:
747 nom = 2;
748 den = 1;
749 v.red.offset = 10;
750 v.green.offset = 5;
751 v.blue.offset = 0;
752 v.red.length = v.green.length = v.blue.length = 5;
753 v.transp.offset = v.transp.length = 0;
754 break;
755 case 16:
756 nom = 2;
757 den = 1;
758 v.red.offset = 11;
759 v.green.offset = 5;
760 v.blue.offset = 0;
761 v.red.length = 5;
762 v.green.length = 6;
763 v.blue.length = 5;
764 v.transp.offset = v.transp.length = 0;
765 break;
766 case 24:
767 nom = 4;
768 den = 1;
769 v.red.offset = 16;
770 v.green.offset = 8;
771 v.blue.offset = 0;
772 v.red.length = v.blue.length = v.green.length = 8;
773 v.transp.offset = v.transp.length = 0;
774 break;
775 case 32:
776 nom = 4;
777 den = 1;
778 v.red.offset = 16;
779 v.green.offset = 8;
780 v.blue.offset = 0;
781 v.red.length = v.blue.length = v.green.length = 8;
782 v.transp.offset = 24;
783 v.transp.length = 8;
784 break;
785 default:
786 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
787 var->xres, var->yres, var->bits_per_pixel);
788 return -EINVAL;
789 }
790
791 if (v.yres_virtual < v.yres)
792 v.yres_virtual = v.yres;
793 if (v.xres_virtual < v.xres)
794 v.xres_virtual = v.xres;
795
796
797 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
798 * with some panels, though I don't quite like this solution
799 */
800 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
801 v.xres_virtual = v.xres_virtual & ~7ul;
802 } else {
803 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
804 & ~(0x3f)) >> 6;
805 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
806 }
807
808 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
809 return -EINVAL;
810
811 if (v.xres_virtual < v.xres)
812 v.xres = v.xres_virtual;
813
814 if (v.xoffset < 0)
815 v.xoffset = 0;
816 if (v.yoffset < 0)
817 v.yoffset = 0;
818
819 if (v.xoffset > v.xres_virtual - v.xres)
820 v.xoffset = v.xres_virtual - v.xres - 1;
821
822 if (v.yoffset > v.yres_virtual - v.yres)
823 v.yoffset = v.yres_virtual - v.yres - 1;
824
825 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
826 v.transp.offset = v.transp.length =
827 v.transp.msb_right = 0;
828
829 memcpy(var, &v, sizeof(v));
830
831 return 0;
832}
833
834
835static int radeonfb_pan_display (struct fb_var_screeninfo *var,
836 struct fb_info *info)
837{
838 struct radeonfb_info *rinfo = info->par;
839
840 if ((var->xoffset + var->xres > var->xres_virtual)
841 || (var->yoffset + var->yres > var->yres_virtual))
842 return -EINVAL;
843
844 if (rinfo->asleep)
845 return 0;
846
847 radeon_fifo_wait(2);
848 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
849 * var->bits_per_pixel / 8) & ~7);
850 return 0;
851}
852
853
67a6680d
CH		 854static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
855 unsigned long arg)
1da177e4
LT		 856{
857 struct radeonfb_info *rinfo = info->par;
858 unsigned int tmp;
859 u32 value = 0;
860 int rc;
861
862 switch (cmd) {
863 /*
864 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
865 * and do something better using 2nd CRTC instead of just hackish
866 * routing to second output
867 */
868 case FBIO_RADEON_SET_MIRROR:
869 if (!rinfo->is_mobility)
870 return -EINVAL;
871
872 rc = get_user(value, (__u32 __user *)arg);
873
874 if (rc)
875 return rc;
876
877 radeon_fifo_wait(2);
878 if (value & 0x01) {
879 tmp = INREG(LVDS_GEN_CNTL);
880
881 tmp |= (LVDS_ON | LVDS_BLON);
882 } else {
883 tmp = INREG(LVDS_GEN_CNTL);
884
885 tmp &= ~(LVDS_ON | LVDS_BLON);
886 }
887
888 OUTREG(LVDS_GEN_CNTL, tmp);
889
890 if (value & 0x02) {
891 tmp = INREG(CRTC_EXT_CNTL);
892 tmp |= CRTC_CRT_ON;
893
894 mirror = 1;
895 } else {
896 tmp = INREG(CRTC_EXT_CNTL);
897 tmp &= ~CRTC_CRT_ON;
898
899 mirror = 0;
900 }
901
902 OUTREG(CRTC_EXT_CNTL, tmp);
903
904 return 0;
905 case FBIO_RADEON_GET_MIRROR:
906 if (!rinfo->is_mobility)
907 return -EINVAL;
908
909 tmp = INREG(LVDS_GEN_CNTL);
910 if ((LVDS_ON | LVDS_BLON) & tmp)
911 value |= 0x01;
912
913 tmp = INREG(CRTC_EXT_CNTL);
914 if (CRTC_CRT_ON & tmp)
915 value |= 0x02;
916
917 return put_user(value, (__u32 __user *)arg);
918 default:
919 return -EINVAL;
920 }
921
922 return -EINVAL;
923}
924
925
926int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
927{
928 u32 val;
929 u32 tmp_pix_clks;
930 int unblank = 0;
931
932 if (rinfo->lock_blank)
933 return 0;
934
935 radeon_engine_idle();
936
937 val = INREG(CRTC_EXT_CNTL);
938 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
939 CRTC_VSYNC_DIS);
940 switch (blank) {
941 case FB_BLANK_VSYNC_SUSPEND:
942 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
943 break;
944 case FB_BLANK_HSYNC_SUSPEND:
945 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
946 break;
947 case FB_BLANK_POWERDOWN:
948 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
949 CRTC_HSYNC_DIS);
950 break;
951 case FB_BLANK_NORMAL:
952 val |= CRTC_DISPLAY_DIS;
953 break;
954 case FB_BLANK_UNBLANK:
955 default:
956 unblank = 1;
957 }
958 OUTREG(CRTC_EXT_CNTL, val);
959
960
961 switch (rinfo->mon1_type) {
962 case MT_DFP:
963 if (unblank)
964 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
965 ~(FP_FPON | FP_TMDS_EN));
966 else {
967 if (mode_switch || blank == FB_BLANK_NORMAL)
968 break;
969 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
970 }
971 break;
972 case MT_LCD:
973 del_timer_sync(&rinfo->lvds_timer);
974 val = INREG(LVDS_GEN_CNTL);
975 if (unblank) {
976 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
977 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
978 & (LVDS_DIGON | LVDS_BL_MOD_EN));
979 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
980 OUTREG(LVDS_GEN_CNTL, target_val);
981 else if ((val ^ target_val) != 0) {
982 OUTREG(LVDS_GEN_CNTL, target_val
983 & ~(LVDS_ON | LVDS_BL_MOD_EN));
984 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
985 rinfo->init_state.lvds_gen_cntl |=
986 target_val & LVDS_STATE_MASK;
987 if (mode_switch) {
988 radeon_msleep(rinfo->panel_info.pwr_delay);
989 OUTREG(LVDS_GEN_CNTL, target_val);
990 }
991 else {
992 rinfo->pending_lvds_gen_cntl = target_val;
993 mod_timer(&rinfo->lvds_timer,
994 jiffies +
995 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
996 }
997 }
998 } else {
999 val |= LVDS_DISPLAY_DIS;
1000 OUTREG(LVDS_GEN_CNTL, val);
1001
1002 /* We don't do a full switch-off on a simple mode switch */
1003 if (mode_switch || blank == FB_BLANK_NORMAL)
1004 break;
1005
1006 /* Asic bug, when turning off LVDS_ON, we have to make sure
1007 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1008 */
1009 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1010 if (rinfo->is_mobility || rinfo->is_IGP)
1011 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1012 val &= ~(LVDS_BL_MOD_EN);
1013 OUTREG(LVDS_GEN_CNTL, val);
1014 udelay(100);
1015 val &= ~(LVDS_ON | LVDS_EN);
1016 OUTREG(LVDS_GEN_CNTL, val);
1017 val &= ~LVDS_DIGON;
1018 rinfo->pending_lvds_gen_cntl = val;
1019 mod_timer(&rinfo->lvds_timer,
1020 jiffies +
1021 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1022 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1023 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1024 if (rinfo->is_mobility || rinfo->is_IGP)
1025 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1026 }
1027 break;
1028 case MT_CRT:
1029 // todo: powerdown DAC
1030 default:
1031 break;
1032 }
1033
7ab87670 1034 return 0;
1da177e4
LT		 1035}
1036
1037static int radeonfb_blank (int blank, struct fb_info *info)
1038{
1039 struct radeonfb_info *rinfo = info->par;
1040
1041 if (rinfo->asleep)
1042 return 0;
1043
1044 return radeon_screen_blank(rinfo, blank, 0);
1045}
1046
71494376
BH		 1047static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1048 unsigned blue, unsigned transp,
1049 struct radeonfb_info *rinfo)
1da177e4 1050{
1da177e4
LT		 1051 u32 pindex;
1052 unsigned int i;
71494376
BH		 1053
1054
1da177e4 1055 if (regno > 255)
db77ec27 1056 return -EINVAL;
1da177e4
LT		 1057
1058 red >>= 8;
1059 green >>= 8;
1060 blue >>= 8;
1061 rinfo->palette[regno].red = red;
1062 rinfo->palette[regno].green = green;
1063 rinfo->palette[regno].blue = blue;
1064
1065 /* default */
1066 pindex = regno;
1067
1068 if (!rinfo->asleep) {
1da177e4 1069 radeon_fifo_wait(9);
1da177e4
LT		 1070
1071 if (rinfo->bpp == 16) {
1072 pindex = regno * 8;
1073
1074 if (rinfo->depth == 16 && regno > 63)
db77ec27 1075 return -EINVAL;
1da177e4 1076 if (rinfo->depth == 15 && regno > 31)
db77ec27 1077 return -EINVAL;
1da177e4 1078
71494376
BH		 1079 /* For 565, the green component is mixed one order
1080 * below
1081 */
1da177e4
LT		 1082 if (rinfo->depth == 16) {
1083 OUTREG(PALETTE_INDEX, pindex>>1);
71494376
BH		 1084 OUTREG(PALETTE_DATA,
1085 (rinfo->palette[regno>>1].red << 16) |
1086 (green << 8) |
1087 (rinfo->palette[regno>>1].blue));
1da177e4
LT		 1088 green = rinfo->palette[regno<<1].green;
1089 }
1090 }
1091
1092 if (rinfo->depth != 16 || regno < 32) {
1093 OUTREG(PALETTE_INDEX, pindex);
71494376
BH		 1094 OUTREG(PALETTE_DATA, (red << 16) |
1095 (green << 8) | blue);
1da177e4 1096 }
1da177e4
LT		 1097 }
1098 if (regno < 16) {
71494376 1099 u32 *pal = rinfo->info->pseudo_palette;
1da177e4
LT		 1100 switch (rinfo->depth) {
1101 case 15:
1102 pal[regno] = (regno << 10) | (regno << 5) | regno;
1103 break;
1104 case 16:
1105 pal[regno] = (regno << 11) | (regno << 5) | regno;
1106 break;
1107 case 24:
1108 pal[regno] = (regno << 16) | (regno << 8) | regno;
1109 break;
1110 case 32:
1111 i = (regno << 8) | regno;
1112 pal[regno] = (i << 16) | i;
1113 break;
1114 }
1115 }
1116 return 0;
1117}
1118
71494376
BH		 1119static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1120 unsigned blue, unsigned transp,
1121 struct fb_info *info)
1122{
1123 struct radeonfb_info *rinfo = info->par;
1124 u32 dac_cntl2, vclk_cntl = 0;
1125 int rc;
1126
1127 if (!rinfo->asleep) {
1128 if (rinfo->is_mobility) {
1129 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1130 OUTPLL(VCLK_ECP_CNTL,
1131 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1132 }
1133
1134 /* Make sure we are on first palette */
1135 if (rinfo->has_CRTC2) {
1136 dac_cntl2 = INREG(DAC_CNTL2);
1137 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1138 OUTREG(DAC_CNTL2, dac_cntl2);
1139 }
1140 }
1141
1142 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1143
1144 if (!rinfo->asleep && rinfo->is_mobility)
1145 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1146
1147 return rc;
1148}
1149
1150static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1151{
1152 struct radeonfb_info *rinfo = info->par;
1153 u16 *red, *green, *blue, *transp;
1154 u32 dac_cntl2, vclk_cntl = 0;
1155 int i, start, rc = 0;
1156
1157 if (!rinfo->asleep) {
1158 if (rinfo->is_mobility) {
1159 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1160 OUTPLL(VCLK_ECP_CNTL,
1161 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1162 }
1163
1164 /* Make sure we are on first palette */
1165 if (rinfo->has_CRTC2) {
1166 dac_cntl2 = INREG(DAC_CNTL2);
1167 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1168 OUTREG(DAC_CNTL2, dac_cntl2);
1169 }
1170 }
1171
1172 red = cmap->red;
1173 green = cmap->green;
1174 blue = cmap->blue;
1175 transp = cmap->transp;
1176 start = cmap->start;
1177
1178 for (i = 0; i < cmap->len; i++) {
1179 u_int hred, hgreen, hblue, htransp = 0xffff;
1180
1181 hred = *red++;
1182 hgreen = *green++;
1183 hblue = *blue++;
1184 if (transp)
1185 htransp = *transp++;
1186 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1187 rinfo);
1188 if (rc)
1189 break;
1190 }
1191
1192 if (!rinfo->asleep && rinfo->is_mobility)
1193 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1194
1195 return rc;
1196}
1da177e4
LT		 1197
1198static void radeon_save_state (struct radeonfb_info *rinfo,
1199 struct radeon_regs *save)
1200{
1201 /* CRTC regs */
1202 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1203 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1204 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1205 save->dac_cntl = INREG(DAC_CNTL);
1206 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1207 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1208 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1209 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1210 save->crtc_pitch = INREG(CRTC_PITCH);
1211 save->surface_cntl = INREG(SURFACE_CNTL);
1212
1213 /* FP regs */
1214 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1215 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1216 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1217 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1218 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1219 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1220 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1221 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1222 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1223 save->tmds_crc = INREG(TMDS_CRC);
1224 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1225 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1226
1227 /* PLL regs */
1228 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1229 radeon_pll_errata_after_index(rinfo);
1230 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1231 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1232}
1233
1234
1235static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1236{
1237 int i;
1238
1239 radeon_fifo_wait(20);
1240
1241 /* Workaround from XFree */
1242 if (rinfo->is_mobility) {
1243 /* A temporal workaround for the occational blanking on certain laptop
1244 * panels. This appears to related to the PLL divider registers
1245 * (fail to lock?). It occurs even when all dividers are the same
1246 * with their old settings. In this case we really don't need to
1247 * fiddle with PLL registers. By doing this we can avoid the blanking
1248 * problem with some panels.
1249 */
1250 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1251 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1252 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1253 /* We still have to force a switch to selected PPLL div thanks to
1254 * an XFree86 driver bug which will switch it away in some cases
1255 * even when using UseFDev */
1256 OUTREGP(CLOCK_CNTL_INDEX,
1257 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1258 ~PPLL_DIV_SEL_MASK);
1259 radeon_pll_errata_after_index(rinfo);
1260 radeon_pll_errata_after_data(rinfo);
1261 return;
1262 }
1263 }
1264
1265 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1266 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1267
1268 /* Reset PPLL & enable atomic update */
1269 OUTPLLP(PPLL_CNTL,
1270 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1271 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1272
1273 /* Switch to selected PPLL divider */
1274 OUTREGP(CLOCK_CNTL_INDEX,
1275 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1276 ~PPLL_DIV_SEL_MASK);
1277 radeon_pll_errata_after_index(rinfo);
1278 radeon_pll_errata_after_data(rinfo);
1279
1280 /* Set PPLL ref. div */
1281 if (rinfo->family == CHIP_FAMILY_R300 ||
1282 rinfo->family == CHIP_FAMILY_RS300 ||
1283 rinfo->family == CHIP_FAMILY_R350 ||
1284 rinfo->family == CHIP_FAMILY_RV350) {
1285 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1286 /* When restoring console mode, use saved PPLL_REF_DIV
1287 * setting.
1288 */
1289 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1290 } else {
1291 /* R300 uses ref_div_acc field as real ref divider */
1292 OUTPLLP(PPLL_REF_DIV,
1293 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1294 ~R300_PPLL_REF_DIV_ACC_MASK);
1295 }
1296 } else
1297 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1298
1299 /* Set PPLL divider 3 & post divider*/
1300 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1301 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1302
1303 /* Write update */
1304 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1305 ;
1306 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1307
1308 /* Wait read update complete */
1309 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1310 the cause yet, but this workaround will mask the problem for now.
1311 Other chips usually will pass at the very first test, so the
1312 workaround shouldn't have any effect on them. */
1313 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1314 ;
1315
1316 OUTPLL(HTOTAL_CNTL, 0);
1317
1318 /* Clear reset & atomic update */
1319 OUTPLLP(PPLL_CNTL, 0,
1320 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1321
1322 /* We may want some locking ... oh well */
1323 radeon_msleep(5);
1324
1325 /* Switch back VCLK source to PPLL */
1326 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1327}
1328
1329/*
1330 * Timer function for delayed LVDS panel power up/down
1331 */
1332static void radeon_lvds_timer_func(unsigned long data)
1333{
1334 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1335
1336 radeon_engine_idle();
1337
1338 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1339}
1340
1341/*
1342 * Apply a video mode. This will apply the whole register set, including
1343 * the PLL registers, to the card
1344 */
1345void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1346 int regs_only)
1347{
1348 int i;
1349 int primary_mon = PRIMARY_MONITOR(rinfo);
1350
1351 if (nomodeset)
1352 return;
1353
1354 if (!regs_only)
1355 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1356
1357 radeon_fifo_wait(31);
1358 for (i=0; i<10; i++)
1359 OUTREG(common_regs[i].reg, common_regs[i].val);
1360
1361 /* Apply surface registers */
1362 for (i=0; i<8; i++) {
1363 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1364 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1365 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1366 }
1367
1368 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1369 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1370 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1371 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1372 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1373 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1374 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1375 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1376 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1377 OUTREG(CRTC_OFFSET, 0);
1378 OUTREG(CRTC_OFFSET_CNTL, 0);
1379 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1380 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1381
1382 radeon_write_pll_regs(rinfo, mode);
1383
1384 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1385 radeon_fifo_wait(10);
1386 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1387 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1388 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1389 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1390 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1391 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1392 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1393 OUTREG(TMDS_CRC, mode->tmds_crc);
1394 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1395 }
1396
1397 if (!regs_only)
1398 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1399
1400 radeon_fifo_wait(2);
1401 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1402
1403 return;
1404}
1405
1406/*
1407 * Calculate the PLL values for a given mode
1408 */
1409static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1410 unsigned long freq)
1411{
1412 const struct {
1413 int divider;
1414 int bitvalue;
1415 } *post_div,
1416 post_divs[] = {
1417 { 1, 0 },
1418 { 2, 1 },
1419 { 4, 2 },
1420 { 8, 3 },
1421 { 3, 4 },
1422 { 16, 5 },
1423 { 6, 6 },
1424 { 12, 7 },
1425 { 0, 0 },
1426 };
1427 int fb_div, pll_output_freq = 0;
1428 int uses_dvo = 0;
1429
1430 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1431 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1432 * recent than an r(v)100...
1433 */
1434#if 1
1435 /* XXX I had reports of flicker happening with the cinema display
1436 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1437 * this case. This could just be a bandwidth calculation issue, I
1438 * haven't implemented the bandwidth code yet, but in the meantime,
1439 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1440 * I haven't seen a case were were absolutely needed an odd PLL
1441 * divider. I'll find a better fix once I have more infos on the
1442 * real cause of the problem.
1443 */
1444 while (rinfo->has_CRTC2) {
1445 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1446 u32 disp_output_cntl;
1447 int source;
1448
1449 /* FP2 path not enabled */
1450 if ((fp2_gen_cntl & FP2_ON) == 0)
1451 break;
1452 /* Not all chip revs have the same format for this register,
1453 * extract the source selection
1454 */
1455 if (rinfo->family == CHIP_FAMILY_R200 ||
1456 rinfo->family == CHIP_FAMILY_R300 ||
1457 rinfo->family == CHIP_FAMILY_R350 ||
1458 rinfo->family == CHIP_FAMILY_RV350) {
1459 source = (fp2_gen_cntl >> 10) & 0x3;
1460 /* sourced from transform unit, check for transform unit
1461 * own source
1462 */
1463 if (source == 3) {
1464 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1465 source = (disp_output_cntl >> 12) & 0x3;
1466 }
1467 } else
1468 source = (fp2_gen_cntl >> 13) & 0x1;
1469 /* sourced from CRTC2 -> exit */
1470 if (source == 1)
1471 break;
1472
1473 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1474 uses_dvo = 1;
1475 break;
1476 }
1477#else
1478 uses_dvo = 1;
1479#endif
1480 if (freq > rinfo->pll.ppll_max)
1481 freq = rinfo->pll.ppll_max;
1482 if (freq*12 < rinfo->pll.ppll_min)
1483 freq = rinfo->pll.ppll_min / 12;
1484 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1485 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1486
1487 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1488 pll_output_freq = post_div->divider * freq;
1489 /* If we output to the DVO port (external TMDS), we don't allow an
1490 * odd PLL divider as those aren't supported on this path
1491 */
1492 if (uses_dvo && (post_div->divider & 1))
1493 continue;
1494 if (pll_output_freq >= rinfo->pll.ppll_min &&
1495 pll_output_freq <= rinfo->pll.ppll_max)
1496 break;
1497 }
1498
1499 /* If we fall through the bottom, try the "default value"
1500 given by the terminal post_div->bitvalue */
1501 if ( !post_div->divider ) {
1502 post_div = &post_divs[post_div->bitvalue];
1503 pll_output_freq = post_div->divider * freq;
1504 }
1505 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1506 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1507 pll_output_freq);
1508
1509 /* If we fall through the bottom, try the "default value"
1510 given by the terminal post_div->bitvalue */
1511 if ( !post_div->divider ) {
1512 post_div = &post_divs[post_div->bitvalue];
1513 pll_output_freq = post_div->divider * freq;
1514 }
1515 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1516 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1517 pll_output_freq);
1518
1519 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1520 rinfo->pll.ref_clk);
1521 regs->ppll_ref_div = rinfo->pll.ref_div;
1522 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1523
1524 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1525 RTRACE("fb_div = 0x%x\n", fb_div);
1526 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1527}
1528
1529static int radeonfb_set_par(struct fb_info *info)
1530{
1531 struct radeonfb_info *rinfo = info->par;
1532 struct fb_var_screeninfo *mode = &info->var;
1533 struct radeon_regs *newmode;
1534 int hTotal, vTotal, hSyncStart, hSyncEnd,
1535 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1536 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1537 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1538 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1539 int i, freq;
1540 int format = 0;
1541 int nopllcalc = 0;
1542 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1543 int primary_mon = PRIMARY_MONITOR(rinfo);
1544 int depth = var_to_depth(mode);
1545 int use_rmx = 0;
1546
1547 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1548 if (!newmode)
1549 return -ENOMEM;
1550
1551 /* We always want engine to be idle on a mode switch, even
1552 * if we won't actually change the mode
1553 */
1554 radeon_engine_idle();
1555
1556 hSyncStart = mode->xres + mode->right_margin;
1557 hSyncEnd = hSyncStart + mode->hsync_len;
1558 hTotal = hSyncEnd + mode->left_margin;
1559
1560 vSyncStart = mode->yres + mode->lower_margin;
1561 vSyncEnd = vSyncStart + mode->vsync_len;
1562 vTotal = vSyncEnd + mode->upper_margin;
1563 pixClock = mode->pixclock;
1564
1565 sync = mode->sync;
1566 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1567 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1568
1569 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1570 if (rinfo->panel_info.xres < mode->xres)
1571 mode->xres = rinfo->panel_info.xres;
1572 if (rinfo->panel_info.yres < mode->yres)
1573 mode->yres = rinfo->panel_info.yres;
1574
1575 hTotal = mode->xres + rinfo->panel_info.hblank;
1576 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1577 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1578
1579 vTotal = mode->yres + rinfo->panel_info.vblank;
1580 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1581 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1582
1583 h_sync_pol = !rinfo->panel_info.hAct_high;
1584 v_sync_pol = !rinfo->panel_info.vAct_high;
1585
1586 pixClock = 100000000 / rinfo->panel_info.clock;
1587
1588 if (rinfo->panel_info.use_bios_dividers) {
1589 nopllcalc = 1;
1590 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1591 (rinfo->panel_info.post_divider << 16);
1592 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1593 }
1594 }
1595 dotClock = 1000000000 / pixClock;
1596 freq = dotClock / 10; /* x100 */
1597
1598 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1599 hSyncStart, hSyncEnd, hTotal);
1600 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1601 vSyncStart, vSyncEnd, vTotal);
1602
1603 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1604 vsync_wid = vSyncEnd - vSyncStart;
1605 if (hsync_wid == 0)
1606 hsync_wid = 1;
1607 else if (hsync_wid > 0x3f) /* max */
1608 hsync_wid = 0x3f;
1609
1610 if (vsync_wid == 0)
1611 vsync_wid = 1;
1612 else if (vsync_wid > 0x1f) /* max */
1613 vsync_wid = 0x1f;
1614
1615 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1616 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1617
1618 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1619
1620 format = radeon_get_dstbpp(depth);
1621 bytpp = mode->bits_per_pixel >> 3;
1622
1623 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1624 hsync_fudge = hsync_fudge_fp[format-1];
1625 else
1626 hsync_fudge = hsync_adj_tab[format-1];
1627
1628 hsync_start = hSyncStart - 8 + hsync_fudge;
1629
1630 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1631 (format << 8);
1632
1633 /* Clear auto-center etc... */
1634 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1635 newmode->crtc_more_cntl &= 0xfffffff0;
1636
1637 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1638 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1639 if (mirror)
1640 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1641
1642 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1643 CRTC_INTERLACE_EN);
1644 } else {
1645 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1646 CRTC_CRT_ON;
1647 }
1648
1649 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1650 DAC_8BIT_EN;
1651
1652 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1653 (((mode->xres / 8) - 1) << 16));
1654
1655 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1656 (hsync_wid << 16) | (h_sync_pol << 23));
1657
1658 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1659 ((mode->yres - 1) << 16);
1660
1661 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1662 (vsync_wid << 16) | (v_sync_pol << 23));
1663
1664 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1665 /* We first calculate the engine pitch */
1666 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1667 & ~(0x3f)) >> 6;
1668
1669 /* Then, re-multiply it to get the CRTC pitch */
1670 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1671 } else
1672 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1673
1674 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1675
1676 /*
1677 * It looks like recent chips have a problem with SURFACE_CNTL,
1678 * setting SURF_TRANSLATION_DIS completely disables the
1679 * swapper as well, so we leave it unset now.
1680 */
1681 newmode->surface_cntl = 0;
1682
1683#if defined(__BIG_ENDIAN)
1684
1685 /* Setup swapping on both apertures, though we currently
1686 * only use aperture 0, enabling swapper on aperture 1
1687 * won't harm
1688 */
1689 switch (mode->bits_per_pixel) {
1690 case 16:
1691 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1692 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1693 break;
1694 case 24:
1695 case 32:
1696 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1697 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1698 break;
1699 }
1700#endif
1701
1702 /* Clear surface registers */
1703 for (i=0; i<8; i++) {
1704 newmode->surf_lower_bound[i] = 0;
1705 newmode->surf_upper_bound[i] = 0x1f;
1706 newmode->surf_info[i] = 0;
1707 }
1708
1709 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1710 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1711 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1712 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1713
1714 rinfo->bpp = mode->bits_per_pixel;
1715 rinfo->depth = depth;
1716
1717 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1718 RTRACE("freq = %lu\n", (unsigned long)freq);
1719
1720 /* We use PPLL_DIV_3 */
1721 newmode->clk_cntl_index = 0x300;
1722
1723 /* Calculate PPLL value if necessary */
1724 if (!nopllcalc)
1725 radeon_calc_pll_regs(rinfo, newmode, freq);
1726
1727 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1728
1729 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1730 unsigned int hRatio, vRatio;
1731
1732 if (mode->xres > rinfo->panel_info.xres)
1733 mode->xres = rinfo->panel_info.xres;
1734 if (mode->yres > rinfo->panel_info.yres)
1735 mode->yres = rinfo->panel_info.yres;
1736
1737 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1738 << HORZ_PANEL_SHIFT);
1739 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1740 << VERT_PANEL_SHIFT);
1741
1742 if (mode->xres != rinfo->panel_info.xres) {
1743 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1744 rinfo->panel_info.xres);
1745 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1746 (newmode->fp_horz_stretch &
1747 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1748 HORZ_AUTO_RATIO_INC)));
1749 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1750 HORZ_STRETCH_ENABLE);
1751 use_rmx = 1;
1752 }
1753 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1754
1755 if (mode->yres != rinfo->panel_info.yres) {
1756 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1757 rinfo->panel_info.yres);
1758 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1759 (newmode->fp_vert_stretch &
1760 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1761 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1762 VERT_STRETCH_ENABLE);
1763 use_rmx = 1;
1764 }
1765 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1766
1767 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1768 ~(FP_SEL_CRTC2 |
1769 FP_RMX_HVSYNC_CONTROL_EN |
1770 FP_DFP_SYNC_SEL |
1771 FP_CRT_SYNC_SEL |
1772 FP_CRTC_LOCK_8DOT |
1773 FP_USE_SHADOW_EN |
1774 FP_CRTC_USE_SHADOW_VEND |
1775 FP_CRT_SYNC_ALT));
1776
1777 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1778 FP_CRTC_DONT_SHADOW_HEND |
1779 FP_PANEL_FORMAT);
1780
1781 if (IS_R300_VARIANT(rinfo) ||
1782 (rinfo->family == CHIP_FAMILY_R200)) {
1783 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1784 if (use_rmx)
1785 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1786 else
1787 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1788 } else
1789 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1790
1791 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1792 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1793 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1794 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1795
1796 if (primary_mon == MT_LCD) {
1797 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1798 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1799 } else {
1800 /* DFP */
1801 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1802 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1803 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1804 if (IS_R300_VARIANT(rinfo) ||
1805 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1806 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1807 else
1808 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1809 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1810 }
1811
1812 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1813 (((mode->xres / 8) - 1) << 16));
1814 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1815 ((mode->yres - 1) << 16);
1816 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1817 (hsync_wid << 16) | (h_sync_pol << 23));
1818 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1819 (vsync_wid << 16) | (v_sync_pol << 23));
1820 }
1821
1822 /* do it! */
1823 if (!rinfo->asleep) {
1824 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1825 radeon_write_mode (rinfo, newmode, 0);
1826 /* (re)initialize the engine */
1827 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1828 radeonfb_engine_init (rinfo);
1829 }
1830 /* Update fix */
1831 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1832 info->fix.line_length = rinfo->pitch*64;
1833 else
1834 info->fix.line_length = mode->xres_virtual
1835 * ((mode->bits_per_pixel + 1) / 8);
1836 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1837 : FB_VISUAL_DIRECTCOLOR;
1838
1839#ifdef CONFIG_BOOTX_TEXT
1840 /* Update debug text engine */
1841 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1842 rinfo->depth, info->fix.line_length);
1843#endif
1844
1845 kfree(newmode);
1846 return 0;
1847}
1848
1849
1850static struct fb_ops radeonfb_ops = {
1851 .owner = THIS_MODULE,
1852 .fb_check_var = radeonfb_check_var,
1853 .fb_set_par = radeonfb_set_par,
1854 .fb_setcolreg = radeonfb_setcolreg,
71494376 1855 .fb_setcmap = radeonfb_setcmap,
1da177e4
LT		 1856 .fb_pan_display = radeonfb_pan_display,
1857 .fb_blank = radeonfb_blank,
1858 .fb_ioctl = radeonfb_ioctl,
1859 .fb_sync = radeonfb_sync,
1860 .fb_fillrect = radeonfb_fillrect,
1861 .fb_copyarea = radeonfb_copyarea,
1862 .fb_imageblit = radeonfb_imageblit,
1da177e4
LT		 1863};
1864
1865
1866static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1867{
1868 struct fb_info *info = rinfo->info;
1869
1870 info->par = rinfo;
1871 info->pseudo_palette = rinfo->pseudo_palette;
1872 info->flags = FBINFO_DEFAULT
1873 | FBINFO_HWACCEL_COPYAREA
1874 | FBINFO_HWACCEL_FILLRECT
1875 | FBINFO_HWACCEL_XPAN
1876 | FBINFO_HWACCEL_YPAN;
1877 info->fbops = &radeonfb_ops;
1878 info->screen_base = rinfo->fb_base;
1879 info->screen_size = rinfo->mapped_vram;
1880 /* Fill fix common fields */
1881 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1882 info->fix.smem_start = rinfo->fb_base_phys;
1883 info->fix.smem_len = rinfo->video_ram;
1884 info->fix.type = FB_TYPE_PACKED_PIXELS;
1885 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1886 info->fix.xpanstep = 8;
1887 info->fix.ypanstep = 1;
1888 info->fix.ywrapstep = 0;
1889 info->fix.type_aux = 0;
1890 info->fix.mmio_start = rinfo->mmio_base_phys;
1891 info->fix.mmio_len = RADEON_REGSIZE;
1892 info->fix.accel = FB_ACCEL_ATI_RADEON;
1893
1894 fb_alloc_cmap(&info->cmap, 256, 0);
1895
1896 if (noaccel)
1897 info->flags |= FBINFO_HWACCEL_DISABLED;
1898
1899 return 0;
1900}
1901
1da177e4
LT		 1902/*
1903 * This reconfigure the card's internal memory map. In theory, we'd like
1904 * to setup the card's memory at the same address as it's PCI bus address,
1905 * and the AGP aperture right after that so that system RAM on 32 bits
1906 * machines at least, is directly accessible. However, doing so would
1907 * conflict with the current XFree drivers...
1908 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1909 * on the proper way to set this up and duplicate this here. In the meantime,
1910 * I put the card's memory at 0 in card space and AGP at some random high
1911 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1912 */
1913#ifdef CONFIG_PPC_OF
1914#undef SET_MC_FB_FROM_APERTURE
1915static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1916{
1917 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1918 u32 save_crtc_ext_cntl;
1919 u32 aper_base, aper_size;
1920 u32 agp_base;
1921
1922 /* First, we disable display to avoid interfering */
1923 if (rinfo->has_CRTC2) {
1924 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1925 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1926 }
1927 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1928 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1929
1930 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1931 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1932 mdelay(100);
1933
1934 aper_base = INREG(CONFIG_APER_0_BASE);
1935 aper_size = INREG(CONFIG_APER_SIZE);
1936
1937#ifdef SET_MC_FB_FROM_APERTURE
1938 /* Set framebuffer to be at the same address as set in PCI BAR */
1939 OUTREG(MC_FB_LOCATION,
1940 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1941 rinfo->fb_local_base = aper_base;
1942#else
1943 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1944 rinfo->fb_local_base = 0;
1945#endif
1946 agp_base = aper_base + aper_size;
1947 if (agp_base & 0xf0000000)
1948 agp_base = (aper_base | 0x0fffffff) + 1;
1949
1950 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1951 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1952 * always the case on PPCs afaik.
1953 */
1954#ifdef SET_MC_FB_FROM_APERTURE
1955 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1956#else
1957 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1958#endif
1959
1960 /* Fixup the display base addresses & engine offsets while we
1961 * are at it as well
1962 */
1963#ifdef SET_MC_FB_FROM_APERTURE
1964 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1965 if (rinfo->has_CRTC2)
1966 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1967 OUTREG(OV0_BASE_ADDR, aper_base);
1968#else
1969 OUTREG(DISPLAY_BASE_ADDR, 0);
1970 if (rinfo->has_CRTC2)
1971 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1972 OUTREG(OV0_BASE_ADDR, 0);
1973#endif
1974 mdelay(100);
1975
1976 /* Restore display settings */
1977 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1978 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1979 if (rinfo->has_CRTC2)
1980 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1981
1982 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1983 aper_base,
1984 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1985 0xffff0000 | (agp_base >> 16));
1986}
1987#endif /* CONFIG_PPC_OF */
1988
1989
1990static void radeon_identify_vram(struct radeonfb_info *rinfo)
1991{
1992 u32 tmp;
1993
1994 /* framebuffer size */
1995 if ((rinfo->family == CHIP_FAMILY_RS100) ||
1996 (rinfo->family == CHIP_FAMILY_RS200) ||
1997 (rinfo->family == CHIP_FAMILY_RS300)) {
1998 u32 tom = INREG(NB_TOM);
1999 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2000
2001 radeon_fifo_wait(6);
2002 OUTREG(MC_FB_LOCATION, tom);
2003 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2004 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2005 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2006
2007 /* This is supposed to fix the crtc2 noise problem. */
2008 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2009
2010 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2011 (rinfo->family == CHIP_FAMILY_RS200)) {
2012 /* This is to workaround the asic bug for RMX, some versions
2013 of BIOS dosen't have this register initialized correctly.
2014 */
2015 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2016 ~CRTC_H_CUTOFF_ACTIVE_EN);
2017 }
2018 } else {
2019 tmp = INREG(CONFIG_MEMSIZE);
2020 }
2021
2022 /* mem size is bits [28:0], mask off the rest */
2023 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2024
2025 /*
2026 * Hack to get around some busted production M6's
2027 * reporting no ram
2028 */
2029 if (rinfo->video_ram == 0) {
2030 switch (rinfo->pdev->device) {
2031 case PCI_CHIP_RADEON_LY:
2032 case PCI_CHIP_RADEON_LZ:
2033 rinfo->video_ram = 8192 * 1024;
2034 break;
2035 default:
2036 break;
2037 }
2038 }
2039
2040
2041 /*
2042 * Now try to identify VRAM type
2043 */
2044 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2045 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2046 rinfo->vram_ddr = 1;
2047 else
2048 rinfo->vram_ddr = 0;
2049
2050 tmp = INREG(MEM_CNTL);
2051 if (IS_R300_VARIANT(rinfo)) {
2052 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2053 switch (tmp) {
2054 case 0: rinfo->vram_width = 64; break;
2055 case 1: rinfo->vram_width = 128; break;
2056 case 2: rinfo->vram_width = 256; break;
2057 default: rinfo->vram_width = 128; break;
2058 }
2059 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2060 (rinfo->family == CHIP_FAMILY_RS100) ||
2061 (rinfo->family == CHIP_FAMILY_RS200)){
2062 if (tmp & RV100_MEM_HALF_MODE)
2063 rinfo->vram_width = 32;
2064 else
2065 rinfo->vram_width = 64;
2066 } else {
2067 if (tmp & MEM_NUM_CHANNELS_MASK)
2068 rinfo->vram_width = 128;
2069 else
2070 rinfo->vram_width = 64;
2071 }
2072
2073 /* This may not be correct, as some cards can have half of channel disabled
2074 * ToDo: identify these cases
2075 */
2076
2077 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2078 pci_name(rinfo->pdev),
2079 rinfo->video_ram / 1024,
2080 rinfo->vram_ddr ? "DDR" : "SDRAM",
2081 rinfo->vram_width);
2082}
2083
2084/*
2085 * Sysfs
2086 */
2087
2088static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2089{
2090 if (off > EDID_LENGTH)
2091 return 0;
2092
2093 if (off + count > EDID_LENGTH)
2094 count = EDID_LENGTH - off;
2095
2096 memcpy(buf, edid + off, count);
2097
2098 return count;
2099}
2100
2101
2102static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
2103{
2104 struct device *dev = container_of(kobj, struct device, kobj);
2105 struct pci_dev *pdev = to_pci_dev(dev);
2106 struct fb_info *info = pci_get_drvdata(pdev);
2107 struct radeonfb_info *rinfo = info->par;
2108
2109 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2110}
2111
2112
2113static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
2114{
2115 struct device *dev = container_of(kobj, struct device, kobj);
2116 struct pci_dev *pdev = to_pci_dev(dev);
2117 struct fb_info *info = pci_get_drvdata(pdev);
2118 struct radeonfb_info *rinfo = info->par;
2119
2120 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2121}
2122
2123static struct bin_attribute edid1_attr = {
2124 .attr = {
2125 .name = "edid1",
2126 .owner = THIS_MODULE,
2127 .mode = 0444,
2128 },
2129 .size = EDID_LENGTH,
2130 .read = radeon_show_edid1,
2131};
2132
2133static struct bin_attribute edid2_attr = {
2134 .attr = {
2135 .name = "edid2",
2136 .owner = THIS_MODULE,
2137 .mode = 0444,
2138 },
2139 .size = EDID_LENGTH,
2140 .read = radeon_show_edid2,
2141};
2142
2143
246846fc 2144static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
1da177e4
LT		 2145 const struct pci_device_id *ent)
2146{
2147 struct fb_info *info;
2148 struct radeonfb_info *rinfo;
2149 int ret;
2150
2151 RTRACE("radeonfb_pci_register BEGIN\n");
2152
2153 /* Enable device in PCI config */
2154 ret = pci_enable_device(pdev);
2155 if (ret < 0) {
2156 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2157 pci_name(pdev));
2158 goto err_out;
2159 }
2160
2161 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2162 if (!info) {
2163 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2164 pci_name(pdev));
2165 ret = -ENOMEM;
2166 goto err_disable;
2167 }
2168 rinfo = info->par;
2169 rinfo->info = info;
2170 rinfo->pdev = pdev;
2171
2172 spin_lock_init(&rinfo->reg_lock);
2173 init_timer(&rinfo->lvds_timer);
2174 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2175 rinfo->lvds_timer.data = (unsigned long)rinfo;
2176
2177 strcpy(rinfo->name, "ATI Radeon XX ");
2178 rinfo->name[11] = ent->device >> 8;
2179 rinfo->name[12] = ent->device & 0xFF;
2180 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2181 rinfo->chipset = pdev->device;
2182 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2183 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2184 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2185
2186 /* Set base addrs */
2187 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2188 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2189
2190 /* request the mem regions */
5251bffc 2191 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
1da177e4 2192 if (ret < 0) {
5251bffc
DB		 2193 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2194 pci_name(rinfo->pdev));
1da177e4
LT		 2195 goto err_release_fb;
2196 }
2197
5251bffc
DB		 2198 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2199 if (ret < 0) {
2200 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2201 pci_name(rinfo->pdev));
2202 goto err_release_pci0;
2203 }
2204
1da177e4
LT		 2205 /* map the regions */
2206 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2207 if (!rinfo->mmio_base) {
5251bffc
DB		 2208 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2209 pci_name(rinfo->pdev));
1da177e4 2210 ret = -EIO;
5251bffc 2211 goto err_release_pci2;
1da177e4
LT		 2212 }
2213
2214 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2215
2216 /*
2217 * Check for errata
2218 */
2219 rinfo->errata = 0;
2220 if (rinfo->family == CHIP_FAMILY_R300 &&
2221 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2222 == CFG_ATI_REV_A11)
2223 rinfo->errata |= CHIP_ERRATA_R300_CG;
2224
2225 if (rinfo->family == CHIP_FAMILY_RV200 ||
2226 rinfo->family == CHIP_FAMILY_RS200)
2227 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2228
2229 if (rinfo->family == CHIP_FAMILY_RV100 ||
2230 rinfo->family == CHIP_FAMILY_RS100 ||
2231 rinfo->family == CHIP_FAMILY_RS200)
2232 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2233
9f47df26 2234#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
1da177e4
LT		 2235 /* On PPC, we obtain the OF device-node pointer to the firmware
2236 * data for this chip
2237 */
2238 rinfo->of_node = pci_device_to_OF_node(pdev);
2239 if (rinfo->of_node == NULL)
2240 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2241 pci_name(rinfo->pdev));
2242
9f47df26
DM		 2243#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
2244#ifdef CONFIG_PPC_OF
1da177e4
LT		 2245 /* On PPC, the firmware sets up a memory mapping that tends
2246 * to cause lockups when enabling the engine. We reconfigure
2247 * the card internal memory mappings properly
2248 */
2249 fixup_memory_mappings(rinfo);
2250#endif /* CONFIG_PPC_OF */
2251
2252 /* Get VRAM size and type */
2253 radeon_identify_vram(rinfo);
2254
2255 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2256
2257 do {
2258 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2259 rinfo->mapped_vram);
2260 } while ( rinfo->fb_base == 0 &&
2261 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2262
8d5f7b43
BH		 2263 if (rinfo->fb_base == NULL) {
2264 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2265 pci_name(rinfo->pdev));
1da177e4
LT		 2266 ret = -EIO;
2267 goto err_unmap_rom;
2268 }
2269
2270 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2271 rinfo->mapped_vram/1024);
2272
2273 /*
4a4efbde 2274 * Map the BIOS ROM if any and retrieve PLL parameters from
1da177e4
LT		 2275 * the BIOS. We skip that on mobility chips as the real panel
2276 * values we need aren't in the ROM but in the BIOS image in
2277 * memory. This is definitely not the best meacnism though,
2278 * we really need the arch code to tell us which is the "primary"
2279 * video adapter to use the memory image (or better, the arch
2280 * should provide us a copy of the BIOS image to shield us from
2281 * archs who would store that elsewhere and/or could initialize
2282 * more than one adapter during boot).
2283 */
2284 if (!rinfo->is_mobility)
2285 radeon_map_ROM(rinfo, pdev);
2286
2287 /*
2288 * On x86, the primary display on laptop may have it's BIOS
2289 * ROM elsewhere, try to locate it at the legacy memory hole.
2290 * We probably need to make sure this is the primary display,
2291 * but that is difficult without some arch support.
2292 */
2293#ifdef CONFIG_X86
2294 if (rinfo->bios_seg == NULL)
2295 radeon_find_mem_vbios(rinfo);
2296#endif
2297
2298 /* If both above failed, try the BIOS ROM again for mobility
2299 * chips
2300 */
2301 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2302 radeon_map_ROM(rinfo, pdev);
2303
2304 /* Get informations about the board's PLL */
2305 radeon_get_pllinfo(rinfo);
2306
2307#ifdef CONFIG_FB_RADEON_I2C
2308 /* Register I2C bus */
2309 radeon_create_i2c_busses(rinfo);
2310#endif
2311
2312 /* set all the vital stuff */
2313 radeon_set_fbinfo (rinfo);
2314
2315 /* Probe screen types */
2316 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2317
2318 /* Build mode list, check out panel native model */
2319 radeon_check_modes(rinfo, mode_option);
2320
2321 /* Register some sysfs stuff (should be done better) */
2322 if (rinfo->mon1_EDID)
2323 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2324 if (rinfo->mon2_EDID)
2325 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2326
2327 /* save current mode regs before we switch into the new one
2328 * so we can restore this upon __exit
2329 */
2330 radeon_save_state (rinfo, &rinfo->init_state);
2331 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2332
2333 /* Setup Power Management capabilities */
2334 if (default_dynclk < -1) {
2335 /* -2 is special: means ON on mobility chips and do not
2336 * change on others
2337 */
994aad25 2338 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
1da177e4 2339 } else
994aad25 2340 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
1da177e4
LT		 2341
2342 pci_set_drvdata(pdev, info);
2343
2344 /* Register with fbdev layer */
2345 ret = register_framebuffer(info);
2346 if (ret < 0) {
2347 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2348 pci_name(rinfo->pdev));
2349 goto err_unmap_fb;
2350 }
2351
2352#ifdef CONFIG_MTRR
2353 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2354 rinfo->video_ram,
2355 MTRR_TYPE_WRCOMB, 1);
2356#endif
2357
202d4e60
RP		 2358 if (backlight)
2359 radeonfb_bl_init(rinfo);
1da177e4
LT		 2360
2361 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2362
2363 if (rinfo->bios_seg)
2364 radeon_unmap_ROM(rinfo, pdev);
2365 RTRACE("radeonfb_pci_register END\n");
2366
2367 return 0;
2368err_unmap_fb:
2369 iounmap(rinfo->fb_base);
2370err_unmap_rom:
2371 kfree(rinfo->mon1_EDID);
2372 kfree(rinfo->mon2_EDID);
2373 if (rinfo->mon1_modedb)
2374 fb_destroy_modedb(rinfo->mon1_modedb);
2375 fb_dealloc_cmap(&info->cmap);
2376#ifdef CONFIG_FB_RADEON_I2C
2377 radeon_delete_i2c_busses(rinfo);
2378#endif
2379 if (rinfo->bios_seg)
2380 radeon_unmap_ROM(rinfo, pdev);
2381 iounmap(rinfo->mmio_base);
5251bffc
DB		 2382err_release_pci2:
2383 pci_release_region(pdev, 2);
2384err_release_pci0:
2385 pci_release_region(pdev, 0);
1da177e4 2386err_release_fb:
5251bffc 2387 framebuffer_release(info);
1da177e4 2388err_disable:
1da177e4
LT		 2389err_out:
2390 return ret;
2391}
2392
2393
2394
2395static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2396{
2397 struct fb_info *info = pci_get_drvdata(pdev);
2398 struct radeonfb_info *rinfo = info->par;
2399
2400 if (!rinfo)
2401 return;
5474c120 2402
1da177e4
LT		 2403 radeonfb_pm_exit(rinfo);
2404
3ca34fcb
JS		 2405 if (rinfo->mon1_EDID)
2406 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2407 if (rinfo->mon2_EDID)
2408 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2409
1da177e4
LT		 2410#if 0
2411 /* restore original state
2412 *
2413 * Doesn't quite work yet, I suspect if we come from a legacy
2414 * VGA mode (or worse, text mode), we need to do some VGA black
2415 * magic here that I know nothing about. --BenH
2416 */
2417 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2418 #endif
2419
2420 del_timer_sync(&rinfo->lvds_timer);
2421
2422#ifdef CONFIG_MTRR
2423 if (rinfo->mtrr_hdl >= 0)
2424 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2425#endif
2426
2427 unregister_framebuffer(info);
2428
37ce69a5
RP		 2429 radeonfb_bl_exit(rinfo);
2430
1da177e4
LT		 2431 iounmap(rinfo->mmio_base);
2432 iounmap(rinfo->fb_base);
2433
5251bffc
DB		 2434 pci_release_region(pdev, 2);
2435 pci_release_region(pdev, 0);
1da177e4
LT		 2436
2437 kfree(rinfo->mon1_EDID);
2438 kfree(rinfo->mon2_EDID);
2439 if (rinfo->mon1_modedb)
2440 fb_destroy_modedb(rinfo->mon1_modedb);
2441#ifdef CONFIG_FB_RADEON_I2C
2442 radeon_delete_i2c_busses(rinfo);
2443#endif
2444 fb_dealloc_cmap(&info->cmap);
2445 framebuffer_release(info);
1da177e4
LT		 2446}
2447
2448
2449static struct pci_driver radeonfb_driver = {
2450 .name = "radeonfb",
2451 .id_table = radeonfb_pci_table,
2452 .probe = radeonfb_pci_register,
2453 .remove = __devexit_p(radeonfb_pci_unregister),
2454#ifdef CONFIG_PM
2455 .suspend = radeonfb_pci_suspend,
2456 .resume = radeonfb_pci_resume,
2457#endif /* CONFIG_PM */
2458};
2459
2460#ifndef MODULE
2461static int __init radeonfb_setup (char *options)
2462{
2463 char *this_opt;
2464
2465 if (!options || !*options)
2466 return 0;
2467
2468 while ((this_opt = strsep (&options, ",")) != NULL) {
2469 if (!*this_opt)
2470 continue;
2471
2472 if (!strncmp(this_opt, "noaccel", 7)) {
2473 noaccel = 1;
2474 } else if (!strncmp(this_opt, "mirror", 6)) {
2475 mirror = 1;
2476 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2477 force_dfp = 1;
2478 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2479 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
202d4e60
RP		 2480 } else if (!strncmp(this_opt, "backlight:", 10)) {
2481 backlight = simple_strtoul(this_opt+10, NULL, 0);
1da177e4
LT		 2482#ifdef CONFIG_MTRR
2483 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2484 nomtrr = 1;
2485#endif
2486 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2487 nomodeset = 1;
2488 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2489 force_measure_pll = 1;
2490 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2491 ignore_edid = 1;
994aad25
VB		 2492#if defined(CONFIG_PM) && defined(CONFIG_X86)
2493 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2494 force_sleep = 1;
2495 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2496 ignore_devlist = 1;
2497#endif
1da177e4
LT		 2498 } else
2499 mode_option = this_opt;
2500 }
2501 return 0;
2502}
2503#endif /* MODULE */
2504
2505static int __init radeonfb_init (void)
2506{
2507#ifndef MODULE
2508 char *option = NULL;
2509
2510 if (fb_get_options("radeonfb", &option))
2511 return -ENODEV;
2512 radeonfb_setup(option);
2513#endif
2514 return pci_register_driver (&radeonfb_driver);
2515}
2516
2517
2518static void __exit radeonfb_exit (void)
2519{
2520 pci_unregister_driver (&radeonfb_driver);
2521}
2522
2523module_init(radeonfb_init);
2524module_exit(radeonfb_exit);
2525
2526MODULE_AUTHOR("Ani Joshi");
2527MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2528MODULE_LICENSE("GPL");
2529module_param(noaccel, bool, 0);
2530module_param(default_dynclk, int, 0);
2531MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2532MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2533module_param(nomodeset, bool, 0);
2534MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2535module_param(mirror, bool, 0);
2536MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2537module_param(force_dfp, bool, 0);
2538MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2539module_param(ignore_edid, bool, 0);
2540MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2541module_param(monitor_layout, charp, 0);
2542MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2543module_param(force_measure_pll, bool, 0);
2544MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2545#ifdef CONFIG_MTRR
2546module_param(nomtrr, bool, 0);
2547MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2548#endif
2549module_param(panel_yres, int, 0);
2550MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2551module_param(mode_option, charp, 0);
2552MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
994aad25
VB		 2553#if defined(CONFIG_PM) && defined(CONFIG_X86)
2554module_param(force_sleep, bool, 0);
2555MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2556module_param(ignore_devlist, bool, 0);
2557MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2558#endif
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