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[SPARC64]: Fix several bugs in flush_ptrace_access().
[mirror_ubuntu-jammy-kernel.git] / drivers / video / aty / radeon_base.c
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1da177e4
LT		 1/*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53#define RADEON_VERSION "0.2.0"
54
55#include <linux/config.h>
56#include <linux/module.h>
57#include <linux/moduleparam.h>
58#include <linux/kernel.h>
59#include <linux/errno.h>
60#include <linux/string.h>
61#include <linux/mm.h>
62#include <linux/tty.h>
63#include <linux/slab.h>
64#include <linux/delay.h>
65#include <linux/time.h>
66#include <linux/fb.h>
67#include <linux/ioport.h>
68#include <linux/init.h>
69#include <linux/pci.h>
70#include <linux/vmalloc.h>
71#include <linux/device.h>
72#include <linux/i2c.h>
73
74#include <asm/io.h>
75#include <asm/uaccess.h>
76
77#ifdef CONFIG_PPC_OF
78
79#include <asm/pci-bridge.h>
80#include "../macmodes.h"
81
82#ifdef CONFIG_PMAC_BACKLIGHT
83#include <asm/backlight.h>
84#endif
85
86#ifdef CONFIG_BOOTX_TEXT
87#include <asm/btext.h>
88#endif
89
90#endif /* CONFIG_PPC_OF */
91
92#ifdef CONFIG_MTRR
93#include <asm/mtrr.h>
94#endif
95
96#include <video/radeon.h>
97#include <linux/radeonfb.h>
98
99#include "../edid.h" // MOVE THAT TO include/video
100#include "ati_ids.h"
101#include "radeonfb.h"
102
103#define MAX_MAPPED_VRAM (2048*2048*4)
104#define MIN_MAPPED_VRAM (1024*768*1)
105
106#define CHIP_DEF(id, family, flags) \
107 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
108
109static struct pci_device_id radeonfb_pci_table[] = {
110 /* Mobility M6 */
111 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
112 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
113 /* Radeon VE/7000 */
114 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
115 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
116 /* Radeon IGP320M (U1) */
117 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
118 /* Radeon IGP320 (A3) */
119 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
120 /* IGP330M/340M/350M (U2) */
121 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
122 /* IGP330/340/350 (A4) */
123 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
124 /* Mobility 7000 IGP */
125 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
126 /* 7000 IGP (A4+) */
127 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
128 /* 8500 AIW */
129 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
130 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
131 /* 8700/8800 */
132 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
133 /* 8500 */
134 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
135 /* 9100 */
136 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
137 /* Mobility M7 */
138 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 /* 7500 */
141 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
142 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
143 /* Mobility M9 */
144 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
146 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
147 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
148 /* 9000/Pro */
149 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
150 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
151 /* Mobility 9100 IGP (U3) */
152 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
153 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
154 /* 9100 IGP (A5) */
155 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
156 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
157 /* Mobility 9200 (M9+) */
158 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
159 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
160 /* 9200 */
161 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
162 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
165 /* 9500 */
166 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
167 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
168 /* 9600TX / FireGL Z1 */
169 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
170 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
171 /* 9700/9500/Pro/FireGL X1 */
172 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
173 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
174 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
175 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
176 /* Mobility M10/M11 */
177 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
183 /* 9600/FireGL T2 */
184 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
185 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
190 /* 9800/Pro/FileGL X2 */
191 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
199 /* Newer stuff */
200 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
203 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
205 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
209 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
210 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
211 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
217 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
224 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
225 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
226 /* Original Radeon/7200 */
227 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
228 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
229 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
230 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
231 { 0, }
232};
233MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
234
235
236typedef struct {
237 u16 reg;
238 u32 val;
239} reg_val;
240
241
242/* these common regs are cleared before mode setting so they do not
243 * interfere with anything
244 */
245static reg_val common_regs[] = {
246 { OVR_CLR, 0 },
247 { OVR_WID_LEFT_RIGHT, 0 },
248 { OVR_WID_TOP_BOTTOM, 0 },
249 { OV0_SCALE_CNTL, 0 },
250 { SUBPIC_CNTL, 0 },
251 { VIPH_CONTROL, 0 },
252 { I2C_CNTL_1, 0 },
253 { GEN_INT_CNTL, 0 },
254 { CAP0_TRIG_CNTL, 0 },
255 { CAP1_TRIG_CNTL, 0 },
256};
257
258/*
259 * globals
260 */
261
262static char *mode_option;
263static char *monitor_layout;
264static int noaccel = 0;
265static int default_dynclk = -2;
266static int nomodeset = 0;
267static int ignore_edid = 0;
268static int mirror = 0;
269static int panel_yres = 0;
270static int force_dfp = 0;
271static int force_measure_pll = 0;
272#ifdef CONFIG_MTRR
273static int nomtrr = 0;
274#endif
275
276/*
277 * prototypes
278 */
279
280
281#ifdef CONFIG_PPC_OF
282
283#ifdef CONFIG_PMAC_BACKLIGHT
284static int radeon_set_backlight_enable(int on, int level, void *data);
285static int radeon_set_backlight_level(int level, void *data);
286static struct backlight_controller radeon_backlight_controller = {
287 radeon_set_backlight_enable,
288 radeon_set_backlight_level
289};
290#endif /* CONFIG_PMAC_BACKLIGHT */
291
292#endif /* CONFIG_PPC_OF */
293
294static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
295{
296 if (!rinfo->bios_seg)
297 return;
298 pci_unmap_rom(dev, rinfo->bios_seg);
299}
300
301static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
302{
303 void __iomem *rom;
304 u16 dptr;
305 u8 rom_type;
306 size_t rom_size;
307
308 /* If this is a primary card, there is a shadow copy of the
309 * ROM somewhere in the first meg. We will just ignore the copy
310 * and use the ROM directly.
311 */
312
313 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
314 unsigned int temp;
315 temp = INREG(MPP_TB_CONFIG);
316 temp &= 0x00ffffffu;
317 temp |= 0x04 << 24;
318 OUTREG(MPP_TB_CONFIG, temp);
319 temp = INREG(MPP_TB_CONFIG);
320
321 rom = pci_map_rom(dev, &rom_size);
322 if (!rom) {
323 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
324 pci_name(rinfo->pdev));
325 return -ENOMEM;
326 }
327
328 rinfo->bios_seg = rom;
329
330 /* Very simple test to make sure it appeared */
331 if (BIOS_IN16(0) != 0xaa55) {
3b4abffb
OH		 332 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
333 "should be 0xaa55\n",
334 pci_name(rinfo->pdev), BIOS_IN16(0));
1da177e4
LT		 335 goto failed;
336 }
337 /* Look for the PCI data to check the ROM type */
338 dptr = BIOS_IN16(0x18);
339
340 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
341 * for now, until I've verified this works everywhere. The goal here is more
342 * to phase out Open Firmware images.
343 *
344 * Currently, we only look at the first PCI data, we could iteratre and deal with
345 * them all, and we should use fb_bios_start relative to start of image and not
346 * relative start of ROM, but so far, I never found a dual-image ATI card
347 *
348 * typedef struct {
349 * u32 signature; + 0x00
350 * u16 vendor; + 0x04
351 * u16 device; + 0x06
352 * u16 reserved_1; + 0x08
353 * u16 dlen; + 0x0a
354 * u8 drevision; + 0x0c
355 * u8 class_hi; + 0x0d
356 * u16 class_lo; + 0x0e
357 * u16 ilen; + 0x10
358 * u16 irevision; + 0x12
359 * u8 type; + 0x14
360 * u8 indicator; + 0x15
361 * u16 reserved_2; + 0x16
362 * } pci_data_t;
363 */
364 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
365 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
366 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
367 goto anyway;
368 }
369 rom_type = BIOS_IN8(dptr + 0x14);
370 switch(rom_type) {
371 case 0:
372 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
373 break;
374 case 1:
375 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
376 goto failed;
377 case 2:
378 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
379 goto failed;
380 default:
381 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
382 goto failed;
383 }
384 anyway:
385 /* Locate the flat panel infos, do some sanity checking !!! */
386 rinfo->fp_bios_start = BIOS_IN16(0x48);
387 return 0;
388
389 failed:
390 rinfo->bios_seg = NULL;
391 radeon_unmap_ROM(rinfo, dev);
392 return -ENXIO;
393}
394
395#ifdef CONFIG_X86
396static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
397{
398 /* I simplified this code as we used to miss the signatures in
399 * a lot of case. It's now closer to XFree, we just don't check
400 * for signatures at all... Something better will have to be done
401 * if we end up having conflicts
402 */
403 u32 segstart;
404 void __iomem *rom_base = NULL;
405
406 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
407 rom_base = ioremap(segstart, 0x10000);
408 if (rom_base == NULL)
409 return -ENOMEM;
410 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
411 break;
412 iounmap(rom_base);
413 rom_base = NULL;
414 }
415 if (rom_base == NULL)
416 return -ENXIO;
417
418 /* Locate the flat panel infos, do some sanity checking !!! */
419 rinfo->bios_seg = rom_base;
420 rinfo->fp_bios_start = BIOS_IN16(0x48);
421
422 return 0;
423}
424#endif
425
426#ifdef CONFIG_PPC_OF
427/*
428 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
429 * tree. Hopefully, ATI OF driver is kind enough to fill these
430 */
431static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
432{
433 struct device_node *dp = rinfo->of_node;
434 u32 *val;
435
436 if (dp == NULL)
437 return -ENODEV;
438 val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);
439 if (!val || !*val) {
440 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
441 return -EINVAL;
442 }
443
444 rinfo->pll.ref_clk = (*val) / 10;
445
446 val = (u32 *) get_property(dp, "ATY,SCLK", NULL);
447 if (val && *val)
448 rinfo->pll.sclk = (*val) / 10;
449
450 val = (u32 *) get_property(dp, "ATY,MCLK", NULL);
451 if (val && *val)
452 rinfo->pll.mclk = (*val) / 10;
453
454 return 0;
455}
456#endif /* CONFIG_PPC_OF */
457
458/*
459 * Read PLL infos from chip registers
460 */
461static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
462{
463 unsigned char ppll_div_sel;
464 unsigned Ns, Nm, M;
465 unsigned sclk, mclk, tmp, ref_div;
466 int hTotal, vTotal, num, denom, m, n;
467 unsigned long long hz, vclk;
468 long xtal;
469 struct timeval start_tv, stop_tv;
470 long total_secs, total_usecs;
471 int i;
472
473 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
474 * here, so... --BenH
475 */
476
477 /* Flush PCI buffers ? */
478 tmp = INREG(DEVICE_ID);
479
480 local_irq_disable();
481
482 for(i=0; i<1000000; i++)
483 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
484 break;
485
486 do_gettimeofday(&start_tv);
487
488 for(i=0; i<1000000; i++)
489 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
490 break;
491
492 for(i=0; i<1000000; i++)
493 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
494 break;
495
496 do_gettimeofday(&stop_tv);
497
498 local_irq_enable();
499
500 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
501 if (total_secs > 10)
502 return -1;
503 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
504 total_usecs += total_secs * 1000000;
505 if (total_usecs < 0)
506 total_usecs = -total_usecs;
507 hz = 1000000/total_usecs;
508
509 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
510 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
511 vclk = (long long)hTotal * (long long)vTotal * hz;
512
513 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
514 case 0:
515 default:
516 num = 1;
517 denom = 1;
518 break;
519 case 1:
520 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
521 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
522 num = 2*n;
523 denom = 2*m;
524 break;
525 case 2:
526 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
527 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
528 num = 2*n;
529 denom = 2*m;
530 break;
531 }
532
533 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
534 radeon_pll_errata_after_index(rinfo);
535
536 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
537 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
538
539 num *= n;
540 denom *= m;
541
542 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
543 case 1:
544 denom *= 2;
545 break;
546 case 2:
547 denom *= 4;
548 break;
549 case 3:
550 denom *= 8;
551 break;
552 case 4:
553 denom *= 3;
554 break;
555 case 6:
556 denom *= 6;
557 break;
558 case 7:
559 denom *= 12;
560 break;
561 }
562
563 vclk *= denom;
564 do_div(vclk, 1000 * num);
565 xtal = vclk;
566
567 if ((xtal > 26900) && (xtal < 27100))
568 xtal = 2700;
569 else if ((xtal > 14200) && (xtal < 14400))
570 xtal = 1432;
571 else if ((xtal > 29400) && (xtal < 29600))
572 xtal = 2950;
573 else {
574 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
575 return -1;
576 }
577
578 tmp = INPLL(M_SPLL_REF_FB_DIV);
579 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
580
581 Ns = (tmp & 0xff0000) >> 16;
582 Nm = (tmp & 0xff00) >> 8;
583 M = (tmp & 0xff);
584 sclk = round_div((2 * Ns * xtal), (2 * M));
585 mclk = round_div((2 * Nm * xtal), (2 * M));
586
587 /* we're done, hopefully these are sane values */
588 rinfo->pll.ref_clk = xtal;
589 rinfo->pll.ref_div = ref_div;
590 rinfo->pll.sclk = sclk;
591 rinfo->pll.mclk = mclk;
592
593 return 0;
594}
595
596/*
597 * Retreive PLL infos by different means (BIOS, Open Firmware, register probing...)
598 */
599static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
600{
601 /*
602 * In the case nothing works, these are defaults; they are mostly
603 * incomplete, however. It does provide ppll_max and _min values
604 * even for most other methods, however.
605 */
606 switch (rinfo->chipset) {
607 case PCI_DEVICE_ID_ATI_RADEON_QW:
608 case PCI_DEVICE_ID_ATI_RADEON_QX:
609 rinfo->pll.ppll_max = 35000;
610 rinfo->pll.ppll_min = 12000;
611 rinfo->pll.mclk = 23000;
612 rinfo->pll.sclk = 23000;
613 rinfo->pll.ref_clk = 2700;
614 break;
615 case PCI_DEVICE_ID_ATI_RADEON_QL:
616 case PCI_DEVICE_ID_ATI_RADEON_QN:
617 case PCI_DEVICE_ID_ATI_RADEON_QO:
618 case PCI_DEVICE_ID_ATI_RADEON_Ql:
619 case PCI_DEVICE_ID_ATI_RADEON_BB:
620 rinfo->pll.ppll_max = 35000;
621 rinfo->pll.ppll_min = 12000;
622 rinfo->pll.mclk = 27500;
623 rinfo->pll.sclk = 27500;
624 rinfo->pll.ref_clk = 2700;
625 break;
626 case PCI_DEVICE_ID_ATI_RADEON_Id:
627 case PCI_DEVICE_ID_ATI_RADEON_Ie:
628 case PCI_DEVICE_ID_ATI_RADEON_If:
629 case PCI_DEVICE_ID_ATI_RADEON_Ig:
630 rinfo->pll.ppll_max = 35000;
631 rinfo->pll.ppll_min = 12000;
632 rinfo->pll.mclk = 25000;
633 rinfo->pll.sclk = 25000;
634 rinfo->pll.ref_clk = 2700;
635 break;
636 case PCI_DEVICE_ID_ATI_RADEON_ND:
637 case PCI_DEVICE_ID_ATI_RADEON_NE:
638 case PCI_DEVICE_ID_ATI_RADEON_NF:
639 case PCI_DEVICE_ID_ATI_RADEON_NG:
640 rinfo->pll.ppll_max = 40000;
641 rinfo->pll.ppll_min = 20000;
642 rinfo->pll.mclk = 27000;
643 rinfo->pll.sclk = 27000;
644 rinfo->pll.ref_clk = 2700;
645 break;
646 case PCI_DEVICE_ID_ATI_RADEON_QD:
647 case PCI_DEVICE_ID_ATI_RADEON_QE:
648 case PCI_DEVICE_ID_ATI_RADEON_QF:
649 case PCI_DEVICE_ID_ATI_RADEON_QG:
650 default:
651 rinfo->pll.ppll_max = 35000;
652 rinfo->pll.ppll_min = 12000;
653 rinfo->pll.mclk = 16600;
654 rinfo->pll.sclk = 16600;
655 rinfo->pll.ref_clk = 2700;
656 break;
657 }
658 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
659
660
661#ifdef CONFIG_PPC_OF
662 /*
663 * Retreive PLL infos from Open Firmware first
664 */
665 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
666 printk(KERN_INFO "radeonfb: Retreived PLL infos from Open Firmware\n");
667 goto found;
668 }
669#endif /* CONFIG_PPC_OF */
670
671 /*
672 * Check out if we have an X86 which gave us some PLL informations
673 * and if yes, retreive them
674 */
675 if (!force_measure_pll && rinfo->bios_seg) {
676 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
677
678 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
679 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
680 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
681 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
682 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
683 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
684
685 printk(KERN_INFO "radeonfb: Retreived PLL infos from BIOS\n");
686 goto found;
687 }
688
689 /*
690 * We didn't get PLL parameters from either OF or BIOS, we try to
691 * probe them
692 */
693 if (radeon_probe_pll_params(rinfo) == 0) {
694 printk(KERN_INFO "radeonfb: Retreived PLL infos from registers\n");
695 goto found;
696 }
697
698 /*
699 * Fall back to already-set defaults...
700 */
701 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
702
703found:
704 /*
705 * Some methods fail to retreive SCLK and MCLK values, we apply default
706 * settings in this case (200Mhz). If that really happne often, we could
707 * fetch from registers instead...
708 */
709 if (rinfo->pll.mclk == 0)
710 rinfo->pll.mclk = 20000;
711 if (rinfo->pll.sclk == 0)
712 rinfo->pll.sclk = 20000;
713
714 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
715 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
716 rinfo->pll.ref_div,
717 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
718 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
719 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
720}
721
722static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
723{
724 struct radeonfb_info *rinfo = info->par;
725 struct fb_var_screeninfo v;
726 int nom, den;
727 unsigned int pitch;
728
729 if (radeon_match_mode(rinfo, &v, var))
730 return -EINVAL;
731
732 switch (v.bits_per_pixel) {
733 case 0 ... 8:
734 v.bits_per_pixel = 8;
735 break;
736 case 9 ... 16:
737 v.bits_per_pixel = 16;
738 break;
739 case 17 ... 24:
740#if 0 /* Doesn't seem to work */
741 v.bits_per_pixel = 24;
742 break;
743#endif
744 return -EINVAL;
745 case 25 ... 32:
746 v.bits_per_pixel = 32;
747 break;
748 default:
749 return -EINVAL;
750 }
751
752 switch (var_to_depth(&v)) {
753 case 8:
754 nom = den = 1;
755 v.red.offset = v.green.offset = v.blue.offset = 0;
756 v.red.length = v.green.length = v.blue.length = 8;
757 v.transp.offset = v.transp.length = 0;
758 break;
759 case 15:
760 nom = 2;
761 den = 1;
762 v.red.offset = 10;
763 v.green.offset = 5;
764 v.blue.offset = 0;
765 v.red.length = v.green.length = v.blue.length = 5;
766 v.transp.offset = v.transp.length = 0;
767 break;
768 case 16:
769 nom = 2;
770 den = 1;
771 v.red.offset = 11;
772 v.green.offset = 5;
773 v.blue.offset = 0;
774 v.red.length = 5;
775 v.green.length = 6;
776 v.blue.length = 5;
777 v.transp.offset = v.transp.length = 0;
778 break;
779 case 24:
780 nom = 4;
781 den = 1;
782 v.red.offset = 16;
783 v.green.offset = 8;
784 v.blue.offset = 0;
785 v.red.length = v.blue.length = v.green.length = 8;
786 v.transp.offset = v.transp.length = 0;
787 break;
788 case 32:
789 nom = 4;
790 den = 1;
791 v.red.offset = 16;
792 v.green.offset = 8;
793 v.blue.offset = 0;
794 v.red.length = v.blue.length = v.green.length = 8;
795 v.transp.offset = 24;
796 v.transp.length = 8;
797 break;
798 default:
799 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
800 var->xres, var->yres, var->bits_per_pixel);
801 return -EINVAL;
802 }
803
804 if (v.yres_virtual < v.yres)
805 v.yres_virtual = v.yres;
806 if (v.xres_virtual < v.xres)
807 v.xres_virtual = v.xres;
808
809
810 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
811 * with some panels, though I don't quite like this solution
812 */
813 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
814 v.xres_virtual = v.xres_virtual & ~7ul;
815 } else {
816 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
817 & ~(0x3f)) >> 6;
818 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
819 }
820
821 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
822 return -EINVAL;
823
824 if (v.xres_virtual < v.xres)
825 v.xres = v.xres_virtual;
826
827 if (v.xoffset < 0)
828 v.xoffset = 0;
829 if (v.yoffset < 0)
830 v.yoffset = 0;
831
832 if (v.xoffset > v.xres_virtual - v.xres)
833 v.xoffset = v.xres_virtual - v.xres - 1;
834
835 if (v.yoffset > v.yres_virtual - v.yres)
836 v.yoffset = v.yres_virtual - v.yres - 1;
837
838 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
839 v.transp.offset = v.transp.length =
840 v.transp.msb_right = 0;
841
842 memcpy(var, &v, sizeof(v));
843
844 return 0;
845}
846
847
848static int radeonfb_pan_display (struct fb_var_screeninfo *var,
849 struct fb_info *info)
850{
851 struct radeonfb_info *rinfo = info->par;
852
853 if ((var->xoffset + var->xres > var->xres_virtual)
854 || (var->yoffset + var->yres > var->yres_virtual))
855 return -EINVAL;
856
857 if (rinfo->asleep)
858 return 0;
859
860 radeon_fifo_wait(2);
861 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
862 * var->bits_per_pixel / 8) & ~7);
863 return 0;
864}
865
866
867static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
868 unsigned long arg, struct fb_info *info)
869{
870 struct radeonfb_info *rinfo = info->par;
871 unsigned int tmp;
872 u32 value = 0;
873 int rc;
874
875 switch (cmd) {
876 /*
877 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
878 * and do something better using 2nd CRTC instead of just hackish
879 * routing to second output
880 */
881 case FBIO_RADEON_SET_MIRROR:
882 if (!rinfo->is_mobility)
883 return -EINVAL;
884
885 rc = get_user(value, (__u32 __user *)arg);
886
887 if (rc)
888 return rc;
889
890 radeon_fifo_wait(2);
891 if (value & 0x01) {
892 tmp = INREG(LVDS_GEN_CNTL);
893
894 tmp |= (LVDS_ON | LVDS_BLON);
895 } else {
896 tmp = INREG(LVDS_GEN_CNTL);
897
898 tmp &= ~(LVDS_ON | LVDS_BLON);
899 }
900
901 OUTREG(LVDS_GEN_CNTL, tmp);
902
903 if (value & 0x02) {
904 tmp = INREG(CRTC_EXT_CNTL);
905 tmp |= CRTC_CRT_ON;
906
907 mirror = 1;
908 } else {
909 tmp = INREG(CRTC_EXT_CNTL);
910 tmp &= ~CRTC_CRT_ON;
911
912 mirror = 0;
913 }
914
915 OUTREG(CRTC_EXT_CNTL, tmp);
916
917 return 0;
918 case FBIO_RADEON_GET_MIRROR:
919 if (!rinfo->is_mobility)
920 return -EINVAL;
921
922 tmp = INREG(LVDS_GEN_CNTL);
923 if ((LVDS_ON | LVDS_BLON) & tmp)
924 value |= 0x01;
925
926 tmp = INREG(CRTC_EXT_CNTL);
927 if (CRTC_CRT_ON & tmp)
928 value |= 0x02;
929
930 return put_user(value, (__u32 __user *)arg);
931 default:
932 return -EINVAL;
933 }
934
935 return -EINVAL;
936}
937
938
939int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
940{
941 u32 val;
942 u32 tmp_pix_clks;
943 int unblank = 0;
944
945 if (rinfo->lock_blank)
946 return 0;
947
948 radeon_engine_idle();
949
950 val = INREG(CRTC_EXT_CNTL);
951 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
952 CRTC_VSYNC_DIS);
953 switch (blank) {
954 case FB_BLANK_VSYNC_SUSPEND:
955 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
956 break;
957 case FB_BLANK_HSYNC_SUSPEND:
958 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
959 break;
960 case FB_BLANK_POWERDOWN:
961 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
962 CRTC_HSYNC_DIS);
963 break;
964 case FB_BLANK_NORMAL:
965 val |= CRTC_DISPLAY_DIS;
966 break;
967 case FB_BLANK_UNBLANK:
968 default:
969 unblank = 1;
970 }
971 OUTREG(CRTC_EXT_CNTL, val);
972
973
974 switch (rinfo->mon1_type) {
975 case MT_DFP:
976 if (unblank)
977 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
978 ~(FP_FPON | FP_TMDS_EN));
979 else {
980 if (mode_switch || blank == FB_BLANK_NORMAL)
981 break;
982 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
983 }
984 break;
985 case MT_LCD:
986 del_timer_sync(&rinfo->lvds_timer);
987 val = INREG(LVDS_GEN_CNTL);
988 if (unblank) {
989 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
990 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
991 & (LVDS_DIGON | LVDS_BL_MOD_EN));
992 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
993 OUTREG(LVDS_GEN_CNTL, target_val);
994 else if ((val ^ target_val) != 0) {
995 OUTREG(LVDS_GEN_CNTL, target_val
996 & ~(LVDS_ON | LVDS_BL_MOD_EN));
997 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
998 rinfo->init_state.lvds_gen_cntl |=
999 target_val & LVDS_STATE_MASK;
1000 if (mode_switch) {
1001 radeon_msleep(rinfo->panel_info.pwr_delay);
1002 OUTREG(LVDS_GEN_CNTL, target_val);
1003 }
1004 else {
1005 rinfo->pending_lvds_gen_cntl = target_val;
1006 mod_timer(&rinfo->lvds_timer,
1007 jiffies +
1008 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1009 }
1010 }
1011 } else {
1012 val |= LVDS_DISPLAY_DIS;
1013 OUTREG(LVDS_GEN_CNTL, val);
1014
1015 /* We don't do a full switch-off on a simple mode switch */
1016 if (mode_switch || blank == FB_BLANK_NORMAL)
1017 break;
1018
1019 /* Asic bug, when turning off LVDS_ON, we have to make sure
1020 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1021 */
1022 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1023 if (rinfo->is_mobility || rinfo->is_IGP)
1024 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1025 val &= ~(LVDS_BL_MOD_EN);
1026 OUTREG(LVDS_GEN_CNTL, val);
1027 udelay(100);
1028 val &= ~(LVDS_ON | LVDS_EN);
1029 OUTREG(LVDS_GEN_CNTL, val);
1030 val &= ~LVDS_DIGON;
1031 rinfo->pending_lvds_gen_cntl = val;
1032 mod_timer(&rinfo->lvds_timer,
1033 jiffies +
1034 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1035 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1036 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1037 if (rinfo->is_mobility || rinfo->is_IGP)
1038 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1039 }
1040 break;
1041 case MT_CRT:
1042 // todo: powerdown DAC
1043 default:
1044 break;
1045 }
1046
1047 /* let fbcon do a soft blank for us */
1048 return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0;
1049}
1050
1051static int radeonfb_blank (int blank, struct fb_info *info)
1052{
1053 struct radeonfb_info *rinfo = info->par;
1054
1055 if (rinfo->asleep)
1056 return 0;
1057
1058 return radeon_screen_blank(rinfo, blank, 0);
1059}
1060
71494376
BH		 1061static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1062 unsigned blue, unsigned transp,
1063 struct radeonfb_info *rinfo)
1da177e4 1064{
1da177e4
LT		 1065 u32 pindex;
1066 unsigned int i;
71494376
BH		 1067
1068
1da177e4
LT		 1069 if (regno > 255)
1070 return 1;
1071
1072 red >>= 8;
1073 green >>= 8;
1074 blue >>= 8;
1075 rinfo->palette[regno].red = red;
1076 rinfo->palette[regno].green = green;
1077 rinfo->palette[regno].blue = blue;
1078
1079 /* default */
1080 pindex = regno;
1081
1082 if (!rinfo->asleep) {
1da177e4 1083 radeon_fifo_wait(9);
1da177e4
LT		 1084
1085 if (rinfo->bpp == 16) {
1086 pindex = regno * 8;
1087
1088 if (rinfo->depth == 16 && regno > 63)
1089 return 1;
1090 if (rinfo->depth == 15 && regno > 31)
1091 return 1;
1092
71494376
BH		 1093 /* For 565, the green component is mixed one order
1094 * below
1095 */
1da177e4
LT		 1096 if (rinfo->depth == 16) {
1097 OUTREG(PALETTE_INDEX, pindex>>1);
71494376
BH		 1098 OUTREG(PALETTE_DATA,
1099 (rinfo->palette[regno>>1].red << 16) |
1100 (green << 8) |
1101 (rinfo->palette[regno>>1].blue));
1da177e4
LT		 1102 green = rinfo->palette[regno<<1].green;
1103 }
1104 }
1105
1106 if (rinfo->depth != 16 || regno < 32) {
1107 OUTREG(PALETTE_INDEX, pindex);
71494376
BH		 1108 OUTREG(PALETTE_DATA, (red << 16) |
1109 (green << 8) | blue);
1da177e4 1110 }
1da177e4
LT		 1111 }
1112 if (regno < 16) {
71494376 1113 u32 *pal = rinfo->info->pseudo_palette;
1da177e4
LT		 1114 switch (rinfo->depth) {
1115 case 15:
1116 pal[regno] = (regno << 10) | (regno << 5) | regno;
1117 break;
1118 case 16:
1119 pal[regno] = (regno << 11) | (regno << 5) | regno;
1120 break;
1121 case 24:
1122 pal[regno] = (regno << 16) | (regno << 8) | regno;
1123 break;
1124 case 32:
1125 i = (regno << 8) | regno;
1126 pal[regno] = (i << 16) | i;
1127 break;
1128 }
1129 }
1130 return 0;
1131}
1132
71494376
BH		 1133static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1134 unsigned blue, unsigned transp,
1135 struct fb_info *info)
1136{
1137 struct radeonfb_info *rinfo = info->par;
1138 u32 dac_cntl2, vclk_cntl = 0;
1139 int rc;
1140
1141 if (!rinfo->asleep) {
1142 if (rinfo->is_mobility) {
1143 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1144 OUTPLL(VCLK_ECP_CNTL,
1145 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1146 }
1147
1148 /* Make sure we are on first palette */
1149 if (rinfo->has_CRTC2) {
1150 dac_cntl2 = INREG(DAC_CNTL2);
1151 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1152 OUTREG(DAC_CNTL2, dac_cntl2);
1153 }
1154 }
1155
1156 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1157
1158 if (!rinfo->asleep && rinfo->is_mobility)
1159 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1160
1161 return rc;
1162}
1163
1164static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1165{
1166 struct radeonfb_info *rinfo = info->par;
1167 u16 *red, *green, *blue, *transp;
1168 u32 dac_cntl2, vclk_cntl = 0;
1169 int i, start, rc = 0;
1170
1171 if (!rinfo->asleep) {
1172 if (rinfo->is_mobility) {
1173 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1174 OUTPLL(VCLK_ECP_CNTL,
1175 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1176 }
1177
1178 /* Make sure we are on first palette */
1179 if (rinfo->has_CRTC2) {
1180 dac_cntl2 = INREG(DAC_CNTL2);
1181 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1182 OUTREG(DAC_CNTL2, dac_cntl2);
1183 }
1184 }
1185
1186 red = cmap->red;
1187 green = cmap->green;
1188 blue = cmap->blue;
1189 transp = cmap->transp;
1190 start = cmap->start;
1191
1192 for (i = 0; i < cmap->len; i++) {
1193 u_int hred, hgreen, hblue, htransp = 0xffff;
1194
1195 hred = *red++;
1196 hgreen = *green++;
1197 hblue = *blue++;
1198 if (transp)
1199 htransp = *transp++;
1200 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1201 rinfo);
1202 if (rc)
1203 break;
1204 }
1205
1206 if (!rinfo->asleep && rinfo->is_mobility)
1207 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1208
1209 return rc;
1210}
1da177e4
LT		 1211
1212static void radeon_save_state (struct radeonfb_info *rinfo,
1213 struct radeon_regs *save)
1214{
1215 /* CRTC regs */
1216 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1217 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1218 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1219 save->dac_cntl = INREG(DAC_CNTL);
1220 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1221 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1222 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1223 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1224 save->crtc_pitch = INREG(CRTC_PITCH);
1225 save->surface_cntl = INREG(SURFACE_CNTL);
1226
1227 /* FP regs */
1228 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1229 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1230 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1231 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1232 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1233 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1234 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1235 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1236 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1237 save->tmds_crc = INREG(TMDS_CRC);
1238 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1239 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1240
1241 /* PLL regs */
1242 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1243 radeon_pll_errata_after_index(rinfo);
1244 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1245 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1246}
1247
1248
1249static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1250{
1251 int i;
1252
1253 radeon_fifo_wait(20);
1254
1255 /* Workaround from XFree */
1256 if (rinfo->is_mobility) {
1257 /* A temporal workaround for the occational blanking on certain laptop
1258 * panels. This appears to related to the PLL divider registers
1259 * (fail to lock?). It occurs even when all dividers are the same
1260 * with their old settings. In this case we really don't need to
1261 * fiddle with PLL registers. By doing this we can avoid the blanking
1262 * problem with some panels.
1263 */
1264 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1265 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1266 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1267 /* We still have to force a switch to selected PPLL div thanks to
1268 * an XFree86 driver bug which will switch it away in some cases
1269 * even when using UseFDev */
1270 OUTREGP(CLOCK_CNTL_INDEX,
1271 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1272 ~PPLL_DIV_SEL_MASK);
1273 radeon_pll_errata_after_index(rinfo);
1274 radeon_pll_errata_after_data(rinfo);
1275 return;
1276 }
1277 }
1278
1279 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1280 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1281
1282 /* Reset PPLL & enable atomic update */
1283 OUTPLLP(PPLL_CNTL,
1284 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1285 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1286
1287 /* Switch to selected PPLL divider */
1288 OUTREGP(CLOCK_CNTL_INDEX,
1289 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1290 ~PPLL_DIV_SEL_MASK);
1291 radeon_pll_errata_after_index(rinfo);
1292 radeon_pll_errata_after_data(rinfo);
1293
1294 /* Set PPLL ref. div */
1295 if (rinfo->family == CHIP_FAMILY_R300 ||
1296 rinfo->family == CHIP_FAMILY_RS300 ||
1297 rinfo->family == CHIP_FAMILY_R350 ||
1298 rinfo->family == CHIP_FAMILY_RV350) {
1299 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1300 /* When restoring console mode, use saved PPLL_REF_DIV
1301 * setting.
1302 */
1303 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1304 } else {
1305 /* R300 uses ref_div_acc field as real ref divider */
1306 OUTPLLP(PPLL_REF_DIV,
1307 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1308 ~R300_PPLL_REF_DIV_ACC_MASK);
1309 }
1310 } else
1311 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1312
1313 /* Set PPLL divider 3 & post divider*/
1314 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1315 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1316
1317 /* Write update */
1318 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1319 ;
1320 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1321
1322 /* Wait read update complete */
1323 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1324 the cause yet, but this workaround will mask the problem for now.
1325 Other chips usually will pass at the very first test, so the
1326 workaround shouldn't have any effect on them. */
1327 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1328 ;
1329
1330 OUTPLL(HTOTAL_CNTL, 0);
1331
1332 /* Clear reset & atomic update */
1333 OUTPLLP(PPLL_CNTL, 0,
1334 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1335
1336 /* We may want some locking ... oh well */
1337 radeon_msleep(5);
1338
1339 /* Switch back VCLK source to PPLL */
1340 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1341}
1342
1343/*
1344 * Timer function for delayed LVDS panel power up/down
1345 */
1346static void radeon_lvds_timer_func(unsigned long data)
1347{
1348 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1349
1350 radeon_engine_idle();
1351
1352 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1353}
1354
1355/*
1356 * Apply a video mode. This will apply the whole register set, including
1357 * the PLL registers, to the card
1358 */
1359void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1360 int regs_only)
1361{
1362 int i;
1363 int primary_mon = PRIMARY_MONITOR(rinfo);
1364
1365 if (nomodeset)
1366 return;
1367
1368 if (!regs_only)
1369 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1370
1371 radeon_fifo_wait(31);
1372 for (i=0; i<10; i++)
1373 OUTREG(common_regs[i].reg, common_regs[i].val);
1374
1375 /* Apply surface registers */
1376 for (i=0; i<8; i++) {
1377 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1378 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1379 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1380 }
1381
1382 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1383 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1384 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1385 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1386 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1387 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1388 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1389 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1390 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1391 OUTREG(CRTC_OFFSET, 0);
1392 OUTREG(CRTC_OFFSET_CNTL, 0);
1393 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1394 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1395
1396 radeon_write_pll_regs(rinfo, mode);
1397
1398 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1399 radeon_fifo_wait(10);
1400 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1401 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1402 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1403 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1404 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1405 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1406 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1407 OUTREG(TMDS_CRC, mode->tmds_crc);
1408 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1409 }
1410
1411 if (!regs_only)
1412 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1413
1414 radeon_fifo_wait(2);
1415 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1416
1417 return;
1418}
1419
1420/*
1421 * Calculate the PLL values for a given mode
1422 */
1423static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1424 unsigned long freq)
1425{
1426 const struct {
1427 int divider;
1428 int bitvalue;
1429 } *post_div,
1430 post_divs[] = {
1431 { 1, 0 },
1432 { 2, 1 },
1433 { 4, 2 },
1434 { 8, 3 },
1435 { 3, 4 },
1436 { 16, 5 },
1437 { 6, 6 },
1438 { 12, 7 },
1439 { 0, 0 },
1440 };
1441 int fb_div, pll_output_freq = 0;
1442 int uses_dvo = 0;
1443
1444 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1445 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1446 * recent than an r(v)100...
1447 */
1448#if 1
1449 /* XXX I had reports of flicker happening with the cinema display
1450 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1451 * this case. This could just be a bandwidth calculation issue, I
1452 * haven't implemented the bandwidth code yet, but in the meantime,
1453 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1454 * I haven't seen a case were were absolutely needed an odd PLL
1455 * divider. I'll find a better fix once I have more infos on the
1456 * real cause of the problem.
1457 */
1458 while (rinfo->has_CRTC2) {
1459 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1460 u32 disp_output_cntl;
1461 int source;
1462
1463 /* FP2 path not enabled */
1464 if ((fp2_gen_cntl & FP2_ON) == 0)
1465 break;
1466 /* Not all chip revs have the same format for this register,
1467 * extract the source selection
1468 */
1469 if (rinfo->family == CHIP_FAMILY_R200 ||
1470 rinfo->family == CHIP_FAMILY_R300 ||
1471 rinfo->family == CHIP_FAMILY_R350 ||
1472 rinfo->family == CHIP_FAMILY_RV350) {
1473 source = (fp2_gen_cntl >> 10) & 0x3;
1474 /* sourced from transform unit, check for transform unit
1475 * own source
1476 */
1477 if (source == 3) {
1478 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1479 source = (disp_output_cntl >> 12) & 0x3;
1480 }
1481 } else
1482 source = (fp2_gen_cntl >> 13) & 0x1;
1483 /* sourced from CRTC2 -> exit */
1484 if (source == 1)
1485 break;
1486
1487 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1488 uses_dvo = 1;
1489 break;
1490 }
1491#else
1492 uses_dvo = 1;
1493#endif
1494 if (freq > rinfo->pll.ppll_max)
1495 freq = rinfo->pll.ppll_max;
1496 if (freq*12 < rinfo->pll.ppll_min)
1497 freq = rinfo->pll.ppll_min / 12;
1498 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1499 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1500
1501 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1502 pll_output_freq = post_div->divider * freq;
1503 /* If we output to the DVO port (external TMDS), we don't allow an
1504 * odd PLL divider as those aren't supported on this path
1505 */
1506 if (uses_dvo && (post_div->divider & 1))
1507 continue;
1508 if (pll_output_freq >= rinfo->pll.ppll_min &&
1509 pll_output_freq <= rinfo->pll.ppll_max)
1510 break;
1511 }
1512
1513 /* If we fall through the bottom, try the "default value"
1514 given by the terminal post_div->bitvalue */
1515 if ( !post_div->divider ) {
1516 post_div = &post_divs[post_div->bitvalue];
1517 pll_output_freq = post_div->divider * freq;
1518 }
1519 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1520 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1521 pll_output_freq);
1522
1523 /* If we fall through the bottom, try the "default value"
1524 given by the terminal post_div->bitvalue */
1525 if ( !post_div->divider ) {
1526 post_div = &post_divs[post_div->bitvalue];
1527 pll_output_freq = post_div->divider * freq;
1528 }
1529 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1530 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1531 pll_output_freq);
1532
1533 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1534 rinfo->pll.ref_clk);
1535 regs->ppll_ref_div = rinfo->pll.ref_div;
1536 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1537
1538 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1539 RTRACE("fb_div = 0x%x\n", fb_div);
1540 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1541}
1542
1543static int radeonfb_set_par(struct fb_info *info)
1544{
1545 struct radeonfb_info *rinfo = info->par;
1546 struct fb_var_screeninfo *mode = &info->var;
1547 struct radeon_regs *newmode;
1548 int hTotal, vTotal, hSyncStart, hSyncEnd,
1549 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1550 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1551 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1552 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1553 int i, freq;
1554 int format = 0;
1555 int nopllcalc = 0;
1556 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1557 int primary_mon = PRIMARY_MONITOR(rinfo);
1558 int depth = var_to_depth(mode);
1559 int use_rmx = 0;
1560
1561 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1562 if (!newmode)
1563 return -ENOMEM;
1564
1565 /* We always want engine to be idle on a mode switch, even
1566 * if we won't actually change the mode
1567 */
1568 radeon_engine_idle();
1569
1570 hSyncStart = mode->xres + mode->right_margin;
1571 hSyncEnd = hSyncStart + mode->hsync_len;
1572 hTotal = hSyncEnd + mode->left_margin;
1573
1574 vSyncStart = mode->yres + mode->lower_margin;
1575 vSyncEnd = vSyncStart + mode->vsync_len;
1576 vTotal = vSyncEnd + mode->upper_margin;
1577 pixClock = mode->pixclock;
1578
1579 sync = mode->sync;
1580 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1581 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1582
1583 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1584 if (rinfo->panel_info.xres < mode->xres)
1585 mode->xres = rinfo->panel_info.xres;
1586 if (rinfo->panel_info.yres < mode->yres)
1587 mode->yres = rinfo->panel_info.yres;
1588
1589 hTotal = mode->xres + rinfo->panel_info.hblank;
1590 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1591 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1592
1593 vTotal = mode->yres + rinfo->panel_info.vblank;
1594 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1595 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1596
1597 h_sync_pol = !rinfo->panel_info.hAct_high;
1598 v_sync_pol = !rinfo->panel_info.vAct_high;
1599
1600 pixClock = 100000000 / rinfo->panel_info.clock;
1601
1602 if (rinfo->panel_info.use_bios_dividers) {
1603 nopllcalc = 1;
1604 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1605 (rinfo->panel_info.post_divider << 16);
1606 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1607 }
1608 }
1609 dotClock = 1000000000 / pixClock;
1610 freq = dotClock / 10; /* x100 */
1611
1612 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1613 hSyncStart, hSyncEnd, hTotal);
1614 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1615 vSyncStart, vSyncEnd, vTotal);
1616
1617 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1618 vsync_wid = vSyncEnd - vSyncStart;
1619 if (hsync_wid == 0)
1620 hsync_wid = 1;
1621 else if (hsync_wid > 0x3f) /* max */
1622 hsync_wid = 0x3f;
1623
1624 if (vsync_wid == 0)
1625 vsync_wid = 1;
1626 else if (vsync_wid > 0x1f) /* max */
1627 vsync_wid = 0x1f;
1628
1629 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1630 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1631
1632 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1633
1634 format = radeon_get_dstbpp(depth);
1635 bytpp = mode->bits_per_pixel >> 3;
1636
1637 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1638 hsync_fudge = hsync_fudge_fp[format-1];
1639 else
1640 hsync_fudge = hsync_adj_tab[format-1];
1641
1642 hsync_start = hSyncStart - 8 + hsync_fudge;
1643
1644 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1645 (format << 8);
1646
1647 /* Clear auto-center etc... */
1648 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1649 newmode->crtc_more_cntl &= 0xfffffff0;
1650
1651 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1652 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1653 if (mirror)
1654 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1655
1656 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1657 CRTC_INTERLACE_EN);
1658 } else {
1659 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1660 CRTC_CRT_ON;
1661 }
1662
1663 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1664 DAC_8BIT_EN;
1665
1666 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1667 (((mode->xres / 8) - 1) << 16));
1668
1669 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1670 (hsync_wid << 16) | (h_sync_pol << 23));
1671
1672 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1673 ((mode->yres - 1) << 16);
1674
1675 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1676 (vsync_wid << 16) | (v_sync_pol << 23));
1677
1678 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1679 /* We first calculate the engine pitch */
1680 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1681 & ~(0x3f)) >> 6;
1682
1683 /* Then, re-multiply it to get the CRTC pitch */
1684 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1685 } else
1686 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1687
1688 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1689
1690 /*
1691 * It looks like recent chips have a problem with SURFACE_CNTL,
1692 * setting SURF_TRANSLATION_DIS completely disables the
1693 * swapper as well, so we leave it unset now.
1694 */
1695 newmode->surface_cntl = 0;
1696
1697#if defined(__BIG_ENDIAN)
1698
1699 /* Setup swapping on both apertures, though we currently
1700 * only use aperture 0, enabling swapper on aperture 1
1701 * won't harm
1702 */
1703 switch (mode->bits_per_pixel) {
1704 case 16:
1705 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1706 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1707 break;
1708 case 24:
1709 case 32:
1710 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1711 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1712 break;
1713 }
1714#endif
1715
1716 /* Clear surface registers */
1717 for (i=0; i<8; i++) {
1718 newmode->surf_lower_bound[i] = 0;
1719 newmode->surf_upper_bound[i] = 0x1f;
1720 newmode->surf_info[i] = 0;
1721 }
1722
1723 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1724 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1725 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1726 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1727
1728 rinfo->bpp = mode->bits_per_pixel;
1729 rinfo->depth = depth;
1730
1731 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1732 RTRACE("freq = %lu\n", (unsigned long)freq);
1733
1734 /* We use PPLL_DIV_3 */
1735 newmode->clk_cntl_index = 0x300;
1736
1737 /* Calculate PPLL value if necessary */
1738 if (!nopllcalc)
1739 radeon_calc_pll_regs(rinfo, newmode, freq);
1740
1741 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1742
1743 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1744 unsigned int hRatio, vRatio;
1745
1746 if (mode->xres > rinfo->panel_info.xres)
1747 mode->xres = rinfo->panel_info.xres;
1748 if (mode->yres > rinfo->panel_info.yres)
1749 mode->yres = rinfo->panel_info.yres;
1750
1751 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1752 << HORZ_PANEL_SHIFT);
1753 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1754 << VERT_PANEL_SHIFT);
1755
1756 if (mode->xres != rinfo->panel_info.xres) {
1757 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1758 rinfo->panel_info.xres);
1759 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1760 (newmode->fp_horz_stretch &
1761 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1762 HORZ_AUTO_RATIO_INC)));
1763 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1764 HORZ_STRETCH_ENABLE);
1765 use_rmx = 1;
1766 }
1767 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1768
1769 if (mode->yres != rinfo->panel_info.yres) {
1770 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1771 rinfo->panel_info.yres);
1772 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1773 (newmode->fp_vert_stretch &
1774 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1775 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1776 VERT_STRETCH_ENABLE);
1777 use_rmx = 1;
1778 }
1779 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1780
1781 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1782 ~(FP_SEL_CRTC2 |
1783 FP_RMX_HVSYNC_CONTROL_EN |
1784 FP_DFP_SYNC_SEL |
1785 FP_CRT_SYNC_SEL |
1786 FP_CRTC_LOCK_8DOT |
1787 FP_USE_SHADOW_EN |
1788 FP_CRTC_USE_SHADOW_VEND |
1789 FP_CRT_SYNC_ALT));
1790
1791 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1792 FP_CRTC_DONT_SHADOW_HEND |
1793 FP_PANEL_FORMAT);
1794
1795 if (IS_R300_VARIANT(rinfo) ||
1796 (rinfo->family == CHIP_FAMILY_R200)) {
1797 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1798 if (use_rmx)
1799 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1800 else
1801 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1802 } else
1803 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1804
1805 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1806 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1807 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1808 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1809
1810 if (primary_mon == MT_LCD) {
1811 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1812 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1813 } else {
1814 /* DFP */
1815 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1816 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1817 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1818 if (IS_R300_VARIANT(rinfo) ||
1819 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1820 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1821 else
1822 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1823 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1824 }
1825
1826 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1827 (((mode->xres / 8) - 1) << 16));
1828 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1829 ((mode->yres - 1) << 16);
1830 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1831 (hsync_wid << 16) | (h_sync_pol << 23));
1832 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1833 (vsync_wid << 16) | (v_sync_pol << 23));
1834 }
1835
1836 /* do it! */
1837 if (!rinfo->asleep) {
1838 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1839 radeon_write_mode (rinfo, newmode, 0);
1840 /* (re)initialize the engine */
1841 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1842 radeonfb_engine_init (rinfo);
1843 }
1844 /* Update fix */
1845 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1846 info->fix.line_length = rinfo->pitch*64;
1847 else
1848 info->fix.line_length = mode->xres_virtual
1849 * ((mode->bits_per_pixel + 1) / 8);
1850 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1851 : FB_VISUAL_DIRECTCOLOR;
1852
1853#ifdef CONFIG_BOOTX_TEXT
1854 /* Update debug text engine */
1855 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1856 rinfo->depth, info->fix.line_length);
1857#endif
1858
1859 kfree(newmode);
1860 return 0;
1861}
1862
1863
1864static struct fb_ops radeonfb_ops = {
1865 .owner = THIS_MODULE,
1866 .fb_check_var = radeonfb_check_var,
1867 .fb_set_par = radeonfb_set_par,
1868 .fb_setcolreg = radeonfb_setcolreg,
71494376 1869 .fb_setcmap = radeonfb_setcmap,
1da177e4
LT		 1870 .fb_pan_display = radeonfb_pan_display,
1871 .fb_blank = radeonfb_blank,
1872 .fb_ioctl = radeonfb_ioctl,
1873 .fb_sync = radeonfb_sync,
1874 .fb_fillrect = radeonfb_fillrect,
1875 .fb_copyarea = radeonfb_copyarea,
1876 .fb_imageblit = radeonfb_imageblit,
1877 .fb_cursor = soft_cursor,
1878};
1879
1880
1881static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1882{
1883 struct fb_info *info = rinfo->info;
1884
1885 info->par = rinfo;
1886 info->pseudo_palette = rinfo->pseudo_palette;
1887 info->flags = FBINFO_DEFAULT
1888 | FBINFO_HWACCEL_COPYAREA
1889 | FBINFO_HWACCEL_FILLRECT
1890 | FBINFO_HWACCEL_XPAN
1891 | FBINFO_HWACCEL_YPAN;
1892 info->fbops = &radeonfb_ops;
1893 info->screen_base = rinfo->fb_base;
1894 info->screen_size = rinfo->mapped_vram;
1895 /* Fill fix common fields */
1896 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1897 info->fix.smem_start = rinfo->fb_base_phys;
1898 info->fix.smem_len = rinfo->video_ram;
1899 info->fix.type = FB_TYPE_PACKED_PIXELS;
1900 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1901 info->fix.xpanstep = 8;
1902 info->fix.ypanstep = 1;
1903 info->fix.ywrapstep = 0;
1904 info->fix.type_aux = 0;
1905 info->fix.mmio_start = rinfo->mmio_base_phys;
1906 info->fix.mmio_len = RADEON_REGSIZE;
1907 info->fix.accel = FB_ACCEL_ATI_RADEON;
1908
1909 fb_alloc_cmap(&info->cmap, 256, 0);
1910
1911 if (noaccel)
1912 info->flags |= FBINFO_HWACCEL_DISABLED;
1913
1914 return 0;
1915}
1916
1917
1918#ifdef CONFIG_PMAC_BACKLIGHT
1919
1920/* TODO: Dbl check these tables, we don't go up to full ON backlight
1921 * in these, possibly because we noticed MacOS doesn't, but I'd prefer
1922 * having some more official numbers from ATI
1923 */
1924static int backlight_conv_m6[] = {
1925 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
1926 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
1927};
1928static int backlight_conv_m7[] = {
1929 0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
1930 0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
1931};
1932
1933#define BACKLIGHT_LVDS_OFF
1934#undef BACKLIGHT_DAC_OFF
1935
1936/* We turn off the LCD completely instead of just dimming the backlight.
1937 * This provides some greater power saving and the display is useless
1938 * without backlight anyway.
1939 */
1940static int radeon_set_backlight_enable(int on, int level, void *data)
1941{
1942 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1943 u32 lvds_gen_cntl, tmpPixclksCntl;
1944 int* conv_table;
1945
1946 if (rinfo->mon1_type != MT_LCD)
1947 return 0;
1948
1949 /* Pardon me for that hack... maybe some day we can figure
1950 * out in what direction backlight should work on a given
1951 * panel ?
1952 */
1953 if ((rinfo->family == CHIP_FAMILY_RV200 ||
1954 rinfo->family == CHIP_FAMILY_RV250 ||
1955 rinfo->family == CHIP_FAMILY_RV280 ||
1956 rinfo->family == CHIP_FAMILY_RV350) &&
1957 !machine_is_compatible("PowerBook4,3") &&
1958 !machine_is_compatible("PowerBook6,3") &&
1959 !machine_is_compatible("PowerBook6,5"))
1960 conv_table = backlight_conv_m7;
1961 else
1962 conv_table = backlight_conv_m6;
1963
1964 del_timer_sync(&rinfo->lvds_timer);
1965 radeon_engine_idle();
1966
1967 lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1968 if (on && (level > BACKLIGHT_OFF)) {
1969 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
1970 if (!(lvds_gen_cntl & LVDS_BLON) || !(lvds_gen_cntl & LVDS_ON)) {
1971 lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_DIGON);
1972 lvds_gen_cntl |= LVDS_BLON | LVDS_EN;
1973 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1974 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1975 lvds_gen_cntl |= (conv_table[level] <<
1976 LVDS_BL_MOD_LEVEL_SHIFT);
1977 lvds_gen_cntl |= LVDS_ON;
1978 lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_BL_MOD_EN);
1979 rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
1980 mod_timer(&rinfo->lvds_timer,
1981 jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1982 } else {
1983 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
1984 lvds_gen_cntl |= (conv_table[level] <<
1985 LVDS_BL_MOD_LEVEL_SHIFT);
1986 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
1987 }
1988 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1989 rinfo->init_state.lvds_gen_cntl |= rinfo->pending_lvds_gen_cntl
1990 & LVDS_STATE_MASK;
1991 } else {
1992 /* Asic bug, when turning off LVDS_ON, we have to make sure
1993 RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1994 */
1995 tmpPixclksCntl = INPLL(PIXCLKS_CNTL);
1996 if (rinfo->is_mobility || rinfo->is_IGP)
1997 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1998 lvds_gen_cntl &= ~(LVDS_BL_MOD_LEVEL_MASK | LVDS_BL_MOD_EN);
1999 lvds_gen_cntl |= (conv_table[0] <<
2000 LVDS_BL_MOD_LEVEL_SHIFT);
2001 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
2002 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2003 udelay(100);
2004 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN);
2005 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2006 lvds_gen_cntl &= ~(LVDS_DIGON);
2007 rinfo->pending_lvds_gen_cntl = lvds_gen_cntl;
2008 mod_timer(&rinfo->lvds_timer,
2009 jiffies + msecs_to_jiffies(rinfo->panel_info.pwr_delay));
2010 if (rinfo->is_mobility || rinfo->is_IGP)
2011 OUTPLL(PIXCLKS_CNTL, tmpPixclksCntl);
2012 }
2013 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
2014 rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
2015
2016 return 0;
2017}
2018
2019
2020static int radeon_set_backlight_level(int level, void *data)
2021{
2022 return radeon_set_backlight_enable(1, level, data);
2023}
2024#endif /* CONFIG_PMAC_BACKLIGHT */
2025
2026
2027/*
2028 * This reconfigure the card's internal memory map. In theory, we'd like
2029 * to setup the card's memory at the same address as it's PCI bus address,
2030 * and the AGP aperture right after that so that system RAM on 32 bits
2031 * machines at least, is directly accessible. However, doing so would
2032 * conflict with the current XFree drivers...
2033 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
2034 * on the proper way to set this up and duplicate this here. In the meantime,
2035 * I put the card's memory at 0 in card space and AGP at some random high
2036 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
2037 */
2038#ifdef CONFIG_PPC_OF
2039#undef SET_MC_FB_FROM_APERTURE
2040static void fixup_memory_mappings(struct radeonfb_info *rinfo)
2041{
2042 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
2043 u32 save_crtc_ext_cntl;
2044 u32 aper_base, aper_size;
2045 u32 agp_base;
2046
2047 /* First, we disable display to avoid interfering */
2048 if (rinfo->has_CRTC2) {
2049 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
2050 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
2051 }
2052 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
2053 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
2054
2055 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
2056 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
2057 mdelay(100);
2058
2059 aper_base = INREG(CONFIG_APER_0_BASE);
2060 aper_size = INREG(CONFIG_APER_SIZE);
2061
2062#ifdef SET_MC_FB_FROM_APERTURE
2063 /* Set framebuffer to be at the same address as set in PCI BAR */
2064 OUTREG(MC_FB_LOCATION,
2065 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
2066 rinfo->fb_local_base = aper_base;
2067#else
2068 OUTREG(MC_FB_LOCATION, 0x7fff0000);
2069 rinfo->fb_local_base = 0;
2070#endif
2071 agp_base = aper_base + aper_size;
2072 if (agp_base & 0xf0000000)
2073 agp_base = (aper_base | 0x0fffffff) + 1;
2074
2075 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
2076 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
2077 * always the case on PPCs afaik.
2078 */
2079#ifdef SET_MC_FB_FROM_APERTURE
2080 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
2081#else
2082 OUTREG(MC_AGP_LOCATION, 0xffffe000);
2083#endif
2084
2085 /* Fixup the display base addresses & engine offsets while we
2086 * are at it as well
2087 */
2088#ifdef SET_MC_FB_FROM_APERTURE
2089 OUTREG(DISPLAY_BASE_ADDR, aper_base);
2090 if (rinfo->has_CRTC2)
2091 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
2092 OUTREG(OV0_BASE_ADDR, aper_base);
2093#else
2094 OUTREG(DISPLAY_BASE_ADDR, 0);
2095 if (rinfo->has_CRTC2)
2096 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
2097 OUTREG(OV0_BASE_ADDR, 0);
2098#endif
2099 mdelay(100);
2100
2101 /* Restore display settings */
2102 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
2103 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
2104 if (rinfo->has_CRTC2)
2105 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
2106
2107 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
2108 aper_base,
2109 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
2110 0xffff0000 | (agp_base >> 16));
2111}
2112#endif /* CONFIG_PPC_OF */
2113
2114
2115static void radeon_identify_vram(struct radeonfb_info *rinfo)
2116{
2117 u32 tmp;
2118
2119 /* framebuffer size */
2120 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2121 (rinfo->family == CHIP_FAMILY_RS200) ||
2122 (rinfo->family == CHIP_FAMILY_RS300)) {
2123 u32 tom = INREG(NB_TOM);
2124 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2125
2126 radeon_fifo_wait(6);
2127 OUTREG(MC_FB_LOCATION, tom);
2128 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2129 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2130 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2131
2132 /* This is supposed to fix the crtc2 noise problem. */
2133 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2134
2135 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2136 (rinfo->family == CHIP_FAMILY_RS200)) {
2137 /* This is to workaround the asic bug for RMX, some versions
2138 of BIOS dosen't have this register initialized correctly.
2139 */
2140 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2141 ~CRTC_H_CUTOFF_ACTIVE_EN);
2142 }
2143 } else {
2144 tmp = INREG(CONFIG_MEMSIZE);
2145 }
2146
2147 /* mem size is bits [28:0], mask off the rest */
2148 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2149
2150 /*
2151 * Hack to get around some busted production M6's
2152 * reporting no ram
2153 */
2154 if (rinfo->video_ram == 0) {
2155 switch (rinfo->pdev->device) {
2156 case PCI_CHIP_RADEON_LY:
2157 case PCI_CHIP_RADEON_LZ:
2158 rinfo->video_ram = 8192 * 1024;
2159 break;
2160 default:
2161 break;
2162 }
2163 }
2164
2165
2166 /*
2167 * Now try to identify VRAM type
2168 */
2169 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2170 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2171 rinfo->vram_ddr = 1;
2172 else
2173 rinfo->vram_ddr = 0;
2174
2175 tmp = INREG(MEM_CNTL);
2176 if (IS_R300_VARIANT(rinfo)) {
2177 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2178 switch (tmp) {
2179 case 0: rinfo->vram_width = 64; break;
2180 case 1: rinfo->vram_width = 128; break;
2181 case 2: rinfo->vram_width = 256; break;
2182 default: rinfo->vram_width = 128; break;
2183 }
2184 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2185 (rinfo->family == CHIP_FAMILY_RS100) ||
2186 (rinfo->family == CHIP_FAMILY_RS200)){
2187 if (tmp & RV100_MEM_HALF_MODE)
2188 rinfo->vram_width = 32;
2189 else
2190 rinfo->vram_width = 64;
2191 } else {
2192 if (tmp & MEM_NUM_CHANNELS_MASK)
2193 rinfo->vram_width = 128;
2194 else
2195 rinfo->vram_width = 64;
2196 }
2197
2198 /* This may not be correct, as some cards can have half of channel disabled
2199 * ToDo: identify these cases
2200 */
2201
2202 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2203 pci_name(rinfo->pdev),
2204 rinfo->video_ram / 1024,
2205 rinfo->vram_ddr ? "DDR" : "SDRAM",
2206 rinfo->vram_width);
2207}
2208
2209/*
2210 * Sysfs
2211 */
2212
2213static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2214{
2215 if (off > EDID_LENGTH)
2216 return 0;
2217
2218 if (off + count > EDID_LENGTH)
2219 count = EDID_LENGTH - off;
2220
2221 memcpy(buf, edid + off, count);
2222
2223 return count;
2224}
2225
2226
2227static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
2228{
2229 struct device *dev = container_of(kobj, struct device, kobj);
2230 struct pci_dev *pdev = to_pci_dev(dev);
2231 struct fb_info *info = pci_get_drvdata(pdev);
2232 struct radeonfb_info *rinfo = info->par;
2233
2234 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2235}
2236
2237
2238static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
2239{
2240 struct device *dev = container_of(kobj, struct device, kobj);
2241 struct pci_dev *pdev = to_pci_dev(dev);
2242 struct fb_info *info = pci_get_drvdata(pdev);
2243 struct radeonfb_info *rinfo = info->par;
2244
2245 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2246}
2247
2248static struct bin_attribute edid1_attr = {
2249 .attr = {
2250 .name = "edid1",
2251 .owner = THIS_MODULE,
2252 .mode = 0444,
2253 },
2254 .size = EDID_LENGTH,
2255 .read = radeon_show_edid1,
2256};
2257
2258static struct bin_attribute edid2_attr = {
2259 .attr = {
2260 .name = "edid2",
2261 .owner = THIS_MODULE,
2262 .mode = 0444,
2263 },
2264 .size = EDID_LENGTH,
2265 .read = radeon_show_edid2,
2266};
2267
2268
2269static int radeonfb_pci_register (struct pci_dev *pdev,
2270 const struct pci_device_id *ent)
2271{
2272 struct fb_info *info;
2273 struct radeonfb_info *rinfo;
2274 int ret;
2275
2276 RTRACE("radeonfb_pci_register BEGIN\n");
2277
2278 /* Enable device in PCI config */
2279 ret = pci_enable_device(pdev);
2280 if (ret < 0) {
2281 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2282 pci_name(pdev));
2283 goto err_out;
2284 }
2285
2286 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2287 if (!info) {
2288 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2289 pci_name(pdev));
2290 ret = -ENOMEM;
2291 goto err_disable;
2292 }
2293 rinfo = info->par;
2294 rinfo->info = info;
2295 rinfo->pdev = pdev;
2296
2297 spin_lock_init(&rinfo->reg_lock);
2298 init_timer(&rinfo->lvds_timer);
2299 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2300 rinfo->lvds_timer.data = (unsigned long)rinfo;
2301
2302 strcpy(rinfo->name, "ATI Radeon XX ");
2303 rinfo->name[11] = ent->device >> 8;
2304 rinfo->name[12] = ent->device & 0xFF;
2305 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2306 rinfo->chipset = pdev->device;
2307 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2308 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2309 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2310
2311 /* Set base addrs */
2312 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2313 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2314
2315 /* request the mem regions */
5251bffc 2316 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
1da177e4 2317 if (ret < 0) {
5251bffc
DB		 2318 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2319 pci_name(rinfo->pdev));
1da177e4
LT		 2320 goto err_release_fb;
2321 }
2322
5251bffc
DB		 2323 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2324 if (ret < 0) {
2325 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2326 pci_name(rinfo->pdev));
2327 goto err_release_pci0;
2328 }
2329
1da177e4
LT		 2330 /* map the regions */
2331 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2332 if (!rinfo->mmio_base) {
5251bffc
DB		 2333 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2334 pci_name(rinfo->pdev));
1da177e4 2335 ret = -EIO;
5251bffc 2336 goto err_release_pci2;
1da177e4
LT		 2337 }
2338
2339 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2340
2341 /*
2342 * Check for errata
2343 */
2344 rinfo->errata = 0;
2345 if (rinfo->family == CHIP_FAMILY_R300 &&
2346 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2347 == CFG_ATI_REV_A11)
2348 rinfo->errata |= CHIP_ERRATA_R300_CG;
2349
2350 if (rinfo->family == CHIP_FAMILY_RV200 ||
2351 rinfo->family == CHIP_FAMILY_RS200)
2352 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2353
2354 if (rinfo->family == CHIP_FAMILY_RV100 ||
2355 rinfo->family == CHIP_FAMILY_RS100 ||
2356 rinfo->family == CHIP_FAMILY_RS200)
2357 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2358
2359#ifdef CONFIG_PPC_OF
2360 /* On PPC, we obtain the OF device-node pointer to the firmware
2361 * data for this chip
2362 */
2363 rinfo->of_node = pci_device_to_OF_node(pdev);
2364 if (rinfo->of_node == NULL)
2365 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2366 pci_name(rinfo->pdev));
2367
2368 /* On PPC, the firmware sets up a memory mapping that tends
2369 * to cause lockups when enabling the engine. We reconfigure
2370 * the card internal memory mappings properly
2371 */
2372 fixup_memory_mappings(rinfo);
2373#endif /* CONFIG_PPC_OF */
2374
2375 /* Get VRAM size and type */
2376 radeon_identify_vram(rinfo);
2377
2378 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2379
2380 do {
2381 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2382 rinfo->mapped_vram);
2383 } while ( rinfo->fb_base == 0 &&
2384 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2385
8d5f7b43
BH		 2386 if (rinfo->fb_base == NULL) {
2387 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2388 pci_name(rinfo->pdev));
1da177e4
LT		 2389 ret = -EIO;
2390 goto err_unmap_rom;
2391 }
2392
2393 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2394 rinfo->mapped_vram/1024);
2395
2396 /*
2397 * Map the BIOS ROM if any and retreive PLL parameters from
2398 * the BIOS. We skip that on mobility chips as the real panel
2399 * values we need aren't in the ROM but in the BIOS image in
2400 * memory. This is definitely not the best meacnism though,
2401 * we really need the arch code to tell us which is the "primary"
2402 * video adapter to use the memory image (or better, the arch
2403 * should provide us a copy of the BIOS image to shield us from
2404 * archs who would store that elsewhere and/or could initialize
2405 * more than one adapter during boot).
2406 */
2407 if (!rinfo->is_mobility)
2408 radeon_map_ROM(rinfo, pdev);
2409
2410 /*
2411 * On x86, the primary display on laptop may have it's BIOS
2412 * ROM elsewhere, try to locate it at the legacy memory hole.
2413 * We probably need to make sure this is the primary display,
2414 * but that is difficult without some arch support.
2415 */
2416#ifdef CONFIG_X86
2417 if (rinfo->bios_seg == NULL)
2418 radeon_find_mem_vbios(rinfo);
2419#endif
2420
2421 /* If both above failed, try the BIOS ROM again for mobility
2422 * chips
2423 */
2424 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2425 radeon_map_ROM(rinfo, pdev);
2426
2427 /* Get informations about the board's PLL */
2428 radeon_get_pllinfo(rinfo);
2429
2430#ifdef CONFIG_FB_RADEON_I2C
2431 /* Register I2C bus */
2432 radeon_create_i2c_busses(rinfo);
2433#endif
2434
2435 /* set all the vital stuff */
2436 radeon_set_fbinfo (rinfo);
2437
2438 /* Probe screen types */
2439 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2440
2441 /* Build mode list, check out panel native model */
2442 radeon_check_modes(rinfo, mode_option);
2443
2444 /* Register some sysfs stuff (should be done better) */
2445 if (rinfo->mon1_EDID)
2446 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2447 if (rinfo->mon2_EDID)
2448 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2449
2450 /* save current mode regs before we switch into the new one
2451 * so we can restore this upon __exit
2452 */
2453 radeon_save_state (rinfo, &rinfo->init_state);
2454 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2455
2456 /* Setup Power Management capabilities */
2457 if (default_dynclk < -1) {
2458 /* -2 is special: means ON on mobility chips and do not
2459 * change on others
2460 */
2461 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1);
2462 } else
2463 radeonfb_pm_init(rinfo, default_dynclk);
2464
2465 pci_set_drvdata(pdev, info);
2466
2467 /* Register with fbdev layer */
2468 ret = register_framebuffer(info);
2469 if (ret < 0) {
2470 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2471 pci_name(rinfo->pdev));
2472 goto err_unmap_fb;
2473 }
2474
2475#ifdef CONFIG_MTRR
2476 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2477 rinfo->video_ram,
2478 MTRR_TYPE_WRCOMB, 1);
2479#endif
2480
2481#ifdef CONFIG_PMAC_BACKLIGHT
2482 if (rinfo->mon1_type == MT_LCD) {
2483 register_backlight_controller(&radeon_backlight_controller,
2484 rinfo, "ati");
2485 register_backlight_controller(&radeon_backlight_controller,
2486 rinfo, "mnca");
2487 }
2488#endif
2489
2490 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2491
2492 if (rinfo->bios_seg)
2493 radeon_unmap_ROM(rinfo, pdev);
2494 RTRACE("radeonfb_pci_register END\n");
2495
2496 return 0;
2497err_unmap_fb:
2498 iounmap(rinfo->fb_base);
2499err_unmap_rom:
2500 kfree(rinfo->mon1_EDID);
2501 kfree(rinfo->mon2_EDID);
2502 if (rinfo->mon1_modedb)
2503 fb_destroy_modedb(rinfo->mon1_modedb);
2504 fb_dealloc_cmap(&info->cmap);
2505#ifdef CONFIG_FB_RADEON_I2C
2506 radeon_delete_i2c_busses(rinfo);
2507#endif
2508 if (rinfo->bios_seg)
2509 radeon_unmap_ROM(rinfo, pdev);
2510 iounmap(rinfo->mmio_base);
5251bffc
DB		 2511err_release_pci2:
2512 pci_release_region(pdev, 2);
2513err_release_pci0:
2514 pci_release_region(pdev, 0);
1da177e4 2515err_release_fb:
5251bffc 2516 framebuffer_release(info);
1da177e4
LT		 2517err_disable:
2518 pci_disable_device(pdev);
2519err_out:
2520 return ret;
2521}
2522
2523
2524
2525static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2526{
2527 struct fb_info *info = pci_get_drvdata(pdev);
2528 struct radeonfb_info *rinfo = info->par;
2529
2530 if (!rinfo)
2531 return;
2532
2533 radeonfb_pm_exit(rinfo);
2534
3ca34fcb
JS		 2535 if (rinfo->mon1_EDID)
2536 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2537 if (rinfo->mon2_EDID)
2538 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2539
1da177e4
LT		 2540#if 0
2541 /* restore original state
2542 *
2543 * Doesn't quite work yet, I suspect if we come from a legacy
2544 * VGA mode (or worse, text mode), we need to do some VGA black
2545 * magic here that I know nothing about. --BenH
2546 */
2547 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2548 #endif
2549
2550 del_timer_sync(&rinfo->lvds_timer);
2551
2552#ifdef CONFIG_MTRR
2553 if (rinfo->mtrr_hdl >= 0)
2554 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2555#endif
2556
2557 unregister_framebuffer(info);
2558
2559 iounmap(rinfo->mmio_base);
2560 iounmap(rinfo->fb_base);
2561
5251bffc
DB		 2562 pci_release_region(pdev, 2);
2563 pci_release_region(pdev, 0);
1da177e4
LT		 2564
2565 kfree(rinfo->mon1_EDID);
2566 kfree(rinfo->mon2_EDID);
2567 if (rinfo->mon1_modedb)
2568 fb_destroy_modedb(rinfo->mon1_modedb);
2569#ifdef CONFIG_FB_RADEON_I2C
2570 radeon_delete_i2c_busses(rinfo);
2571#endif
2572 fb_dealloc_cmap(&info->cmap);
2573 framebuffer_release(info);
2574 pci_disable_device(pdev);
2575}
2576
2577
2578static struct pci_driver radeonfb_driver = {
2579 .name = "radeonfb",
2580 .id_table = radeonfb_pci_table,
2581 .probe = radeonfb_pci_register,
2582 .remove = __devexit_p(radeonfb_pci_unregister),
2583#ifdef CONFIG_PM
2584 .suspend = radeonfb_pci_suspend,
2585 .resume = radeonfb_pci_resume,
2586#endif /* CONFIG_PM */
2587};
2588
2589#ifndef MODULE
2590static int __init radeonfb_setup (char *options)
2591{
2592 char *this_opt;
2593
2594 if (!options || !*options)
2595 return 0;
2596
2597 while ((this_opt = strsep (&options, ",")) != NULL) {
2598 if (!*this_opt)
2599 continue;
2600
2601 if (!strncmp(this_opt, "noaccel", 7)) {
2602 noaccel = 1;
2603 } else if (!strncmp(this_opt, "mirror", 6)) {
2604 mirror = 1;
2605 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2606 force_dfp = 1;
2607 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2608 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2609#ifdef CONFIG_MTRR
2610 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2611 nomtrr = 1;
2612#endif
2613 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2614 nomodeset = 1;
2615 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2616 force_measure_pll = 1;
2617 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2618 ignore_edid = 1;
2619 } else
2620 mode_option = this_opt;
2621 }
2622 return 0;
2623}
2624#endif /* MODULE */
2625
2626static int __init radeonfb_init (void)
2627{
2628#ifndef MODULE
2629 char *option = NULL;
2630
2631 if (fb_get_options("radeonfb", &option))
2632 return -ENODEV;
2633 radeonfb_setup(option);
2634#endif
2635 return pci_register_driver (&radeonfb_driver);
2636}
2637
2638
2639static void __exit radeonfb_exit (void)
2640{
2641 pci_unregister_driver (&radeonfb_driver);
2642}
2643
2644module_init(radeonfb_init);
2645module_exit(radeonfb_exit);
2646
2647MODULE_AUTHOR("Ani Joshi");
2648MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2649MODULE_LICENSE("GPL");
2650module_param(noaccel, bool, 0);
2651module_param(default_dynclk, int, 0);
2652MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2653MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2654module_param(nomodeset, bool, 0);
2655MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2656module_param(mirror, bool, 0);
2657MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2658module_param(force_dfp, bool, 0);
2659MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2660module_param(ignore_edid, bool, 0);
2661MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2662module_param(monitor_layout, charp, 0);
2663MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2664module_param(force_measure_pll, bool, 0);
2665MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2666#ifdef CONFIG_MTRR
2667module_param(nomtrr, bool, 0);
2668MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2669#endif
2670module_param(panel_yres, int, 0);
2671MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2672module_param(mode_option, charp, 0);
2673MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
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