]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/video/chipsfb.c -- frame buffer device for | |
3 | * Chips & Technologies 65550 chip. | |
4 | * | |
5 | * Copyright (C) 1998-2002 Paul Mackerras | |
6 | * | |
7 | * This file is derived from the Powermac "chips" driver: | |
8 | * Copyright (C) 1997 Fabio Riccardi. | |
9 | * And from the frame buffer device for Open Firmware-initialized devices: | |
10 | * Copyright (C) 1997 Geert Uytterhoeven. | |
11 | * | |
12 | * This file is subject to the terms and conditions of the GNU General Public | |
13 | * License. See the file COPYING in the main directory of this archive for | |
14 | * more details. | |
15 | */ | |
16 | ||
17 | #include <linux/config.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/mm.h> | |
23 | #include <linux/tty.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/vmalloc.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/fb.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/pci.h> | |
8c870933 | 31 | #include <linux/console.h> |
1da177e4 LT |
32 | #include <asm/io.h> |
33 | ||
34 | #ifdef CONFIG_PMAC_BACKLIGHT | |
35 | #include <asm/backlight.h> | |
36 | #endif | |
1da177e4 LT |
37 | |
38 | /* | |
39 | * Since we access the display with inb/outb to fixed port numbers, | |
40 | * we can only handle one 6555x chip. -- paulus | |
41 | */ | |
1da177e4 LT |
42 | #define write_ind(num, val, ap, dp) do { \ |
43 | outb((num), (ap)); outb((val), (dp)); \ | |
44 | } while (0) | |
45 | #define read_ind(num, var, ap, dp) do { \ | |
46 | outb((num), (ap)); var = inb((dp)); \ | |
47 | } while (0) | |
48 | ||
49 | /* extension registers */ | |
50 | #define write_xr(num, val) write_ind(num, val, 0x3d6, 0x3d7) | |
51 | #define read_xr(num, var) read_ind(num, var, 0x3d6, 0x3d7) | |
52 | /* flat panel registers */ | |
53 | #define write_fr(num, val) write_ind(num, val, 0x3d0, 0x3d1) | |
54 | #define read_fr(num, var) read_ind(num, var, 0x3d0, 0x3d1) | |
55 | /* CRTC registers */ | |
56 | #define write_cr(num, val) write_ind(num, val, 0x3d4, 0x3d5) | |
57 | #define read_cr(num, var) read_ind(num, var, 0x3d4, 0x3d5) | |
58 | /* graphics registers */ | |
59 | #define write_gr(num, val) write_ind(num, val, 0x3ce, 0x3cf) | |
60 | #define read_gr(num, var) read_ind(num, var, 0x3ce, 0x3cf) | |
61 | /* sequencer registers */ | |
62 | #define write_sr(num, val) write_ind(num, val, 0x3c4, 0x3c5) | |
63 | #define read_sr(num, var) read_ind(num, var, 0x3c4, 0x3c5) | |
64 | /* attribute registers - slightly strange */ | |
65 | #define write_ar(num, val) do { \ | |
66 | inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \ | |
67 | } while (0) | |
68 | #define read_ar(num, var) do { \ | |
69 | inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \ | |
70 | } while (0) | |
71 | ||
1da177e4 LT |
72 | /* |
73 | * Exported functions | |
74 | */ | |
75 | int chips_init(void); | |
76 | ||
77 | static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *); | |
78 | static int chipsfb_check_var(struct fb_var_screeninfo *var, | |
79 | struct fb_info *info); | |
80 | static int chipsfb_set_par(struct fb_info *info); | |
81 | static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
82 | u_int transp, struct fb_info *info); | |
83 | static int chipsfb_blank(int blank, struct fb_info *info); | |
84 | ||
85 | static struct fb_ops chipsfb_ops = { | |
86 | .owner = THIS_MODULE, | |
87 | .fb_check_var = chipsfb_check_var, | |
88 | .fb_set_par = chipsfb_set_par, | |
89 | .fb_setcolreg = chipsfb_setcolreg, | |
90 | .fb_blank = chipsfb_blank, | |
91 | .fb_fillrect = cfb_fillrect, | |
92 | .fb_copyarea = cfb_copyarea, | |
93 | .fb_imageblit = cfb_imageblit, | |
1da177e4 LT |
94 | }; |
95 | ||
96 | static int chipsfb_check_var(struct fb_var_screeninfo *var, | |
97 | struct fb_info *info) | |
98 | { | |
99 | if (var->xres > 800 || var->yres > 600 | |
100 | || var->xres_virtual > 800 || var->yres_virtual > 600 | |
101 | || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16) | |
102 | || var->nonstd | |
103 | || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) | |
104 | return -EINVAL; | |
105 | ||
106 | var->xres = var->xres_virtual = 800; | |
107 | var->yres = var->yres_virtual = 600; | |
108 | ||
109 | return 0; | |
110 | } | |
111 | ||
112 | static int chipsfb_set_par(struct fb_info *info) | |
113 | { | |
114 | if (info->var.bits_per_pixel == 16) { | |
115 | write_cr(0x13, 200); // Set line length (doublewords) | |
116 | write_xr(0x81, 0x14); // 15 bit (555) color mode | |
117 | write_xr(0x82, 0x00); // Disable palettes | |
118 | write_xr(0x20, 0x10); // 16 bit blitter mode | |
119 | ||
120 | info->fix.line_length = 800*2; | |
121 | info->fix.visual = FB_VISUAL_TRUECOLOR; | |
122 | ||
123 | info->var.red.offset = 10; | |
124 | info->var.green.offset = 5; | |
125 | info->var.blue.offset = 0; | |
126 | info->var.red.length = info->var.green.length = | |
127 | info->var.blue.length = 5; | |
128 | ||
129 | } else { | |
130 | /* p->var.bits_per_pixel == 8 */ | |
131 | write_cr(0x13, 100); // Set line length (doublewords) | |
132 | write_xr(0x81, 0x12); // 8 bit color mode | |
133 | write_xr(0x82, 0x08); // Graphics gamma enable | |
134 | write_xr(0x20, 0x00); // 8 bit blitter mode | |
135 | ||
136 | info->fix.line_length = 800; | |
137 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
138 | ||
139 | info->var.red.offset = info->var.green.offset = | |
140 | info->var.blue.offset = 0; | |
141 | info->var.red.length = info->var.green.length = | |
142 | info->var.blue.length = 8; | |
143 | ||
144 | } | |
145 | return 0; | |
146 | } | |
147 | ||
148 | static int chipsfb_blank(int blank, struct fb_info *info) | |
149 | { | |
150 | #ifdef CONFIG_PMAC_BACKLIGHT | |
151 | // used to disable backlight only for blank > 1, but it seems | |
152 | // useful at blank = 1 too (saves battery, extends backlight life) | |
153 | set_backlight_enable(!blank); | |
154 | #endif /* CONFIG_PMAC_BACKLIGHT */ | |
155 | ||
156 | return 1; /* get fb_blank to set the colormap to all black */ | |
157 | } | |
158 | ||
159 | static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
160 | u_int transp, struct fb_info *info) | |
161 | { | |
162 | if (regno > 255) | |
163 | return 1; | |
164 | red >>= 8; | |
165 | green >>= 8; | |
166 | blue >>= 8; | |
167 | outb(regno, 0x3c8); | |
168 | udelay(1); | |
169 | outb(red, 0x3c9); | |
170 | outb(green, 0x3c9); | |
171 | outb(blue, 0x3c9); | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | struct chips_init_reg { | |
177 | unsigned char addr; | |
178 | unsigned char data; | |
179 | }; | |
180 | ||
181 | #define N_ELTS(x) (sizeof(x) / sizeof(x[0])) | |
182 | ||
183 | static struct chips_init_reg chips_init_sr[] = { | |
184 | { 0x00, 0x03 }, | |
185 | { 0x01, 0x01 }, | |
186 | { 0x02, 0x0f }, | |
187 | { 0x04, 0x0e } | |
188 | }; | |
189 | ||
190 | static struct chips_init_reg chips_init_gr[] = { | |
191 | { 0x05, 0x00 }, | |
192 | { 0x06, 0x0d }, | |
193 | { 0x08, 0xff } | |
194 | }; | |
195 | ||
196 | static struct chips_init_reg chips_init_ar[] = { | |
197 | { 0x10, 0x01 }, | |
198 | { 0x12, 0x0f }, | |
199 | { 0x13, 0x00 } | |
200 | }; | |
201 | ||
202 | static struct chips_init_reg chips_init_cr[] = { | |
203 | { 0x00, 0x7f }, | |
204 | { 0x01, 0x63 }, | |
205 | { 0x02, 0x63 }, | |
206 | { 0x03, 0x83 }, | |
207 | { 0x04, 0x66 }, | |
208 | { 0x05, 0x10 }, | |
209 | { 0x06, 0x72 }, | |
210 | { 0x07, 0x3e }, | |
211 | { 0x08, 0x00 }, | |
212 | { 0x09, 0x40 }, | |
213 | { 0x0c, 0x00 }, | |
214 | { 0x0d, 0x00 }, | |
215 | { 0x10, 0x59 }, | |
216 | { 0x11, 0x0d }, | |
217 | { 0x12, 0x57 }, | |
218 | { 0x13, 0x64 }, | |
219 | { 0x14, 0x00 }, | |
220 | { 0x15, 0x57 }, | |
221 | { 0x16, 0x73 }, | |
222 | { 0x17, 0xe3 }, | |
223 | { 0x18, 0xff }, | |
224 | { 0x30, 0x02 }, | |
225 | { 0x31, 0x02 }, | |
226 | { 0x32, 0x02 }, | |
227 | { 0x33, 0x02 }, | |
228 | { 0x40, 0x00 }, | |
229 | { 0x41, 0x00 }, | |
230 | { 0x40, 0x80 } | |
231 | }; | |
232 | ||
233 | static struct chips_init_reg chips_init_fr[] = { | |
234 | { 0x01, 0x02 }, | |
235 | { 0x03, 0x08 }, | |
236 | { 0x04, 0x81 }, | |
237 | { 0x05, 0x21 }, | |
238 | { 0x08, 0x0c }, | |
239 | { 0x0a, 0x74 }, | |
240 | { 0x0b, 0x11 }, | |
241 | { 0x10, 0x0c }, | |
242 | { 0x11, 0xe0 }, | |
243 | /* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */ | |
244 | { 0x20, 0x63 }, | |
245 | { 0x21, 0x68 }, | |
246 | { 0x22, 0x19 }, | |
247 | { 0x23, 0x7f }, | |
248 | { 0x24, 0x68 }, | |
249 | { 0x26, 0x00 }, | |
250 | { 0x27, 0x0f }, | |
251 | { 0x30, 0x57 }, | |
252 | { 0x31, 0x58 }, | |
253 | { 0x32, 0x0d }, | |
254 | { 0x33, 0x72 }, | |
255 | { 0x34, 0x02 }, | |
256 | { 0x35, 0x22 }, | |
257 | { 0x36, 0x02 }, | |
258 | { 0x37, 0x00 } | |
259 | }; | |
260 | ||
261 | static struct chips_init_reg chips_init_xr[] = { | |
262 | { 0xce, 0x00 }, /* set default memory clock */ | |
263 | { 0xcc, 0x43 }, /* memory clock ratio */ | |
264 | { 0xcd, 0x18 }, | |
265 | { 0xce, 0xa1 }, | |
266 | { 0xc8, 0x84 }, | |
267 | { 0xc9, 0x0a }, | |
268 | { 0xca, 0x00 }, | |
269 | { 0xcb, 0x20 }, | |
270 | { 0xcf, 0x06 }, | |
271 | { 0xd0, 0x0e }, | |
272 | { 0x09, 0x01 }, | |
273 | { 0x0a, 0x02 }, | |
274 | { 0x0b, 0x01 }, | |
275 | { 0x20, 0x00 }, | |
276 | { 0x40, 0x03 }, | |
277 | { 0x41, 0x01 }, | |
278 | { 0x42, 0x00 }, | |
279 | { 0x80, 0x82 }, | |
280 | { 0x81, 0x12 }, | |
281 | { 0x82, 0x08 }, | |
282 | { 0xa0, 0x00 }, | |
283 | { 0xa8, 0x00 } | |
284 | }; | |
285 | ||
286 | static void __init chips_hw_init(void) | |
287 | { | |
288 | int i; | |
289 | ||
290 | for (i = 0; i < N_ELTS(chips_init_xr); ++i) | |
291 | write_xr(chips_init_xr[i].addr, chips_init_xr[i].data); | |
292 | outb(0x29, 0x3c2); /* set misc output reg */ | |
293 | for (i = 0; i < N_ELTS(chips_init_sr); ++i) | |
294 | write_sr(chips_init_sr[i].addr, chips_init_sr[i].data); | |
295 | for (i = 0; i < N_ELTS(chips_init_gr); ++i) | |
296 | write_gr(chips_init_gr[i].addr, chips_init_gr[i].data); | |
297 | for (i = 0; i < N_ELTS(chips_init_ar); ++i) | |
298 | write_ar(chips_init_ar[i].addr, chips_init_ar[i].data); | |
299 | for (i = 0; i < N_ELTS(chips_init_cr); ++i) | |
300 | write_cr(chips_init_cr[i].addr, chips_init_cr[i].data); | |
301 | for (i = 0; i < N_ELTS(chips_init_fr); ++i) | |
302 | write_fr(chips_init_fr[i].addr, chips_init_fr[i].data); | |
303 | } | |
304 | ||
305 | static struct fb_fix_screeninfo chipsfb_fix __initdata = { | |
306 | .id = "C&T 65550", | |
307 | .type = FB_TYPE_PACKED_PIXELS, | |
308 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
309 | .accel = FB_ACCEL_NONE, | |
310 | .line_length = 800, | |
311 | ||
312 | // FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB. | |
313 | // * "3500" PowerBook G3 (the original PB G3) has 2MB. | |
314 | // * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips. | |
315 | // Motherboard actually supports 2MB -- there are two blank locations | |
316 | // for a second pair of DRAMs. (Thanks, Apple!) | |
317 | // * 3400 has 1MB (I think). Don't know if it's expandable. | |
318 | // -- Tim Seufert | |
319 | .smem_len = 0x100000, /* 1MB */ | |
320 | }; | |
321 | ||
322 | static struct fb_var_screeninfo chipsfb_var __initdata = { | |
323 | .xres = 800, | |
324 | .yres = 600, | |
325 | .xres_virtual = 800, | |
326 | .yres_virtual = 600, | |
327 | .bits_per_pixel = 8, | |
328 | .red = { .length = 8 }, | |
329 | .green = { .length = 8 }, | |
330 | .blue = { .length = 8 }, | |
331 | .height = -1, | |
332 | .width = -1, | |
333 | .vmode = FB_VMODE_NONINTERLACED, | |
334 | .pixclock = 10000, | |
335 | .left_margin = 16, | |
336 | .right_margin = 16, | |
337 | .upper_margin = 16, | |
338 | .lower_margin = 16, | |
339 | .hsync_len = 8, | |
340 | .vsync_len = 8, | |
341 | }; | |
342 | ||
343 | static void __init init_chips(struct fb_info *p, unsigned long addr) | |
344 | { | |
8c870933 BH |
345 | memset(p->screen_base, 0, 0x100000); |
346 | ||
1da177e4 LT |
347 | p->fix = chipsfb_fix; |
348 | p->fix.smem_start = addr; | |
349 | ||
350 | p->var = chipsfb_var; | |
351 | ||
352 | p->fbops = &chipsfb_ops; | |
353 | p->flags = FBINFO_DEFAULT; | |
354 | ||
355 | fb_alloc_cmap(&p->cmap, 256, 0); | |
356 | ||
1da177e4 LT |
357 | chips_hw_init(); |
358 | } | |
359 | ||
360 | static int __devinit | |
361 | chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent) | |
362 | { | |
8c870933 | 363 | struct fb_info *p; |
1da177e4 LT |
364 | unsigned long addr, size; |
365 | unsigned short cmd; | |
8c870933 BH |
366 | int rc = -ENODEV; |
367 | ||
368 | if (pci_enable_device(dp) < 0) { | |
369 | dev_err(&dp->dev, "Cannot enable PCI device\n"); | |
370 | goto err_out; | |
371 | } | |
1da177e4 LT |
372 | |
373 | if ((dp->resource[0].flags & IORESOURCE_MEM) == 0) | |
8c870933 | 374 | goto err_disable; |
1da177e4 LT |
375 | addr = pci_resource_start(dp, 0); |
376 | size = pci_resource_len(dp, 0); | |
377 | if (addr == 0) | |
8c870933 BH |
378 | goto err_disable; |
379 | ||
380 | p = framebuffer_alloc(0, &dp->dev); | |
381 | if (p == NULL) { | |
382 | dev_err(&dp->dev, "Cannot allocate framebuffer structure\n"); | |
383 | rc = -ENOMEM; | |
384 | goto err_disable; | |
385 | } | |
386 | ||
387 | if (pci_request_region(dp, 0, "chipsfb") != 0) { | |
388 | dev_err(&dp->dev, "Cannot request framebuffer\n"); | |
389 | rc = -EBUSY; | |
390 | goto err_release_fb; | |
391 | } | |
1da177e4 LT |
392 | |
393 | #ifdef __BIG_ENDIAN | |
394 | addr += 0x800000; // Use big-endian aperture | |
395 | #endif | |
396 | ||
397 | /* we should use pci_enable_device here, but, | |
398 | the device doesn't declare its I/O ports in its BARs | |
399 | so pci_enable_device won't turn on I/O responses */ | |
400 | pci_read_config_word(dp, PCI_COMMAND, &cmd); | |
401 | cmd |= 3; /* enable memory and IO space */ | |
402 | pci_write_config_word(dp, PCI_COMMAND, cmd); | |
403 | ||
404 | #ifdef CONFIG_PMAC_BACKLIGHT | |
405 | /* turn on the backlight */ | |
406 | set_backlight_enable(1); | |
407 | #endif /* CONFIG_PMAC_BACKLIGHT */ | |
408 | ||
8c870933 | 409 | #ifdef CONFIG_PPC |
1da177e4 | 410 | p->screen_base = __ioremap(addr, 0x200000, _PAGE_NO_CACHE); |
8c870933 BH |
411 | #else |
412 | p->screen_base = ioremap(addr, 0x200000); | |
413 | #endif | |
1da177e4 | 414 | if (p->screen_base == NULL) { |
8c870933 BH |
415 | dev_err(&dp->dev, "Cannot map framebuffer\n"); |
416 | rc = -ENOMEM; | |
417 | goto err_release_pci; | |
1da177e4 | 418 | } |
8c870933 BH |
419 | |
420 | pci_set_drvdata(dp, p); | |
1da177e4 | 421 | p->device = &dp->dev; |
8c870933 | 422 | |
1da177e4 LT |
423 | init_chips(p, addr); |
424 | ||
8c870933 BH |
425 | if (register_framebuffer(p) < 0) { |
426 | dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n"); | |
427 | goto err_unmap; | |
428 | } | |
429 | ||
430 | dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer" | |
431 | " (%dK RAM detected)\n", | |
432 | p->node, p->fix.smem_len / 1024); | |
1da177e4 | 433 | |
1da177e4 | 434 | return 0; |
8c870933 BH |
435 | |
436 | err_unmap: | |
437 | iounmap(p->screen_base); | |
438 | err_release_pci: | |
439 | pci_release_region(dp, 0); | |
440 | err_release_fb: | |
441 | framebuffer_release(p); | |
442 | err_disable: | |
443 | err_out: | |
444 | return rc; | |
1da177e4 LT |
445 | } |
446 | ||
447 | static void __devexit chipsfb_remove(struct pci_dev *dp) | |
448 | { | |
449 | struct fb_info *p = pci_get_drvdata(dp); | |
450 | ||
8c870933 | 451 | if (p->screen_base == NULL) |
1da177e4 LT |
452 | return; |
453 | unregister_framebuffer(p); | |
454 | iounmap(p->screen_base); | |
455 | p->screen_base = NULL; | |
8c870933 BH |
456 | pci_release_region(dp, 0); |
457 | } | |
458 | ||
459 | #ifdef CONFIG_PM | |
460 | static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
461 | { | |
462 | struct fb_info *p = pci_get_drvdata(pdev); | |
463 | ||
ca078bae | 464 | if (state.event == pdev->dev.power.power_state.event) |
8c870933 | 465 | return 0; |
ca078bae | 466 | if (state.event != PM_SUSPEND_MEM) |
8c870933 BH |
467 | goto done; |
468 | ||
469 | acquire_console_sem(); | |
470 | chipsfb_blank(1, p); | |
471 | fb_set_suspend(p, 1); | |
472 | release_console_sem(); | |
473 | done: | |
474 | pdev->dev.power.power_state = state; | |
475 | return 0; | |
476 | } | |
477 | ||
478 | static int chipsfb_pci_resume(struct pci_dev *pdev) | |
479 | { | |
480 | struct fb_info *p = pci_get_drvdata(pdev); | |
1da177e4 | 481 | |
8c870933 BH |
482 | acquire_console_sem(); |
483 | fb_set_suspend(p, 0); | |
484 | chipsfb_blank(0, p); | |
485 | release_console_sem(); | |
486 | ||
487 | pdev->dev.power.power_state = PMSG_ON; | |
488 | return 0; | |
1da177e4 | 489 | } |
8c870933 BH |
490 | #endif /* CONFIG_PM */ |
491 | ||
1da177e4 LT |
492 | |
493 | static struct pci_device_id chipsfb_pci_tbl[] = { | |
494 | { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID }, | |
495 | { 0 } | |
496 | }; | |
497 | ||
498 | MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl); | |
499 | ||
500 | static struct pci_driver chipsfb_driver = { | |
501 | .name = "chipsfb", | |
502 | .id_table = chipsfb_pci_tbl, | |
503 | .probe = chipsfb_pci_init, | |
504 | .remove = __devexit_p(chipsfb_remove), | |
8c870933 BH |
505 | #ifdef CONFIG_PM |
506 | .suspend = chipsfb_pci_suspend, | |
507 | .resume = chipsfb_pci_resume, | |
508 | #endif | |
1da177e4 LT |
509 | }; |
510 | ||
511 | int __init chips_init(void) | |
512 | { | |
513 | if (fb_get_options("chipsfb", NULL)) | |
514 | return -ENODEV; | |
515 | ||
516 | return pci_register_driver(&chipsfb_driver); | |
517 | } | |
518 | ||
519 | module_init(chips_init); | |
520 | ||
521 | static void __exit chipsfb_exit(void) | |
522 | { | |
523 | pci_unregister_driver(&chipsfb_driver); | |
524 | } | |
525 | ||
1da177e4 | 526 | MODULE_LICENSE("GPL"); |