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Drivers: video: remove __dev* attributes.
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CommitLineData
1da177e4
LT
1/*
2 * drivers/video/chipsfb.c -- frame buffer device for
3 * Chips & Technologies 65550 chip.
4 *
5 * Copyright (C) 1998-2002 Paul Mackerras
6 *
7 * This file is derived from the Powermac "chips" driver:
8 * Copyright (C) 1997 Fabio Riccardi.
9 * And from the frame buffer device for Open Firmware-initialized devices:
10 * Copyright (C) 1997 Geert Uytterhoeven.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 */
16
1da177e4
LT
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/string.h>
21#include <linux/mm.h>
1da177e4
LT
22#include <linux/vmalloc.h>
23#include <linux/delay.h>
24#include <linux/interrupt.h>
25#include <linux/fb.h>
26b97237 26#include <linux/pm.h>
1da177e4
LT
27#include <linux/init.h>
28#include <linux/pci.h>
8c870933 29#include <linux/console.h>
1da177e4
LT
30#include <asm/io.h>
31
32#ifdef CONFIG_PMAC_BACKLIGHT
33#include <asm/backlight.h>
34#endif
1da177e4
LT
35
36/*
37 * Since we access the display with inb/outb to fixed port numbers,
38 * we can only handle one 6555x chip. -- paulus
39 */
1da177e4
LT
40#define write_ind(num, val, ap, dp) do { \
41 outb((num), (ap)); outb((val), (dp)); \
42} while (0)
43#define read_ind(num, var, ap, dp) do { \
44 outb((num), (ap)); var = inb((dp)); \
45} while (0)
46
47/* extension registers */
48#define write_xr(num, val) write_ind(num, val, 0x3d6, 0x3d7)
49#define read_xr(num, var) read_ind(num, var, 0x3d6, 0x3d7)
50/* flat panel registers */
51#define write_fr(num, val) write_ind(num, val, 0x3d0, 0x3d1)
52#define read_fr(num, var) read_ind(num, var, 0x3d0, 0x3d1)
53/* CRTC registers */
54#define write_cr(num, val) write_ind(num, val, 0x3d4, 0x3d5)
55#define read_cr(num, var) read_ind(num, var, 0x3d4, 0x3d5)
56/* graphics registers */
57#define write_gr(num, val) write_ind(num, val, 0x3ce, 0x3cf)
58#define read_gr(num, var) read_ind(num, var, 0x3ce, 0x3cf)
59/* sequencer registers */
60#define write_sr(num, val) write_ind(num, val, 0x3c4, 0x3c5)
61#define read_sr(num, var) read_ind(num, var, 0x3c4, 0x3c5)
62/* attribute registers - slightly strange */
63#define write_ar(num, val) do { \
64 inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \
65} while (0)
66#define read_ar(num, var) do { \
67 inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \
68} while (0)
69
1da177e4
LT
70/*
71 * Exported functions
72 */
73int chips_init(void);
74
75static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
76static int chipsfb_check_var(struct fb_var_screeninfo *var,
77 struct fb_info *info);
78static int chipsfb_set_par(struct fb_info *info);
79static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
80 u_int transp, struct fb_info *info);
81static int chipsfb_blank(int blank, struct fb_info *info);
82
83static struct fb_ops chipsfb_ops = {
84 .owner = THIS_MODULE,
85 .fb_check_var = chipsfb_check_var,
86 .fb_set_par = chipsfb_set_par,
87 .fb_setcolreg = chipsfb_setcolreg,
88 .fb_blank = chipsfb_blank,
89 .fb_fillrect = cfb_fillrect,
90 .fb_copyarea = cfb_copyarea,
91 .fb_imageblit = cfb_imageblit,
1da177e4
LT
92};
93
94static int chipsfb_check_var(struct fb_var_screeninfo *var,
95 struct fb_info *info)
96{
97 if (var->xres > 800 || var->yres > 600
98 || var->xres_virtual > 800 || var->yres_virtual > 600
99 || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)
100 || var->nonstd
101 || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
102 return -EINVAL;
103
104 var->xres = var->xres_virtual = 800;
105 var->yres = var->yres_virtual = 600;
106
107 return 0;
108}
109
110static int chipsfb_set_par(struct fb_info *info)
111{
112 if (info->var.bits_per_pixel == 16) {
113 write_cr(0x13, 200); // Set line length (doublewords)
114 write_xr(0x81, 0x14); // 15 bit (555) color mode
115 write_xr(0x82, 0x00); // Disable palettes
116 write_xr(0x20, 0x10); // 16 bit blitter mode
117
118 info->fix.line_length = 800*2;
119 info->fix.visual = FB_VISUAL_TRUECOLOR;
120
121 info->var.red.offset = 10;
122 info->var.green.offset = 5;
123 info->var.blue.offset = 0;
124 info->var.red.length = info->var.green.length =
125 info->var.blue.length = 5;
126
127 } else {
128 /* p->var.bits_per_pixel == 8 */
129 write_cr(0x13, 100); // Set line length (doublewords)
130 write_xr(0x81, 0x12); // 8 bit color mode
131 write_xr(0x82, 0x08); // Graphics gamma enable
132 write_xr(0x20, 0x00); // 8 bit blitter mode
133
134 info->fix.line_length = 800;
135 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
136
137 info->var.red.offset = info->var.green.offset =
138 info->var.blue.offset = 0;
139 info->var.red.length = info->var.green.length =
140 info->var.blue.length = 8;
141
142 }
143 return 0;
144}
145
146static int chipsfb_blank(int blank, struct fb_info *info)
147{
1da177e4
LT
148 return 1; /* get fb_blank to set the colormap to all black */
149}
150
151static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
152 u_int transp, struct fb_info *info)
153{
154 if (regno > 255)
155 return 1;
156 red >>= 8;
157 green >>= 8;
158 blue >>= 8;
159 outb(regno, 0x3c8);
160 udelay(1);
161 outb(red, 0x3c9);
162 outb(green, 0x3c9);
163 outb(blue, 0x3c9);
164
165 return 0;
166}
167
168struct chips_init_reg {
169 unsigned char addr;
170 unsigned char data;
171};
172
1da177e4
LT
173static struct chips_init_reg chips_init_sr[] = {
174 { 0x00, 0x03 },
175 { 0x01, 0x01 },
176 { 0x02, 0x0f },
177 { 0x04, 0x0e }
178};
179
180static struct chips_init_reg chips_init_gr[] = {
181 { 0x05, 0x00 },
182 { 0x06, 0x0d },
183 { 0x08, 0xff }
184};
185
186static struct chips_init_reg chips_init_ar[] = {
187 { 0x10, 0x01 },
188 { 0x12, 0x0f },
189 { 0x13, 0x00 }
190};
191
192static struct chips_init_reg chips_init_cr[] = {
193 { 0x00, 0x7f },
194 { 0x01, 0x63 },
195 { 0x02, 0x63 },
196 { 0x03, 0x83 },
197 { 0x04, 0x66 },
198 { 0x05, 0x10 },
199 { 0x06, 0x72 },
200 { 0x07, 0x3e },
201 { 0x08, 0x00 },
202 { 0x09, 0x40 },
203 { 0x0c, 0x00 },
204 { 0x0d, 0x00 },
205 { 0x10, 0x59 },
206 { 0x11, 0x0d },
207 { 0x12, 0x57 },
208 { 0x13, 0x64 },
209 { 0x14, 0x00 },
210 { 0x15, 0x57 },
211 { 0x16, 0x73 },
212 { 0x17, 0xe3 },
213 { 0x18, 0xff },
214 { 0x30, 0x02 },
215 { 0x31, 0x02 },
216 { 0x32, 0x02 },
217 { 0x33, 0x02 },
218 { 0x40, 0x00 },
219 { 0x41, 0x00 },
220 { 0x40, 0x80 }
221};
222
223static struct chips_init_reg chips_init_fr[] = {
224 { 0x01, 0x02 },
225 { 0x03, 0x08 },
226 { 0x04, 0x81 },
227 { 0x05, 0x21 },
228 { 0x08, 0x0c },
229 { 0x0a, 0x74 },
230 { 0x0b, 0x11 },
231 { 0x10, 0x0c },
232 { 0x11, 0xe0 },
233 /* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */
234 { 0x20, 0x63 },
235 { 0x21, 0x68 },
236 { 0x22, 0x19 },
237 { 0x23, 0x7f },
238 { 0x24, 0x68 },
239 { 0x26, 0x00 },
240 { 0x27, 0x0f },
241 { 0x30, 0x57 },
242 { 0x31, 0x58 },
243 { 0x32, 0x0d },
244 { 0x33, 0x72 },
245 { 0x34, 0x02 },
246 { 0x35, 0x22 },
247 { 0x36, 0x02 },
248 { 0x37, 0x00 }
249};
250
251static struct chips_init_reg chips_init_xr[] = {
252 { 0xce, 0x00 }, /* set default memory clock */
253 { 0xcc, 0x43 }, /* memory clock ratio */
254 { 0xcd, 0x18 },
255 { 0xce, 0xa1 },
256 { 0xc8, 0x84 },
257 { 0xc9, 0x0a },
258 { 0xca, 0x00 },
259 { 0xcb, 0x20 },
260 { 0xcf, 0x06 },
261 { 0xd0, 0x0e },
262 { 0x09, 0x01 },
263 { 0x0a, 0x02 },
264 { 0x0b, 0x01 },
265 { 0x20, 0x00 },
266 { 0x40, 0x03 },
267 { 0x41, 0x01 },
268 { 0x42, 0x00 },
269 { 0x80, 0x82 },
270 { 0x81, 0x12 },
271 { 0x82, 0x08 },
272 { 0xa0, 0x00 },
273 { 0xa8, 0x00 }
274};
275
276static void __init chips_hw_init(void)
277{
278 int i;
279
d1ae418e 280 for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
1da177e4
LT
281 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
282 outb(0x29, 0x3c2); /* set misc output reg */
d1ae418e 283 for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
1da177e4 284 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
d1ae418e 285 for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
1da177e4 286 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
d1ae418e 287 for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
1da177e4 288 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
d1ae418e 289 for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
1da177e4 290 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
d1ae418e 291 for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
1da177e4
LT
292 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
293}
294
48c68c4f 295static struct fb_fix_screeninfo chipsfb_fix = {
1da177e4
LT
296 .id = "C&T 65550",
297 .type = FB_TYPE_PACKED_PIXELS,
298 .visual = FB_VISUAL_PSEUDOCOLOR,
299 .accel = FB_ACCEL_NONE,
300 .line_length = 800,
301
302// FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.
303// * "3500" PowerBook G3 (the original PB G3) has 2MB.
304// * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.
305// Motherboard actually supports 2MB -- there are two blank locations
306// for a second pair of DRAMs. (Thanks, Apple!)
307// * 3400 has 1MB (I think). Don't know if it's expandable.
308// -- Tim Seufert
309 .smem_len = 0x100000, /* 1MB */
310};
311
48c68c4f 312static struct fb_var_screeninfo chipsfb_var = {
1da177e4
LT
313 .xres = 800,
314 .yres = 600,
315 .xres_virtual = 800,
316 .yres_virtual = 600,
317 .bits_per_pixel = 8,
318 .red = { .length = 8 },
319 .green = { .length = 8 },
320 .blue = { .length = 8 },
321 .height = -1,
322 .width = -1,
323 .vmode = FB_VMODE_NONINTERLACED,
324 .pixclock = 10000,
325 .left_margin = 16,
326 .right_margin = 16,
327 .upper_margin = 16,
328 .lower_margin = 16,
329 .hsync_len = 8,
330 .vsync_len = 8,
331};
332
48c68c4f 333static void init_chips(struct fb_info *p, unsigned long addr)
1da177e4 334{
8c870933
BH
335 memset(p->screen_base, 0, 0x100000);
336
1da177e4
LT
337 p->fix = chipsfb_fix;
338 p->fix.smem_start = addr;
339
340 p->var = chipsfb_var;
341
342 p->fbops = &chipsfb_ops;
343 p->flags = FBINFO_DEFAULT;
344
345 fb_alloc_cmap(&p->cmap, 256, 0);
346
1da177e4
LT
347 chips_hw_init();
348}
349
48c68c4f 350static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
1da177e4 351{
8c870933 352 struct fb_info *p;
1da177e4
LT
353 unsigned long addr, size;
354 unsigned short cmd;
8c870933
BH
355 int rc = -ENODEV;
356
357 if (pci_enable_device(dp) < 0) {
358 dev_err(&dp->dev, "Cannot enable PCI device\n");
359 goto err_out;
360 }
1da177e4
LT
361
362 if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
8c870933 363 goto err_disable;
1da177e4
LT
364 addr = pci_resource_start(dp, 0);
365 size = pci_resource_len(dp, 0);
366 if (addr == 0)
8c870933
BH
367 goto err_disable;
368
369 p = framebuffer_alloc(0, &dp->dev);
370 if (p == NULL) {
371 dev_err(&dp->dev, "Cannot allocate framebuffer structure\n");
372 rc = -ENOMEM;
373 goto err_disable;
374 }
375
376 if (pci_request_region(dp, 0, "chipsfb") != 0) {
377 dev_err(&dp->dev, "Cannot request framebuffer\n");
378 rc = -EBUSY;
379 goto err_release_fb;
380 }
1da177e4
LT
381
382#ifdef __BIG_ENDIAN
383 addr += 0x800000; // Use big-endian aperture
384#endif
385
386 /* we should use pci_enable_device here, but,
387 the device doesn't declare its I/O ports in its BARs
388 so pci_enable_device won't turn on I/O responses */
389 pci_read_config_word(dp, PCI_COMMAND, &cmd);
390 cmd |= 3; /* enable memory and IO space */
391 pci_write_config_word(dp, PCI_COMMAND, cmd);
392
393#ifdef CONFIG_PMAC_BACKLIGHT
394 /* turn on the backlight */
5474c120
MH
395 mutex_lock(&pmac_backlight_mutex);
396 if (pmac_backlight) {
599a52d1 397 pmac_backlight->props.power = FB_BLANK_UNBLANK;
28ee086d 398 backlight_update_status(pmac_backlight);
5474c120
MH
399 }
400 mutex_unlock(&pmac_backlight_mutex);
1da177e4
LT
401#endif /* CONFIG_PMAC_BACKLIGHT */
402
8c870933 403#ifdef CONFIG_PPC
1da177e4 404 p->screen_base = __ioremap(addr, 0x200000, _PAGE_NO_CACHE);
8c870933
BH
405#else
406 p->screen_base = ioremap(addr, 0x200000);
407#endif
1da177e4 408 if (p->screen_base == NULL) {
8c870933
BH
409 dev_err(&dp->dev, "Cannot map framebuffer\n");
410 rc = -ENOMEM;
411 goto err_release_pci;
1da177e4 412 }
8c870933
BH
413
414 pci_set_drvdata(dp, p);
8c870933 415
1da177e4
LT
416 init_chips(p, addr);
417
8c870933
BH
418 if (register_framebuffer(p) < 0) {
419 dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");
420 goto err_unmap;
421 }
422
423 dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"
424 " (%dK RAM detected)\n",
425 p->node, p->fix.smem_len / 1024);
1da177e4 426
1da177e4 427 return 0;
8c870933
BH
428
429 err_unmap:
430 iounmap(p->screen_base);
431 err_release_pci:
432 pci_release_region(dp, 0);
433 err_release_fb:
434 framebuffer_release(p);
435 err_disable:
436 err_out:
437 return rc;
1da177e4
LT
438}
439
48c68c4f 440static void chipsfb_remove(struct pci_dev *dp)
1da177e4
LT
441{
442 struct fb_info *p = pci_get_drvdata(dp);
443
8c870933 444 if (p->screen_base == NULL)
1da177e4
LT
445 return;
446 unregister_framebuffer(p);
447 iounmap(p->screen_base);
448 p->screen_base = NULL;
8c870933
BH
449 pci_release_region(dp, 0);
450}
451
452#ifdef CONFIG_PM
453static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
454{
455 struct fb_info *p = pci_get_drvdata(pdev);
456
ca078bae 457 if (state.event == pdev->dev.power.power_state.event)
8c870933 458 return 0;
3a2d5b70 459 if (!(state.event & PM_EVENT_SLEEP))
8c870933
BH
460 goto done;
461
ac751efa 462 console_lock();
8c870933
BH
463 chipsfb_blank(1, p);
464 fb_set_suspend(p, 1);
ac751efa 465 console_unlock();
8c870933
BH
466 done:
467 pdev->dev.power.power_state = state;
468 return 0;
469}
470
471static int chipsfb_pci_resume(struct pci_dev *pdev)
472{
473 struct fb_info *p = pci_get_drvdata(pdev);
1da177e4 474
ac751efa 475 console_lock();
8c870933
BH
476 fb_set_suspend(p, 0);
477 chipsfb_blank(0, p);
ac751efa 478 console_unlock();
8c870933
BH
479
480 pdev->dev.power.power_state = PMSG_ON;
481 return 0;
1da177e4 482}
8c870933
BH
483#endif /* CONFIG_PM */
484
1da177e4
LT
485
486static struct pci_device_id chipsfb_pci_tbl[] = {
487 { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },
488 { 0 }
489};
490
491MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);
492
493static struct pci_driver chipsfb_driver = {
494 .name = "chipsfb",
495 .id_table = chipsfb_pci_tbl,
496 .probe = chipsfb_pci_init,
48c68c4f 497 .remove = chipsfb_remove,
8c870933
BH
498#ifdef CONFIG_PM
499 .suspend = chipsfb_pci_suspend,
500 .resume = chipsfb_pci_resume,
501#endif
1da177e4
LT
502};
503
504int __init chips_init(void)
505{
506 if (fb_get_options("chipsfb", NULL))
507 return -ENODEV;
508
509 return pci_register_driver(&chipsfb_driver);
510}
511
512module_init(chips_init);
513
514static void __exit chipsfb_exit(void)
515{
516 pci_unregister_driver(&chipsfb_driver);
517}
518
1da177e4 519MODULE_LICENSE("GPL");