[mirror_ubuntu-zesty-kernel.git] / drivers / video / chipsfb.c

/*
 *  drivers/video/chipsfb.c -- frame buffer device for
 *  Chips & Technologies 65550 chip.
 *
 *  Copyright (C) 1998-2002 Paul Mackerras
 *
 *  This file is derived from the Powermac "chips" driver:
 *  Copyright (C) 1997 Fabio Riccardi.
 *  And from the frame buffer device for Open Firmware-initialized devices:
 *  Copyright (C) 1997 Geert Uytterhoeven.
 *
 *  This file is subject to the terms and conditions of the GNU General Public
 *  License. See the file COPYING in the main directory of this archive for
 *  more details.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fb.h>
#include <linux/pm.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/console.h>
#include <asm/io.h>

#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif

/*
 * Since we access the display with inb/outb to fixed port numbers,
 * we can only handle one 6555x chip.  -- paulus
 */
#define write_ind(num, val, ap, dp)	do { \
	outb((num), (ap)); outb((val), (dp)); \
} while (0)
#define read_ind(num, var, ap, dp)	do { \
	outb((num), (ap)); var = inb((dp)); \
} while (0)

/* extension registers */
#define write_xr(num, val)	write_ind(num, val, 0x3d6, 0x3d7)
#define read_xr(num, var)	read_ind(num, var, 0x3d6, 0x3d7)
/* flat panel registers */
#define write_fr(num, val)	write_ind(num, val, 0x3d0, 0x3d1)
#define read_fr(num, var)	read_ind(num, var, 0x3d0, 0x3d1)
/* CRTC registers */
#define write_cr(num, val)	write_ind(num, val, 0x3d4, 0x3d5)
#define read_cr(num, var)	read_ind(num, var, 0x3d4, 0x3d5)
/* graphics registers */
#define write_gr(num, val)	write_ind(num, val, 0x3ce, 0x3cf)
#define read_gr(num, var)	read_ind(num, var, 0x3ce, 0x3cf)
/* sequencer registers */
#define write_sr(num, val)	write_ind(num, val, 0x3c4, 0x3c5)
#define read_sr(num, var)	read_ind(num, var, 0x3c4, 0x3c5)
/* attribute registers - slightly strange */
#define write_ar(num, val)	do { \
	inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \
} while (0)
#define read_ar(num, var)	do { \
	inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \
} while (0)

/*
 * Exported functions
 */
int chips_init(void);

static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
static int chipsfb_check_var(struct fb_var_screeninfo *var,
			     struct fb_info *info);
static int chipsfb_set_par(struct fb_info *info);
static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
			     u_int transp, struct fb_info *info);
static int chipsfb_blank(int blank, struct fb_info *info);

static struct fb_ops chipsfb_ops = {
	.owner		= THIS_MODULE,
	.fb_check_var	= chipsfb_check_var,
	.fb_set_par	= chipsfb_set_par,
	.fb_setcolreg	= chipsfb_setcolreg,
	.fb_blank	= chipsfb_blank,
	.fb_fillrect	= cfb_fillrect,
	.fb_copyarea	= cfb_copyarea,
	.fb_imageblit	= cfb_imageblit,
};

static int chipsfb_check_var(struct fb_var_screeninfo *var,
			     struct fb_info *info)
{
	if (var->xres > 800 || var->yres > 600
	    || var->xres_virtual > 800 || var->yres_virtual > 600
	    || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)
	    || var->nonstd
	    || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
		return -EINVAL;

	var->xres = var->xres_virtual = 800;
	var->yres = var->yres_virtual = 600;

	return 0;
}

static int chipsfb_set_par(struct fb_info *info)
{
	if (info->var.bits_per_pixel == 16) {
		write_cr(0x13, 200);		// Set line length (doublewords)
		write_xr(0x81, 0x14);		// 15 bit (555) color mode
		write_xr(0x82, 0x00);		// Disable palettes
		write_xr(0x20, 0x10);		// 16 bit blitter mode

		info->fix.line_length = 800*2;
		info->fix.visual = FB_VISUAL_TRUECOLOR;

		info->var.red.offset = 10;
		info->var.green.offset = 5;
		info->var.blue.offset = 0;
		info->var.red.length = info->var.green.length =
			info->var.blue.length = 5;
		
	} else {
		/* p->var.bits_per_pixel == 8 */
		write_cr(0x13, 100);		// Set line length (doublewords)
		write_xr(0x81, 0x12);		// 8 bit color mode
		write_xr(0x82, 0x08);		// Graphics gamma enable
		write_xr(0x20, 0x00);		// 8 bit blitter mode

		info->fix.line_length = 800;
		info->fix.visual = FB_VISUAL_PSEUDOCOLOR;		

 		info->var.red.offset = info->var.green.offset =
			info->var.blue.offset = 0;
		info->var.red.length = info->var.green.length =
			info->var.blue.length = 8;
		
	}
	return 0;
}

static int chipsfb_blank(int blank, struct fb_info *info)
{
	return 1;	/* get fb_blank to set the colormap to all black */
}

static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
			     u_int transp, struct fb_info *info)
{
	if (regno > 255)
		return 1;
	red >>= 8;
	green >>= 8;
	blue >>= 8;
	outb(regno, 0x3c8);
	udelay(1);
	outb(red, 0x3c9);
	outb(green, 0x3c9);
	outb(blue, 0x3c9);

	return 0;
}

struct chips_init_reg {
	unsigned char addr;
	unsigned char data;
};

static struct chips_init_reg chips_init_sr[] = {
	{ 0x00, 0x03 },
	{ 0x01, 0x01 },
	{ 0x02, 0x0f },
	{ 0x04, 0x0e }
};

static struct chips_init_reg chips_init_gr[] = {
	{ 0x05, 0x00 },
	{ 0x06, 0x0d },
	{ 0x08, 0xff }
};

static struct chips_init_reg chips_init_ar[] = {
	{ 0x10, 0x01 },
	{ 0x12, 0x0f },
	{ 0x13, 0x00 }
};

static struct chips_init_reg chips_init_cr[] = {
	{ 0x00, 0x7f },
	{ 0x01, 0x63 },
	{ 0x02, 0x63 },
	{ 0x03, 0x83 },
	{ 0x04, 0x66 },
	{ 0x05, 0x10 },
	{ 0x06, 0x72 },
	{ 0x07, 0x3e },
	{ 0x08, 0x00 },
	{ 0x09, 0x40 },
	{ 0x0c, 0x00 },
	{ 0x0d, 0x00 },
	{ 0x10, 0x59 },
	{ 0x11, 0x0d },
	{ 0x12, 0x57 },
	{ 0x13, 0x64 },
	{ 0x14, 0x00 },
	{ 0x15, 0x57 },
	{ 0x16, 0x73 },
	{ 0x17, 0xe3 },
	{ 0x18, 0xff },
	{ 0x30, 0x02 },
	{ 0x31, 0x02 },
	{ 0x32, 0x02 },
	{ 0x33, 0x02 },
	{ 0x40, 0x00 },
	{ 0x41, 0x00 },
	{ 0x40, 0x80 }
};

static struct chips_init_reg chips_init_fr[] = {
	{ 0x01, 0x02 },
	{ 0x03, 0x08 },
	{ 0x04, 0x81 },
	{ 0x05, 0x21 },
	{ 0x08, 0x0c },
	{ 0x0a, 0x74 },
	{ 0x0b, 0x11 },
	{ 0x10, 0x0c },
	{ 0x11, 0xe0 },
	/* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */
	{ 0x20, 0x63 },
	{ 0x21, 0x68 },
	{ 0x22, 0x19 },
	{ 0x23, 0x7f },
	{ 0x24, 0x68 },
	{ 0x26, 0x00 },
	{ 0x27, 0x0f },
	{ 0x30, 0x57 },
	{ 0x31, 0x58 },
	{ 0x32, 0x0d },
	{ 0x33, 0x72 },
	{ 0x34, 0x02 },
	{ 0x35, 0x22 },
	{ 0x36, 0x02 },
	{ 0x37, 0x00 }
};

static struct chips_init_reg chips_init_xr[] = {
	{ 0xce, 0x00 },		/* set default memory clock */
	{ 0xcc, 0x43 },		/* memory clock ratio */
	{ 0xcd, 0x18 },
	{ 0xce, 0xa1 },
	{ 0xc8, 0x84 },
	{ 0xc9, 0x0a },
	{ 0xca, 0x00 },
	{ 0xcb, 0x20 },
	{ 0xcf, 0x06 },
	{ 0xd0, 0x0e },
	{ 0x09, 0x01 },
	{ 0x0a, 0x02 },
	{ 0x0b, 0x01 },
	{ 0x20, 0x00 },
	{ 0x40, 0x03 },
	{ 0x41, 0x01 },
	{ 0x42, 0x00 },
	{ 0x80, 0x82 },
	{ 0x81, 0x12 },
	{ 0x82, 0x08 },
	{ 0xa0, 0x00 },
	{ 0xa8, 0x00 }
};

static void __init chips_hw_init(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
		write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
	outb(0x29, 0x3c2); /* set misc output reg */
	for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
		write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
	for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
		write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
	for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
		write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
	for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
		write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
	for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
		write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
}

static struct fb_fix_screeninfo chipsfb_fix = {
	.id =		"C&T 65550",
	.type =		FB_TYPE_PACKED_PIXELS,
	.visual =	FB_VISUAL_PSEUDOCOLOR,
	.accel =	FB_ACCEL_NONE,
	.line_length =	800,

// FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.
// * "3500" PowerBook G3 (the original PB G3) has 2MB.
// * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.
//   Motherboard actually supports 2MB -- there are two blank locations
//   for a second pair of DRAMs.  (Thanks, Apple!)
// * 3400 has 1MB (I think).  Don't know if it's expandable.
// -- Tim Seufert
	.smem_len =	0x100000,	/* 1MB */
};

static struct fb_var_screeninfo chipsfb_var = {
	.xres = 800,
	.yres = 600,
	.xres_virtual = 800,
	.yres_virtual = 600,
	.bits_per_pixel = 8,
	.red = { .length = 8 },
	.green = { .length = 8 },
	.blue = { .length = 8 },
	.height = -1,
	.width = -1,
	.vmode = FB_VMODE_NONINTERLACED,
	.pixclock = 10000,
	.left_margin = 16,
	.right_margin = 16,
	.upper_margin = 16,
	.lower_margin = 16,
	.hsync_len = 8,
	.vsync_len = 8,
};

static void init_chips(struct fb_info *p, unsigned long addr)
{
	memset(p->screen_base, 0, 0x100000);

	p->fix = chipsfb_fix;
	p->fix.smem_start = addr;

	p->var = chipsfb_var;

	p->fbops = &chipsfb_ops;
	p->flags = FBINFO_DEFAULT;

	fb_alloc_cmap(&p->cmap, 256, 0);

	chips_hw_init();
}

static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
{
	struct fb_info *p;
	unsigned long addr, size;
	unsigned short cmd;
	int rc = -ENODEV;

	if (pci_enable_device(dp) < 0) {
		dev_err(&dp->dev, "Cannot enable PCI device\n");
		goto err_out;
	}

	if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
		goto err_disable;
	addr = pci_resource_start(dp, 0);
	size = pci_resource_len(dp, 0);
	if (addr == 0)
		goto err_disable;

	p = framebuffer_alloc(0, &dp->dev);
	if (p == NULL) {
		dev_err(&dp->dev, "Cannot allocate framebuffer structure\n");
		rc = -ENOMEM;
		goto err_disable;
	}

	if (pci_request_region(dp, 0, "chipsfb") != 0) {
		dev_err(&dp->dev, "Cannot request framebuffer\n");
		rc = -EBUSY;
		goto err_release_fb;
	}

#ifdef __BIG_ENDIAN
	addr += 0x800000;	// Use big-endian aperture
#endif

	/* we should use pci_enable_device here, but,
	   the device doesn't declare its I/O ports in its BARs
	   so pci_enable_device won't turn on I/O responses */
	pci_read_config_word(dp, PCI_COMMAND, &cmd);
	cmd |= 3;	/* enable memory and IO space */
	pci_write_config_word(dp, PCI_COMMAND, cmd);

#ifdef CONFIG_PMAC_BACKLIGHT
	/* turn on the backlight */
	mutex_lock(&pmac_backlight_mutex);
	if (pmac_backlight) {
		pmac_backlight->props.power = FB_BLANK_UNBLANK;
		backlight_update_status(pmac_backlight);
	}
	mutex_unlock(&pmac_backlight_mutex);
#endif /* CONFIG_PMAC_BACKLIGHT */

#ifdef CONFIG_PPC
	p->screen_base = __ioremap(addr, 0x200000, _PAGE_NO_CACHE);
#else
	p->screen_base = ioremap(addr, 0x200000);
#endif
	if (p->screen_base == NULL) {
		dev_err(&dp->dev, "Cannot map framebuffer\n");
		rc = -ENOMEM;
		goto err_release_pci;
	}

	pci_set_drvdata(dp, p);

	init_chips(p, addr);

	if (register_framebuffer(p) < 0) {
		dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");
		goto err_unmap;
	}

	dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"
		 " (%dK RAM detected)\n",
		 p->node, p->fix.smem_len / 1024);

	return 0;

 err_unmap:
	iounmap(p->screen_base);
 err_release_pci:
	pci_release_region(dp, 0);
 err_release_fb:
	framebuffer_release(p);
 err_disable:
 err_out:
	return rc;
}

static void chipsfb_remove(struct pci_dev *dp)
{
	struct fb_info *p = pci_get_drvdata(dp);

	if (p->screen_base == NULL)
		return;
	unregister_framebuffer(p);
	iounmap(p->screen_base);
	p->screen_base = NULL;
	pci_release_region(dp, 0);
}

#ifdef CONFIG_PM
static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
{
        struct fb_info *p = pci_get_drvdata(pdev);

	if (state.event == pdev->dev.power.power_state.event)
		return 0;
	if (!(state.event & PM_EVENT_SLEEP))
		goto done;

	console_lock();
	chipsfb_blank(1, p);
	fb_set_suspend(p, 1);
	console_unlock();
 done:
	pdev->dev.power.power_state = state;
	return 0;
}

static int chipsfb_pci_resume(struct pci_dev *pdev)
{
        struct fb_info *p = pci_get_drvdata(pdev);

	console_lock();
	fb_set_suspend(p, 0);
	chipsfb_blank(0, p);
	console_unlock();

	pdev->dev.power.power_state = PMSG_ON;
	return 0;
}
#endif /* CONFIG_PM */


static struct pci_device_id chipsfb_pci_tbl[] = {
	{ PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },
	{ 0 }
};

MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);

static struct pci_driver chipsfb_driver = {
	.name =		"chipsfb",
	.id_table =	chipsfb_pci_tbl,
	.probe =	chipsfb_pci_init,
	.remove =	chipsfb_remove,
#ifdef CONFIG_PM
	.suspend =	chipsfb_pci_suspend,
	.resume =	chipsfb_pci_resume,
#endif
};

int __init chips_init(void)
{
	if (fb_get_options("chipsfb", NULL))
		return -ENODEV;

	return pci_register_driver(&chipsfb_driver);
}

module_init(chips_init);

static void __exit chipsfb_exit(void)
{
	pci_unregister_driver(&chipsfb_driver);
}

MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/video/chipsfb.c -- frame buffer device for
	3	* Chips & Technologies 65550 chip.
	4	*
	5	* Copyright (C) 1998-2002 Paul Mackerras
	6	*
	7	* This file is derived from the Powermac "chips" driver:
	8	* Copyright (C) 1997 Fabio Riccardi.
	9	* And from the frame buffer device for Open Firmware-initialized devices:
	10	* Copyright (C) 1997 Geert Uytterhoeven.
	11	*
	12	* This file is subject to the terms and conditions of the GNU General Public
	13	* License. See the file COPYING in the main directory of this archive for
	14	* more details.
	15	*/
	16
1da177e4 LT	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/errno.h>
	20	#include <linux/string.h>
	21	#include <linux/mm.h>
1da177e4 LT	22	#include <linux/vmalloc.h>
	23	#include <linux/delay.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/fb.h>
26b97237	26	#include <linux/pm.h>
1da177e4 LT	27	#include <linux/init.h>
1da177e4 LT	28	#include <linux/pci.h>
8c870933	29	#include <linux/console.h>
1da177e4 LT	30	#include <asm/io.h>
	31
	32	#ifdef CONFIG_PMAC_BACKLIGHT
	33	#include <asm/backlight.h>
	34	#endif
1da177e4 LT	35
	36	/*
	37	* Since we access the display with inb/outb to fixed port numbers,
	38	* we can only handle one 6555x chip. -- paulus
	39	*/
1da177e4 LT	40	#define write_ind(num, val, ap, dp) do { \
	41	outb((num), (ap)); outb((val), (dp)); \
	42	} while (0)
	43	#define read_ind(num, var, ap, dp) do { \
	44	outb((num), (ap)); var = inb((dp)); \
	45	} while (0)
	46
	47	/* extension registers */
	48	#define write_xr(num, val) write_ind(num, val, 0x3d6, 0x3d7)
	49	#define read_xr(num, var) read_ind(num, var, 0x3d6, 0x3d7)
	50	/* flat panel registers */
	51	#define write_fr(num, val) write_ind(num, val, 0x3d0, 0x3d1)
	52	#define read_fr(num, var) read_ind(num, var, 0x3d0, 0x3d1)
	53	/* CRTC registers */
	54	#define write_cr(num, val) write_ind(num, val, 0x3d4, 0x3d5)
	55	#define read_cr(num, var) read_ind(num, var, 0x3d4, 0x3d5)
	56	/* graphics registers */
	57	#define write_gr(num, val) write_ind(num, val, 0x3ce, 0x3cf)
	58	#define read_gr(num, var) read_ind(num, var, 0x3ce, 0x3cf)
	59	/* sequencer registers */
	60	#define write_sr(num, val) write_ind(num, val, 0x3c4, 0x3c5)
	61	#define read_sr(num, var) read_ind(num, var, 0x3c4, 0x3c5)
	62	/* attribute registers - slightly strange */
	63	#define write_ar(num, val) do { \
	64	inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \
	65	} while (0)
	66	#define read_ar(num, var) do { \
	67	inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \
	68	} while (0)
	69
1da177e4 LT	70	/*
	71	* Exported functions
	72	*/
	73	int chips_init(void);
	74
	75	static int chipsfb_pci_init(struct pci_dev dp, const struct pci_device_id );
	76	static int chipsfb_check_var(struct fb_var_screeninfo *var,
	77	struct fb_info *info);
	78	static int chipsfb_set_par(struct fb_info *info);
	79	static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
	80	u_int transp, struct fb_info *info);
	81	static int chipsfb_blank(int blank, struct fb_info *info);
	82
	83	static struct fb_ops chipsfb_ops = {
	84	.owner = THIS_MODULE,
	85	.fb_check_var = chipsfb_check_var,
	86	.fb_set_par = chipsfb_set_par,
	87	.fb_setcolreg = chipsfb_setcolreg,
	88	.fb_blank = chipsfb_blank,
	89	.fb_fillrect = cfb_fillrect,
	90	.fb_copyarea = cfb_copyarea,
	91	.fb_imageblit = cfb_imageblit,
1da177e4 LT	92	};
	93
	94	static int chipsfb_check_var(struct fb_var_screeninfo *var,
	95	struct fb_info *info)
	96	{
	97	if (var->xres > 800 \|\| var->yres > 600
	98	\|\| var->xres_virtual > 800 \|\| var->yres_virtual > 600
	99	\|\| (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)
	100	\|\| var->nonstd
	101	\|\| (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
	102	return -EINVAL;
	103
	104	var->xres = var->xres_virtual = 800;
	105	var->yres = var->yres_virtual = 600;
	106
	107	return 0;
	108	}
	109
	110	static int chipsfb_set_par(struct fb_info *info)
	111	{
	112	if (info->var.bits_per_pixel == 16) {
	113	write_cr(0x13, 200); // Set line length (doublewords)
	114	write_xr(0x81, 0x14); // 15 bit (555) color mode
	115	write_xr(0x82, 0x00); // Disable palettes
	116	write_xr(0x20, 0x10); // 16 bit blitter mode
	117
	118	info->fix.line_length = 800*2;
	119	info->fix.visual = FB_VISUAL_TRUECOLOR;
	120
	121	info->var.red.offset = 10;
	122	info->var.green.offset = 5;
	123	info->var.blue.offset = 0;
	124	info->var.red.length = info->var.green.length =
	125	info->var.blue.length = 5;
	126
	127	} else {
	128	/* p->var.bits_per_pixel == 8 */
	129	write_cr(0x13, 100); // Set line length (doublewords)
	130	write_xr(0x81, 0x12); // 8 bit color mode
	131	write_xr(0x82, 0x08); // Graphics gamma enable
	132	write_xr(0x20, 0x00); // 8 bit blitter mode
	133
	134	info->fix.line_length = 800;
	135	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
	136
	137	info->var.red.offset = info->var.green.offset =
	138	info->var.blue.offset = 0;
	139	info->var.red.length = info->var.green.length =
	140	info->var.blue.length = 8;
	141
	142	}
	143	return 0;
	144	}
	145
	146	static int chipsfb_blank(int blank, struct fb_info *info)
	147	{
1da177e4 LT	148	return 1; /* get fb_blank to set the colormap to all black */
	149	}
	150
	151	static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
	152	u_int transp, struct fb_info *info)
	153	{
	154	if (regno > 255)
	155	return 1;
	156	red >>= 8;
	157	green >>= 8;
	158	blue >>= 8;
	159	outb(regno, 0x3c8);
	160	udelay(1);
	161	outb(red, 0x3c9);
	162	outb(green, 0x3c9);
	163	outb(blue, 0x3c9);
	164
	165	return 0;
	166	}
	167
	168	struct chips_init_reg {
	169	unsigned char addr;
	170	unsigned char data;
	171	};
	172
1da177e4 LT	173	static struct chips_init_reg chips_init_sr[] = {
	174	{ 0x00, 0x03 },
	175	{ 0x01, 0x01 },
	176	{ 0x02, 0x0f },
	177	{ 0x04, 0x0e }
	178	};
	179
	180	static struct chips_init_reg chips_init_gr[] = {
	181	{ 0x05, 0x00 },
	182	{ 0x06, 0x0d },
	183	{ 0x08, 0xff }
	184	};
	185
	186	static struct chips_init_reg chips_init_ar[] = {
	187	{ 0x10, 0x01 },
	188	{ 0x12, 0x0f },
	189	{ 0x13, 0x00 }
	190	};
	191
	192	static struct chips_init_reg chips_init_cr[] = {
	193	{ 0x00, 0x7f },
	194	{ 0x01, 0x63 },
	195	{ 0x02, 0x63 },
	196	{ 0x03, 0x83 },
	197	{ 0x04, 0x66 },
	198	{ 0x05, 0x10 },
	199	{ 0x06, 0x72 },
	200	{ 0x07, 0x3e },
	201	{ 0x08, 0x00 },
	202	{ 0x09, 0x40 },
	203	{ 0x0c, 0x00 },
	204	{ 0x0d, 0x00 },
	205	{ 0x10, 0x59 },
	206	{ 0x11, 0x0d },
	207	{ 0x12, 0x57 },
	208	{ 0x13, 0x64 },
	209	{ 0x14, 0x00 },
	210	{ 0x15, 0x57 },
	211	{ 0x16, 0x73 },
	212	{ 0x17, 0xe3 },
	213	{ 0x18, 0xff },
	214	{ 0x30, 0x02 },
	215	{ 0x31, 0x02 },
	216	{ 0x32, 0x02 },
	217	{ 0x33, 0x02 },
	218	{ 0x40, 0x00 },
	219	{ 0x41, 0x00 },
	220	{ 0x40, 0x80 }
	221	};
	222
	223	static struct chips_init_reg chips_init_fr[] = {
	224	{ 0x01, 0x02 },
	225	{ 0x03, 0x08 },
	226	{ 0x04, 0x81 },
	227	{ 0x05, 0x21 },
	228	{ 0x08, 0x0c },
	229	{ 0x0a, 0x74 },
	230	{ 0x0b, 0x11 },
	231	{ 0x10, 0x0c },
	232	{ 0x11, 0xe0 },
	233	/* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */
	234	{ 0x20, 0x63 },
	235	{ 0x21, 0x68 },
	236	{ 0x22, 0x19 },
237	{ 0x23, 0x7f },
238	{ 0x24, 0x68 },
239	{ 0x26, 0x00 },
240	{ 0x27, 0x0f },
241	{ 0x30, 0x57 },
242	{ 0x31, 0x58 },
243	{ 0x32, 0x0d },
244	{ 0x33, 0x72 },
245	{ 0x34, 0x02 },
246	{ 0x35, 0x22 },
247	{ 0x36, 0x02 },
248	{ 0x37, 0x00 }
249	};
250
251	static struct chips_init_reg chips_init_xr[] = {
252	{ 0xce, 0x00 }, /* set default memory clock */
253	{ 0xcc, 0x43 }, /* memory clock ratio */
254	{ 0xcd, 0x18 },
255	{ 0xce, 0xa1 },
256	{ 0xc8, 0x84 },
257	{ 0xc9, 0x0a },
258	{ 0xca, 0x00 },
259	{ 0xcb, 0x20 },
260	{ 0xcf, 0x06 },
261	{ 0xd0, 0x0e },
262	{ 0x09, 0x01 },
263	{ 0x0a, 0x02 },
264	{ 0x0b, 0x01 },
265	{ 0x20, 0x00 },
266	{ 0x40, 0x03 },
267	{ 0x41, 0x01 },
268	{ 0x42, 0x00 },
269	{ 0x80, 0x82 },
270	{ 0x81, 0x12 },
271	{ 0x82, 0x08 },
272	{ 0xa0, 0x00 },
273	{ 0xa8, 0x00 }
274	};
275
276	static void __init chips_hw_init(void)
277	{
278	int i;
279
d1ae418e	280	for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
1da177e4 LT	281	write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
1da177e4 LT	282	outb(0x29, 0x3c2); /* set misc output reg */
d1ae418e	283	for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
1da177e4	284	write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
d1ae418e	285	for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
1da177e4	286	write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
d1ae418e	287	for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
1da177e4	288	write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
d1ae418e	289	for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
1da177e4	290	write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
d1ae418e	291	for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
1da177e4 LT	292	write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
	293	}
	294
48c68c4f	295	static struct fb_fix_screeninfo chipsfb_fix = {
1da177e4 LT	296	.id = "C&T 65550",
	297	.type = FB_TYPE_PACKED_PIXELS,
	298	.visual = FB_VISUAL_PSEUDOCOLOR,
	299	.accel = FB_ACCEL_NONE,
	300	.line_length = 800,
	301
	302	// FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.
	303	// * "3500" PowerBook G3 (the original PB G3) has 2MB.
	304	// * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.
	305	// Motherboard actually supports 2MB -- there are two blank locations
	306	// for a second pair of DRAMs. (Thanks, Apple!)
	307	// * 3400 has 1MB (I think). Don't know if it's expandable.
	308	// -- Tim Seufert
	309	.smem_len = 0x100000, /* 1MB */
	310	};
	311
48c68c4f	312	static struct fb_var_screeninfo chipsfb_var = {
1da177e4 LT	313	.xres = 800,
	314	.yres = 600,
	315	.xres_virtual = 800,
	316	.yres_virtual = 600,
	317	.bits_per_pixel = 8,
	318	.red = { .length = 8 },
	319	.green = { .length = 8 },
	320	.blue = { .length = 8 },
	321	.height = -1,
	322	.width = -1,
	323	.vmode = FB_VMODE_NONINTERLACED,
	324	.pixclock = 10000,
	325	.left_margin = 16,
	326	.right_margin = 16,
	327	.upper_margin = 16,
	328	.lower_margin = 16,
	329	.hsync_len = 8,
	330	.vsync_len = 8,
	331	};
	332
48c68c4f	333	static void init_chips(struct fb_info *p, unsigned long addr)
1da177e4	334	{
8c870933 BH	335	memset(p->screen_base, 0, 0x100000);
8c870933 BH	336
1da177e4 LT	337	p->fix = chipsfb_fix;
	338	p->fix.smem_start = addr;
	339
	340	p->var = chipsfb_var;
	341
	342	p->fbops = &chipsfb_ops;
	343	p->flags = FBINFO_DEFAULT;
	344
	345	fb_alloc_cmap(&p->cmap, 256, 0);
	346
1da177e4 LT	347	chips_hw_init();
	348	}
	349
48c68c4f	350	static int chipsfb_pci_init(struct pci_dev dp, const struct pci_device_id ent)
1da177e4	351	{
8c870933	352	struct fb_info *p;
1da177e4 LT	353	unsigned long addr, size;
1da177e4 LT	354	unsigned short cmd;
8c870933 BH	355	int rc = -ENODEV;
	356
	357	if (pci_enable_device(dp) < 0) {
	358	dev_err(&dp->dev, "Cannot enable PCI device\n");
	359	goto err_out;
	360	}
1da177e4 LT	361
1da177e4 LT	362	if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
8c870933	363	goto err_disable;
1da177e4 LT	364	addr = pci_resource_start(dp, 0);
	365	size = pci_resource_len(dp, 0);
	366	if (addr == 0)
8c870933 BH	367	goto err_disable;
	368
	369	p = framebuffer_alloc(0, &dp->dev);
	370	if (p == NULL) {
	371	dev_err(&dp->dev, "Cannot allocate framebuffer structure\n");
	372	rc = -ENOMEM;
	373	goto err_disable;
	374	}
	375
	376	if (pci_request_region(dp, 0, "chipsfb") != 0) {
	377	dev_err(&dp->dev, "Cannot request framebuffer\n");
	378	rc = -EBUSY;
	379	goto err_release_fb;
	380	}
1da177e4 LT	381
	382	#ifdef __BIG_ENDIAN
	383	addr += 0x800000; // Use big-endian aperture
	384	#endif
	385
	386	/* we should use pci_enable_device here, but,
	387	the device doesn't declare its I/O ports in its BARs
	388	so pci_enable_device won't turn on I/O responses */
	389	pci_read_config_word(dp, PCI_COMMAND, &cmd);
	390	cmd \|= 3; /* enable memory and IO space */
	391	pci_write_config_word(dp, PCI_COMMAND, cmd);
	392
	393	#ifdef CONFIG_PMAC_BACKLIGHT
	394	/* turn on the backlight */
5474c120 MH	395	mutex_lock(&pmac_backlight_mutex);
5474c120 MH	396	if (pmac_backlight) {
599a52d1	397	pmac_backlight->props.power = FB_BLANK_UNBLANK;
28ee086d	398	backlight_update_status(pmac_backlight);
5474c120 MH	399	}
5474c120 MH	400	mutex_unlock(&pmac_backlight_mutex);
1da177e4 LT	401	#endif /* CONFIG_PMAC_BACKLIGHT */
1da177e4 LT	402
8c870933	403	#ifdef CONFIG_PPC
1da177e4	404	p->screen_base = __ioremap(addr, 0x200000, _PAGE_NO_CACHE);
8c870933 BH	405	#else
	406	p->screen_base = ioremap(addr, 0x200000);
	407	#endif
1da177e4	408	if (p->screen_base == NULL) {
8c870933 BH	409	dev_err(&dp->dev, "Cannot map framebuffer\n");
	410	rc = -ENOMEM;
	411	goto err_release_pci;
1da177e4	412	}
8c870933 BH	413
8c870933 BH	414	pci_set_drvdata(dp, p);
8c870933	415
1da177e4 LT	416	init_chips(p, addr);
1da177e4 LT	417
8c870933 BH	418	if (register_framebuffer(p) < 0) {
	419	dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");
	420	goto err_unmap;
	421	}
	422
	423	dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"
	424	" (%dK RAM detected)\n",
	425	p->node, p->fix.smem_len / 1024);
1da177e4	426
1da177e4	427	return 0;
8c870933 BH	428
	429	err_unmap:
	430	iounmap(p->screen_base);
	431	err_release_pci:
	432	pci_release_region(dp, 0);
	433	err_release_fb:
	434	framebuffer_release(p);
	435	err_disable:
	436	err_out:
	437	return rc;
1da177e4 LT	438	}
1da177e4 LT	439
48c68c4f	440	static void chipsfb_remove(struct pci_dev *dp)
1da177e4 LT	441	{
	442	struct fb_info *p = pci_get_drvdata(dp);
	443
8c870933	444	if (p->screen_base == NULL)
1da177e4 LT	445	return;
	446	unregister_framebuffer(p);
	447	iounmap(p->screen_base);
	448	p->screen_base = NULL;
8c870933 BH	449	pci_release_region(dp, 0);
	450	}
	451
	452	#ifdef CONFIG_PM
	453	static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
	454	{
	455	struct fb_info *p = pci_get_drvdata(pdev);
	456
ca078bae	457	if (state.event == pdev->dev.power.power_state.event)
8c870933	458	return 0;
3a2d5b70	459	if (!(state.event & PM_EVENT_SLEEP))
8c870933 BH	460	goto done;
8c870933 BH	461
ac751efa	462	console_lock();
8c870933 BH	463	chipsfb_blank(1, p);
8c870933 BH	464	fb_set_suspend(p, 1);
ac751efa	465	console_unlock();
8c870933 BH	466	done:
	467	pdev->dev.power.power_state = state;
	468	return 0;
	469	}
	470
	471	static int chipsfb_pci_resume(struct pci_dev *pdev)
	472	{
	473	struct fb_info *p = pci_get_drvdata(pdev);
1da177e4	474
ac751efa	475	console_lock();
8c870933 BH	476	fb_set_suspend(p, 0);
8c870933 BH	477	chipsfb_blank(0, p);
ac751efa	478	console_unlock();
8c870933 BH	479
	480	pdev->dev.power.power_state = PMSG_ON;
	481	return 0;
1da177e4	482	}
8c870933 BH	483	#endif /* CONFIG_PM */
8c870933 BH	484
1da177e4 LT	485
	486	static struct pci_device_id chipsfb_pci_tbl[] = {
	487	{ PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },
	488	{ 0 }
	489	};
	490
	491	MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);
	492
	493	static struct pci_driver chipsfb_driver = {
	494	.name = "chipsfb",
	495	.id_table = chipsfb_pci_tbl,
	496	.probe = chipsfb_pci_init,
48c68c4f	497	.remove = chipsfb_remove,
8c870933 BH	498	#ifdef CONFIG_PM
	499	.suspend = chipsfb_pci_suspend,
	500	.resume = chipsfb_pci_resume,
	501	#endif
1da177e4 LT	502	};
	503
	504	int __init chips_init(void)
	505	{
	506	if (fb_get_options("chipsfb", NULL))
	507	return -ENODEV;
	508
	509	return pci_register_driver(&chipsfb_driver);
	510	}
	511
	512	module_init(chips_init);
	513
	514	static void __exit chipsfb_exit(void)
	515	{
	516	pci_unregister_driver(&chipsfb_driver);
	517	}
	518
1da177e4	519	MODULE_LICENSE("GPL");