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4ed824d9 SR |
1 | /* |
2 | * Copyright (C) 2008-2009 MontaVista Software Inc. | |
3 | * Copyright (C) 2008-2009 Texas Instruments Inc | |
4 | * | |
5 | * Based on the LCD driver for TI Avalanche processors written by | |
6 | * Ajay Singh and Shalom Hai. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option)any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #include <linux/module.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/fb.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/uaccess.h> | |
4ed824d9 SR |
29 | #include <linux/interrupt.h> |
30 | #include <linux/clk.h> | |
e04e5483 | 31 | #include <linux/cpufreq.h> |
1d3c6c7b | 32 | #include <linux/console.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
3b9cc4ea | 34 | #include <linux/lcm.h> |
4ed824d9 | 35 | #include <video/da8xx-fb.h> |
12fa8350 | 36 | #include <asm/div64.h> |
4ed824d9 SR |
37 | |
38 | #define DRIVER_NAME "da8xx_lcdc" | |
39 | ||
c6daf05b MP |
40 | #define LCD_VERSION_1 1 |
41 | #define LCD_VERSION_2 2 | |
42 | ||
4ed824d9 | 43 | /* LCD Status Register */ |
1f9c3e1f | 44 | #define LCD_END_OF_FRAME1 BIT(9) |
4ed824d9 | 45 | #define LCD_END_OF_FRAME0 BIT(8) |
1f9c3e1f | 46 | #define LCD_PL_LOAD_DONE BIT(6) |
4ed824d9 SR |
47 | #define LCD_FIFO_UNDERFLOW BIT(5) |
48 | #define LCD_SYNC_LOST BIT(2) | |
49 | ||
50 | /* LCD DMA Control Register */ | |
51 | #define LCD_DMA_BURST_SIZE(x) ((x) << 4) | |
52 | #define LCD_DMA_BURST_1 0x0 | |
53 | #define LCD_DMA_BURST_2 0x1 | |
54 | #define LCD_DMA_BURST_4 0x2 | |
55 | #define LCD_DMA_BURST_8 0x3 | |
56 | #define LCD_DMA_BURST_16 0x4 | |
c6daf05b MP |
57 | #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) |
58 | #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) | |
59 | #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) | |
4ed824d9 SR |
60 | #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) |
61 | ||
62 | /* LCD Control Register */ | |
63 | #define LCD_CLK_DIVISOR(x) ((x) << 8) | |
64 | #define LCD_RASTER_MODE 0x01 | |
65 | ||
66 | /* LCD Raster Control Register */ | |
67 | #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) | |
68 | #define PALETTE_AND_DATA 0x00 | |
69 | #define PALETTE_ONLY 0x01 | |
1f9c3e1f | 70 | #define DATA_ONLY 0x02 |
4ed824d9 SR |
71 | |
72 | #define LCD_MONO_8BIT_MODE BIT(9) | |
73 | #define LCD_RASTER_ORDER BIT(8) | |
74 | #define LCD_TFT_MODE BIT(7) | |
c6daf05b MP |
75 | #define LCD_V1_UNDERFLOW_INT_ENA BIT(6) |
76 | #define LCD_V2_UNDERFLOW_INT_ENA BIT(5) | |
77 | #define LCD_V1_PL_INT_ENA BIT(4) | |
78 | #define LCD_V2_PL_INT_ENA BIT(6) | |
4ed824d9 SR |
79 | #define LCD_MONOCHROME_MODE BIT(1) |
80 | #define LCD_RASTER_ENABLE BIT(0) | |
81 | #define LCD_TFT_ALT_ENABLE BIT(23) | |
82 | #define LCD_STN_565_ENABLE BIT(24) | |
c6daf05b MP |
83 | #define LCD_V2_DMA_CLK_EN BIT(2) |
84 | #define LCD_V2_LIDD_CLK_EN BIT(1) | |
85 | #define LCD_V2_CORE_CLK_EN BIT(0) | |
86 | #define LCD_V2_LPP_B10 26 | |
4ed824d9 SR |
87 | |
88 | /* LCD Raster Timing 2 Register */ | |
89 | #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) | |
90 | #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) | |
91 | #define LCD_SYNC_CTRL BIT(25) | |
92 | #define LCD_SYNC_EDGE BIT(24) | |
93 | #define LCD_INVERT_PIXEL_CLOCK BIT(22) | |
94 | #define LCD_INVERT_LINE_CLOCK BIT(21) | |
95 | #define LCD_INVERT_FRAME_CLOCK BIT(20) | |
96 | ||
97 | /* LCD Block */ | |
c6daf05b | 98 | #define LCD_PID_REG 0x0 |
4ed824d9 SR |
99 | #define LCD_CTRL_REG 0x4 |
100 | #define LCD_STAT_REG 0x8 | |
101 | #define LCD_RASTER_CTRL_REG 0x28 | |
102 | #define LCD_RASTER_TIMING_0_REG 0x2C | |
103 | #define LCD_RASTER_TIMING_1_REG 0x30 | |
104 | #define LCD_RASTER_TIMING_2_REG 0x34 | |
105 | #define LCD_DMA_CTRL_REG 0x40 | |
106 | #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44 | |
107 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48 | |
1f9c3e1f MA |
108 | #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C |
109 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50 | |
110 | ||
c6daf05b MP |
111 | /* Interrupt Registers available only in Version 2 */ |
112 | #define LCD_RAW_STAT_REG 0x58 | |
113 | #define LCD_MASKED_STAT_REG 0x5c | |
114 | #define LCD_INT_ENABLE_SET_REG 0x60 | |
115 | #define LCD_INT_ENABLE_CLR_REG 0x64 | |
116 | #define LCD_END_OF_INT_IND_REG 0x68 | |
117 | ||
118 | /* Clock registers available only on Version 2 */ | |
119 | #define LCD_CLK_ENABLE_REG 0x6c | |
120 | #define LCD_CLK_RESET_REG 0x70 | |
74a0efde | 121 | #define LCD_CLK_MAIN_RESET BIT(3) |
c6daf05b | 122 | |
1f9c3e1f | 123 | #define LCD_NUM_BUFFERS 2 |
4ed824d9 SR |
124 | |
125 | #define WSI_TIMEOUT 50 | |
126 | #define PALETTE_SIZE 256 | |
127 | #define LEFT_MARGIN 64 | |
128 | #define RIGHT_MARGIN 64 | |
129 | #define UPPER_MARGIN 32 | |
130 | #define LOWER_MARGIN 32 | |
131 | ||
132 | static resource_size_t da8xx_fb_reg_base; | |
133 | static struct resource *lcdc_regs; | |
c6daf05b MP |
134 | static unsigned int lcd_revision; |
135 | static irq_handler_t lcdc_irq_handler; | |
4ed824d9 SR |
136 | |
137 | static inline unsigned int lcdc_read(unsigned int addr) | |
138 | { | |
139 | return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr)); | |
140 | } | |
141 | ||
142 | static inline void lcdc_write(unsigned int val, unsigned int addr) | |
143 | { | |
144 | __raw_writel(val, da8xx_fb_reg_base + (addr)); | |
145 | } | |
146 | ||
147 | struct da8xx_fb_par { | |
4ed824d9 SR |
148 | resource_size_t p_palette_base; |
149 | unsigned char *v_palette_base; | |
1f9c3e1f MA |
150 | dma_addr_t vram_phys; |
151 | unsigned long vram_size; | |
152 | void *vram_virt; | |
153 | unsigned int dma_start; | |
154 | unsigned int dma_end; | |
4ed824d9 SR |
155 | struct clk *lcdc_clk; |
156 | int irq; | |
157 | unsigned short pseudo_palette[16]; | |
4ed824d9 | 158 | unsigned int palette_sz; |
8097b174 | 159 | unsigned int pxl_clk; |
36113804 | 160 | int blank; |
1f9c3e1f MA |
161 | wait_queue_head_t vsync_wait; |
162 | int vsync_flag; | |
163 | int vsync_timeout; | |
e04e5483 C |
164 | #ifdef CONFIG_CPU_FREQ |
165 | struct notifier_block freq_transition; | |
f820917a | 166 | unsigned int lcd_fck_rate; |
e04e5483 | 167 | #endif |
36113804 | 168 | void (*panel_power_ctrl)(int); |
4ed824d9 SR |
169 | }; |
170 | ||
171 | /* Variable Screen Information */ | |
172 | static struct fb_var_screeninfo da8xx_fb_var __devinitdata = { | |
173 | .xoffset = 0, | |
174 | .yoffset = 0, | |
175 | .transp = {0, 0, 0}, | |
176 | .nonstd = 0, | |
177 | .activate = 0, | |
178 | .height = -1, | |
179 | .width = -1, | |
4ed824d9 SR |
180 | .accel_flags = 0, |
181 | .left_margin = LEFT_MARGIN, | |
182 | .right_margin = RIGHT_MARGIN, | |
183 | .upper_margin = UPPER_MARGIN, | |
184 | .lower_margin = LOWER_MARGIN, | |
185 | .sync = 0, | |
186 | .vmode = FB_VMODE_NONINTERLACED | |
187 | }; | |
188 | ||
189 | static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = { | |
190 | .id = "DA8xx FB Drv", | |
191 | .type = FB_TYPE_PACKED_PIXELS, | |
192 | .type_aux = 0, | |
193 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
1f9c3e1f | 194 | .xpanstep = 0, |
4ed824d9 | 195 | .ypanstep = 1, |
1f9c3e1f | 196 | .ywrapstep = 0, |
4ed824d9 SR |
197 | .accel = FB_ACCEL_NONE |
198 | }; | |
199 | ||
200 | struct da8xx_panel { | |
201 | const char name[25]; /* Full name <vendor>_<model> */ | |
202 | unsigned short width; | |
203 | unsigned short height; | |
204 | int hfp; /* Horizontal front porch */ | |
205 | int hbp; /* Horizontal back porch */ | |
206 | int hsw; /* Horizontal Sync Pulse Width */ | |
207 | int vfp; /* Vertical front porch */ | |
208 | int vbp; /* Vertical back porch */ | |
209 | int vsw; /* Vertical Sync Pulse Width */ | |
8097b174 | 210 | unsigned int pxl_clk; /* Pixel clock */ |
2f93e8f4 | 211 | unsigned char invert_pxl_clk; /* Invert Pixel clock */ |
4ed824d9 SR |
212 | }; |
213 | ||
214 | static struct da8xx_panel known_lcd_panels[] = { | |
215 | /* Sharp LCD035Q3DG01 */ | |
216 | [0] = { | |
217 | .name = "Sharp_LCD035Q3DG01", | |
218 | .width = 320, | |
219 | .height = 240, | |
220 | .hfp = 8, | |
221 | .hbp = 6, | |
222 | .hsw = 0, | |
223 | .vfp = 2, | |
224 | .vbp = 2, | |
225 | .vsw = 0, | |
8097b174 | 226 | .pxl_clk = 4608000, |
2f93e8f4 | 227 | .invert_pxl_clk = 1, |
4ed824d9 SR |
228 | }, |
229 | /* Sharp LK043T1DG01 */ | |
230 | [1] = { | |
231 | .name = "Sharp_LK043T1DG01", | |
232 | .width = 480, | |
233 | .height = 272, | |
234 | .hfp = 2, | |
235 | .hbp = 2, | |
236 | .hsw = 41, | |
237 | .vfp = 2, | |
238 | .vbp = 2, | |
239 | .vsw = 10, | |
8097b174 | 240 | .pxl_clk = 7833600, |
2f93e8f4 | 241 | .invert_pxl_clk = 0, |
4ed824d9 | 242 | }, |
f413070e AG |
243 | [2] = { |
244 | /* Hitachi SP10Q010 */ | |
245 | .name = "SP10Q010", | |
246 | .width = 320, | |
247 | .height = 240, | |
248 | .hfp = 10, | |
249 | .hbp = 10, | |
250 | .hsw = 10, | |
251 | .vfp = 10, | |
252 | .vbp = 10, | |
253 | .vsw = 10, | |
254 | .pxl_clk = 7833600, | |
255 | .invert_pxl_clk = 0, | |
256 | }, | |
4ed824d9 SR |
257 | }; |
258 | ||
36113804 C |
259 | /* Enable the Raster Engine of the LCD Controller */ |
260 | static inline void lcd_enable_raster(void) | |
261 | { | |
262 | u32 reg; | |
263 | ||
74a0efde MP |
264 | /* Bring LCDC out of reset */ |
265 | if (lcd_revision == LCD_VERSION_2) | |
266 | lcdc_write(0, LCD_CLK_RESET_REG); | |
267 | ||
36113804 C |
268 | reg = lcdc_read(LCD_RASTER_CTRL_REG); |
269 | if (!(reg & LCD_RASTER_ENABLE)) | |
270 | lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); | |
271 | } | |
272 | ||
4ed824d9 | 273 | /* Disable the Raster Engine of the LCD Controller */ |
36113804 | 274 | static inline void lcd_disable_raster(void) |
4ed824d9 | 275 | { |
4ed824d9 SR |
276 | u32 reg; |
277 | ||
278 | reg = lcdc_read(LCD_RASTER_CTRL_REG); | |
2f93e8f4 | 279 | if (reg & LCD_RASTER_ENABLE) |
4ed824d9 | 280 | lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); |
74a0efde MP |
281 | |
282 | if (lcd_revision == LCD_VERSION_2) | |
283 | /* Write 1 to reset LCDC */ | |
284 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
4ed824d9 SR |
285 | } |
286 | ||
287 | static void lcd_blit(int load_mode, struct da8xx_fb_par *par) | |
288 | { | |
1f9c3e1f MA |
289 | u32 start; |
290 | u32 end; | |
291 | u32 reg_ras; | |
292 | u32 reg_dma; | |
c6daf05b | 293 | u32 reg_int; |
1f9c3e1f MA |
294 | |
295 | /* init reg to clear PLM (loading mode) fields */ | |
296 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
297 | reg_ras &= ~(3 << 20); | |
298 | ||
299 | reg_dma = lcdc_read(LCD_DMA_CTRL_REG); | |
300 | ||
301 | if (load_mode == LOAD_DATA) { | |
302 | start = par->dma_start; | |
303 | end = par->dma_end; | |
304 | ||
305 | reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); | |
c6daf05b MP |
306 | if (lcd_revision == LCD_VERSION_1) { |
307 | reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; | |
308 | } else { | |
309 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
310 | LCD_V2_END_OF_FRAME0_INT_ENA | | |
311 | LCD_V2_END_OF_FRAME1_INT_ENA; | |
312 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
313 | } | |
1f9c3e1f MA |
314 | reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; |
315 | ||
316 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
317 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
318 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
319 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
320 | } else if (load_mode == LOAD_PALETTE) { | |
321 | start = par->p_palette_base; | |
322 | end = start + par->palette_sz - 1; | |
323 | ||
324 | reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); | |
c6daf05b MP |
325 | |
326 | if (lcd_revision == LCD_VERSION_1) { | |
327 | reg_ras |= LCD_V1_PL_INT_ENA; | |
328 | } else { | |
329 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
330 | LCD_V2_PL_INT_ENA; | |
331 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
332 | } | |
1f9c3e1f MA |
333 | |
334 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
335 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
336 | } | |
4ed824d9 | 337 | |
1f9c3e1f MA |
338 | lcdc_write(reg_dma, LCD_DMA_CTRL_REG); |
339 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); | |
4ed824d9 | 340 | |
1f9c3e1f MA |
341 | /* |
342 | * The Raster enable bit must be set after all other control fields are | |
343 | * set. | |
344 | */ | |
345 | lcd_enable_raster(); | |
4ed824d9 SR |
346 | } |
347 | ||
348 | /* Configure the Burst Size of DMA */ | |
349 | static int lcd_cfg_dma(int burst_size) | |
350 | { | |
351 | u32 reg; | |
352 | ||
353 | reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001; | |
354 | switch (burst_size) { | |
355 | case 1: | |
356 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); | |
357 | break; | |
358 | case 2: | |
359 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); | |
360 | break; | |
361 | case 4: | |
362 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); | |
363 | break; | |
364 | case 8: | |
365 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); | |
366 | break; | |
367 | case 16: | |
368 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); | |
369 | break; | |
370 | default: | |
371 | return -EINVAL; | |
372 | } | |
2f93e8f4 | 373 | lcdc_write(reg, LCD_DMA_CTRL_REG); |
4ed824d9 SR |
374 | |
375 | return 0; | |
376 | } | |
377 | ||
378 | static void lcd_cfg_ac_bias(int period, int transitions_per_int) | |
379 | { | |
380 | u32 reg; | |
381 | ||
382 | /* Set the AC Bias Period and Number of Transisitons per Interrupt */ | |
383 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000; | |
384 | reg |= LCD_AC_BIAS_FREQUENCY(period) | | |
385 | LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); | |
386 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
387 | } | |
388 | ||
389 | static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, | |
390 | int front_porch) | |
391 | { | |
392 | u32 reg; | |
393 | ||
394 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf; | |
395 | reg |= ((back_porch & 0xff) << 24) | |
396 | | ((front_porch & 0xff) << 16) | |
397 | | ((pulse_width & 0x3f) << 10); | |
398 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); | |
399 | } | |
400 | ||
401 | static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, | |
402 | int front_porch) | |
403 | { | |
404 | u32 reg; | |
405 | ||
406 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff; | |
407 | reg |= ((back_porch & 0xff) << 24) | |
408 | | ((front_porch & 0xff) << 16) | |
409 | | ((pulse_width & 0x3f) << 10); | |
410 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
411 | } | |
412 | ||
413 | static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) | |
414 | { | |
415 | u32 reg; | |
c6daf05b | 416 | u32 reg_int; |
4ed824d9 SR |
417 | |
418 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE | | |
419 | LCD_MONO_8BIT_MODE | | |
420 | LCD_MONOCHROME_MODE); | |
421 | ||
422 | switch (cfg->p_disp_panel->panel_shade) { | |
423 | case MONOCHROME: | |
424 | reg |= LCD_MONOCHROME_MODE; | |
425 | if (cfg->mono_8bit_mode) | |
426 | reg |= LCD_MONO_8BIT_MODE; | |
427 | break; | |
428 | case COLOR_ACTIVE: | |
429 | reg |= LCD_TFT_MODE; | |
430 | if (cfg->tft_alt_mode) | |
431 | reg |= LCD_TFT_ALT_ENABLE; | |
432 | break; | |
433 | ||
434 | case COLOR_PASSIVE: | |
435 | if (cfg->stn_565_mode) | |
436 | reg |= LCD_STN_565_ENABLE; | |
437 | break; | |
438 | ||
439 | default: | |
440 | return -EINVAL; | |
441 | } | |
442 | ||
443 | /* enable additional interrupts here */ | |
c6daf05b MP |
444 | if (lcd_revision == LCD_VERSION_1) { |
445 | reg |= LCD_V1_UNDERFLOW_INT_ENA; | |
446 | } else { | |
447 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
448 | LCD_V2_UNDERFLOW_INT_ENA; | |
449 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
450 | } | |
4ed824d9 SR |
451 | |
452 | lcdc_write(reg, LCD_RASTER_CTRL_REG); | |
453 | ||
454 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
455 | ||
456 | if (cfg->sync_ctrl) | |
457 | reg |= LCD_SYNC_CTRL; | |
458 | else | |
459 | reg &= ~LCD_SYNC_CTRL; | |
460 | ||
461 | if (cfg->sync_edge) | |
462 | reg |= LCD_SYNC_EDGE; | |
463 | else | |
464 | reg &= ~LCD_SYNC_EDGE; | |
465 | ||
4ed824d9 SR |
466 | if (cfg->invert_line_clock) |
467 | reg |= LCD_INVERT_LINE_CLOCK; | |
468 | else | |
469 | reg &= ~LCD_INVERT_LINE_CLOCK; | |
470 | ||
471 | if (cfg->invert_frm_clock) | |
472 | reg |= LCD_INVERT_FRAME_CLOCK; | |
473 | else | |
474 | reg &= ~LCD_INVERT_FRAME_CLOCK; | |
475 | ||
476 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
477 | ||
478 | return 0; | |
479 | } | |
480 | ||
481 | static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, | |
482 | u32 bpp, u32 raster_order) | |
483 | { | |
1f9c3e1f | 484 | u32 reg; |
4ed824d9 | 485 | |
4ed824d9 SR |
486 | /* Set the Panel Width */ |
487 | /* Pixels per line = (PPL + 1)*16 */ | |
4d740801 MP |
488 | if (lcd_revision == LCD_VERSION_1) { |
489 | /* | |
490 | * 0x3F in bits 4..9 gives max horizontal resolution = 1024 | |
491 | * pixels. | |
492 | */ | |
493 | width &= 0x3f0; | |
494 | } else { | |
495 | /* | |
496 | * 0x7F in bits 4..10 gives max horizontal resolution = 2048 | |
497 | * pixels. | |
498 | */ | |
499 | width &= 0x7f0; | |
500 | } | |
501 | ||
4ed824d9 SR |
502 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG); |
503 | reg &= 0xfffffc00; | |
4d740801 MP |
504 | if (lcd_revision == LCD_VERSION_1) { |
505 | reg |= ((width >> 4) - 1) << 4; | |
506 | } else { | |
507 | width = (width >> 4) - 1; | |
508 | reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); | |
509 | } | |
4ed824d9 SR |
510 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); |
511 | ||
512 | /* Set the Panel Height */ | |
4d740801 | 513 | /* Set bits 9:0 of Lines Per Pixel */ |
4ed824d9 SR |
514 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG); |
515 | reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); | |
516 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
517 | ||
4d740801 MP |
518 | /* Set bit 10 of Lines Per Pixel */ |
519 | if (lcd_revision == LCD_VERSION_2) { | |
520 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
521 | reg |= ((height - 1) & 0x400) << 16; | |
522 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
523 | } | |
524 | ||
4ed824d9 SR |
525 | /* Set the Raster Order of the Frame Buffer */ |
526 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8); | |
527 | if (raster_order) | |
528 | reg |= LCD_RASTER_ORDER; | |
529 | lcdc_write(reg, LCD_RASTER_CTRL_REG); | |
530 | ||
531 | switch (bpp) { | |
532 | case 1: | |
533 | case 2: | |
534 | case 4: | |
535 | case 16: | |
536 | par->palette_sz = 16 * 2; | |
537 | break; | |
538 | ||
539 | case 8: | |
540 | par->palette_sz = 256 * 2; | |
541 | break; | |
542 | ||
543 | default: | |
544 | return -EINVAL; | |
545 | } | |
546 | ||
4ed824d9 SR |
547 | return 0; |
548 | } | |
549 | ||
550 | static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, | |
551 | unsigned blue, unsigned transp, | |
552 | struct fb_info *info) | |
553 | { | |
554 | struct da8xx_fb_par *par = info->par; | |
1f9c3e1f | 555 | unsigned short *palette = (unsigned short *) par->v_palette_base; |
4ed824d9 | 556 | u_short pal; |
1f9c3e1f | 557 | int update_hw = 0; |
4ed824d9 SR |
558 | |
559 | if (regno > 255) | |
560 | return 1; | |
561 | ||
562 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) | |
563 | return 1; | |
564 | ||
f413070e AG |
565 | if (info->var.bits_per_pixel == 4) { |
566 | if (regno > 15) | |
567 | return 1; | |
568 | ||
569 | if (info->var.grayscale) { | |
570 | pal = regno; | |
571 | } else { | |
572 | red >>= 4; | |
573 | green >>= 8; | |
574 | blue >>= 12; | |
575 | ||
576 | pal = (red & 0x0f00); | |
577 | pal |= (green & 0x00f0); | |
578 | pal |= (blue & 0x000f); | |
579 | } | |
580 | if (regno == 0) | |
581 | pal |= 0x2000; | |
582 | palette[regno] = pal; | |
583 | ||
584 | } else if (info->var.bits_per_pixel == 8) { | |
4ed824d9 SR |
585 | red >>= 4; |
586 | green >>= 8; | |
587 | blue >>= 12; | |
588 | ||
589 | pal = (red & 0x0f00); | |
590 | pal |= (green & 0x00f0); | |
591 | pal |= (blue & 0x000f); | |
592 | ||
1f9c3e1f MA |
593 | if (palette[regno] != pal) { |
594 | update_hw = 1; | |
595 | palette[regno] = pal; | |
596 | } | |
4ed824d9 SR |
597 | } else if ((info->var.bits_per_pixel == 16) && regno < 16) { |
598 | red >>= (16 - info->var.red.length); | |
599 | red <<= info->var.red.offset; | |
600 | ||
601 | green >>= (16 - info->var.green.length); | |
602 | green <<= info->var.green.offset; | |
603 | ||
604 | blue >>= (16 - info->var.blue.length); | |
605 | blue <<= info->var.blue.offset; | |
606 | ||
607 | par->pseudo_palette[regno] = red | green | blue; | |
608 | ||
1f9c3e1f MA |
609 | if (palette[0] != 0x4000) { |
610 | update_hw = 1; | |
611 | palette[0] = 0x4000; | |
612 | } | |
4ed824d9 SR |
613 | } |
614 | ||
1f9c3e1f MA |
615 | /* Update the palette in the h/w as needed. */ |
616 | if (update_hw) | |
617 | lcd_blit(LOAD_PALETTE, par); | |
618 | ||
4ed824d9 SR |
619 | return 0; |
620 | } | |
621 | ||
2f93e8f4 | 622 | static void lcd_reset(struct da8xx_fb_par *par) |
4ed824d9 | 623 | { |
4ed824d9 | 624 | /* Disable the Raster if previously Enabled */ |
36113804 | 625 | lcd_disable_raster(); |
4ed824d9 SR |
626 | |
627 | /* DMA has to be disabled */ | |
628 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
629 | lcdc_write(0, LCD_RASTER_CTRL_REG); | |
c6daf05b | 630 | |
74a0efde | 631 | if (lcd_revision == LCD_VERSION_2) { |
c6daf05b | 632 | lcdc_write(0, LCD_INT_ENABLE_SET_REG); |
74a0efde MP |
633 | /* Write 1 to reset */ |
634 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
635 | lcdc_write(0, LCD_CLK_RESET_REG); | |
636 | } | |
4ed824d9 SR |
637 | } |
638 | ||
8097b174 C |
639 | static void lcd_calc_clk_divider(struct da8xx_fb_par *par) |
640 | { | |
641 | unsigned int lcd_clk, div; | |
642 | ||
643 | lcd_clk = clk_get_rate(par->lcdc_clk); | |
644 | div = lcd_clk / par->pxl_clk; | |
645 | ||
646 | /* Configure the LCD clock divisor. */ | |
647 | lcdc_write(LCD_CLK_DIVISOR(div) | | |
648 | (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG); | |
c6daf05b MP |
649 | |
650 | if (lcd_revision == LCD_VERSION_2) | |
651 | lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | | |
652 | LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG); | |
653 | ||
8097b174 C |
654 | } |
655 | ||
4ed824d9 SR |
656 | static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, |
657 | struct da8xx_panel *panel) | |
658 | { | |
659 | u32 bpp; | |
660 | int ret = 0; | |
661 | ||
2f93e8f4 | 662 | lcd_reset(par); |
4ed824d9 | 663 | |
8097b174 C |
664 | /* Calculate the divider */ |
665 | lcd_calc_clk_divider(par); | |
4ed824d9 | 666 | |
2f93e8f4 SR |
667 | if (panel->invert_pxl_clk) |
668 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) | | |
669 | LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
670 | else | |
671 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) & | |
672 | ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
673 | ||
4ed824d9 SR |
674 | /* Configure the DMA burst size. */ |
675 | ret = lcd_cfg_dma(cfg->dma_burst_sz); | |
676 | if (ret < 0) | |
677 | return ret; | |
678 | ||
679 | /* Configure the AC bias properties. */ | |
680 | lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); | |
681 | ||
682 | /* Configure the vertical and horizontal sync properties. */ | |
683 | lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp); | |
684 | lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp); | |
685 | ||
686 | /* Configure for disply */ | |
687 | ret = lcd_cfg_display(cfg); | |
688 | if (ret < 0) | |
689 | return ret; | |
690 | ||
691 | if (QVGA != cfg->p_disp_panel->panel_type) | |
692 | return -EINVAL; | |
693 | ||
694 | if (cfg->bpp <= cfg->p_disp_panel->max_bpp && | |
695 | cfg->bpp >= cfg->p_disp_panel->min_bpp) | |
696 | bpp = cfg->bpp; | |
697 | else | |
698 | bpp = cfg->p_disp_panel->max_bpp; | |
699 | if (bpp == 12) | |
700 | bpp = 16; | |
701 | ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width, | |
702 | (unsigned int)panel->height, bpp, | |
703 | cfg->raster_order); | |
704 | if (ret < 0) | |
705 | return ret; | |
706 | ||
707 | /* Configure FDD */ | |
708 | lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) | | |
709 | (cfg->fdd << 12), LCD_RASTER_CTRL_REG); | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
c6daf05b MP |
714 | /* IRQ handler for version 2 of LCDC */ |
715 | static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) | |
716 | { | |
717 | struct da8xx_fb_par *par = arg; | |
718 | u32 stat = lcdc_read(LCD_MASKED_STAT_REG); | |
719 | u32 reg_int; | |
720 | ||
721 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
722 | lcd_disable_raster(); | |
723 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
724 | lcd_enable_raster(); | |
725 | } else if (stat & LCD_PL_LOAD_DONE) { | |
726 | /* | |
727 | * Must disable raster before changing state of any control bit. | |
728 | * And also must be disabled before clearing the PL loading | |
729 | * interrupt via the following write to the status register. If | |
730 | * this is done after then one gets multiple PL done interrupts. | |
731 | */ | |
732 | lcd_disable_raster(); | |
733 | ||
734 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
735 | ||
736 | /* Disable PL completion inerrupt */ | |
737 | reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) | | |
738 | (LCD_V2_PL_INT_ENA); | |
739 | lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG); | |
740 | ||
741 | /* Setup and start data loading mode */ | |
742 | lcd_blit(LOAD_DATA, par); | |
743 | } else { | |
744 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
745 | ||
746 | if (stat & LCD_END_OF_FRAME0) { | |
747 | lcdc_write(par->dma_start, | |
748 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
749 | lcdc_write(par->dma_end, | |
750 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
751 | par->vsync_flag = 1; | |
752 | wake_up_interruptible(&par->vsync_wait); | |
753 | } | |
754 | ||
755 | if (stat & LCD_END_OF_FRAME1) { | |
756 | lcdc_write(par->dma_start, | |
757 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
758 | lcdc_write(par->dma_end, | |
759 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
760 | par->vsync_flag = 1; | |
761 | wake_up_interruptible(&par->vsync_wait); | |
762 | } | |
763 | } | |
764 | ||
765 | lcdc_write(0, LCD_END_OF_INT_IND_REG); | |
766 | return IRQ_HANDLED; | |
767 | } | |
768 | ||
769 | /* IRQ handler for version 1 LCDC */ | |
770 | static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg) | |
4ed824d9 | 771 | { |
1f9c3e1f | 772 | struct da8xx_fb_par *par = arg; |
4ed824d9 | 773 | u32 stat = lcdc_read(LCD_STAT_REG); |
1f9c3e1f | 774 | u32 reg_ras; |
4ed824d9 SR |
775 | |
776 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
36113804 | 777 | lcd_disable_raster(); |
4ed824d9 | 778 | lcdc_write(stat, LCD_STAT_REG); |
36113804 | 779 | lcd_enable_raster(); |
1f9c3e1f MA |
780 | } else if (stat & LCD_PL_LOAD_DONE) { |
781 | /* | |
782 | * Must disable raster before changing state of any control bit. | |
783 | * And also must be disabled before clearing the PL loading | |
784 | * interrupt via the following write to the status register. If | |
785 | * this is done after then one gets multiple PL done interrupts. | |
786 | */ | |
787 | lcd_disable_raster(); | |
788 | ||
4ed824d9 SR |
789 | lcdc_write(stat, LCD_STAT_REG); |
790 | ||
1f9c3e1f MA |
791 | /* Disable PL completion inerrupt */ |
792 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
c6daf05b | 793 | reg_ras &= ~LCD_V1_PL_INT_ENA; |
1f9c3e1f MA |
794 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); |
795 | ||
796 | /* Setup and start data loading mode */ | |
797 | lcd_blit(LOAD_DATA, par); | |
798 | } else { | |
799 | lcdc_write(stat, LCD_STAT_REG); | |
800 | ||
801 | if (stat & LCD_END_OF_FRAME0) { | |
802 | lcdc_write(par->dma_start, | |
803 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
804 | lcdc_write(par->dma_end, | |
805 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
806 | par->vsync_flag = 1; | |
807 | wake_up_interruptible(&par->vsync_wait); | |
808 | } | |
809 | ||
810 | if (stat & LCD_END_OF_FRAME1) { | |
811 | lcdc_write(par->dma_start, | |
812 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
813 | lcdc_write(par->dma_end, | |
814 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
815 | par->vsync_flag = 1; | |
816 | wake_up_interruptible(&par->vsync_wait); | |
817 | } | |
818 | } | |
819 | ||
4ed824d9 SR |
820 | return IRQ_HANDLED; |
821 | } | |
822 | ||
823 | static int fb_check_var(struct fb_var_screeninfo *var, | |
824 | struct fb_info *info) | |
825 | { | |
826 | int err = 0; | |
827 | ||
828 | switch (var->bits_per_pixel) { | |
829 | case 1: | |
830 | case 8: | |
831 | var->red.offset = 0; | |
832 | var->red.length = 8; | |
833 | var->green.offset = 0; | |
834 | var->green.length = 8; | |
835 | var->blue.offset = 0; | |
836 | var->blue.length = 8; | |
837 | var->transp.offset = 0; | |
838 | var->transp.length = 0; | |
f413070e | 839 | var->nonstd = 0; |
4ed824d9 SR |
840 | break; |
841 | case 4: | |
842 | var->red.offset = 0; | |
843 | var->red.length = 4; | |
844 | var->green.offset = 0; | |
845 | var->green.length = 4; | |
846 | var->blue.offset = 0; | |
847 | var->blue.length = 4; | |
848 | var->transp.offset = 0; | |
849 | var->transp.length = 0; | |
f413070e | 850 | var->nonstd = FB_NONSTD_REV_PIX_IN_B; |
4ed824d9 SR |
851 | break; |
852 | case 16: /* RGB 565 */ | |
3510b8f7 | 853 | var->red.offset = 11; |
4ed824d9 SR |
854 | var->red.length = 5; |
855 | var->green.offset = 5; | |
856 | var->green.length = 6; | |
3510b8f7 | 857 | var->blue.offset = 0; |
4ed824d9 SR |
858 | var->blue.length = 5; |
859 | var->transp.offset = 0; | |
860 | var->transp.length = 0; | |
f413070e | 861 | var->nonstd = 0; |
4ed824d9 SR |
862 | break; |
863 | default: | |
864 | err = -EINVAL; | |
865 | } | |
866 | ||
867 | var->red.msb_right = 0; | |
868 | var->green.msb_right = 0; | |
869 | var->blue.msb_right = 0; | |
870 | var->transp.msb_right = 0; | |
871 | return err; | |
872 | } | |
873 | ||
e04e5483 C |
874 | #ifdef CONFIG_CPU_FREQ |
875 | static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb, | |
876 | unsigned long val, void *data) | |
877 | { | |
878 | struct da8xx_fb_par *par; | |
e04e5483 C |
879 | |
880 | par = container_of(nb, struct da8xx_fb_par, freq_transition); | |
f820917a MP |
881 | if (val == CPUFREQ_POSTCHANGE) { |
882 | if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) { | |
883 | par->lcd_fck_rate = clk_get_rate(par->lcdc_clk); | |
884 | lcd_disable_raster(); | |
885 | lcd_calc_clk_divider(par); | |
886 | lcd_enable_raster(); | |
887 | } | |
e04e5483 C |
888 | } |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
893 | static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par) | |
894 | { | |
895 | par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition; | |
896 | ||
897 | return cpufreq_register_notifier(&par->freq_transition, | |
898 | CPUFREQ_TRANSITION_NOTIFIER); | |
899 | } | |
900 | ||
901 | static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par) | |
902 | { | |
903 | cpufreq_unregister_notifier(&par->freq_transition, | |
904 | CPUFREQ_TRANSITION_NOTIFIER); | |
905 | } | |
906 | #endif | |
907 | ||
4ed824d9 SR |
908 | static int __devexit fb_remove(struct platform_device *dev) |
909 | { | |
910 | struct fb_info *info = dev_get_drvdata(&dev->dev); | |
4ed824d9 SR |
911 | |
912 | if (info) { | |
913 | struct da8xx_fb_par *par = info->par; | |
914 | ||
e04e5483 C |
915 | #ifdef CONFIG_CPU_FREQ |
916 | lcd_da8xx_cpufreq_deregister(par); | |
917 | #endif | |
36113804 C |
918 | if (par->panel_power_ctrl) |
919 | par->panel_power_ctrl(0); | |
920 | ||
921 | lcd_disable_raster(); | |
4ed824d9 SR |
922 | lcdc_write(0, LCD_RASTER_CTRL_REG); |
923 | ||
924 | /* disable DMA */ | |
925 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
926 | ||
927 | unregister_framebuffer(info); | |
928 | fb_dealloc_cmap(&info->cmap); | |
1f9c3e1f MA |
929 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, |
930 | par->p_palette_base); | |
931 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, | |
932 | par->vram_phys); | |
4ed824d9 SR |
933 | free_irq(par->irq, par); |
934 | clk_disable(par->lcdc_clk); | |
935 | clk_put(par->lcdc_clk); | |
936 | framebuffer_release(info); | |
937 | iounmap((void __iomem *)da8xx_fb_reg_base); | |
938 | release_mem_region(lcdc_regs->start, resource_size(lcdc_regs)); | |
939 | ||
940 | } | |
2f93e8f4 | 941 | return 0; |
4ed824d9 SR |
942 | } |
943 | ||
1f9c3e1f MA |
944 | /* |
945 | * Function to wait for vertical sync which for this LCD peripheral | |
946 | * translates into waiting for the current raster frame to complete. | |
947 | */ | |
948 | static int fb_wait_for_vsync(struct fb_info *info) | |
949 | { | |
950 | struct da8xx_fb_par *par = info->par; | |
951 | int ret; | |
952 | ||
953 | /* | |
954 | * Set flag to 0 and wait for isr to set to 1. It would seem there is a | |
25985edc | 955 | * race condition here where the ISR could have occurred just before or |
1f9c3e1f MA |
956 | * just after this set. But since we are just coarsely waiting for |
957 | * a frame to complete then that's OK. i.e. if the frame completed | |
958 | * just before this code executed then we have to wait another full | |
959 | * frame time but there is no way to avoid such a situation. On the | |
960 | * other hand if the frame completed just after then we don't need | |
961 | * to wait long at all. Either way we are guaranteed to return to the | |
962 | * user immediately after a frame completion which is all that is | |
963 | * required. | |
964 | */ | |
965 | par->vsync_flag = 0; | |
966 | ret = wait_event_interruptible_timeout(par->vsync_wait, | |
967 | par->vsync_flag != 0, | |
968 | par->vsync_timeout); | |
969 | if (ret < 0) | |
970 | return ret; | |
971 | if (ret == 0) | |
972 | return -ETIMEDOUT; | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
4ed824d9 SR |
977 | static int fb_ioctl(struct fb_info *info, unsigned int cmd, |
978 | unsigned long arg) | |
979 | { | |
980 | struct lcd_sync_arg sync_arg; | |
981 | ||
982 | switch (cmd) { | |
983 | case FBIOGET_CONTRAST: | |
984 | case FBIOPUT_CONTRAST: | |
985 | case FBIGET_BRIGHTNESS: | |
986 | case FBIPUT_BRIGHTNESS: | |
987 | case FBIGET_COLOR: | |
988 | case FBIPUT_COLOR: | |
2f93e8f4 | 989 | return -ENOTTY; |
4ed824d9 SR |
990 | case FBIPUT_HSYNC: |
991 | if (copy_from_user(&sync_arg, (char *)arg, | |
992 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 993 | return -EFAULT; |
4ed824d9 SR |
994 | lcd_cfg_horizontal_sync(sync_arg.back_porch, |
995 | sync_arg.pulse_width, | |
996 | sync_arg.front_porch); | |
997 | break; | |
998 | case FBIPUT_VSYNC: | |
999 | if (copy_from_user(&sync_arg, (char *)arg, | |
1000 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1001 | return -EFAULT; |
4ed824d9 SR |
1002 | lcd_cfg_vertical_sync(sync_arg.back_porch, |
1003 | sync_arg.pulse_width, | |
1004 | sync_arg.front_porch); | |
1005 | break; | |
1f9c3e1f MA |
1006 | case FBIO_WAITFORVSYNC: |
1007 | return fb_wait_for_vsync(info); | |
4ed824d9 SR |
1008 | default: |
1009 | return -EINVAL; | |
1010 | } | |
1011 | return 0; | |
1012 | } | |
1013 | ||
312d9715 C |
1014 | static int cfb_blank(int blank, struct fb_info *info) |
1015 | { | |
1016 | struct da8xx_fb_par *par = info->par; | |
1017 | int ret = 0; | |
1018 | ||
1019 | if (par->blank == blank) | |
1020 | return 0; | |
1021 | ||
1022 | par->blank = blank; | |
1023 | switch (blank) { | |
1024 | case FB_BLANK_UNBLANK: | |
1025 | if (par->panel_power_ctrl) | |
1026 | par->panel_power_ctrl(1); | |
1027 | ||
1028 | lcd_enable_raster(); | |
1029 | break; | |
99a647d1 YY |
1030 | case FB_BLANK_NORMAL: |
1031 | case FB_BLANK_VSYNC_SUSPEND: | |
1032 | case FB_BLANK_HSYNC_SUSPEND: | |
312d9715 C |
1033 | case FB_BLANK_POWERDOWN: |
1034 | if (par->panel_power_ctrl) | |
1035 | par->panel_power_ctrl(0); | |
1036 | ||
1037 | lcd_disable_raster(); | |
1038 | break; | |
1039 | default: | |
1040 | ret = -EINVAL; | |
1041 | } | |
1042 | ||
1043 | return ret; | |
1044 | } | |
1045 | ||
1f9c3e1f MA |
1046 | /* |
1047 | * Set new x,y offsets in the virtual display for the visible area and switch | |
1048 | * to the new mode. | |
1049 | */ | |
1050 | static int da8xx_pan_display(struct fb_var_screeninfo *var, | |
1051 | struct fb_info *fbi) | |
1052 | { | |
1053 | int ret = 0; | |
1054 | struct fb_var_screeninfo new_var; | |
1055 | struct da8xx_fb_par *par = fbi->par; | |
1056 | struct fb_fix_screeninfo *fix = &fbi->fix; | |
1057 | unsigned int end; | |
1058 | unsigned int start; | |
1059 | ||
1060 | if (var->xoffset != fbi->var.xoffset || | |
1061 | var->yoffset != fbi->var.yoffset) { | |
1062 | memcpy(&new_var, &fbi->var, sizeof(new_var)); | |
1063 | new_var.xoffset = var->xoffset; | |
1064 | new_var.yoffset = var->yoffset; | |
1065 | if (fb_check_var(&new_var, fbi)) | |
1066 | ret = -EINVAL; | |
1067 | else { | |
1068 | memcpy(&fbi->var, &new_var, sizeof(new_var)); | |
1069 | ||
1070 | start = fix->smem_start + | |
1071 | new_var.yoffset * fix->line_length + | |
e6c4d3d4 LP |
1072 | new_var.xoffset * fbi->var.bits_per_pixel / 8; |
1073 | end = start + fbi->var.yres * fix->line_length - 1; | |
1f9c3e1f MA |
1074 | par->dma_start = start; |
1075 | par->dma_end = end; | |
1076 | } | |
1077 | } | |
1078 | ||
1079 | return ret; | |
1080 | } | |
1081 | ||
4ed824d9 SR |
1082 | static struct fb_ops da8xx_fb_ops = { |
1083 | .owner = THIS_MODULE, | |
1084 | .fb_check_var = fb_check_var, | |
1085 | .fb_setcolreg = fb_setcolreg, | |
1f9c3e1f | 1086 | .fb_pan_display = da8xx_pan_display, |
4ed824d9 SR |
1087 | .fb_ioctl = fb_ioctl, |
1088 | .fb_fillrect = cfb_fillrect, | |
1089 | .fb_copyarea = cfb_copyarea, | |
1090 | .fb_imageblit = cfb_imageblit, | |
312d9715 | 1091 | .fb_blank = cfb_blank, |
4ed824d9 SR |
1092 | }; |
1093 | ||
12fa8350 MP |
1094 | /* Calculate and return pixel clock period in pico seconds */ |
1095 | static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par) | |
1096 | { | |
1097 | unsigned int lcd_clk, div; | |
1098 | unsigned int configured_pix_clk; | |
1099 | unsigned long long pix_clk_period_picosec = 1000000000000ULL; | |
1100 | ||
1101 | lcd_clk = clk_get_rate(par->lcdc_clk); | |
1102 | div = lcd_clk / par->pxl_clk; | |
1103 | configured_pix_clk = (lcd_clk / div); | |
1104 | ||
1105 | do_div(pix_clk_period_picosec, configured_pix_clk); | |
1106 | ||
1107 | return pix_clk_period_picosec; | |
1108 | } | |
1109 | ||
1db41e03 | 1110 | static int __devinit fb_probe(struct platform_device *device) |
4ed824d9 SR |
1111 | { |
1112 | struct da8xx_lcdc_platform_data *fb_pdata = | |
1113 | device->dev.platform_data; | |
1114 | struct lcd_ctrl_config *lcd_cfg; | |
1115 | struct da8xx_panel *lcdc_info; | |
1116 | struct fb_info *da8xx_fb_info; | |
1117 | struct clk *fb_clk = NULL; | |
1118 | struct da8xx_fb_par *par; | |
1119 | resource_size_t len; | |
1120 | int ret, i; | |
3b9cc4ea | 1121 | unsigned long ulcm; |
4ed824d9 SR |
1122 | |
1123 | if (fb_pdata == NULL) { | |
1124 | dev_err(&device->dev, "Can not get platform data\n"); | |
1125 | return -ENOENT; | |
1126 | } | |
1127 | ||
1128 | lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0); | |
1129 | if (!lcdc_regs) { | |
1130 | dev_err(&device->dev, | |
1131 | "Can not get memory resource for LCD controller\n"); | |
1132 | return -ENOENT; | |
1133 | } | |
1134 | ||
1135 | len = resource_size(lcdc_regs); | |
1136 | ||
1137 | lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name); | |
1138 | if (!lcdc_regs) | |
1139 | return -EBUSY; | |
1140 | ||
1141 | da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len); | |
1142 | if (!da8xx_fb_reg_base) { | |
1143 | ret = -EBUSY; | |
1144 | goto err_request_mem; | |
1145 | } | |
1146 | ||
1147 | fb_clk = clk_get(&device->dev, NULL); | |
1148 | if (IS_ERR(fb_clk)) { | |
1149 | dev_err(&device->dev, "Can not get device clock\n"); | |
1150 | ret = -ENODEV; | |
1151 | goto err_ioremap; | |
1152 | } | |
1153 | ret = clk_enable(fb_clk); | |
1154 | if (ret) | |
1155 | goto err_clk_put; | |
1156 | ||
c6daf05b MP |
1157 | /* Determine LCD IP Version */ |
1158 | switch (lcdc_read(LCD_PID_REG)) { | |
1159 | case 0x4C100102: | |
1160 | lcd_revision = LCD_VERSION_1; | |
1161 | break; | |
1162 | case 0x4F200800: | |
1163 | lcd_revision = LCD_VERSION_2; | |
1164 | break; | |
1165 | default: | |
1166 | dev_warn(&device->dev, "Unknown PID Reg value 0x%x, " | |
1167 | "defaulting to LCD revision 1\n", | |
1168 | lcdc_read(LCD_PID_REG)); | |
1169 | lcd_revision = LCD_VERSION_1; | |
1170 | break; | |
1171 | } | |
1172 | ||
4ed824d9 SR |
1173 | for (i = 0, lcdc_info = known_lcd_panels; |
1174 | i < ARRAY_SIZE(known_lcd_panels); | |
1175 | i++, lcdc_info++) { | |
1176 | if (strcmp(fb_pdata->type, lcdc_info->name) == 0) | |
1177 | break; | |
1178 | } | |
1179 | ||
1180 | if (i == ARRAY_SIZE(known_lcd_panels)) { | |
1181 | dev_err(&device->dev, "GLCD: No valid panel found\n"); | |
dd04a6b3 | 1182 | ret = -ENODEV; |
4ed824d9 SR |
1183 | goto err_clk_disable; |
1184 | } else | |
1185 | dev_info(&device->dev, "GLCD: Found %s panel\n", | |
1186 | fb_pdata->type); | |
1187 | ||
1188 | lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data; | |
1189 | ||
1190 | da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par), | |
1191 | &device->dev); | |
1192 | if (!da8xx_fb_info) { | |
1193 | dev_dbg(&device->dev, "Memory allocation failed for fb_info\n"); | |
1194 | ret = -ENOMEM; | |
1195 | goto err_clk_disable; | |
1196 | } | |
1197 | ||
1198 | par = da8xx_fb_info->par; | |
8097b174 | 1199 | par->lcdc_clk = fb_clk; |
f820917a MP |
1200 | #ifdef CONFIG_CPU_FREQ |
1201 | par->lcd_fck_rate = clk_get_rate(fb_clk); | |
1202 | #endif | |
8097b174 | 1203 | par->pxl_clk = lcdc_info->pxl_clk; |
36113804 C |
1204 | if (fb_pdata->panel_power_ctrl) { |
1205 | par->panel_power_ctrl = fb_pdata->panel_power_ctrl; | |
1206 | par->panel_power_ctrl(1); | |
1207 | } | |
4ed824d9 SR |
1208 | |
1209 | if (lcd_init(par, lcd_cfg, lcdc_info) < 0) { | |
1210 | dev_err(&device->dev, "lcd_init failed\n"); | |
1211 | ret = -EFAULT; | |
1212 | goto err_release_fb; | |
1213 | } | |
1214 | ||
1215 | /* allocate frame buffer */ | |
1f9c3e1f | 1216 | par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp; |
3b9cc4ea AN |
1217 | ulcm = lcm((lcdc_info->width * lcd_cfg->bpp)/8, PAGE_SIZE); |
1218 | par->vram_size = roundup(par->vram_size/8, ulcm); | |
1f9c3e1f MA |
1219 | par->vram_size = par->vram_size * LCD_NUM_BUFFERS; |
1220 | ||
1221 | par->vram_virt = dma_alloc_coherent(NULL, | |
1222 | par->vram_size, | |
1223 | (resource_size_t *) &par->vram_phys, | |
1224 | GFP_KERNEL | GFP_DMA); | |
1225 | if (!par->vram_virt) { | |
4ed824d9 SR |
1226 | dev_err(&device->dev, |
1227 | "GLCD: kmalloc for frame buffer failed\n"); | |
1228 | ret = -EINVAL; | |
1229 | goto err_release_fb; | |
1230 | } | |
1231 | ||
1f9c3e1f MA |
1232 | da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt; |
1233 | da8xx_fb_fix.smem_start = par->vram_phys; | |
1234 | da8xx_fb_fix.smem_len = par->vram_size; | |
1235 | da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8; | |
1236 | ||
1237 | par->dma_start = par->vram_phys; | |
1238 | par->dma_end = par->dma_start + lcdc_info->height * | |
1239 | da8xx_fb_fix.line_length - 1; | |
1240 | ||
1241 | /* allocate palette buffer */ | |
1242 | par->v_palette_base = dma_alloc_coherent(NULL, | |
1243 | PALETTE_SIZE, | |
1244 | (resource_size_t *) | |
1245 | &par->p_palette_base, | |
1246 | GFP_KERNEL | GFP_DMA); | |
1247 | if (!par->v_palette_base) { | |
1248 | dev_err(&device->dev, | |
1249 | "GLCD: kmalloc for palette buffer failed\n"); | |
1250 | ret = -EINVAL; | |
1251 | goto err_release_fb_mem; | |
1252 | } | |
1253 | memset(par->v_palette_base, 0, PALETTE_SIZE); | |
4ed824d9 | 1254 | |
4ed824d9 SR |
1255 | par->irq = platform_get_irq(device, 0); |
1256 | if (par->irq < 0) { | |
1257 | ret = -ENOENT; | |
1f9c3e1f | 1258 | goto err_release_pl_mem; |
4ed824d9 SR |
1259 | } |
1260 | ||
4ed824d9 SR |
1261 | /* Initialize par */ |
1262 | da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp; | |
1263 | ||
1264 | da8xx_fb_var.xres = lcdc_info->width; | |
1265 | da8xx_fb_var.xres_virtual = lcdc_info->width; | |
1266 | ||
1f9c3e1f MA |
1267 | da8xx_fb_var.yres = lcdc_info->height; |
1268 | da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS; | |
4ed824d9 SR |
1269 | |
1270 | da8xx_fb_var.grayscale = | |
1271 | lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; | |
1272 | da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; | |
1273 | ||
1274 | da8xx_fb_var.hsync_len = lcdc_info->hsw; | |
1275 | da8xx_fb_var.vsync_len = lcdc_info->vsw; | |
084e104b AG |
1276 | da8xx_fb_var.right_margin = lcdc_info->hfp; |
1277 | da8xx_fb_var.left_margin = lcdc_info->hbp; | |
1278 | da8xx_fb_var.lower_margin = lcdc_info->vfp; | |
1279 | da8xx_fb_var.upper_margin = lcdc_info->vbp; | |
12fa8350 | 1280 | da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par); |
4ed824d9 SR |
1281 | |
1282 | /* Initialize fbinfo */ | |
1283 | da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; | |
1284 | da8xx_fb_info->fix = da8xx_fb_fix; | |
1285 | da8xx_fb_info->var = da8xx_fb_var; | |
1286 | da8xx_fb_info->fbops = &da8xx_fb_ops; | |
1287 | da8xx_fb_info->pseudo_palette = par->pseudo_palette; | |
3510b8f7 SR |
1288 | da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? |
1289 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
4ed824d9 SR |
1290 | |
1291 | ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0); | |
1292 | if (ret) | |
93c176f3 | 1293 | goto err_release_pl_mem; |
4ed824d9 SR |
1294 | da8xx_fb_info->cmap.len = par->palette_sz; |
1295 | ||
4ed824d9 SR |
1296 | /* initialize var_screeninfo */ |
1297 | da8xx_fb_var.activate = FB_ACTIVATE_FORCE; | |
1298 | fb_set_var(da8xx_fb_info, &da8xx_fb_var); | |
1299 | ||
1300 | dev_set_drvdata(&device->dev, da8xx_fb_info); | |
1f9c3e1f MA |
1301 | |
1302 | /* initialize the vsync wait queue */ | |
1303 | init_waitqueue_head(&par->vsync_wait); | |
1304 | par->vsync_timeout = HZ / 5; | |
1305 | ||
4ed824d9 SR |
1306 | /* Register the Frame Buffer */ |
1307 | if (register_framebuffer(da8xx_fb_info) < 0) { | |
1308 | dev_err(&device->dev, | |
1309 | "GLCD: Frame Buffer Registration Failed!\n"); | |
1310 | ret = -EINVAL; | |
1311 | goto err_dealloc_cmap; | |
1312 | } | |
1313 | ||
e04e5483 C |
1314 | #ifdef CONFIG_CPU_FREQ |
1315 | ret = lcd_da8xx_cpufreq_register(par); | |
1316 | if (ret) { | |
1317 | dev_err(&device->dev, "failed to register cpufreq\n"); | |
1318 | goto err_cpu_freq; | |
1319 | } | |
1320 | #endif | |
93c176f3 | 1321 | |
c6daf05b MP |
1322 | if (lcd_revision == LCD_VERSION_1) |
1323 | lcdc_irq_handler = lcdc_irq_handler_rev01; | |
1324 | else | |
1325 | lcdc_irq_handler = lcdc_irq_handler_rev02; | |
1326 | ||
1327 | ret = request_irq(par->irq, lcdc_irq_handler, 0, | |
1328 | DRIVER_NAME, par); | |
93c176f3 CA |
1329 | if (ret) |
1330 | goto irq_freq; | |
4ed824d9 SR |
1331 | return 0; |
1332 | ||
93c176f3 | 1333 | irq_freq: |
e04e5483 | 1334 | #ifdef CONFIG_CPU_FREQ |
360c202b | 1335 | lcd_da8xx_cpufreq_deregister(par); |
e04e5483 | 1336 | err_cpu_freq: |
3a84409c | 1337 | #endif |
e04e5483 | 1338 | unregister_framebuffer(da8xx_fb_info); |
e04e5483 | 1339 | |
4ed824d9 SR |
1340 | err_dealloc_cmap: |
1341 | fb_dealloc_cmap(&da8xx_fb_info->cmap); | |
1342 | ||
1f9c3e1f MA |
1343 | err_release_pl_mem: |
1344 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, | |
1345 | par->p_palette_base); | |
1346 | ||
4ed824d9 | 1347 | err_release_fb_mem: |
1f9c3e1f | 1348 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys); |
4ed824d9 SR |
1349 | |
1350 | err_release_fb: | |
1351 | framebuffer_release(da8xx_fb_info); | |
1352 | ||
1353 | err_clk_disable: | |
1354 | clk_disable(fb_clk); | |
1355 | ||
1356 | err_clk_put: | |
1357 | clk_put(fb_clk); | |
1358 | ||
1359 | err_ioremap: | |
1360 | iounmap((void __iomem *)da8xx_fb_reg_base); | |
1361 | ||
1362 | err_request_mem: | |
1363 | release_mem_region(lcdc_regs->start, len); | |
1364 | ||
1365 | return ret; | |
1366 | } | |
1367 | ||
1368 | #ifdef CONFIG_PM | |
1369 | static int fb_suspend(struct platform_device *dev, pm_message_t state) | |
1370 | { | |
1d3c6c7b C |
1371 | struct fb_info *info = platform_get_drvdata(dev); |
1372 | struct da8xx_fb_par *par = info->par; | |
1373 | ||
ac751efa | 1374 | console_lock(); |
1d3c6c7b C |
1375 | if (par->panel_power_ctrl) |
1376 | par->panel_power_ctrl(0); | |
1377 | ||
1378 | fb_set_suspend(info, 1); | |
1379 | lcd_disable_raster(); | |
1380 | clk_disable(par->lcdc_clk); | |
ac751efa | 1381 | console_unlock(); |
1d3c6c7b C |
1382 | |
1383 | return 0; | |
4ed824d9 SR |
1384 | } |
1385 | static int fb_resume(struct platform_device *dev) | |
1386 | { | |
1d3c6c7b C |
1387 | struct fb_info *info = platform_get_drvdata(dev); |
1388 | struct da8xx_fb_par *par = info->par; | |
1389 | ||
ac751efa | 1390 | console_lock(); |
1d3c6c7b C |
1391 | if (par->panel_power_ctrl) |
1392 | par->panel_power_ctrl(1); | |
1393 | ||
1394 | clk_enable(par->lcdc_clk); | |
1395 | lcd_enable_raster(); | |
1396 | fb_set_suspend(info, 0); | |
ac751efa | 1397 | console_unlock(); |
1d3c6c7b C |
1398 | |
1399 | return 0; | |
4ed824d9 SR |
1400 | } |
1401 | #else | |
1402 | #define fb_suspend NULL | |
1403 | #define fb_resume NULL | |
1404 | #endif | |
1405 | ||
1406 | static struct platform_driver da8xx_fb_driver = { | |
1407 | .probe = fb_probe, | |
1db41e03 | 1408 | .remove = __devexit_p(fb_remove), |
4ed824d9 SR |
1409 | .suspend = fb_suspend, |
1410 | .resume = fb_resume, | |
1411 | .driver = { | |
1412 | .name = DRIVER_NAME, | |
1413 | .owner = THIS_MODULE, | |
1414 | }, | |
1415 | }; | |
1416 | ||
1417 | static int __init da8xx_fb_init(void) | |
1418 | { | |
1419 | return platform_driver_register(&da8xx_fb_driver); | |
1420 | } | |
1421 | ||
1422 | static void __exit da8xx_fb_cleanup(void) | |
1423 | { | |
1424 | platform_driver_unregister(&da8xx_fb_driver); | |
1425 | } | |
1426 | ||
1427 | module_init(da8xx_fb_init); | |
1428 | module_exit(da8xx_fb_cleanup); | |
1429 | ||
1430 | MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx"); | |
1431 | MODULE_AUTHOR("Texas Instruments"); | |
1432 | MODULE_LICENSE("GPL"); |