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4ed824d9 SR |
1 | /* |
2 | * Copyright (C) 2008-2009 MontaVista Software Inc. | |
3 | * Copyright (C) 2008-2009 Texas Instruments Inc | |
4 | * | |
5 | * Based on the LCD driver for TI Avalanche processors written by | |
6 | * Ajay Singh and Shalom Hai. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option)any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #include <linux/module.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/fb.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/uaccess.h> | |
9dd44d5d | 29 | #include <linux/pm_runtime.h> |
4ed824d9 | 30 | #include <linux/interrupt.h> |
a481b37a | 31 | #include <linux/wait.h> |
4ed824d9 | 32 | #include <linux/clk.h> |
e04e5483 | 33 | #include <linux/cpufreq.h> |
1d3c6c7b | 34 | #include <linux/console.h> |
deb95c6c | 35 | #include <linux/spinlock.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
a0239073 | 37 | #include <linux/delay.h> |
3b9cc4ea | 38 | #include <linux/lcm.h> |
4ed824d9 | 39 | #include <video/da8xx-fb.h> |
12fa8350 | 40 | #include <asm/div64.h> |
4ed824d9 SR |
41 | |
42 | #define DRIVER_NAME "da8xx_lcdc" | |
43 | ||
c6daf05b MP |
44 | #define LCD_VERSION_1 1 |
45 | #define LCD_VERSION_2 2 | |
46 | ||
4ed824d9 | 47 | /* LCD Status Register */ |
1f9c3e1f | 48 | #define LCD_END_OF_FRAME1 BIT(9) |
4ed824d9 | 49 | #define LCD_END_OF_FRAME0 BIT(8) |
1f9c3e1f | 50 | #define LCD_PL_LOAD_DONE BIT(6) |
4ed824d9 SR |
51 | #define LCD_FIFO_UNDERFLOW BIT(5) |
52 | #define LCD_SYNC_LOST BIT(2) | |
a481b37a | 53 | #define LCD_FRAME_DONE BIT(0) |
4ed824d9 SR |
54 | |
55 | /* LCD DMA Control Register */ | |
56 | #define LCD_DMA_BURST_SIZE(x) ((x) << 4) | |
57 | #define LCD_DMA_BURST_1 0x0 | |
58 | #define LCD_DMA_BURST_2 0x1 | |
59 | #define LCD_DMA_BURST_4 0x2 | |
60 | #define LCD_DMA_BURST_8 0x3 | |
61 | #define LCD_DMA_BURST_16 0x4 | |
c6daf05b MP |
62 | #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) |
63 | #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) | |
64 | #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) | |
4ed824d9 SR |
65 | #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) |
66 | ||
67 | /* LCD Control Register */ | |
68 | #define LCD_CLK_DIVISOR(x) ((x) << 8) | |
69 | #define LCD_RASTER_MODE 0x01 | |
70 | ||
71 | /* LCD Raster Control Register */ | |
72 | #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) | |
73 | #define PALETTE_AND_DATA 0x00 | |
74 | #define PALETTE_ONLY 0x01 | |
1f9c3e1f | 75 | #define DATA_ONLY 0x02 |
4ed824d9 SR |
76 | |
77 | #define LCD_MONO_8BIT_MODE BIT(9) | |
78 | #define LCD_RASTER_ORDER BIT(8) | |
79 | #define LCD_TFT_MODE BIT(7) | |
c6daf05b MP |
80 | #define LCD_V1_UNDERFLOW_INT_ENA BIT(6) |
81 | #define LCD_V2_UNDERFLOW_INT_ENA BIT(5) | |
82 | #define LCD_V1_PL_INT_ENA BIT(4) | |
83 | #define LCD_V2_PL_INT_ENA BIT(6) | |
4ed824d9 SR |
84 | #define LCD_MONOCHROME_MODE BIT(1) |
85 | #define LCD_RASTER_ENABLE BIT(0) | |
86 | #define LCD_TFT_ALT_ENABLE BIT(23) | |
87 | #define LCD_STN_565_ENABLE BIT(24) | |
c6daf05b MP |
88 | #define LCD_V2_DMA_CLK_EN BIT(2) |
89 | #define LCD_V2_LIDD_CLK_EN BIT(1) | |
90 | #define LCD_V2_CORE_CLK_EN BIT(0) | |
91 | #define LCD_V2_LPP_B10 26 | |
1a2b750c MP |
92 | #define LCD_V2_TFT_24BPP_MODE BIT(25) |
93 | #define LCD_V2_TFT_24BPP_UNPACK BIT(26) | |
4ed824d9 SR |
94 | |
95 | /* LCD Raster Timing 2 Register */ | |
96 | #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) | |
97 | #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) | |
98 | #define LCD_SYNC_CTRL BIT(25) | |
99 | #define LCD_SYNC_EDGE BIT(24) | |
100 | #define LCD_INVERT_PIXEL_CLOCK BIT(22) | |
101 | #define LCD_INVERT_LINE_CLOCK BIT(21) | |
102 | #define LCD_INVERT_FRAME_CLOCK BIT(20) | |
103 | ||
104 | /* LCD Block */ | |
c6daf05b | 105 | #define LCD_PID_REG 0x0 |
4ed824d9 SR |
106 | #define LCD_CTRL_REG 0x4 |
107 | #define LCD_STAT_REG 0x8 | |
108 | #define LCD_RASTER_CTRL_REG 0x28 | |
109 | #define LCD_RASTER_TIMING_0_REG 0x2C | |
110 | #define LCD_RASTER_TIMING_1_REG 0x30 | |
111 | #define LCD_RASTER_TIMING_2_REG 0x34 | |
112 | #define LCD_DMA_CTRL_REG 0x40 | |
113 | #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44 | |
114 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48 | |
1f9c3e1f MA |
115 | #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C |
116 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50 | |
117 | ||
c6daf05b MP |
118 | /* Interrupt Registers available only in Version 2 */ |
119 | #define LCD_RAW_STAT_REG 0x58 | |
120 | #define LCD_MASKED_STAT_REG 0x5c | |
121 | #define LCD_INT_ENABLE_SET_REG 0x60 | |
122 | #define LCD_INT_ENABLE_CLR_REG 0x64 | |
123 | #define LCD_END_OF_INT_IND_REG 0x68 | |
124 | ||
125 | /* Clock registers available only on Version 2 */ | |
126 | #define LCD_CLK_ENABLE_REG 0x6c | |
127 | #define LCD_CLK_RESET_REG 0x70 | |
74a0efde | 128 | #define LCD_CLK_MAIN_RESET BIT(3) |
c6daf05b | 129 | |
1f9c3e1f | 130 | #define LCD_NUM_BUFFERS 2 |
4ed824d9 SR |
131 | |
132 | #define WSI_TIMEOUT 50 | |
133 | #define PALETTE_SIZE 256 | |
4ed824d9 | 134 | |
34aef6eb | 135 | static void __iomem *da8xx_fb_reg_base; |
4ed824d9 | 136 | static struct resource *lcdc_regs; |
c6daf05b MP |
137 | static unsigned int lcd_revision; |
138 | static irq_handler_t lcdc_irq_handler; | |
a481b37a MP |
139 | static wait_queue_head_t frame_done_wq; |
140 | static int frame_done_flag; | |
4ed824d9 SR |
141 | |
142 | static inline unsigned int lcdc_read(unsigned int addr) | |
143 | { | |
144 | return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr)); | |
145 | } | |
146 | ||
147 | static inline void lcdc_write(unsigned int val, unsigned int addr) | |
148 | { | |
149 | __raw_writel(val, da8xx_fb_reg_base + (addr)); | |
150 | } | |
151 | ||
152 | struct da8xx_fb_par { | |
4ed824d9 SR |
153 | resource_size_t p_palette_base; |
154 | unsigned char *v_palette_base; | |
1f9c3e1f MA |
155 | dma_addr_t vram_phys; |
156 | unsigned long vram_size; | |
157 | void *vram_virt; | |
158 | unsigned int dma_start; | |
159 | unsigned int dma_end; | |
4ed824d9 SR |
160 | struct clk *lcdc_clk; |
161 | int irq; | |
4ed824d9 | 162 | unsigned int palette_sz; |
36113804 | 163 | int blank; |
1f9c3e1f MA |
164 | wait_queue_head_t vsync_wait; |
165 | int vsync_flag; | |
166 | int vsync_timeout; | |
deb95c6c MP |
167 | spinlock_t lock_for_chan_update; |
168 | ||
169 | /* | |
170 | * LCDC has 2 ping pong DMA channels, channel 0 | |
171 | * and channel 1. | |
172 | */ | |
173 | unsigned int which_dma_channel_done; | |
e04e5483 C |
174 | #ifdef CONFIG_CPU_FREQ |
175 | struct notifier_block freq_transition; | |
176 | #endif | |
44f627ae | 177 | unsigned int lcd_fck_rate; |
36113804 | 178 | void (*panel_power_ctrl)(int); |
1a2b750c | 179 | u32 pseudo_palette[16]; |
b6dbe8e4 AM |
180 | struct fb_videomode mode; |
181 | struct lcd_ctrl_config cfg; | |
4ed824d9 SR |
182 | }; |
183 | ||
be0f6dbc | 184 | static struct fb_var_screeninfo da8xx_fb_var; |
4ed824d9 | 185 | |
48c68c4f | 186 | static struct fb_fix_screeninfo da8xx_fb_fix = { |
4ed824d9 SR |
187 | .id = "DA8xx FB Drv", |
188 | .type = FB_TYPE_PACKED_PIXELS, | |
189 | .type_aux = 0, | |
190 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
1f9c3e1f | 191 | .xpanstep = 0, |
4ed824d9 | 192 | .ypanstep = 1, |
1f9c3e1f | 193 | .ywrapstep = 0, |
4ed824d9 SR |
194 | .accel = FB_ACCEL_NONE |
195 | }; | |
196 | ||
f772fabd | 197 | static struct fb_videomode known_lcd_panels[] = { |
4ed824d9 SR |
198 | /* Sharp LCD035Q3DG01 */ |
199 | [0] = { | |
f772fabd MP |
200 | .name = "Sharp_LCD035Q3DG01", |
201 | .xres = 320, | |
202 | .yres = 240, | |
a6a799f8 | 203 | .pixclock = KHZ2PICOS(4607), |
f772fabd MP |
204 | .left_margin = 6, |
205 | .right_margin = 8, | |
206 | .upper_margin = 2, | |
207 | .lower_margin = 2, | |
208 | .hsync_len = 0, | |
209 | .vsync_len = 0, | |
3b43ad20 MP |
210 | .sync = FB_SYNC_CLK_INVERT | |
211 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
4ed824d9 SR |
212 | }, |
213 | /* Sharp LK043T1DG01 */ | |
214 | [1] = { | |
f772fabd MP |
215 | .name = "Sharp_LK043T1DG01", |
216 | .xres = 480, | |
217 | .yres = 272, | |
a6a799f8 | 218 | .pixclock = KHZ2PICOS(7833), |
f772fabd MP |
219 | .left_margin = 2, |
220 | .right_margin = 2, | |
221 | .upper_margin = 2, | |
222 | .lower_margin = 2, | |
223 | .hsync_len = 41, | |
224 | .vsync_len = 10, | |
3b43ad20 | 225 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
f772fabd | 226 | .flag = 0, |
4ed824d9 | 227 | }, |
f413070e AG |
228 | [2] = { |
229 | /* Hitachi SP10Q010 */ | |
f772fabd MP |
230 | .name = "SP10Q010", |
231 | .xres = 320, | |
232 | .yres = 240, | |
a6a799f8 | 233 | .pixclock = KHZ2PICOS(7833), |
f772fabd MP |
234 | .left_margin = 10, |
235 | .right_margin = 10, | |
236 | .upper_margin = 10, | |
237 | .lower_margin = 10, | |
238 | .hsync_len = 10, | |
239 | .vsync_len = 10, | |
3b43ad20 | 240 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
f772fabd | 241 | .flag = 0, |
f413070e | 242 | }, |
4ed824d9 SR |
243 | }; |
244 | ||
36113804 C |
245 | /* Enable the Raster Engine of the LCD Controller */ |
246 | static inline void lcd_enable_raster(void) | |
247 | { | |
248 | u32 reg; | |
249 | ||
92b4e450 MP |
250 | /* Put LCDC in reset for several cycles */ |
251 | if (lcd_revision == LCD_VERSION_2) | |
252 | /* Write 1 to reset LCDC */ | |
253 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
254 | mdelay(1); | |
255 | ||
74a0efde MP |
256 | /* Bring LCDC out of reset */ |
257 | if (lcd_revision == LCD_VERSION_2) | |
258 | lcdc_write(0, LCD_CLK_RESET_REG); | |
92b4e450 | 259 | mdelay(1); |
74a0efde | 260 | |
92b4e450 | 261 | /* Above reset sequence doesnot reset register context */ |
36113804 C |
262 | reg = lcdc_read(LCD_RASTER_CTRL_REG); |
263 | if (!(reg & LCD_RASTER_ENABLE)) | |
264 | lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); | |
265 | } | |
266 | ||
4ed824d9 | 267 | /* Disable the Raster Engine of the LCD Controller */ |
a481b37a | 268 | static inline void lcd_disable_raster(bool wait_for_frame_done) |
4ed824d9 | 269 | { |
4ed824d9 | 270 | u32 reg; |
a481b37a | 271 | int ret; |
4ed824d9 SR |
272 | |
273 | reg = lcdc_read(LCD_RASTER_CTRL_REG); | |
2f93e8f4 | 274 | if (reg & LCD_RASTER_ENABLE) |
4ed824d9 | 275 | lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); |
a481b37a MP |
276 | else |
277 | /* return if already disabled */ | |
278 | return; | |
279 | ||
280 | if ((wait_for_frame_done == true) && (lcd_revision == LCD_VERSION_2)) { | |
281 | frame_done_flag = 0; | |
282 | ret = wait_event_interruptible_timeout(frame_done_wq, | |
283 | frame_done_flag != 0, | |
284 | msecs_to_jiffies(50)); | |
285 | if (ret == 0) | |
286 | pr_err("LCD Controller timed out\n"); | |
287 | } | |
4ed824d9 SR |
288 | } |
289 | ||
290 | static void lcd_blit(int load_mode, struct da8xx_fb_par *par) | |
291 | { | |
1f9c3e1f MA |
292 | u32 start; |
293 | u32 end; | |
294 | u32 reg_ras; | |
295 | u32 reg_dma; | |
c6daf05b | 296 | u32 reg_int; |
1f9c3e1f MA |
297 | |
298 | /* init reg to clear PLM (loading mode) fields */ | |
299 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
300 | reg_ras &= ~(3 << 20); | |
301 | ||
302 | reg_dma = lcdc_read(LCD_DMA_CTRL_REG); | |
303 | ||
304 | if (load_mode == LOAD_DATA) { | |
305 | start = par->dma_start; | |
306 | end = par->dma_end; | |
307 | ||
308 | reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); | |
c6daf05b MP |
309 | if (lcd_revision == LCD_VERSION_1) { |
310 | reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; | |
311 | } else { | |
312 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
313 | LCD_V2_END_OF_FRAME0_INT_ENA | | |
a481b37a MP |
314 | LCD_V2_END_OF_FRAME1_INT_ENA | |
315 | LCD_FRAME_DONE; | |
c6daf05b MP |
316 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); |
317 | } | |
1f9c3e1f MA |
318 | reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; |
319 | ||
320 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
321 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
322 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
323 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
324 | } else if (load_mode == LOAD_PALETTE) { | |
325 | start = par->p_palette_base; | |
326 | end = start + par->palette_sz - 1; | |
327 | ||
328 | reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); | |
c6daf05b MP |
329 | |
330 | if (lcd_revision == LCD_VERSION_1) { | |
331 | reg_ras |= LCD_V1_PL_INT_ENA; | |
332 | } else { | |
333 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
334 | LCD_V2_PL_INT_ENA; | |
335 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
336 | } | |
1f9c3e1f MA |
337 | |
338 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
339 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
340 | } | |
4ed824d9 | 341 | |
1f9c3e1f MA |
342 | lcdc_write(reg_dma, LCD_DMA_CTRL_REG); |
343 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); | |
4ed824d9 | 344 | |
1f9c3e1f MA |
345 | /* |
346 | * The Raster enable bit must be set after all other control fields are | |
347 | * set. | |
348 | */ | |
349 | lcd_enable_raster(); | |
4ed824d9 SR |
350 | } |
351 | ||
fb8fa943 MP |
352 | /* Configure the Burst Size and fifo threhold of DMA */ |
353 | static int lcd_cfg_dma(int burst_size, int fifo_th) | |
4ed824d9 SR |
354 | { |
355 | u32 reg; | |
356 | ||
357 | reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001; | |
358 | switch (burst_size) { | |
359 | case 1: | |
360 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); | |
361 | break; | |
362 | case 2: | |
363 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); | |
364 | break; | |
365 | case 4: | |
366 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); | |
367 | break; | |
368 | case 8: | |
369 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); | |
370 | break; | |
371 | case 16: | |
3b43ad20 | 372 | default: |
4ed824d9 SR |
373 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); |
374 | break; | |
4ed824d9 | 375 | } |
fb8fa943 MP |
376 | |
377 | reg |= (fifo_th << 8); | |
378 | ||
2f93e8f4 | 379 | lcdc_write(reg, LCD_DMA_CTRL_REG); |
4ed824d9 SR |
380 | |
381 | return 0; | |
382 | } | |
383 | ||
384 | static void lcd_cfg_ac_bias(int period, int transitions_per_int) | |
385 | { | |
386 | u32 reg; | |
387 | ||
388 | /* Set the AC Bias Period and Number of Transisitons per Interrupt */ | |
389 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000; | |
390 | reg |= LCD_AC_BIAS_FREQUENCY(period) | | |
391 | LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); | |
392 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
393 | } | |
394 | ||
395 | static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, | |
396 | int front_porch) | |
397 | { | |
398 | u32 reg; | |
399 | ||
400 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf; | |
401 | reg |= ((back_porch & 0xff) << 24) | |
402 | | ((front_porch & 0xff) << 16) | |
403 | | ((pulse_width & 0x3f) << 10); | |
404 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); | |
405 | } | |
406 | ||
407 | static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, | |
408 | int front_porch) | |
409 | { | |
410 | u32 reg; | |
411 | ||
412 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff; | |
413 | reg |= ((back_porch & 0xff) << 24) | |
414 | | ((front_porch & 0xff) << 16) | |
415 | | ((pulse_width & 0x3f) << 10); | |
416 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
417 | } | |
418 | ||
3b43ad20 MP |
419 | static int lcd_cfg_display(const struct lcd_ctrl_config *cfg, |
420 | struct fb_videomode *panel) | |
4ed824d9 SR |
421 | { |
422 | u32 reg; | |
c6daf05b | 423 | u32 reg_int; |
4ed824d9 SR |
424 | |
425 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE | | |
426 | LCD_MONO_8BIT_MODE | | |
427 | LCD_MONOCHROME_MODE); | |
428 | ||
3b43ad20 | 429 | switch (cfg->panel_shade) { |
4ed824d9 SR |
430 | case MONOCHROME: |
431 | reg |= LCD_MONOCHROME_MODE; | |
432 | if (cfg->mono_8bit_mode) | |
433 | reg |= LCD_MONO_8BIT_MODE; | |
434 | break; | |
435 | case COLOR_ACTIVE: | |
436 | reg |= LCD_TFT_MODE; | |
437 | if (cfg->tft_alt_mode) | |
438 | reg |= LCD_TFT_ALT_ENABLE; | |
439 | break; | |
440 | ||
441 | case COLOR_PASSIVE: | |
3b43ad20 MP |
442 | /* AC bias applicable only for Pasive panels */ |
443 | lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); | |
444 | if (cfg->bpp == 12 && cfg->stn_565_mode) | |
4ed824d9 SR |
445 | reg |= LCD_STN_565_ENABLE; |
446 | break; | |
447 | ||
448 | default: | |
449 | return -EINVAL; | |
450 | } | |
451 | ||
452 | /* enable additional interrupts here */ | |
c6daf05b MP |
453 | if (lcd_revision == LCD_VERSION_1) { |
454 | reg |= LCD_V1_UNDERFLOW_INT_ENA; | |
455 | } else { | |
456 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
457 | LCD_V2_UNDERFLOW_INT_ENA; | |
458 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
459 | } | |
4ed824d9 SR |
460 | |
461 | lcdc_write(reg, LCD_RASTER_CTRL_REG); | |
462 | ||
463 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
464 | ||
3b43ad20 | 465 | reg |= LCD_SYNC_CTRL; |
4ed824d9 SR |
466 | |
467 | if (cfg->sync_edge) | |
468 | reg |= LCD_SYNC_EDGE; | |
469 | else | |
470 | reg &= ~LCD_SYNC_EDGE; | |
471 | ||
3b43ad20 | 472 | if (panel->sync & FB_SYNC_HOR_HIGH_ACT) |
4ed824d9 SR |
473 | reg |= LCD_INVERT_LINE_CLOCK; |
474 | else | |
475 | reg &= ~LCD_INVERT_LINE_CLOCK; | |
476 | ||
3b43ad20 | 477 | if (panel->sync & FB_SYNC_VERT_HIGH_ACT) |
4ed824d9 SR |
478 | reg |= LCD_INVERT_FRAME_CLOCK; |
479 | else | |
480 | reg &= ~LCD_INVERT_FRAME_CLOCK; | |
481 | ||
482 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
487 | static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, | |
488 | u32 bpp, u32 raster_order) | |
489 | { | |
1f9c3e1f | 490 | u32 reg; |
4ed824d9 | 491 | |
1a2b750c MP |
492 | if (bpp > 16 && lcd_revision == LCD_VERSION_1) |
493 | return -EINVAL; | |
494 | ||
4ed824d9 SR |
495 | /* Set the Panel Width */ |
496 | /* Pixels per line = (PPL + 1)*16 */ | |
4d740801 MP |
497 | if (lcd_revision == LCD_VERSION_1) { |
498 | /* | |
499 | * 0x3F in bits 4..9 gives max horizontal resolution = 1024 | |
500 | * pixels. | |
501 | */ | |
502 | width &= 0x3f0; | |
503 | } else { | |
504 | /* | |
505 | * 0x7F in bits 4..10 gives max horizontal resolution = 2048 | |
506 | * pixels. | |
507 | */ | |
508 | width &= 0x7f0; | |
509 | } | |
510 | ||
4ed824d9 SR |
511 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG); |
512 | reg &= 0xfffffc00; | |
4d740801 MP |
513 | if (lcd_revision == LCD_VERSION_1) { |
514 | reg |= ((width >> 4) - 1) << 4; | |
515 | } else { | |
516 | width = (width >> 4) - 1; | |
517 | reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); | |
518 | } | |
4ed824d9 SR |
519 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); |
520 | ||
521 | /* Set the Panel Height */ | |
4d740801 | 522 | /* Set bits 9:0 of Lines Per Pixel */ |
4ed824d9 SR |
523 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG); |
524 | reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); | |
525 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
526 | ||
4d740801 MP |
527 | /* Set bit 10 of Lines Per Pixel */ |
528 | if (lcd_revision == LCD_VERSION_2) { | |
529 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
530 | reg |= ((height - 1) & 0x400) << 16; | |
531 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
532 | } | |
533 | ||
4ed824d9 SR |
534 | /* Set the Raster Order of the Frame Buffer */ |
535 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8); | |
536 | if (raster_order) | |
537 | reg |= LCD_RASTER_ORDER; | |
1a2b750c MP |
538 | |
539 | par->palette_sz = 16 * 2; | |
4ed824d9 SR |
540 | |
541 | switch (bpp) { | |
542 | case 1: | |
543 | case 2: | |
544 | case 4: | |
545 | case 16: | |
1a2b750c MP |
546 | break; |
547 | case 24: | |
548 | reg |= LCD_V2_TFT_24BPP_MODE; | |
549 | case 32: | |
550 | reg |= LCD_V2_TFT_24BPP_UNPACK; | |
4ed824d9 SR |
551 | break; |
552 | ||
553 | case 8: | |
554 | par->palette_sz = 256 * 2; | |
555 | break; | |
556 | ||
557 | default: | |
558 | return -EINVAL; | |
559 | } | |
560 | ||
1a2b750c MP |
561 | lcdc_write(reg, LCD_RASTER_CTRL_REG); |
562 | ||
4ed824d9 SR |
563 | return 0; |
564 | } | |
565 | ||
1a2b750c | 566 | #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) |
4ed824d9 SR |
567 | static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, |
568 | unsigned blue, unsigned transp, | |
569 | struct fb_info *info) | |
570 | { | |
571 | struct da8xx_fb_par *par = info->par; | |
1f9c3e1f | 572 | unsigned short *palette = (unsigned short *) par->v_palette_base; |
4ed824d9 | 573 | u_short pal; |
1f9c3e1f | 574 | int update_hw = 0; |
4ed824d9 SR |
575 | |
576 | if (regno > 255) | |
577 | return 1; | |
578 | ||
579 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) | |
580 | return 1; | |
581 | ||
1a2b750c MP |
582 | if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
583 | return -EINVAL; | |
f413070e | 584 | |
1a2b750c MP |
585 | switch (info->fix.visual) { |
586 | case FB_VISUAL_TRUECOLOR: | |
587 | red = CNVT_TOHW(red, info->var.red.length); | |
588 | green = CNVT_TOHW(green, info->var.green.length); | |
589 | blue = CNVT_TOHW(blue, info->var.blue.length); | |
590 | break; | |
591 | case FB_VISUAL_PSEUDOCOLOR: | |
592 | switch (info->var.bits_per_pixel) { | |
593 | case 4: | |
594 | if (regno > 15) | |
595 | return -EINVAL; | |
596 | ||
597 | if (info->var.grayscale) { | |
598 | pal = regno; | |
599 | } else { | |
600 | red >>= 4; | |
601 | green >>= 8; | |
602 | blue >>= 12; | |
603 | ||
604 | pal = red & 0x0f00; | |
605 | pal |= green & 0x00f0; | |
606 | pal |= blue & 0x000f; | |
607 | } | |
608 | if (regno == 0) | |
609 | pal |= 0x2000; | |
610 | palette[regno] = pal; | |
611 | break; | |
612 | ||
613 | case 8: | |
f413070e AG |
614 | red >>= 4; |
615 | green >>= 8; | |
616 | blue >>= 12; | |
617 | ||
618 | pal = (red & 0x0f00); | |
619 | pal |= (green & 0x00f0); | |
620 | pal |= (blue & 0x000f); | |
4ed824d9 | 621 | |
1a2b750c MP |
622 | if (palette[regno] != pal) { |
623 | update_hw = 1; | |
624 | palette[regno] = pal; | |
625 | } | |
626 | break; | |
1f9c3e1f | 627 | } |
1a2b750c MP |
628 | break; |
629 | } | |
4ed824d9 | 630 | |
1a2b750c MP |
631 | /* Truecolor has hardware independent palette */ |
632 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { | |
633 | u32 v; | |
4ed824d9 | 634 | |
1a2b750c MP |
635 | if (regno > 15) |
636 | return -EINVAL; | |
4ed824d9 | 637 | |
1a2b750c MP |
638 | v = (red << info->var.red.offset) | |
639 | (green << info->var.green.offset) | | |
640 | (blue << info->var.blue.offset); | |
4ed824d9 | 641 | |
1a2b750c MP |
642 | switch (info->var.bits_per_pixel) { |
643 | case 16: | |
644 | ((u16 *) (info->pseudo_palette))[regno] = v; | |
645 | break; | |
646 | case 24: | |
647 | case 32: | |
648 | ((u32 *) (info->pseudo_palette))[regno] = v; | |
649 | break; | |
650 | } | |
1f9c3e1f MA |
651 | if (palette[0] != 0x4000) { |
652 | update_hw = 1; | |
653 | palette[0] = 0x4000; | |
654 | } | |
4ed824d9 SR |
655 | } |
656 | ||
1f9c3e1f MA |
657 | /* Update the palette in the h/w as needed. */ |
658 | if (update_hw) | |
659 | lcd_blit(LOAD_PALETTE, par); | |
660 | ||
4ed824d9 SR |
661 | return 0; |
662 | } | |
1a2b750c | 663 | #undef CNVT_TOHW |
4ed824d9 | 664 | |
39c87d45 | 665 | static void da8xx_fb_lcd_reset(void) |
4ed824d9 | 666 | { |
4ed824d9 | 667 | /* Disable the Raster if previously Enabled */ |
a481b37a | 668 | lcd_disable_raster(false); |
4ed824d9 SR |
669 | |
670 | /* DMA has to be disabled */ | |
671 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
672 | lcdc_write(0, LCD_RASTER_CTRL_REG); | |
c6daf05b | 673 | |
74a0efde | 674 | if (lcd_revision == LCD_VERSION_2) { |
c6daf05b | 675 | lcdc_write(0, LCD_INT_ENABLE_SET_REG); |
74a0efde MP |
676 | /* Write 1 to reset */ |
677 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
678 | lcdc_write(0, LCD_CLK_RESET_REG); | |
679 | } | |
4ed824d9 SR |
680 | } |
681 | ||
a6a799f8 DE |
682 | static inline unsigned da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par, |
683 | unsigned pixclock) | |
8097b174 | 684 | { |
a6a799f8 DE |
685 | return par->lcd_fck_rate / (PICOS2KHZ(pixclock) * 1000); |
686 | } | |
8097b174 | 687 | |
a6a799f8 DE |
688 | static inline void da8xx_fb_config_clk_divider(unsigned div) |
689 | { | |
8097b174 C |
690 | /* Configure the LCD clock divisor. */ |
691 | lcdc_write(LCD_CLK_DIVISOR(div) | | |
692 | (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG); | |
c6daf05b MP |
693 | |
694 | if (lcd_revision == LCD_VERSION_2) | |
695 | lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | | |
696 | LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG); | |
a6a799f8 DE |
697 | } |
698 | ||
699 | static inline void da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par, | |
700 | struct fb_videomode *mode) | |
701 | { | |
702 | unsigned div = da8xx_fb_calc_clk_divider(par, mode->pixclock); | |
c6daf05b | 703 | |
a6a799f8 | 704 | da8xx_fb_config_clk_divider(div); |
8097b174 C |
705 | } |
706 | ||
4ed824d9 | 707 | static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, |
f772fabd | 708 | struct fb_videomode *panel) |
4ed824d9 SR |
709 | { |
710 | u32 bpp; | |
711 | int ret = 0; | |
712 | ||
39c87d45 | 713 | da8xx_fb_lcd_reset(); |
4ed824d9 | 714 | |
a6a799f8 | 715 | da8xx_fb_calc_config_clk_divider(par, panel); |
4ed824d9 | 716 | |
f772fabd | 717 | if (panel->sync & FB_SYNC_CLK_INVERT) |
2f93e8f4 SR |
718 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) | |
719 | LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
720 | else | |
721 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) & | |
722 | ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
723 | ||
fb8fa943 MP |
724 | /* Configure the DMA burst size and fifo threshold. */ |
725 | ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th); | |
4ed824d9 SR |
726 | if (ret < 0) |
727 | return ret; | |
728 | ||
4ed824d9 | 729 | /* Configure the vertical and horizontal sync properties. */ |
f772fabd MP |
730 | lcd_cfg_vertical_sync(panel->lower_margin, panel->vsync_len, |
731 | panel->upper_margin); | |
732 | lcd_cfg_horizontal_sync(panel->right_margin, panel->hsync_len, | |
733 | panel->left_margin); | |
4ed824d9 SR |
734 | |
735 | /* Configure for disply */ | |
3b43ad20 | 736 | ret = lcd_cfg_display(cfg, panel); |
4ed824d9 SR |
737 | if (ret < 0) |
738 | return ret; | |
739 | ||
3b43ad20 | 740 | bpp = cfg->bpp; |
4ed824d9 | 741 | |
4ed824d9 SR |
742 | if (bpp == 12) |
743 | bpp = 16; | |
f772fabd MP |
744 | ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres, |
745 | (unsigned int)panel->yres, bpp, | |
4ed824d9 SR |
746 | cfg->raster_order); |
747 | if (ret < 0) | |
748 | return ret; | |
749 | ||
750 | /* Configure FDD */ | |
751 | lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) | | |
752 | (cfg->fdd << 12), LCD_RASTER_CTRL_REG); | |
753 | ||
754 | return 0; | |
755 | } | |
756 | ||
c6daf05b MP |
757 | /* IRQ handler for version 2 of LCDC */ |
758 | static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) | |
759 | { | |
760 | struct da8xx_fb_par *par = arg; | |
761 | u32 stat = lcdc_read(LCD_MASKED_STAT_REG); | |
c6daf05b MP |
762 | |
763 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
a481b37a | 764 | lcd_disable_raster(false); |
c6daf05b MP |
765 | lcdc_write(stat, LCD_MASKED_STAT_REG); |
766 | lcd_enable_raster(); | |
767 | } else if (stat & LCD_PL_LOAD_DONE) { | |
768 | /* | |
769 | * Must disable raster before changing state of any control bit. | |
770 | * And also must be disabled before clearing the PL loading | |
771 | * interrupt via the following write to the status register. If | |
772 | * this is done after then one gets multiple PL done interrupts. | |
773 | */ | |
a481b37a | 774 | lcd_disable_raster(false); |
c6daf05b MP |
775 | |
776 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
777 | ||
8a81dccd MP |
778 | /* Disable PL completion interrupt */ |
779 | lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG); | |
c6daf05b MP |
780 | |
781 | /* Setup and start data loading mode */ | |
782 | lcd_blit(LOAD_DATA, par); | |
783 | } else { | |
784 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
785 | ||
786 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 787 | par->which_dma_channel_done = 0; |
c6daf05b MP |
788 | lcdc_write(par->dma_start, |
789 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
790 | lcdc_write(par->dma_end, | |
791 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
792 | par->vsync_flag = 1; | |
793 | wake_up_interruptible(&par->vsync_wait); | |
794 | } | |
795 | ||
796 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 797 | par->which_dma_channel_done = 1; |
c6daf05b MP |
798 | lcdc_write(par->dma_start, |
799 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
800 | lcdc_write(par->dma_end, | |
801 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
802 | par->vsync_flag = 1; | |
803 | wake_up_interruptible(&par->vsync_wait); | |
804 | } | |
a481b37a MP |
805 | |
806 | /* Set only when controller is disabled and at the end of | |
807 | * active frame | |
808 | */ | |
809 | if (stat & BIT(0)) { | |
810 | frame_done_flag = 1; | |
811 | wake_up_interruptible(&frame_done_wq); | |
812 | } | |
c6daf05b MP |
813 | } |
814 | ||
815 | lcdc_write(0, LCD_END_OF_INT_IND_REG); | |
816 | return IRQ_HANDLED; | |
817 | } | |
818 | ||
819 | /* IRQ handler for version 1 LCDC */ | |
820 | static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg) | |
4ed824d9 | 821 | { |
1f9c3e1f | 822 | struct da8xx_fb_par *par = arg; |
4ed824d9 | 823 | u32 stat = lcdc_read(LCD_STAT_REG); |
1f9c3e1f | 824 | u32 reg_ras; |
4ed824d9 SR |
825 | |
826 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
a481b37a | 827 | lcd_disable_raster(false); |
4ed824d9 | 828 | lcdc_write(stat, LCD_STAT_REG); |
36113804 | 829 | lcd_enable_raster(); |
1f9c3e1f MA |
830 | } else if (stat & LCD_PL_LOAD_DONE) { |
831 | /* | |
832 | * Must disable raster before changing state of any control bit. | |
833 | * And also must be disabled before clearing the PL loading | |
834 | * interrupt via the following write to the status register. If | |
835 | * this is done after then one gets multiple PL done interrupts. | |
836 | */ | |
a481b37a | 837 | lcd_disable_raster(false); |
1f9c3e1f | 838 | |
4ed824d9 SR |
839 | lcdc_write(stat, LCD_STAT_REG); |
840 | ||
1f9c3e1f MA |
841 | /* Disable PL completion inerrupt */ |
842 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
c6daf05b | 843 | reg_ras &= ~LCD_V1_PL_INT_ENA; |
1f9c3e1f MA |
844 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); |
845 | ||
846 | /* Setup and start data loading mode */ | |
847 | lcd_blit(LOAD_DATA, par); | |
848 | } else { | |
849 | lcdc_write(stat, LCD_STAT_REG); | |
850 | ||
851 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 852 | par->which_dma_channel_done = 0; |
1f9c3e1f MA |
853 | lcdc_write(par->dma_start, |
854 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
855 | lcdc_write(par->dma_end, | |
856 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
857 | par->vsync_flag = 1; | |
858 | wake_up_interruptible(&par->vsync_wait); | |
859 | } | |
860 | ||
861 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 862 | par->which_dma_channel_done = 1; |
1f9c3e1f MA |
863 | lcdc_write(par->dma_start, |
864 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
865 | lcdc_write(par->dma_end, | |
866 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
867 | par->vsync_flag = 1; | |
868 | wake_up_interruptible(&par->vsync_wait); | |
869 | } | |
870 | } | |
871 | ||
4ed824d9 SR |
872 | return IRQ_HANDLED; |
873 | } | |
874 | ||
875 | static int fb_check_var(struct fb_var_screeninfo *var, | |
876 | struct fb_info *info) | |
877 | { | |
878 | int err = 0; | |
87dac71d AM |
879 | struct da8xx_fb_par *par = info->par; |
880 | int bpp = var->bits_per_pixel >> 3; | |
881 | unsigned long line_size = var->xres_virtual * bpp; | |
4ed824d9 | 882 | |
1a2b750c MP |
883 | if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
884 | return -EINVAL; | |
885 | ||
4ed824d9 SR |
886 | switch (var->bits_per_pixel) { |
887 | case 1: | |
888 | case 8: | |
889 | var->red.offset = 0; | |
890 | var->red.length = 8; | |
891 | var->green.offset = 0; | |
892 | var->green.length = 8; | |
893 | var->blue.offset = 0; | |
894 | var->blue.length = 8; | |
895 | var->transp.offset = 0; | |
896 | var->transp.length = 0; | |
f413070e | 897 | var->nonstd = 0; |
4ed824d9 SR |
898 | break; |
899 | case 4: | |
900 | var->red.offset = 0; | |
901 | var->red.length = 4; | |
902 | var->green.offset = 0; | |
903 | var->green.length = 4; | |
904 | var->blue.offset = 0; | |
905 | var->blue.length = 4; | |
906 | var->transp.offset = 0; | |
907 | var->transp.length = 0; | |
f413070e | 908 | var->nonstd = FB_NONSTD_REV_PIX_IN_B; |
4ed824d9 SR |
909 | break; |
910 | case 16: /* RGB 565 */ | |
3510b8f7 | 911 | var->red.offset = 11; |
4ed824d9 SR |
912 | var->red.length = 5; |
913 | var->green.offset = 5; | |
914 | var->green.length = 6; | |
3510b8f7 | 915 | var->blue.offset = 0; |
4ed824d9 SR |
916 | var->blue.length = 5; |
917 | var->transp.offset = 0; | |
918 | var->transp.length = 0; | |
f413070e | 919 | var->nonstd = 0; |
4ed824d9 | 920 | break; |
1a2b750c MP |
921 | case 24: |
922 | var->red.offset = 16; | |
923 | var->red.length = 8; | |
924 | var->green.offset = 8; | |
925 | var->green.length = 8; | |
926 | var->blue.offset = 0; | |
927 | var->blue.length = 8; | |
928 | var->nonstd = 0; | |
929 | break; | |
930 | case 32: | |
931 | var->transp.offset = 24; | |
932 | var->transp.length = 8; | |
933 | var->red.offset = 16; | |
934 | var->red.length = 8; | |
935 | var->green.offset = 8; | |
936 | var->green.length = 8; | |
937 | var->blue.offset = 0; | |
938 | var->blue.length = 8; | |
939 | var->nonstd = 0; | |
940 | break; | |
4ed824d9 SR |
941 | default: |
942 | err = -EINVAL; | |
943 | } | |
944 | ||
945 | var->red.msb_right = 0; | |
946 | var->green.msb_right = 0; | |
947 | var->blue.msb_right = 0; | |
948 | var->transp.msb_right = 0; | |
87dac71d AM |
949 | |
950 | if (line_size * var->yres_virtual > par->vram_size) | |
951 | var->yres_virtual = par->vram_size / line_size; | |
952 | ||
953 | if (var->yres > var->yres_virtual) | |
954 | var->yres = var->yres_virtual; | |
955 | ||
956 | if (var->xres > var->xres_virtual) | |
957 | var->xres = var->xres_virtual; | |
958 | ||
959 | if (var->xres + var->xoffset > var->xres_virtual) | |
960 | var->xoffset = var->xres_virtual - var->xres; | |
961 | if (var->yres + var->yoffset > var->yres_virtual) | |
962 | var->yoffset = var->yres_virtual - var->yres; | |
963 | ||
4ed824d9 SR |
964 | return err; |
965 | } | |
966 | ||
e04e5483 C |
967 | #ifdef CONFIG_CPU_FREQ |
968 | static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb, | |
969 | unsigned long val, void *data) | |
970 | { | |
971 | struct da8xx_fb_par *par; | |
e04e5483 C |
972 | |
973 | par = container_of(nb, struct da8xx_fb_par, freq_transition); | |
f820917a MP |
974 | if (val == CPUFREQ_POSTCHANGE) { |
975 | if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) { | |
976 | par->lcd_fck_rate = clk_get_rate(par->lcdc_clk); | |
a481b37a | 977 | lcd_disable_raster(true); |
a6a799f8 | 978 | da8xx_fb_calc_config_clk_divider(par, &par->mode); |
67900814 MP |
979 | if (par->blank == FB_BLANK_UNBLANK) |
980 | lcd_enable_raster(); | |
f820917a | 981 | } |
e04e5483 C |
982 | } |
983 | ||
984 | return 0; | |
985 | } | |
986 | ||
987 | static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par) | |
988 | { | |
989 | par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition; | |
990 | ||
991 | return cpufreq_register_notifier(&par->freq_transition, | |
992 | CPUFREQ_TRANSITION_NOTIFIER); | |
993 | } | |
994 | ||
995 | static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par) | |
996 | { | |
997 | cpufreq_unregister_notifier(&par->freq_transition, | |
998 | CPUFREQ_TRANSITION_NOTIFIER); | |
999 | } | |
1000 | #endif | |
1001 | ||
48c68c4f | 1002 | static int fb_remove(struct platform_device *dev) |
4ed824d9 SR |
1003 | { |
1004 | struct fb_info *info = dev_get_drvdata(&dev->dev); | |
4ed824d9 SR |
1005 | |
1006 | if (info) { | |
1007 | struct da8xx_fb_par *par = info->par; | |
1008 | ||
e04e5483 C |
1009 | #ifdef CONFIG_CPU_FREQ |
1010 | lcd_da8xx_cpufreq_deregister(par); | |
1011 | #endif | |
36113804 C |
1012 | if (par->panel_power_ctrl) |
1013 | par->panel_power_ctrl(0); | |
1014 | ||
a481b37a | 1015 | lcd_disable_raster(true); |
4ed824d9 SR |
1016 | lcdc_write(0, LCD_RASTER_CTRL_REG); |
1017 | ||
1018 | /* disable DMA */ | |
1019 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
1020 | ||
1021 | unregister_framebuffer(info); | |
1022 | fb_dealloc_cmap(&info->cmap); | |
1f9c3e1f MA |
1023 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, |
1024 | par->p_palette_base); | |
1025 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, | |
1026 | par->vram_phys); | |
4ed824d9 | 1027 | free_irq(par->irq, par); |
9dd44d5d MP |
1028 | pm_runtime_put_sync(&dev->dev); |
1029 | pm_runtime_disable(&dev->dev); | |
4ed824d9 | 1030 | framebuffer_release(info); |
34aef6eb | 1031 | iounmap(da8xx_fb_reg_base); |
4ed824d9 SR |
1032 | release_mem_region(lcdc_regs->start, resource_size(lcdc_regs)); |
1033 | ||
1034 | } | |
2f93e8f4 | 1035 | return 0; |
4ed824d9 SR |
1036 | } |
1037 | ||
1f9c3e1f MA |
1038 | /* |
1039 | * Function to wait for vertical sync which for this LCD peripheral | |
1040 | * translates into waiting for the current raster frame to complete. | |
1041 | */ | |
1042 | static int fb_wait_for_vsync(struct fb_info *info) | |
1043 | { | |
1044 | struct da8xx_fb_par *par = info->par; | |
1045 | int ret; | |
1046 | ||
1047 | /* | |
1048 | * Set flag to 0 and wait for isr to set to 1. It would seem there is a | |
25985edc | 1049 | * race condition here where the ISR could have occurred just before or |
1f9c3e1f MA |
1050 | * just after this set. But since we are just coarsely waiting for |
1051 | * a frame to complete then that's OK. i.e. if the frame completed | |
1052 | * just before this code executed then we have to wait another full | |
1053 | * frame time but there is no way to avoid such a situation. On the | |
1054 | * other hand if the frame completed just after then we don't need | |
1055 | * to wait long at all. Either way we are guaranteed to return to the | |
1056 | * user immediately after a frame completion which is all that is | |
1057 | * required. | |
1058 | */ | |
1059 | par->vsync_flag = 0; | |
1060 | ret = wait_event_interruptible_timeout(par->vsync_wait, | |
1061 | par->vsync_flag != 0, | |
1062 | par->vsync_timeout); | |
1063 | if (ret < 0) | |
1064 | return ret; | |
1065 | if (ret == 0) | |
1066 | return -ETIMEDOUT; | |
1067 | ||
1068 | return 0; | |
1069 | } | |
1070 | ||
4ed824d9 SR |
1071 | static int fb_ioctl(struct fb_info *info, unsigned int cmd, |
1072 | unsigned long arg) | |
1073 | { | |
1074 | struct lcd_sync_arg sync_arg; | |
1075 | ||
1076 | switch (cmd) { | |
1077 | case FBIOGET_CONTRAST: | |
1078 | case FBIOPUT_CONTRAST: | |
1079 | case FBIGET_BRIGHTNESS: | |
1080 | case FBIPUT_BRIGHTNESS: | |
1081 | case FBIGET_COLOR: | |
1082 | case FBIPUT_COLOR: | |
2f93e8f4 | 1083 | return -ENOTTY; |
4ed824d9 SR |
1084 | case FBIPUT_HSYNC: |
1085 | if (copy_from_user(&sync_arg, (char *)arg, | |
1086 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1087 | return -EFAULT; |
4ed824d9 SR |
1088 | lcd_cfg_horizontal_sync(sync_arg.back_porch, |
1089 | sync_arg.pulse_width, | |
1090 | sync_arg.front_porch); | |
1091 | break; | |
1092 | case FBIPUT_VSYNC: | |
1093 | if (copy_from_user(&sync_arg, (char *)arg, | |
1094 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1095 | return -EFAULT; |
4ed824d9 SR |
1096 | lcd_cfg_vertical_sync(sync_arg.back_porch, |
1097 | sync_arg.pulse_width, | |
1098 | sync_arg.front_porch); | |
1099 | break; | |
1f9c3e1f MA |
1100 | case FBIO_WAITFORVSYNC: |
1101 | return fb_wait_for_vsync(info); | |
4ed824d9 SR |
1102 | default: |
1103 | return -EINVAL; | |
1104 | } | |
1105 | return 0; | |
1106 | } | |
1107 | ||
312d9715 C |
1108 | static int cfb_blank(int blank, struct fb_info *info) |
1109 | { | |
1110 | struct da8xx_fb_par *par = info->par; | |
1111 | int ret = 0; | |
1112 | ||
1113 | if (par->blank == blank) | |
1114 | return 0; | |
1115 | ||
1116 | par->blank = blank; | |
1117 | switch (blank) { | |
1118 | case FB_BLANK_UNBLANK: | |
f7c848b6 MP |
1119 | lcd_enable_raster(); |
1120 | ||
312d9715 C |
1121 | if (par->panel_power_ctrl) |
1122 | par->panel_power_ctrl(1); | |
312d9715 | 1123 | break; |
99a647d1 YY |
1124 | case FB_BLANK_NORMAL: |
1125 | case FB_BLANK_VSYNC_SUSPEND: | |
1126 | case FB_BLANK_HSYNC_SUSPEND: | |
312d9715 C |
1127 | case FB_BLANK_POWERDOWN: |
1128 | if (par->panel_power_ctrl) | |
1129 | par->panel_power_ctrl(0); | |
1130 | ||
a481b37a | 1131 | lcd_disable_raster(true); |
312d9715 C |
1132 | break; |
1133 | default: | |
1134 | ret = -EINVAL; | |
1135 | } | |
1136 | ||
1137 | return ret; | |
1138 | } | |
1139 | ||
1f9c3e1f MA |
1140 | /* |
1141 | * Set new x,y offsets in the virtual display for the visible area and switch | |
1142 | * to the new mode. | |
1143 | */ | |
1144 | static int da8xx_pan_display(struct fb_var_screeninfo *var, | |
1145 | struct fb_info *fbi) | |
1146 | { | |
1147 | int ret = 0; | |
1148 | struct fb_var_screeninfo new_var; | |
1149 | struct da8xx_fb_par *par = fbi->par; | |
1150 | struct fb_fix_screeninfo *fix = &fbi->fix; | |
1151 | unsigned int end; | |
1152 | unsigned int start; | |
deb95c6c | 1153 | unsigned long irq_flags; |
1f9c3e1f MA |
1154 | |
1155 | if (var->xoffset != fbi->var.xoffset || | |
1156 | var->yoffset != fbi->var.yoffset) { | |
1157 | memcpy(&new_var, &fbi->var, sizeof(new_var)); | |
1158 | new_var.xoffset = var->xoffset; | |
1159 | new_var.yoffset = var->yoffset; | |
1160 | if (fb_check_var(&new_var, fbi)) | |
1161 | ret = -EINVAL; | |
1162 | else { | |
1163 | memcpy(&fbi->var, &new_var, sizeof(new_var)); | |
1164 | ||
1165 | start = fix->smem_start + | |
1166 | new_var.yoffset * fix->line_length + | |
e6c4d3d4 LP |
1167 | new_var.xoffset * fbi->var.bits_per_pixel / 8; |
1168 | end = start + fbi->var.yres * fix->line_length - 1; | |
1f9c3e1f MA |
1169 | par->dma_start = start; |
1170 | par->dma_end = end; | |
deb95c6c MP |
1171 | spin_lock_irqsave(&par->lock_for_chan_update, |
1172 | irq_flags); | |
1173 | if (par->which_dma_channel_done == 0) { | |
1174 | lcdc_write(par->dma_start, | |
1175 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1176 | lcdc_write(par->dma_end, | |
1177 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1178 | } else if (par->which_dma_channel_done == 1) { | |
1179 | lcdc_write(par->dma_start, | |
1180 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1181 | lcdc_write(par->dma_end, | |
1182 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1183 | } | |
1184 | spin_unlock_irqrestore(&par->lock_for_chan_update, | |
1185 | irq_flags); | |
1f9c3e1f MA |
1186 | } |
1187 | } | |
1188 | ||
1189 | return ret; | |
1190 | } | |
1191 | ||
4ed824d9 SR |
1192 | static struct fb_ops da8xx_fb_ops = { |
1193 | .owner = THIS_MODULE, | |
1194 | .fb_check_var = fb_check_var, | |
1195 | .fb_setcolreg = fb_setcolreg, | |
1f9c3e1f | 1196 | .fb_pan_display = da8xx_pan_display, |
4ed824d9 SR |
1197 | .fb_ioctl = fb_ioctl, |
1198 | .fb_fillrect = cfb_fillrect, | |
1199 | .fb_copyarea = cfb_copyarea, | |
1200 | .fb_imageblit = cfb_imageblit, | |
312d9715 | 1201 | .fb_blank = cfb_blank, |
4ed824d9 SR |
1202 | }; |
1203 | ||
48c68c4f | 1204 | static int fb_probe(struct platform_device *device) |
4ed824d9 SR |
1205 | { |
1206 | struct da8xx_lcdc_platform_data *fb_pdata = | |
1207 | device->dev.platform_data; | |
1208 | struct lcd_ctrl_config *lcd_cfg; | |
f772fabd | 1209 | struct fb_videomode *lcdc_info; |
4ed824d9 SR |
1210 | struct fb_info *da8xx_fb_info; |
1211 | struct clk *fb_clk = NULL; | |
1212 | struct da8xx_fb_par *par; | |
1213 | resource_size_t len; | |
1214 | int ret, i; | |
3b9cc4ea | 1215 | unsigned long ulcm; |
4ed824d9 SR |
1216 | |
1217 | if (fb_pdata == NULL) { | |
1218 | dev_err(&device->dev, "Can not get platform data\n"); | |
1219 | return -ENOENT; | |
1220 | } | |
1221 | ||
1222 | lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0); | |
1223 | if (!lcdc_regs) { | |
1224 | dev_err(&device->dev, | |
1225 | "Can not get memory resource for LCD controller\n"); | |
1226 | return -ENOENT; | |
1227 | } | |
1228 | ||
1229 | len = resource_size(lcdc_regs); | |
1230 | ||
1231 | lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name); | |
1232 | if (!lcdc_regs) | |
1233 | return -EBUSY; | |
1234 | ||
34aef6eb | 1235 | da8xx_fb_reg_base = ioremap(lcdc_regs->start, len); |
4ed824d9 SR |
1236 | if (!da8xx_fb_reg_base) { |
1237 | ret = -EBUSY; | |
1238 | goto err_request_mem; | |
1239 | } | |
1240 | ||
81cec3c7 | 1241 | fb_clk = clk_get(&device->dev, "fck"); |
4ed824d9 SR |
1242 | if (IS_ERR(fb_clk)) { |
1243 | dev_err(&device->dev, "Can not get device clock\n"); | |
1244 | ret = -ENODEV; | |
1245 | goto err_ioremap; | |
1246 | } | |
9dd44d5d MP |
1247 | |
1248 | pm_runtime_enable(&device->dev); | |
1249 | pm_runtime_get_sync(&device->dev); | |
4ed824d9 | 1250 | |
c6daf05b MP |
1251 | /* Determine LCD IP Version */ |
1252 | switch (lcdc_read(LCD_PID_REG)) { | |
1253 | case 0x4C100102: | |
1254 | lcd_revision = LCD_VERSION_1; | |
1255 | break; | |
1256 | case 0x4F200800: | |
8f22e8ea | 1257 | case 0x4F201000: |
c6daf05b MP |
1258 | lcd_revision = LCD_VERSION_2; |
1259 | break; | |
1260 | default: | |
1261 | dev_warn(&device->dev, "Unknown PID Reg value 0x%x, " | |
1262 | "defaulting to LCD revision 1\n", | |
1263 | lcdc_read(LCD_PID_REG)); | |
1264 | lcd_revision = LCD_VERSION_1; | |
1265 | break; | |
1266 | } | |
1267 | ||
4ed824d9 SR |
1268 | for (i = 0, lcdc_info = known_lcd_panels; |
1269 | i < ARRAY_SIZE(known_lcd_panels); | |
1270 | i++, lcdc_info++) { | |
1271 | if (strcmp(fb_pdata->type, lcdc_info->name) == 0) | |
1272 | break; | |
1273 | } | |
1274 | ||
1275 | if (i == ARRAY_SIZE(known_lcd_panels)) { | |
1276 | dev_err(&device->dev, "GLCD: No valid panel found\n"); | |
dd04a6b3 | 1277 | ret = -ENODEV; |
9dd44d5d | 1278 | goto err_pm_runtime_disable; |
4ed824d9 SR |
1279 | } else |
1280 | dev_info(&device->dev, "GLCD: Found %s panel\n", | |
1281 | fb_pdata->type); | |
1282 | ||
1283 | lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data; | |
1284 | ||
1285 | da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par), | |
1286 | &device->dev); | |
1287 | if (!da8xx_fb_info) { | |
1288 | dev_dbg(&device->dev, "Memory allocation failed for fb_info\n"); | |
1289 | ret = -ENOMEM; | |
9dd44d5d | 1290 | goto err_pm_runtime_disable; |
4ed824d9 SR |
1291 | } |
1292 | ||
1293 | par = da8xx_fb_info->par; | |
8097b174 | 1294 | par->lcdc_clk = fb_clk; |
f820917a | 1295 | par->lcd_fck_rate = clk_get_rate(fb_clk); |
36113804 C |
1296 | if (fb_pdata->panel_power_ctrl) { |
1297 | par->panel_power_ctrl = fb_pdata->panel_power_ctrl; | |
1298 | par->panel_power_ctrl(1); | |
1299 | } | |
4ed824d9 | 1300 | |
b866458b | 1301 | fb_videomode_to_var(&da8xx_fb_var, lcdc_info); |
b6dbe8e4 AM |
1302 | fb_var_to_videomode(&par->mode, &da8xx_fb_var); |
1303 | par->cfg = *lcd_cfg; | |
b866458b | 1304 | |
4ed824d9 SR |
1305 | if (lcd_init(par, lcd_cfg, lcdc_info) < 0) { |
1306 | dev_err(&device->dev, "lcd_init failed\n"); | |
1307 | ret = -EFAULT; | |
1308 | goto err_release_fb; | |
1309 | } | |
1310 | ||
1311 | /* allocate frame buffer */ | |
f772fabd MP |
1312 | par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp; |
1313 | ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE); | |
3b9cc4ea | 1314 | par->vram_size = roundup(par->vram_size/8, ulcm); |
1f9c3e1f MA |
1315 | par->vram_size = par->vram_size * LCD_NUM_BUFFERS; |
1316 | ||
1317 | par->vram_virt = dma_alloc_coherent(NULL, | |
1318 | par->vram_size, | |
1319 | (resource_size_t *) &par->vram_phys, | |
1320 | GFP_KERNEL | GFP_DMA); | |
1321 | if (!par->vram_virt) { | |
4ed824d9 SR |
1322 | dev_err(&device->dev, |
1323 | "GLCD: kmalloc for frame buffer failed\n"); | |
1324 | ret = -EINVAL; | |
1325 | goto err_release_fb; | |
1326 | } | |
1327 | ||
1f9c3e1f MA |
1328 | da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt; |
1329 | da8xx_fb_fix.smem_start = par->vram_phys; | |
1330 | da8xx_fb_fix.smem_len = par->vram_size; | |
f772fabd | 1331 | da8xx_fb_fix.line_length = (lcdc_info->xres * lcd_cfg->bpp) / 8; |
1f9c3e1f MA |
1332 | |
1333 | par->dma_start = par->vram_phys; | |
f772fabd | 1334 | par->dma_end = par->dma_start + lcdc_info->yres * |
1f9c3e1f MA |
1335 | da8xx_fb_fix.line_length - 1; |
1336 | ||
1337 | /* allocate palette buffer */ | |
1338 | par->v_palette_base = dma_alloc_coherent(NULL, | |
1339 | PALETTE_SIZE, | |
1340 | (resource_size_t *) | |
1341 | &par->p_palette_base, | |
1342 | GFP_KERNEL | GFP_DMA); | |
1343 | if (!par->v_palette_base) { | |
1344 | dev_err(&device->dev, | |
1345 | "GLCD: kmalloc for palette buffer failed\n"); | |
1346 | ret = -EINVAL; | |
1347 | goto err_release_fb_mem; | |
1348 | } | |
1349 | memset(par->v_palette_base, 0, PALETTE_SIZE); | |
4ed824d9 | 1350 | |
4ed824d9 SR |
1351 | par->irq = platform_get_irq(device, 0); |
1352 | if (par->irq < 0) { | |
1353 | ret = -ENOENT; | |
1f9c3e1f | 1354 | goto err_release_pl_mem; |
4ed824d9 SR |
1355 | } |
1356 | ||
4ed824d9 | 1357 | da8xx_fb_var.grayscale = |
3b43ad20 | 1358 | lcd_cfg->panel_shade == MONOCHROME ? 1 : 0; |
4ed824d9 | 1359 | da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; |
4ed824d9 SR |
1360 | |
1361 | /* Initialize fbinfo */ | |
1362 | da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; | |
1363 | da8xx_fb_info->fix = da8xx_fb_fix; | |
1364 | da8xx_fb_info->var = da8xx_fb_var; | |
1365 | da8xx_fb_info->fbops = &da8xx_fb_ops; | |
1366 | da8xx_fb_info->pseudo_palette = par->pseudo_palette; | |
3510b8f7 SR |
1367 | da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? |
1368 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
4ed824d9 SR |
1369 | |
1370 | ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0); | |
1371 | if (ret) | |
93c176f3 | 1372 | goto err_release_pl_mem; |
4ed824d9 SR |
1373 | da8xx_fb_info->cmap.len = par->palette_sz; |
1374 | ||
4ed824d9 SR |
1375 | /* initialize var_screeninfo */ |
1376 | da8xx_fb_var.activate = FB_ACTIVATE_FORCE; | |
1377 | fb_set_var(da8xx_fb_info, &da8xx_fb_var); | |
1378 | ||
1379 | dev_set_drvdata(&device->dev, da8xx_fb_info); | |
1f9c3e1f MA |
1380 | |
1381 | /* initialize the vsync wait queue */ | |
1382 | init_waitqueue_head(&par->vsync_wait); | |
1383 | par->vsync_timeout = HZ / 5; | |
deb95c6c MP |
1384 | par->which_dma_channel_done = -1; |
1385 | spin_lock_init(&par->lock_for_chan_update); | |
1f9c3e1f | 1386 | |
4ed824d9 SR |
1387 | /* Register the Frame Buffer */ |
1388 | if (register_framebuffer(da8xx_fb_info) < 0) { | |
1389 | dev_err(&device->dev, | |
1390 | "GLCD: Frame Buffer Registration Failed!\n"); | |
1391 | ret = -EINVAL; | |
1392 | goto err_dealloc_cmap; | |
1393 | } | |
1394 | ||
e04e5483 C |
1395 | #ifdef CONFIG_CPU_FREQ |
1396 | ret = lcd_da8xx_cpufreq_register(par); | |
1397 | if (ret) { | |
1398 | dev_err(&device->dev, "failed to register cpufreq\n"); | |
1399 | goto err_cpu_freq; | |
1400 | } | |
1401 | #endif | |
93c176f3 | 1402 | |
c6daf05b MP |
1403 | if (lcd_revision == LCD_VERSION_1) |
1404 | lcdc_irq_handler = lcdc_irq_handler_rev01; | |
a481b37a MP |
1405 | else { |
1406 | init_waitqueue_head(&frame_done_wq); | |
c6daf05b | 1407 | lcdc_irq_handler = lcdc_irq_handler_rev02; |
a481b37a | 1408 | } |
c6daf05b MP |
1409 | |
1410 | ret = request_irq(par->irq, lcdc_irq_handler, 0, | |
1411 | DRIVER_NAME, par); | |
93c176f3 CA |
1412 | if (ret) |
1413 | goto irq_freq; | |
4ed824d9 SR |
1414 | return 0; |
1415 | ||
93c176f3 | 1416 | irq_freq: |
e04e5483 | 1417 | #ifdef CONFIG_CPU_FREQ |
360c202b | 1418 | lcd_da8xx_cpufreq_deregister(par); |
e04e5483 | 1419 | err_cpu_freq: |
3a84409c | 1420 | #endif |
e04e5483 | 1421 | unregister_framebuffer(da8xx_fb_info); |
e04e5483 | 1422 | |
4ed824d9 SR |
1423 | err_dealloc_cmap: |
1424 | fb_dealloc_cmap(&da8xx_fb_info->cmap); | |
1425 | ||
1f9c3e1f MA |
1426 | err_release_pl_mem: |
1427 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, | |
1428 | par->p_palette_base); | |
1429 | ||
4ed824d9 | 1430 | err_release_fb_mem: |
1f9c3e1f | 1431 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys); |
4ed824d9 SR |
1432 | |
1433 | err_release_fb: | |
1434 | framebuffer_release(da8xx_fb_info); | |
1435 | ||
9dd44d5d MP |
1436 | err_pm_runtime_disable: |
1437 | pm_runtime_put_sync(&device->dev); | |
1438 | pm_runtime_disable(&device->dev); | |
4ed824d9 SR |
1439 | |
1440 | err_ioremap: | |
34aef6eb | 1441 | iounmap(da8xx_fb_reg_base); |
4ed824d9 SR |
1442 | |
1443 | err_request_mem: | |
1444 | release_mem_region(lcdc_regs->start, len); | |
1445 | ||
1446 | return ret; | |
1447 | } | |
1448 | ||
1449 | #ifdef CONFIG_PM | |
7a93cbbb MP |
1450 | struct lcdc_context { |
1451 | u32 clk_enable; | |
1452 | u32 ctrl; | |
1453 | u32 dma_ctrl; | |
1454 | u32 raster_timing_0; | |
1455 | u32 raster_timing_1; | |
1456 | u32 raster_timing_2; | |
1457 | u32 int_enable_set; | |
1458 | u32 dma_frm_buf_base_addr_0; | |
1459 | u32 dma_frm_buf_ceiling_addr_0; | |
1460 | u32 dma_frm_buf_base_addr_1; | |
1461 | u32 dma_frm_buf_ceiling_addr_1; | |
1462 | u32 raster_ctrl; | |
1463 | } reg_context; | |
1464 | ||
1465 | static void lcd_context_save(void) | |
1466 | { | |
1467 | if (lcd_revision == LCD_VERSION_2) { | |
1468 | reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG); | |
1469 | reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG); | |
1470 | } | |
1471 | ||
1472 | reg_context.ctrl = lcdc_read(LCD_CTRL_REG); | |
1473 | reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG); | |
1474 | reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG); | |
1475 | reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG); | |
1476 | reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
1477 | reg_context.dma_frm_buf_base_addr_0 = | |
1478 | lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1479 | reg_context.dma_frm_buf_ceiling_addr_0 = | |
1480 | lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1481 | reg_context.dma_frm_buf_base_addr_1 = | |
1482 | lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1483 | reg_context.dma_frm_buf_ceiling_addr_1 = | |
1484 | lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1485 | reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG); | |
1486 | return; | |
1487 | } | |
1488 | ||
1489 | static void lcd_context_restore(void) | |
1490 | { | |
1491 | if (lcd_revision == LCD_VERSION_2) { | |
1492 | lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG); | |
1493 | lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG); | |
1494 | } | |
1495 | ||
1496 | lcdc_write(reg_context.ctrl, LCD_CTRL_REG); | |
1497 | lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG); | |
1498 | lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG); | |
1499 | lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG); | |
1500 | lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG); | |
1501 | lcdc_write(reg_context.dma_frm_buf_base_addr_0, | |
1502 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1503 | lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0, | |
1504 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1505 | lcdc_write(reg_context.dma_frm_buf_base_addr_1, | |
1506 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1507 | lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1, | |
1508 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1509 | lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG); | |
1510 | return; | |
1511 | } | |
1512 | ||
4ed824d9 SR |
1513 | static int fb_suspend(struct platform_device *dev, pm_message_t state) |
1514 | { | |
1d3c6c7b C |
1515 | struct fb_info *info = platform_get_drvdata(dev); |
1516 | struct da8xx_fb_par *par = info->par; | |
1517 | ||
ac751efa | 1518 | console_lock(); |
1d3c6c7b C |
1519 | if (par->panel_power_ctrl) |
1520 | par->panel_power_ctrl(0); | |
1521 | ||
1522 | fb_set_suspend(info, 1); | |
a481b37a | 1523 | lcd_disable_raster(true); |
7a93cbbb | 1524 | lcd_context_save(); |
9dd44d5d | 1525 | pm_runtime_put_sync(&dev->dev); |
ac751efa | 1526 | console_unlock(); |
1d3c6c7b C |
1527 | |
1528 | return 0; | |
4ed824d9 SR |
1529 | } |
1530 | static int fb_resume(struct platform_device *dev) | |
1531 | { | |
1d3c6c7b C |
1532 | struct fb_info *info = platform_get_drvdata(dev); |
1533 | struct da8xx_fb_par *par = info->par; | |
1534 | ||
ac751efa | 1535 | console_lock(); |
9dd44d5d | 1536 | pm_runtime_get_sync(&dev->dev); |
7a93cbbb | 1537 | lcd_context_restore(); |
67900814 MP |
1538 | if (par->blank == FB_BLANK_UNBLANK) { |
1539 | lcd_enable_raster(); | |
f7c848b6 | 1540 | |
67900814 MP |
1541 | if (par->panel_power_ctrl) |
1542 | par->panel_power_ctrl(1); | |
1543 | } | |
1d3c6c7b | 1544 | |
1d3c6c7b | 1545 | fb_set_suspend(info, 0); |
ac751efa | 1546 | console_unlock(); |
1d3c6c7b C |
1547 | |
1548 | return 0; | |
4ed824d9 SR |
1549 | } |
1550 | #else | |
1551 | #define fb_suspend NULL | |
1552 | #define fb_resume NULL | |
1553 | #endif | |
1554 | ||
1555 | static struct platform_driver da8xx_fb_driver = { | |
1556 | .probe = fb_probe, | |
48c68c4f | 1557 | .remove = fb_remove, |
4ed824d9 SR |
1558 | .suspend = fb_suspend, |
1559 | .resume = fb_resume, | |
1560 | .driver = { | |
1561 | .name = DRIVER_NAME, | |
1562 | .owner = THIS_MODULE, | |
1563 | }, | |
1564 | }; | |
1565 | ||
1566 | static int __init da8xx_fb_init(void) | |
1567 | { | |
1568 | return platform_driver_register(&da8xx_fb_driver); | |
1569 | } | |
1570 | ||
1571 | static void __exit da8xx_fb_cleanup(void) | |
1572 | { | |
1573 | platform_driver_unregister(&da8xx_fb_driver); | |
1574 | } | |
1575 | ||
1576 | module_init(da8xx_fb_init); | |
1577 | module_exit(da8xx_fb_cleanup); | |
1578 | ||
1579 | MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx"); | |
1580 | MODULE_AUTHOR("Texas Instruments"); | |
1581 | MODULE_LICENSE("GPL"); |