]>
Commit | Line | Data |
---|---|---|
4ed824d9 SR |
1 | /* |
2 | * Copyright (C) 2008-2009 MontaVista Software Inc. | |
3 | * Copyright (C) 2008-2009 Texas Instruments Inc | |
4 | * | |
5 | * Based on the LCD driver for TI Avalanche processors written by | |
6 | * Ajay Singh and Shalom Hai. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option)any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #include <linux/module.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/fb.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/uaccess.h> | |
4ed824d9 | 29 | #include <linux/interrupt.h> |
a481b37a | 30 | #include <linux/wait.h> |
4ed824d9 | 31 | #include <linux/clk.h> |
e04e5483 | 32 | #include <linux/cpufreq.h> |
1d3c6c7b | 33 | #include <linux/console.h> |
deb95c6c | 34 | #include <linux/spinlock.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
a0239073 | 36 | #include <linux/delay.h> |
3b9cc4ea | 37 | #include <linux/lcm.h> |
4ed824d9 | 38 | #include <video/da8xx-fb.h> |
12fa8350 | 39 | #include <asm/div64.h> |
4ed824d9 SR |
40 | |
41 | #define DRIVER_NAME "da8xx_lcdc" | |
42 | ||
c6daf05b MP |
43 | #define LCD_VERSION_1 1 |
44 | #define LCD_VERSION_2 2 | |
45 | ||
4ed824d9 | 46 | /* LCD Status Register */ |
1f9c3e1f | 47 | #define LCD_END_OF_FRAME1 BIT(9) |
4ed824d9 | 48 | #define LCD_END_OF_FRAME0 BIT(8) |
1f9c3e1f | 49 | #define LCD_PL_LOAD_DONE BIT(6) |
4ed824d9 SR |
50 | #define LCD_FIFO_UNDERFLOW BIT(5) |
51 | #define LCD_SYNC_LOST BIT(2) | |
a481b37a | 52 | #define LCD_FRAME_DONE BIT(0) |
4ed824d9 SR |
53 | |
54 | /* LCD DMA Control Register */ | |
55 | #define LCD_DMA_BURST_SIZE(x) ((x) << 4) | |
56 | #define LCD_DMA_BURST_1 0x0 | |
57 | #define LCD_DMA_BURST_2 0x1 | |
58 | #define LCD_DMA_BURST_4 0x2 | |
59 | #define LCD_DMA_BURST_8 0x3 | |
60 | #define LCD_DMA_BURST_16 0x4 | |
c6daf05b MP |
61 | #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) |
62 | #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) | |
63 | #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) | |
4ed824d9 SR |
64 | #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) |
65 | ||
66 | /* LCD Control Register */ | |
67 | #define LCD_CLK_DIVISOR(x) ((x) << 8) | |
68 | #define LCD_RASTER_MODE 0x01 | |
69 | ||
70 | /* LCD Raster Control Register */ | |
71 | #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) | |
72 | #define PALETTE_AND_DATA 0x00 | |
73 | #define PALETTE_ONLY 0x01 | |
1f9c3e1f | 74 | #define DATA_ONLY 0x02 |
4ed824d9 SR |
75 | |
76 | #define LCD_MONO_8BIT_MODE BIT(9) | |
77 | #define LCD_RASTER_ORDER BIT(8) | |
78 | #define LCD_TFT_MODE BIT(7) | |
c6daf05b MP |
79 | #define LCD_V1_UNDERFLOW_INT_ENA BIT(6) |
80 | #define LCD_V2_UNDERFLOW_INT_ENA BIT(5) | |
81 | #define LCD_V1_PL_INT_ENA BIT(4) | |
82 | #define LCD_V2_PL_INT_ENA BIT(6) | |
4ed824d9 SR |
83 | #define LCD_MONOCHROME_MODE BIT(1) |
84 | #define LCD_RASTER_ENABLE BIT(0) | |
85 | #define LCD_TFT_ALT_ENABLE BIT(23) | |
86 | #define LCD_STN_565_ENABLE BIT(24) | |
c6daf05b MP |
87 | #define LCD_V2_DMA_CLK_EN BIT(2) |
88 | #define LCD_V2_LIDD_CLK_EN BIT(1) | |
89 | #define LCD_V2_CORE_CLK_EN BIT(0) | |
90 | #define LCD_V2_LPP_B10 26 | |
1a2b750c MP |
91 | #define LCD_V2_TFT_24BPP_MODE BIT(25) |
92 | #define LCD_V2_TFT_24BPP_UNPACK BIT(26) | |
4ed824d9 SR |
93 | |
94 | /* LCD Raster Timing 2 Register */ | |
95 | #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) | |
96 | #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) | |
97 | #define LCD_SYNC_CTRL BIT(25) | |
98 | #define LCD_SYNC_EDGE BIT(24) | |
99 | #define LCD_INVERT_PIXEL_CLOCK BIT(22) | |
100 | #define LCD_INVERT_LINE_CLOCK BIT(21) | |
101 | #define LCD_INVERT_FRAME_CLOCK BIT(20) | |
102 | ||
103 | /* LCD Block */ | |
c6daf05b | 104 | #define LCD_PID_REG 0x0 |
4ed824d9 SR |
105 | #define LCD_CTRL_REG 0x4 |
106 | #define LCD_STAT_REG 0x8 | |
107 | #define LCD_RASTER_CTRL_REG 0x28 | |
108 | #define LCD_RASTER_TIMING_0_REG 0x2C | |
109 | #define LCD_RASTER_TIMING_1_REG 0x30 | |
110 | #define LCD_RASTER_TIMING_2_REG 0x34 | |
111 | #define LCD_DMA_CTRL_REG 0x40 | |
112 | #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44 | |
113 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48 | |
1f9c3e1f MA |
114 | #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C |
115 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50 | |
116 | ||
c6daf05b MP |
117 | /* Interrupt Registers available only in Version 2 */ |
118 | #define LCD_RAW_STAT_REG 0x58 | |
119 | #define LCD_MASKED_STAT_REG 0x5c | |
120 | #define LCD_INT_ENABLE_SET_REG 0x60 | |
121 | #define LCD_INT_ENABLE_CLR_REG 0x64 | |
122 | #define LCD_END_OF_INT_IND_REG 0x68 | |
123 | ||
124 | /* Clock registers available only on Version 2 */ | |
125 | #define LCD_CLK_ENABLE_REG 0x6c | |
126 | #define LCD_CLK_RESET_REG 0x70 | |
74a0efde | 127 | #define LCD_CLK_MAIN_RESET BIT(3) |
c6daf05b | 128 | |
1f9c3e1f | 129 | #define LCD_NUM_BUFFERS 2 |
4ed824d9 SR |
130 | |
131 | #define WSI_TIMEOUT 50 | |
132 | #define PALETTE_SIZE 256 | |
133 | #define LEFT_MARGIN 64 | |
134 | #define RIGHT_MARGIN 64 | |
135 | #define UPPER_MARGIN 32 | |
136 | #define LOWER_MARGIN 32 | |
137 | ||
138 | static resource_size_t da8xx_fb_reg_base; | |
139 | static struct resource *lcdc_regs; | |
c6daf05b MP |
140 | static unsigned int lcd_revision; |
141 | static irq_handler_t lcdc_irq_handler; | |
a481b37a MP |
142 | static wait_queue_head_t frame_done_wq; |
143 | static int frame_done_flag; | |
4ed824d9 SR |
144 | |
145 | static inline unsigned int lcdc_read(unsigned int addr) | |
146 | { | |
147 | return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr)); | |
148 | } | |
149 | ||
150 | static inline void lcdc_write(unsigned int val, unsigned int addr) | |
151 | { | |
152 | __raw_writel(val, da8xx_fb_reg_base + (addr)); | |
153 | } | |
154 | ||
155 | struct da8xx_fb_par { | |
4ed824d9 SR |
156 | resource_size_t p_palette_base; |
157 | unsigned char *v_palette_base; | |
1f9c3e1f MA |
158 | dma_addr_t vram_phys; |
159 | unsigned long vram_size; | |
160 | void *vram_virt; | |
161 | unsigned int dma_start; | |
162 | unsigned int dma_end; | |
4ed824d9 SR |
163 | struct clk *lcdc_clk; |
164 | int irq; | |
4ed824d9 | 165 | unsigned int palette_sz; |
8097b174 | 166 | unsigned int pxl_clk; |
36113804 | 167 | int blank; |
1f9c3e1f MA |
168 | wait_queue_head_t vsync_wait; |
169 | int vsync_flag; | |
170 | int vsync_timeout; | |
deb95c6c MP |
171 | spinlock_t lock_for_chan_update; |
172 | ||
173 | /* | |
174 | * LCDC has 2 ping pong DMA channels, channel 0 | |
175 | * and channel 1. | |
176 | */ | |
177 | unsigned int which_dma_channel_done; | |
e04e5483 C |
178 | #ifdef CONFIG_CPU_FREQ |
179 | struct notifier_block freq_transition; | |
f820917a | 180 | unsigned int lcd_fck_rate; |
e04e5483 | 181 | #endif |
36113804 | 182 | void (*panel_power_ctrl)(int); |
1a2b750c | 183 | u32 pseudo_palette[16]; |
4ed824d9 SR |
184 | }; |
185 | ||
186 | /* Variable Screen Information */ | |
187 | static struct fb_var_screeninfo da8xx_fb_var __devinitdata = { | |
188 | .xoffset = 0, | |
189 | .yoffset = 0, | |
190 | .transp = {0, 0, 0}, | |
191 | .nonstd = 0, | |
192 | .activate = 0, | |
193 | .height = -1, | |
194 | .width = -1, | |
4ed824d9 SR |
195 | .accel_flags = 0, |
196 | .left_margin = LEFT_MARGIN, | |
197 | .right_margin = RIGHT_MARGIN, | |
198 | .upper_margin = UPPER_MARGIN, | |
199 | .lower_margin = LOWER_MARGIN, | |
200 | .sync = 0, | |
201 | .vmode = FB_VMODE_NONINTERLACED | |
202 | }; | |
203 | ||
204 | static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = { | |
205 | .id = "DA8xx FB Drv", | |
206 | .type = FB_TYPE_PACKED_PIXELS, | |
207 | .type_aux = 0, | |
208 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
1f9c3e1f | 209 | .xpanstep = 0, |
4ed824d9 | 210 | .ypanstep = 1, |
1f9c3e1f | 211 | .ywrapstep = 0, |
4ed824d9 SR |
212 | .accel = FB_ACCEL_NONE |
213 | }; | |
214 | ||
215 | struct da8xx_panel { | |
216 | const char name[25]; /* Full name <vendor>_<model> */ | |
217 | unsigned short width; | |
218 | unsigned short height; | |
219 | int hfp; /* Horizontal front porch */ | |
220 | int hbp; /* Horizontal back porch */ | |
221 | int hsw; /* Horizontal Sync Pulse Width */ | |
222 | int vfp; /* Vertical front porch */ | |
223 | int vbp; /* Vertical back porch */ | |
224 | int vsw; /* Vertical Sync Pulse Width */ | |
8097b174 | 225 | unsigned int pxl_clk; /* Pixel clock */ |
2f93e8f4 | 226 | unsigned char invert_pxl_clk; /* Invert Pixel clock */ |
4ed824d9 SR |
227 | }; |
228 | ||
229 | static struct da8xx_panel known_lcd_panels[] = { | |
230 | /* Sharp LCD035Q3DG01 */ | |
231 | [0] = { | |
232 | .name = "Sharp_LCD035Q3DG01", | |
233 | .width = 320, | |
234 | .height = 240, | |
235 | .hfp = 8, | |
236 | .hbp = 6, | |
237 | .hsw = 0, | |
238 | .vfp = 2, | |
239 | .vbp = 2, | |
240 | .vsw = 0, | |
8097b174 | 241 | .pxl_clk = 4608000, |
2f93e8f4 | 242 | .invert_pxl_clk = 1, |
4ed824d9 SR |
243 | }, |
244 | /* Sharp LK043T1DG01 */ | |
245 | [1] = { | |
246 | .name = "Sharp_LK043T1DG01", | |
247 | .width = 480, | |
248 | .height = 272, | |
249 | .hfp = 2, | |
250 | .hbp = 2, | |
251 | .hsw = 41, | |
252 | .vfp = 2, | |
253 | .vbp = 2, | |
254 | .vsw = 10, | |
8097b174 | 255 | .pxl_clk = 7833600, |
2f93e8f4 | 256 | .invert_pxl_clk = 0, |
4ed824d9 | 257 | }, |
f413070e AG |
258 | [2] = { |
259 | /* Hitachi SP10Q010 */ | |
260 | .name = "SP10Q010", | |
261 | .width = 320, | |
262 | .height = 240, | |
263 | .hfp = 10, | |
264 | .hbp = 10, | |
265 | .hsw = 10, | |
266 | .vfp = 10, | |
267 | .vbp = 10, | |
268 | .vsw = 10, | |
269 | .pxl_clk = 7833600, | |
270 | .invert_pxl_clk = 0, | |
271 | }, | |
4ed824d9 SR |
272 | }; |
273 | ||
36113804 C |
274 | /* Enable the Raster Engine of the LCD Controller */ |
275 | static inline void lcd_enable_raster(void) | |
276 | { | |
277 | u32 reg; | |
278 | ||
92b4e450 MP |
279 | /* Put LCDC in reset for several cycles */ |
280 | if (lcd_revision == LCD_VERSION_2) | |
281 | /* Write 1 to reset LCDC */ | |
282 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
283 | mdelay(1); | |
284 | ||
74a0efde MP |
285 | /* Bring LCDC out of reset */ |
286 | if (lcd_revision == LCD_VERSION_2) | |
287 | lcdc_write(0, LCD_CLK_RESET_REG); | |
92b4e450 | 288 | mdelay(1); |
74a0efde | 289 | |
92b4e450 | 290 | /* Above reset sequence doesnot reset register context */ |
36113804 C |
291 | reg = lcdc_read(LCD_RASTER_CTRL_REG); |
292 | if (!(reg & LCD_RASTER_ENABLE)) | |
293 | lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); | |
294 | } | |
295 | ||
4ed824d9 | 296 | /* Disable the Raster Engine of the LCD Controller */ |
a481b37a | 297 | static inline void lcd_disable_raster(bool wait_for_frame_done) |
4ed824d9 | 298 | { |
4ed824d9 | 299 | u32 reg; |
a481b37a | 300 | int ret; |
4ed824d9 SR |
301 | |
302 | reg = lcdc_read(LCD_RASTER_CTRL_REG); | |
2f93e8f4 | 303 | if (reg & LCD_RASTER_ENABLE) |
4ed824d9 | 304 | lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); |
a481b37a MP |
305 | else |
306 | /* return if already disabled */ | |
307 | return; | |
308 | ||
309 | if ((wait_for_frame_done == true) && (lcd_revision == LCD_VERSION_2)) { | |
310 | frame_done_flag = 0; | |
311 | ret = wait_event_interruptible_timeout(frame_done_wq, | |
312 | frame_done_flag != 0, | |
313 | msecs_to_jiffies(50)); | |
314 | if (ret == 0) | |
315 | pr_err("LCD Controller timed out\n"); | |
316 | } | |
4ed824d9 SR |
317 | } |
318 | ||
319 | static void lcd_blit(int load_mode, struct da8xx_fb_par *par) | |
320 | { | |
1f9c3e1f MA |
321 | u32 start; |
322 | u32 end; | |
323 | u32 reg_ras; | |
324 | u32 reg_dma; | |
c6daf05b | 325 | u32 reg_int; |
1f9c3e1f MA |
326 | |
327 | /* init reg to clear PLM (loading mode) fields */ | |
328 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
329 | reg_ras &= ~(3 << 20); | |
330 | ||
331 | reg_dma = lcdc_read(LCD_DMA_CTRL_REG); | |
332 | ||
333 | if (load_mode == LOAD_DATA) { | |
334 | start = par->dma_start; | |
335 | end = par->dma_end; | |
336 | ||
337 | reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); | |
c6daf05b MP |
338 | if (lcd_revision == LCD_VERSION_1) { |
339 | reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; | |
340 | } else { | |
341 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
342 | LCD_V2_END_OF_FRAME0_INT_ENA | | |
a481b37a MP |
343 | LCD_V2_END_OF_FRAME1_INT_ENA | |
344 | LCD_FRAME_DONE; | |
c6daf05b MP |
345 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); |
346 | } | |
1f9c3e1f MA |
347 | reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; |
348 | ||
349 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
350 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
351 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
352 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
353 | } else if (load_mode == LOAD_PALETTE) { | |
354 | start = par->p_palette_base; | |
355 | end = start + par->palette_sz - 1; | |
356 | ||
357 | reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); | |
c6daf05b MP |
358 | |
359 | if (lcd_revision == LCD_VERSION_1) { | |
360 | reg_ras |= LCD_V1_PL_INT_ENA; | |
361 | } else { | |
362 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
363 | LCD_V2_PL_INT_ENA; | |
364 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
365 | } | |
1f9c3e1f MA |
366 | |
367 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
368 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
369 | } | |
4ed824d9 | 370 | |
1f9c3e1f MA |
371 | lcdc_write(reg_dma, LCD_DMA_CTRL_REG); |
372 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); | |
4ed824d9 | 373 | |
1f9c3e1f MA |
374 | /* |
375 | * The Raster enable bit must be set after all other control fields are | |
376 | * set. | |
377 | */ | |
378 | lcd_enable_raster(); | |
4ed824d9 SR |
379 | } |
380 | ||
fb8fa943 MP |
381 | /* Configure the Burst Size and fifo threhold of DMA */ |
382 | static int lcd_cfg_dma(int burst_size, int fifo_th) | |
4ed824d9 SR |
383 | { |
384 | u32 reg; | |
385 | ||
386 | reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001; | |
387 | switch (burst_size) { | |
388 | case 1: | |
389 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); | |
390 | break; | |
391 | case 2: | |
392 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); | |
393 | break; | |
394 | case 4: | |
395 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); | |
396 | break; | |
397 | case 8: | |
398 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); | |
399 | break; | |
400 | case 16: | |
401 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); | |
402 | break; | |
403 | default: | |
404 | return -EINVAL; | |
405 | } | |
fb8fa943 MP |
406 | |
407 | reg |= (fifo_th << 8); | |
408 | ||
2f93e8f4 | 409 | lcdc_write(reg, LCD_DMA_CTRL_REG); |
4ed824d9 SR |
410 | |
411 | return 0; | |
412 | } | |
413 | ||
414 | static void lcd_cfg_ac_bias(int period, int transitions_per_int) | |
415 | { | |
416 | u32 reg; | |
417 | ||
418 | /* Set the AC Bias Period and Number of Transisitons per Interrupt */ | |
419 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000; | |
420 | reg |= LCD_AC_BIAS_FREQUENCY(period) | | |
421 | LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); | |
422 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
423 | } | |
424 | ||
425 | static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, | |
426 | int front_porch) | |
427 | { | |
428 | u32 reg; | |
429 | ||
430 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf; | |
431 | reg |= ((back_porch & 0xff) << 24) | |
432 | | ((front_porch & 0xff) << 16) | |
433 | | ((pulse_width & 0x3f) << 10); | |
434 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); | |
435 | } | |
436 | ||
437 | static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, | |
438 | int front_porch) | |
439 | { | |
440 | u32 reg; | |
441 | ||
442 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff; | |
443 | reg |= ((back_porch & 0xff) << 24) | |
444 | | ((front_porch & 0xff) << 16) | |
445 | | ((pulse_width & 0x3f) << 10); | |
446 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
447 | } | |
448 | ||
449 | static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) | |
450 | { | |
451 | u32 reg; | |
c6daf05b | 452 | u32 reg_int; |
4ed824d9 SR |
453 | |
454 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE | | |
455 | LCD_MONO_8BIT_MODE | | |
456 | LCD_MONOCHROME_MODE); | |
457 | ||
458 | switch (cfg->p_disp_panel->panel_shade) { | |
459 | case MONOCHROME: | |
460 | reg |= LCD_MONOCHROME_MODE; | |
461 | if (cfg->mono_8bit_mode) | |
462 | reg |= LCD_MONO_8BIT_MODE; | |
463 | break; | |
464 | case COLOR_ACTIVE: | |
465 | reg |= LCD_TFT_MODE; | |
466 | if (cfg->tft_alt_mode) | |
467 | reg |= LCD_TFT_ALT_ENABLE; | |
468 | break; | |
469 | ||
470 | case COLOR_PASSIVE: | |
471 | if (cfg->stn_565_mode) | |
472 | reg |= LCD_STN_565_ENABLE; | |
473 | break; | |
474 | ||
475 | default: | |
476 | return -EINVAL; | |
477 | } | |
478 | ||
479 | /* enable additional interrupts here */ | |
c6daf05b MP |
480 | if (lcd_revision == LCD_VERSION_1) { |
481 | reg |= LCD_V1_UNDERFLOW_INT_ENA; | |
482 | } else { | |
483 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
484 | LCD_V2_UNDERFLOW_INT_ENA; | |
485 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
486 | } | |
4ed824d9 SR |
487 | |
488 | lcdc_write(reg, LCD_RASTER_CTRL_REG); | |
489 | ||
490 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
491 | ||
492 | if (cfg->sync_ctrl) | |
493 | reg |= LCD_SYNC_CTRL; | |
494 | else | |
495 | reg &= ~LCD_SYNC_CTRL; | |
496 | ||
497 | if (cfg->sync_edge) | |
498 | reg |= LCD_SYNC_EDGE; | |
499 | else | |
500 | reg &= ~LCD_SYNC_EDGE; | |
501 | ||
4ed824d9 SR |
502 | if (cfg->invert_line_clock) |
503 | reg |= LCD_INVERT_LINE_CLOCK; | |
504 | else | |
505 | reg &= ~LCD_INVERT_LINE_CLOCK; | |
506 | ||
507 | if (cfg->invert_frm_clock) | |
508 | reg |= LCD_INVERT_FRAME_CLOCK; | |
509 | else | |
510 | reg &= ~LCD_INVERT_FRAME_CLOCK; | |
511 | ||
512 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
517 | static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, | |
518 | u32 bpp, u32 raster_order) | |
519 | { | |
1f9c3e1f | 520 | u32 reg; |
4ed824d9 | 521 | |
1a2b750c MP |
522 | if (bpp > 16 && lcd_revision == LCD_VERSION_1) |
523 | return -EINVAL; | |
524 | ||
4ed824d9 SR |
525 | /* Set the Panel Width */ |
526 | /* Pixels per line = (PPL + 1)*16 */ | |
4d740801 MP |
527 | if (lcd_revision == LCD_VERSION_1) { |
528 | /* | |
529 | * 0x3F in bits 4..9 gives max horizontal resolution = 1024 | |
530 | * pixels. | |
531 | */ | |
532 | width &= 0x3f0; | |
533 | } else { | |
534 | /* | |
535 | * 0x7F in bits 4..10 gives max horizontal resolution = 2048 | |
536 | * pixels. | |
537 | */ | |
538 | width &= 0x7f0; | |
539 | } | |
540 | ||
4ed824d9 SR |
541 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG); |
542 | reg &= 0xfffffc00; | |
4d740801 MP |
543 | if (lcd_revision == LCD_VERSION_1) { |
544 | reg |= ((width >> 4) - 1) << 4; | |
545 | } else { | |
546 | width = (width >> 4) - 1; | |
547 | reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); | |
548 | } | |
4ed824d9 SR |
549 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); |
550 | ||
551 | /* Set the Panel Height */ | |
4d740801 | 552 | /* Set bits 9:0 of Lines Per Pixel */ |
4ed824d9 SR |
553 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG); |
554 | reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); | |
555 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
556 | ||
4d740801 MP |
557 | /* Set bit 10 of Lines Per Pixel */ |
558 | if (lcd_revision == LCD_VERSION_2) { | |
559 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
560 | reg |= ((height - 1) & 0x400) << 16; | |
561 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
562 | } | |
563 | ||
4ed824d9 SR |
564 | /* Set the Raster Order of the Frame Buffer */ |
565 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8); | |
566 | if (raster_order) | |
567 | reg |= LCD_RASTER_ORDER; | |
1a2b750c MP |
568 | |
569 | par->palette_sz = 16 * 2; | |
4ed824d9 SR |
570 | |
571 | switch (bpp) { | |
572 | case 1: | |
573 | case 2: | |
574 | case 4: | |
575 | case 16: | |
1a2b750c MP |
576 | break; |
577 | case 24: | |
578 | reg |= LCD_V2_TFT_24BPP_MODE; | |
579 | case 32: | |
580 | reg |= LCD_V2_TFT_24BPP_UNPACK; | |
4ed824d9 SR |
581 | break; |
582 | ||
583 | case 8: | |
584 | par->palette_sz = 256 * 2; | |
585 | break; | |
586 | ||
587 | default: | |
588 | return -EINVAL; | |
589 | } | |
590 | ||
1a2b750c MP |
591 | lcdc_write(reg, LCD_RASTER_CTRL_REG); |
592 | ||
4ed824d9 SR |
593 | return 0; |
594 | } | |
595 | ||
1a2b750c | 596 | #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) |
4ed824d9 SR |
597 | static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, |
598 | unsigned blue, unsigned transp, | |
599 | struct fb_info *info) | |
600 | { | |
601 | struct da8xx_fb_par *par = info->par; | |
1f9c3e1f | 602 | unsigned short *palette = (unsigned short *) par->v_palette_base; |
4ed824d9 | 603 | u_short pal; |
1f9c3e1f | 604 | int update_hw = 0; |
4ed824d9 SR |
605 | |
606 | if (regno > 255) | |
607 | return 1; | |
608 | ||
609 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) | |
610 | return 1; | |
611 | ||
1a2b750c MP |
612 | if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
613 | return -EINVAL; | |
f413070e | 614 | |
1a2b750c MP |
615 | switch (info->fix.visual) { |
616 | case FB_VISUAL_TRUECOLOR: | |
617 | red = CNVT_TOHW(red, info->var.red.length); | |
618 | green = CNVT_TOHW(green, info->var.green.length); | |
619 | blue = CNVT_TOHW(blue, info->var.blue.length); | |
620 | break; | |
621 | case FB_VISUAL_PSEUDOCOLOR: | |
622 | switch (info->var.bits_per_pixel) { | |
623 | case 4: | |
624 | if (regno > 15) | |
625 | return -EINVAL; | |
626 | ||
627 | if (info->var.grayscale) { | |
628 | pal = regno; | |
629 | } else { | |
630 | red >>= 4; | |
631 | green >>= 8; | |
632 | blue >>= 12; | |
633 | ||
634 | pal = red & 0x0f00; | |
635 | pal |= green & 0x00f0; | |
636 | pal |= blue & 0x000f; | |
637 | } | |
638 | if (regno == 0) | |
639 | pal |= 0x2000; | |
640 | palette[regno] = pal; | |
641 | break; | |
642 | ||
643 | case 8: | |
f413070e AG |
644 | red >>= 4; |
645 | green >>= 8; | |
646 | blue >>= 12; | |
647 | ||
648 | pal = (red & 0x0f00); | |
649 | pal |= (green & 0x00f0); | |
650 | pal |= (blue & 0x000f); | |
4ed824d9 | 651 | |
1a2b750c MP |
652 | if (palette[regno] != pal) { |
653 | update_hw = 1; | |
654 | palette[regno] = pal; | |
655 | } | |
656 | break; | |
1f9c3e1f | 657 | } |
1a2b750c MP |
658 | break; |
659 | } | |
4ed824d9 | 660 | |
1a2b750c MP |
661 | /* Truecolor has hardware independent palette */ |
662 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { | |
663 | u32 v; | |
4ed824d9 | 664 | |
1a2b750c MP |
665 | if (regno > 15) |
666 | return -EINVAL; | |
667 | ||
668 | v = (red << info->var.red.offset) | | |
669 | (green << info->var.green.offset) | | |
670 | (blue << info->var.blue.offset); | |
671 | ||
672 | switch (info->var.bits_per_pixel) { | |
673 | case 16: | |
674 | ((u16 *) (info->pseudo_palette))[regno] = v; | |
675 | break; | |
676 | case 24: | |
677 | case 32: | |
678 | ((u32 *) (info->pseudo_palette))[regno] = v; | |
679 | break; | |
680 | } | |
1f9c3e1f MA |
681 | if (palette[0] != 0x4000) { |
682 | update_hw = 1; | |
683 | palette[0] = 0x4000; | |
684 | } | |
4ed824d9 SR |
685 | } |
686 | ||
1f9c3e1f MA |
687 | /* Update the palette in the h/w as needed. */ |
688 | if (update_hw) | |
689 | lcd_blit(LOAD_PALETTE, par); | |
690 | ||
4ed824d9 SR |
691 | return 0; |
692 | } | |
1a2b750c | 693 | #undef CNVT_TOHW |
4ed824d9 | 694 | |
2f93e8f4 | 695 | static void lcd_reset(struct da8xx_fb_par *par) |
4ed824d9 | 696 | { |
4ed824d9 | 697 | /* Disable the Raster if previously Enabled */ |
a481b37a | 698 | lcd_disable_raster(false); |
4ed824d9 SR |
699 | |
700 | /* DMA has to be disabled */ | |
701 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
702 | lcdc_write(0, LCD_RASTER_CTRL_REG); | |
c6daf05b | 703 | |
74a0efde | 704 | if (lcd_revision == LCD_VERSION_2) { |
c6daf05b | 705 | lcdc_write(0, LCD_INT_ENABLE_SET_REG); |
74a0efde MP |
706 | /* Write 1 to reset */ |
707 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
708 | lcdc_write(0, LCD_CLK_RESET_REG); | |
709 | } | |
4ed824d9 SR |
710 | } |
711 | ||
8097b174 C |
712 | static void lcd_calc_clk_divider(struct da8xx_fb_par *par) |
713 | { | |
714 | unsigned int lcd_clk, div; | |
715 | ||
716 | lcd_clk = clk_get_rate(par->lcdc_clk); | |
717 | div = lcd_clk / par->pxl_clk; | |
718 | ||
719 | /* Configure the LCD clock divisor. */ | |
720 | lcdc_write(LCD_CLK_DIVISOR(div) | | |
721 | (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG); | |
c6daf05b MP |
722 | |
723 | if (lcd_revision == LCD_VERSION_2) | |
724 | lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | | |
725 | LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG); | |
726 | ||
8097b174 C |
727 | } |
728 | ||
4ed824d9 SR |
729 | static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, |
730 | struct da8xx_panel *panel) | |
731 | { | |
732 | u32 bpp; | |
733 | int ret = 0; | |
734 | ||
2f93e8f4 | 735 | lcd_reset(par); |
4ed824d9 | 736 | |
8097b174 C |
737 | /* Calculate the divider */ |
738 | lcd_calc_clk_divider(par); | |
4ed824d9 | 739 | |
2f93e8f4 SR |
740 | if (panel->invert_pxl_clk) |
741 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) | | |
742 | LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
743 | else | |
744 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) & | |
745 | ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
746 | ||
fb8fa943 MP |
747 | /* Configure the DMA burst size and fifo threshold. */ |
748 | ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th); | |
4ed824d9 SR |
749 | if (ret < 0) |
750 | return ret; | |
751 | ||
752 | /* Configure the AC bias properties. */ | |
753 | lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); | |
754 | ||
755 | /* Configure the vertical and horizontal sync properties. */ | |
756 | lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp); | |
757 | lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp); | |
758 | ||
759 | /* Configure for disply */ | |
760 | ret = lcd_cfg_display(cfg); | |
761 | if (ret < 0) | |
762 | return ret; | |
763 | ||
764 | if (QVGA != cfg->p_disp_panel->panel_type) | |
765 | return -EINVAL; | |
766 | ||
767 | if (cfg->bpp <= cfg->p_disp_panel->max_bpp && | |
768 | cfg->bpp >= cfg->p_disp_panel->min_bpp) | |
769 | bpp = cfg->bpp; | |
770 | else | |
771 | bpp = cfg->p_disp_panel->max_bpp; | |
772 | if (bpp == 12) | |
773 | bpp = 16; | |
774 | ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width, | |
775 | (unsigned int)panel->height, bpp, | |
776 | cfg->raster_order); | |
777 | if (ret < 0) | |
778 | return ret; | |
779 | ||
780 | /* Configure FDD */ | |
781 | lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) | | |
782 | (cfg->fdd << 12), LCD_RASTER_CTRL_REG); | |
783 | ||
784 | return 0; | |
785 | } | |
786 | ||
c6daf05b MP |
787 | /* IRQ handler for version 2 of LCDC */ |
788 | static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) | |
789 | { | |
790 | struct da8xx_fb_par *par = arg; | |
791 | u32 stat = lcdc_read(LCD_MASKED_STAT_REG); | |
c6daf05b MP |
792 | |
793 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
a481b37a | 794 | lcd_disable_raster(false); |
c6daf05b MP |
795 | lcdc_write(stat, LCD_MASKED_STAT_REG); |
796 | lcd_enable_raster(); | |
797 | } else if (stat & LCD_PL_LOAD_DONE) { | |
798 | /* | |
799 | * Must disable raster before changing state of any control bit. | |
800 | * And also must be disabled before clearing the PL loading | |
801 | * interrupt via the following write to the status register. If | |
802 | * this is done after then one gets multiple PL done interrupts. | |
803 | */ | |
a481b37a | 804 | lcd_disable_raster(false); |
c6daf05b MP |
805 | |
806 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
807 | ||
8a81dccd MP |
808 | /* Disable PL completion interrupt */ |
809 | lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG); | |
c6daf05b MP |
810 | |
811 | /* Setup and start data loading mode */ | |
812 | lcd_blit(LOAD_DATA, par); | |
813 | } else { | |
814 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
815 | ||
816 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 817 | par->which_dma_channel_done = 0; |
c6daf05b MP |
818 | lcdc_write(par->dma_start, |
819 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
820 | lcdc_write(par->dma_end, | |
821 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
822 | par->vsync_flag = 1; | |
823 | wake_up_interruptible(&par->vsync_wait); | |
824 | } | |
825 | ||
826 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 827 | par->which_dma_channel_done = 1; |
c6daf05b MP |
828 | lcdc_write(par->dma_start, |
829 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
830 | lcdc_write(par->dma_end, | |
831 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
832 | par->vsync_flag = 1; | |
833 | wake_up_interruptible(&par->vsync_wait); | |
834 | } | |
a481b37a MP |
835 | |
836 | /* Set only when controller is disabled and at the end of | |
837 | * active frame | |
838 | */ | |
839 | if (stat & BIT(0)) { | |
840 | frame_done_flag = 1; | |
841 | wake_up_interruptible(&frame_done_wq); | |
842 | } | |
c6daf05b MP |
843 | } |
844 | ||
845 | lcdc_write(0, LCD_END_OF_INT_IND_REG); | |
846 | return IRQ_HANDLED; | |
847 | } | |
848 | ||
849 | /* IRQ handler for version 1 LCDC */ | |
850 | static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg) | |
4ed824d9 | 851 | { |
1f9c3e1f | 852 | struct da8xx_fb_par *par = arg; |
4ed824d9 | 853 | u32 stat = lcdc_read(LCD_STAT_REG); |
1f9c3e1f | 854 | u32 reg_ras; |
4ed824d9 SR |
855 | |
856 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
a481b37a | 857 | lcd_disable_raster(false); |
4ed824d9 | 858 | lcdc_write(stat, LCD_STAT_REG); |
36113804 | 859 | lcd_enable_raster(); |
1f9c3e1f MA |
860 | } else if (stat & LCD_PL_LOAD_DONE) { |
861 | /* | |
862 | * Must disable raster before changing state of any control bit. | |
863 | * And also must be disabled before clearing the PL loading | |
864 | * interrupt via the following write to the status register. If | |
865 | * this is done after then one gets multiple PL done interrupts. | |
866 | */ | |
a481b37a | 867 | lcd_disable_raster(false); |
1f9c3e1f | 868 | |
4ed824d9 SR |
869 | lcdc_write(stat, LCD_STAT_REG); |
870 | ||
1f9c3e1f MA |
871 | /* Disable PL completion inerrupt */ |
872 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
c6daf05b | 873 | reg_ras &= ~LCD_V1_PL_INT_ENA; |
1f9c3e1f MA |
874 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); |
875 | ||
876 | /* Setup and start data loading mode */ | |
877 | lcd_blit(LOAD_DATA, par); | |
878 | } else { | |
879 | lcdc_write(stat, LCD_STAT_REG); | |
880 | ||
881 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 882 | par->which_dma_channel_done = 0; |
1f9c3e1f MA |
883 | lcdc_write(par->dma_start, |
884 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
885 | lcdc_write(par->dma_end, | |
886 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
887 | par->vsync_flag = 1; | |
888 | wake_up_interruptible(&par->vsync_wait); | |
889 | } | |
890 | ||
891 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 892 | par->which_dma_channel_done = 1; |
1f9c3e1f MA |
893 | lcdc_write(par->dma_start, |
894 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
895 | lcdc_write(par->dma_end, | |
896 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
897 | par->vsync_flag = 1; | |
898 | wake_up_interruptible(&par->vsync_wait); | |
899 | } | |
900 | } | |
901 | ||
4ed824d9 SR |
902 | return IRQ_HANDLED; |
903 | } | |
904 | ||
905 | static int fb_check_var(struct fb_var_screeninfo *var, | |
906 | struct fb_info *info) | |
907 | { | |
908 | int err = 0; | |
909 | ||
1a2b750c MP |
910 | if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
911 | return -EINVAL; | |
912 | ||
4ed824d9 SR |
913 | switch (var->bits_per_pixel) { |
914 | case 1: | |
915 | case 8: | |
916 | var->red.offset = 0; | |
917 | var->red.length = 8; | |
918 | var->green.offset = 0; | |
919 | var->green.length = 8; | |
920 | var->blue.offset = 0; | |
921 | var->blue.length = 8; | |
922 | var->transp.offset = 0; | |
923 | var->transp.length = 0; | |
f413070e | 924 | var->nonstd = 0; |
4ed824d9 SR |
925 | break; |
926 | case 4: | |
927 | var->red.offset = 0; | |
928 | var->red.length = 4; | |
929 | var->green.offset = 0; | |
930 | var->green.length = 4; | |
931 | var->blue.offset = 0; | |
932 | var->blue.length = 4; | |
933 | var->transp.offset = 0; | |
934 | var->transp.length = 0; | |
f413070e | 935 | var->nonstd = FB_NONSTD_REV_PIX_IN_B; |
4ed824d9 SR |
936 | break; |
937 | case 16: /* RGB 565 */ | |
3510b8f7 | 938 | var->red.offset = 11; |
4ed824d9 SR |
939 | var->red.length = 5; |
940 | var->green.offset = 5; | |
941 | var->green.length = 6; | |
3510b8f7 | 942 | var->blue.offset = 0; |
4ed824d9 SR |
943 | var->blue.length = 5; |
944 | var->transp.offset = 0; | |
945 | var->transp.length = 0; | |
f413070e | 946 | var->nonstd = 0; |
4ed824d9 | 947 | break; |
1a2b750c MP |
948 | case 24: |
949 | var->red.offset = 16; | |
950 | var->red.length = 8; | |
951 | var->green.offset = 8; | |
952 | var->green.length = 8; | |
953 | var->blue.offset = 0; | |
954 | var->blue.length = 8; | |
955 | var->nonstd = 0; | |
956 | break; | |
957 | case 32: | |
958 | var->transp.offset = 24; | |
959 | var->transp.length = 8; | |
960 | var->red.offset = 16; | |
961 | var->red.length = 8; | |
962 | var->green.offset = 8; | |
963 | var->green.length = 8; | |
964 | var->blue.offset = 0; | |
965 | var->blue.length = 8; | |
966 | var->nonstd = 0; | |
967 | break; | |
4ed824d9 SR |
968 | default: |
969 | err = -EINVAL; | |
970 | } | |
971 | ||
972 | var->red.msb_right = 0; | |
973 | var->green.msb_right = 0; | |
974 | var->blue.msb_right = 0; | |
975 | var->transp.msb_right = 0; | |
976 | return err; | |
977 | } | |
978 | ||
e04e5483 C |
979 | #ifdef CONFIG_CPU_FREQ |
980 | static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb, | |
981 | unsigned long val, void *data) | |
982 | { | |
983 | struct da8xx_fb_par *par; | |
e04e5483 C |
984 | |
985 | par = container_of(nb, struct da8xx_fb_par, freq_transition); | |
f820917a MP |
986 | if (val == CPUFREQ_POSTCHANGE) { |
987 | if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) { | |
988 | par->lcd_fck_rate = clk_get_rate(par->lcdc_clk); | |
a481b37a | 989 | lcd_disable_raster(true); |
f820917a | 990 | lcd_calc_clk_divider(par); |
67900814 MP |
991 | if (par->blank == FB_BLANK_UNBLANK) |
992 | lcd_enable_raster(); | |
f820917a | 993 | } |
e04e5483 C |
994 | } |
995 | ||
996 | return 0; | |
997 | } | |
998 | ||
999 | static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par) | |
1000 | { | |
1001 | par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition; | |
1002 | ||
1003 | return cpufreq_register_notifier(&par->freq_transition, | |
1004 | CPUFREQ_TRANSITION_NOTIFIER); | |
1005 | } | |
1006 | ||
1007 | static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par) | |
1008 | { | |
1009 | cpufreq_unregister_notifier(&par->freq_transition, | |
1010 | CPUFREQ_TRANSITION_NOTIFIER); | |
1011 | } | |
1012 | #endif | |
1013 | ||
4ed824d9 SR |
1014 | static int __devexit fb_remove(struct platform_device *dev) |
1015 | { | |
1016 | struct fb_info *info = dev_get_drvdata(&dev->dev); | |
4ed824d9 SR |
1017 | |
1018 | if (info) { | |
1019 | struct da8xx_fb_par *par = info->par; | |
1020 | ||
e04e5483 C |
1021 | #ifdef CONFIG_CPU_FREQ |
1022 | lcd_da8xx_cpufreq_deregister(par); | |
1023 | #endif | |
36113804 C |
1024 | if (par->panel_power_ctrl) |
1025 | par->panel_power_ctrl(0); | |
1026 | ||
a481b37a | 1027 | lcd_disable_raster(true); |
4ed824d9 SR |
1028 | lcdc_write(0, LCD_RASTER_CTRL_REG); |
1029 | ||
1030 | /* disable DMA */ | |
1031 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
1032 | ||
1033 | unregister_framebuffer(info); | |
1034 | fb_dealloc_cmap(&info->cmap); | |
1f9c3e1f MA |
1035 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, |
1036 | par->p_palette_base); | |
1037 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, | |
1038 | par->vram_phys); | |
4ed824d9 SR |
1039 | free_irq(par->irq, par); |
1040 | clk_disable(par->lcdc_clk); | |
1041 | clk_put(par->lcdc_clk); | |
1042 | framebuffer_release(info); | |
1043 | iounmap((void __iomem *)da8xx_fb_reg_base); | |
1044 | release_mem_region(lcdc_regs->start, resource_size(lcdc_regs)); | |
1045 | ||
1046 | } | |
2f93e8f4 | 1047 | return 0; |
4ed824d9 SR |
1048 | } |
1049 | ||
1f9c3e1f MA |
1050 | /* |
1051 | * Function to wait for vertical sync which for this LCD peripheral | |
1052 | * translates into waiting for the current raster frame to complete. | |
1053 | */ | |
1054 | static int fb_wait_for_vsync(struct fb_info *info) | |
1055 | { | |
1056 | struct da8xx_fb_par *par = info->par; | |
1057 | int ret; | |
1058 | ||
1059 | /* | |
1060 | * Set flag to 0 and wait for isr to set to 1. It would seem there is a | |
25985edc | 1061 | * race condition here where the ISR could have occurred just before or |
1f9c3e1f MA |
1062 | * just after this set. But since we are just coarsely waiting for |
1063 | * a frame to complete then that's OK. i.e. if the frame completed | |
1064 | * just before this code executed then we have to wait another full | |
1065 | * frame time but there is no way to avoid such a situation. On the | |
1066 | * other hand if the frame completed just after then we don't need | |
1067 | * to wait long at all. Either way we are guaranteed to return to the | |
1068 | * user immediately after a frame completion which is all that is | |
1069 | * required. | |
1070 | */ | |
1071 | par->vsync_flag = 0; | |
1072 | ret = wait_event_interruptible_timeout(par->vsync_wait, | |
1073 | par->vsync_flag != 0, | |
1074 | par->vsync_timeout); | |
1075 | if (ret < 0) | |
1076 | return ret; | |
1077 | if (ret == 0) | |
1078 | return -ETIMEDOUT; | |
1079 | ||
1080 | return 0; | |
1081 | } | |
1082 | ||
4ed824d9 SR |
1083 | static int fb_ioctl(struct fb_info *info, unsigned int cmd, |
1084 | unsigned long arg) | |
1085 | { | |
1086 | struct lcd_sync_arg sync_arg; | |
1087 | ||
1088 | switch (cmd) { | |
1089 | case FBIOGET_CONTRAST: | |
1090 | case FBIOPUT_CONTRAST: | |
1091 | case FBIGET_BRIGHTNESS: | |
1092 | case FBIPUT_BRIGHTNESS: | |
1093 | case FBIGET_COLOR: | |
1094 | case FBIPUT_COLOR: | |
2f93e8f4 | 1095 | return -ENOTTY; |
4ed824d9 SR |
1096 | case FBIPUT_HSYNC: |
1097 | if (copy_from_user(&sync_arg, (char *)arg, | |
1098 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1099 | return -EFAULT; |
4ed824d9 SR |
1100 | lcd_cfg_horizontal_sync(sync_arg.back_porch, |
1101 | sync_arg.pulse_width, | |
1102 | sync_arg.front_porch); | |
1103 | break; | |
1104 | case FBIPUT_VSYNC: | |
1105 | if (copy_from_user(&sync_arg, (char *)arg, | |
1106 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1107 | return -EFAULT; |
4ed824d9 SR |
1108 | lcd_cfg_vertical_sync(sync_arg.back_porch, |
1109 | sync_arg.pulse_width, | |
1110 | sync_arg.front_porch); | |
1111 | break; | |
1f9c3e1f MA |
1112 | case FBIO_WAITFORVSYNC: |
1113 | return fb_wait_for_vsync(info); | |
4ed824d9 SR |
1114 | default: |
1115 | return -EINVAL; | |
1116 | } | |
1117 | return 0; | |
1118 | } | |
1119 | ||
312d9715 C |
1120 | static int cfb_blank(int blank, struct fb_info *info) |
1121 | { | |
1122 | struct da8xx_fb_par *par = info->par; | |
1123 | int ret = 0; | |
1124 | ||
1125 | if (par->blank == blank) | |
1126 | return 0; | |
1127 | ||
1128 | par->blank = blank; | |
1129 | switch (blank) { | |
1130 | case FB_BLANK_UNBLANK: | |
f7c848b6 MP |
1131 | lcd_enable_raster(); |
1132 | ||
312d9715 C |
1133 | if (par->panel_power_ctrl) |
1134 | par->panel_power_ctrl(1); | |
312d9715 | 1135 | break; |
99a647d1 YY |
1136 | case FB_BLANK_NORMAL: |
1137 | case FB_BLANK_VSYNC_SUSPEND: | |
1138 | case FB_BLANK_HSYNC_SUSPEND: | |
312d9715 C |
1139 | case FB_BLANK_POWERDOWN: |
1140 | if (par->panel_power_ctrl) | |
1141 | par->panel_power_ctrl(0); | |
1142 | ||
a481b37a | 1143 | lcd_disable_raster(true); |
312d9715 C |
1144 | break; |
1145 | default: | |
1146 | ret = -EINVAL; | |
1147 | } | |
1148 | ||
1149 | return ret; | |
1150 | } | |
1151 | ||
1f9c3e1f MA |
1152 | /* |
1153 | * Set new x,y offsets in the virtual display for the visible area and switch | |
1154 | * to the new mode. | |
1155 | */ | |
1156 | static int da8xx_pan_display(struct fb_var_screeninfo *var, | |
1157 | struct fb_info *fbi) | |
1158 | { | |
1159 | int ret = 0; | |
1160 | struct fb_var_screeninfo new_var; | |
1161 | struct da8xx_fb_par *par = fbi->par; | |
1162 | struct fb_fix_screeninfo *fix = &fbi->fix; | |
1163 | unsigned int end; | |
1164 | unsigned int start; | |
deb95c6c | 1165 | unsigned long irq_flags; |
1f9c3e1f MA |
1166 | |
1167 | if (var->xoffset != fbi->var.xoffset || | |
1168 | var->yoffset != fbi->var.yoffset) { | |
1169 | memcpy(&new_var, &fbi->var, sizeof(new_var)); | |
1170 | new_var.xoffset = var->xoffset; | |
1171 | new_var.yoffset = var->yoffset; | |
1172 | if (fb_check_var(&new_var, fbi)) | |
1173 | ret = -EINVAL; | |
1174 | else { | |
1175 | memcpy(&fbi->var, &new_var, sizeof(new_var)); | |
1176 | ||
1177 | start = fix->smem_start + | |
1178 | new_var.yoffset * fix->line_length + | |
e6c4d3d4 LP |
1179 | new_var.xoffset * fbi->var.bits_per_pixel / 8; |
1180 | end = start + fbi->var.yres * fix->line_length - 1; | |
1f9c3e1f MA |
1181 | par->dma_start = start; |
1182 | par->dma_end = end; | |
deb95c6c MP |
1183 | spin_lock_irqsave(&par->lock_for_chan_update, |
1184 | irq_flags); | |
1185 | if (par->which_dma_channel_done == 0) { | |
1186 | lcdc_write(par->dma_start, | |
1187 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1188 | lcdc_write(par->dma_end, | |
1189 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1190 | } else if (par->which_dma_channel_done == 1) { | |
1191 | lcdc_write(par->dma_start, | |
1192 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1193 | lcdc_write(par->dma_end, | |
1194 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1195 | } | |
1196 | spin_unlock_irqrestore(&par->lock_for_chan_update, | |
1197 | irq_flags); | |
1f9c3e1f MA |
1198 | } |
1199 | } | |
1200 | ||
1201 | return ret; | |
1202 | } | |
1203 | ||
4ed824d9 SR |
1204 | static struct fb_ops da8xx_fb_ops = { |
1205 | .owner = THIS_MODULE, | |
1206 | .fb_check_var = fb_check_var, | |
1207 | .fb_setcolreg = fb_setcolreg, | |
1f9c3e1f | 1208 | .fb_pan_display = da8xx_pan_display, |
4ed824d9 SR |
1209 | .fb_ioctl = fb_ioctl, |
1210 | .fb_fillrect = cfb_fillrect, | |
1211 | .fb_copyarea = cfb_copyarea, | |
1212 | .fb_imageblit = cfb_imageblit, | |
312d9715 | 1213 | .fb_blank = cfb_blank, |
4ed824d9 SR |
1214 | }; |
1215 | ||
12fa8350 MP |
1216 | /* Calculate and return pixel clock period in pico seconds */ |
1217 | static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par) | |
1218 | { | |
1219 | unsigned int lcd_clk, div; | |
1220 | unsigned int configured_pix_clk; | |
1221 | unsigned long long pix_clk_period_picosec = 1000000000000ULL; | |
1222 | ||
1223 | lcd_clk = clk_get_rate(par->lcdc_clk); | |
1224 | div = lcd_clk / par->pxl_clk; | |
1225 | configured_pix_clk = (lcd_clk / div); | |
1226 | ||
1227 | do_div(pix_clk_period_picosec, configured_pix_clk); | |
1228 | ||
1229 | return pix_clk_period_picosec; | |
1230 | } | |
1231 | ||
1db41e03 | 1232 | static int __devinit fb_probe(struct platform_device *device) |
4ed824d9 SR |
1233 | { |
1234 | struct da8xx_lcdc_platform_data *fb_pdata = | |
1235 | device->dev.platform_data; | |
1236 | struct lcd_ctrl_config *lcd_cfg; | |
1237 | struct da8xx_panel *lcdc_info; | |
1238 | struct fb_info *da8xx_fb_info; | |
1239 | struct clk *fb_clk = NULL; | |
1240 | struct da8xx_fb_par *par; | |
1241 | resource_size_t len; | |
1242 | int ret, i; | |
3b9cc4ea | 1243 | unsigned long ulcm; |
4ed824d9 SR |
1244 | |
1245 | if (fb_pdata == NULL) { | |
1246 | dev_err(&device->dev, "Can not get platform data\n"); | |
1247 | return -ENOENT; | |
1248 | } | |
1249 | ||
1250 | lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0); | |
1251 | if (!lcdc_regs) { | |
1252 | dev_err(&device->dev, | |
1253 | "Can not get memory resource for LCD controller\n"); | |
1254 | return -ENOENT; | |
1255 | } | |
1256 | ||
1257 | len = resource_size(lcdc_regs); | |
1258 | ||
1259 | lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name); | |
1260 | if (!lcdc_regs) | |
1261 | return -EBUSY; | |
1262 | ||
1263 | da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len); | |
1264 | if (!da8xx_fb_reg_base) { | |
1265 | ret = -EBUSY; | |
1266 | goto err_request_mem; | |
1267 | } | |
1268 | ||
1269 | fb_clk = clk_get(&device->dev, NULL); | |
1270 | if (IS_ERR(fb_clk)) { | |
1271 | dev_err(&device->dev, "Can not get device clock\n"); | |
1272 | ret = -ENODEV; | |
1273 | goto err_ioremap; | |
1274 | } | |
1275 | ret = clk_enable(fb_clk); | |
1276 | if (ret) | |
1277 | goto err_clk_put; | |
1278 | ||
c6daf05b MP |
1279 | /* Determine LCD IP Version */ |
1280 | switch (lcdc_read(LCD_PID_REG)) { | |
1281 | case 0x4C100102: | |
1282 | lcd_revision = LCD_VERSION_1; | |
1283 | break; | |
1284 | case 0x4F200800: | |
1285 | lcd_revision = LCD_VERSION_2; | |
1286 | break; | |
1287 | default: | |
1288 | dev_warn(&device->dev, "Unknown PID Reg value 0x%x, " | |
1289 | "defaulting to LCD revision 1\n", | |
1290 | lcdc_read(LCD_PID_REG)); | |
1291 | lcd_revision = LCD_VERSION_1; | |
1292 | break; | |
1293 | } | |
1294 | ||
4ed824d9 SR |
1295 | for (i = 0, lcdc_info = known_lcd_panels; |
1296 | i < ARRAY_SIZE(known_lcd_panels); | |
1297 | i++, lcdc_info++) { | |
1298 | if (strcmp(fb_pdata->type, lcdc_info->name) == 0) | |
1299 | break; | |
1300 | } | |
1301 | ||
1302 | if (i == ARRAY_SIZE(known_lcd_panels)) { | |
1303 | dev_err(&device->dev, "GLCD: No valid panel found\n"); | |
dd04a6b3 | 1304 | ret = -ENODEV; |
4ed824d9 SR |
1305 | goto err_clk_disable; |
1306 | } else | |
1307 | dev_info(&device->dev, "GLCD: Found %s panel\n", | |
1308 | fb_pdata->type); | |
1309 | ||
1310 | lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data; | |
1311 | ||
1312 | da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par), | |
1313 | &device->dev); | |
1314 | if (!da8xx_fb_info) { | |
1315 | dev_dbg(&device->dev, "Memory allocation failed for fb_info\n"); | |
1316 | ret = -ENOMEM; | |
1317 | goto err_clk_disable; | |
1318 | } | |
1319 | ||
1320 | par = da8xx_fb_info->par; | |
8097b174 | 1321 | par->lcdc_clk = fb_clk; |
f820917a MP |
1322 | #ifdef CONFIG_CPU_FREQ |
1323 | par->lcd_fck_rate = clk_get_rate(fb_clk); | |
1324 | #endif | |
8097b174 | 1325 | par->pxl_clk = lcdc_info->pxl_clk; |
36113804 C |
1326 | if (fb_pdata->panel_power_ctrl) { |
1327 | par->panel_power_ctrl = fb_pdata->panel_power_ctrl; | |
1328 | par->panel_power_ctrl(1); | |
1329 | } | |
4ed824d9 SR |
1330 | |
1331 | if (lcd_init(par, lcd_cfg, lcdc_info) < 0) { | |
1332 | dev_err(&device->dev, "lcd_init failed\n"); | |
1333 | ret = -EFAULT; | |
1334 | goto err_release_fb; | |
1335 | } | |
1336 | ||
1337 | /* allocate frame buffer */ | |
1f9c3e1f | 1338 | par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp; |
3b9cc4ea AN |
1339 | ulcm = lcm((lcdc_info->width * lcd_cfg->bpp)/8, PAGE_SIZE); |
1340 | par->vram_size = roundup(par->vram_size/8, ulcm); | |
1f9c3e1f MA |
1341 | par->vram_size = par->vram_size * LCD_NUM_BUFFERS; |
1342 | ||
1343 | par->vram_virt = dma_alloc_coherent(NULL, | |
1344 | par->vram_size, | |
1345 | (resource_size_t *) &par->vram_phys, | |
1346 | GFP_KERNEL | GFP_DMA); | |
1347 | if (!par->vram_virt) { | |
4ed824d9 SR |
1348 | dev_err(&device->dev, |
1349 | "GLCD: kmalloc for frame buffer failed\n"); | |
1350 | ret = -EINVAL; | |
1351 | goto err_release_fb; | |
1352 | } | |
1353 | ||
1f9c3e1f MA |
1354 | da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt; |
1355 | da8xx_fb_fix.smem_start = par->vram_phys; | |
1356 | da8xx_fb_fix.smem_len = par->vram_size; | |
1357 | da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8; | |
1358 | ||
1359 | par->dma_start = par->vram_phys; | |
1360 | par->dma_end = par->dma_start + lcdc_info->height * | |
1361 | da8xx_fb_fix.line_length - 1; | |
1362 | ||
1363 | /* allocate palette buffer */ | |
1364 | par->v_palette_base = dma_alloc_coherent(NULL, | |
1365 | PALETTE_SIZE, | |
1366 | (resource_size_t *) | |
1367 | &par->p_palette_base, | |
1368 | GFP_KERNEL | GFP_DMA); | |
1369 | if (!par->v_palette_base) { | |
1370 | dev_err(&device->dev, | |
1371 | "GLCD: kmalloc for palette buffer failed\n"); | |
1372 | ret = -EINVAL; | |
1373 | goto err_release_fb_mem; | |
1374 | } | |
1375 | memset(par->v_palette_base, 0, PALETTE_SIZE); | |
4ed824d9 | 1376 | |
4ed824d9 SR |
1377 | par->irq = platform_get_irq(device, 0); |
1378 | if (par->irq < 0) { | |
1379 | ret = -ENOENT; | |
1f9c3e1f | 1380 | goto err_release_pl_mem; |
4ed824d9 SR |
1381 | } |
1382 | ||
4ed824d9 SR |
1383 | /* Initialize par */ |
1384 | da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp; | |
1385 | ||
1386 | da8xx_fb_var.xres = lcdc_info->width; | |
1387 | da8xx_fb_var.xres_virtual = lcdc_info->width; | |
1388 | ||
1f9c3e1f MA |
1389 | da8xx_fb_var.yres = lcdc_info->height; |
1390 | da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS; | |
4ed824d9 SR |
1391 | |
1392 | da8xx_fb_var.grayscale = | |
1393 | lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; | |
1394 | da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; | |
1395 | ||
1396 | da8xx_fb_var.hsync_len = lcdc_info->hsw; | |
1397 | da8xx_fb_var.vsync_len = lcdc_info->vsw; | |
084e104b AG |
1398 | da8xx_fb_var.right_margin = lcdc_info->hfp; |
1399 | da8xx_fb_var.left_margin = lcdc_info->hbp; | |
1400 | da8xx_fb_var.lower_margin = lcdc_info->vfp; | |
1401 | da8xx_fb_var.upper_margin = lcdc_info->vbp; | |
12fa8350 | 1402 | da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par); |
4ed824d9 SR |
1403 | |
1404 | /* Initialize fbinfo */ | |
1405 | da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; | |
1406 | da8xx_fb_info->fix = da8xx_fb_fix; | |
1407 | da8xx_fb_info->var = da8xx_fb_var; | |
1408 | da8xx_fb_info->fbops = &da8xx_fb_ops; | |
1409 | da8xx_fb_info->pseudo_palette = par->pseudo_palette; | |
3510b8f7 SR |
1410 | da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? |
1411 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
4ed824d9 SR |
1412 | |
1413 | ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0); | |
1414 | if (ret) | |
93c176f3 | 1415 | goto err_release_pl_mem; |
4ed824d9 SR |
1416 | da8xx_fb_info->cmap.len = par->palette_sz; |
1417 | ||
4ed824d9 SR |
1418 | /* initialize var_screeninfo */ |
1419 | da8xx_fb_var.activate = FB_ACTIVATE_FORCE; | |
1420 | fb_set_var(da8xx_fb_info, &da8xx_fb_var); | |
1421 | ||
1422 | dev_set_drvdata(&device->dev, da8xx_fb_info); | |
1f9c3e1f MA |
1423 | |
1424 | /* initialize the vsync wait queue */ | |
1425 | init_waitqueue_head(&par->vsync_wait); | |
1426 | par->vsync_timeout = HZ / 5; | |
deb95c6c MP |
1427 | par->which_dma_channel_done = -1; |
1428 | spin_lock_init(&par->lock_for_chan_update); | |
1f9c3e1f | 1429 | |
4ed824d9 SR |
1430 | /* Register the Frame Buffer */ |
1431 | if (register_framebuffer(da8xx_fb_info) < 0) { | |
1432 | dev_err(&device->dev, | |
1433 | "GLCD: Frame Buffer Registration Failed!\n"); | |
1434 | ret = -EINVAL; | |
1435 | goto err_dealloc_cmap; | |
1436 | } | |
1437 | ||
e04e5483 C |
1438 | #ifdef CONFIG_CPU_FREQ |
1439 | ret = lcd_da8xx_cpufreq_register(par); | |
1440 | if (ret) { | |
1441 | dev_err(&device->dev, "failed to register cpufreq\n"); | |
1442 | goto err_cpu_freq; | |
1443 | } | |
1444 | #endif | |
93c176f3 | 1445 | |
c6daf05b MP |
1446 | if (lcd_revision == LCD_VERSION_1) |
1447 | lcdc_irq_handler = lcdc_irq_handler_rev01; | |
a481b37a MP |
1448 | else { |
1449 | init_waitqueue_head(&frame_done_wq); | |
c6daf05b | 1450 | lcdc_irq_handler = lcdc_irq_handler_rev02; |
a481b37a | 1451 | } |
c6daf05b MP |
1452 | |
1453 | ret = request_irq(par->irq, lcdc_irq_handler, 0, | |
1454 | DRIVER_NAME, par); | |
93c176f3 CA |
1455 | if (ret) |
1456 | goto irq_freq; | |
4ed824d9 SR |
1457 | return 0; |
1458 | ||
93c176f3 | 1459 | irq_freq: |
e04e5483 | 1460 | #ifdef CONFIG_CPU_FREQ |
360c202b | 1461 | lcd_da8xx_cpufreq_deregister(par); |
e04e5483 | 1462 | err_cpu_freq: |
3a84409c | 1463 | #endif |
e04e5483 | 1464 | unregister_framebuffer(da8xx_fb_info); |
e04e5483 | 1465 | |
4ed824d9 SR |
1466 | err_dealloc_cmap: |
1467 | fb_dealloc_cmap(&da8xx_fb_info->cmap); | |
1468 | ||
1f9c3e1f MA |
1469 | err_release_pl_mem: |
1470 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, | |
1471 | par->p_palette_base); | |
1472 | ||
4ed824d9 | 1473 | err_release_fb_mem: |
1f9c3e1f | 1474 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys); |
4ed824d9 SR |
1475 | |
1476 | err_release_fb: | |
1477 | framebuffer_release(da8xx_fb_info); | |
1478 | ||
1479 | err_clk_disable: | |
1480 | clk_disable(fb_clk); | |
1481 | ||
1482 | err_clk_put: | |
1483 | clk_put(fb_clk); | |
1484 | ||
1485 | err_ioremap: | |
1486 | iounmap((void __iomem *)da8xx_fb_reg_base); | |
1487 | ||
1488 | err_request_mem: | |
1489 | release_mem_region(lcdc_regs->start, len); | |
1490 | ||
1491 | return ret; | |
1492 | } | |
1493 | ||
1494 | #ifdef CONFIG_PM | |
1495 | static int fb_suspend(struct platform_device *dev, pm_message_t state) | |
1496 | { | |
1d3c6c7b C |
1497 | struct fb_info *info = platform_get_drvdata(dev); |
1498 | struct da8xx_fb_par *par = info->par; | |
1499 | ||
ac751efa | 1500 | console_lock(); |
1d3c6c7b C |
1501 | if (par->panel_power_ctrl) |
1502 | par->panel_power_ctrl(0); | |
1503 | ||
1504 | fb_set_suspend(info, 1); | |
a481b37a | 1505 | lcd_disable_raster(true); |
1d3c6c7b | 1506 | clk_disable(par->lcdc_clk); |
ac751efa | 1507 | console_unlock(); |
1d3c6c7b C |
1508 | |
1509 | return 0; | |
4ed824d9 SR |
1510 | } |
1511 | static int fb_resume(struct platform_device *dev) | |
1512 | { | |
1d3c6c7b C |
1513 | struct fb_info *info = platform_get_drvdata(dev); |
1514 | struct da8xx_fb_par *par = info->par; | |
1515 | ||
ac751efa | 1516 | console_lock(); |
f7c848b6 | 1517 | clk_enable(par->lcdc_clk); |
67900814 MP |
1518 | if (par->blank == FB_BLANK_UNBLANK) { |
1519 | lcd_enable_raster(); | |
f7c848b6 | 1520 | |
67900814 MP |
1521 | if (par->panel_power_ctrl) |
1522 | par->panel_power_ctrl(1); | |
1523 | } | |
1d3c6c7b | 1524 | |
1d3c6c7b | 1525 | fb_set_suspend(info, 0); |
ac751efa | 1526 | console_unlock(); |
1d3c6c7b C |
1527 | |
1528 | return 0; | |
4ed824d9 SR |
1529 | } |
1530 | #else | |
1531 | #define fb_suspend NULL | |
1532 | #define fb_resume NULL | |
1533 | #endif | |
1534 | ||
1535 | static struct platform_driver da8xx_fb_driver = { | |
1536 | .probe = fb_probe, | |
1db41e03 | 1537 | .remove = __devexit_p(fb_remove), |
4ed824d9 SR |
1538 | .suspend = fb_suspend, |
1539 | .resume = fb_resume, | |
1540 | .driver = { | |
1541 | .name = DRIVER_NAME, | |
1542 | .owner = THIS_MODULE, | |
1543 | }, | |
1544 | }; | |
1545 | ||
1546 | static int __init da8xx_fb_init(void) | |
1547 | { | |
1548 | return platform_driver_register(&da8xx_fb_driver); | |
1549 | } | |
1550 | ||
1551 | static void __exit da8xx_fb_cleanup(void) | |
1552 | { | |
1553 | platform_driver_unregister(&da8xx_fb_driver); | |
1554 | } | |
1555 | ||
1556 | module_init(da8xx_fb_init); | |
1557 | module_exit(da8xx_fb_cleanup); | |
1558 | ||
1559 | MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx"); | |
1560 | MODULE_AUTHOR("Texas Instruments"); | |
1561 | MODULE_LICENSE("GPL"); |