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4ed824d9 SR |
1 | /* |
2 | * Copyright (C) 2008-2009 MontaVista Software Inc. | |
3 | * Copyright (C) 2008-2009 Texas Instruments Inc | |
4 | * | |
5 | * Based on the LCD driver for TI Avalanche processors written by | |
6 | * Ajay Singh and Shalom Hai. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option)any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #include <linux/module.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/fb.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/uaccess.h> | |
9dd44d5d | 29 | #include <linux/pm_runtime.h> |
4ed824d9 | 30 | #include <linux/interrupt.h> |
a481b37a | 31 | #include <linux/wait.h> |
4ed824d9 | 32 | #include <linux/clk.h> |
e04e5483 | 33 | #include <linux/cpufreq.h> |
1d3c6c7b | 34 | #include <linux/console.h> |
deb95c6c | 35 | #include <linux/spinlock.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
a0239073 | 37 | #include <linux/delay.h> |
3b9cc4ea | 38 | #include <linux/lcm.h> |
4ed824d9 | 39 | #include <video/da8xx-fb.h> |
12fa8350 | 40 | #include <asm/div64.h> |
4ed824d9 SR |
41 | |
42 | #define DRIVER_NAME "da8xx_lcdc" | |
43 | ||
c6daf05b MP |
44 | #define LCD_VERSION_1 1 |
45 | #define LCD_VERSION_2 2 | |
46 | ||
4ed824d9 | 47 | /* LCD Status Register */ |
1f9c3e1f | 48 | #define LCD_END_OF_FRAME1 BIT(9) |
4ed824d9 | 49 | #define LCD_END_OF_FRAME0 BIT(8) |
1f9c3e1f | 50 | #define LCD_PL_LOAD_DONE BIT(6) |
4ed824d9 SR |
51 | #define LCD_FIFO_UNDERFLOW BIT(5) |
52 | #define LCD_SYNC_LOST BIT(2) | |
a481b37a | 53 | #define LCD_FRAME_DONE BIT(0) |
4ed824d9 SR |
54 | |
55 | /* LCD DMA Control Register */ | |
56 | #define LCD_DMA_BURST_SIZE(x) ((x) << 4) | |
57 | #define LCD_DMA_BURST_1 0x0 | |
58 | #define LCD_DMA_BURST_2 0x1 | |
59 | #define LCD_DMA_BURST_4 0x2 | |
60 | #define LCD_DMA_BURST_8 0x3 | |
61 | #define LCD_DMA_BURST_16 0x4 | |
c6daf05b MP |
62 | #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) |
63 | #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) | |
64 | #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) | |
4ed824d9 SR |
65 | #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) |
66 | ||
67 | /* LCD Control Register */ | |
68 | #define LCD_CLK_DIVISOR(x) ((x) << 8) | |
69 | #define LCD_RASTER_MODE 0x01 | |
70 | ||
71 | /* LCD Raster Control Register */ | |
72 | #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) | |
73 | #define PALETTE_AND_DATA 0x00 | |
74 | #define PALETTE_ONLY 0x01 | |
1f9c3e1f | 75 | #define DATA_ONLY 0x02 |
4ed824d9 SR |
76 | |
77 | #define LCD_MONO_8BIT_MODE BIT(9) | |
78 | #define LCD_RASTER_ORDER BIT(8) | |
79 | #define LCD_TFT_MODE BIT(7) | |
c6daf05b MP |
80 | #define LCD_V1_UNDERFLOW_INT_ENA BIT(6) |
81 | #define LCD_V2_UNDERFLOW_INT_ENA BIT(5) | |
82 | #define LCD_V1_PL_INT_ENA BIT(4) | |
83 | #define LCD_V2_PL_INT_ENA BIT(6) | |
4ed824d9 SR |
84 | #define LCD_MONOCHROME_MODE BIT(1) |
85 | #define LCD_RASTER_ENABLE BIT(0) | |
86 | #define LCD_TFT_ALT_ENABLE BIT(23) | |
87 | #define LCD_STN_565_ENABLE BIT(24) | |
c6daf05b MP |
88 | #define LCD_V2_DMA_CLK_EN BIT(2) |
89 | #define LCD_V2_LIDD_CLK_EN BIT(1) | |
90 | #define LCD_V2_CORE_CLK_EN BIT(0) | |
91 | #define LCD_V2_LPP_B10 26 | |
1a2b750c MP |
92 | #define LCD_V2_TFT_24BPP_MODE BIT(25) |
93 | #define LCD_V2_TFT_24BPP_UNPACK BIT(26) | |
4ed824d9 SR |
94 | |
95 | /* LCD Raster Timing 2 Register */ | |
96 | #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) | |
97 | #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) | |
98 | #define LCD_SYNC_CTRL BIT(25) | |
99 | #define LCD_SYNC_EDGE BIT(24) | |
100 | #define LCD_INVERT_PIXEL_CLOCK BIT(22) | |
101 | #define LCD_INVERT_LINE_CLOCK BIT(21) | |
102 | #define LCD_INVERT_FRAME_CLOCK BIT(20) | |
103 | ||
104 | /* LCD Block */ | |
c6daf05b | 105 | #define LCD_PID_REG 0x0 |
4ed824d9 SR |
106 | #define LCD_CTRL_REG 0x4 |
107 | #define LCD_STAT_REG 0x8 | |
108 | #define LCD_RASTER_CTRL_REG 0x28 | |
109 | #define LCD_RASTER_TIMING_0_REG 0x2C | |
110 | #define LCD_RASTER_TIMING_1_REG 0x30 | |
111 | #define LCD_RASTER_TIMING_2_REG 0x34 | |
112 | #define LCD_DMA_CTRL_REG 0x40 | |
113 | #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44 | |
114 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48 | |
1f9c3e1f MA |
115 | #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C |
116 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50 | |
117 | ||
c6daf05b MP |
118 | /* Interrupt Registers available only in Version 2 */ |
119 | #define LCD_RAW_STAT_REG 0x58 | |
120 | #define LCD_MASKED_STAT_REG 0x5c | |
121 | #define LCD_INT_ENABLE_SET_REG 0x60 | |
122 | #define LCD_INT_ENABLE_CLR_REG 0x64 | |
123 | #define LCD_END_OF_INT_IND_REG 0x68 | |
124 | ||
125 | /* Clock registers available only on Version 2 */ | |
126 | #define LCD_CLK_ENABLE_REG 0x6c | |
127 | #define LCD_CLK_RESET_REG 0x70 | |
74a0efde | 128 | #define LCD_CLK_MAIN_RESET BIT(3) |
c6daf05b | 129 | |
1f9c3e1f | 130 | #define LCD_NUM_BUFFERS 2 |
4ed824d9 SR |
131 | |
132 | #define WSI_TIMEOUT 50 | |
133 | #define PALETTE_SIZE 256 | |
4ed824d9 | 134 | |
34aef6eb | 135 | static void __iomem *da8xx_fb_reg_base; |
4ed824d9 | 136 | static struct resource *lcdc_regs; |
c6daf05b MP |
137 | static unsigned int lcd_revision; |
138 | static irq_handler_t lcdc_irq_handler; | |
a481b37a MP |
139 | static wait_queue_head_t frame_done_wq; |
140 | static int frame_done_flag; | |
4ed824d9 SR |
141 | |
142 | static inline unsigned int lcdc_read(unsigned int addr) | |
143 | { | |
144 | return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr)); | |
145 | } | |
146 | ||
147 | static inline void lcdc_write(unsigned int val, unsigned int addr) | |
148 | { | |
149 | __raw_writel(val, da8xx_fb_reg_base + (addr)); | |
150 | } | |
151 | ||
152 | struct da8xx_fb_par { | |
dbe8e48a | 153 | struct device *dev; |
4ed824d9 SR |
154 | resource_size_t p_palette_base; |
155 | unsigned char *v_palette_base; | |
1f9c3e1f MA |
156 | dma_addr_t vram_phys; |
157 | unsigned long vram_size; | |
158 | void *vram_virt; | |
159 | unsigned int dma_start; | |
160 | unsigned int dma_end; | |
4ed824d9 SR |
161 | struct clk *lcdc_clk; |
162 | int irq; | |
4ed824d9 | 163 | unsigned int palette_sz; |
36113804 | 164 | int blank; |
1f9c3e1f MA |
165 | wait_queue_head_t vsync_wait; |
166 | int vsync_flag; | |
167 | int vsync_timeout; | |
deb95c6c MP |
168 | spinlock_t lock_for_chan_update; |
169 | ||
170 | /* | |
171 | * LCDC has 2 ping pong DMA channels, channel 0 | |
172 | * and channel 1. | |
173 | */ | |
174 | unsigned int which_dma_channel_done; | |
e04e5483 C |
175 | #ifdef CONFIG_CPU_FREQ |
176 | struct notifier_block freq_transition; | |
177 | #endif | |
44f627ae | 178 | unsigned int lcd_fck_rate; |
36113804 | 179 | void (*panel_power_ctrl)(int); |
1a2b750c | 180 | u32 pseudo_palette[16]; |
b6dbe8e4 AM |
181 | struct fb_videomode mode; |
182 | struct lcd_ctrl_config cfg; | |
4ed824d9 SR |
183 | }; |
184 | ||
be0f6dbc | 185 | static struct fb_var_screeninfo da8xx_fb_var; |
4ed824d9 | 186 | |
48c68c4f | 187 | static struct fb_fix_screeninfo da8xx_fb_fix = { |
4ed824d9 SR |
188 | .id = "DA8xx FB Drv", |
189 | .type = FB_TYPE_PACKED_PIXELS, | |
190 | .type_aux = 0, | |
191 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
1f9c3e1f | 192 | .xpanstep = 0, |
4ed824d9 | 193 | .ypanstep = 1, |
1f9c3e1f | 194 | .ywrapstep = 0, |
4ed824d9 SR |
195 | .accel = FB_ACCEL_NONE |
196 | }; | |
197 | ||
f772fabd | 198 | static struct fb_videomode known_lcd_panels[] = { |
4ed824d9 SR |
199 | /* Sharp LCD035Q3DG01 */ |
200 | [0] = { | |
f772fabd MP |
201 | .name = "Sharp_LCD035Q3DG01", |
202 | .xres = 320, | |
203 | .yres = 240, | |
a6a799f8 | 204 | .pixclock = KHZ2PICOS(4607), |
f772fabd MP |
205 | .left_margin = 6, |
206 | .right_margin = 8, | |
207 | .upper_margin = 2, | |
208 | .lower_margin = 2, | |
209 | .hsync_len = 0, | |
210 | .vsync_len = 0, | |
3b43ad20 MP |
211 | .sync = FB_SYNC_CLK_INVERT | |
212 | FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
4ed824d9 SR |
213 | }, |
214 | /* Sharp LK043T1DG01 */ | |
215 | [1] = { | |
f772fabd MP |
216 | .name = "Sharp_LK043T1DG01", |
217 | .xres = 480, | |
218 | .yres = 272, | |
a6a799f8 | 219 | .pixclock = KHZ2PICOS(7833), |
f772fabd MP |
220 | .left_margin = 2, |
221 | .right_margin = 2, | |
222 | .upper_margin = 2, | |
223 | .lower_margin = 2, | |
224 | .hsync_len = 41, | |
225 | .vsync_len = 10, | |
3b43ad20 | 226 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
f772fabd | 227 | .flag = 0, |
4ed824d9 | 228 | }, |
f413070e AG |
229 | [2] = { |
230 | /* Hitachi SP10Q010 */ | |
f772fabd MP |
231 | .name = "SP10Q010", |
232 | .xres = 320, | |
233 | .yres = 240, | |
a6a799f8 | 234 | .pixclock = KHZ2PICOS(7833), |
f772fabd MP |
235 | .left_margin = 10, |
236 | .right_margin = 10, | |
237 | .upper_margin = 10, | |
238 | .lower_margin = 10, | |
239 | .hsync_len = 10, | |
240 | .vsync_len = 10, | |
3b43ad20 | 241 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
f772fabd | 242 | .flag = 0, |
f413070e | 243 | }, |
4ed824d9 SR |
244 | }; |
245 | ||
36113804 C |
246 | /* Enable the Raster Engine of the LCD Controller */ |
247 | static inline void lcd_enable_raster(void) | |
248 | { | |
249 | u32 reg; | |
250 | ||
92b4e450 MP |
251 | /* Put LCDC in reset for several cycles */ |
252 | if (lcd_revision == LCD_VERSION_2) | |
253 | /* Write 1 to reset LCDC */ | |
254 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
255 | mdelay(1); | |
256 | ||
74a0efde MP |
257 | /* Bring LCDC out of reset */ |
258 | if (lcd_revision == LCD_VERSION_2) | |
259 | lcdc_write(0, LCD_CLK_RESET_REG); | |
92b4e450 | 260 | mdelay(1); |
74a0efde | 261 | |
92b4e450 | 262 | /* Above reset sequence doesnot reset register context */ |
36113804 C |
263 | reg = lcdc_read(LCD_RASTER_CTRL_REG); |
264 | if (!(reg & LCD_RASTER_ENABLE)) | |
265 | lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); | |
266 | } | |
267 | ||
4ed824d9 | 268 | /* Disable the Raster Engine of the LCD Controller */ |
a481b37a | 269 | static inline void lcd_disable_raster(bool wait_for_frame_done) |
4ed824d9 | 270 | { |
4ed824d9 | 271 | u32 reg; |
a481b37a | 272 | int ret; |
4ed824d9 SR |
273 | |
274 | reg = lcdc_read(LCD_RASTER_CTRL_REG); | |
2f93e8f4 | 275 | if (reg & LCD_RASTER_ENABLE) |
4ed824d9 | 276 | lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); |
a481b37a MP |
277 | else |
278 | /* return if already disabled */ | |
279 | return; | |
280 | ||
281 | if ((wait_for_frame_done == true) && (lcd_revision == LCD_VERSION_2)) { | |
282 | frame_done_flag = 0; | |
283 | ret = wait_event_interruptible_timeout(frame_done_wq, | |
284 | frame_done_flag != 0, | |
285 | msecs_to_jiffies(50)); | |
286 | if (ret == 0) | |
287 | pr_err("LCD Controller timed out\n"); | |
288 | } | |
4ed824d9 SR |
289 | } |
290 | ||
291 | static void lcd_blit(int load_mode, struct da8xx_fb_par *par) | |
292 | { | |
1f9c3e1f MA |
293 | u32 start; |
294 | u32 end; | |
295 | u32 reg_ras; | |
296 | u32 reg_dma; | |
c6daf05b | 297 | u32 reg_int; |
1f9c3e1f MA |
298 | |
299 | /* init reg to clear PLM (loading mode) fields */ | |
300 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
301 | reg_ras &= ~(3 << 20); | |
302 | ||
303 | reg_dma = lcdc_read(LCD_DMA_CTRL_REG); | |
304 | ||
305 | if (load_mode == LOAD_DATA) { | |
306 | start = par->dma_start; | |
307 | end = par->dma_end; | |
308 | ||
309 | reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); | |
c6daf05b MP |
310 | if (lcd_revision == LCD_VERSION_1) { |
311 | reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; | |
312 | } else { | |
313 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
314 | LCD_V2_END_OF_FRAME0_INT_ENA | | |
a481b37a MP |
315 | LCD_V2_END_OF_FRAME1_INT_ENA | |
316 | LCD_FRAME_DONE; | |
c6daf05b MP |
317 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); |
318 | } | |
1f9c3e1f MA |
319 | reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; |
320 | ||
321 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
322 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
323 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
324 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
325 | } else if (load_mode == LOAD_PALETTE) { | |
326 | start = par->p_palette_base; | |
327 | end = start + par->palette_sz - 1; | |
328 | ||
329 | reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); | |
c6daf05b MP |
330 | |
331 | if (lcd_revision == LCD_VERSION_1) { | |
332 | reg_ras |= LCD_V1_PL_INT_ENA; | |
333 | } else { | |
334 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
335 | LCD_V2_PL_INT_ENA; | |
336 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
337 | } | |
1f9c3e1f MA |
338 | |
339 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
340 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
341 | } | |
4ed824d9 | 342 | |
1f9c3e1f MA |
343 | lcdc_write(reg_dma, LCD_DMA_CTRL_REG); |
344 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); | |
4ed824d9 | 345 | |
1f9c3e1f MA |
346 | /* |
347 | * The Raster enable bit must be set after all other control fields are | |
348 | * set. | |
349 | */ | |
350 | lcd_enable_raster(); | |
4ed824d9 SR |
351 | } |
352 | ||
fb8fa943 MP |
353 | /* Configure the Burst Size and fifo threhold of DMA */ |
354 | static int lcd_cfg_dma(int burst_size, int fifo_th) | |
4ed824d9 SR |
355 | { |
356 | u32 reg; | |
357 | ||
358 | reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001; | |
359 | switch (burst_size) { | |
360 | case 1: | |
361 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); | |
362 | break; | |
363 | case 2: | |
364 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); | |
365 | break; | |
366 | case 4: | |
367 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); | |
368 | break; | |
369 | case 8: | |
370 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); | |
371 | break; | |
372 | case 16: | |
3b43ad20 | 373 | default: |
4ed824d9 SR |
374 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); |
375 | break; | |
4ed824d9 | 376 | } |
fb8fa943 MP |
377 | |
378 | reg |= (fifo_th << 8); | |
379 | ||
2f93e8f4 | 380 | lcdc_write(reg, LCD_DMA_CTRL_REG); |
4ed824d9 SR |
381 | |
382 | return 0; | |
383 | } | |
384 | ||
385 | static void lcd_cfg_ac_bias(int period, int transitions_per_int) | |
386 | { | |
387 | u32 reg; | |
388 | ||
389 | /* Set the AC Bias Period and Number of Transisitons per Interrupt */ | |
390 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000; | |
391 | reg |= LCD_AC_BIAS_FREQUENCY(period) | | |
392 | LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); | |
393 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
394 | } | |
395 | ||
396 | static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, | |
397 | int front_porch) | |
398 | { | |
399 | u32 reg; | |
400 | ||
401 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf; | |
402 | reg |= ((back_porch & 0xff) << 24) | |
403 | | ((front_porch & 0xff) << 16) | |
404 | | ((pulse_width & 0x3f) << 10); | |
405 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); | |
406 | } | |
407 | ||
408 | static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, | |
409 | int front_porch) | |
410 | { | |
411 | u32 reg; | |
412 | ||
413 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff; | |
414 | reg |= ((back_porch & 0xff) << 24) | |
415 | | ((front_porch & 0xff) << 16) | |
416 | | ((pulse_width & 0x3f) << 10); | |
417 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
418 | } | |
419 | ||
3b43ad20 MP |
420 | static int lcd_cfg_display(const struct lcd_ctrl_config *cfg, |
421 | struct fb_videomode *panel) | |
4ed824d9 SR |
422 | { |
423 | u32 reg; | |
c6daf05b | 424 | u32 reg_int; |
4ed824d9 SR |
425 | |
426 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE | | |
427 | LCD_MONO_8BIT_MODE | | |
428 | LCD_MONOCHROME_MODE); | |
429 | ||
3b43ad20 | 430 | switch (cfg->panel_shade) { |
4ed824d9 SR |
431 | case MONOCHROME: |
432 | reg |= LCD_MONOCHROME_MODE; | |
433 | if (cfg->mono_8bit_mode) | |
434 | reg |= LCD_MONO_8BIT_MODE; | |
435 | break; | |
436 | case COLOR_ACTIVE: | |
437 | reg |= LCD_TFT_MODE; | |
438 | if (cfg->tft_alt_mode) | |
439 | reg |= LCD_TFT_ALT_ENABLE; | |
440 | break; | |
441 | ||
442 | case COLOR_PASSIVE: | |
3b43ad20 MP |
443 | /* AC bias applicable only for Pasive panels */ |
444 | lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); | |
445 | if (cfg->bpp == 12 && cfg->stn_565_mode) | |
4ed824d9 SR |
446 | reg |= LCD_STN_565_ENABLE; |
447 | break; | |
448 | ||
449 | default: | |
450 | return -EINVAL; | |
451 | } | |
452 | ||
453 | /* enable additional interrupts here */ | |
c6daf05b MP |
454 | if (lcd_revision == LCD_VERSION_1) { |
455 | reg |= LCD_V1_UNDERFLOW_INT_ENA; | |
456 | } else { | |
457 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
458 | LCD_V2_UNDERFLOW_INT_ENA; | |
459 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
460 | } | |
4ed824d9 SR |
461 | |
462 | lcdc_write(reg, LCD_RASTER_CTRL_REG); | |
463 | ||
464 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
465 | ||
3b43ad20 | 466 | reg |= LCD_SYNC_CTRL; |
4ed824d9 SR |
467 | |
468 | if (cfg->sync_edge) | |
469 | reg |= LCD_SYNC_EDGE; | |
470 | else | |
471 | reg &= ~LCD_SYNC_EDGE; | |
472 | ||
3b43ad20 | 473 | if (panel->sync & FB_SYNC_HOR_HIGH_ACT) |
4ed824d9 SR |
474 | reg |= LCD_INVERT_LINE_CLOCK; |
475 | else | |
476 | reg &= ~LCD_INVERT_LINE_CLOCK; | |
477 | ||
3b43ad20 | 478 | if (panel->sync & FB_SYNC_VERT_HIGH_ACT) |
4ed824d9 SR |
479 | reg |= LCD_INVERT_FRAME_CLOCK; |
480 | else | |
481 | reg &= ~LCD_INVERT_FRAME_CLOCK; | |
482 | ||
483 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, | |
489 | u32 bpp, u32 raster_order) | |
490 | { | |
1f9c3e1f | 491 | u32 reg; |
4ed824d9 | 492 | |
1a2b750c MP |
493 | if (bpp > 16 && lcd_revision == LCD_VERSION_1) |
494 | return -EINVAL; | |
495 | ||
4ed824d9 SR |
496 | /* Set the Panel Width */ |
497 | /* Pixels per line = (PPL + 1)*16 */ | |
4d740801 MP |
498 | if (lcd_revision == LCD_VERSION_1) { |
499 | /* | |
500 | * 0x3F in bits 4..9 gives max horizontal resolution = 1024 | |
501 | * pixels. | |
502 | */ | |
503 | width &= 0x3f0; | |
504 | } else { | |
505 | /* | |
506 | * 0x7F in bits 4..10 gives max horizontal resolution = 2048 | |
507 | * pixels. | |
508 | */ | |
509 | width &= 0x7f0; | |
510 | } | |
511 | ||
4ed824d9 SR |
512 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG); |
513 | reg &= 0xfffffc00; | |
4d740801 MP |
514 | if (lcd_revision == LCD_VERSION_1) { |
515 | reg |= ((width >> 4) - 1) << 4; | |
516 | } else { | |
517 | width = (width >> 4) - 1; | |
518 | reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); | |
519 | } | |
4ed824d9 SR |
520 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); |
521 | ||
522 | /* Set the Panel Height */ | |
4d740801 | 523 | /* Set bits 9:0 of Lines Per Pixel */ |
4ed824d9 SR |
524 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG); |
525 | reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); | |
526 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
527 | ||
4d740801 MP |
528 | /* Set bit 10 of Lines Per Pixel */ |
529 | if (lcd_revision == LCD_VERSION_2) { | |
530 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
531 | reg |= ((height - 1) & 0x400) << 16; | |
532 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
533 | } | |
534 | ||
4ed824d9 SR |
535 | /* Set the Raster Order of the Frame Buffer */ |
536 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8); | |
537 | if (raster_order) | |
538 | reg |= LCD_RASTER_ORDER; | |
1a2b750c MP |
539 | |
540 | par->palette_sz = 16 * 2; | |
4ed824d9 SR |
541 | |
542 | switch (bpp) { | |
543 | case 1: | |
544 | case 2: | |
545 | case 4: | |
546 | case 16: | |
1a2b750c MP |
547 | break; |
548 | case 24: | |
549 | reg |= LCD_V2_TFT_24BPP_MODE; | |
550 | case 32: | |
551 | reg |= LCD_V2_TFT_24BPP_UNPACK; | |
4ed824d9 SR |
552 | break; |
553 | ||
554 | case 8: | |
555 | par->palette_sz = 256 * 2; | |
556 | break; | |
557 | ||
558 | default: | |
559 | return -EINVAL; | |
560 | } | |
561 | ||
1a2b750c MP |
562 | lcdc_write(reg, LCD_RASTER_CTRL_REG); |
563 | ||
4ed824d9 SR |
564 | return 0; |
565 | } | |
566 | ||
1a2b750c | 567 | #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) |
4ed824d9 SR |
568 | static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, |
569 | unsigned blue, unsigned transp, | |
570 | struct fb_info *info) | |
571 | { | |
572 | struct da8xx_fb_par *par = info->par; | |
1f9c3e1f | 573 | unsigned short *palette = (unsigned short *) par->v_palette_base; |
4ed824d9 | 574 | u_short pal; |
1f9c3e1f | 575 | int update_hw = 0; |
4ed824d9 SR |
576 | |
577 | if (regno > 255) | |
578 | return 1; | |
579 | ||
580 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) | |
581 | return 1; | |
582 | ||
1a2b750c MP |
583 | if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
584 | return -EINVAL; | |
f413070e | 585 | |
1a2b750c MP |
586 | switch (info->fix.visual) { |
587 | case FB_VISUAL_TRUECOLOR: | |
588 | red = CNVT_TOHW(red, info->var.red.length); | |
589 | green = CNVT_TOHW(green, info->var.green.length); | |
590 | blue = CNVT_TOHW(blue, info->var.blue.length); | |
591 | break; | |
592 | case FB_VISUAL_PSEUDOCOLOR: | |
593 | switch (info->var.bits_per_pixel) { | |
594 | case 4: | |
595 | if (regno > 15) | |
596 | return -EINVAL; | |
597 | ||
598 | if (info->var.grayscale) { | |
599 | pal = regno; | |
600 | } else { | |
601 | red >>= 4; | |
602 | green >>= 8; | |
603 | blue >>= 12; | |
604 | ||
605 | pal = red & 0x0f00; | |
606 | pal |= green & 0x00f0; | |
607 | pal |= blue & 0x000f; | |
608 | } | |
609 | if (regno == 0) | |
610 | pal |= 0x2000; | |
611 | palette[regno] = pal; | |
612 | break; | |
613 | ||
614 | case 8: | |
f413070e AG |
615 | red >>= 4; |
616 | green >>= 8; | |
617 | blue >>= 12; | |
618 | ||
619 | pal = (red & 0x0f00); | |
620 | pal |= (green & 0x00f0); | |
621 | pal |= (blue & 0x000f); | |
4ed824d9 | 622 | |
1a2b750c MP |
623 | if (palette[regno] != pal) { |
624 | update_hw = 1; | |
625 | palette[regno] = pal; | |
626 | } | |
627 | break; | |
1f9c3e1f | 628 | } |
1a2b750c MP |
629 | break; |
630 | } | |
4ed824d9 | 631 | |
1a2b750c MP |
632 | /* Truecolor has hardware independent palette */ |
633 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { | |
634 | u32 v; | |
4ed824d9 | 635 | |
1a2b750c MP |
636 | if (regno > 15) |
637 | return -EINVAL; | |
4ed824d9 | 638 | |
1a2b750c MP |
639 | v = (red << info->var.red.offset) | |
640 | (green << info->var.green.offset) | | |
641 | (blue << info->var.blue.offset); | |
4ed824d9 | 642 | |
1a2b750c MP |
643 | switch (info->var.bits_per_pixel) { |
644 | case 16: | |
645 | ((u16 *) (info->pseudo_palette))[regno] = v; | |
646 | break; | |
647 | case 24: | |
648 | case 32: | |
649 | ((u32 *) (info->pseudo_palette))[regno] = v; | |
650 | break; | |
651 | } | |
1f9c3e1f MA |
652 | if (palette[0] != 0x4000) { |
653 | update_hw = 1; | |
654 | palette[0] = 0x4000; | |
655 | } | |
4ed824d9 SR |
656 | } |
657 | ||
1f9c3e1f MA |
658 | /* Update the palette in the h/w as needed. */ |
659 | if (update_hw) | |
660 | lcd_blit(LOAD_PALETTE, par); | |
661 | ||
4ed824d9 SR |
662 | return 0; |
663 | } | |
1a2b750c | 664 | #undef CNVT_TOHW |
4ed824d9 | 665 | |
39c87d45 | 666 | static void da8xx_fb_lcd_reset(void) |
4ed824d9 | 667 | { |
4ed824d9 | 668 | /* Disable the Raster if previously Enabled */ |
a481b37a | 669 | lcd_disable_raster(false); |
4ed824d9 SR |
670 | |
671 | /* DMA has to be disabled */ | |
672 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
673 | lcdc_write(0, LCD_RASTER_CTRL_REG); | |
c6daf05b | 674 | |
74a0efde | 675 | if (lcd_revision == LCD_VERSION_2) { |
c6daf05b | 676 | lcdc_write(0, LCD_INT_ENABLE_SET_REG); |
74a0efde MP |
677 | /* Write 1 to reset */ |
678 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
679 | lcdc_write(0, LCD_CLK_RESET_REG); | |
680 | } | |
4ed824d9 SR |
681 | } |
682 | ||
a6a799f8 DE |
683 | static inline unsigned da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par, |
684 | unsigned pixclock) | |
8097b174 | 685 | { |
a6a799f8 DE |
686 | return par->lcd_fck_rate / (PICOS2KHZ(pixclock) * 1000); |
687 | } | |
8097b174 | 688 | |
a6a799f8 DE |
689 | static inline void da8xx_fb_config_clk_divider(unsigned div) |
690 | { | |
8097b174 C |
691 | /* Configure the LCD clock divisor. */ |
692 | lcdc_write(LCD_CLK_DIVISOR(div) | | |
693 | (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG); | |
c6daf05b MP |
694 | |
695 | if (lcd_revision == LCD_VERSION_2) | |
696 | lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | | |
697 | LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG); | |
a6a799f8 DE |
698 | } |
699 | ||
700 | static inline void da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par, | |
701 | struct fb_videomode *mode) | |
702 | { | |
703 | unsigned div = da8xx_fb_calc_clk_divider(par, mode->pixclock); | |
c6daf05b | 704 | |
a6a799f8 | 705 | da8xx_fb_config_clk_divider(div); |
8097b174 C |
706 | } |
707 | ||
4ed824d9 | 708 | static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, |
f772fabd | 709 | struct fb_videomode *panel) |
4ed824d9 SR |
710 | { |
711 | u32 bpp; | |
712 | int ret = 0; | |
713 | ||
39c87d45 | 714 | da8xx_fb_lcd_reset(); |
4ed824d9 | 715 | |
a6a799f8 | 716 | da8xx_fb_calc_config_clk_divider(par, panel); |
4ed824d9 | 717 | |
f772fabd | 718 | if (panel->sync & FB_SYNC_CLK_INVERT) |
2f93e8f4 SR |
719 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) | |
720 | LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
721 | else | |
722 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) & | |
723 | ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
724 | ||
fb8fa943 MP |
725 | /* Configure the DMA burst size and fifo threshold. */ |
726 | ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th); | |
4ed824d9 SR |
727 | if (ret < 0) |
728 | return ret; | |
729 | ||
4ed824d9 | 730 | /* Configure the vertical and horizontal sync properties. */ |
f772fabd MP |
731 | lcd_cfg_vertical_sync(panel->lower_margin, panel->vsync_len, |
732 | panel->upper_margin); | |
733 | lcd_cfg_horizontal_sync(panel->right_margin, panel->hsync_len, | |
734 | panel->left_margin); | |
4ed824d9 SR |
735 | |
736 | /* Configure for disply */ | |
3b43ad20 | 737 | ret = lcd_cfg_display(cfg, panel); |
4ed824d9 SR |
738 | if (ret < 0) |
739 | return ret; | |
740 | ||
3b43ad20 | 741 | bpp = cfg->bpp; |
4ed824d9 | 742 | |
4ed824d9 SR |
743 | if (bpp == 12) |
744 | bpp = 16; | |
f772fabd MP |
745 | ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres, |
746 | (unsigned int)panel->yres, bpp, | |
4ed824d9 SR |
747 | cfg->raster_order); |
748 | if (ret < 0) | |
749 | return ret; | |
750 | ||
751 | /* Configure FDD */ | |
752 | lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) | | |
753 | (cfg->fdd << 12), LCD_RASTER_CTRL_REG); | |
754 | ||
755 | return 0; | |
756 | } | |
757 | ||
c6daf05b MP |
758 | /* IRQ handler for version 2 of LCDC */ |
759 | static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) | |
760 | { | |
761 | struct da8xx_fb_par *par = arg; | |
762 | u32 stat = lcdc_read(LCD_MASKED_STAT_REG); | |
c6daf05b MP |
763 | |
764 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
a481b37a | 765 | lcd_disable_raster(false); |
c6daf05b MP |
766 | lcdc_write(stat, LCD_MASKED_STAT_REG); |
767 | lcd_enable_raster(); | |
768 | } else if (stat & LCD_PL_LOAD_DONE) { | |
769 | /* | |
770 | * Must disable raster before changing state of any control bit. | |
771 | * And also must be disabled before clearing the PL loading | |
772 | * interrupt via the following write to the status register. If | |
773 | * this is done after then one gets multiple PL done interrupts. | |
774 | */ | |
a481b37a | 775 | lcd_disable_raster(false); |
c6daf05b MP |
776 | |
777 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
778 | ||
8a81dccd MP |
779 | /* Disable PL completion interrupt */ |
780 | lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG); | |
c6daf05b MP |
781 | |
782 | /* Setup and start data loading mode */ | |
783 | lcd_blit(LOAD_DATA, par); | |
784 | } else { | |
785 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
786 | ||
787 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 788 | par->which_dma_channel_done = 0; |
c6daf05b MP |
789 | lcdc_write(par->dma_start, |
790 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
791 | lcdc_write(par->dma_end, | |
792 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
793 | par->vsync_flag = 1; | |
794 | wake_up_interruptible(&par->vsync_wait); | |
795 | } | |
796 | ||
797 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 798 | par->which_dma_channel_done = 1; |
c6daf05b MP |
799 | lcdc_write(par->dma_start, |
800 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
801 | lcdc_write(par->dma_end, | |
802 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
803 | par->vsync_flag = 1; | |
804 | wake_up_interruptible(&par->vsync_wait); | |
805 | } | |
a481b37a MP |
806 | |
807 | /* Set only when controller is disabled and at the end of | |
808 | * active frame | |
809 | */ | |
810 | if (stat & BIT(0)) { | |
811 | frame_done_flag = 1; | |
812 | wake_up_interruptible(&frame_done_wq); | |
813 | } | |
c6daf05b MP |
814 | } |
815 | ||
816 | lcdc_write(0, LCD_END_OF_INT_IND_REG); | |
817 | return IRQ_HANDLED; | |
818 | } | |
819 | ||
820 | /* IRQ handler for version 1 LCDC */ | |
821 | static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg) | |
4ed824d9 | 822 | { |
1f9c3e1f | 823 | struct da8xx_fb_par *par = arg; |
4ed824d9 | 824 | u32 stat = lcdc_read(LCD_STAT_REG); |
1f9c3e1f | 825 | u32 reg_ras; |
4ed824d9 SR |
826 | |
827 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
a481b37a | 828 | lcd_disable_raster(false); |
4ed824d9 | 829 | lcdc_write(stat, LCD_STAT_REG); |
36113804 | 830 | lcd_enable_raster(); |
1f9c3e1f MA |
831 | } else if (stat & LCD_PL_LOAD_DONE) { |
832 | /* | |
833 | * Must disable raster before changing state of any control bit. | |
834 | * And also must be disabled before clearing the PL loading | |
835 | * interrupt via the following write to the status register. If | |
836 | * this is done after then one gets multiple PL done interrupts. | |
837 | */ | |
a481b37a | 838 | lcd_disable_raster(false); |
1f9c3e1f | 839 | |
4ed824d9 SR |
840 | lcdc_write(stat, LCD_STAT_REG); |
841 | ||
1f9c3e1f MA |
842 | /* Disable PL completion inerrupt */ |
843 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
c6daf05b | 844 | reg_ras &= ~LCD_V1_PL_INT_ENA; |
1f9c3e1f MA |
845 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); |
846 | ||
847 | /* Setup and start data loading mode */ | |
848 | lcd_blit(LOAD_DATA, par); | |
849 | } else { | |
850 | lcdc_write(stat, LCD_STAT_REG); | |
851 | ||
852 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 853 | par->which_dma_channel_done = 0; |
1f9c3e1f MA |
854 | lcdc_write(par->dma_start, |
855 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
856 | lcdc_write(par->dma_end, | |
857 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
858 | par->vsync_flag = 1; | |
859 | wake_up_interruptible(&par->vsync_wait); | |
860 | } | |
861 | ||
862 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 863 | par->which_dma_channel_done = 1; |
1f9c3e1f MA |
864 | lcdc_write(par->dma_start, |
865 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
866 | lcdc_write(par->dma_end, | |
867 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
868 | par->vsync_flag = 1; | |
869 | wake_up_interruptible(&par->vsync_wait); | |
870 | } | |
871 | } | |
872 | ||
4ed824d9 SR |
873 | return IRQ_HANDLED; |
874 | } | |
875 | ||
876 | static int fb_check_var(struct fb_var_screeninfo *var, | |
877 | struct fb_info *info) | |
878 | { | |
879 | int err = 0; | |
87dac71d AM |
880 | struct da8xx_fb_par *par = info->par; |
881 | int bpp = var->bits_per_pixel >> 3; | |
882 | unsigned long line_size = var->xres_virtual * bpp; | |
4ed824d9 | 883 | |
1a2b750c MP |
884 | if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
885 | return -EINVAL; | |
886 | ||
4ed824d9 SR |
887 | switch (var->bits_per_pixel) { |
888 | case 1: | |
889 | case 8: | |
890 | var->red.offset = 0; | |
891 | var->red.length = 8; | |
892 | var->green.offset = 0; | |
893 | var->green.length = 8; | |
894 | var->blue.offset = 0; | |
895 | var->blue.length = 8; | |
896 | var->transp.offset = 0; | |
897 | var->transp.length = 0; | |
f413070e | 898 | var->nonstd = 0; |
4ed824d9 SR |
899 | break; |
900 | case 4: | |
901 | var->red.offset = 0; | |
902 | var->red.length = 4; | |
903 | var->green.offset = 0; | |
904 | var->green.length = 4; | |
905 | var->blue.offset = 0; | |
906 | var->blue.length = 4; | |
907 | var->transp.offset = 0; | |
908 | var->transp.length = 0; | |
f413070e | 909 | var->nonstd = FB_NONSTD_REV_PIX_IN_B; |
4ed824d9 SR |
910 | break; |
911 | case 16: /* RGB 565 */ | |
3510b8f7 | 912 | var->red.offset = 11; |
4ed824d9 SR |
913 | var->red.length = 5; |
914 | var->green.offset = 5; | |
915 | var->green.length = 6; | |
3510b8f7 | 916 | var->blue.offset = 0; |
4ed824d9 SR |
917 | var->blue.length = 5; |
918 | var->transp.offset = 0; | |
919 | var->transp.length = 0; | |
f413070e | 920 | var->nonstd = 0; |
4ed824d9 | 921 | break; |
1a2b750c MP |
922 | case 24: |
923 | var->red.offset = 16; | |
924 | var->red.length = 8; | |
925 | var->green.offset = 8; | |
926 | var->green.length = 8; | |
927 | var->blue.offset = 0; | |
928 | var->blue.length = 8; | |
929 | var->nonstd = 0; | |
930 | break; | |
931 | case 32: | |
932 | var->transp.offset = 24; | |
933 | var->transp.length = 8; | |
934 | var->red.offset = 16; | |
935 | var->red.length = 8; | |
936 | var->green.offset = 8; | |
937 | var->green.length = 8; | |
938 | var->blue.offset = 0; | |
939 | var->blue.length = 8; | |
940 | var->nonstd = 0; | |
941 | break; | |
4ed824d9 SR |
942 | default: |
943 | err = -EINVAL; | |
944 | } | |
945 | ||
946 | var->red.msb_right = 0; | |
947 | var->green.msb_right = 0; | |
948 | var->blue.msb_right = 0; | |
949 | var->transp.msb_right = 0; | |
87dac71d AM |
950 | |
951 | if (line_size * var->yres_virtual > par->vram_size) | |
952 | var->yres_virtual = par->vram_size / line_size; | |
953 | ||
954 | if (var->yres > var->yres_virtual) | |
955 | var->yres = var->yres_virtual; | |
956 | ||
957 | if (var->xres > var->xres_virtual) | |
958 | var->xres = var->xres_virtual; | |
959 | ||
960 | if (var->xres + var->xoffset > var->xres_virtual) | |
961 | var->xoffset = var->xres_virtual - var->xres; | |
962 | if (var->yres + var->yoffset > var->yres_virtual) | |
963 | var->yoffset = var->yres_virtual - var->yres; | |
964 | ||
4ed824d9 SR |
965 | return err; |
966 | } | |
967 | ||
e04e5483 C |
968 | #ifdef CONFIG_CPU_FREQ |
969 | static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb, | |
970 | unsigned long val, void *data) | |
971 | { | |
972 | struct da8xx_fb_par *par; | |
e04e5483 C |
973 | |
974 | par = container_of(nb, struct da8xx_fb_par, freq_transition); | |
f820917a MP |
975 | if (val == CPUFREQ_POSTCHANGE) { |
976 | if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) { | |
977 | par->lcd_fck_rate = clk_get_rate(par->lcdc_clk); | |
a481b37a | 978 | lcd_disable_raster(true); |
a6a799f8 | 979 | da8xx_fb_calc_config_clk_divider(par, &par->mode); |
67900814 MP |
980 | if (par->blank == FB_BLANK_UNBLANK) |
981 | lcd_enable_raster(); | |
f820917a | 982 | } |
e04e5483 C |
983 | } |
984 | ||
985 | return 0; | |
986 | } | |
987 | ||
988 | static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par) | |
989 | { | |
990 | par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition; | |
991 | ||
992 | return cpufreq_register_notifier(&par->freq_transition, | |
993 | CPUFREQ_TRANSITION_NOTIFIER); | |
994 | } | |
995 | ||
996 | static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par) | |
997 | { | |
998 | cpufreq_unregister_notifier(&par->freq_transition, | |
999 | CPUFREQ_TRANSITION_NOTIFIER); | |
1000 | } | |
1001 | #endif | |
1002 | ||
48c68c4f | 1003 | static int fb_remove(struct platform_device *dev) |
4ed824d9 SR |
1004 | { |
1005 | struct fb_info *info = dev_get_drvdata(&dev->dev); | |
4ed824d9 SR |
1006 | |
1007 | if (info) { | |
1008 | struct da8xx_fb_par *par = info->par; | |
1009 | ||
e04e5483 C |
1010 | #ifdef CONFIG_CPU_FREQ |
1011 | lcd_da8xx_cpufreq_deregister(par); | |
1012 | #endif | |
36113804 C |
1013 | if (par->panel_power_ctrl) |
1014 | par->panel_power_ctrl(0); | |
1015 | ||
a481b37a | 1016 | lcd_disable_raster(true); |
4ed824d9 SR |
1017 | lcdc_write(0, LCD_RASTER_CTRL_REG); |
1018 | ||
1019 | /* disable DMA */ | |
1020 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
1021 | ||
1022 | unregister_framebuffer(info); | |
1023 | fb_dealloc_cmap(&info->cmap); | |
1f9c3e1f MA |
1024 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, |
1025 | par->p_palette_base); | |
1026 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, | |
1027 | par->vram_phys); | |
4ed824d9 | 1028 | free_irq(par->irq, par); |
9dd44d5d MP |
1029 | pm_runtime_put_sync(&dev->dev); |
1030 | pm_runtime_disable(&dev->dev); | |
4ed824d9 | 1031 | framebuffer_release(info); |
34aef6eb | 1032 | iounmap(da8xx_fb_reg_base); |
4ed824d9 SR |
1033 | release_mem_region(lcdc_regs->start, resource_size(lcdc_regs)); |
1034 | ||
1035 | } | |
2f93e8f4 | 1036 | return 0; |
4ed824d9 SR |
1037 | } |
1038 | ||
1f9c3e1f MA |
1039 | /* |
1040 | * Function to wait for vertical sync which for this LCD peripheral | |
1041 | * translates into waiting for the current raster frame to complete. | |
1042 | */ | |
1043 | static int fb_wait_for_vsync(struct fb_info *info) | |
1044 | { | |
1045 | struct da8xx_fb_par *par = info->par; | |
1046 | int ret; | |
1047 | ||
1048 | /* | |
1049 | * Set flag to 0 and wait for isr to set to 1. It would seem there is a | |
25985edc | 1050 | * race condition here where the ISR could have occurred just before or |
1f9c3e1f MA |
1051 | * just after this set. But since we are just coarsely waiting for |
1052 | * a frame to complete then that's OK. i.e. if the frame completed | |
1053 | * just before this code executed then we have to wait another full | |
1054 | * frame time but there is no way to avoid such a situation. On the | |
1055 | * other hand if the frame completed just after then we don't need | |
1056 | * to wait long at all. Either way we are guaranteed to return to the | |
1057 | * user immediately after a frame completion which is all that is | |
1058 | * required. | |
1059 | */ | |
1060 | par->vsync_flag = 0; | |
1061 | ret = wait_event_interruptible_timeout(par->vsync_wait, | |
1062 | par->vsync_flag != 0, | |
1063 | par->vsync_timeout); | |
1064 | if (ret < 0) | |
1065 | return ret; | |
1066 | if (ret == 0) | |
1067 | return -ETIMEDOUT; | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
4ed824d9 SR |
1072 | static int fb_ioctl(struct fb_info *info, unsigned int cmd, |
1073 | unsigned long arg) | |
1074 | { | |
1075 | struct lcd_sync_arg sync_arg; | |
1076 | ||
1077 | switch (cmd) { | |
1078 | case FBIOGET_CONTRAST: | |
1079 | case FBIOPUT_CONTRAST: | |
1080 | case FBIGET_BRIGHTNESS: | |
1081 | case FBIPUT_BRIGHTNESS: | |
1082 | case FBIGET_COLOR: | |
1083 | case FBIPUT_COLOR: | |
2f93e8f4 | 1084 | return -ENOTTY; |
4ed824d9 SR |
1085 | case FBIPUT_HSYNC: |
1086 | if (copy_from_user(&sync_arg, (char *)arg, | |
1087 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1088 | return -EFAULT; |
4ed824d9 SR |
1089 | lcd_cfg_horizontal_sync(sync_arg.back_porch, |
1090 | sync_arg.pulse_width, | |
1091 | sync_arg.front_porch); | |
1092 | break; | |
1093 | case FBIPUT_VSYNC: | |
1094 | if (copy_from_user(&sync_arg, (char *)arg, | |
1095 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1096 | return -EFAULT; |
4ed824d9 SR |
1097 | lcd_cfg_vertical_sync(sync_arg.back_porch, |
1098 | sync_arg.pulse_width, | |
1099 | sync_arg.front_porch); | |
1100 | break; | |
1f9c3e1f MA |
1101 | case FBIO_WAITFORVSYNC: |
1102 | return fb_wait_for_vsync(info); | |
4ed824d9 SR |
1103 | default: |
1104 | return -EINVAL; | |
1105 | } | |
1106 | return 0; | |
1107 | } | |
1108 | ||
312d9715 C |
1109 | static int cfb_blank(int blank, struct fb_info *info) |
1110 | { | |
1111 | struct da8xx_fb_par *par = info->par; | |
1112 | int ret = 0; | |
1113 | ||
1114 | if (par->blank == blank) | |
1115 | return 0; | |
1116 | ||
1117 | par->blank = blank; | |
1118 | switch (blank) { | |
1119 | case FB_BLANK_UNBLANK: | |
f7c848b6 MP |
1120 | lcd_enable_raster(); |
1121 | ||
312d9715 C |
1122 | if (par->panel_power_ctrl) |
1123 | par->panel_power_ctrl(1); | |
312d9715 | 1124 | break; |
99a647d1 YY |
1125 | case FB_BLANK_NORMAL: |
1126 | case FB_BLANK_VSYNC_SUSPEND: | |
1127 | case FB_BLANK_HSYNC_SUSPEND: | |
312d9715 C |
1128 | case FB_BLANK_POWERDOWN: |
1129 | if (par->panel_power_ctrl) | |
1130 | par->panel_power_ctrl(0); | |
1131 | ||
a481b37a | 1132 | lcd_disable_raster(true); |
312d9715 C |
1133 | break; |
1134 | default: | |
1135 | ret = -EINVAL; | |
1136 | } | |
1137 | ||
1138 | return ret; | |
1139 | } | |
1140 | ||
1f9c3e1f MA |
1141 | /* |
1142 | * Set new x,y offsets in the virtual display for the visible area and switch | |
1143 | * to the new mode. | |
1144 | */ | |
1145 | static int da8xx_pan_display(struct fb_var_screeninfo *var, | |
1146 | struct fb_info *fbi) | |
1147 | { | |
1148 | int ret = 0; | |
1149 | struct fb_var_screeninfo new_var; | |
1150 | struct da8xx_fb_par *par = fbi->par; | |
1151 | struct fb_fix_screeninfo *fix = &fbi->fix; | |
1152 | unsigned int end; | |
1153 | unsigned int start; | |
deb95c6c | 1154 | unsigned long irq_flags; |
1f9c3e1f MA |
1155 | |
1156 | if (var->xoffset != fbi->var.xoffset || | |
1157 | var->yoffset != fbi->var.yoffset) { | |
1158 | memcpy(&new_var, &fbi->var, sizeof(new_var)); | |
1159 | new_var.xoffset = var->xoffset; | |
1160 | new_var.yoffset = var->yoffset; | |
1161 | if (fb_check_var(&new_var, fbi)) | |
1162 | ret = -EINVAL; | |
1163 | else { | |
1164 | memcpy(&fbi->var, &new_var, sizeof(new_var)); | |
1165 | ||
1166 | start = fix->smem_start + | |
1167 | new_var.yoffset * fix->line_length + | |
e6c4d3d4 LP |
1168 | new_var.xoffset * fbi->var.bits_per_pixel / 8; |
1169 | end = start + fbi->var.yres * fix->line_length - 1; | |
1f9c3e1f MA |
1170 | par->dma_start = start; |
1171 | par->dma_end = end; | |
deb95c6c MP |
1172 | spin_lock_irqsave(&par->lock_for_chan_update, |
1173 | irq_flags); | |
1174 | if (par->which_dma_channel_done == 0) { | |
1175 | lcdc_write(par->dma_start, | |
1176 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1177 | lcdc_write(par->dma_end, | |
1178 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1179 | } else if (par->which_dma_channel_done == 1) { | |
1180 | lcdc_write(par->dma_start, | |
1181 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1182 | lcdc_write(par->dma_end, | |
1183 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1184 | } | |
1185 | spin_unlock_irqrestore(&par->lock_for_chan_update, | |
1186 | irq_flags); | |
1f9c3e1f MA |
1187 | } |
1188 | } | |
1189 | ||
1190 | return ret; | |
1191 | } | |
1192 | ||
4ed824d9 SR |
1193 | static struct fb_ops da8xx_fb_ops = { |
1194 | .owner = THIS_MODULE, | |
1195 | .fb_check_var = fb_check_var, | |
1196 | .fb_setcolreg = fb_setcolreg, | |
1f9c3e1f | 1197 | .fb_pan_display = da8xx_pan_display, |
4ed824d9 SR |
1198 | .fb_ioctl = fb_ioctl, |
1199 | .fb_fillrect = cfb_fillrect, | |
1200 | .fb_copyarea = cfb_copyarea, | |
1201 | .fb_imageblit = cfb_imageblit, | |
312d9715 | 1202 | .fb_blank = cfb_blank, |
4ed824d9 SR |
1203 | }; |
1204 | ||
48c68c4f | 1205 | static int fb_probe(struct platform_device *device) |
4ed824d9 SR |
1206 | { |
1207 | struct da8xx_lcdc_platform_data *fb_pdata = | |
1208 | device->dev.platform_data; | |
1209 | struct lcd_ctrl_config *lcd_cfg; | |
f772fabd | 1210 | struct fb_videomode *lcdc_info; |
4ed824d9 SR |
1211 | struct fb_info *da8xx_fb_info; |
1212 | struct clk *fb_clk = NULL; | |
1213 | struct da8xx_fb_par *par; | |
1214 | resource_size_t len; | |
1215 | int ret, i; | |
3b9cc4ea | 1216 | unsigned long ulcm; |
4ed824d9 SR |
1217 | |
1218 | if (fb_pdata == NULL) { | |
1219 | dev_err(&device->dev, "Can not get platform data\n"); | |
1220 | return -ENOENT; | |
1221 | } | |
1222 | ||
1223 | lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0); | |
1224 | if (!lcdc_regs) { | |
1225 | dev_err(&device->dev, | |
1226 | "Can not get memory resource for LCD controller\n"); | |
1227 | return -ENOENT; | |
1228 | } | |
1229 | ||
1230 | len = resource_size(lcdc_regs); | |
1231 | ||
1232 | lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name); | |
1233 | if (!lcdc_regs) | |
1234 | return -EBUSY; | |
1235 | ||
34aef6eb | 1236 | da8xx_fb_reg_base = ioremap(lcdc_regs->start, len); |
4ed824d9 SR |
1237 | if (!da8xx_fb_reg_base) { |
1238 | ret = -EBUSY; | |
1239 | goto err_request_mem; | |
1240 | } | |
1241 | ||
81cec3c7 | 1242 | fb_clk = clk_get(&device->dev, "fck"); |
4ed824d9 SR |
1243 | if (IS_ERR(fb_clk)) { |
1244 | dev_err(&device->dev, "Can not get device clock\n"); | |
1245 | ret = -ENODEV; | |
1246 | goto err_ioremap; | |
1247 | } | |
9dd44d5d MP |
1248 | |
1249 | pm_runtime_enable(&device->dev); | |
1250 | pm_runtime_get_sync(&device->dev); | |
4ed824d9 | 1251 | |
c6daf05b MP |
1252 | /* Determine LCD IP Version */ |
1253 | switch (lcdc_read(LCD_PID_REG)) { | |
1254 | case 0x4C100102: | |
1255 | lcd_revision = LCD_VERSION_1; | |
1256 | break; | |
1257 | case 0x4F200800: | |
8f22e8ea | 1258 | case 0x4F201000: |
c6daf05b MP |
1259 | lcd_revision = LCD_VERSION_2; |
1260 | break; | |
1261 | default: | |
1262 | dev_warn(&device->dev, "Unknown PID Reg value 0x%x, " | |
1263 | "defaulting to LCD revision 1\n", | |
1264 | lcdc_read(LCD_PID_REG)); | |
1265 | lcd_revision = LCD_VERSION_1; | |
1266 | break; | |
1267 | } | |
1268 | ||
4ed824d9 SR |
1269 | for (i = 0, lcdc_info = known_lcd_panels; |
1270 | i < ARRAY_SIZE(known_lcd_panels); | |
1271 | i++, lcdc_info++) { | |
1272 | if (strcmp(fb_pdata->type, lcdc_info->name) == 0) | |
1273 | break; | |
1274 | } | |
1275 | ||
1276 | if (i == ARRAY_SIZE(known_lcd_panels)) { | |
1277 | dev_err(&device->dev, "GLCD: No valid panel found\n"); | |
dd04a6b3 | 1278 | ret = -ENODEV; |
9dd44d5d | 1279 | goto err_pm_runtime_disable; |
4ed824d9 SR |
1280 | } else |
1281 | dev_info(&device->dev, "GLCD: Found %s panel\n", | |
1282 | fb_pdata->type); | |
1283 | ||
1284 | lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data; | |
1285 | ||
1286 | da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par), | |
1287 | &device->dev); | |
1288 | if (!da8xx_fb_info) { | |
1289 | dev_dbg(&device->dev, "Memory allocation failed for fb_info\n"); | |
1290 | ret = -ENOMEM; | |
9dd44d5d | 1291 | goto err_pm_runtime_disable; |
4ed824d9 SR |
1292 | } |
1293 | ||
1294 | par = da8xx_fb_info->par; | |
dbe8e48a | 1295 | par->dev = &device->dev; |
8097b174 | 1296 | par->lcdc_clk = fb_clk; |
f820917a | 1297 | par->lcd_fck_rate = clk_get_rate(fb_clk); |
36113804 C |
1298 | if (fb_pdata->panel_power_ctrl) { |
1299 | par->panel_power_ctrl = fb_pdata->panel_power_ctrl; | |
1300 | par->panel_power_ctrl(1); | |
1301 | } | |
4ed824d9 | 1302 | |
b866458b | 1303 | fb_videomode_to_var(&da8xx_fb_var, lcdc_info); |
b6dbe8e4 AM |
1304 | fb_var_to_videomode(&par->mode, &da8xx_fb_var); |
1305 | par->cfg = *lcd_cfg; | |
b866458b | 1306 | |
4ed824d9 SR |
1307 | if (lcd_init(par, lcd_cfg, lcdc_info) < 0) { |
1308 | dev_err(&device->dev, "lcd_init failed\n"); | |
1309 | ret = -EFAULT; | |
1310 | goto err_release_fb; | |
1311 | } | |
1312 | ||
1313 | /* allocate frame buffer */ | |
f772fabd MP |
1314 | par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp; |
1315 | ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE); | |
3b9cc4ea | 1316 | par->vram_size = roundup(par->vram_size/8, ulcm); |
1f9c3e1f MA |
1317 | par->vram_size = par->vram_size * LCD_NUM_BUFFERS; |
1318 | ||
1319 | par->vram_virt = dma_alloc_coherent(NULL, | |
1320 | par->vram_size, | |
1321 | (resource_size_t *) &par->vram_phys, | |
1322 | GFP_KERNEL | GFP_DMA); | |
1323 | if (!par->vram_virt) { | |
4ed824d9 SR |
1324 | dev_err(&device->dev, |
1325 | "GLCD: kmalloc for frame buffer failed\n"); | |
1326 | ret = -EINVAL; | |
1327 | goto err_release_fb; | |
1328 | } | |
1329 | ||
1f9c3e1f MA |
1330 | da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt; |
1331 | da8xx_fb_fix.smem_start = par->vram_phys; | |
1332 | da8xx_fb_fix.smem_len = par->vram_size; | |
f772fabd | 1333 | da8xx_fb_fix.line_length = (lcdc_info->xres * lcd_cfg->bpp) / 8; |
1f9c3e1f MA |
1334 | |
1335 | par->dma_start = par->vram_phys; | |
f772fabd | 1336 | par->dma_end = par->dma_start + lcdc_info->yres * |
1f9c3e1f MA |
1337 | da8xx_fb_fix.line_length - 1; |
1338 | ||
1339 | /* allocate palette buffer */ | |
1340 | par->v_palette_base = dma_alloc_coherent(NULL, | |
1341 | PALETTE_SIZE, | |
1342 | (resource_size_t *) | |
1343 | &par->p_palette_base, | |
1344 | GFP_KERNEL | GFP_DMA); | |
1345 | if (!par->v_palette_base) { | |
1346 | dev_err(&device->dev, | |
1347 | "GLCD: kmalloc for palette buffer failed\n"); | |
1348 | ret = -EINVAL; | |
1349 | goto err_release_fb_mem; | |
1350 | } | |
1351 | memset(par->v_palette_base, 0, PALETTE_SIZE); | |
4ed824d9 | 1352 | |
4ed824d9 SR |
1353 | par->irq = platform_get_irq(device, 0); |
1354 | if (par->irq < 0) { | |
1355 | ret = -ENOENT; | |
1f9c3e1f | 1356 | goto err_release_pl_mem; |
4ed824d9 SR |
1357 | } |
1358 | ||
4ed824d9 | 1359 | da8xx_fb_var.grayscale = |
3b43ad20 | 1360 | lcd_cfg->panel_shade == MONOCHROME ? 1 : 0; |
4ed824d9 | 1361 | da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; |
4ed824d9 SR |
1362 | |
1363 | /* Initialize fbinfo */ | |
1364 | da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; | |
1365 | da8xx_fb_info->fix = da8xx_fb_fix; | |
1366 | da8xx_fb_info->var = da8xx_fb_var; | |
1367 | da8xx_fb_info->fbops = &da8xx_fb_ops; | |
1368 | da8xx_fb_info->pseudo_palette = par->pseudo_palette; | |
3510b8f7 SR |
1369 | da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? |
1370 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
4ed824d9 SR |
1371 | |
1372 | ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0); | |
1373 | if (ret) | |
93c176f3 | 1374 | goto err_release_pl_mem; |
4ed824d9 SR |
1375 | da8xx_fb_info->cmap.len = par->palette_sz; |
1376 | ||
4ed824d9 SR |
1377 | /* initialize var_screeninfo */ |
1378 | da8xx_fb_var.activate = FB_ACTIVATE_FORCE; | |
1379 | fb_set_var(da8xx_fb_info, &da8xx_fb_var); | |
1380 | ||
1381 | dev_set_drvdata(&device->dev, da8xx_fb_info); | |
1f9c3e1f MA |
1382 | |
1383 | /* initialize the vsync wait queue */ | |
1384 | init_waitqueue_head(&par->vsync_wait); | |
1385 | par->vsync_timeout = HZ / 5; | |
deb95c6c MP |
1386 | par->which_dma_channel_done = -1; |
1387 | spin_lock_init(&par->lock_for_chan_update); | |
1f9c3e1f | 1388 | |
4ed824d9 SR |
1389 | /* Register the Frame Buffer */ |
1390 | if (register_framebuffer(da8xx_fb_info) < 0) { | |
1391 | dev_err(&device->dev, | |
1392 | "GLCD: Frame Buffer Registration Failed!\n"); | |
1393 | ret = -EINVAL; | |
1394 | goto err_dealloc_cmap; | |
1395 | } | |
1396 | ||
e04e5483 C |
1397 | #ifdef CONFIG_CPU_FREQ |
1398 | ret = lcd_da8xx_cpufreq_register(par); | |
1399 | if (ret) { | |
1400 | dev_err(&device->dev, "failed to register cpufreq\n"); | |
1401 | goto err_cpu_freq; | |
1402 | } | |
1403 | #endif | |
93c176f3 | 1404 | |
c6daf05b MP |
1405 | if (lcd_revision == LCD_VERSION_1) |
1406 | lcdc_irq_handler = lcdc_irq_handler_rev01; | |
a481b37a MP |
1407 | else { |
1408 | init_waitqueue_head(&frame_done_wq); | |
c6daf05b | 1409 | lcdc_irq_handler = lcdc_irq_handler_rev02; |
a481b37a | 1410 | } |
c6daf05b MP |
1411 | |
1412 | ret = request_irq(par->irq, lcdc_irq_handler, 0, | |
1413 | DRIVER_NAME, par); | |
93c176f3 CA |
1414 | if (ret) |
1415 | goto irq_freq; | |
4ed824d9 SR |
1416 | return 0; |
1417 | ||
93c176f3 | 1418 | irq_freq: |
e04e5483 | 1419 | #ifdef CONFIG_CPU_FREQ |
360c202b | 1420 | lcd_da8xx_cpufreq_deregister(par); |
e04e5483 | 1421 | err_cpu_freq: |
3a84409c | 1422 | #endif |
e04e5483 | 1423 | unregister_framebuffer(da8xx_fb_info); |
e04e5483 | 1424 | |
4ed824d9 SR |
1425 | err_dealloc_cmap: |
1426 | fb_dealloc_cmap(&da8xx_fb_info->cmap); | |
1427 | ||
1f9c3e1f MA |
1428 | err_release_pl_mem: |
1429 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, | |
1430 | par->p_palette_base); | |
1431 | ||
4ed824d9 | 1432 | err_release_fb_mem: |
1f9c3e1f | 1433 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys); |
4ed824d9 SR |
1434 | |
1435 | err_release_fb: | |
1436 | framebuffer_release(da8xx_fb_info); | |
1437 | ||
9dd44d5d MP |
1438 | err_pm_runtime_disable: |
1439 | pm_runtime_put_sync(&device->dev); | |
1440 | pm_runtime_disable(&device->dev); | |
4ed824d9 SR |
1441 | |
1442 | err_ioremap: | |
34aef6eb | 1443 | iounmap(da8xx_fb_reg_base); |
4ed824d9 SR |
1444 | |
1445 | err_request_mem: | |
1446 | release_mem_region(lcdc_regs->start, len); | |
1447 | ||
1448 | return ret; | |
1449 | } | |
1450 | ||
1451 | #ifdef CONFIG_PM | |
7a93cbbb MP |
1452 | struct lcdc_context { |
1453 | u32 clk_enable; | |
1454 | u32 ctrl; | |
1455 | u32 dma_ctrl; | |
1456 | u32 raster_timing_0; | |
1457 | u32 raster_timing_1; | |
1458 | u32 raster_timing_2; | |
1459 | u32 int_enable_set; | |
1460 | u32 dma_frm_buf_base_addr_0; | |
1461 | u32 dma_frm_buf_ceiling_addr_0; | |
1462 | u32 dma_frm_buf_base_addr_1; | |
1463 | u32 dma_frm_buf_ceiling_addr_1; | |
1464 | u32 raster_ctrl; | |
1465 | } reg_context; | |
1466 | ||
1467 | static void lcd_context_save(void) | |
1468 | { | |
1469 | if (lcd_revision == LCD_VERSION_2) { | |
1470 | reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG); | |
1471 | reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG); | |
1472 | } | |
1473 | ||
1474 | reg_context.ctrl = lcdc_read(LCD_CTRL_REG); | |
1475 | reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG); | |
1476 | reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG); | |
1477 | reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG); | |
1478 | reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
1479 | reg_context.dma_frm_buf_base_addr_0 = | |
1480 | lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1481 | reg_context.dma_frm_buf_ceiling_addr_0 = | |
1482 | lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1483 | reg_context.dma_frm_buf_base_addr_1 = | |
1484 | lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1485 | reg_context.dma_frm_buf_ceiling_addr_1 = | |
1486 | lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1487 | reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG); | |
1488 | return; | |
1489 | } | |
1490 | ||
1491 | static void lcd_context_restore(void) | |
1492 | { | |
1493 | if (lcd_revision == LCD_VERSION_2) { | |
1494 | lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG); | |
1495 | lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG); | |
1496 | } | |
1497 | ||
1498 | lcdc_write(reg_context.ctrl, LCD_CTRL_REG); | |
1499 | lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG); | |
1500 | lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG); | |
1501 | lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG); | |
1502 | lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG); | |
1503 | lcdc_write(reg_context.dma_frm_buf_base_addr_0, | |
1504 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1505 | lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0, | |
1506 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1507 | lcdc_write(reg_context.dma_frm_buf_base_addr_1, | |
1508 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1509 | lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1, | |
1510 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1511 | lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG); | |
1512 | return; | |
1513 | } | |
1514 | ||
4ed824d9 SR |
1515 | static int fb_suspend(struct platform_device *dev, pm_message_t state) |
1516 | { | |
1d3c6c7b C |
1517 | struct fb_info *info = platform_get_drvdata(dev); |
1518 | struct da8xx_fb_par *par = info->par; | |
1519 | ||
ac751efa | 1520 | console_lock(); |
1d3c6c7b C |
1521 | if (par->panel_power_ctrl) |
1522 | par->panel_power_ctrl(0); | |
1523 | ||
1524 | fb_set_suspend(info, 1); | |
a481b37a | 1525 | lcd_disable_raster(true); |
7a93cbbb | 1526 | lcd_context_save(); |
9dd44d5d | 1527 | pm_runtime_put_sync(&dev->dev); |
ac751efa | 1528 | console_unlock(); |
1d3c6c7b C |
1529 | |
1530 | return 0; | |
4ed824d9 SR |
1531 | } |
1532 | static int fb_resume(struct platform_device *dev) | |
1533 | { | |
1d3c6c7b C |
1534 | struct fb_info *info = platform_get_drvdata(dev); |
1535 | struct da8xx_fb_par *par = info->par; | |
1536 | ||
ac751efa | 1537 | console_lock(); |
9dd44d5d | 1538 | pm_runtime_get_sync(&dev->dev); |
7a93cbbb | 1539 | lcd_context_restore(); |
67900814 MP |
1540 | if (par->blank == FB_BLANK_UNBLANK) { |
1541 | lcd_enable_raster(); | |
f7c848b6 | 1542 | |
67900814 MP |
1543 | if (par->panel_power_ctrl) |
1544 | par->panel_power_ctrl(1); | |
1545 | } | |
1d3c6c7b | 1546 | |
1d3c6c7b | 1547 | fb_set_suspend(info, 0); |
ac751efa | 1548 | console_unlock(); |
1d3c6c7b C |
1549 | |
1550 | return 0; | |
4ed824d9 SR |
1551 | } |
1552 | #else | |
1553 | #define fb_suspend NULL | |
1554 | #define fb_resume NULL | |
1555 | #endif | |
1556 | ||
1557 | static struct platform_driver da8xx_fb_driver = { | |
1558 | .probe = fb_probe, | |
48c68c4f | 1559 | .remove = fb_remove, |
4ed824d9 SR |
1560 | .suspend = fb_suspend, |
1561 | .resume = fb_resume, | |
1562 | .driver = { | |
1563 | .name = DRIVER_NAME, | |
1564 | .owner = THIS_MODULE, | |
1565 | }, | |
1566 | }; | |
1567 | ||
1568 | static int __init da8xx_fb_init(void) | |
1569 | { | |
1570 | return platform_driver_register(&da8xx_fb_driver); | |
1571 | } | |
1572 | ||
1573 | static void __exit da8xx_fb_cleanup(void) | |
1574 | { | |
1575 | platform_driver_unregister(&da8xx_fb_driver); | |
1576 | } | |
1577 | ||
1578 | module_init(da8xx_fb_init); | |
1579 | module_exit(da8xx_fb_cleanup); | |
1580 | ||
1581 | MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx"); | |
1582 | MODULE_AUTHOR("Texas Instruments"); | |
1583 | MODULE_LICENSE("GPL"); |