[mirror_ubuntu-bionic-kernel.git] / drivers / video / exynos / exynos_dp_core.h

/*
 * Header file for Samsung DP (Display Port) interface driver.
 *
 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
 * Author: Jingoo Han <jg1.han@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#ifndef _EXYNOS_DP_CORE_H
#define _EXYNOS_DP_CORE_H

struct link_train {
	int eq_loop;
	int cr_loop[4];

	u8 link_rate;
	u8 lane_count;
	u8 training_lane[4];

	enum link_training_state lt_state;
};

struct exynos_dp_device {
	struct device		*dev;
	struct clk		*clock;
	unsigned int		irq;
	void __iomem		*reg_base;

	struct video_info	*video_info;
	struct link_train	link_train;
};

/* exynos_dp_reg.c */
void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
void exynos_dp_stop_video(struct exynos_dp_device *dp);
void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
void exynos_dp_reset(struct exynos_dp_device *dp);
void exynos_dp_swreset(struct exynos_dp_device *dp);
void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
				enum analog_power_block block,
				bool enable);
void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
void exynos_dp_init_hpd(struct exynos_dp_device *dp);
void exynos_dp_reset_aux(struct exynos_dp_device *dp);
void exynos_dp_init_aux(struct exynos_dp_device *dp);
int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
				unsigned int reg_addr,
				unsigned char data);
int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
				unsigned int reg_addr,
				unsigned char *data);
int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
				unsigned int reg_addr,
				unsigned int count,
				unsigned char data[]);
int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
				unsigned int reg_addr,
				unsigned int count,
				unsigned char data[]);
int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
				unsigned int device_addr,
				unsigned int reg_addr);
int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
				unsigned int device_addr,
				unsigned int reg_addr,
				unsigned int *data);
int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
				unsigned int device_addr,
				unsigned int reg_addr,
				unsigned int count,
				unsigned char edid[]);
void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
				 enum pattern_set pattern);
void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
				u32 training_lane);
void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
				u32 training_lane);
void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
				u32 training_lane);
void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
				u32 training_lane);
u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
void exynos_dp_reset_macro(struct exynos_dp_device *dp);
void exynos_dp_init_video(struct exynos_dp_device *dp);

void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
				u32 color_depth,
				u32 color_space,
				u32 dynamic_range,
				u32 ycbcr_coeff);
int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
			enum clock_recovery_m_value_type type,
			u32 m_value,
			u32 n_value);
void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
void exynos_dp_start_video(struct exynos_dp_device *dp);
int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
			struct video_info *video_info);
void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);

/* I2C EDID Chip ID, Slave Address */
#define I2C_EDID_DEVICE_ADDR			0x50
#define I2C_E_EDID_DEVICE_ADDR			0x30

#define EDID_BLOCK_LENGTH			0x80
#define EDID_HEADER_PATTERN			0x00
#define EDID_EXTENSION_FLAG			0x7e
#define EDID_CHECKSUM				0x7f

/* Definition for DPCD Register */
#define DPCD_ADDR_DPCD_REV			0x0000
#define DPCD_ADDR_MAX_LINK_RATE			0x0001
#define DPCD_ADDR_MAX_LANE_COUNT		0x0002
#define DPCD_ADDR_LINK_BW_SET			0x0100
#define DPCD_ADDR_LANE_COUNT_SET		0x0101
#define DPCD_ADDR_TRAINING_PATTERN_SET		0x0102
#define DPCD_ADDR_TRAINING_LANE0_SET		0x0103
#define DPCD_ADDR_LANE0_1_STATUS		0x0202
#define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED	0x0204
#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1	0x0206
#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3	0x0207
#define DPCD_ADDR_TEST_REQUEST			0x0218
#define DPCD_ADDR_TEST_RESPONSE			0x0260
#define DPCD_ADDR_TEST_EDID_CHECKSUM		0x0261
#define DPCD_ADDR_SINK_POWER_STATE		0x0600

/* DPCD_ADDR_MAX_LANE_COUNT */
#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)

/* DPCD_ADDR_LANE_COUNT_SET */
#define DPCD_ENHANCED_FRAME_EN			(0x1 << 7)
#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)

/* DPCD_ADDR_TRAINING_PATTERN_SET */
#define DPCD_SCRAMBLING_DISABLED		(0x1 << 5)
#define DPCD_SCRAMBLING_ENABLED			(0x0 << 5)
#define DPCD_TRAINING_PATTERN_2			(0x2 << 0)
#define DPCD_TRAINING_PATTERN_1			(0x1 << 0)
#define DPCD_TRAINING_PATTERN_DISABLED		(0x0 << 0)

/* DPCD_ADDR_TRAINING_LANE0_SET */
#define DPCD_MAX_PRE_EMPHASIS_REACHED		(0x1 << 5)
#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0	(0x0 << 3)
#define DPCD_MAX_SWING_REACHED			(0x1 << 2)
#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0	(0x0 << 0)

/* DPCD_ADDR_LANE0_1_STATUS */
#define DPCD_LANE_SYMBOL_LOCKED			(0x1 << 2)
#define DPCD_LANE_CHANNEL_EQ_DONE		(0x1 << 1)
#define DPCD_LANE_CR_DONE			(0x1 << 0)
#define DPCD_CHANNEL_EQ_BITS			(DPCD_LANE_CR_DONE|	\
						 DPCD_LANE_CHANNEL_EQ_DONE|\
						 DPCD_LANE_SYMBOL_LOCKED)

/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
#define DPCD_LINK_STATUS_UPDATED		(0x1 << 7)
#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED	(0x1 << 6)
#define DPCD_INTERLANE_ALIGN_DONE		(0x1 << 0)

/* DPCD_ADDR_TEST_REQUEST */
#define DPCD_TEST_EDID_READ			(0x1 << 2)

/* DPCD_ADDR_TEST_RESPONSE */
#define DPCD_TEST_EDID_CHECKSUM_WRITE		(0x1 << 2)

/* DPCD_ADDR_SINK_POWER_STATE */
#define DPCD_SET_POWER_STATE_D0			(0x1 << 0)
#define DPCD_SET_POWER_STATE_D4			(0x2 << 0)

#endif /* _EXYNOS_DP_CORE_H */
Commit	Line	Data
e9474be4 JH	1	/*
	2	* Header file for Samsung DP (Display Port) interface driver.
	3	*
	4	* Copyright (C) 2012 Samsung Electronics Co., Ltd.
	5	* Author: Jingoo Han <jg1.han@samsung.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*/
	12
	13	#ifndef _EXYNOS_DP_CORE_H
	14	#define _EXYNOS_DP_CORE_H
	15
	16	struct link_train {
	17	int eq_loop;
	18	int cr_loop[4];
	19
	20	u8 link_rate;
	21	u8 lane_count;
	22	u8 training_lane[4];
	23
	24	enum link_training_state lt_state;
	25	};
	26
	27	struct exynos_dp_device {
	28	struct device *dev;
e9474be4 JH	29	struct clk *clock;
	30	unsigned int irq;
	31	void __iomem *reg_base;
	32
	33	struct video_info *video_info;
	34	struct link_train link_train;
	35	};
	36
	37	/* exynos_dp_reg.c */
	38	void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
	39	void exynos_dp_stop_video(struct exynos_dp_device *dp);
	40	void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
8affaf5c	41	void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
e9474be4 JH	42	void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
e9474be4 JH	43	void exynos_dp_reset(struct exynos_dp_device *dp);
24db03a8	44	void exynos_dp_swreset(struct exynos_dp_device *dp);
e9474be4	45	void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
09d00d17	46	enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
e9474be4 JH	47	void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
	48	void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
	49	enum analog_power_block block,
	50	bool enable);
	51	void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
	52	void exynos_dp_init_hpd(struct exynos_dp_device *dp);
	53	void exynos_dp_reset_aux(struct exynos_dp_device *dp);
	54	void exynos_dp_init_aux(struct exynos_dp_device *dp);
	55	int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
	56	void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
	57	int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
	58	int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
	59	unsigned int reg_addr,
	60	unsigned char data);
	61	int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
	62	unsigned int reg_addr,
	63	unsigned char *data);
	64	int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
	65	unsigned int reg_addr,
	66	unsigned int count,
	67	unsigned char data[]);
	68	int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
	69	unsigned int reg_addr,
	70	unsigned int count,
	71	unsigned char data[]);
	72	int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
	73	unsigned int device_addr,
	74	unsigned int reg_addr);
	75	int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
	76	unsigned int device_addr,
	77	unsigned int reg_addr,
	78	unsigned int *data);
	79	int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
	80	unsigned int device_addr,
	81	unsigned int reg_addr,
	82	unsigned int count,
	83	unsigned char edid[]);
	84	void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
	85	void exynos_dp_get_link_bandwidth(struct exynos_dp_device dp, u32 bwtype);
	86	void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
	87	void exynos_dp_get_lane_count(struct exynos_dp_device dp, u32 count);
e9474be4 JH	88	void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
	89	void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
	90	enum pattern_set pattern);
	91	void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
	92	void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
	93	void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
	94	void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
	95	void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
	96	u32 training_lane);
	97	void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
	98	u32 training_lane);
	99	void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
	100	u32 training_lane);
	101	void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
	102	u32 training_lane);
	103	u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
	104	u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
	105	u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
	106	u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
	107	void exynos_dp_reset_macro(struct exynos_dp_device *dp);
1ec7be9c	108	void exynos_dp_init_video(struct exynos_dp_device *dp);
e9474be4 JH	109
	110	void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
	111	u32 color_depth,
	112	u32 color_space,
	113	u32 dynamic_range,
	114	u32 ycbcr_coeff);
	115	int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
	116	void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
	117	enum clock_recovery_m_value_type type,
	118	u32 m_value,
	119	u32 n_value);
	120	void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
	121	void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
	122	void exynos_dp_start_video(struct exynos_dp_device *dp);
	123	int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
	124	void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
	125	struct video_info *video_info);
	126	void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
	127	void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
	128
	129	/* I2C EDID Chip ID, Slave Address */
	130	#define I2C_EDID_DEVICE_ADDR 0x50
	131	#define I2C_E_EDID_DEVICE_ADDR 0x30
	132
	133	#define EDID_BLOCK_LENGTH 0x80
	134	#define EDID_HEADER_PATTERN 0x00
	135	#define EDID_EXTENSION_FLAG 0x7e
	136	#define EDID_CHECKSUM 0x7f
	137
	138	/* Definition for DPCD Register */
	139	#define DPCD_ADDR_DPCD_REV 0x0000
	140	#define DPCD_ADDR_MAX_LINK_RATE 0x0001
	141	#define DPCD_ADDR_MAX_LANE_COUNT 0x0002
	142	#define DPCD_ADDR_LINK_BW_SET 0x0100
	143	#define DPCD_ADDR_LANE_COUNT_SET 0x0101
	144	#define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
	145	#define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
	146	#define DPCD_ADDR_LANE0_1_STATUS 0x0202
d5c0eed0	147	#define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x0204
e9474be4 JH	148	#define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
	149	#define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
	150	#define DPCD_ADDR_TEST_REQUEST 0x0218
	151	#define DPCD_ADDR_TEST_RESPONSE 0x0260
	152	#define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
	153	#define DPCD_ADDR_SINK_POWER_STATE 0x0600
	154
	155	/* DPCD_ADDR_MAX_LANE_COUNT */
	156	#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
	157	#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
	158
	159	/* DPCD_ADDR_LANE_COUNT_SET */
	160	#define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
	161	#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
	162
	163	/* DPCD_ADDR_TRAINING_PATTERN_SET */
	164	#define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
	165	#define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
	166	#define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
	167	#define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
	168	#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
	169
	170	/* DPCD_ADDR_TRAINING_LANE0_SET */
	171	#define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
	172	#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
	173	#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
	174	#define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
	175	#define DPCD_MAX_SWING_REACHED (0x1 << 2)
	176	#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
	177	#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
	178	#define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
	179
	180	/* DPCD_ADDR_LANE0_1_STATUS */
	181	#define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
	182	#define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
	183	#define DPCD_LANE_CR_DONE (0x1 << 0)
	184	#define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE\| \
	185	DPCD_LANE_CHANNEL_EQ_DONE\|\
	186	DPCD_LANE_SYMBOL_LOCKED)
	187
	188	/* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
	189	#define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
	190	#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
	191	#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
	192
	193	/* DPCD_ADDR_TEST_REQUEST */
	194	#define DPCD_TEST_EDID_READ (0x1 << 2)
	195
	196	/* DPCD_ADDR_TEST_RESPONSE */
	197	#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
	198
	199	/* DPCD_ADDR_SINK_POWER_STATE */
	200	#define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
	201	#define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
	202
	203	#endif /* _EXYNOS_DP_CORE_H */