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video: exynos_dp: Fix get_pll_lock_status return value
[mirror_ubuntu-artful-kernel.git] / drivers / video / exynos / exynos_dp_reg.c
CommitLineData
e9474be4
JH		 1/*
2 * Samsung DP (Display port) register interface driver.
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/device.h>
14#include <linux/io.h>
15#include <linux/delay.h>
16
17#include <video/exynos_dp.h>
18
e9474be4
JH		 19#include "exynos_dp_core.h"
20#include "exynos_dp_reg.h"
21
22#define COMMON_INT_MASK_1 (0)
23#define COMMON_INT_MASK_2 (0)
24#define COMMON_INT_MASK_3 (0)
25#define COMMON_INT_MASK_4 (0)
26#define INT_STA_MASK (0)
27
28void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
29{
30 u32 reg;
31
32 if (enable) {
33 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
34 reg |= HDCP_VIDEO_MUTE;
35 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
36 } else {
37 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
38 reg &= ~HDCP_VIDEO_MUTE;
39 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
40 }
41}
42
43void exynos_dp_stop_video(struct exynos_dp_device *dp)
44{
45 u32 reg;
46
47 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
48 reg &= ~VIDEO_EN;
49 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
50}
51
52void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
53{
54 u32 reg;
55
56 if (enable)
57 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
58 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
59 else
60 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
61 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
62
63 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
64}
65
8affaf5c
JH		 66void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
67{
68 u32 reg;
69
70 reg = TX_TERMINAL_CTRL_50_OHM;
71 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
72
73 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
74 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
75
76 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
77 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
78
79 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
80 TX_CUR1_2X | TX_CUR_8_MA;
81 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
82
83 reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
84 CH1_AMP_400_MV | CH0_AMP_400_MV;
85 writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
86}
87
e9474be4
JH		 88void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
89{
90 /* Set interrupt pin assertion polarity as high */
91 writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL);
92
93 /* Clear pending regisers */
94 writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
95 writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
96 writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
97 writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
98 writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
99
100 /* 0:mask,1: unmask */
101 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
102 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
103 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
104 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
105 writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
106}
107
108void exynos_dp_reset(struct exynos_dp_device *dp)
109{
110 u32 reg;
111
e9474be4
JH		 112 exynos_dp_stop_video(dp);
113 exynos_dp_enable_video_mute(dp, 0);
114
115 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
116 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
117 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
118 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
119
120 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
121 SERDES_FIFO_FUNC_EN_N |
122 LS_CLK_DOMAIN_FUNC_EN_N;
123 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
124
a2c81bc1 125 usleep_range(20, 30);
e9474be4
JH		 126
127 exynos_dp_lane_swap(dp, 0);
128
129 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
130 writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
131 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
132 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
133
134 writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
135 writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
136
137 writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
138 writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
139
140 writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
141
142 writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
143
144 writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
145 writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
146
147 writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
148 writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
149
150 writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
151
8affaf5c 152 exynos_dp_init_analog_param(dp);
e9474be4
JH		 153 exynos_dp_init_interrupt(dp);
154}
155
24db03a8
JH		 156void exynos_dp_swreset(struct exynos_dp_device *dp)
157{
158 writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
159}
160
e9474be4
JH		 161void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
162{
163 u32 reg;
164
165 /* 0: mask, 1: unmask */
166 reg = COMMON_INT_MASK_1;
167 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
168
169 reg = COMMON_INT_MASK_2;
170 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
171
172 reg = COMMON_INT_MASK_3;
173 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
174
175 reg = COMMON_INT_MASK_4;
176 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
177
178 reg = INT_STA_MASK;
179 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
180}
181
09d00d17 182enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
e9474be4
JH		 183{
184 u32 reg;
185
186 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
187 if (reg & PLL_LOCK)
188 return PLL_LOCKED;
189 else
190 return PLL_UNLOCKED;
191}
192
193void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
194{
195 u32 reg;
196
197 if (enable) {
198 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
199 reg |= DP_PLL_PD;
200 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
201 } else {
202 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
203 reg &= ~DP_PLL_PD;
204 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
205 }
206}
207
208void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
209 enum analog_power_block block,
210 bool enable)
211{
212 u32 reg;
213
214 switch (block) {
215 case AUX_BLOCK:
216 if (enable) {
217 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
218 reg |= AUX_PD;
219 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
220 } else {
221 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
222 reg &= ~AUX_PD;
223 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
224 }
225 break;
226 case CH0_BLOCK:
227 if (enable) {
228 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
229 reg |= CH0_PD;
230 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
231 } else {
232 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
233 reg &= ~CH0_PD;
234 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
235 }
236 break;
237 case CH1_BLOCK:
238 if (enable) {
239 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
240 reg |= CH1_PD;
241 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
242 } else {
243 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
244 reg &= ~CH1_PD;
245 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
246 }
247 break;
248 case CH2_BLOCK:
249 if (enable) {
250 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
251 reg |= CH2_PD;
252 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
253 } else {
254 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
255 reg &= ~CH2_PD;
256 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
257 }
258 break;
259 case CH3_BLOCK:
260 if (enable) {
261 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
262 reg |= CH3_PD;
263 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
264 } else {
265 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
266 reg &= ~CH3_PD;
267 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
268 }
269 break;
270 case ANALOG_TOTAL:
271 if (enable) {
272 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
273 reg |= DP_PHY_PD;
274 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
275 } else {
276 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
277 reg &= ~DP_PHY_PD;
278 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
279 }
280 break;
281 case POWER_ALL:
282 if (enable) {
283 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
284 CH1_PD | CH0_PD;
285 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
286 } else {
287 writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
288 }
289 break;
290 default:
291 break;
292 }
293}
294
295void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
296{
297 u32 reg;
b5cfeed6 298 int timeout_loop = 0;
e9474be4
JH		 299
300 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
301
302 reg = PLL_LOCK_CHG;
303 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
304
305 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
306 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
307 writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
308
309 /* Power up PLL */
b5cfeed6 310 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
e9474be4
JH		 311 exynos_dp_set_pll_power_down(dp, 0);
312
b5cfeed6
JH		 313 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
314 timeout_loop++;
315 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
316 dev_err(dp->dev, "failed to get pll lock status\n");
317 return;
318 }
319 usleep_range(10, 20);
320 }
321 }
322
e9474be4
JH		 323 /* Enable Serdes FIFO function and Link symbol clock domain module */
324 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
325 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
326 | AUX_FUNC_EN_N);
327 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
328}
329
330void exynos_dp_init_hpd(struct exynos_dp_device *dp)
331{
332 u32 reg;
333
334 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
335 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
336
337 reg = INT_HPD;
338 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
339
340 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
341 reg &= ~(F_HPD | HPD_CTRL);
342 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
343}
344
345void exynos_dp_reset_aux(struct exynos_dp_device *dp)
346{
347 u32 reg;
348
349 /* Disable AUX channel module */
350 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
351 reg |= AUX_FUNC_EN_N;
352 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
353}
354
355void exynos_dp_init_aux(struct exynos_dp_device *dp)
356{
357 u32 reg;
358
359 /* Clear inerrupts related to AUX channel */
360 reg = RPLY_RECEIV | AUX_ERR;
361 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
362
363 exynos_dp_reset_aux(dp);
364
365 /* Disable AUX transaction H/W retry */
366 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
367 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
368 writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL) ;
369
370 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
371 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
372 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
373
374 /* Enable AUX channel module */
375 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
376 reg &= ~AUX_FUNC_EN_N;
377 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
378}
379
380int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
381{
382 u32 reg;
383
384 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
385 if (reg & HPD_STATUS)
386 return 0;
387
388 return -EINVAL;
389}
390
391void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
392{
393 u32 reg;
394
395 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
396 reg &= ~SW_FUNC_EN_N;
397 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
398}
399
400int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
401{
402 int reg;
403 int retval = 0;
bada5537 404 int timeout_loop = 0;
e9474be4
JH		 405
406 /* Enable AUX CH operation */
407 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
408 reg |= AUX_EN;
409 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
410
411 /* Is AUX CH command reply received? */
412 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
bada5537
JH		 413 while (!(reg & RPLY_RECEIV)) {
414 timeout_loop++;
415 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
416 dev_err(dp->dev, "AUX CH command reply failed!\n");
417 return -ETIMEDOUT;
418 }
e9474be4 419 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
bada5537
JH		 420 usleep_range(10, 11);
421 }
e9474be4
JH		 422
423 /* Clear interrupt source for AUX CH command reply */
424 writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
425
426 /* Clear interrupt source for AUX CH access error */
427 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
428 if (reg & AUX_ERR) {
429 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
430 return -EREMOTEIO;
431 }
432
433 /* Check AUX CH error access status */
434 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
435 if ((reg & AUX_STATUS_MASK) != 0) {
436 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
437 reg & AUX_STATUS_MASK);
438 return -EREMOTEIO;
439 }
440
441 return retval;
442}
443
444int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
445 unsigned int reg_addr,
446 unsigned char data)
447{
448 u32 reg;
449 int i;
450 int retval;
451
452 for (i = 0; i < 3; i++) {
453 /* Clear AUX CH data buffer */
454 reg = BUF_CLR;
455 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
456
457 /* Select DPCD device address */
458 reg = AUX_ADDR_7_0(reg_addr);
459 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
460 reg = AUX_ADDR_15_8(reg_addr);
461 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
462 reg = AUX_ADDR_19_16(reg_addr);
463 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
464
465 /* Write data buffer */
466 reg = (unsigned int)data;
467 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
468
469 /*
470 * Set DisplayPort transaction and write 1 byte
471 * If bit 3 is 1, DisplayPort transaction.
472 * If Bit 3 is 0, I2C transaction.
473 */
474 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
475 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
476
477 /* Start AUX transaction */
478 retval = exynos_dp_start_aux_transaction(dp);
479 if (retval == 0)
480 break;
481 else
8fefbb75
SP		 482 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
483 __func__);
e9474be4
JH		 484 }
485
486 return retval;
487}
488
489int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
490 unsigned int reg_addr,
491 unsigned char *data)
492{
493 u32 reg;
494 int i;
495 int retval;
496
497 for (i = 0; i < 10; i++) {
498 /* Clear AUX CH data buffer */
499 reg = BUF_CLR;
500 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
501
502 /* Select DPCD device address */
503 reg = AUX_ADDR_7_0(reg_addr);
504 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
505 reg = AUX_ADDR_15_8(reg_addr);
506 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
507 reg = AUX_ADDR_19_16(reg_addr);
508 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
509
510 /*
511 * Set DisplayPort transaction and read 1 byte
512 * If bit 3 is 1, DisplayPort transaction.
513 * If Bit 3 is 0, I2C transaction.
514 */
515 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
516 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
517
518 /* Start AUX transaction */
519 retval = exynos_dp_start_aux_transaction(dp);
520 if (retval == 0)
521 break;
522 else
8fefbb75
SP		 523 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
524 __func__);
e9474be4
JH		 525 }
526
527 /* Read data buffer */
528 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
529 *data = (unsigned char)(reg & 0xff);
530
531 return retval;
532}
533
534int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
535 unsigned int reg_addr,
536 unsigned int count,
537 unsigned char data[])
538{
539 u32 reg;
540 unsigned int start_offset;
541 unsigned int cur_data_count;
542 unsigned int cur_data_idx;
543 int i;
544 int retval = 0;
545
546 /* Clear AUX CH data buffer */
547 reg = BUF_CLR;
548 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
549
550 start_offset = 0;
551 while (start_offset < count) {
552 /* Buffer size of AUX CH is 16 * 4bytes */
553 if ((count - start_offset) > 16)
554 cur_data_count = 16;
555 else
556 cur_data_count = count - start_offset;
557
558 for (i = 0; i < 10; i++) {
559 /* Select DPCD device address */
560 reg = AUX_ADDR_7_0(reg_addr + start_offset);
561 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
562 reg = AUX_ADDR_15_8(reg_addr + start_offset);
563 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
564 reg = AUX_ADDR_19_16(reg_addr + start_offset);
565 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
566
567 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
568 cur_data_idx++) {
569 reg = data[start_offset + cur_data_idx];
570 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
571 + 4 * cur_data_idx);
572 }
573
574 /*
575 * Set DisplayPort transaction and write
576 * If bit 3 is 1, DisplayPort transaction.
577 * If Bit 3 is 0, I2C transaction.
578 */
579 reg = AUX_LENGTH(cur_data_count) |
580 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
581 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
582
583 /* Start AUX transaction */
584 retval = exynos_dp_start_aux_transaction(dp);
585 if (retval == 0)
586 break;
587 else
8fefbb75
SP		 588 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
589 __func__);
e9474be4
JH		 590 }
591
592 start_offset += cur_data_count;
593 }
594
595 return retval;
596}
597
598int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
599 unsigned int reg_addr,
600 unsigned int count,
601 unsigned char data[])
602{
603 u32 reg;
604 unsigned int start_offset;
605 unsigned int cur_data_count;
606 unsigned int cur_data_idx;
607 int i;
608 int retval = 0;
609
610 /* Clear AUX CH data buffer */
611 reg = BUF_CLR;
612 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
613
614 start_offset = 0;
615 while (start_offset < count) {
616 /* Buffer size of AUX CH is 16 * 4bytes */
617 if ((count - start_offset) > 16)
618 cur_data_count = 16;
619 else
620 cur_data_count = count - start_offset;
621
622 /* AUX CH Request Transaction process */
623 for (i = 0; i < 10; i++) {
624 /* Select DPCD device address */
625 reg = AUX_ADDR_7_0(reg_addr + start_offset);
626 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
627 reg = AUX_ADDR_15_8(reg_addr + start_offset);
628 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
629 reg = AUX_ADDR_19_16(reg_addr + start_offset);
630 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
631
632 /*
633 * Set DisplayPort transaction and read
634 * If bit 3 is 1, DisplayPort transaction.
635 * If Bit 3 is 0, I2C transaction.
636 */
637 reg = AUX_LENGTH(cur_data_count) |
638 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
639 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
640
641 /* Start AUX transaction */
642 retval = exynos_dp_start_aux_transaction(dp);
643 if (retval == 0)
644 break;
645 else
8fefbb75
SP		 646 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
647 __func__);
e9474be4
JH		 648 }
649
650 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
651 cur_data_idx++) {
652 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
653 + 4 * cur_data_idx);
654 data[start_offset + cur_data_idx] =
655 (unsigned char)reg;
656 }
657
658 start_offset += cur_data_count;
659 }
660
661 return retval;
662}
663
664int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
665 unsigned int device_addr,
666 unsigned int reg_addr)
667{
668 u32 reg;
669 int retval;
670
671 /* Set EDID device address */
672 reg = device_addr;
673 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
674 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
675 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
676
677 /* Set offset from base address of EDID device */
678 writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
679
680 /*
681 * Set I2C transaction and write address
682 * If bit 3 is 1, DisplayPort transaction.
683 * If Bit 3 is 0, I2C transaction.
684 */
685 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
686 AUX_TX_COMM_WRITE;
687 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
688
689 /* Start AUX transaction */
690 retval = exynos_dp_start_aux_transaction(dp);
691 if (retval != 0)
8fefbb75 692 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
e9474be4
JH		 693
694 return retval;
695}
696
697int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
698 unsigned int device_addr,
699 unsigned int reg_addr,
700 unsigned int *data)
701{
702 u32 reg;
703 int i;
704 int retval;
705
706 for (i = 0; i < 10; i++) {
707 /* Clear AUX CH data buffer */
708 reg = BUF_CLR;
709 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
710
711 /* Select EDID device */
712 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
713 if (retval != 0) {
714 dev_err(dp->dev, "Select EDID device fail!\n");
715 continue;
716 }
717
718 /*
719 * Set I2C transaction and read data
720 * If bit 3 is 1, DisplayPort transaction.
721 * If Bit 3 is 0, I2C transaction.
722 */
723 reg = AUX_TX_COMM_I2C_TRANSACTION |
724 AUX_TX_COMM_READ;
725 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
726
727 /* Start AUX transaction */
728 retval = exynos_dp_start_aux_transaction(dp);
729 if (retval == 0)
730 break;
731 else
8fefbb75
SP		 732 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
733 __func__);
e9474be4
JH		 734 }
735
736 /* Read data */
737 if (retval == 0)
738 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
739
740 return retval;
741}
742
743int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
744 unsigned int device_addr,
745 unsigned int reg_addr,
746 unsigned int count,
747 unsigned char edid[])
748{
749 u32 reg;
750 unsigned int i, j;
751 unsigned int cur_data_idx;
752 unsigned int defer = 0;
753 int retval = 0;
754
755 for (i = 0; i < count; i += 16) {
756 for (j = 0; j < 100; j++) {
757 /* Clear AUX CH data buffer */
758 reg = BUF_CLR;
759 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
760
761 /* Set normal AUX CH command */
762 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
763 reg &= ~ADDR_ONLY;
764 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
765
766 /*
767 * If Rx sends defer, Tx sends only reads
ff0c2642 768 * request without sending address
e9474be4
JH		 769 */
770 if (!defer)
771 retval = exynos_dp_select_i2c_device(dp,
772 device_addr, reg_addr + i);
773 else
774 defer = 0;
775
776 if (retval == 0) {
777 /*
778 * Set I2C transaction and write data
779 * If bit 3 is 1, DisplayPort transaction.
780 * If Bit 3 is 0, I2C transaction.
781 */
782 reg = AUX_LENGTH(16) |
783 AUX_TX_COMM_I2C_TRANSACTION |
784 AUX_TX_COMM_READ;
785 writel(reg, dp->reg_base +
786 EXYNOS_DP_AUX_CH_CTL_1);
787
788 /* Start AUX transaction */
789 retval = exynos_dp_start_aux_transaction(dp);
790 if (retval == 0)
791 break;
792 else
8fefbb75
SP		 793 dev_dbg(dp->dev,
794 "%s: Aux Transaction fail!\n",
795 __func__);
e9474be4
JH		 796 }
797 /* Check if Rx sends defer */
798 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
799 if (reg == AUX_RX_COMM_AUX_DEFER ||
800 reg == AUX_RX_COMM_I2C_DEFER) {
801 dev_err(dp->dev, "Defer: %d\n\n", reg);
802 defer = 1;
803 }
804 }
805
806 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
807 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
808 + 4 * cur_data_idx);
809 edid[i + cur_data_idx] = (unsigned char)reg;
810 }
811 }
812
813 return retval;
814}
815
816void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
817{
818 u32 reg;
819
820 reg = bwtype;
821 if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
822 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
823}
824
825void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
826{
827 u32 reg;
828
829 reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
830 *bwtype = reg;
831}
832
833void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
834{
835 u32 reg;
836
837 reg = count;
838 writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
839}
840
841void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
842{
843 u32 reg;
844
845 reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
846 *count = reg;
847}
848
849void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
850{
851 u32 reg;
852
853 if (enable) {
854 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
855 reg |= ENHANCED;
856 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
857 } else {
858 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
859 reg &= ~ENHANCED;
860 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
861 }
862}
863
864void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
865 enum pattern_set pattern)
866{
867 u32 reg;
868
869 switch (pattern) {
870 case PRBS7:
871 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
872 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
873 break;
874 case D10_2:
875 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
876 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
877 break;
878 case TRAINING_PTN1:
879 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
880 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
881 break;
882 case TRAINING_PTN2:
883 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
884 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
885 break;
886 case DP_NONE:
887 reg = SCRAMBLING_ENABLE |
888 LINK_QUAL_PATTERN_SET_DISABLE |
889 SW_TRAINING_PATTERN_SET_NORMAL;
890 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
891 break;
892 default:
893 break;
894 }
895}
896
897void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
898{
899 u32 reg;
900
901 reg = level << PRE_EMPHASIS_SET_SHIFT;
902 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
903}
904
905void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
906{
907 u32 reg;
908
909 reg = level << PRE_EMPHASIS_SET_SHIFT;
910 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
911}
912
913void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
914{
915 u32 reg;
916
917 reg = level << PRE_EMPHASIS_SET_SHIFT;
918 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
919}
920
921void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
922{
923 u32 reg;
924
925 reg = level << PRE_EMPHASIS_SET_SHIFT;
926 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
927}
928
929void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
930 u32 training_lane)
931{
932 u32 reg;
933
934 reg = training_lane;
935 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
936}
937
938void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
939 u32 training_lane)
940{
941 u32 reg;
942
943 reg = training_lane;
944 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
945}
946
947void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
948 u32 training_lane)
949{
950 u32 reg;
951
952 reg = training_lane;
953 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
954}
955
956void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
957 u32 training_lane)
958{
959 u32 reg;
960
961 reg = training_lane;
962 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
963}
964
965u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
966{
967 u32 reg;
968
969 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
970 return reg;
971}
972
973u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
974{
975 u32 reg;
976
977 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
978 return reg;
979}
980
981u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
982{
983 u32 reg;
984
985 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
986 return reg;
987}
988
989u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
990{
991 u32 reg;
992
993 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
994 return reg;
995}
996
997void exynos_dp_reset_macro(struct exynos_dp_device *dp)
998{
999 u32 reg;
1000
1001 reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
1002 reg |= MACRO_RST;
1003 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
1004
1005 /* 10 us is the minimum reset time. */
a2c81bc1 1006 usleep_range(10, 20);
e9474be4
JH		 1007
1008 reg &= ~MACRO_RST;
1009 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
1010}
1011
1012int exynos_dp_init_video(struct exynos_dp_device *dp)
1013{
1014 u32 reg;
1015
1016 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1017 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
1018
1019 reg = 0x0;
1020 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1021
1022 reg = CHA_CRI(4) | CHA_CTRL;
1023 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1024
1025 reg = 0x0;
1026 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1027
1028 reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1029 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
1030
1031 return 0;
1032}
1033
1034void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
1035 u32 color_depth,
1036 u32 color_space,
1037 u32 dynamic_range,
1038 u32 ycbcr_coeff)
1039{
1040 u32 reg;
1041
1042 /* Configure the input color depth, color space, dynamic range */
1043 reg = (dynamic_range << IN_D_RANGE_SHIFT) |
1044 (color_depth << IN_BPC_SHIFT) |
1045 (color_space << IN_COLOR_F_SHIFT);
1046 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
1047
1048 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1049 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1050 reg &= ~IN_YC_COEFFI_MASK;
1051 if (ycbcr_coeff)
1052 reg |= IN_YC_COEFFI_ITU709;
1053 else
1054 reg |= IN_YC_COEFFI_ITU601;
1055 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1056}
1057
1058int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
1059{
1060 u32 reg;
1061
1062 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1063 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1064
1065 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1066
1067 if (!(reg & DET_STA)) {
1068 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1069 return -EINVAL;
1070 }
1071
1072 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1073 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1074
1075 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1076 dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1077
1078 if (reg & CHA_STA) {
1079 dev_dbg(dp->dev, "Input stream clk is changing\n");
1080 return -EINVAL;
1081 }
1082
1083 return 0;
1084}
1085
1086void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
1087 enum clock_recovery_m_value_type type,
1088 u32 m_value,
1089 u32 n_value)
1090{
1091 u32 reg;
1092
1093 if (type == REGISTER_M) {
1094 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1095 reg |= FIX_M_VID;
1096 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1097 reg = m_value & 0xff;
1098 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
1099 reg = (m_value >> 8) & 0xff;
1100 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
1101 reg = (m_value >> 16) & 0xff;
1102 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
1103
1104 reg = n_value & 0xff;
1105 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
1106 reg = (n_value >> 8) & 0xff;
1107 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
1108 reg = (n_value >> 16) & 0xff;
1109 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
1110 } else {
1111 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1112 reg &= ~FIX_M_VID;
1113 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1114
1115 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
1116 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
1117 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
1118 }
1119}
1120
1121void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
1122{
1123 u32 reg;
1124
1125 if (type == VIDEO_TIMING_FROM_CAPTURE) {
1126 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1127 reg &= ~FORMAT_SEL;
1128 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1129 } else {
1130 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1131 reg |= FORMAT_SEL;
1132 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1133 }
1134}
1135
1136void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
1137{
1138 u32 reg;
1139
1140 if (enable) {
1141 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1142 reg &= ~VIDEO_MODE_MASK;
1143 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1144 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1145 } else {
1146 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1147 reg &= ~VIDEO_MODE_MASK;
1148 reg |= VIDEO_MODE_SLAVE_MODE;
1149 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1150 }
1151}
1152
1153void exynos_dp_start_video(struct exynos_dp_device *dp)
1154{
1155 u32 reg;
1156
1157 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1158 reg |= VIDEO_EN;
1159 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1160}
1161
1162int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
1163{
1164 u32 reg;
1165
1166 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1167 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1168
1169 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1170 if (!(reg & STRM_VALID)) {
1171 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1172 return -EINVAL;
1173 }
1174
1175 return 0;
1176}
1177
1178void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
1179 struct video_info *video_info)
1180{
1181 u32 reg;
1182
1183 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1184 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1185 reg |= MASTER_VID_FUNC_EN_N;
1186 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1187
1188 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1189 reg &= ~INTERACE_SCAN_CFG;
1190 reg |= (video_info->interlaced << 2);
1191 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1192
1193 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1194 reg &= ~VSYNC_POLARITY_CFG;
1195 reg |= (video_info->v_sync_polarity << 1);
1196 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1197
1198 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1199 reg &= ~HSYNC_POLARITY_CFG;
1200 reg |= (video_info->h_sync_polarity << 0);
1201 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1202
1203 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1204 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1205}
1206
1207void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
1208{
1209 u32 reg;
1210
1211 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1212 reg &= ~SCRAMBLING_DISABLE;
1213 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1214}
1215
1216void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
1217{
1218 u32 reg;
1219
1220 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1221 reg |= SCRAMBLING_DISABLE;
1222 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1223}
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